// Auto-generated.
// The changes will be LOST.

#![allow(clippy::collapsible_else_if)]
#![allow(clippy::upper_case_acronyms)]
#![allow(clippy::enum_variant_names)]
#![allow(non_snake_case, non_camel_case_types)]
#![allow(dead_code)]
use bitfield_struct::bitfield;
use disarm64_defn::defn::Insn;
use disarm64_defn::defn::InsnOpcode;
use disarm64_defn::defn::InsnOperand;
use disarm64_defn::BitfieldSpec;
use disarm64_defn::InsnBitField;
use disarm64_defn::InsnClass;
use disarm64_defn::InsnFeatureSet;
use disarm64_defn::InsnFlags;
use disarm64_defn::InsnOperandClass;
use disarm64_defn::InsnOperandKind;
use disarm64_defn::InsnOperandQualifier;
#[doc = r" Leaf nodes in the decision tree"]
struct Leaf {
    insn: &'static Insn,
    factory: fn(u32) -> Opcode,
}
#[doc = r" The decision tree node"]
enum Decode {
    #[doc = r" Branch in the decision tree"]
    Branch {
        mask: u32,
        next: [Option<u16>; 2],
    },
    Leaf(&'static [Leaf]),
}
#[doc = r" The decode table"]
type DecodeTable = &'static [Decode];
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ABS_Rd_Rn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ABS_SVE_Zd_SVE_Pg3_SVE_Zn {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ABS_Vd_Vn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ABS_Sd_Sn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ADC_Rd_Rn_Rm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ADCLB_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ADCLT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ADCS_Rd_Rn_Rm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ADD_SME_ZA_array_off3_0_SVE_ZnxN_SME_Zm {
    #[bits(3)]
    pub imm3_0: u32,
    #[bits(2)]
    pub _op_3: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ADD_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_S_SME_Zm_S_S {
    #[bits(3)]
    pub imm3_0: u32,
    #[bits(2)]
    pub _op_3: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ADD_SME_ZA_array_off3_0_SME_Znx2_SME_Zmx2 {
    #[bits(3)]
    pub imm3_0: u32,
    #[bits(3)]
    pub _op_3: u32,
    #[bits(4)]
    pub sme_zn2: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(2)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm2: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ADD_SME_ZA_array_off3_0_SME_Znx4_SME_Zmx4 {
    #[bits(3)]
    pub imm3_0: u32,
    #[bits(4)]
    pub _op_3: u32,
    #[bits(3)]
    pub sme_zn4: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(3)]
    pub _op_15: u32,
    #[bits(3)]
    pub sme_zm4: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ADD_SME_ZA_array_off3_0_SME_Znx2 {
    #[bits(3)]
    pub imm3_0: u32,
    #[bits(3)]
    pub _op_3: u32,
    #[bits(4)]
    pub sme_zn2: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(17)]
    pub _op_15: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ADD_SME_ZA_array_off3_0_SME_Znx4 {
    #[bits(3)]
    pub imm3_0: u32,
    #[bits(4)]
    pub _op_3: u32,
    #[bits(3)]
    pub sme_zn4: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(17)]
    pub _op_15: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ADD_SME_Zdnx2_SME_Zdnx2_SME_Zm {
    #[bits(1)]
    pub _op_0: u32,
    #[bits(4)]
    pub sme_zdn2: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ADD_SME_Zdnx4_SME_Zdnx4_SME_Zm {
    #[bits(2)]
    pub _op_0: u32,
    #[bits(3)]
    pub sme_zdn4: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ADD_Rd_SP_Rn_SP_AIMM {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(12)]
    pub imm12: u32,
    #[bits(2)]
    pub shift: u32,
    #[bits(8)]
    pub _op_24: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ADD_Rd_Rn_Rm_SFT {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ADD_Rd_SP_Rn_SP_Rm_EXT {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zm_5: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ADD_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ADD_SVE_Zd_SVE_Zd_SVE_AIMM {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(9)]
    pub sve_imm9: u32,
    #[bits(18)]
    pub _op_14: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ADD_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ADD_Sd_Sn_Sm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ADDG_Rd_SP_Rn_SP_UIMM10_UIMM4_ADDG {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(4)]
    pub imm4_10: u32,
    #[bits(2)]
    pub _op_14: u32,
    #[bits(6)]
    pub immr: u32,
    #[bits(10)]
    pub _op_22: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ADDHA_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn {
    #[bits(2)]
    pub sme_zada_2b: u32,
    #[bits(3)]
    pub _op_2: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub sme_pm: u32,
    #[bits(16)]
    pub _op_16: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ADDHA_SME_ZAda_3b_SVE_Pg3_SME_Pm_SVE_Zn {
    #[bits(3)]
    pub sme_zada_3b: u32,
    #[bits(2)]
    pub _op_3: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub sme_pm: u32,
    #[bits(16)]
    pub _op_16: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ADDHN_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ADDHN2_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ADDHNB_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ADDHNT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ADDP_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ADDP_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ADDP_Sd_Vn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ADDPL_Rd_SP_SVE_Rn_SP_SVE_SIMM6 {
    #[bits(5)]
    pub rd: u32,
    #[bits(6)]
    pub sve_imms: u32,
    #[bits(5)]
    pub _op_11: u32,
    #[bits(5)]
    pub sve_rn: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ADDQV_Vd_SVE_Pg3_SVE_Zn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ADDS_Rd_Rn_SP_AIMM {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(12)]
    pub imm12: u32,
    #[bits(2)]
    pub shift: u32,
    #[bits(8)]
    pub _op_24: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ADDS_Rd_Rn_Rm_SFT {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ADDS_Rd_Rn_SP_Rm_EXT {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ADDSPL_Rd_SP_SVE_Rn_SP_SVE_SIMM6 {
    #[bits(5)]
    pub rd: u32,
    #[bits(6)]
    pub sve_imms: u32,
    #[bits(5)]
    pub _op_11: u32,
    #[bits(5)]
    pub sve_rn: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ADDSVL_Rd_SP_SVE_Rn_SP_SVE_SIMM6 {
    #[bits(5)]
    pub rd: u32,
    #[bits(6)]
    pub sve_imms: u32,
    #[bits(5)]
    pub _op_11: u32,
    #[bits(5)]
    pub sve_rn: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ADDV_Fd_Vn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ADDVA_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn {
    #[bits(2)]
    pub sme_zada_2b: u32,
    #[bits(3)]
    pub _op_2: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub sme_pm: u32,
    #[bits(16)]
    pub _op_16: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ADDVA_SME_ZAda_3b_SVE_Pg3_SME_Pm_SVE_Zn {
    #[bits(3)]
    pub sme_zada_3b: u32,
    #[bits(2)]
    pub _op_3: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub sme_pm: u32,
    #[bits(16)]
    pub _op_16: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ADDVL_Rd_SP_SVE_Rn_SP_SVE_SIMM6 {
    #[bits(5)]
    pub rd: u32,
    #[bits(6)]
    pub sve_imms: u32,
    #[bits(5)]
    pub _op_11: u32,
    #[bits(5)]
    pub sve_rn: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ADR_Rd_ADDR_PCREL21 {
    #[bits(5)]
    pub rd: u32,
    #[bits(19)]
    pub immhi: u32,
    #[bits(5)]
    pub _op_24: u32,
    #[bits(2)]
    pub immlo: u32,
    #[bits(1)]
    pub _op_31: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ADR_SVE_Zd_SVE_ADDR_ZZ_SXTW {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ADR_SVE_Zd_SVE_ADDR_ZZ_UXTW {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ADR_SVE_Zd_SVE_ADDR_ZZ_LSL {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ADRP_Rd_ADDR_ADRP {
    #[bits(5)]
    pub rd: u32,
    #[bits(19)]
    pub immhi: u32,
    #[bits(5)]
    pub _op_24: u32,
    #[bits(2)]
    pub immlo: u32,
    #[bits(1)]
    pub _op_31: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct AESD_SVE_Zd_SVE_Zd_SVE_Zn {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct AESD_Vd_Vn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct AESE_SVE_Zd_SVE_Zd_SVE_Zn {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct AESE_Vd_Vn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct AESIMC_SVE_Zd_SVE_Zd {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(27)]
    pub _op_5: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct AESIMC_Vd_Vn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct AESMC_SVE_Zd_SVE_Zd {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(27)]
    pub _op_5: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct AESMC_Vd_Vn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct AND_Rd_SP_Rn_LIMM {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub imms: u32,
    #[bits(6)]
    pub immr: u32,
    #[bits(1)]
    pub n: u32,
    #[bits(9)]
    pub _op_23: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct AND_Rd_Rn_Rm_SFT {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct AND_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zm_5: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct AND_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct AND_SVE_Zd_SVE_Zd_SVE_LIMM {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(6)]
    pub sve_imms: u32,
    #[bits(6)]
    pub sve_immr: u32,
    #[bits(1)]
    pub sve_n: u32,
    #[bits(14)]
    pub _op_18: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct AND_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm {
    #[bits(4)]
    pub sve_pd: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(4)]
    pub sve_pn: u32,
    #[bits(1)]
    pub _op_9: u32,
    #[bits(4)]
    pub sve_pg4_10: u32,
    #[bits(2)]
    pub _op_14: u32,
    #[bits(4)]
    pub sve_pm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct AND_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ANDQV_Vd_SVE_Pg3_SVE_Zn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ANDS_Rd_Rn_LIMM {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub imms: u32,
    #[bits(6)]
    pub immr: u32,
    #[bits(1)]
    pub n: u32,
    #[bits(9)]
    pub _op_23: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ANDS_Rd_Rn_Rm_SFT {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ANDS_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm {
    #[bits(4)]
    pub sve_pd: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(4)]
    pub sve_pn: u32,
    #[bits(1)]
    pub _op_9: u32,
    #[bits(4)]
    pub sve_pg4_10: u32,
    #[bits(2)]
    pub _op_14: u32,
    #[bits(4)]
    pub sve_pm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ANDV_SVE_Vd_SVE_Pg3_SVE_Zn {
    #[bits(5)]
    pub sve_vd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ASR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_SHRIMM_PRED {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_imm5: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(9)]
    pub _op_13: u32,
    #[bits(2)]
    pub sve_tszh: u32,
    #[bits(8)]
    pub _op_24: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ASR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zm_5: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ASR_SVE_Zd_S_B_SVE_Pg3_P_M_SVE_Zd_S_B_SVE_Zm_5_S_D {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zm_5: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ASR_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ASR_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub imm5: u32,
    #[bits(1)]
    pub _op_21: u32,
    #[bits(2)]
    pub sve_tszh: u32,
    #[bits(8)]
    pub _op_24: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ASRD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_SHRIMM_PRED {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_imm5: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(9)]
    pub _op_13: u32,
    #[bits(2)]
    pub sve_tszh: u32,
    #[bits(8)]
    pub _op_24: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ASRR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zm_5: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ASRV_Rd_Rn_Rm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct AUTDA_Rd_Rn_SP {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct AUTDB_Rd_Rn_SP {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct AUTDZA_Rd {
    #[bits(5)]
    pub rd: u32,
    #[bits(27)]
    pub _op_5: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct AUTDZB_Rd {
    #[bits(5)]
    pub rd: u32,
    #[bits(27)]
    pub _op_5: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct AUTIA_Rd_Rn_SP {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct AUTIB_Rd_Rn_SP {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct AUTIZA_Rd {
    #[bits(5)]
    pub rd: u32,
    #[bits(27)]
    pub _op_5: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct AUTIZB_Rd {
    #[bits(5)]
    pub rd: u32,
    #[bits(27)]
    pub _op_5: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct AXFLAG {
    #[bits(32)]
    pub _op_0: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct B_ADDR_PCREL26 {
    #[bits(26)]
    pub imm26: u32,
    #[bits(6)]
    pub _op_26: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct B__ADDR_PCREL19 {
    #[bits(4)]
    pub cond: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(19)]
    pub imm19: u32,
    #[bits(8)]
    pub _op_24: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct BC__ADDR_PCREL19 {
    #[bits(4)]
    pub cond: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(19)]
    pub imm19: u32,
    #[bits(8)]
    pub _op_24: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct BCAX_SVE_Zd_SVE_Zd_SVE_Zm_16_SVE_Zn {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct BCAX_Vd_Vn_Vm_Va {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(5)]
    pub ra: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct BDEP_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct BEXT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct BFADD_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct BFADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zm_5: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct BFCLAMP_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct BFCVT_SVE_Zd_SME_Znx2 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(1)]
    pub _op_5: u32,
    #[bits(4)]
    pub sme_zn2: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct BFCVT_SVE_Zd_SVE_Pg3_SVE_Zn {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct BFCVT_Fd_Fn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct BFCVTN_SVE_Zd_SME_Znx2 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(1)]
    pub _op_5: u32,
    #[bits(4)]
    pub sme_zn2: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct BFCVTN_Vd_Vn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct BFCVTN2_Vd_Vn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct BFCVTNT_SVE_Zd_SVE_Pg3_SVE_Zn {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct BFDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2 {
    #[bits(3)]
    pub imm3_0: u32,
    #[bits(3)]
    pub _op_3: u32,
    #[bits(4)]
    pub sme_zn2: u32,
    #[bits(2)]
    pub imm2_10: u32,
    #[bits(1)]
    pub _op_12: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct BFDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2 {
    #[bits(3)]
    pub imm3_0: u32,
    #[bits(4)]
    pub _op_3: u32,
    #[bits(3)]
    pub sme_zn4: u32,
    #[bits(2)]
    pub imm2_10: u32,
    #[bits(1)]
    pub _op_12: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct BFDOT_SME_ZA_array_off3_0_SVE_ZnxN_SME_Zm {
    #[bits(3)]
    pub imm3_0: u32,
    #[bits(2)]
    pub _op_3: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct BFDOT_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_H_SME_Zm_S_H {
    #[bits(3)]
    pub imm3_0: u32,
    #[bits(2)]
    pub _op_3: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct BFDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zmx2 {
    #[bits(3)]
    pub imm3_0: u32,
    #[bits(3)]
    pub _op_3: u32,
    #[bits(4)]
    pub sme_zn2: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(2)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm2: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct BFDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zmx4 {
    #[bits(3)]
    pub imm3_0: u32,
    #[bits(4)]
    pub _op_3: u32,
    #[bits(3)]
    pub sme_zn4: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(3)]
    pub _op_15: u32,
    #[bits(3)]
    pub sme_zm4: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct BFDOT_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct BFDOT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct BFDOT_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct BFDOT_Vd_Vn_Em {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct BFM_Rd_Rn_IMMR_IMMS {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub imm6_10: u32,
    #[bits(6)]
    pub immr: u32,
    #[bits(10)]
    pub _op_22: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct BFMAX_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zm_5: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct BFMAXNM_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zm_5: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct BFMIN_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zm_5: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct BFMINNM_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zm_5: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct BFMLA_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(1)]
    pub _op_10: u32,
    #[bits(1)]
    pub sve_i3l: u32,
    #[bits(4)]
    pub _op_12: u32,
    #[bits(3)]
    pub sve_imm3: u32,
    #[bits(2)]
    pub sve_i3h2: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct BFMLA_SVE_Zd_SVE_Pg3_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct BFMLAL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm_INDEX3_10 {
    #[bits(3)]
    pub imm3_0: u32,
    #[bits(2)]
    pub _op_3: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(2)]
    pub imm2_10: u32,
    #[bits(1)]
    pub _op_12: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub imm1_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct BFMLAL_SME_ZA_array_off2x2_SME_Znx2_SME_Zm_INDEX3_2 {
    #[bits(2)]
    pub imm2_0: u32,
    #[bits(1)]
    pub imm1_2: u32,
    #[bits(3)]
    pub _op_3: u32,
    #[bits(4)]
    pub sme_zn2: u32,
    #[bits(2)]
    pub imm2_10: u32,
    #[bits(1)]
    pub _op_12: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct BFMLAL_SME_ZA_array_off2x2_SME_Znx4_SME_Zm_INDEX3_2 {
    #[bits(2)]
    pub imm2_0: u32,
    #[bits(1)]
    pub imm1_2: u32,
    #[bits(4)]
    pub _op_3: u32,
    #[bits(3)]
    pub sme_zn4: u32,
    #[bits(2)]
    pub imm2_10: u32,
    #[bits(1)]
    pub _op_12: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct BFMLAL_SME_ZA_array_off2x2_SVE_ZnxN_SME_Zm {
    #[bits(2)]
    pub imm2_0: u32,
    #[bits(3)]
    pub _op_2: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct BFMLAL_SME_ZA_array_off2x2_S_S_SVE_ZnxN_S_H_SME_Zm_S_H {
    #[bits(2)]
    pub imm2_0: u32,
    #[bits(3)]
    pub _op_2: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct BFMLAL_SME_ZA_array_off2x2_SME_Znx2_SME_Zmx2 {
    #[bits(2)]
    pub imm2_0: u32,
    #[bits(4)]
    pub _op_2: u32,
    #[bits(4)]
    pub sme_zn2: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(2)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm2: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct BFMLAL_SME_ZA_array_off2x2_SME_Znx4_SME_Zmx4 {
    #[bits(2)]
    pub imm2_0: u32,
    #[bits(5)]
    pub _op_2: u32,
    #[bits(3)]
    pub sme_zn4: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(3)]
    pub _op_15: u32,
    #[bits(3)]
    pub sme_zm4: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct BFMLAL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm {
    #[bits(3)]
    pub imm3_0: u32,
    #[bits(2)]
    pub _op_3: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct BFMLALB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(1)]
    pub _op_10: u32,
    #[bits(1)]
    pub sve_i3l: u32,
    #[bits(4)]
    pub _op_12: u32,
    #[bits(3)]
    pub sve_imm3: u32,
    #[bits(2)]
    pub sve_i3h2: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct BFMLALB_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct BFMLALB_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct BFMLALB_Vd_Vn_Em16 {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct BFMLALT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(1)]
    pub _op_10: u32,
    #[bits(1)]
    pub sve_i3l: u32,
    #[bits(4)]
    pub _op_12: u32,
    #[bits(3)]
    pub sve_imm3: u32,
    #[bits(2)]
    pub sve_i3h2: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct BFMLALT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct BFMLALT_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct BFMLALT_Vd_Vn_Em16 {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct BFMLS_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(1)]
    pub _op_10: u32,
    #[bits(1)]
    pub sve_i3l: u32,
    #[bits(4)]
    pub _op_12: u32,
    #[bits(3)]
    pub sve_imm3: u32,
    #[bits(2)]
    pub sve_i3h2: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct BFMLS_SVE_Zd_SVE_Pg3_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct BFMLSL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm_INDEX3_10 {
    #[bits(3)]
    pub imm3_0: u32,
    #[bits(2)]
    pub _op_3: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(2)]
    pub imm2_10: u32,
    #[bits(1)]
    pub _op_12: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub imm1_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct BFMLSL_SME_ZA_array_off2x2_SME_Znx2_SME_Zm_INDEX3_2 {
    #[bits(2)]
    pub imm2_0: u32,
    #[bits(1)]
    pub imm1_2: u32,
    #[bits(3)]
    pub _op_3: u32,
    #[bits(4)]
    pub sme_zn2: u32,
    #[bits(2)]
    pub imm2_10: u32,
    #[bits(1)]
    pub _op_12: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct BFMLSL_SME_ZA_array_off2x2_SME_Znx4_SME_Zm_INDEX3_2 {
    #[bits(2)]
    pub imm2_0: u32,
    #[bits(1)]
    pub imm1_2: u32,
    #[bits(4)]
    pub _op_3: u32,
    #[bits(3)]
    pub sme_zn4: u32,
    #[bits(2)]
    pub imm2_10: u32,
    #[bits(1)]
    pub _op_12: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct BFMLSL_SME_ZA_array_off2x2_SVE_ZnxN_SME_Zm {
    #[bits(2)]
    pub imm2_0: u32,
    #[bits(3)]
    pub _op_2: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct BFMLSL_SME_ZA_array_off2x2_S_S_SVE_ZnxN_S_H_SME_Zm_S_H {
    #[bits(2)]
    pub imm2_0: u32,
    #[bits(3)]
    pub _op_2: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct BFMLSL_SME_ZA_array_off2x2_SME_Znx2_SME_Zmx2 {
    #[bits(2)]
    pub imm2_0: u32,
    #[bits(4)]
    pub _op_2: u32,
    #[bits(4)]
    pub sme_zn2: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(2)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm2: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct BFMLSL_SME_ZA_array_off2x2_SME_Znx4_SME_Zmx4 {
    #[bits(2)]
    pub imm2_0: u32,
    #[bits(5)]
    pub _op_2: u32,
    #[bits(3)]
    pub sme_zn4: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(3)]
    pub _op_15: u32,
    #[bits(3)]
    pub sme_zm4: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct BFMLSL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm {
    #[bits(3)]
    pub imm3_0: u32,
    #[bits(2)]
    pub _op_3: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct BFMLSLB_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct BFMLSLB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(1)]
    pub _op_10: u32,
    #[bits(1)]
    pub sve_i3l: u32,
    #[bits(4)]
    pub _op_12: u32,
    #[bits(3)]
    pub sve_imm3: u32,
    #[bits(2)]
    pub sve_i3h2: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct BFMLSLT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct BFMLSLT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(1)]
    pub _op_10: u32,
    #[bits(1)]
    pub sve_i3l: u32,
    #[bits(4)]
    pub _op_12: u32,
    #[bits(3)]
    pub sve_imm3: u32,
    #[bits(2)]
    pub sve_i3h2: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct BFMMLA_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct BFMMLA_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct BFMOPA_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16 {
    #[bits(2)]
    pub sme_zada_2b: u32,
    #[bits(3)]
    pub _op_2: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub sme_pm: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct BFMOPS_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16 {
    #[bits(2)]
    pub sme_zada_2b: u32,
    #[bits(3)]
    pub _op_2: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub sme_pm: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct BFMUL_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(1)]
    pub _op_10: u32,
    #[bits(1)]
    pub sve_i3l: u32,
    #[bits(4)]
    pub _op_12: u32,
    #[bits(3)]
    pub sve_imm3: u32,
    #[bits(2)]
    pub sve_i3h2: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct BFMUL_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct BFMUL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zm_5: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct BFSUB_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct BFSUB_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zm_5: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct BFVDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2 {
    #[bits(3)]
    pub imm3_0: u32,
    #[bits(3)]
    pub _op_3: u32,
    #[bits(4)]
    pub sme_zn2: u32,
    #[bits(2)]
    pub imm2_10: u32,
    #[bits(1)]
    pub _op_12: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct BGRP_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct BIC_Rd_Rn_Rm_SFT {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct BIC_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zm_5: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct BIC_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct BIC_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm {
    #[bits(4)]
    pub sve_pd: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(4)]
    pub sve_pn: u32,
    #[bits(1)]
    pub _op_9: u32,
    #[bits(4)]
    pub sve_pg4_10: u32,
    #[bits(2)]
    pub _op_14: u32,
    #[bits(4)]
    pub sve_pm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct BIC_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct BIC_Vd_SIMD_IMM_SFT {
    #[bits(5)]
    pub rd: u32,
    #[bits(27)]
    pub _op_5: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct BIC_Vd_V_4H_SIMD_IMM_SFT_LSL {
    #[bits(5)]
    pub rd: u32,
    #[bits(27)]
    pub _op_5: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct BICS_Rd_Rn_Rm_SFT {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct BICS_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm {
    #[bits(4)]
    pub sve_pd: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(4)]
    pub sve_pn: u32,
    #[bits(1)]
    pub _op_9: u32,
    #[bits(4)]
    pub sve_pg4_10: u32,
    #[bits(2)]
    pub _op_14: u32,
    #[bits(4)]
    pub sve_pm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct BIF_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct BIT_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct BL_ADDR_PCREL26 {
    #[bits(26)]
    pub imm26: u32,
    #[bits(6)]
    pub _op_26: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct BLR_Rn {
    #[bits(5)]
    pub _op_0: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct BLRAA_Rn_Rd_SP {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct BLRAAZ_Rn {
    #[bits(5)]
    pub _op_0: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct BLRAB_Rn_Rd_SP {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct BLRABZ_Rn {
    #[bits(5)]
    pub _op_0: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct BMOPA_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16 {
    #[bits(2)]
    pub sme_zada_2b: u32,
    #[bits(3)]
    pub _op_2: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub sme_pm: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct BMOPS_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16 {
    #[bits(2)]
    pub sme_zada_2b: u32,
    #[bits(3)]
    pub _op_2: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub sme_pm: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct BR_Rn {
    #[bits(5)]
    pub _op_0: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct BRAA_Rn_Rd_SP {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct BRAAZ_Rn {
    #[bits(5)]
    pub _op_0: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct BRAB_Rn_Rd_SP {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct BRABZ_Rn {
    #[bits(5)]
    pub _op_0: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct BRK_EXCEPTION {
    #[bits(5)]
    pub _op_0: u32,
    #[bits(16)]
    pub imm16_5: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct BRKA_SVE_Pd_SVE_Pg4_10_SVE_Pn {
    #[bits(4)]
    pub sve_pd: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(4)]
    pub sve_pn: u32,
    #[bits(1)]
    pub _op_9: u32,
    #[bits(4)]
    pub sve_pg4_10: u32,
    #[bits(18)]
    pub _op_14: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct BRKAS_SVE_Pd_SVE_Pg4_10_SVE_Pn {
    #[bits(4)]
    pub sve_pd: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(4)]
    pub sve_pn: u32,
    #[bits(1)]
    pub _op_9: u32,
    #[bits(4)]
    pub sve_pg4_10: u32,
    #[bits(18)]
    pub _op_14: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct BRKB_SVE_Pd_SVE_Pg4_10_SVE_Pn {
    #[bits(4)]
    pub sve_pd: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(4)]
    pub sve_pn: u32,
    #[bits(1)]
    pub _op_9: u32,
    #[bits(4)]
    pub sve_pg4_10: u32,
    #[bits(18)]
    pub _op_14: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct BRKBS_SVE_Pd_SVE_Pg4_10_SVE_Pn {
    #[bits(4)]
    pub sve_pd: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(4)]
    pub sve_pn: u32,
    #[bits(1)]
    pub _op_9: u32,
    #[bits(4)]
    pub sve_pg4_10: u32,
    #[bits(18)]
    pub _op_14: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct BRKN_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pd {
    #[bits(4)]
    pub sve_pd: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(4)]
    pub sve_pn: u32,
    #[bits(1)]
    pub _op_9: u32,
    #[bits(4)]
    pub sve_pg4_10: u32,
    #[bits(18)]
    pub _op_14: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct BRKNS_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pd {
    #[bits(4)]
    pub sve_pd: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(4)]
    pub sve_pn: u32,
    #[bits(1)]
    pub _op_9: u32,
    #[bits(4)]
    pub sve_pg4_10: u32,
    #[bits(18)]
    pub _op_14: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct BRKPA_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm {
    #[bits(4)]
    pub sve_pd: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(4)]
    pub sve_pn: u32,
    #[bits(1)]
    pub _op_9: u32,
    #[bits(4)]
    pub sve_pg4_10: u32,
    #[bits(2)]
    pub _op_14: u32,
    #[bits(4)]
    pub sve_pm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct BRKPAS_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm {
    #[bits(4)]
    pub sve_pd: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(4)]
    pub sve_pn: u32,
    #[bits(1)]
    pub _op_9: u32,
    #[bits(4)]
    pub sve_pg4_10: u32,
    #[bits(2)]
    pub _op_14: u32,
    #[bits(4)]
    pub sve_pm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct BRKPB_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm {
    #[bits(4)]
    pub sve_pd: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(4)]
    pub sve_pn: u32,
    #[bits(1)]
    pub _op_9: u32,
    #[bits(4)]
    pub sve_pg4_10: u32,
    #[bits(2)]
    pub _op_14: u32,
    #[bits(4)]
    pub sve_pm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct BRKPBS_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm {
    #[bits(4)]
    pub sve_pd: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(4)]
    pub sve_pn: u32,
    #[bits(1)]
    pub _op_9: u32,
    #[bits(4)]
    pub sve_pg4_10: u32,
    #[bits(2)]
    pub _op_14: u32,
    #[bits(4)]
    pub sve_pm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct BSL_SVE_Zd_SVE_Zd_SVE_Zm_16_SVE_Zn {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct BSL_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct BSL1N_SVE_Zd_SVE_Zd_SVE_Zm_16_SVE_Zn {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct BSL2N_SVE_Zd_SVE_Zd_SVE_Zm_16_SVE_Zn {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CADD_SVE_Zd_SVE_Zd_SVE_Zn_SVE_IMM_ROT3 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(1)]
    pub sve_rot3: u32,
    #[bits(21)]
    pub _op_11: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CAS_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CASA_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CASAB_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CASAH_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CASAL_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CASALB_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CASALH_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CASB_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CASH_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CASL_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CASLB_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CASLH_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CASP_Rs_PAIRREG_Rt_PAIRREG_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CASPA_Rs_PAIRREG_Rt_PAIRREG_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CASPAL_Rs_PAIRREG_Rt_PAIRREG_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CASPL_Rs_PAIRREG_Rt_PAIRREG_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CBNZ_Rt_ADDR_PCREL19 {
    #[bits(5)]
    pub rt: u32,
    #[bits(19)]
    pub imm19: u32,
    #[bits(8)]
    pub _op_24: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CBZ_Rt_ADDR_PCREL19 {
    #[bits(5)]
    pub rt: u32,
    #[bits(19)]
    pub imm19: u32,
    #[bits(8)]
    pub _op_24: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CCMN_Rn_Rm_NZCV_COND {
    #[bits(4)]
    pub nzcv: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CCMN_Rn_CCMP_IMM_NZCV_COND {
    #[bits(4)]
    pub nzcv: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub imm5: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CCMP_Rn_Rm_NZCV_COND {
    #[bits(4)]
    pub nzcv: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CCMP_Rn_CCMP_IMM_NZCV_COND {
    #[bits(4)]
    pub nzcv: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub imm5: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CDOT_SVE_Zd_SVE_Zn_SVE_Zm_16_SVE_IMM_ROT2 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(2)]
    pub sve_rot2: u32,
    #[bits(4)]
    pub _op_12: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CDOT_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX_SVE_IMM_ROT2 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(2)]
    pub sve_rot2: u32,
    #[bits(4)]
    pub _op_12: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CDOT_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX_SVE_IMM_ROT2 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(2)]
    pub sve_rot2: u32,
    #[bits(4)]
    pub _op_12: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CFINV {
    #[bits(32)]
    pub _op_0: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CHKFEAT_X16 {
    #[bits(32)]
    pub _op_0: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CLASTA_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zm_5: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CLASTA_SVE_Vd_SVE_Pg3_SVE_Vd_SVE_Zm_5 {
    #[bits(5)]
    pub sve_vd: u32,
    #[bits(5)]
    pub sve_zm_5: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CLASTA_Rd_SVE_Pg3_Rd_SVE_Zm_5 {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub sve_zm_5: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CLASTB_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zm_5: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CLASTB_SVE_Vd_SVE_Pg3_SVE_Vd_SVE_Zm_5 {
    #[bits(5)]
    pub sve_vd: u32,
    #[bits(5)]
    pub sve_zm_5: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CLASTB_Rd_SVE_Pg3_Rd_SVE_Zm_5 {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub sve_zm_5: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CLREX_UIMM4 {
    #[bits(8)]
    pub _op_0: u32,
    #[bits(4)]
    pub crm: u32,
    #[bits(20)]
    pub _op_12: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CLS_Rd_Rn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CLS_SVE_Zd_SVE_Pg3_SVE_Zn {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CLS_Vd_Vn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CLZ_Rd_Rn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CLZ_SVE_Zd_SVE_Pg3_SVE_Zn {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CLZ_Vd_Vn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CMEQ_Vd_Vn_IMM0 {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CMEQ_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CMEQ_Sd_Sn_IMM0 {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CMEQ_Sd_Sn_Sm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CMGE_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CMGE_Vd_Vn_IMM0 {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CMGE_Sd_Sn_IMM0 {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CMGE_Sd_Sn_Sm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CMGT_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CMGT_Vd_Vn_IMM0 {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CMGT_Sd_Sn_IMM0 {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CMGT_Sd_Sn_Sm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CMHI_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CMHI_Sd_Sn_Sm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CMHS_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CMHS_Sd_Sn_Sm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CMLA_SVE_Zd_SVE_Zn_SVE_Zm_16_SVE_IMM_ROT2 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(2)]
    pub sve_rot2: u32,
    #[bits(4)]
    pub _op_12: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CMLA_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX_SVE_IMM_ROT2 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(2)]
    pub sve_rot2: u32,
    #[bits(4)]
    pub _op_12: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CMLA_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX_SVE_IMM_ROT2 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(2)]
    pub sve_rot2: u32,
    #[bits(4)]
    pub _op_12: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CMLE_Vd_Vn_IMM0 {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CMLE_Sd_Sn_IMM0 {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CMLT_Vd_Vn_IMM0 {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CMLT_Sd_Sn_IMM0 {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CMPEQ_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16 {
    #[bits(4)]
    pub sve_pd: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CMPEQ_SVE_Pd_S_B_SVE_Pg3_P_Z_SVE_Zn_S_B_SVE_Zm_16_S_B {
    #[bits(4)]
    pub sve_pd: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CMPEQ_SVE_Pd_SVE_Pg3_SVE_Zn_SIMM5 {
    #[bits(4)]
    pub sve_pd: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub imm5: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CMPGE_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16 {
    #[bits(4)]
    pub sve_pd: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CMPGE_SVE_Pd_S_B_SVE_Pg3_P_Z_SVE_Zn_S_B_SVE_Zm_16_S_B {
    #[bits(4)]
    pub sve_pd: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CMPGE_SVE_Pd_SVE_Pg3_SVE_Zn_SIMM5 {
    #[bits(4)]
    pub sve_pd: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub imm5: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CMPGT_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16 {
    #[bits(4)]
    pub sve_pd: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CMPGT_SVE_Pd_S_B_SVE_Pg3_P_Z_SVE_Zn_S_B_SVE_Zm_16_S_B {
    #[bits(4)]
    pub sve_pd: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CMPGT_SVE_Pd_SVE_Pg3_SVE_Zn_SIMM5 {
    #[bits(4)]
    pub sve_pd: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub imm5: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CMPHI_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16 {
    #[bits(4)]
    pub sve_pd: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CMPHI_SVE_Pd_S_B_SVE_Pg3_P_Z_SVE_Zn_S_B_SVE_Zm_16_S_D {
    #[bits(4)]
    pub sve_pd: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CMPHI_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_UIMM7 {
    #[bits(4)]
    pub sve_pd: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(1)]
    pub _op_13: u32,
    #[bits(7)]
    pub sve_imm7: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CMPHS_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16 {
    #[bits(4)]
    pub sve_pd: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CMPHS_SVE_Pd_S_B_SVE_Pg3_P_Z_SVE_Zn_S_B_SVE_Zm_16_S_D {
    #[bits(4)]
    pub sve_pd: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CMPHS_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_UIMM7 {
    #[bits(4)]
    pub sve_pd: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(1)]
    pub _op_13: u32,
    #[bits(7)]
    pub sve_imm7: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CMPLE_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16 {
    #[bits(4)]
    pub sve_pd: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CMPLE_SVE_Pd_SVE_Pg3_SVE_Zn_SIMM5 {
    #[bits(4)]
    pub sve_pd: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub imm5: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CMPLO_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16 {
    #[bits(4)]
    pub sve_pd: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CMPLO_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_UIMM7 {
    #[bits(4)]
    pub sve_pd: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(1)]
    pub _op_13: u32,
    #[bits(7)]
    pub sve_imm7: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CMPLS_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16 {
    #[bits(4)]
    pub sve_pd: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CMPLS_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_UIMM7 {
    #[bits(4)]
    pub sve_pd: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(1)]
    pub _op_13: u32,
    #[bits(7)]
    pub sve_imm7: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CMPLT_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16 {
    #[bits(4)]
    pub sve_pd: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CMPLT_SVE_Pd_SVE_Pg3_SVE_Zn_SIMM5 {
    #[bits(4)]
    pub sve_pd: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub imm5: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CMPNE_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16 {
    #[bits(4)]
    pub sve_pd: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CMPNE_SVE_Pd_S_B_SVE_Pg3_P_Z_SVE_Zn_S_B_SVE_Zm_16_S_B {
    #[bits(4)]
    pub sve_pd: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CMPNE_SVE_Pd_SVE_Pg3_SVE_Zn_SIMM5 {
    #[bits(4)]
    pub sve_pd: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub imm5: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CMTST_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CMTST_Sd_Sn_Sm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CNOT_SVE_Zd_SVE_Pg3_SVE_Zn {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CNT_Rd_Rn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CNT_SVE_Zd_SVE_Pg3_SVE_Zn {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CNT_Vd_Vn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CNTB_Rd_SVE_PATTERN_SCALED {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub sve_pattern: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CNTD_Rd_SVE_PATTERN_SCALED {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub sve_pattern: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CNTH_Rd_SVE_PATTERN_SCALED {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub sve_pattern: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CNTP_Rd_SVE_Pg4_10_SVE_Pn {
    #[bits(5)]
    pub rd: u32,
    #[bits(4)]
    pub sve_pn: u32,
    #[bits(1)]
    pub _op_9: u32,
    #[bits(4)]
    pub sve_pg4_10: u32,
    #[bits(18)]
    pub _op_14: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CNTP_Rd_SME_PNn_SME_VLxN_10 {
    #[bits(5)]
    pub rd: u32,
    #[bits(4)]
    pub sve_pn: u32,
    #[bits(1)]
    pub _op_9: u32,
    #[bits(1)]
    pub sme_vl_10: u32,
    #[bits(21)]
    pub _op_11: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CNTW_Rd_SVE_PATTERN_SCALED {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub sve_pattern: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct COMPACT_SVE_Zd_SVE_Pg3_SVE_Zn {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CPY_SVE_Zd_SVE_Pg4_16_SVE_ASIMM {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(9)]
    pub sve_imm9: u32,
    #[bits(2)]
    pub _op_14: u32,
    #[bits(4)]
    pub sve_pg4_16: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CPY_SVE_Zd_SVE_Pg3_SVE_Vn {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_vn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CPY_SVE_Zd_SVE_Pg3_Rn_SP {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CPYE_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CPYEN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CPYERN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CPYERT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CPYERTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CPYERTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CPYERTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CPYET_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CPYETN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CPYETRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CPYETWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CPYEWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CPYEWT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CPYEWTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CPYEWTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CPYEWTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CPYFE_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CPYFEN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CPYFERN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CPYFERT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CPYFERTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CPYFERTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CPYFERTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CPYFET_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CPYFETN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CPYFETRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CPYFETWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CPYFEWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CPYFEWT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CPYFEWTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CPYFEWTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CPYFEWTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CPYFM_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CPYFMN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CPYFMRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CPYFMRT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CPYFMRTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CPYFMRTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CPYFMRTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CPYFMT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CPYFMTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CPYFMTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CPYFMTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CPYFMWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CPYFMWT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CPYFMWTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CPYFMWTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CPYFMWTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CPYFP_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CPYFPN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CPYFPRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CPYFPRT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CPYFPRTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CPYFPRTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CPYFPRTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CPYFPT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CPYFPTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CPYFPTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CPYFPTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CPYFPWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CPYFPWT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CPYFPWTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CPYFPWTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CPYFPWTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CPYM_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CPYMN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CPYMRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CPYMRT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CPYMRTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CPYMRTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CPYMRTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CPYMT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CPYMTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CPYMTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CPYMTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CPYMWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CPYMWT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CPYMWTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CPYMWTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CPYMWTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CPYP_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CPYPN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CPYPRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CPYPRT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CPYPRTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CPYPRTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CPYPRTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CPYPT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CPYPTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CPYPTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CPYPTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CPYPWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CPYPWT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CPYPWTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CPYPWTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CPYPWTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CRC32B_Rd_Rn_Rm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CRC32CB_Rd_Rn_Rm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CRC32CH_Rd_Rn_Rm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CRC32CW_Rd_Rn_Rm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CRC32CX_Rd_Rn_Rm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CRC32H_Rd_Rn_Rm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CRC32W_Rd_Rn_Rm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CRC32X_Rd_Rn_Rm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CSEL_Rd_Rn_Rm_COND {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CSINC_Rd_Rn_Rm_COND {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CSINV_Rd_Rn_Rm_COND {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CSNEG_Rd_Rn_Rm_COND {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CTERMEQ_Rn_Rm {
    #[bits(5)]
    pub _op_0: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CTERMNE_Rn_Rm {
    #[bits(5)]
    pub _op_0: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct CTZ_Rd_Rn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct DCPS1_EXCEPTION {
    #[bits(5)]
    pub _op_0: u32,
    #[bits(16)]
    pub imm16_5: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct DCPS2_EXCEPTION {
    #[bits(5)]
    pub _op_0: u32,
    #[bits(16)]
    pub imm16_5: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct DCPS3_EXCEPTION {
    #[bits(5)]
    pub _op_0: u32,
    #[bits(16)]
    pub imm16_5: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct DECB_Rd_SVE_PATTERN_SCALED {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub sve_pattern: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct DECD_SVE_Zd_SVE_PATTERN_SCALED {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_pattern: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct DECD_Rd_SVE_PATTERN_SCALED {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub sve_pattern: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct DECH_SVE_Zd_SVE_PATTERN_SCALED {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_pattern: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct DECH_Rd_SVE_PATTERN_SCALED {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub sve_pattern: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct DECP_SVE_Zd_SVE_Pg4_5 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(4)]
    pub sve_pg4_5: u32,
    #[bits(23)]
    pub _op_9: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct DECP_Rd_SVE_Pg4_5 {
    #[bits(5)]
    pub rd: u32,
    #[bits(4)]
    pub sve_pg4_5: u32,
    #[bits(23)]
    pub _op_9: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct DECW_SVE_Zd_SVE_PATTERN_SCALED {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_pattern: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct DECW_Rd_SVE_PATTERN_SCALED {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub sve_pattern: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct DGH {
    #[bits(32)]
    pub _op_0: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct DMB_BARRIER {
    #[bits(32)]
    pub _op_0: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct DRPS {
    #[bits(32)]
    pub _op_0: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct DSB_BARRIER_DSB_NXS {
    #[bits(32)]
    pub _op_0: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct DSB_BARRIER {
    #[bits(32)]
    pub _op_0: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct DUP_SVE_Zd_SVE_Zn_INDEX {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct DUP_SVE_Zd_Rn_SP {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct DUP_SVE_Zd_SVE_ASIMM {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(9)]
    pub sve_imm9: u32,
    #[bits(18)]
    pub _op_14: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct DUP_Vd_En {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct DUP_Vd_Rn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct DUP_Sd_En {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct DUPM_SVE_Zd_SVE_LIMM {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(6)]
    pub sve_imms: u32,
    #[bits(6)]
    pub sve_immr: u32,
    #[bits(1)]
    pub sve_n: u32,
    #[bits(14)]
    pub _op_18: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct DUPQ_SVE_Zd_SVE_Zn_5_INDEX {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(4)]
    pub sve_tsz: u32,
    #[bits(1)]
    pub sve_i2h: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct EON_Rd_Rn_Rm_SFT {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct EOR_Rd_SP_Rn_LIMM {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub imms: u32,
    #[bits(6)]
    pub immr: u32,
    #[bits(1)]
    pub n: u32,
    #[bits(9)]
    pub _op_23: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct EOR_Rd_Rn_Rm_SFT {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct EOR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zm_5: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct EOR_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct EOR_SVE_Zd_SVE_Zd_SVE_LIMM {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(6)]
    pub sve_imms: u32,
    #[bits(6)]
    pub sve_immr: u32,
    #[bits(1)]
    pub sve_n: u32,
    #[bits(14)]
    pub _op_18: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct EOR_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm {
    #[bits(4)]
    pub sve_pd: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(4)]
    pub sve_pn: u32,
    #[bits(1)]
    pub _op_9: u32,
    #[bits(4)]
    pub sve_pg4_10: u32,
    #[bits(2)]
    pub _op_14: u32,
    #[bits(4)]
    pub sve_pm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct EOR_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct EOR3_SVE_Zd_SVE_Zd_SVE_Zm_16_SVE_Zn {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct EOR3_Vd_Vn_Vm_Va {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(5)]
    pub ra: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct EORBT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct EORQV_Vd_SVE_Pg3_SVE_Zn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct EORS_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm {
    #[bits(4)]
    pub sve_pd: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(4)]
    pub sve_pn: u32,
    #[bits(1)]
    pub _op_9: u32,
    #[bits(4)]
    pub sve_pg4_10: u32,
    #[bits(2)]
    pub _op_14: u32,
    #[bits(4)]
    pub sve_pm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct EORTB_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct EORV_SVE_Vd_SVE_Pg3_SVE_Zn {
    #[bits(5)]
    pub sve_vd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ERET {
    #[bits(32)]
    pub _op_0: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ERETAA {
    #[bits(32)]
    pub _op_0: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ERETAB {
    #[bits(32)]
    pub _op_0: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct EXT_SVE_Zd_SVE_Zd_SVE_Zm_5_SVE_UIMM8_53 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zm_5: u32,
    #[bits(3)]
    pub imm3_10: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub imm5: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct EXT_SVE_Zd_SVE_ZnxN_SVE_UIMM8_53 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub imm3_10: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub imm5: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct EXT_Vd_Vn_Vm_IDX {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(1)]
    pub _op_10: u32,
    #[bits(4)]
    pub imm4_11: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct EXTQ_SVE_Zd_SVE_Zd_SVE_Zm_imm4 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zm_5: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(4)]
    pub sve_imm4: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct EXTR_Rd_Rn_Rm_IMMS {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub imm6_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FABD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zm_5: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FABD_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FABD_Sd_Sn_Sm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FABD_Vd_V_2S_Vn_V_2S_Vm_V_2S {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FABD_Sd_S_S_Sn_S_S_Sm_S_S {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FABS_SVE_Zd_SVE_Pg3_SVE_Zn {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FABS_Vd_Vn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FABS_Vd_V_4H_Vn_V_4H {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FABS_Fd_Fn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FABS_Fd_S_S_Fn_S_S {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FACGE_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16 {
    #[bits(4)]
    pub sve_pd: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FACGE_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FACGE_Sd_Sn_Sm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FACGE_Vd_V_2S_Vn_V_2S_Vm_V_2S {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FACGE_Sd_S_S_Sn_S_S_Sm_S_S {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FACGT_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16 {
    #[bits(4)]
    pub sve_pd: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FACGT_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FACGT_Sd_Sn_Sm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FACGT_Vd_V_2S_Vn_V_2S_Vm_V_2S {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FACGT_Sd_S_S_Sn_S_S_Sm_S_S {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FADD_SME_ZA_array_off3_0_SME_Znx2 {
    #[bits(3)]
    pub imm3_0: u32,
    #[bits(3)]
    pub _op_3: u32,
    #[bits(4)]
    pub sme_zn2: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(17)]
    pub _op_15: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FADD_SME_ZA_array_off3_0_SME_Znx4 {
    #[bits(3)]
    pub imm3_0: u32,
    #[bits(4)]
    pub _op_3: u32,
    #[bits(3)]
    pub sme_zn4: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(17)]
    pub _op_15: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FADD_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zm_5: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_I1_HALF_ONE {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(1)]
    pub sve_i1: u32,
    #[bits(4)]
    pub _op_6: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FADD_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FADD_Vd_V_2S_Vn_V_2S_Vm_V_2S {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FADD_Fd_Fn_Fm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FADD_Fd_S_S_Fn_S_S_Fm_S_S {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FADDA_SVE_Vd_SVE_Pg3_SVE_Vd_SVE_Zm_5 {
    #[bits(5)]
    pub sve_vd: u32,
    #[bits(5)]
    pub sve_zm_5: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FADDP_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FADDP_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FADDP_Vd_V_2S_Vn_V_2S_Vm_V_2S {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FADDP_Sd_Vn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FADDP_Sd_S_S_Vn_V_2S {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FADDQV_Vd_SVE_Pg3_SVE_Zn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FADDV_SVE_Vd_SVE_Pg3_SVE_Zn {
    #[bits(5)]
    pub sve_vd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5_SVE_IMM_ROT1 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zm_5: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(1)]
    pub sve_rot1: u32,
    #[bits(15)]
    pub _op_17: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCADD_Vd_Vn_Vm_IMM_ROT3 {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(2)]
    pub _op_10: u32,
    #[bits(1)]
    pub rotate3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCCMP_Fn_Fm_NZCV_COND {
    #[bits(4)]
    pub nzcv: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCCMP_Fn_S_S_Fm_S_S_NZCV_COND {
    #[bits(4)]
    pub nzcv: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCCMPE_Fn_Fm_NZCV_COND {
    #[bits(4)]
    pub nzcv: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCCMPE_Fn_S_S_Fm_S_S_NZCV_COND {
    #[bits(4)]
    pub nzcv: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCLAMP_SME_Zdnx2_SVE_Zn_SVE_Zm_16 {
    #[bits(1)]
    pub _op_0: u32,
    #[bits(4)]
    pub sme_zdn2: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCLAMP_SME_Zdnx4_SVE_Zn_SVE_Zm_16 {
    #[bits(2)]
    pub _op_0: u32,
    #[bits(3)]
    pub sme_zdn4: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCLAMP_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCMEQ_SVE_Pd_SVE_Pg3_SVE_Zn_FPIMM0 {
    #[bits(4)]
    pub sve_pd: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCMEQ_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16 {
    #[bits(4)]
    pub sve_pd: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCMEQ_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCMEQ_Sd_Sn_Sm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCMEQ_Vd_Vn_FPIMM0 {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCMEQ_Vd_V_4H_Vn_V_4H_FPIMM0 {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCMEQ_Vd_V_2S_Vn_V_2S_Vm_V_2S {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCMEQ_Sd_Sn_FPIMM0 {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCMEQ_Sd_S_H_Sn_S_H_FPIMM0 {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCMEQ_Sd_S_S_Sn_S_S_Sm_S_S {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCMGE_SVE_Pd_SVE_Pg3_SVE_Zn_FPIMM0 {
    #[bits(4)]
    pub sve_pd: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCMGE_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16 {
    #[bits(4)]
    pub sve_pd: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCMGE_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCMGE_Sd_Sn_Sm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCMGE_Vd_Vn_FPIMM0 {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCMGE_Vd_V_4H_Vn_V_4H_FPIMM0 {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCMGE_Vd_V_2S_Vn_V_2S_Vm_V_2S {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCMGE_Sd_Sn_FPIMM0 {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCMGE_Sd_S_H_Sn_S_H_FPIMM0 {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCMGE_Sd_S_S_Sn_S_S_Sm_S_S {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCMGT_SVE_Pd_SVE_Pg3_SVE_Zn_FPIMM0 {
    #[bits(4)]
    pub sve_pd: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCMGT_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16 {
    #[bits(4)]
    pub sve_pd: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCMGT_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCMGT_Sd_Sn_Sm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCMGT_Vd_Vn_FPIMM0 {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCMGT_Vd_V_4H_Vn_V_4H_FPIMM0 {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCMGT_Vd_V_2S_Vn_V_2S_Vm_V_2S {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCMGT_Sd_Sn_FPIMM0 {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCMGT_Sd_S_H_Sn_S_H_FPIMM0 {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCMGT_Sd_S_S_Sn_S_S_Sm_S_S {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCMLA_SVE_Zd_SVE_Pg3_SVE_Zn_SVE_Zm_16_IMM_ROT2 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(2)]
    pub rotate2: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCMLA_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX_SVE_IMM_ROT2 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(2)]
    pub sve_rot2: u32,
    #[bits(4)]
    pub _op_12: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCMLA_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX_SVE_IMM_ROT2 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(2)]
    pub sve_rot2: u32,
    #[bits(4)]
    pub _op_12: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCMLA_Vd_Vn_Vm_IMM_ROT1 {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(1)]
    pub _op_10: u32,
    #[bits(2)]
    pub rotate1: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCMLA_Vd_Vn_Em_IMM_ROT2 {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub rotate2: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCMLE_SVE_Pd_SVE_Pg3_SVE_Zn_FPIMM0 {
    #[bits(4)]
    pub sve_pd: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCMLE_Vd_Vn_FPIMM0 {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCMLE_Vd_V_4H_Vn_V_4H_FPIMM0 {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCMLE_Sd_Sn_FPIMM0 {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCMLE_Sd_S_H_Sn_S_H_FPIMM0 {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCMLT_SVE_Pd_SVE_Pg3_SVE_Zn_FPIMM0 {
    #[bits(4)]
    pub sve_pd: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCMLT_Vd_Vn_FPIMM0 {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCMLT_Vd_V_4H_Vn_V_4H_FPIMM0 {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCMLT_Sd_Sn_FPIMM0 {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCMLT_Sd_S_H_Sn_S_H_FPIMM0 {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCMNE_SVE_Pd_SVE_Pg3_SVE_Zn_FPIMM0 {
    #[bits(4)]
    pub sve_pd: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCMNE_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16 {
    #[bits(4)]
    pub sve_pd: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCMP_Fn_Fm {
    #[bits(5)]
    pub _op_0: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCMP_Fn_S_S_Fm_S_S {
    #[bits(5)]
    pub _op_0: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCMP_Fn_FPIMM0 {
    #[bits(5)]
    pub _op_0: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCMP_Fn_S_S_FPIMM0 {
    #[bits(5)]
    pub _op_0: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCMPE_Fn_Fm {
    #[bits(5)]
    pub _op_0: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCMPE_Fn_S_S_Fm_S_S {
    #[bits(5)]
    pub _op_0: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCMPE_Fn_FPIMM0 {
    #[bits(5)]
    pub _op_0: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCMPE_Fn_S_S_FPIMM0 {
    #[bits(5)]
    pub _op_0: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCMUO_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16 {
    #[bits(4)]
    pub sve_pd: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCPY_SVE_Zd_SVE_Pg4_16_SVE_FPIMM8 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(8)]
    pub sve_imm8: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(4)]
    pub sve_pg4_16: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCSEL_Fd_Fn_Fm_COND {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCSEL_Fd_S_S_Fn_S_S_Fm_S_S_COND {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCVT_SVE_Zd_SME_Znx2 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(1)]
    pub _op_5: u32,
    #[bits(4)]
    pub sme_zn2: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCVT_SVE_Zd_SVE_Pg3_SVE_Zn {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCVT_SVE_Zd_S_H_SVE_Pg3_P_M_SVE_Zn_S_D {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCVT_SVE_Zd_S_S_SVE_Pg3_P_M_SVE_Zn_S_D {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCVT_SVE_Zd_S_S_SVE_Pg3_P_M_SVE_Zn_S_H {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCVT_SVE_Zd_S_D_SVE_Pg3_P_M_SVE_Zn_S_H {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCVT_SVE_Zd_S_D_SVE_Pg3_P_M_SVE_Zn_S_S {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCVT_Fd_Fn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCVTAS_Vd_Vn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCVTAS_Vd_V_4H_Vn_V_4H {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCVTAS_Rd_Fn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCVTAS_Rd_W_Fn_S_D {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCVTAS_Sd_Sn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCVTAS_Sd_S_H_Sn_S_H {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCVTAU_Vd_Vn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCVTAU_Vd_V_4H_Vn_V_4H {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCVTAU_Rd_Fn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCVTAU_Rd_W_Fn_S_D {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCVTAU_Sd_Sn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCVTAU_Sd_S_H_Sn_S_H {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCVTL_Vd_Vn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCVTL2_Vd_Vn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCVTLT_SVE_Zd_SVE_Pg3_SVE_Zn {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCVTLT_SVE_Zd_S_D_SVE_Pg3_P_M_SVE_Zn_S_S {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCVTMS_Vd_Vn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCVTMS_Vd_V_4H_Vn_V_4H {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCVTMS_Rd_Fn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCVTMS_Rd_W_Fn_S_D {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCVTMS_Sd_Sn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCVTMS_Sd_S_H_Sn_S_H {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCVTMU_Vd_Vn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCVTMU_Vd_V_4H_Vn_V_4H {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCVTMU_Rd_Fn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCVTMU_Rd_W_Fn_S_D {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCVTMU_Sd_Sn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCVTMU_Sd_S_H_Sn_S_H {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCVTN_SVE_Zd_SME_Znx2 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(1)]
    pub _op_5: u32,
    #[bits(4)]
    pub sme_zn2: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCVTN_Vd_Vn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCVTN2_Vd_Vn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCVTNS_Vd_Vn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCVTNS_Vd_V_4H_Vn_V_4H {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCVTNS_Rd_Fn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCVTNS_Rd_W_Fn_S_D {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCVTNS_Sd_Sn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCVTNS_Sd_S_H_Sn_S_H {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCVTNT_SVE_Zd_SVE_Pg3_SVE_Zn {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCVTNT_SVE_Zd_S_S_SVE_Pg3_P_M_SVE_Zn_S_D {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCVTNU_Vd_Vn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCVTNU_Vd_V_4H_Vn_V_4H {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCVTNU_Rd_Fn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCVTNU_Rd_W_Fn_S_D {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCVTNU_Sd_Sn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCVTNU_Sd_S_H_Sn_S_H {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCVTPS_Vd_Vn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCVTPS_Vd_V_4H_Vn_V_4H {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCVTPS_Rd_Fn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCVTPS_Rd_W_Fn_S_D {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCVTPS_Sd_Sn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCVTPS_Sd_S_H_Sn_S_H {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCVTPU_Vd_Vn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCVTPU_Vd_V_4H_Vn_V_4H {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCVTPU_Rd_Fn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCVTPU_Rd_W_Fn_S_D {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCVTPU_Sd_Sn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCVTPU_Sd_S_H_Sn_S_H {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCVTX_SVE_Zd_SVE_Pg3_SVE_Zn {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCVTXN_Vd_Vn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCVTXN_Sd_Sn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCVTXN2_Vd_Vn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCVTXNT_SVE_Zd_SVE_Pg3_SVE_Zn {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCVTZS_SME_Zdnx2_SME_Znx2 {
    #[bits(1)]
    pub _op_0: u32,
    #[bits(4)]
    pub sme_zdn2: u32,
    #[bits(1)]
    pub _op_5: u32,
    #[bits(4)]
    pub sme_zn2: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCVTZS_SME_Zdnx4_SME_Znx4 {
    #[bits(2)]
    pub _op_0: u32,
    #[bits(3)]
    pub sme_zdn4: u32,
    #[bits(2)]
    pub _op_5: u32,
    #[bits(3)]
    pub sme_zn4: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCVTZS_SVE_Zd_SVE_Pg3_SVE_Zn {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCVTZS_SVE_Zd_S_S_SVE_Pg3_P_M_SVE_Zn_S_D {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCVTZS_SVE_Zd_S_S_SVE_Pg3_P_M_SVE_Zn_S_H {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCVTZS_SVE_Zd_S_D_SVE_Pg3_P_M_SVE_Zn_S_S {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCVTZS_SVE_Zd_S_H_SVE_Pg3_P_M_SVE_Zn_S_H {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCVTZS_SVE_Zd_S_D_SVE_Pg3_P_M_SVE_Zn_S_H {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCVTZS_SVE_Zd_S_D_SVE_Pg3_P_M_SVE_Zn_S_D {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCVTZS_Rd_Fn_FBITS {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub scale: u32,
    #[bits(16)]
    pub _op_16: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCVTZS_Rd_W_Fn_S_D_FBITS_imm_1_32 {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub scale: u32,
    #[bits(16)]
    pub _op_16: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCVTZS_Vd_Vn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCVTZS_Vd_V_4H_Vn_V_4H {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCVTZS_Rd_Fn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCVTZS_Rd_W_Fn_S_D {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCVTZS_Sd_Sn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCVTZS_Sd_S_H_Sn_S_H {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCVTZS_Vd_Vn_IMM_VLSR {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCVTZS_Vd_V_2S_Vn_V_2S_IMM_VLSR_V_2S {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCVTZS_Sd_Sn_IMM_VLSR {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCVTZS_Sd_S_S_Sn_S_S_IMM_VLSR_S_S {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCVTZU_SME_Zdnx2_SME_Znx2 {
    #[bits(1)]
    pub _op_0: u32,
    #[bits(4)]
    pub sme_zdn2: u32,
    #[bits(1)]
    pub _op_5: u32,
    #[bits(4)]
    pub sme_zn2: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCVTZU_SME_Zdnx4_SME_Znx4 {
    #[bits(2)]
    pub _op_0: u32,
    #[bits(3)]
    pub sme_zdn4: u32,
    #[bits(2)]
    pub _op_5: u32,
    #[bits(3)]
    pub sme_zn4: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCVTZU_SVE_Zd_SVE_Pg3_SVE_Zn {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCVTZU_SVE_Zd_S_S_SVE_Pg3_P_M_SVE_Zn_S_S {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCVTZU_SVE_Zd_S_S_SVE_Pg3_P_M_SVE_Zn_S_H {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCVTZU_SVE_Zd_S_D_SVE_Pg3_P_M_SVE_Zn_S_S {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCVTZU_SVE_Zd_S_H_SVE_Pg3_P_M_SVE_Zn_S_H {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCVTZU_SVE_Zd_S_D_SVE_Pg3_P_M_SVE_Zn_S_H {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCVTZU_SVE_Zd_S_D_SVE_Pg3_P_M_SVE_Zn_S_D {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCVTZU_Rd_Fn_FBITS {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub scale: u32,
    #[bits(16)]
    pub _op_16: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCVTZU_Rd_W_Fn_S_D_FBITS_imm_1_32 {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub scale: u32,
    #[bits(16)]
    pub _op_16: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCVTZU_Vd_Vn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCVTZU_Vd_V_4H_Vn_V_4H {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCVTZU_Rd_Fn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCVTZU_Rd_W_Fn_S_D {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCVTZU_Sd_Sn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCVTZU_Sd_S_H_Sn_S_H {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCVTZU_Vd_Vn_IMM_VLSR {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCVTZU_Vd_V_2S_Vn_V_2S_IMM_VLSR_V_2S {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCVTZU_Sd_Sn_IMM_VLSR {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FCVTZU_Sd_S_S_Sn_S_S_IMM_VLSR_S_S {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FDIV_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zm_5: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FDIV_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FDIV_Vd_V_2S_Vn_V_2S_Vm_V_2S {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FDIV_Fd_Fn_Fm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FDIV_Fd_S_S_Fn_S_S_Fm_S_S {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FDIVR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zm_5: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2 {
    #[bits(3)]
    pub imm3_0: u32,
    #[bits(3)]
    pub _op_3: u32,
    #[bits(4)]
    pub sme_zn2: u32,
    #[bits(2)]
    pub imm2_10: u32,
    #[bits(1)]
    pub _op_12: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2 {
    #[bits(3)]
    pub imm3_0: u32,
    #[bits(4)]
    pub _op_3: u32,
    #[bits(3)]
    pub sme_zn4: u32,
    #[bits(2)]
    pub imm2_10: u32,
    #[bits(1)]
    pub _op_12: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FDOT_SME_ZA_array_off3_0_SVE_ZnxN_SME_Zm {
    #[bits(3)]
    pub imm3_0: u32,
    #[bits(2)]
    pub _op_3: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FDOT_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_H_SME_Zm_S_H {
    #[bits(3)]
    pub imm3_0: u32,
    #[bits(2)]
    pub _op_3: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zmx2 {
    #[bits(3)]
    pub imm3_0: u32,
    #[bits(3)]
    pub _op_3: u32,
    #[bits(4)]
    pub sme_zn2: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(2)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm2: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zmx4 {
    #[bits(3)]
    pub imm3_0: u32,
    #[bits(4)]
    pub _op_3: u32,
    #[bits(3)]
    pub sme_zn4: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(3)]
    pub _op_15: u32,
    #[bits(3)]
    pub sme_zm4: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FDOT_SVE_Zd_SVE_Zn_SVE_Zm3_19_INDEX {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(3)]
    pub sve_imm3: u32,
    #[bits(2)]
    pub imm2_19: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FDOT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FDUP_SVE_Zd_SVE_FPIMM8 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(8)]
    pub sve_imm8: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FEXPA_SVE_Zd_SVE_Zn {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FJCVTZS_Rd_Fn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FLOGB_SVE_Zd_SVE_Pg3_SVE_Zn {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMAD_SVE_Zd_SVE_Pg3_SVE_Zm_5_SVE_Za_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zm_5: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub sve_za_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMADD_Fd_Fn_Fm_Fa {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(5)]
    pub ra: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMADD_Fd_S_S_Fn_S_S_Fm_S_S_Fa_S_S {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(5)]
    pub ra: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMAX_SME_Zdnx2_SME_Zdnx2_SME_Zm {
    #[bits(1)]
    pub _op_0: u32,
    #[bits(4)]
    pub sme_zdn2: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMAX_SME_Zdnx2_SME_Zdnx2_SME_Zmx2 {
    #[bits(1)]
    pub _op_0: u32,
    #[bits(4)]
    pub sme_zdn2: u32,
    #[bits(12)]
    pub _op_5: u32,
    #[bits(4)]
    pub sme_zm2: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMAX_SME_Zdnx4_SME_Zdnx4_SME_Zm {
    #[bits(2)]
    pub _op_0: u32,
    #[bits(3)]
    pub sme_zdn4: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMAX_SME_Zdnx4_SME_Zdnx4_SME_Zmx4 {
    #[bits(2)]
    pub _op_0: u32,
    #[bits(3)]
    pub sme_zdn4: u32,
    #[bits(13)]
    pub _op_5: u32,
    #[bits(3)]
    pub sme_zm4: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMAX_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zm_5: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMAX_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_I1_ZERO_ONE {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(1)]
    pub sve_i1: u32,
    #[bits(4)]
    pub _op_6: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMAX_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMAX_Vd_V_2S_Vn_V_2S_Vm_V_2S {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMAX_Fd_Fn_Fm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMAX_Fd_S_S_Fn_S_S_Fm_S_S {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMAXNM_SME_Zdnx2_SME_Zdnx2_SME_Zm {
    #[bits(1)]
    pub _op_0: u32,
    #[bits(4)]
    pub sme_zdn2: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMAXNM_SME_Zdnx2_SME_Zdnx2_SME_Zmx2 {
    #[bits(1)]
    pub _op_0: u32,
    #[bits(4)]
    pub sme_zdn2: u32,
    #[bits(12)]
    pub _op_5: u32,
    #[bits(4)]
    pub sme_zm2: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMAXNM_SME_Zdnx4_SME_Zdnx4_SME_Zm {
    #[bits(2)]
    pub _op_0: u32,
    #[bits(3)]
    pub sme_zdn4: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMAXNM_SME_Zdnx4_SME_Zdnx4_SME_Zmx4 {
    #[bits(2)]
    pub _op_0: u32,
    #[bits(3)]
    pub sme_zdn4: u32,
    #[bits(13)]
    pub _op_5: u32,
    #[bits(3)]
    pub sme_zm4: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMAXNM_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zm_5: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMAXNM_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_I1_ZERO_ONE {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(1)]
    pub sve_i1: u32,
    #[bits(4)]
    pub _op_6: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMAXNM_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMAXNM_Vd_V_2S_Vn_V_2S_Vm_V_2S {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMAXNM_Fd_Fn_Fm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMAXNM_Fd_S_S_Fn_S_S_Fm_S_S {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMAXNMP_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMAXNMP_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMAXNMP_Vd_V_2S_Vn_V_2S_Vm_V_2S {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMAXNMP_Sd_Vn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMAXNMP_Sd_S_S_Vn_V_2S {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMAXNMQV_Vd_SVE_Pg3_SVE_Zn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMAXNMV_SVE_Vd_SVE_Pg3_SVE_Zn {
    #[bits(5)]
    pub sve_vd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMAXNMV_Fd_Vn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMAXNMV_Fd_S_S_Vn_V_4S {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMAXP_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMAXP_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMAXP_Vd_V_2S_Vn_V_2S_Vm_V_2S {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMAXP_Sd_Vn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMAXP_Sd_S_S_Vn_V_2S {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMAXQV_Vd_SVE_Pg3_SVE_Zn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMAXV_SVE_Vd_SVE_Pg3_SVE_Zn {
    #[bits(5)]
    pub sve_vd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMAXV_Fd_Vn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMAXV_Fd_S_S_Vn_V_4S {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMIN_SME_Zdnx2_SME_Zdnx2_SME_Zm {
    #[bits(1)]
    pub _op_0: u32,
    #[bits(4)]
    pub sme_zdn2: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMIN_SME_Zdnx2_SME_Zdnx2_SME_Zmx2 {
    #[bits(1)]
    pub _op_0: u32,
    #[bits(4)]
    pub sme_zdn2: u32,
    #[bits(12)]
    pub _op_5: u32,
    #[bits(4)]
    pub sme_zm2: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMIN_SME_Zdnx4_SME_Zdnx4_SME_Zm {
    #[bits(2)]
    pub _op_0: u32,
    #[bits(3)]
    pub sme_zdn4: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMIN_SME_Zdnx4_SME_Zdnx4_SME_Zmx4 {
    #[bits(2)]
    pub _op_0: u32,
    #[bits(3)]
    pub sme_zdn4: u32,
    #[bits(13)]
    pub _op_5: u32,
    #[bits(3)]
    pub sme_zm4: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMIN_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zm_5: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMIN_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_I1_ZERO_ONE {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(1)]
    pub sve_i1: u32,
    #[bits(4)]
    pub _op_6: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMIN_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMIN_Vd_V_2S_Vn_V_2S_Vm_V_2S {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMIN_Fd_Fn_Fm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMIN_Fd_S_S_Fn_S_S_Fm_S_S {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMINNM_SME_Zdnx2_SME_Zdnx2_SME_Zm {
    #[bits(1)]
    pub _op_0: u32,
    #[bits(4)]
    pub sme_zdn2: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMINNM_SME_Zdnx2_SME_Zdnx2_SME_Zmx2 {
    #[bits(1)]
    pub _op_0: u32,
    #[bits(4)]
    pub sme_zdn2: u32,
    #[bits(12)]
    pub _op_5: u32,
    #[bits(4)]
    pub sme_zm2: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMINNM_SME_Zdnx4_SME_Zdnx4_SME_Zm {
    #[bits(2)]
    pub _op_0: u32,
    #[bits(3)]
    pub sme_zdn4: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMINNM_SME_Zdnx4_SME_Zdnx4_SME_Zmx4 {
    #[bits(2)]
    pub _op_0: u32,
    #[bits(3)]
    pub sme_zdn4: u32,
    #[bits(13)]
    pub _op_5: u32,
    #[bits(3)]
    pub sme_zm4: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMINNM_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zm_5: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMINNM_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_I1_ZERO_ONE {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(1)]
    pub sve_i1: u32,
    #[bits(4)]
    pub _op_6: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMINNM_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMINNM_Vd_V_2S_Vn_V_2S_Vm_V_2S {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMINNM_Fd_Fn_Fm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMINNM_Fd_S_S_Fn_S_S_Fm_S_S {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMINNMP_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMINNMP_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMINNMP_Vd_V_2S_Vn_V_2S_Vm_V_2S {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMINNMP_Sd_Vn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMINNMP_Sd_S_S_Vn_V_2S {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMINNMQV_Vd_SVE_Pg3_SVE_Zn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMINNMV_SVE_Vd_SVE_Pg3_SVE_Zn {
    #[bits(5)]
    pub sve_vd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMINNMV_Fd_Vn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMINNMV_Fd_S_S_Vn_V_4S {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMINP_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMINP_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMINP_Vd_V_2S_Vn_V_2S_Vm_V_2S {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMINP_Sd_Vn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMINP_Sd_S_S_Vn_V_2S {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMINQV_Vd_SVE_Pg3_SVE_Zn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMINV_SVE_Vd_SVE_Pg3_SVE_Zn {
    #[bits(5)]
    pub sve_vd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMINV_Fd_Vn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMINV_Fd_S_S_Vn_V_4S {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMLA_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2 {
    #[bits(3)]
    pub imm3_0: u32,
    #[bits(3)]
    pub _op_3: u32,
    #[bits(4)]
    pub sme_zn2: u32,
    #[bits(2)]
    pub imm2_10: u32,
    #[bits(1)]
    pub _op_12: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMLA_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2 {
    #[bits(3)]
    pub imm3_0: u32,
    #[bits(4)]
    pub _op_3: u32,
    #[bits(3)]
    pub sme_zn4: u32,
    #[bits(2)]
    pub imm2_10: u32,
    #[bits(1)]
    pub _op_12: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMLA_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX1 {
    #[bits(3)]
    pub imm3_0: u32,
    #[bits(3)]
    pub _op_3: u32,
    #[bits(4)]
    pub sme_zn2: u32,
    #[bits(1)]
    pub imm1_10: u32,
    #[bits(2)]
    pub _op_11: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMLA_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX1 {
    #[bits(3)]
    pub imm3_0: u32,
    #[bits(4)]
    pub _op_3: u32,
    #[bits(3)]
    pub sme_zn4: u32,
    #[bits(1)]
    pub imm1_10: u32,
    #[bits(2)]
    pub _op_11: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMLA_SME_ZA_array_off3_0_SVE_ZnxN_SME_Zm {
    #[bits(3)]
    pub imm3_0: u32,
    #[bits(2)]
    pub _op_3: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMLA_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_S_SME_Zm_S_S {
    #[bits(3)]
    pub imm3_0: u32,
    #[bits(2)]
    pub _op_3: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMLA_SME_ZA_array_off3_0_SME_Znx2_SME_Zmx2 {
    #[bits(3)]
    pub imm3_0: u32,
    #[bits(3)]
    pub _op_3: u32,
    #[bits(4)]
    pub sme_zn2: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(2)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm2: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMLA_SME_ZA_array_off3_0_SME_Znx4_SME_Zmx4 {
    #[bits(3)]
    pub imm3_0: u32,
    #[bits(4)]
    pub _op_3: u32,
    #[bits(3)]
    pub sme_zn4: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(3)]
    pub _op_15: u32,
    #[bits(3)]
    pub sme_zm4: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMLA_SVE_Zd_SVE_Zn_SVE_Zm3_22_INDEX {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(1)]
    pub _op_21: u32,
    #[bits(1)]
    pub sve_i3h: u32,
    #[bits(9)]
    pub _op_23: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMLA_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMLA_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMLA_SVE_Zd_SVE_Pg3_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMLA_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMLA_Vd_V_2S_Vn_V_2S_Vm_V_2S {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMLA_Vd_Vn_Em16 {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMLA_Vd_Vn_Em {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMLA_Sd_Sn_Em16 {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMLA_Sd_Sn_Em {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMLAL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm_INDEX3_10 {
    #[bits(3)]
    pub imm3_0: u32,
    #[bits(2)]
    pub _op_3: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(2)]
    pub imm2_10: u32,
    #[bits(1)]
    pub _op_12: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub imm1_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMLAL_SME_ZA_array_off2x2_SME_Znx2_SME_Zm_INDEX3_2 {
    #[bits(2)]
    pub imm2_0: u32,
    #[bits(1)]
    pub imm1_2: u32,
    #[bits(3)]
    pub _op_3: u32,
    #[bits(4)]
    pub sme_zn2: u32,
    #[bits(2)]
    pub imm2_10: u32,
    #[bits(1)]
    pub _op_12: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMLAL_SME_ZA_array_off2x2_SME_Znx4_SME_Zm_INDEX3_2 {
    #[bits(2)]
    pub imm2_0: u32,
    #[bits(1)]
    pub imm1_2: u32,
    #[bits(4)]
    pub _op_3: u32,
    #[bits(3)]
    pub sme_zn4: u32,
    #[bits(2)]
    pub imm2_10: u32,
    #[bits(1)]
    pub _op_12: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMLAL_SME_ZA_array_off2x2_SVE_ZnxN_SME_Zm {
    #[bits(2)]
    pub imm2_0: u32,
    #[bits(3)]
    pub _op_2: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMLAL_SME_ZA_array_off2x2_S_S_SVE_ZnxN_S_H_SME_Zm_S_H {
    #[bits(2)]
    pub imm2_0: u32,
    #[bits(3)]
    pub _op_2: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMLAL_SME_ZA_array_off2x2_SME_Znx2_SME_Zmx2 {
    #[bits(2)]
    pub imm2_0: u32,
    #[bits(4)]
    pub _op_2: u32,
    #[bits(4)]
    pub sme_zn2: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(2)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm2: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMLAL_SME_ZA_array_off2x2_SME_Znx4_SME_Zmx4 {
    #[bits(2)]
    pub imm2_0: u32,
    #[bits(5)]
    pub _op_2: u32,
    #[bits(3)]
    pub sme_zn4: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(3)]
    pub _op_15: u32,
    #[bits(3)]
    pub sme_zm4: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMLAL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm {
    #[bits(3)]
    pub imm3_0: u32,
    #[bits(2)]
    pub _op_3: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMLAL_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMLAL_Vd_V_4S_Vn_V_4H_Vm_V_4H {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMLAL_Vd_Vn_Em16 {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMLAL_Vd_V_4S_Vn_V_4H_Em16_S_H {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMLAL2_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMLAL2_Vd_V_4S_Vn_V_4H_Vm_V_4H {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMLAL2_Vd_Vn_Em16 {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMLAL2_Vd_V_4S_Vn_V_4H_Em16_S_H {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMLALB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(1)]
    pub _op_10: u32,
    #[bits(1)]
    pub sve_i3l: u32,
    #[bits(4)]
    pub _op_12: u32,
    #[bits(3)]
    pub sve_imm3: u32,
    #[bits(2)]
    pub sve_i3h2: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMLALB_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMLALT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(1)]
    pub _op_10: u32,
    #[bits(1)]
    pub sve_i3l: u32,
    #[bits(4)]
    pub _op_12: u32,
    #[bits(3)]
    pub sve_imm3: u32,
    #[bits(2)]
    pub sve_i3h2: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMLALT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMLS_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2 {
    #[bits(3)]
    pub imm3_0: u32,
    #[bits(3)]
    pub _op_3: u32,
    #[bits(4)]
    pub sme_zn2: u32,
    #[bits(2)]
    pub imm2_10: u32,
    #[bits(1)]
    pub _op_12: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMLS_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2 {
    #[bits(3)]
    pub imm3_0: u32,
    #[bits(4)]
    pub _op_3: u32,
    #[bits(3)]
    pub sme_zn4: u32,
    #[bits(2)]
    pub imm2_10: u32,
    #[bits(1)]
    pub _op_12: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMLS_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX1 {
    #[bits(3)]
    pub imm3_0: u32,
    #[bits(3)]
    pub _op_3: u32,
    #[bits(4)]
    pub sme_zn2: u32,
    #[bits(1)]
    pub imm1_10: u32,
    #[bits(2)]
    pub _op_11: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMLS_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX1 {
    #[bits(3)]
    pub imm3_0: u32,
    #[bits(4)]
    pub _op_3: u32,
    #[bits(3)]
    pub sme_zn4: u32,
    #[bits(1)]
    pub imm1_10: u32,
    #[bits(2)]
    pub _op_11: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMLS_SME_ZA_array_off3_0_SVE_ZnxN_SME_Zm {
    #[bits(3)]
    pub imm3_0: u32,
    #[bits(2)]
    pub _op_3: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMLS_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_S_SME_Zm_S_S {
    #[bits(3)]
    pub imm3_0: u32,
    #[bits(2)]
    pub _op_3: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMLS_SME_ZA_array_off3_0_SME_Znx2_SME_Zmx2 {
    #[bits(3)]
    pub imm3_0: u32,
    #[bits(3)]
    pub _op_3: u32,
    #[bits(4)]
    pub sme_zn2: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(2)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm2: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMLS_SME_ZA_array_off3_0_SME_Znx4_SME_Zmx4 {
    #[bits(3)]
    pub imm3_0: u32,
    #[bits(4)]
    pub _op_3: u32,
    #[bits(3)]
    pub sme_zn4: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(3)]
    pub _op_15: u32,
    #[bits(3)]
    pub sme_zm4: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMLS_SVE_Zd_SVE_Zn_SVE_Zm3_22_INDEX {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(1)]
    pub _op_21: u32,
    #[bits(1)]
    pub sve_i3h: u32,
    #[bits(9)]
    pub _op_23: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMLS_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMLS_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMLS_SVE_Zd_SVE_Pg3_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMLS_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMLS_Vd_V_2S_Vn_V_2S_Vm_V_2S {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMLS_Vd_Vn_Em16 {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMLS_Vd_Vn_Em {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMLS_Sd_Sn_Em16 {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMLS_Sd_Sn_Em {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMLSL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm_INDEX3_10 {
    #[bits(3)]
    pub imm3_0: u32,
    #[bits(2)]
    pub _op_3: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(2)]
    pub imm2_10: u32,
    #[bits(1)]
    pub _op_12: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub imm1_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMLSL_SME_ZA_array_off2x2_SME_Znx2_SME_Zm_INDEX3_2 {
    #[bits(2)]
    pub imm2_0: u32,
    #[bits(1)]
    pub imm1_2: u32,
    #[bits(3)]
    pub _op_3: u32,
    #[bits(4)]
    pub sme_zn2: u32,
    #[bits(2)]
    pub imm2_10: u32,
    #[bits(1)]
    pub _op_12: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMLSL_SME_ZA_array_off2x2_SME_Znx4_SME_Zm_INDEX3_2 {
    #[bits(2)]
    pub imm2_0: u32,
    #[bits(1)]
    pub imm1_2: u32,
    #[bits(4)]
    pub _op_3: u32,
    #[bits(3)]
    pub sme_zn4: u32,
    #[bits(2)]
    pub imm2_10: u32,
    #[bits(1)]
    pub _op_12: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMLSL_SME_ZA_array_off2x2_SVE_ZnxN_SME_Zm {
    #[bits(2)]
    pub imm2_0: u32,
    #[bits(3)]
    pub _op_2: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMLSL_SME_ZA_array_off2x2_S_S_SVE_ZnxN_S_H_SME_Zm_S_H {
    #[bits(2)]
    pub imm2_0: u32,
    #[bits(3)]
    pub _op_2: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMLSL_SME_ZA_array_off2x2_SME_Znx2_SME_Zmx2 {
    #[bits(2)]
    pub imm2_0: u32,
    #[bits(4)]
    pub _op_2: u32,
    #[bits(4)]
    pub sme_zn2: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(2)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm2: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMLSL_SME_ZA_array_off2x2_SME_Znx4_SME_Zmx4 {
    #[bits(2)]
    pub imm2_0: u32,
    #[bits(5)]
    pub _op_2: u32,
    #[bits(3)]
    pub sme_zn4: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(3)]
    pub _op_15: u32,
    #[bits(3)]
    pub sme_zm4: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMLSL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm {
    #[bits(3)]
    pub imm3_0: u32,
    #[bits(2)]
    pub _op_3: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMLSL_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMLSL_Vd_V_4S_Vn_V_4H_Vm_V_4H {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMLSL_Vd_Vn_Em16 {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMLSL_Vd_V_4S_Vn_V_4H_Em16_S_H {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMLSL2_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMLSL2_Vd_V_4S_Vn_V_4H_Vm_V_4H {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMLSL2_Vd_Vn_Em16 {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMLSL2_Vd_V_4S_Vn_V_4H_Em16_S_H {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMLSLB_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMLSLB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(1)]
    pub _op_10: u32,
    #[bits(1)]
    pub sve_i3l: u32,
    #[bits(4)]
    pub _op_12: u32,
    #[bits(3)]
    pub sve_imm3: u32,
    #[bits(2)]
    pub sve_i3h2: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMLSLT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMLSLT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(1)]
    pub _op_10: u32,
    #[bits(1)]
    pub sve_i3l: u32,
    #[bits(4)]
    pub _op_12: u32,
    #[bits(3)]
    pub sve_imm3: u32,
    #[bits(2)]
    pub sve_i3h2: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMMLA_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMMLA_SVE_Zd_S_D_SVE_Zn_S_D_SVE_Zm_16_S_D {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMOPA_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16 {
    #[bits(2)]
    pub sme_zada_2b: u32,
    #[bits(3)]
    pub _op_2: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub sme_pm: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMOPA_SME_ZAda_3b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16 {
    #[bits(3)]
    pub sme_zada_3b: u32,
    #[bits(2)]
    pub _op_3: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub sme_pm: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMOPA_SME_ZAda_2b_S_S_SVE_Pg3_P_M_SME_Pm_P_M_SVE_Zn_S_H_SVE_Zm_16_S_H {
    #[bits(2)]
    pub sme_zada_2b: u32,
    #[bits(3)]
    pub _op_2: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub sme_pm: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMOPS_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16 {
    #[bits(2)]
    pub sme_zada_2b: u32,
    #[bits(3)]
    pub _op_2: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub sme_pm: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMOPS_SME_ZAda_3b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16 {
    #[bits(3)]
    pub sme_zada_3b: u32,
    #[bits(2)]
    pub _op_3: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub sme_pm: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMOPS_SME_ZAda_2b_S_S_SVE_Pg3_P_M_SME_Pm_P_M_SVE_Zn_S_H_SVE_Zm_16_S_H {
    #[bits(2)]
    pub sme_zada_2b: u32,
    #[bits(3)]
    pub _op_2: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub sme_pm: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMOV_Rd_Fn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMOV_Rd_W_Fn_S_S {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMOV_Rd_VnD1 {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMOV_Fd_Rn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMOV_Fd_S_S_Rn_W {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMOV_VdD1_Rn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMOV_Fd_Fn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMOV_Fd_S_S_Fn_S_S {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMOV_Fd_FPIMM {
    #[bits(5)]
    pub rd: u32,
    #[bits(8)]
    pub _op_5: u32,
    #[bits(8)]
    pub imm8: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMOV_Fd_S_S_FPIMM {
    #[bits(5)]
    pub rd: u32,
    #[bits(8)]
    pub _op_5: u32,
    #[bits(8)]
    pub imm8: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMOV_Vd_SIMD_FPIMM {
    #[bits(5)]
    pub rd: u32,
    #[bits(27)]
    pub _op_5: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMOV_Vd_V_2D_SIMD_FPIMM {
    #[bits(5)]
    pub rd: u32,
    #[bits(27)]
    pub _op_5: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMOV_Vd_V_4H_SIMD_FPIMM {
    #[bits(5)]
    pub rd: u32,
    #[bits(27)]
    pub _op_5: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMSB_SVE_Zd_SVE_Pg3_SVE_Zm_5_SVE_Za_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zm_5: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub sve_za_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMSUB_Fd_Fn_Fm_Fa {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(5)]
    pub ra: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMSUB_Fd_S_S_Fn_S_S_Fm_S_S_Fa_S_S {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(5)]
    pub ra: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMUL_SVE_Zd_SVE_Zn_SVE_Zm3_22_INDEX {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(1)]
    pub _op_21: u32,
    #[bits(1)]
    pub sve_i3h: u32,
    #[bits(9)]
    pub _op_23: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMUL_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMUL_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMUL_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMUL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zm_5: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMUL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_I1_HALF_TWO {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(1)]
    pub sve_i1: u32,
    #[bits(4)]
    pub _op_6: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMUL_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMUL_Vd_V_2S_Vn_V_2S_Vm_V_2S {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMUL_Fd_Fn_Fm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMUL_Fd_S_S_Fn_S_S_Fm_S_S {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMUL_Vd_Vn_Em16 {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMUL_Vd_Vn_Em {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMUL_Sd_Sn_Em16 {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMUL_Sd_Sn_Em {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMULX_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zm_5: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMULX_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMULX_Sd_Sn_Sm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMULX_Vd_V_2S_Vn_V_2S_Vm_V_2S {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMULX_Sd_S_S_Sn_S_S_Sm_S_S {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMULX_Vd_Vn_Em16 {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMULX_Vd_Vn_Em {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMULX_Sd_Sn_Em16 {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FMULX_Sd_Sn_Em {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FNEG_SVE_Zd_SVE_Pg3_SVE_Zn {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FNEG_Vd_Vn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FNEG_Vd_V_4H_Vn_V_4H {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FNEG_Fd_Fn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FNEG_Fd_S_S_Fn_S_S {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FNMAD_SVE_Zd_SVE_Pg3_SVE_Zm_5_SVE_Za_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zm_5: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub sve_za_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FNMADD_Fd_Fn_Fm_Fa {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(5)]
    pub ra: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FNMADD_Fd_S_S_Fn_S_S_Fm_S_S_Fa_S_S {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(5)]
    pub ra: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FNMLA_SVE_Zd_SVE_Pg3_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FNMLS_SVE_Zd_SVE_Pg3_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FNMSB_SVE_Zd_SVE_Pg3_SVE_Zm_5_SVE_Za_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zm_5: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub sve_za_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FNMSUB_Fd_Fn_Fm_Fa {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(5)]
    pub ra: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FNMSUB_Fd_S_S_Fn_S_S_Fm_S_S_Fa_S_S {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(5)]
    pub ra: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FNMUL_Fd_Fn_Fm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FNMUL_Fd_S_S_Fn_S_S_Fm_S_S {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FRECPE_SVE_Zd_SVE_Zn {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FRECPE_Vd_Vn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FRECPE_Vd_V_4H_Vn_V_4H {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FRECPE_Sd_Sn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FRECPE_Sd_S_H_Sn_S_H {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FRECPS_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FRECPS_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FRECPS_Sd_Sn_Sm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FRECPS_Vd_V_2S_Vn_V_2S_Vm_V_2S {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FRECPS_Sd_S_S_Sn_S_S_Sm_S_S {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FRECPX_SVE_Zd_SVE_Pg3_SVE_Zn {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FRECPX_Sd_Sn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FRECPX_Sd_S_H_Sn_S_H {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FRINT32X_Vd_Vn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FRINT32X_Fd_Fn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FRINT32Z_Vd_Vn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FRINT32Z_Fd_Fn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FRINT64X_Vd_Vn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FRINT64X_Fd_Fn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FRINT64Z_Vd_Vn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FRINT64Z_Fd_Fn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FRINTA_SME_Zdnx2_SME_Znx2 {
    #[bits(1)]
    pub _op_0: u32,
    #[bits(4)]
    pub sme_zdn2: u32,
    #[bits(1)]
    pub _op_5: u32,
    #[bits(4)]
    pub sme_zn2: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FRINTA_SME_Zdnx4_SME_Znx4 {
    #[bits(2)]
    pub _op_0: u32,
    #[bits(3)]
    pub sme_zdn4: u32,
    #[bits(2)]
    pub _op_5: u32,
    #[bits(3)]
    pub sme_zn4: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FRINTA_SVE_Zd_SVE_Pg3_SVE_Zn {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FRINTA_Vd_Vn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FRINTA_Vd_V_4H_Vn_V_4H {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FRINTA_Fd_Fn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FRINTA_Fd_S_S_Fn_S_S {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FRINTI_SVE_Zd_SVE_Pg3_SVE_Zn {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FRINTI_Vd_Vn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FRINTI_Vd_V_4H_Vn_V_4H {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FRINTI_Fd_Fn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FRINTI_Fd_S_S_Fn_S_S {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FRINTM_SME_Zdnx2_SME_Znx2 {
    #[bits(1)]
    pub _op_0: u32,
    #[bits(4)]
    pub sme_zdn2: u32,
    #[bits(1)]
    pub _op_5: u32,
    #[bits(4)]
    pub sme_zn2: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FRINTM_SME_Zdnx4_SME_Znx4 {
    #[bits(2)]
    pub _op_0: u32,
    #[bits(3)]
    pub sme_zdn4: u32,
    #[bits(2)]
    pub _op_5: u32,
    #[bits(3)]
    pub sme_zn4: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FRINTM_SVE_Zd_SVE_Pg3_SVE_Zn {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FRINTM_Vd_Vn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FRINTM_Vd_V_4H_Vn_V_4H {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FRINTM_Fd_Fn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FRINTM_Fd_S_S_Fn_S_S {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FRINTN_SME_Zdnx2_SME_Znx2 {
    #[bits(1)]
    pub _op_0: u32,
    #[bits(4)]
    pub sme_zdn2: u32,
    #[bits(1)]
    pub _op_5: u32,
    #[bits(4)]
    pub sme_zn2: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FRINTN_SME_Zdnx4_SME_Znx4 {
    #[bits(2)]
    pub _op_0: u32,
    #[bits(3)]
    pub sme_zdn4: u32,
    #[bits(2)]
    pub _op_5: u32,
    #[bits(3)]
    pub sme_zn4: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FRINTN_SVE_Zd_SVE_Pg3_SVE_Zn {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FRINTN_Vd_Vn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FRINTN_Vd_V_4H_Vn_V_4H {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FRINTN_Fd_Fn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FRINTN_Fd_S_S_Fn_S_S {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FRINTP_SME_Zdnx2_SME_Znx2 {
    #[bits(1)]
    pub _op_0: u32,
    #[bits(4)]
    pub sme_zdn2: u32,
    #[bits(1)]
    pub _op_5: u32,
    #[bits(4)]
    pub sme_zn2: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FRINTP_SME_Zdnx4_SME_Znx4 {
    #[bits(2)]
    pub _op_0: u32,
    #[bits(3)]
    pub sme_zdn4: u32,
    #[bits(2)]
    pub _op_5: u32,
    #[bits(3)]
    pub sme_zn4: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FRINTP_SVE_Zd_SVE_Pg3_SVE_Zn {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FRINTP_Vd_Vn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FRINTP_Vd_V_4H_Vn_V_4H {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FRINTP_Fd_Fn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FRINTP_Fd_S_S_Fn_S_S {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FRINTX_SVE_Zd_SVE_Pg3_SVE_Zn {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FRINTX_Vd_Vn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FRINTX_Vd_V_4H_Vn_V_4H {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FRINTX_Fd_Fn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FRINTX_Fd_S_S_Fn_S_S {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FRINTZ_SVE_Zd_SVE_Pg3_SVE_Zn {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FRINTZ_Vd_Vn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FRINTZ_Vd_V_4H_Vn_V_4H {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FRINTZ_Fd_Fn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FRINTZ_Fd_S_S_Fn_S_S {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FRSQRTE_SVE_Zd_SVE_Zn {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FRSQRTE_Vd_Vn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FRSQRTE_Vd_V_4H_Vn_V_4H {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FRSQRTE_Sd_Sn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FRSQRTE_Sd_S_H_Sn_S_H {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FRSQRTS_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FRSQRTS_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FRSQRTS_Sd_Sn_Sm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FRSQRTS_Vd_V_2S_Vn_V_2S_Vm_V_2S {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FRSQRTS_Sd_S_S_Sn_S_S_Sm_S_S {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FSCALE_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zm_5: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FSQRT_SVE_Zd_SVE_Pg3_SVE_Zn {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FSQRT_Vd_Vn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FSQRT_Vd_V_4H_Vn_V_4H {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FSQRT_Fd_Fn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FSQRT_Fd_S_S_Fn_S_S {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FSUB_SME_ZA_array_off3_0_SME_Znx2 {
    #[bits(3)]
    pub imm3_0: u32,
    #[bits(3)]
    pub _op_3: u32,
    #[bits(4)]
    pub sme_zn2: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(17)]
    pub _op_15: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FSUB_SME_ZA_array_off3_0_SME_Znx4 {
    #[bits(3)]
    pub imm3_0: u32,
    #[bits(4)]
    pub _op_3: u32,
    #[bits(3)]
    pub sme_zn4: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(17)]
    pub _op_15: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FSUB_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FSUB_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zm_5: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FSUB_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_I1_HALF_ONE {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(1)]
    pub sve_i1: u32,
    #[bits(4)]
    pub _op_6: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FSUB_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FSUB_Vd_V_2S_Vn_V_2S_Vm_V_2S {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FSUB_Fd_Fn_Fm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FSUB_Fd_S_S_Fn_S_S_Fm_S_S {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FSUBR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zm_5: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FSUBR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_I1_HALF_ONE {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(1)]
    pub sve_i1: u32,
    #[bits(4)]
    pub _op_6: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FTMAD_SVE_Zd_SVE_Zd_SVE_Zm_5_SVE_UIMM3 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zm_5: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(3)]
    pub sve_imm3: u32,
    #[bits(13)]
    pub _op_19: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FTSMUL_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FTSSEL_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct FVDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2 {
    #[bits(3)]
    pub imm3_0: u32,
    #[bits(3)]
    pub _op_3: u32,
    #[bits(4)]
    pub sme_zn2: u32,
    #[bits(2)]
    pub imm2_10: u32,
    #[bits(1)]
    pub _op_12: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct GCSPOPCX {
    #[bits(32)]
    pub _op_0: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct GCSPOPM {
    #[bits(32)]
    pub _op_0: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct GCSPOPM_Rt {
    #[bits(5)]
    pub rt: u32,
    #[bits(27)]
    pub _op_5: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct GCSPOPX {
    #[bits(32)]
    pub _op_0: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct GCSPUSHM_Rt {
    #[bits(5)]
    pub rt: u32,
    #[bits(27)]
    pub _op_5: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct GCSPUSHX {
    #[bits(32)]
    pub _op_0: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct GCSSS1_Rt {
    #[bits(5)]
    pub rt: u32,
    #[bits(27)]
    pub _op_5: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct GCSSS2_Rt {
    #[bits(5)]
    pub rt: u32,
    #[bits(27)]
    pub _op_5: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct GCSSTR_Rt_Rn_SP {
    #[bits(5)]
    pub rt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct GCSSTTR_Rt_Rn_SP {
    #[bits(5)]
    pub rt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct GMI_Rd_Rn_SP_Rm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct HINT_UIMM7 {
    #[bits(5)]
    pub _op_0: u32,
    #[bits(3)]
    pub op2: u32,
    #[bits(4)]
    pub crm: u32,
    #[bits(20)]
    pub _op_12: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct HISTCNT_SVE_Zd_SVE_Pg3_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct HISTSEG_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct HLT_EXCEPTION {
    #[bits(5)]
    pub _op_0: u32,
    #[bits(16)]
    pub imm16_5: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct HVC_EXCEPTION {
    #[bits(5)]
    pub _op_0: u32,
    #[bits(16)]
    pub imm16_5: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct INCB_Rd_SVE_PATTERN_SCALED {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub sve_pattern: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct INCD_SVE_Zd_SVE_PATTERN_SCALED {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_pattern: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct INCD_Rd_SVE_PATTERN_SCALED {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub sve_pattern: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct INCH_SVE_Zd_SVE_PATTERN_SCALED {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_pattern: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct INCH_Rd_SVE_PATTERN_SCALED {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub sve_pattern: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct INCP_SVE_Zd_SVE_Pg4_5 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(4)]
    pub sve_pg4_5: u32,
    #[bits(23)]
    pub _op_9: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct INCP_Rd_SVE_Pg4_5 {
    #[bits(5)]
    pub rd: u32,
    #[bits(4)]
    pub sve_pg4_5: u32,
    #[bits(23)]
    pub _op_9: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct INCW_SVE_Zd_SVE_PATTERN_SCALED {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_pattern: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct INCW_Rd_SVE_PATTERN_SCALED {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub sve_pattern: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct INDEX_SVE_Zd_SVE_SIMM5_SVE_SIMM5B {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_imm5: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_imm5b: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct INDEX_SVE_Zd_Rn_SIMM5 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub imm5: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct INDEX_SVE_Zd_SVE_SIMM5_Rm {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_imm5: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct INDEX_SVE_Zd_Rn_Rm {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct INS_Ed_Rn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct INS_Ed_En {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct INSR_SVE_Zd_SVE_Rm {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_rm: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct INSR_SVE_Zd_SVE_Vm {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_vm: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct IRG_Rd_SP_Rn_SP_Rm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ISB_BARRIER_ISB {
    #[bits(32)]
    pub _op_0: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LASTA_SVE_Vd_SVE_Pg3_SVE_Zn {
    #[bits(5)]
    pub sve_vd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LASTA_Rd_SVE_Pg3_SVE_Zn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LASTB_SVE_Vd_SVE_Pg3_SVE_Zn {
    #[bits(5)]
    pub sve_vd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LASTB_Rd_SVE_Pg3_SVE_Zn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1_LVt_SIMD_ADDR_SIMPLE {
    #[bits(32)]
    pub _op_0: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1_LEt_SIMD_ADDR_SIMPLE {
    #[bits(32)]
    pub _op_0: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1_LVt_SIMD_ADDR_POST {
    #[bits(32)]
    pub _op_0: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1_LEt_SIMD_ADDR_POST {
    #[bits(32)]
    pub _op_0: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1B_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR {
    #[bits(1)]
    pub _op_0: u32,
    #[bits(4)]
    pub sme_zdn2: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1B_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR {
    #[bits(2)]
    pub _op_0: u32,
    #[bits(3)]
    pub sme_zdn4: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1B_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_RR {
    #[bits(4)]
    pub imm4_0: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub sme_v: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(1)]
    pub _op_21: u32,
    #[bits(2)]
    pub sme_size_22: u32,
    #[bits(1)]
    pub index2: u32,
    #[bits(7)]
    pub _op_25: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1B_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_R {
    #[bits(4)]
    pub imm4_0: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub sme_v: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(1)]
    pub _op_21: u32,
    #[bits(2)]
    pub sme_size_22: u32,
    #[bits(1)]
    pub index2: u32,
    #[bits(7)]
    pub _op_25: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1B_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL {
    #[bits(1)]
    pub _op_0: u32,
    #[bits(4)]
    pub sme_zdn2: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1B_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL {
    #[bits(2)]
    pub _op_0: u32,
    #[bits(3)]
    pub sme_zdn4: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1B_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR {
    #[bits(3)]
    pub sme_zt3: u32,
    #[bits(1)]
    pub _op_3: u32,
    #[bits(1)]
    pub sme_ztt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1B_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR {
    #[bits(2)]
    pub sme_zt2: u32,
    #[bits(2)]
    pub _op_2: u32,
    #[bits(1)]
    pub sme_ztt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1B_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL {
    #[bits(3)]
    pub sme_zt3: u32,
    #[bits(1)]
    pub _op_3: u32,
    #[bits(1)]
    pub sme_ztt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1B_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL {
    #[bits(2)]
    pub sme_zt2: u32,
    #[bits(2)]
    pub _op_2: u32,
    #[bits(1)]
    pub sme_ztt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(1)]
    pub _op_21: u32,
    #[bits(1)]
    pub sve_xs_22: u32,
    #[bits(9)]
    pub _op_23: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1B_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW_22_S_D {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(1)]
    pub _op_21: u32,
    #[bits(1)]
    pub sve_xs_22: u32,
    #[bits(9)]
    pub _op_23: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1B_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_ZI_U5_S_D {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1B_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RX {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1B_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1B_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RX {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1B_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RX {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1B_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1B_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1D_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR_LSL3 {
    #[bits(1)]
    pub _op_0: u32,
    #[bits(4)]
    pub sme_zdn2: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1D_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR_LSL3 {
    #[bits(2)]
    pub _op_0: u32,
    #[bits(3)]
    pub sme_zdn4: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1D_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL {
    #[bits(1)]
    pub _op_0: u32,
    #[bits(4)]
    pub sme_zdn2: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1D_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL {
    #[bits(2)]
    pub _op_0: u32,
    #[bits(3)]
    pub sme_zdn4: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1D_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_RR_LSL3 {
    #[bits(4)]
    pub imm4_0: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub sme_v: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(1)]
    pub _op_21: u32,
    #[bits(2)]
    pub sme_size_22: u32,
    #[bits(1)]
    pub index2: u32,
    #[bits(7)]
    pub _op_25: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1D_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_R {
    #[bits(4)]
    pub imm4_0: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub sme_v: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(1)]
    pub _op_21: u32,
    #[bits(2)]
    pub sme_size_22: u32,
    #[bits(1)]
    pub index2: u32,
    #[bits(7)]
    pub _op_25: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1D_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL3 {
    #[bits(3)]
    pub sme_zt3: u32,
    #[bits(1)]
    pub _op_3: u32,
    #[bits(1)]
    pub sme_ztt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1D_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL3 {
    #[bits(2)]
    pub sme_zt2: u32,
    #[bits(2)]
    pub _op_2: u32,
    #[bits(1)]
    pub sme_ztt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1D_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL {
    #[bits(3)]
    pub sme_zt3: u32,
    #[bits(1)]
    pub _op_3: u32,
    #[bits(1)]
    pub sme_ztt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1D_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL {
    #[bits(2)]
    pub sme_zt2: u32,
    #[bits(2)]
    pub _op_2: u32,
    #[bits(1)]
    pub sme_ztt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(1)]
    pub _op_21: u32,
    #[bits(1)]
    pub sve_xs_22: u32,
    #[bits(9)]
    pub _op_23: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW3_22 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(1)]
    pub _op_21: u32,
    #[bits(1)]
    pub sve_xs_22: u32,
    #[bits(9)]
    pub _op_23: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x8 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL3 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL3 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1H_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR_LSL1 {
    #[bits(1)]
    pub _op_0: u32,
    #[bits(4)]
    pub sme_zdn2: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1H_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR_LSL1 {
    #[bits(2)]
    pub _op_0: u32,
    #[bits(3)]
    pub sme_zdn4: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1H_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL {
    #[bits(1)]
    pub _op_0: u32,
    #[bits(4)]
    pub sme_zdn2: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1H_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL {
    #[bits(2)]
    pub _op_0: u32,
    #[bits(3)]
    pub sme_zdn4: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1H_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_RR_LSL1 {
    #[bits(4)]
    pub imm4_0: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub sme_v: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(1)]
    pub _op_21: u32,
    #[bits(2)]
    pub sme_size_22: u32,
    #[bits(1)]
    pub index2: u32,
    #[bits(7)]
    pub _op_25: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1H_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_R {
    #[bits(4)]
    pub imm4_0: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub sme_v: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(1)]
    pub _op_21: u32,
    #[bits(2)]
    pub sme_size_22: u32,
    #[bits(1)]
    pub index2: u32,
    #[bits(7)]
    pub _op_25: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1H_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL1 {
    #[bits(3)]
    pub sme_zt3: u32,
    #[bits(1)]
    pub _op_3: u32,
    #[bits(1)]
    pub sme_ztt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1H_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL1 {
    #[bits(2)]
    pub sme_zt2: u32,
    #[bits(2)]
    pub _op_2: u32,
    #[bits(1)]
    pub sme_ztt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1H_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL {
    #[bits(3)]
    pub sme_zt3: u32,
    #[bits(1)]
    pub _op_3: u32,
    #[bits(1)]
    pub sme_ztt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1H_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL {
    #[bits(2)]
    pub sme_zt2: u32,
    #[bits(2)]
    pub _op_2: u32,
    #[bits(1)]
    pub sme_ztt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(1)]
    pub _op_21: u32,
    #[bits(1)]
    pub sve_xs_22: u32,
    #[bits(9)]
    pub _op_23: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1H_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW_22_S_D {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(1)]
    pub _op_21: u32,
    #[bits(1)]
    pub sve_xs_22: u32,
    #[bits(9)]
    pub _op_23: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW1_22 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(1)]
    pub _op_21: u32,
    #[bits(1)]
    pub sve_xs_22: u32,
    #[bits(9)]
    pub _op_23: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1H_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW1_22_S_D {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(1)]
    pub _op_21: u32,
    #[bits(1)]
    pub sve_xs_22: u32,
    #[bits(9)]
    pub _op_23: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x2 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1H_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_ZI_U5x2_S_D {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL1 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1H_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RX_LSL1 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1H_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RX_LSL1 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1H_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1H_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1Q_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_RR_LSL4 {
    #[bits(4)]
    pub imm4_0: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub sme_v: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(1)]
    pub _op_21: u32,
    #[bits(2)]
    pub sme_size_22: u32,
    #[bits(1)]
    pub index2: u32,
    #[bits(7)]
    pub _op_25: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1Q_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_R {
    #[bits(4)]
    pub imm4_0: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub sme_v: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(1)]
    pub _op_21: u32,
    #[bits(2)]
    pub sme_size_22: u32,
    #[bits(1)]
    pub index2: u32,
    #[bits(7)]
    pub _op_25: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1Q_SVE_Zt_SVE_Pg3_SVE_ADDR_ZX {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1R_LVt_AL_SIMD_ADDR_SIMPLE {
    #[bits(32)]
    pub _op_0: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1R_LVt_AL_SIMD_ADDR_POST {
    #[bits(32)]
    pub _op_0: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1RB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_U6 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1RB_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RI_U6 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1RB_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RI_U6 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1RB_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RI_U6 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1RD_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_U6x8 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1RH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_U6x2 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1RH_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RI_U6x2 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1RH_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RI_U6x2 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1ROB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1ROB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x32 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1ROD_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL3 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1ROD_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x32 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1ROH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1ROH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x32 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1ROW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1ROW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x32 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1RQB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1RQB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x16 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1RQD_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL3 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1RQD_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x16 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1RQH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1RQH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x16 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1RQW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1RQW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x16 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1RSB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_U6 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1RSB_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RI_U6 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1RSB_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RI_U6 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1RSH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_U6x2 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1RSH_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RI_U6x2 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1RSW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_U6x4 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1RW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_U6x4 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1RW_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RI_U6x4 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1SB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(1)]
    pub _op_21: u32,
    #[bits(1)]
    pub sve_xs_22: u32,
    #[bits(9)]
    pub _op_23: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1SB_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW_22_S_D {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(1)]
    pub _op_21: u32,
    #[bits(1)]
    pub sve_xs_22: u32,
    #[bits(9)]
    pub _op_23: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1SB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1SB_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_ZI_U5_S_D {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1SB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1SB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1SB_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RX {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1SB_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RX {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1SB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1SB_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1SB_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(1)]
    pub _op_21: u32,
    #[bits(1)]
    pub sve_xs_22: u32,
    #[bits(9)]
    pub _op_23: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1SH_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW_22_S_D {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(1)]
    pub _op_21: u32,
    #[bits(1)]
    pub sve_xs_22: u32,
    #[bits(9)]
    pub _op_23: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW1_22 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(1)]
    pub _op_21: u32,
    #[bits(1)]
    pub sve_xs_22: u32,
    #[bits(9)]
    pub _op_23: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1SH_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW1_22_S_D {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(1)]
    pub _op_21: u32,
    #[bits(1)]
    pub sve_xs_22: u32,
    #[bits(9)]
    pub _op_23: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x2 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1SH_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_ZI_U5x2_S_D {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL1 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1SH_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RX_LSL1 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1SH_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(1)]
    pub _op_21: u32,
    #[bits(1)]
    pub sve_xs_22: u32,
    #[bits(9)]
    pub _op_23: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW2_22 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(1)]
    pub _op_21: u32,
    #[bits(1)]
    pub sve_xs_22: u32,
    #[bits(9)]
    pub _op_23: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x4 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL2 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1W_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR_LSL2 {
    #[bits(1)]
    pub _op_0: u32,
    #[bits(4)]
    pub sme_zdn2: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1W_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR_LSL2 {
    #[bits(2)]
    pub _op_0: u32,
    #[bits(3)]
    pub sme_zdn4: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1W_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_RR_LSL2 {
    #[bits(4)]
    pub imm4_0: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub sme_v: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(1)]
    pub _op_21: u32,
    #[bits(2)]
    pub sme_size_22: u32,
    #[bits(1)]
    pub index2: u32,
    #[bits(7)]
    pub _op_25: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1W_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_R {
    #[bits(4)]
    pub imm4_0: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub sme_v: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(1)]
    pub _op_21: u32,
    #[bits(2)]
    pub sme_size_22: u32,
    #[bits(1)]
    pub index2: u32,
    #[bits(7)]
    pub _op_25: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1W_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL {
    #[bits(1)]
    pub _op_0: u32,
    #[bits(4)]
    pub sme_zdn2: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1W_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL {
    #[bits(2)]
    pub _op_0: u32,
    #[bits(3)]
    pub sme_zdn4: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1W_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL2 {
    #[bits(3)]
    pub sme_zt3: u32,
    #[bits(1)]
    pub _op_3: u32,
    #[bits(1)]
    pub sme_ztt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1W_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL2 {
    #[bits(2)]
    pub sme_zt2: u32,
    #[bits(2)]
    pub _op_2: u32,
    #[bits(1)]
    pub sme_ztt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1W_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL {
    #[bits(3)]
    pub sme_zt3: u32,
    #[bits(1)]
    pub _op_3: u32,
    #[bits(1)]
    pub sme_ztt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1W_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL {
    #[bits(2)]
    pub sme_zt2: u32,
    #[bits(2)]
    pub _op_2: u32,
    #[bits(1)]
    pub sme_ztt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(1)]
    pub _op_21: u32,
    #[bits(1)]
    pub sve_xs_22: u32,
    #[bits(9)]
    pub _op_23: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW2_22 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(1)]
    pub _op_21: u32,
    #[bits(1)]
    pub sve_xs_22: u32,
    #[bits(9)]
    pub _op_23: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x4 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1W_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW_22_S_D {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(1)]
    pub _op_21: u32,
    #[bits(1)]
    pub sve_xs_22: u32,
    #[bits(9)]
    pub _op_23: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1W_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW2_22_S_D {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(1)]
    pub _op_21: u32,
    #[bits(1)]
    pub sve_xs_22: u32,
    #[bits(9)]
    pub _op_23: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1W_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_ZI_U5x4_S_D {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL2 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1W_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RX_LSL2 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD1W_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD2_LVt_SIMD_ADDR_SIMPLE {
    #[bits(32)]
    pub _op_0: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD2_LEt_SIMD_ADDR_SIMPLE {
    #[bits(32)]
    pub _op_0: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD2_LVt_SIMD_ADDR_POST {
    #[bits(32)]
    pub _op_0: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD2_LEt_SIMD_ADDR_POST {
    #[bits(32)]
    pub _op_0: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD2B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD2B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x2xVL {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD2D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL3 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD2D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x2xVL {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD2H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD2H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x2xVL {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD2Q_SME_Zt2_SVE_Pg3_SVE_ADDR_RI_S4x2xVL {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD2Q_SME_Zt2_SVE_Pg3_SVE_ADDR_RR_LSL4 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD2R_LVt_AL_SIMD_ADDR_SIMPLE {
    #[bits(32)]
    pub _op_0: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD2R_LVt_AL_SIMD_ADDR_POST {
    #[bits(32)]
    pub _op_0: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD2W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD2W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x2xVL {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD3_LVt_SIMD_ADDR_SIMPLE {
    #[bits(32)]
    pub _op_0: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD3_LEt_SIMD_ADDR_SIMPLE {
    #[bits(32)]
    pub _op_0: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD3_LVt_SIMD_ADDR_POST {
    #[bits(32)]
    pub _op_0: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD3_LEt_SIMD_ADDR_POST {
    #[bits(32)]
    pub _op_0: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD3B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD3B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x3xVL {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD3D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL3 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD3D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x3xVL {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD3H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD3H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x3xVL {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD3Q_SME_Zt3_SVE_Pg3_SVE_ADDR_RI_S4x2xVL {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD3Q_SME_Zt3_SVE_Pg3_SVE_ADDR_RR_LSL4 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD3R_LVt_AL_SIMD_ADDR_SIMPLE {
    #[bits(32)]
    pub _op_0: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD3R_LVt_AL_SIMD_ADDR_POST {
    #[bits(32)]
    pub _op_0: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD3W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD3W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x3xVL {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD4_LVt_SIMD_ADDR_SIMPLE {
    #[bits(32)]
    pub _op_0: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD4_LEt_SIMD_ADDR_SIMPLE {
    #[bits(32)]
    pub _op_0: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD4_LVt_SIMD_ADDR_POST {
    #[bits(32)]
    pub _op_0: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD4_LEt_SIMD_ADDR_POST {
    #[bits(32)]
    pub _op_0: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD4B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD4B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x4xVL {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD4D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL3 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD4D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x4xVL {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD4H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD4H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x4xVL {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD4Q_SME_Zt4_SVE_Pg3_SVE_ADDR_RI_S4x2xVL {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD4Q_SME_Zt4_SVE_Pg3_SVE_ADDR_RR_LSL4 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD4R_LVt_AL_SIMD_ADDR_SIMPLE {
    #[bits(32)]
    pub _op_0: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD4R_LVt_AL_SIMD_ADDR_POST {
    #[bits(32)]
    pub _op_0: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD4W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD4W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x4xVL {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LD64B_Rt_LS64_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(27)]
    pub _op_5: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDADD_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDADDA_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDADDAB_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDADDAH_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDADDAL_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDADDALB_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDADDALH_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDADDB_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDADDH_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDADDL_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDADDLB_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDADDLH_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDAP1_LEt_SIMD_ADDR_SIMPLE {
    #[bits(32)]
    pub _op_0: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDAPR_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(27)]
    pub _op_5: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDAPR_Rt_RCPC3_ADDR_POSTIND {
    #[bits(5)]
    pub rt: u32,
    #[bits(27)]
    pub _op_5: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDAPRB_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(27)]
    pub _op_5: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDAPRH_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(27)]
    pub _op_5: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDAPUR_Rt_ADDR_OFFSET {
    #[bits(5)]
    pub rt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(1)]
    pub _op_10: u32,
    #[bits(1)]
    pub index: u32,
    #[bits(9)]
    pub imm9: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDAPUR_Rt_X_ADDR_OFFSET {
    #[bits(5)]
    pub rt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(1)]
    pub _op_10: u32,
    #[bits(1)]
    pub index: u32,
    #[bits(9)]
    pub imm9: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDAPUR_Ft_RCPC3_ADDR_OFFSET {
    #[bits(5)]
    pub rt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(2)]
    pub _op_10: u32,
    #[bits(9)]
    pub imm9: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDAPURB_Rt_ADDR_OFFSET {
    #[bits(5)]
    pub rt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(1)]
    pub _op_10: u32,
    #[bits(1)]
    pub index: u32,
    #[bits(9)]
    pub imm9: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDAPURH_Rt_ADDR_OFFSET {
    #[bits(5)]
    pub rt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(1)]
    pub _op_10: u32,
    #[bits(1)]
    pub index: u32,
    #[bits(9)]
    pub imm9: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDAPURSB_Rt_ADDR_OFFSET {
    #[bits(5)]
    pub rt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(1)]
    pub _op_10: u32,
    #[bits(1)]
    pub index: u32,
    #[bits(9)]
    pub imm9: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDAPURSB_Rt_W_ADDR_OFFSET {
    #[bits(5)]
    pub rt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(1)]
    pub _op_10: u32,
    #[bits(1)]
    pub index: u32,
    #[bits(9)]
    pub imm9: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDAPURSH_Rt_ADDR_OFFSET {
    #[bits(5)]
    pub rt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(1)]
    pub _op_10: u32,
    #[bits(1)]
    pub index: u32,
    #[bits(9)]
    pub imm9: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDAPURSH_Rt_W_ADDR_OFFSET {
    #[bits(5)]
    pub rt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(1)]
    pub _op_10: u32,
    #[bits(1)]
    pub index: u32,
    #[bits(9)]
    pub imm9: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDAPURSW_Rt_ADDR_OFFSET {
    #[bits(5)]
    pub rt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(1)]
    pub _op_10: u32,
    #[bits(1)]
    pub index: u32,
    #[bits(9)]
    pub imm9: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDAR_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(27)]
    pub _op_5: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDARB_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(27)]
    pub _op_5: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDARH_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(27)]
    pub _op_5: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDAXP_Rt_Rt2_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(5)]
    pub _op_5: u32,
    #[bits(5)]
    pub rt2: u32,
    #[bits(17)]
    pub _op_15: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDAXR_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(27)]
    pub _op_5: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDAXRB_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(27)]
    pub _op_5: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDAXRH_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(27)]
    pub _op_5: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDCLR_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDCLRA_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDCLRAB_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDCLRAH_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDCLRAL_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDCLRALB_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDCLRALH_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDCLRB_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDCLRH_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDCLRL_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDCLRLB_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDCLRLH_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDCLRP_LSE128_Rt_LSE128_Rt2_ADDR_SIMPLE {
    #[bits(5)]
    pub lse128_rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub lse128_rt2: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDCLRPA_LSE128_Rt_LSE128_Rt2_ADDR_SIMPLE {
    #[bits(5)]
    pub lse128_rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub lse128_rt2: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDCLRPAL_LSE128_Rt_LSE128_Rt2_ADDR_SIMPLE {
    #[bits(5)]
    pub lse128_rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub lse128_rt2: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDCLRPL_LSE128_Rt_LSE128_Rt2_ADDR_SIMPLE {
    #[bits(5)]
    pub lse128_rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub lse128_rt2: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDEOR_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDEORA_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDEORAB_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDEORAH_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDEORAL_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDEORALB_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDEORALH_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDEORB_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDEORH_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDEORL_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDEORLB_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDEORLH_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDFF1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(1)]
    pub _op_21: u32,
    #[bits(1)]
    pub sve_xs_22: u32,
    #[bits(9)]
    pub _op_23: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDFF1B_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW_22_S_D {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(1)]
    pub _op_21: u32,
    #[bits(1)]
    pub sve_xs_22: u32,
    #[bits(9)]
    pub _op_23: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDFF1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDFF1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDFF1B_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_ZI_U5_S_D {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDFF1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RR {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDFF1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_R {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDFF1B_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RR {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDFF1B_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_R {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDFF1B_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RR {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDFF1B_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_R {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDFF1B_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RR {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDFF1B_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_R {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDFF1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(1)]
    pub _op_21: u32,
    #[bits(1)]
    pub sve_xs_22: u32,
    #[bits(9)]
    pub _op_23: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDFF1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW3_22 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(1)]
    pub _op_21: u32,
    #[bits(1)]
    pub sve_xs_22: u32,
    #[bits(9)]
    pub _op_23: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDFF1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDFF1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x8 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDFF1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL3 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDFF1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RR_LSL3 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDFF1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_R {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDFF1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(1)]
    pub _op_21: u32,
    #[bits(1)]
    pub sve_xs_22: u32,
    #[bits(9)]
    pub _op_23: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDFF1H_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW_22_S_D {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(1)]
    pub _op_21: u32,
    #[bits(1)]
    pub sve_xs_22: u32,
    #[bits(9)]
    pub _op_23: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDFF1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW1_22 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(1)]
    pub _op_21: u32,
    #[bits(1)]
    pub sve_xs_22: u32,
    #[bits(9)]
    pub _op_23: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDFF1H_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW1_22_S_D {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(1)]
    pub _op_21: u32,
    #[bits(1)]
    pub sve_xs_22: u32,
    #[bits(9)]
    pub _op_23: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDFF1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x2 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDFF1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDFF1H_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_ZI_U5x2_S_D {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDFF1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL1 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDFF1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RR_LSL1 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDFF1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_R {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDFF1H_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RR_LSL1 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDFF1H_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_R {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDFF1H_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RR_LSL1 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDFF1H_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_R {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDFF1SB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(1)]
    pub _op_21: u32,
    #[bits(1)]
    pub sve_xs_22: u32,
    #[bits(9)]
    pub _op_23: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDFF1SB_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW_22_S_D {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(1)]
    pub _op_21: u32,
    #[bits(1)]
    pub sve_xs_22: u32,
    #[bits(9)]
    pub _op_23: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDFF1SB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDFF1SB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDFF1SB_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_ZI_U5_S_D {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDFF1SB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RR {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDFF1SB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_R {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDFF1SB_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RR {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDFF1SB_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_R {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDFF1SB_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RR {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDFF1SB_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_R {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDFF1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(1)]
    pub _op_21: u32,
    #[bits(1)]
    pub sve_xs_22: u32,
    #[bits(9)]
    pub _op_23: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDFF1SH_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW_22_S_D {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(1)]
    pub _op_21: u32,
    #[bits(1)]
    pub sve_xs_22: u32,
    #[bits(9)]
    pub _op_23: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDFF1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW1_22 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(1)]
    pub _op_21: u32,
    #[bits(1)]
    pub sve_xs_22: u32,
    #[bits(9)]
    pub _op_23: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDFF1SH_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW1_22_S_D {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(1)]
    pub _op_21: u32,
    #[bits(1)]
    pub sve_xs_22: u32,
    #[bits(9)]
    pub _op_23: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDFF1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x2 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDFF1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDFF1SH_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_ZI_U5x2_S_D {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDFF1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL1 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDFF1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RR_LSL1 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDFF1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_R {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDFF1SH_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RR_LSL1 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDFF1SH_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_R {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDFF1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RR_LSL2 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDFF1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_R {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDFF1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(1)]
    pub _op_21: u32,
    #[bits(1)]
    pub sve_xs_22: u32,
    #[bits(9)]
    pub _op_23: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDFF1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW2_22 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(1)]
    pub _op_21: u32,
    #[bits(1)]
    pub sve_xs_22: u32,
    #[bits(9)]
    pub _op_23: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDFF1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDFF1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x4 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDFF1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL2 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDFF1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(1)]
    pub _op_21: u32,
    #[bits(1)]
    pub sve_xs_22: u32,
    #[bits(9)]
    pub _op_23: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDFF1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW2_22 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(1)]
    pub _op_21: u32,
    #[bits(1)]
    pub sve_xs_22: u32,
    #[bits(9)]
    pub _op_23: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDFF1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x4 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDFF1W_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW_22_S_D {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(1)]
    pub _op_21: u32,
    #[bits(1)]
    pub sve_xs_22: u32,
    #[bits(9)]
    pub _op_23: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDFF1W_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW2_22_S_D {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(1)]
    pub _op_21: u32,
    #[bits(1)]
    pub sve_xs_22: u32,
    #[bits(9)]
    pub _op_23: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDFF1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDFF1W_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_ZI_U5x4_S_D {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDFF1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL2 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDFF1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RR_LSL2 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDFF1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_R {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDFF1W_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RR_LSL2 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDFF1W_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_R {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDG_Rt_ADDR_SIMM13 {
    #[bits(5)]
    pub rt: u32,
    #[bits(6)]
    pub _op_5: u32,
    #[bits(1)]
    pub index: u32,
    #[bits(9)]
    pub imm9: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDGM_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(27)]
    pub _op_5: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDIAPP_Rt_Rs_RCPC3_ADDR_OPT_POSTIND {
    #[bits(5)]
    pub rt: u32,
    #[bits(7)]
    pub _op_5: u32,
    #[bits(4)]
    pub opc2: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDLAR_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(27)]
    pub _op_5: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDLARB_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(27)]
    pub _op_5: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDLARH_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(27)]
    pub _op_5: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDNF1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDNF1B_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDNF1B_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDNF1B_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDNF1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDNF1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDNF1H_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDNF1H_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDNF1SB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDNF1SB_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDNF1SB_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDNF1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDNF1SH_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDNF1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDNF1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDNF1W_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDNP_Rt_Rt2_ADDR_SIMM7 {
    #[bits(5)]
    pub rt: u32,
    #[bits(5)]
    pub _op_5: u32,
    #[bits(5)]
    pub rt2: u32,
    #[bits(7)]
    pub imm7: u32,
    #[bits(2)]
    pub _op_22: u32,
    #[bits(1)]
    pub index2: u32,
    #[bits(7)]
    pub _op_25: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDNP_Ft_Ft2_ADDR_SIMM7 {
    #[bits(5)]
    pub rt: u32,
    #[bits(5)]
    pub _op_5: u32,
    #[bits(5)]
    pub rt2: u32,
    #[bits(7)]
    pub imm7: u32,
    #[bits(2)]
    pub _op_22: u32,
    #[bits(1)]
    pub index2: u32,
    #[bits(7)]
    pub _op_25: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDNT1B_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR {
    #[bits(1)]
    pub _op_0: u32,
    #[bits(4)]
    pub sme_zdn2: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDNT1B_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR {
    #[bits(2)]
    pub _op_0: u32,
    #[bits(3)]
    pub sme_zdn4: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDNT1B_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL {
    #[bits(1)]
    pub _op_0: u32,
    #[bits(4)]
    pub sme_zdn2: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDNT1B_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL {
    #[bits(2)]
    pub _op_0: u32,
    #[bits(3)]
    pub sme_zdn4: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDNT1B_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR {
    #[bits(3)]
    pub sme_zt3: u32,
    #[bits(1)]
    pub _op_3: u32,
    #[bits(1)]
    pub sme_ztt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDNT1B_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR {
    #[bits(2)]
    pub sme_zt2: u32,
    #[bits(2)]
    pub _op_2: u32,
    #[bits(1)]
    pub sme_ztt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDNT1B_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL {
    #[bits(3)]
    pub sme_zt3: u32,
    #[bits(1)]
    pub _op_3: u32,
    #[bits(1)]
    pub sme_ztt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDNT1B_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL {
    #[bits(2)]
    pub sme_zt2: u32,
    #[bits(2)]
    pub _op_2: u32,
    #[bits(1)]
    pub sme_ztt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDNT1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZX {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDNT1B_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_ZX_S_S {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDNT1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDNT1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDNT1D_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR_LSL3 {
    #[bits(1)]
    pub _op_0: u32,
    #[bits(4)]
    pub sme_zdn2: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDNT1D_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR_LSL3 {
    #[bits(2)]
    pub _op_0: u32,
    #[bits(3)]
    pub sme_zdn4: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDNT1D_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL {
    #[bits(1)]
    pub _op_0: u32,
    #[bits(4)]
    pub sme_zdn2: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDNT1D_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL {
    #[bits(2)]
    pub _op_0: u32,
    #[bits(3)]
    pub sme_zdn4: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDNT1D_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL3 {
    #[bits(3)]
    pub sme_zt3: u32,
    #[bits(1)]
    pub _op_3: u32,
    #[bits(1)]
    pub sme_ztt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDNT1D_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL3 {
    #[bits(2)]
    pub sme_zt2: u32,
    #[bits(2)]
    pub _op_2: u32,
    #[bits(1)]
    pub sme_ztt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDNT1D_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL {
    #[bits(3)]
    pub sme_zt3: u32,
    #[bits(1)]
    pub _op_3: u32,
    #[bits(1)]
    pub sme_ztt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDNT1D_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL {
    #[bits(2)]
    pub sme_zt2: u32,
    #[bits(2)]
    pub _op_2: u32,
    #[bits(1)]
    pub sme_ztt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDNT1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZX {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDNT1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL3 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDNT1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDNT1H_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR_LSL1 {
    #[bits(1)]
    pub _op_0: u32,
    #[bits(4)]
    pub sme_zdn2: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDNT1H_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR_LSL1 {
    #[bits(2)]
    pub _op_0: u32,
    #[bits(3)]
    pub sme_zdn4: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDNT1H_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL {
    #[bits(1)]
    pub _op_0: u32,
    #[bits(4)]
    pub sme_zdn2: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDNT1H_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL {
    #[bits(2)]
    pub _op_0: u32,
    #[bits(3)]
    pub sme_zdn4: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDNT1H_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL1 {
    #[bits(3)]
    pub sme_zt3: u32,
    #[bits(1)]
    pub _op_3: u32,
    #[bits(1)]
    pub sme_ztt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDNT1H_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL1 {
    #[bits(2)]
    pub sme_zt2: u32,
    #[bits(2)]
    pub _op_2: u32,
    #[bits(1)]
    pub sme_ztt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDNT1H_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL {
    #[bits(3)]
    pub sme_zt3: u32,
    #[bits(1)]
    pub _op_3: u32,
    #[bits(1)]
    pub sme_ztt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDNT1H_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL {
    #[bits(2)]
    pub sme_zt2: u32,
    #[bits(2)]
    pub _op_2: u32,
    #[bits(1)]
    pub sme_ztt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDNT1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZX {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDNT1H_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_ZX_S_S {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDNT1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDNT1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDNT1SB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZX {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDNT1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZX {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDNT1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZX {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDNT1W_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR_LSL2 {
    #[bits(1)]
    pub _op_0: u32,
    #[bits(4)]
    pub sme_zdn2: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDNT1W_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR_LSL2 {
    #[bits(2)]
    pub _op_0: u32,
    #[bits(3)]
    pub sme_zdn4: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDNT1W_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL {
    #[bits(1)]
    pub _op_0: u32,
    #[bits(4)]
    pub sme_zdn2: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDNT1W_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL {
    #[bits(2)]
    pub _op_0: u32,
    #[bits(3)]
    pub sme_zdn4: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDNT1W_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL2 {
    #[bits(3)]
    pub sme_zt3: u32,
    #[bits(1)]
    pub _op_3: u32,
    #[bits(1)]
    pub sme_ztt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDNT1W_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL2 {
    #[bits(2)]
    pub sme_zt2: u32,
    #[bits(2)]
    pub _op_2: u32,
    #[bits(1)]
    pub sme_ztt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDNT1W_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL {
    #[bits(3)]
    pub sme_zt3: u32,
    #[bits(1)]
    pub _op_3: u32,
    #[bits(1)]
    pub sme_ztt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDNT1W_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL {
    #[bits(2)]
    pub sme_zt2: u32,
    #[bits(2)]
    pub _op_2: u32,
    #[bits(1)]
    pub sme_ztt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDNT1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZX {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDNT1W_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_ZX_S_D {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDNT1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDNT1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDP_Rt_Rt2_ADDR_SIMM7 {
    #[bits(5)]
    pub rt: u32,
    #[bits(5)]
    pub _op_5: u32,
    #[bits(5)]
    pub rt2: u32,
    #[bits(7)]
    pub imm7: u32,
    #[bits(2)]
    pub _op_22: u32,
    #[bits(1)]
    pub index2: u32,
    #[bits(7)]
    pub _op_25: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDP_Rt_W_Rt2_W_ADDR_SIMM7_S_S {
    #[bits(5)]
    pub rt: u32,
    #[bits(5)]
    pub _op_5: u32,
    #[bits(5)]
    pub rt2: u32,
    #[bits(7)]
    pub imm7: u32,
    #[bits(2)]
    pub _op_22: u32,
    #[bits(1)]
    pub index2: u32,
    #[bits(7)]
    pub _op_25: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDP_Ft_Ft2_ADDR_SIMM7 {
    #[bits(5)]
    pub rt: u32,
    #[bits(5)]
    pub _op_5: u32,
    #[bits(5)]
    pub rt2: u32,
    #[bits(7)]
    pub imm7: u32,
    #[bits(2)]
    pub _op_22: u32,
    #[bits(1)]
    pub index2: u32,
    #[bits(7)]
    pub _op_25: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDP_Ft_S_S_Ft2_S_S_ADDR_SIMM7_S_S {
    #[bits(5)]
    pub rt: u32,
    #[bits(5)]
    pub _op_5: u32,
    #[bits(5)]
    pub rt2: u32,
    #[bits(7)]
    pub imm7: u32,
    #[bits(2)]
    pub _op_22: u32,
    #[bits(1)]
    pub index2: u32,
    #[bits(7)]
    pub _op_25: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDPSW_Rt_Rt2_ADDR_SIMM7 {
    #[bits(5)]
    pub rt: u32,
    #[bits(5)]
    pub _op_5: u32,
    #[bits(5)]
    pub rt2: u32,
    #[bits(7)]
    pub imm7: u32,
    #[bits(2)]
    pub _op_22: u32,
    #[bits(1)]
    pub index2: u32,
    #[bits(7)]
    pub _op_25: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDPSW_Rt_X_Rt2_X_ADDR_SIMM7_S_S {
    #[bits(5)]
    pub rt: u32,
    #[bits(5)]
    pub _op_5: u32,
    #[bits(5)]
    pub rt2: u32,
    #[bits(7)]
    pub imm7: u32,
    #[bits(2)]
    pub _op_22: u32,
    #[bits(1)]
    pub index2: u32,
    #[bits(7)]
    pub _op_25: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDR_SME_ZA_array_off4_SME_ADDR_RI_U4xVL {
    #[bits(4)]
    pub imm4_0: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(17)]
    pub _op_15: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDR_SME_ZT0_SIMD_ADDR_SIMPLE {
    #[bits(32)]
    pub _op_0: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDR_Rt_ADDR_PCREL19 {
    #[bits(5)]
    pub rt: u32,
    #[bits(19)]
    pub imm19: u32,
    #[bits(8)]
    pub _op_24: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDR_Rt_ADDR_REGOFF {
    #[bits(5)]
    pub rt: u32,
    #[bits(27)]
    pub _op_5: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDR_Rt_ADDR_SIMM9 {
    #[bits(5)]
    pub rt: u32,
    #[bits(6)]
    pub _op_5: u32,
    #[bits(1)]
    pub index: u32,
    #[bits(9)]
    pub imm9: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDR_Rt_ADDR_UIMM12 {
    #[bits(5)]
    pub rt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(12)]
    pub imm12: u32,
    #[bits(10)]
    pub _op_22: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDR_SVE_Pt_SVE_ADDR_RI_S9xVL {
    #[bits(4)]
    pub sve_pt: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDR_SVE_PNt_SVE_ADDR_RI_S9xVL {
    #[bits(4)]
    pub sve_pt: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDR_SVE_Zt_SVE_ADDR_RI_S9xVL {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDR_Ft_ADDR_PCREL19 {
    #[bits(5)]
    pub rt: u32,
    #[bits(19)]
    pub imm19: u32,
    #[bits(8)]
    pub _op_24: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDR_Ft_ADDR_REGOFF {
    #[bits(5)]
    pub rt: u32,
    #[bits(27)]
    pub _op_5: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDR_Ft_ADDR_SIMM9 {
    #[bits(5)]
    pub rt: u32,
    #[bits(6)]
    pub _op_5: u32,
    #[bits(1)]
    pub index: u32,
    #[bits(9)]
    pub imm9: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDR_Ft_ADDR_UIMM12 {
    #[bits(5)]
    pub rt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(12)]
    pub imm12: u32,
    #[bits(10)]
    pub _op_22: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDRAA_Rt_ADDR_SIMM10 {
    #[bits(5)]
    pub rt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(1)]
    pub _op_10: u32,
    #[bits(1)]
    pub index: u32,
    #[bits(9)]
    pub imm9: u32,
    #[bits(1)]
    pub _op_21: u32,
    #[bits(1)]
    pub s_imm10: u32,
    #[bits(9)]
    pub _op_23: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDRAB_Rt_ADDR_SIMM10 {
    #[bits(5)]
    pub rt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(1)]
    pub _op_10: u32,
    #[bits(1)]
    pub index: u32,
    #[bits(9)]
    pub imm9: u32,
    #[bits(1)]
    pub _op_21: u32,
    #[bits(1)]
    pub s_imm10: u32,
    #[bits(9)]
    pub _op_23: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDRB_Rt_ADDR_REGOFF {
    #[bits(5)]
    pub rt: u32,
    #[bits(27)]
    pub _op_5: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDRB_Rt_ADDR_SIMM9 {
    #[bits(5)]
    pub rt: u32,
    #[bits(6)]
    pub _op_5: u32,
    #[bits(1)]
    pub index: u32,
    #[bits(9)]
    pub imm9: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDRB_Rt_ADDR_UIMM12 {
    #[bits(5)]
    pub rt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(12)]
    pub imm12: u32,
    #[bits(10)]
    pub _op_22: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDRH_Rt_ADDR_REGOFF {
    #[bits(5)]
    pub rt: u32,
    #[bits(27)]
    pub _op_5: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDRH_Rt_ADDR_SIMM9 {
    #[bits(5)]
    pub rt: u32,
    #[bits(6)]
    pub _op_5: u32,
    #[bits(1)]
    pub index: u32,
    #[bits(9)]
    pub imm9: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDRH_Rt_ADDR_UIMM12 {
    #[bits(5)]
    pub rt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(12)]
    pub imm12: u32,
    #[bits(10)]
    pub _op_22: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDRSB_Rt_ADDR_REGOFF {
    #[bits(5)]
    pub rt: u32,
    #[bits(27)]
    pub _op_5: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDRSB_Rt_ADDR_SIMM9 {
    #[bits(5)]
    pub rt: u32,
    #[bits(6)]
    pub _op_5: u32,
    #[bits(1)]
    pub index: u32,
    #[bits(9)]
    pub imm9: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDRSB_Rt_ADDR_UIMM12 {
    #[bits(5)]
    pub rt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(12)]
    pub imm12: u32,
    #[bits(10)]
    pub _op_22: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDRSH_Rt_ADDR_REGOFF {
    #[bits(5)]
    pub rt: u32,
    #[bits(27)]
    pub _op_5: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDRSH_Rt_ADDR_SIMM9 {
    #[bits(5)]
    pub rt: u32,
    #[bits(6)]
    pub _op_5: u32,
    #[bits(1)]
    pub index: u32,
    #[bits(9)]
    pub imm9: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDRSH_Rt_ADDR_UIMM12 {
    #[bits(5)]
    pub rt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(12)]
    pub imm12: u32,
    #[bits(10)]
    pub _op_22: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDRSW_Rt_ADDR_PCREL19 {
    #[bits(5)]
    pub rt: u32,
    #[bits(19)]
    pub imm19: u32,
    #[bits(8)]
    pub _op_24: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDRSW_Rt_ADDR_REGOFF {
    #[bits(5)]
    pub rt: u32,
    #[bits(27)]
    pub _op_5: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDRSW_Rt_ADDR_SIMM9 {
    #[bits(5)]
    pub rt: u32,
    #[bits(6)]
    pub _op_5: u32,
    #[bits(1)]
    pub index: u32,
    #[bits(9)]
    pub imm9: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDRSW_Rt_ADDR_UIMM12 {
    #[bits(5)]
    pub rt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(12)]
    pub imm12: u32,
    #[bits(10)]
    pub _op_22: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDSET_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDSETA_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDSETAB_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDSETAH_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDSETAL_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDSETALB_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDSETALH_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDSETB_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDSETH_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDSETL_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDSETLB_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDSETLH_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDSETP_LSE128_Rt_LSE128_Rt2_ADDR_SIMPLE {
    #[bits(5)]
    pub lse128_rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub lse128_rt2: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDSETPA_LSE128_Rt_LSE128_Rt2_ADDR_SIMPLE {
    #[bits(5)]
    pub lse128_rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub lse128_rt2: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDSETPAL_LSE128_Rt_LSE128_Rt2_ADDR_SIMPLE {
    #[bits(5)]
    pub lse128_rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub lse128_rt2: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDSETPL_LSE128_Rt_LSE128_Rt2_ADDR_SIMPLE {
    #[bits(5)]
    pub lse128_rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub lse128_rt2: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDSMAX_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDSMAXA_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDSMAXAB_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDSMAXAH_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDSMAXAL_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDSMAXALB_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDSMAXALH_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDSMAXB_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDSMAXH_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDSMAXL_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDSMAXLB_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDSMAXLH_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDSMIN_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDSMINA_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDSMINAB_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDSMINAH_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDSMINAL_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDSMINALB_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDSMINALH_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDSMINB_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDSMINH_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDSMINL_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDSMINLB_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDSMINLH_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDTR_Rt_ADDR_SIMM9 {
    #[bits(5)]
    pub rt: u32,
    #[bits(6)]
    pub _op_5: u32,
    #[bits(1)]
    pub index: u32,
    #[bits(9)]
    pub imm9: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDTRB_Rt_ADDR_SIMM9 {
    #[bits(5)]
    pub rt: u32,
    #[bits(6)]
    pub _op_5: u32,
    #[bits(1)]
    pub index: u32,
    #[bits(9)]
    pub imm9: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDTRH_Rt_ADDR_SIMM9 {
    #[bits(5)]
    pub rt: u32,
    #[bits(6)]
    pub _op_5: u32,
    #[bits(1)]
    pub index: u32,
    #[bits(9)]
    pub imm9: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDTRSB_Rt_ADDR_SIMM9 {
    #[bits(5)]
    pub rt: u32,
    #[bits(6)]
    pub _op_5: u32,
    #[bits(1)]
    pub index: u32,
    #[bits(9)]
    pub imm9: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDTRSH_Rt_ADDR_SIMM9 {
    #[bits(5)]
    pub rt: u32,
    #[bits(6)]
    pub _op_5: u32,
    #[bits(1)]
    pub index: u32,
    #[bits(9)]
    pub imm9: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDTRSW_Rt_ADDR_SIMM9 {
    #[bits(5)]
    pub rt: u32,
    #[bits(6)]
    pub _op_5: u32,
    #[bits(1)]
    pub index: u32,
    #[bits(9)]
    pub imm9: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDUMAX_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDUMAXA_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDUMAXAB_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDUMAXAH_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDUMAXAL_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDUMAXALB_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDUMAXALH_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDUMAXB_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDUMAXH_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDUMAXL_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDUMAXLB_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDUMAXLH_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDUMIN_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDUMINA_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDUMINAB_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDUMINAH_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDUMINAL_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDUMINALB_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDUMINALH_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDUMINB_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDUMINH_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDUMINL_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDUMINLB_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDUMINLH_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDUR_Rt_ADDR_SIMM9 {
    #[bits(5)]
    pub rt: u32,
    #[bits(6)]
    pub _op_5: u32,
    #[bits(1)]
    pub index: u32,
    #[bits(9)]
    pub imm9: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDUR_Ft_ADDR_SIMM9 {
    #[bits(5)]
    pub rt: u32,
    #[bits(6)]
    pub _op_5: u32,
    #[bits(1)]
    pub index: u32,
    #[bits(9)]
    pub imm9: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDURB_Rt_ADDR_SIMM9 {
    #[bits(5)]
    pub rt: u32,
    #[bits(6)]
    pub _op_5: u32,
    #[bits(1)]
    pub index: u32,
    #[bits(9)]
    pub imm9: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDURH_Rt_ADDR_SIMM9 {
    #[bits(5)]
    pub rt: u32,
    #[bits(6)]
    pub _op_5: u32,
    #[bits(1)]
    pub index: u32,
    #[bits(9)]
    pub imm9: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDURSB_Rt_ADDR_SIMM9 {
    #[bits(5)]
    pub rt: u32,
    #[bits(6)]
    pub _op_5: u32,
    #[bits(1)]
    pub index: u32,
    #[bits(9)]
    pub imm9: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDURSH_Rt_ADDR_SIMM9 {
    #[bits(5)]
    pub rt: u32,
    #[bits(6)]
    pub _op_5: u32,
    #[bits(1)]
    pub index: u32,
    #[bits(9)]
    pub imm9: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDURSW_Rt_ADDR_SIMM9 {
    #[bits(5)]
    pub rt: u32,
    #[bits(6)]
    pub _op_5: u32,
    #[bits(1)]
    pub index: u32,
    #[bits(9)]
    pub imm9: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDXP_Rt_Rt2_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(5)]
    pub _op_5: u32,
    #[bits(5)]
    pub rt2: u32,
    #[bits(17)]
    pub _op_15: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDXR_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(27)]
    pub _op_5: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDXRB_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(27)]
    pub _op_5: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LDXRH_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(27)]
    pub _op_5: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LSL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_SHLIMM_PRED {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_imm5: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(9)]
    pub _op_13: u32,
    #[bits(2)]
    pub sve_tszh: u32,
    #[bits(8)]
    pub _op_24: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LSL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zm_5: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LSL_SVE_Zd_S_B_SVE_Pg3_P_M_SVE_Zd_S_B_SVE_Zm_5_S_D {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zm_5: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LSL_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LSL_SVE_Zd_SVE_Zn_SVE_SHLIMM_UNPRED {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub imm5: u32,
    #[bits(1)]
    pub _op_21: u32,
    #[bits(2)]
    pub sve_tszh: u32,
    #[bits(8)]
    pub _op_24: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LSLR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zm_5: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LSLV_Rd_Rn_Rm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LSR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_SHRIMM_PRED {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_imm5: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(9)]
    pub _op_13: u32,
    #[bits(2)]
    pub sve_tszh: u32,
    #[bits(8)]
    pub _op_24: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LSR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zm_5: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LSR_SVE_Zd_S_B_SVE_Pg3_P_M_SVE_Zd_S_B_SVE_Zm_5_S_D {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zm_5: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LSR_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LSR_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub imm5: u32,
    #[bits(1)]
    pub _op_21: u32,
    #[bits(2)]
    pub sve_tszh: u32,
    #[bits(8)]
    pub _op_24: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LSRR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zm_5: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LSRV_Rd_Rn_Rm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LUTI2_SME_Zdnx4_SME_ZT0_SME_Zn_INDEX2_16 {
    #[bits(2)]
    pub _op_0: u32,
    #[bits(3)]
    pub sme_zdn4: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(2)]
    pub imm2_16: u32,
    #[bits(14)]
    pub _op_18: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LUTI2_SME_Zdnx2_SME_ZT0_SME_Zn_INDEX3_15 {
    #[bits(1)]
    pub _op_0: u32,
    #[bits(4)]
    pub sme_zdn2: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(5)]
    pub _op_10: u32,
    #[bits(3)]
    pub imm3_15: u32,
    #[bits(14)]
    pub _op_18: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LUTI2_SVE_Zd_SME_ZT0_SME_Zn_INDEX4_14 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(4)]
    pub _op_10: u32,
    #[bits(4)]
    pub imm4_14: u32,
    #[bits(14)]
    pub _op_18: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LUTI4_SME_Zdnx4_SME_ZT0_SME_Zn_INDEX1_16 {
    #[bits(2)]
    pub _op_0: u32,
    #[bits(3)]
    pub sme_zdn4: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(1)]
    pub imm1_16: u32,
    #[bits(15)]
    pub _op_17: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LUTI4_SME_Zdnx2_SME_ZT0_SME_Zn_INDEX2_15 {
    #[bits(1)]
    pub _op_0: u32,
    #[bits(4)]
    pub sme_zdn2: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(5)]
    pub _op_10: u32,
    #[bits(2)]
    pub imm2_15: u32,
    #[bits(15)]
    pub _op_17: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct LUTI4_SVE_Zd_SME_ZT0_SME_Zn_INDEX3_14 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(4)]
    pub _op_10: u32,
    #[bits(3)]
    pub imm3_14: u32,
    #[bits(15)]
    pub _op_17: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct MAD_SVE_Zd_SVE_Pg3_SVE_Zm_16_SVE_Za_5 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_za_5: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct MADD_Rd_Rn_Rm_Ra {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(5)]
    pub ra: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct MATCH_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16 {
    #[bits(4)]
    pub sve_pd: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct MLA_SVE_Zd_SVE_Zn_SVE_Zm3_22_INDEX {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(1)]
    pub _op_21: u32,
    #[bits(1)]
    pub sve_i3h: u32,
    #[bits(9)]
    pub _op_23: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct MLA_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct MLA_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct MLA_SVE_Zd_SVE_Pg3_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct MLA_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct MLA_Vd_Vn_Em16 {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct MLS_SVE_Zd_SVE_Zn_SVE_Zm3_22_INDEX {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(1)]
    pub _op_21: u32,
    #[bits(1)]
    pub sve_i3h: u32,
    #[bits(9)]
    pub _op_23: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct MLS_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct MLS_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct MLS_SVE_Zd_SVE_Pg3_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct MLS_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct MLS_Vd_Vn_Em16 {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct MOV_SME_ZA_HV_idx_dest_SVE_Pg3_SVE_Zn {
    #[bits(4)]
    pub imm4_0: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub sme_v: u32,
    #[bits(1)]
    pub sme_q: u32,
    #[bits(5)]
    pub _op_17: u32,
    #[bits(2)]
    pub sme_size_22: u32,
    #[bits(8)]
    pub _op_24: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct MOV_SVE_Zd_SVE_Pg3_SME_ZA_HV_idx_src {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(4)]
    pub imm4_5: u32,
    #[bits(1)]
    pub _op_9: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub sme_v: u32,
    #[bits(1)]
    pub sme_q: u32,
    #[bits(5)]
    pub _op_17: u32,
    #[bits(2)]
    pub sme_size_22: u32,
    #[bits(8)]
    pub _op_24: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct MOV_SME_ZA_HV_idx_destxN_SME_Znx2 {
    #[bits(3)]
    pub imm3_0: u32,
    #[bits(3)]
    pub _op_3: u32,
    #[bits(4)]
    pub sme_zn2: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub sme_v: u32,
    #[bits(16)]
    pub _op_16: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct MOV_SME_Zdnx2_SME_ZA_HV_idx_srcxN {
    #[bits(1)]
    pub _op_0: u32,
    #[bits(4)]
    pub sme_zdn2: u32,
    #[bits(3)]
    pub imm3_5: u32,
    #[bits(5)]
    pub _op_8: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub sme_v: u32,
    #[bits(16)]
    pub _op_16: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct MOV_SME_ZA_array_off3_0_SME_Znx2 {
    #[bits(3)]
    pub imm3_0: u32,
    #[bits(3)]
    pub _op_3: u32,
    #[bits(4)]
    pub sme_zn2: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(17)]
    pub _op_15: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct MOV_SME_Zdnx2_SME_ZA_array_off3_5 {
    #[bits(1)]
    pub _op_0: u32,
    #[bits(4)]
    pub sme_zdn2: u32,
    #[bits(3)]
    pub imm3_5: u32,
    #[bits(5)]
    pub _op_8: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(17)]
    pub _op_15: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct MOV_SME_ZA_HV_idx_destxN_SME_Znx4 {
    #[bits(3)]
    pub imm3_0: u32,
    #[bits(4)]
    pub _op_3: u32,
    #[bits(3)]
    pub sme_zn4: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub sme_v: u32,
    #[bits(16)]
    pub _op_16: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct MOV_SME_Zdnx4_SME_ZA_HV_idx_srcxN {
    #[bits(2)]
    pub _op_0: u32,
    #[bits(3)]
    pub sme_zdn4: u32,
    #[bits(3)]
    pub imm3_5: u32,
    #[bits(5)]
    pub _op_8: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub sme_v: u32,
    #[bits(16)]
    pub _op_16: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct MOV_SME_ZA_array_off3_0_SME_Znx4 {
    #[bits(3)]
    pub imm3_0: u32,
    #[bits(4)]
    pub _op_3: u32,
    #[bits(3)]
    pub sme_zn4: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(17)]
    pub _op_15: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct MOV_SME_Zdnx4_SME_ZA_array_off3_5 {
    #[bits(2)]
    pub _op_0: u32,
    #[bits(3)]
    pub sme_zdn4: u32,
    #[bits(3)]
    pub imm3_5: u32,
    #[bits(5)]
    pub _op_8: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(17)]
    pub _op_15: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct MOVA_SME_ZA_HV_idx_dest_SVE_Pg3_SVE_Zn {
    #[bits(4)]
    pub imm4_0: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub sme_v: u32,
    #[bits(1)]
    pub sme_q: u32,
    #[bits(5)]
    pub _op_17: u32,
    #[bits(2)]
    pub sme_size_22: u32,
    #[bits(8)]
    pub _op_24: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct MOVA_SVE_Zd_SVE_Pg3_SME_ZA_HV_idx_src {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(4)]
    pub imm4_5: u32,
    #[bits(1)]
    pub _op_9: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub sme_v: u32,
    #[bits(1)]
    pub sme_q: u32,
    #[bits(5)]
    pub _op_17: u32,
    #[bits(2)]
    pub sme_size_22: u32,
    #[bits(8)]
    pub _op_24: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct MOVA_SME_ZA_HV_idx_destxN_SME_Znx2 {
    #[bits(3)]
    pub imm3_0: u32,
    #[bits(3)]
    pub _op_3: u32,
    #[bits(4)]
    pub sme_zn2: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub sme_v: u32,
    #[bits(16)]
    pub _op_16: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct MOVA_SME_Zdnx2_SME_ZA_HV_idx_srcxN {
    #[bits(1)]
    pub _op_0: u32,
    #[bits(4)]
    pub sme_zdn2: u32,
    #[bits(3)]
    pub imm3_5: u32,
    #[bits(5)]
    pub _op_8: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub sme_v: u32,
    #[bits(16)]
    pub _op_16: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct MOVA_SME_ZA_array_off3_0_SME_Znx2 {
    #[bits(3)]
    pub imm3_0: u32,
    #[bits(3)]
    pub _op_3: u32,
    #[bits(4)]
    pub sme_zn2: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(17)]
    pub _op_15: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct MOVA_SME_Zdnx2_SME_ZA_array_off3_5 {
    #[bits(1)]
    pub _op_0: u32,
    #[bits(4)]
    pub sme_zdn2: u32,
    #[bits(3)]
    pub imm3_5: u32,
    #[bits(5)]
    pub _op_8: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(17)]
    pub _op_15: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct MOVA_SME_ZA_HV_idx_destxN_SME_Znx4 {
    #[bits(3)]
    pub imm3_0: u32,
    #[bits(4)]
    pub _op_3: u32,
    #[bits(3)]
    pub sme_zn4: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub sme_v: u32,
    #[bits(16)]
    pub _op_16: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct MOVA_SME_Zdnx4_SME_ZA_HV_idx_srcxN {
    #[bits(2)]
    pub _op_0: u32,
    #[bits(3)]
    pub sme_zdn4: u32,
    #[bits(3)]
    pub imm3_5: u32,
    #[bits(5)]
    pub _op_8: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub sme_v: u32,
    #[bits(16)]
    pub _op_16: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct MOVA_SME_ZA_array_off3_0_SME_Znx4 {
    #[bits(3)]
    pub imm3_0: u32,
    #[bits(4)]
    pub _op_3: u32,
    #[bits(3)]
    pub sme_zn4: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(17)]
    pub _op_15: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct MOVA_SME_Zdnx4_SME_ZA_array_off3_5 {
    #[bits(2)]
    pub _op_0: u32,
    #[bits(3)]
    pub sme_zdn4: u32,
    #[bits(3)]
    pub imm3_5: u32,
    #[bits(5)]
    pub _op_8: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(17)]
    pub _op_15: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct MOVAZ_SME_Zdnx2_SME_ZA_array_vrsb_1 {
    #[bits(1)]
    pub _op_0: u32,
    #[bits(4)]
    pub sme_zdn2: u32,
    #[bits(3)]
    pub off3: u32,
    #[bits(5)]
    pub _op_8: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub sme_v: u32,
    #[bits(16)]
    pub _op_16: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct MOVAZ_SME_Zdnx2_SME_ZA_array_vrss_1 {
    #[bits(1)]
    pub _op_0: u32,
    #[bits(4)]
    pub sme_zdn2: u32,
    #[bits(1)]
    pub ol: u32,
    #[bits(2)]
    pub zan_2: u32,
    #[bits(5)]
    pub _op_8: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub sme_v: u32,
    #[bits(16)]
    pub _op_16: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct MOVAZ_SME_Zdnx2_SME_ZA_array_vrsh_1 {
    #[bits(1)]
    pub _op_0: u32,
    #[bits(4)]
    pub sme_zdn2: u32,
    #[bits(2)]
    pub off2: u32,
    #[bits(1)]
    pub zan_1: u32,
    #[bits(5)]
    pub _op_8: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub sme_v: u32,
    #[bits(16)]
    pub _op_16: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct MOVAZ_SME_Zdnx2_SME_ZA_array_vrsd_1 {
    #[bits(1)]
    pub _op_0: u32,
    #[bits(4)]
    pub sme_zdn2: u32,
    #[bits(3)]
    pub zan_3: u32,
    #[bits(5)]
    pub _op_8: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub sme_v: u32,
    #[bits(16)]
    pub _op_16: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct MOVAZ_SME_Zdnx4_SME_ZA_array_vrsb_2 {
    #[bits(2)]
    pub _op_0: u32,
    #[bits(3)]
    pub sme_zdn4: u32,
    #[bits(2)]
    pub off2: u32,
    #[bits(6)]
    pub _op_7: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub sme_v: u32,
    #[bits(16)]
    pub _op_16: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct MOVAZ_SME_Zdnx4_SME_ZA_array_vrss_2 {
    #[bits(2)]
    pub _op_0: u32,
    #[bits(3)]
    pub sme_zdn4: u32,
    #[bits(2)]
    pub off2: u32,
    #[bits(6)]
    pub _op_7: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub sme_v: u32,
    #[bits(16)]
    pub _op_16: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct MOVAZ_SME_Zdnx4_SME_ZA_array_vrsh_2 {
    #[bits(2)]
    pub _op_0: u32,
    #[bits(3)]
    pub sme_zdn4: u32,
    #[bits(1)]
    pub ol: u32,
    #[bits(1)]
    pub zan: u32,
    #[bits(6)]
    pub _op_7: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub sme_v: u32,
    #[bits(16)]
    pub _op_16: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct MOVAZ_SME_Zdnx4_SME_ZA_array_vrsd_2 {
    #[bits(2)]
    pub _op_0: u32,
    #[bits(3)]
    pub sme_zdn4: u32,
    #[bits(3)]
    pub zan_3: u32,
    #[bits(5)]
    pub _op_8: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub sme_v: u32,
    #[bits(16)]
    pub _op_16: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct MOVI_Vd_SIMD_IMM_SFT {
    #[bits(5)]
    pub rd: u32,
    #[bits(27)]
    pub _op_5: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct MOVI_Vd_V_4H_SIMD_IMM_SFT_LSL {
    #[bits(5)]
    pub rd: u32,
    #[bits(27)]
    pub _op_5: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct MOVI_Vd_V_2S_SIMD_IMM_SFT_MSL {
    #[bits(5)]
    pub rd: u32,
    #[bits(27)]
    pub _op_5: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct MOVI_Vd_V_8B_SIMD_IMM_SFT_LSL {
    #[bits(5)]
    pub rd: u32,
    #[bits(27)]
    pub _op_5: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct MOVI_Sd_SIMD_IMM {
    #[bits(5)]
    pub rd: u32,
    #[bits(27)]
    pub _op_5: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct MOVI_Vd_SIMD_IMM {
    #[bits(5)]
    pub rd: u32,
    #[bits(27)]
    pub _op_5: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct MOVK_Rd_HALF {
    #[bits(5)]
    pub rd: u32,
    #[bits(16)]
    pub imm16_5: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct MOVN_Rd_HALF {
    #[bits(5)]
    pub rd: u32,
    #[bits(16)]
    pub imm16_5: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct MOVPRFX_SVE_Zd_SVE_Pg3_SVE_Zn {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct MOVPRFX_SVE_Zd_SVE_Zn {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct MOVT_Rt_SME_ZT0_INDEX {
    #[bits(5)]
    pub rt: u32,
    #[bits(7)]
    pub _op_5: u32,
    #[bits(3)]
    pub imm3_12: u32,
    #[bits(17)]
    pub _op_15: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct MOVT_SME_ZT0_INDEX_Rt {
    #[bits(5)]
    pub rt: u32,
    #[bits(7)]
    pub _op_5: u32,
    #[bits(3)]
    pub imm3_12: u32,
    #[bits(17)]
    pub _op_15: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct MOVZ_Rd_HALF {
    #[bits(5)]
    pub rd: u32,
    #[bits(16)]
    pub imm16_5: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct MRRS_Rt_PAIRREG_SYSREG128 {
    #[bits(5)]
    pub rt: u32,
    #[bits(27)]
    pub _op_5: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct MRS_Rt_SYSREG {
    #[bits(5)]
    pub rt: u32,
    #[bits(27)]
    pub _op_5: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct MSB_SVE_Zd_SVE_Pg3_SVE_Zm_16_SVE_Za_5 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_za_5: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct MSR_PSTATEFIELD_UIMM4 {
    #[bits(8)]
    pub _op_0: u32,
    #[bits(4)]
    pub crm: u32,
    #[bits(20)]
    pub _op_12: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct MSR_SYSREG_Rt {
    #[bits(5)]
    pub rt: u32,
    #[bits(27)]
    pub _op_5: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct MSRR_SYSREG128_Rt_PAIRREG {
    #[bits(5)]
    pub rt: u32,
    #[bits(27)]
    pub _op_5: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct MSUB_Rd_Rn_Rm_Ra {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(5)]
    pub ra: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct MUL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zm_5: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct MUL_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct MUL_SVE_Zd_SVE_Zn_SVE_Zm3_22_INDEX {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(1)]
    pub _op_21: u32,
    #[bits(1)]
    pub sve_i3h: u32,
    #[bits(9)]
    pub _op_23: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct MUL_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct MUL_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct MUL_SVE_Zd_SVE_Zd_SVE_SIMM8 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(8)]
    pub sve_imm8: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct MUL_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct MUL_Vd_Vn_Em16 {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct MVNI_Vd_SIMD_IMM_SFT {
    #[bits(5)]
    pub rd: u32,
    #[bits(27)]
    pub _op_5: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct MVNI_Vd_V_4H_SIMD_IMM_SFT_LSL {
    #[bits(5)]
    pub rd: u32,
    #[bits(27)]
    pub _op_5: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct MVNI_Vd_V_2S_SIMD_IMM_SFT_MSL {
    #[bits(5)]
    pub rd: u32,
    #[bits(27)]
    pub _op_5: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct NAND_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm {
    #[bits(4)]
    pub sve_pd: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(4)]
    pub sve_pn: u32,
    #[bits(1)]
    pub _op_9: u32,
    #[bits(4)]
    pub sve_pg4_10: u32,
    #[bits(2)]
    pub _op_14: u32,
    #[bits(4)]
    pub sve_pm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct NANDS_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm {
    #[bits(4)]
    pub sve_pd: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(4)]
    pub sve_pn: u32,
    #[bits(1)]
    pub _op_9: u32,
    #[bits(4)]
    pub sve_pg4_10: u32,
    #[bits(2)]
    pub _op_14: u32,
    #[bits(4)]
    pub sve_pm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct NBSL_SVE_Zd_SVE_Zd_SVE_Zm_16_SVE_Zn {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct NEG_SVE_Zd_SVE_Pg3_SVE_Zn {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct NEG_Vd_Vn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct NEG_Sd_Sn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct NMATCH_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16 {
    #[bits(4)]
    pub sve_pd: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct NOR_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm {
    #[bits(4)]
    pub sve_pd: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(4)]
    pub sve_pn: u32,
    #[bits(1)]
    pub _op_9: u32,
    #[bits(4)]
    pub sve_pg4_10: u32,
    #[bits(2)]
    pub _op_14: u32,
    #[bits(4)]
    pub sve_pm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct NORS_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm {
    #[bits(4)]
    pub sve_pd: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(4)]
    pub sve_pn: u32,
    #[bits(1)]
    pub _op_9: u32,
    #[bits(4)]
    pub sve_pg4_10: u32,
    #[bits(2)]
    pub _op_14: u32,
    #[bits(4)]
    pub sve_pm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct NOT_SVE_Zd_SVE_Pg3_SVE_Zn {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct NOT_Vd_Vn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ORN_Rd_Rn_Rm_SFT {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ORN_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm {
    #[bits(4)]
    pub sve_pd: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(4)]
    pub sve_pn: u32,
    #[bits(1)]
    pub _op_9: u32,
    #[bits(4)]
    pub sve_pg4_10: u32,
    #[bits(2)]
    pub _op_14: u32,
    #[bits(4)]
    pub sve_pm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ORN_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ORNS_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm {
    #[bits(4)]
    pub sve_pd: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(4)]
    pub sve_pn: u32,
    #[bits(1)]
    pub _op_9: u32,
    #[bits(4)]
    pub sve_pg4_10: u32,
    #[bits(2)]
    pub _op_14: u32,
    #[bits(4)]
    pub sve_pm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ORR_Rd_SP_Rn_LIMM {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub imms: u32,
    #[bits(6)]
    pub immr: u32,
    #[bits(1)]
    pub n: u32,
    #[bits(9)]
    pub _op_23: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ORR_Rd_Rn_Rm_SFT {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ORR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zm_5: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ORR_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ORR_SVE_Zd_SVE_Zd_SVE_LIMM {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(6)]
    pub sve_imms: u32,
    #[bits(6)]
    pub sve_immr: u32,
    #[bits(1)]
    pub sve_n: u32,
    #[bits(14)]
    pub _op_18: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ORR_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm {
    #[bits(4)]
    pub sve_pd: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(4)]
    pub sve_pn: u32,
    #[bits(1)]
    pub _op_9: u32,
    #[bits(4)]
    pub sve_pg4_10: u32,
    #[bits(2)]
    pub _op_14: u32,
    #[bits(4)]
    pub sve_pm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ORR_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ORR_Vd_SIMD_IMM_SFT {
    #[bits(5)]
    pub rd: u32,
    #[bits(27)]
    pub _op_5: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ORR_Vd_V_4H_SIMD_IMM_SFT_LSL {
    #[bits(5)]
    pub rd: u32,
    #[bits(27)]
    pub _op_5: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ORRS_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm {
    #[bits(4)]
    pub sve_pd: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(4)]
    pub sve_pn: u32,
    #[bits(1)]
    pub _op_9: u32,
    #[bits(4)]
    pub sve_pg4_10: u32,
    #[bits(2)]
    pub _op_14: u32,
    #[bits(4)]
    pub sve_pm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ORV_SVE_Vd_SVE_Pg3_SVE_Zn {
    #[bits(5)]
    pub sve_vd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct PACDA_Rd_Rn_SP {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct PACDB_Rd_Rn_SP {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct PACDZA_Rd {
    #[bits(5)]
    pub rd: u32,
    #[bits(27)]
    pub _op_5: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct PACDZB_Rd {
    #[bits(5)]
    pub rd: u32,
    #[bits(27)]
    pub _op_5: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct PACGA_Rd_Rn_Rm_SP {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct PACIA_Rd_Rn_SP {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct PACIB_Rd_Rn_SP {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct PACIZA_Rd {
    #[bits(5)]
    pub rd: u32,
    #[bits(27)]
    pub _op_5: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct PACIZB_Rd {
    #[bits(5)]
    pub rd: u32,
    #[bits(27)]
    pub _op_5: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct PEXT_SVE_Pd_SME_PNn3_INDEX2 {
    #[bits(4)]
    pub sve_pd: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(3)]
    pub sme_pnn3: u32,
    #[bits(2)]
    pub imm2_8: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct PEXT_SME_PdxN_SME_PNn3_INDEX1 {
    #[bits(4)]
    pub sve_pd: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(3)]
    pub sme_pnn3: u32,
    #[bits(1)]
    pub imm1_8: u32,
    #[bits(23)]
    pub _op_9: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct PFALSE_SVE_Pd {
    #[bits(4)]
    pub sve_pd: u32,
    #[bits(28)]
    pub _op_4: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct PFALSE_SVE_PNd {
    #[bits(4)]
    pub sve_pd: u32,
    #[bits(28)]
    pub _op_4: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct PFIRST_SVE_Pd_SVE_Pg4_5_SVE_Pd {
    #[bits(4)]
    pub sve_pd: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(4)]
    pub sve_pg4_5: u32,
    #[bits(23)]
    pub _op_9: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct PMUL_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct PMUL_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct PMULL_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct PMULL_Vd_V_1Q_Vn_V_1D_Vm_V_1D {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct PMULL2_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct PMULL2_Vd_V_1Q_Vn_V_2D_Vm_V_2D {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct PMULLB_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct PMULLB_SVE_Zd_S_H_SVE_Zn_S_B_SVE_Zm_16_S_B {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct PMULLT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct PMULLT_SVE_Zd_S_H_SVE_Zn_S_B_SVE_Zm_16_S_B {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct PNEXT_SVE_Pd_SVE_Pg4_5_SVE_Pd {
    #[bits(4)]
    pub sve_pd: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(4)]
    pub sve_pg4_5: u32,
    #[bits(23)]
    pub _op_9: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct PRFB_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RZ_XTW_22 {
    #[bits(4)]
    pub sve_prfop: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(1)]
    pub _op_21: u32,
    #[bits(1)]
    pub sve_xs_22: u32,
    #[bits(9)]
    pub _op_23: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct PRFB_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RZ_XTW_22_c4200000 {
    #[bits(4)]
    pub sve_prfop: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(1)]
    pub _op_21: u32,
    #[bits(1)]
    pub sve_xs_22: u32,
    #[bits(9)]
    pub _op_23: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct PRFB_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RZ {
    #[bits(4)]
    pub sve_prfop: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct PRFB_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RX {
    #[bits(4)]
    pub sve_prfop: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct PRFB_SVE_PRFOP_SVE_Pg3_SVE_ADDR_ZI_U5 {
    #[bits(4)]
    pub sve_prfop: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct PRFB_SVE_PRFOP_SVE_Pg3_SVE_ADDR_ZI_U5_c400e000 {
    #[bits(4)]
    pub sve_prfop: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct PRFB_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RI_S6xVL {
    #[bits(4)]
    pub sve_prfop: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct PRFD_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RZ_XTW3_22 {
    #[bits(4)]
    pub sve_prfop: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(1)]
    pub _op_21: u32,
    #[bits(1)]
    pub sve_xs_22: u32,
    #[bits(9)]
    pub _op_23: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct PRFD_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RZ_XTW3_22_c4206000 {
    #[bits(4)]
    pub sve_prfop: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(1)]
    pub _op_21: u32,
    #[bits(1)]
    pub sve_xs_22: u32,
    #[bits(9)]
    pub _op_23: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct PRFD_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RZ_LSL3 {
    #[bits(4)]
    pub sve_prfop: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct PRFD_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RX_LSL3 {
    #[bits(4)]
    pub sve_prfop: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct PRFD_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RI_S6xVL {
    #[bits(4)]
    pub sve_prfop: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct PRFD_SVE_PRFOP_SVE_Pg3_SVE_ADDR_ZI_U5x8 {
    #[bits(4)]
    pub sve_prfop: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct PRFD_SVE_PRFOP_SVE_Pg3_SVE_ADDR_ZI_U5x8_c580e000 {
    #[bits(4)]
    pub sve_prfop: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct PRFH_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RX_LSL1 {
    #[bits(4)]
    pub sve_prfop: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct PRFH_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RZ_XTW1_22 {
    #[bits(4)]
    pub sve_prfop: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(1)]
    pub _op_21: u32,
    #[bits(1)]
    pub sve_xs_22: u32,
    #[bits(9)]
    pub _op_23: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct PRFH_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RZ_XTW1_22_c4202000 {
    #[bits(4)]
    pub sve_prfop: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(1)]
    pub _op_21: u32,
    #[bits(1)]
    pub sve_xs_22: u32,
    #[bits(9)]
    pub _op_23: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct PRFH_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RZ_LSL1 {
    #[bits(4)]
    pub sve_prfop: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct PRFH_SVE_PRFOP_SVE_Pg3_SVE_ADDR_ZI_U5x2 {
    #[bits(4)]
    pub sve_prfop: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct PRFH_SVE_PRFOP_SVE_Pg3_SVE_ADDR_ZI_U5x2_c480e000 {
    #[bits(4)]
    pub sve_prfop: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct PRFH_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RI_S6xVL {
    #[bits(4)]
    pub sve_prfop: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct PRFM_PRFOP_ADDR_PCREL19 {
    #[bits(5)]
    pub _op_0: u32,
    #[bits(19)]
    pub imm19: u32,
    #[bits(8)]
    pub _op_24: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct PRFM_PRFOP_ADDR_REGOFF {
    #[bits(32)]
    pub _op_0: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct PRFM_PRFOP_ADDR_UIMM12 {
    #[bits(5)]
    pub _op_0: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(12)]
    pub imm12: u32,
    #[bits(10)]
    pub _op_22: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct PRFUM_PRFOP_ADDR_SIMM9 {
    #[bits(11)]
    pub _op_0: u32,
    #[bits(1)]
    pub index: u32,
    #[bits(9)]
    pub imm9: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct PRFW_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RZ_XTW2_22 {
    #[bits(4)]
    pub sve_prfop: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(1)]
    pub _op_21: u32,
    #[bits(1)]
    pub sve_xs_22: u32,
    #[bits(9)]
    pub _op_23: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct PRFW_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RZ_XTW2_22_c4204000 {
    #[bits(4)]
    pub sve_prfop: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(1)]
    pub _op_21: u32,
    #[bits(1)]
    pub sve_xs_22: u32,
    #[bits(9)]
    pub _op_23: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct PRFW_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RZ_LSL2 {
    #[bits(4)]
    pub sve_prfop: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct PRFW_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RI_S6xVL {
    #[bits(4)]
    pub sve_prfop: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct PRFW_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RX_LSL2 {
    #[bits(4)]
    pub sve_prfop: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct PRFW_SVE_PRFOP_SVE_Pg3_SVE_ADDR_ZI_U5x4 {
    #[bits(4)]
    pub sve_prfop: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct PRFW_SVE_PRFOP_SVE_Pg3_SVE_ADDR_ZI_U5x4_c500e000 {
    #[bits(4)]
    pub sve_prfop: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct PSEL_SVE_Pd_SVE_Pg4_10_SME_PnT_Wm_imm {
    #[bits(4)]
    pub sve_pd: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(4)]
    pub sve_pn: u32,
    #[bits(1)]
    pub _op_9: u32,
    #[bits(4)]
    pub sve_pg4_10: u32,
    #[bits(2)]
    pub _op_14: u32,
    #[bits(2)]
    pub sme_rm: u32,
    #[bits(3)]
    pub sme_tszl: u32,
    #[bits(1)]
    pub _op_21: u32,
    #[bits(1)]
    pub sme_tszh: u32,
    #[bits(1)]
    pub sme_i1: u32,
    #[bits(8)]
    pub _op_24: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct PSEL_SVE_PNd_SVE_PNg4_10_SME_PnT_Wm_imm {
    #[bits(4)]
    pub sve_pd: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(4)]
    pub sve_pn: u32,
    #[bits(1)]
    pub _op_9: u32,
    #[bits(4)]
    pub sve_pg4_10: u32,
    #[bits(2)]
    pub _op_14: u32,
    #[bits(2)]
    pub sme_rm: u32,
    #[bits(3)]
    pub sme_tszl: u32,
    #[bits(1)]
    pub _op_21: u32,
    #[bits(1)]
    pub sme_tszh: u32,
    #[bits(1)]
    pub sme_i1: u32,
    #[bits(8)]
    pub _op_24: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct PTEST_SVE_Pg4_10_SVE_Pn {
    #[bits(5)]
    pub _op_0: u32,
    #[bits(4)]
    pub sve_pn: u32,
    #[bits(1)]
    pub _op_9: u32,
    #[bits(4)]
    pub sve_pg4_10: u32,
    #[bits(18)]
    pub _op_14: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct PTRUE_SME_PNd3 {
    #[bits(3)]
    pub sme_pnd3: u32,
    #[bits(29)]
    pub _op_3: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct PTRUE_SVE_Pd_SVE_PATTERN {
    #[bits(4)]
    pub sve_pd: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub sve_pattern: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct PTRUES_SVE_Pd_SVE_PATTERN {
    #[bits(4)]
    pub sve_pd: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub sve_pattern: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct PUNPKHI_SVE_Pd_SVE_Pn {
    #[bits(4)]
    pub sve_pd: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(4)]
    pub sve_pn: u32,
    #[bits(23)]
    pub _op_9: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct PUNPKLO_SVE_Pd_SVE_Pn {
    #[bits(4)]
    pub sve_pd: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(4)]
    pub sve_pn: u32,
    #[bits(23)]
    pub _op_9: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct RADDHN_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct RADDHN2_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct RADDHNB_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct RADDHNT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct RAX1_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct RAX1_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct RBIT_Rd_Rn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct RBIT_SVE_Zd_SVE_Pg3_SVE_Zn {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct RBIT_Vd_Vn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct RCWCAS_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct RCWCASA_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct RCWCASAL_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct RCWCASL_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct RCWCASP_Rs_PAIRREG_Rt_PAIRREG_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct RCWCASPA_Rs_PAIRREG_Rt_PAIRREG_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct RCWCASPAL_Rs_PAIRREG_Rt_PAIRREG_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct RCWCASPL_Rs_PAIRREG_Rt_PAIRREG_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct RCWCLR_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct RCWCLRA_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct RCWCLRAL_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct RCWCLRL_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct RCWCLRP_Rt_Rs_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct RCWCLRPA_Rt_Rs_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct RCWCLRPAL_Rt_Rs_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct RCWCLRPL_Rt_Rs_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct RCWSCAS_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct RCWSCASA_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct RCWSCASAL_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct RCWSCASL_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct RCWSCASP_Rs_PAIRREG_Rt_PAIRREG_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct RCWSCASPA_Rs_PAIRREG_Rt_PAIRREG_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct RCWSCASPAL_Rs_PAIRREG_Rt_PAIRREG_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct RCWSCASPL_Rs_PAIRREG_Rt_PAIRREG_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct RCWSCLR_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct RCWSCLRA_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct RCWSCLRAL_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct RCWSCLRL_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct RCWSCLRP_Rt_Rs_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct RCWSCLRPA_Rt_Rs_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct RCWSCLRPAL_Rt_Rs_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct RCWSCLRPL_Rt_Rs_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct RCWSET_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct RCWSETA_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct RCWSETAL_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct RCWSETL_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct RCWSETP_Rt_Rs_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct RCWSETPA_Rt_Rs_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct RCWSETPAL_Rt_Rs_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct RCWSETPL_Rt_Rs_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct RCWSSET_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct RCWSSETA_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct RCWSSETAL_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct RCWSSETL_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct RCWSSETP_Rt_Rs_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct RCWSSETPA_Rt_Rs_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct RCWSSETPAL_Rt_Rs_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct RCWSSETPL_Rt_Rs_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct RCWSSWP_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct RCWSSWPA_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct RCWSSWPAL_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct RCWSSWPL_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct RCWSSWPP_Rt_Rs_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct RCWSSWPPA_Rt_Rs_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct RCWSSWPPAL_Rt_Rs_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct RCWSSWPPL_Rt_Rs_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct RCWSWP_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct RCWSWPA_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct RCWSWPAL_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct RCWSWPL_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct RCWSWPP_Rt_Rs_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct RCWSWPPA_Rt_Rs_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct RCWSWPPAL_Rt_Rs_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct RCWSWPPL_Rt_Rs_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct RDFFR_SVE_Pd_SVE_Pg4_5 {
    #[bits(4)]
    pub sve_pd: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(4)]
    pub sve_pg4_5: u32,
    #[bits(23)]
    pub _op_9: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct RDFFR_SVE_Pd {
    #[bits(4)]
    pub sve_pd: u32,
    #[bits(28)]
    pub _op_4: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct RDFFRS_SVE_Pd_SVE_Pg4_5 {
    #[bits(4)]
    pub sve_pd: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(4)]
    pub sve_pg4_5: u32,
    #[bits(23)]
    pub _op_9: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct RDSVL_Rd_SVE_SIMM6 {
    #[bits(5)]
    pub rd: u32,
    #[bits(6)]
    pub sve_imms: u32,
    #[bits(21)]
    pub _op_11: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct RDVL_Rd_SVE_SIMM6 {
    #[bits(5)]
    pub rd: u32,
    #[bits(6)]
    pub sve_imms: u32,
    #[bits(21)]
    pub _op_11: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct RET_Rn {
    #[bits(5)]
    pub _op_0: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct RETAA {
    #[bits(32)]
    pub _op_0: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct RETAB {
    #[bits(32)]
    pub _op_0: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct REV_Rd_Rn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct REV_Rd_X_Rn_X {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct REV_SVE_Zd_SVE_Zn {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct REV_SVE_Pd_SVE_Pn {
    #[bits(4)]
    pub sve_pd: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(4)]
    pub sve_pn: u32,
    #[bits(23)]
    pub _op_9: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct REV16_Rd_Rn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct REV16_Vd_Vn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct REV32_Rd_Rn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct REV32_Vd_Vn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct REV64_Vd_Vn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct REVB_SVE_Zd_SVE_Pg3_SVE_Zn {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct REVD_SVE_Zd_SVE_Pg3_SVE_Zn {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct REVH_SVE_Zd_SVE_Pg3_SVE_Zn {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct REVW_SVE_Zd_SVE_Pg3_SVE_Zn {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct RMIF_Rn_IMM_2_MASK {
    #[bits(4)]
    pub imm4_0: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(5)]
    pub _op_10: u32,
    #[bits(6)]
    pub imm6_15: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct RORV_Rd_Rn_Rm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct RPRFM_RPRFMOP_Rm_SIMD_ADDR_SIMPLE {
    #[bits(3)]
    pub imm3_0: u32,
    #[bits(9)]
    pub _op_3: u32,
    #[bits(2)]
    pub imm2_12: u32,
    #[bits(1)]
    pub _op_14: u32,
    #[bits(1)]
    pub imm1_15: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct RSHRN_Vd_Vn_IMM_VLSR {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct RSHRN2_Vd_Vn_IMM_VLSR {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct RSHRNB_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(3)]
    pub sve_imm3: u32,
    #[bits(2)]
    pub sve_tszl_19: u32,
    #[bits(1)]
    pub _op_21: u32,
    #[bits(1)]
    pub sve_sz: u32,
    #[bits(9)]
    pub _op_23: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct RSHRNT_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(3)]
    pub sve_imm3: u32,
    #[bits(2)]
    pub sve_tszl_19: u32,
    #[bits(1)]
    pub _op_21: u32,
    #[bits(1)]
    pub sve_sz: u32,
    #[bits(9)]
    pub _op_23: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct RSUBHN_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct RSUBHN2_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct RSUBHNB_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct RSUBHNT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SABA_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SABA_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SABAL_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SABAL2_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SABALB_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SABALT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SABD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zm_5: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SABD_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SABDL_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SABDL2_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SABDLB_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SABDLT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SADALP_SVE_Zd_SVE_Pg3_SVE_Zn {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SADALP_Vd_Vn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SADDL_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SADDL2_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SADDLB_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SADDLBT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SADDLP_Vd_Vn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SADDLT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SADDLV_Fd_Vn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SADDV_SVE_Vd_SVE_Pg3_SVE_Zn {
    #[bits(5)]
    pub sve_vd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SADDW_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SADDW2_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SADDWB_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SADDWT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SB {
    #[bits(32)]
    pub _op_0: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SBC_Rd_Rn_Rm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SBCLB_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SBCLT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SBCS_Rd_Rn_Rm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SBFM_Rd_Rn_IMMR_IMMS {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub imm6_10: u32,
    #[bits(6)]
    pub immr: u32,
    #[bits(10)]
    pub _op_22: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SCLAMP_SME_Zdnx2_SVE_Zn_SVE_Zm_16 {
    #[bits(1)]
    pub _op_0: u32,
    #[bits(4)]
    pub sme_zdn2: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SCLAMP_SME_Zdnx4_SVE_Zn_SVE_Zm_16 {
    #[bits(2)]
    pub _op_0: u32,
    #[bits(3)]
    pub sme_zdn4: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SCLAMP_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SCVTF_SME_Zdnx2_SME_Znx2 {
    #[bits(1)]
    pub _op_0: u32,
    #[bits(4)]
    pub sme_zdn2: u32,
    #[bits(1)]
    pub _op_5: u32,
    #[bits(4)]
    pub sme_zn2: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SCVTF_SME_Zdnx4_SME_Znx4 {
    #[bits(2)]
    pub _op_0: u32,
    #[bits(3)]
    pub sme_zdn4: u32,
    #[bits(2)]
    pub _op_5: u32,
    #[bits(3)]
    pub sme_zn4: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SCVTF_SVE_Zd_SVE_Pg3_SVE_Zn {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SCVTF_SVE_Zd_S_S_SVE_Pg3_P_M_SVE_Zn_S_S {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SCVTF_SVE_Zd_S_H_SVE_Pg3_P_M_SVE_Zn_S_S {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SCVTF_SVE_Zd_S_S_SVE_Pg3_P_M_SVE_Zn_S_D {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SCVTF_SVE_Zd_S_H_SVE_Pg3_P_M_SVE_Zn_S_H {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SCVTF_SVE_Zd_S_H_SVE_Pg3_P_M_SVE_Zn_S_D {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SCVTF_SVE_Zd_S_D_SVE_Pg3_P_M_SVE_Zn_S_D {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SCVTF_Fd_Rn_FBITS {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub scale: u32,
    #[bits(16)]
    pub _op_16: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SCVTF_Fd_S_D_Rn_W_FBITS_imm_1_32 {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub scale: u32,
    #[bits(16)]
    pub _op_16: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SCVTF_Vd_Vn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SCVTF_Vd_V_4H_Vn_V_4H {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SCVTF_Fd_Rn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SCVTF_Fd_S_D_Rn_W {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SCVTF_Sd_Sn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SCVTF_Sd_S_H_Sn_S_H {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SCVTF_Vd_Vn_IMM_VLSR {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SCVTF_Vd_V_2S_Vn_V_2S_IMM_VLSR_V_2S {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SCVTF_Sd_Sn_IMM_VLSR {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SCVTF_Sd_S_S_Sn_S_S_IMM_VLSR_S_S {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SDIV_Rd_Rn_Rm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SDIV_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zm_5: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SDIVR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zm_5: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2 {
    #[bits(3)]
    pub imm3_0: u32,
    #[bits(3)]
    pub _op_3: u32,
    #[bits(4)]
    pub sme_zn2: u32,
    #[bits(2)]
    pub imm2_10: u32,
    #[bits(1)]
    pub _op_12: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SDOT_SME_ZA_array_off3_0_S_S_SME_Znx2_S_B_SME_Zm_INDEX2_S_B {
    #[bits(3)]
    pub imm3_0: u32,
    #[bits(3)]
    pub _op_3: u32,
    #[bits(4)]
    pub sme_zn2: u32,
    #[bits(2)]
    pub imm2_10: u32,
    #[bits(1)]
    pub _op_12: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2 {
    #[bits(3)]
    pub imm3_0: u32,
    #[bits(4)]
    pub _op_3: u32,
    #[bits(3)]
    pub sme_zn4: u32,
    #[bits(2)]
    pub imm2_10: u32,
    #[bits(1)]
    pub _op_12: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SDOT_SME_ZA_array_off3_0_S_S_SME_Znx4_S_B_SME_Zm_INDEX2_S_B {
    #[bits(3)]
    pub imm3_0: u32,
    #[bits(4)]
    pub _op_3: u32,
    #[bits(3)]
    pub sme_zn4: u32,
    #[bits(2)]
    pub imm2_10: u32,
    #[bits(1)]
    pub _op_12: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX1 {
    #[bits(3)]
    pub imm3_0: u32,
    #[bits(3)]
    pub _op_3: u32,
    #[bits(4)]
    pub sme_zn2: u32,
    #[bits(1)]
    pub imm1_10: u32,
    #[bits(2)]
    pub _op_11: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX1 {
    #[bits(3)]
    pub imm3_0: u32,
    #[bits(4)]
    pub _op_3: u32,
    #[bits(3)]
    pub sme_zn4: u32,
    #[bits(1)]
    pub imm1_10: u32,
    #[bits(2)]
    pub _op_11: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SDOT_SME_ZA_array_off3_0_SVE_ZnxN_SME_Zm {
    #[bits(3)]
    pub imm3_0: u32,
    #[bits(2)]
    pub _op_3: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SDOT_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_B_SME_Zm_S_B {
    #[bits(3)]
    pub imm3_0: u32,
    #[bits(2)]
    pub _op_3: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zmx2 {
    #[bits(3)]
    pub imm3_0: u32,
    #[bits(3)]
    pub _op_3: u32,
    #[bits(4)]
    pub sme_zn2: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(2)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm2: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zmx4 {
    #[bits(3)]
    pub imm3_0: u32,
    #[bits(4)]
    pub _op_3: u32,
    #[bits(3)]
    pub sme_zn4: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(3)]
    pub _op_15: u32,
    #[bits(3)]
    pub sme_zm4: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SDOT_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_H_SME_Zm_S_H {
    #[bits(3)]
    pub imm3_0: u32,
    #[bits(2)]
    pub _op_3: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SDOT_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_H_SME_Zm_S_H_c1701408 {
    #[bits(3)]
    pub imm3_0: u32,
    #[bits(2)]
    pub _op_3: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SDOT_SME_ZA_array_off3_0_S_S_SME_Znx2_S_H_SME_Zmx2_S_H {
    #[bits(3)]
    pub imm3_0: u32,
    #[bits(3)]
    pub _op_3: u32,
    #[bits(4)]
    pub sme_zn2: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(2)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm2: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SDOT_SME_ZA_array_off3_0_S_S_SME_Znx4_S_H_SME_Zmx4_S_H {
    #[bits(3)]
    pub imm3_0: u32,
    #[bits(4)]
    pub _op_3: u32,
    #[bits(3)]
    pub sme_zn4: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(3)]
    pub _op_15: u32,
    #[bits(3)]
    pub sme_zm4: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SDOT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SDOT_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SDOT_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SDOT_SVE_Zd_S_S_SVE_Zn_S_H_SVE_Zm_16_S_H {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SDOT_SVE_Zd_SVE_Zn_SVE_Zm3_19_INDEX {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(3)]
    pub sve_imm3: u32,
    #[bits(2)]
    pub imm2_19: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SDOT_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SDOT_Vd_Vn_Em {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SEL_SME_Zdnx2_SME_PNg3_SME_Znx2_SME_Zmx2 {
    #[bits(1)]
    pub _op_0: u32,
    #[bits(4)]
    pub sme_zdn2: u32,
    #[bits(1)]
    pub _op_5: u32,
    #[bits(4)]
    pub sme_zn2: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(4)]
    pub _op_13: u32,
    #[bits(4)]
    pub sme_zm2: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SEL_SME_Zdnx4_SME_PNg3_SME_Znx4_SME_Zmx4 {
    #[bits(2)]
    pub _op_0: u32,
    #[bits(3)]
    pub sme_zdn4: u32,
    #[bits(2)]
    pub _op_5: u32,
    #[bits(3)]
    pub sme_zn4: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(5)]
    pub _op_13: u32,
    #[bits(3)]
    pub sme_zm4: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SEL_SVE_Zd_SVE_Pg4_10_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(4)]
    pub sve_pg4_10: u32,
    #[bits(2)]
    pub _op_14: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SEL_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm {
    #[bits(4)]
    pub sve_pd: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(4)]
    pub sve_pn: u32,
    #[bits(1)]
    pub _op_9: u32,
    #[bits(4)]
    pub sve_pg4_10: u32,
    #[bits(2)]
    pub _op_14: u32,
    #[bits(4)]
    pub sve_pm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SETE_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SETEN_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SETET_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SETETN_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SETF16_Rn {
    #[bits(5)]
    pub _op_0: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SETF8_Rn {
    #[bits(5)]
    pub _op_0: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SETFFR {
    #[bits(32)]
    pub _op_0: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SETGE_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SETGEN_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SETGET_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SETGETN_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SETGM_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SETGMN_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SETGMT_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SETGMTN_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SETGP_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SETGPN_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SETGPT_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SETGPTN_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SETM_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SETMN_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SETMT_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SETMTN_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SETP_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SETPN_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SETPT_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SETPTN_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SHA1C_Fd_Fn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SHA1H_Fd_Fn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SHA1M_Fd_Fn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SHA1P_Fd_Fn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SHA1SU0_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SHA1SU1_Vd_Vn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SHA256H_Fd_Fn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SHA256H2_Fd_Fn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SHA256SU0_Vd_Vn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SHA256SU1_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SHA512H_Fd_Fn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SHA512H2_Fd_Fn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SHA512SU0_Vd_Vn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SHA512SU1_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SHADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SHADD_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SHL_Vd_Vn_IMM_VLSL {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SHL_Sd_Sn_IMM_VLSL {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SHLL_Vd_Vn_SHLL_IMM {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SHLL2_Vd_Vn_SHLL_IMM {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SHRN_Vd_Vn_IMM_VLSR {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SHRN2_Vd_Vn_IMM_VLSR {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SHRNB_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(3)]
    pub sve_imm3: u32,
    #[bits(2)]
    pub sve_tszl_19: u32,
    #[bits(1)]
    pub _op_21: u32,
    #[bits(1)]
    pub sve_sz: u32,
    #[bits(9)]
    pub _op_23: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SHRNT_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(3)]
    pub sve_imm3: u32,
    #[bits(2)]
    pub sve_tszl_19: u32,
    #[bits(1)]
    pub _op_21: u32,
    #[bits(1)]
    pub sve_sz: u32,
    #[bits(9)]
    pub _op_23: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SHSUB_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SHSUB_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SHSUBR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SLI_SVE_Zd_SVE_Zn_SVE_SHLIMM_UNPRED {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub imm5: u32,
    #[bits(1)]
    pub _op_21: u32,
    #[bits(2)]
    pub sve_tszh: u32,
    #[bits(8)]
    pub _op_24: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SLI_Vd_Vn_IMM_VLSL {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SLI_Sd_Sn_IMM_VLSL {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SM3PARTW1_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SM3PARTW2_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SM3SS1_Vd_Vn_Vm_Va {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(5)]
    pub ra: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SM3TT1A_Vd_Vn_Em {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SM3TT1B_Vd_Vn_Em {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SM3TT2A_Vd_Vn_Em {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SM3TT2B_Vd_Vn_Em {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SM4E_SVE_Zd_SVE_Zd_SVE_Zn {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SM4E_Vd_Vn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SM4EKEY_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SM4EKEY_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SMADDL_Rd_Rn_Rm_Ra {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(5)]
    pub ra: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SMAX_SME_Zdnx2_SME_Zdnx2_SME_Zm {
    #[bits(1)]
    pub _op_0: u32,
    #[bits(4)]
    pub sme_zdn2: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SMAX_SME_Zdnx2_SME_Zdnx2_SME_Zmx2 {
    #[bits(1)]
    pub _op_0: u32,
    #[bits(4)]
    pub sme_zdn2: u32,
    #[bits(12)]
    pub _op_5: u32,
    #[bits(4)]
    pub sme_zm2: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SMAX_SME_Zdnx4_SME_Zdnx4_SME_Zm {
    #[bits(2)]
    pub _op_0: u32,
    #[bits(3)]
    pub sme_zdn4: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SMAX_SME_Zdnx4_SME_Zdnx4_SME_Zmx4 {
    #[bits(2)]
    pub _op_0: u32,
    #[bits(3)]
    pub sme_zdn4: u32,
    #[bits(13)]
    pub _op_5: u32,
    #[bits(3)]
    pub sme_zm4: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SMAX_Rd_Rn_CSSC_SIMM8 {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(8)]
    pub cssc_imm8: u32,
    #[bits(14)]
    pub _op_18: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SMAX_Rd_Rn_Rm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SMAX_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zm_5: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SMAX_SVE_Zd_SVE_Zd_SVE_SIMM8 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(8)]
    pub sve_imm8: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SMAX_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SMAXP_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SMAXP_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SMAXQV_Vd_SVE_Pg3_SVE_Zn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SMAXV_SVE_Vd_SVE_Pg3_SVE_Zn {
    #[bits(5)]
    pub sve_vd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SMAXV_Fd_Vn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SMC_EXCEPTION {
    #[bits(5)]
    pub _op_0: u32,
    #[bits(16)]
    pub imm16_5: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SMIN_SME_Zdnx2_SME_Zdnx2_SME_Zm {
    #[bits(1)]
    pub _op_0: u32,
    #[bits(4)]
    pub sme_zdn2: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SMIN_SME_Zdnx2_SME_Zdnx2_SME_Zmx2 {
    #[bits(1)]
    pub _op_0: u32,
    #[bits(4)]
    pub sme_zdn2: u32,
    #[bits(12)]
    pub _op_5: u32,
    #[bits(4)]
    pub sme_zm2: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SMIN_SME_Zdnx4_SME_Zdnx4_SME_Zm {
    #[bits(2)]
    pub _op_0: u32,
    #[bits(3)]
    pub sme_zdn4: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SMIN_SME_Zdnx4_SME_Zdnx4_SME_Zmx4 {
    #[bits(2)]
    pub _op_0: u32,
    #[bits(3)]
    pub sme_zdn4: u32,
    #[bits(13)]
    pub _op_5: u32,
    #[bits(3)]
    pub sme_zm4: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SMIN_Rd_Rn_CSSC_SIMM8 {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(8)]
    pub cssc_imm8: u32,
    #[bits(14)]
    pub _op_18: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SMIN_Rd_Rn_Rm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SMIN_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zm_5: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SMIN_SVE_Zd_SVE_Zd_SVE_SIMM8 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(8)]
    pub sve_imm8: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SMIN_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SMINP_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SMINP_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SMINQV_Vd_SVE_Pg3_SVE_Zn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SMINV_SVE_Vd_SVE_Pg3_SVE_Zn {
    #[bits(5)]
    pub sve_vd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SMINV_Fd_Vn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SMLAL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm_INDEX3_10 {
    #[bits(3)]
    pub imm3_0: u32,
    #[bits(2)]
    pub _op_3: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(2)]
    pub imm2_10: u32,
    #[bits(1)]
    pub _op_12: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub imm1_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SMLAL_SME_ZA_array_off2x2_SME_Znx2_SME_Zm_INDEX3_2 {
    #[bits(2)]
    pub imm2_0: u32,
    #[bits(1)]
    pub imm1_2: u32,
    #[bits(3)]
    pub _op_3: u32,
    #[bits(4)]
    pub sme_zn2: u32,
    #[bits(2)]
    pub imm2_10: u32,
    #[bits(1)]
    pub _op_12: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SMLAL_SME_ZA_array_off2x2_SME_Znx4_SME_Zm_INDEX3_2 {
    #[bits(2)]
    pub imm2_0: u32,
    #[bits(1)]
    pub imm1_2: u32,
    #[bits(4)]
    pub _op_3: u32,
    #[bits(3)]
    pub sme_zn4: u32,
    #[bits(2)]
    pub imm2_10: u32,
    #[bits(1)]
    pub _op_12: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SMLAL_SME_ZA_array_off2x2_SVE_ZnxN_SME_Zm {
    #[bits(2)]
    pub imm2_0: u32,
    #[bits(3)]
    pub _op_2: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SMLAL_SME_ZA_array_off2x2_S_S_SVE_ZnxN_S_H_SME_Zm_S_H {
    #[bits(2)]
    pub imm2_0: u32,
    #[bits(3)]
    pub _op_2: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SMLAL_SME_ZA_array_off2x2_SME_Znx2_SME_Zmx2 {
    #[bits(2)]
    pub imm2_0: u32,
    #[bits(4)]
    pub _op_2: u32,
    #[bits(4)]
    pub sme_zn2: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(2)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm2: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SMLAL_SME_ZA_array_off2x2_SME_Znx4_SME_Zmx4 {
    #[bits(2)]
    pub imm2_0: u32,
    #[bits(5)]
    pub _op_2: u32,
    #[bits(3)]
    pub sme_zn4: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(3)]
    pub _op_15: u32,
    #[bits(3)]
    pub sme_zm4: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SMLAL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm {
    #[bits(3)]
    pub imm3_0: u32,
    #[bits(2)]
    pub _op_3: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SMLAL_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SMLAL_Vd_Vn_Em16 {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SMLAL2_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SMLAL2_Vd_Vn_Em16 {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SMLALB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(1)]
    pub _op_10: u32,
    #[bits(1)]
    pub sve_i3l: u32,
    #[bits(4)]
    pub _op_12: u32,
    #[bits(3)]
    pub sve_imm3: u32,
    #[bits(2)]
    pub sve_i3h2: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SMLALB_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(1)]
    pub _op_10: u32,
    #[bits(1)]
    pub sve_i3l: u32,
    #[bits(4)]
    pub _op_12: u32,
    #[bits(4)]
    pub sve_imm4: u32,
    #[bits(1)]
    pub sve_i2h: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SMLALB_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SMLALL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm_INDEX4_10 {
    #[bits(2)]
    pub imm2_0: u32,
    #[bits(3)]
    pub _op_2: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub imm3_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub imm1_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SMLALL_SME_ZA_array_off1x4_SME_Znx2_SME_Zm_INDEX4_1 {
    #[bits(1)]
    pub imm1_0: u32,
    #[bits(2)]
    pub imm2_1: u32,
    #[bits(3)]
    pub _op_3: u32,
    #[bits(4)]
    pub sme_zn2: u32,
    #[bits(2)]
    pub imm2_10: u32,
    #[bits(1)]
    pub _op_12: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SMLALL_SME_ZA_array_off1x4_SME_Znx4_SME_Zm_INDEX4_1 {
    #[bits(1)]
    pub imm1_0: u32,
    #[bits(2)]
    pub imm2_1: u32,
    #[bits(4)]
    pub _op_3: u32,
    #[bits(3)]
    pub sme_zn4: u32,
    #[bits(2)]
    pub imm2_10: u32,
    #[bits(1)]
    pub _op_12: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SMLALL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm_INDEX3_10 {
    #[bits(2)]
    pub imm2_0: u32,
    #[bits(3)]
    pub _op_2: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(2)]
    pub imm2_10: u32,
    #[bits(1)]
    pub _op_12: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub imm1_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SMLALL_SME_ZA_array_off1x4_SME_Znx2_SME_Zm_INDEX3_1 {
    #[bits(1)]
    pub imm1_0: u32,
    #[bits(2)]
    pub imm2_1: u32,
    #[bits(3)]
    pub _op_3: u32,
    #[bits(4)]
    pub sme_zn2: u32,
    #[bits(1)]
    pub imm1_10: u32,
    #[bits(2)]
    pub _op_11: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SMLALL_SME_ZA_array_off1x4_SME_Znx4_SME_Zm_INDEX3_1 {
    #[bits(1)]
    pub imm1_0: u32,
    #[bits(2)]
    pub imm2_1: u32,
    #[bits(4)]
    pub _op_3: u32,
    #[bits(3)]
    pub sme_zn4: u32,
    #[bits(1)]
    pub imm1_10: u32,
    #[bits(2)]
    pub _op_11: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SMLALL_SME_ZA_array_off1x4_SVE_ZnxN_SME_Zm {
    #[bits(1)]
    pub imm1_0: u32,
    #[bits(4)]
    pub _op_1: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SMLALL_SME_ZA_array_off1x4_S_S_SVE_ZnxN_S_B_SME_Zm_S_B {
    #[bits(1)]
    pub imm1_0: u32,
    #[bits(4)]
    pub _op_1: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SMLALL_SME_ZA_array_off1x4_SME_Znx2_SME_Zmx2 {
    #[bits(1)]
    pub imm1_0: u32,
    #[bits(5)]
    pub _op_1: u32,
    #[bits(4)]
    pub sme_zn2: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(2)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm2: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SMLALL_SME_ZA_array_off1x4_SME_Znx4_SME_Zmx4 {
    #[bits(1)]
    pub imm1_0: u32,
    #[bits(6)]
    pub _op_1: u32,
    #[bits(3)]
    pub sme_zn4: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(3)]
    pub _op_15: u32,
    #[bits(3)]
    pub sme_zm4: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SMLALL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm {
    #[bits(2)]
    pub imm2_0: u32,
    #[bits(3)]
    pub _op_2: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SMLALT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(1)]
    pub _op_10: u32,
    #[bits(1)]
    pub sve_i3l: u32,
    #[bits(4)]
    pub _op_12: u32,
    #[bits(3)]
    pub sve_imm3: u32,
    #[bits(2)]
    pub sve_i3h2: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SMLALT_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(1)]
    pub _op_10: u32,
    #[bits(1)]
    pub sve_i3l: u32,
    #[bits(4)]
    pub _op_12: u32,
    #[bits(4)]
    pub sve_imm4: u32,
    #[bits(1)]
    pub sve_i2h: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SMLALT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SMLSL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm_INDEX3_10 {
    #[bits(3)]
    pub imm3_0: u32,
    #[bits(2)]
    pub _op_3: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(2)]
    pub imm2_10: u32,
    #[bits(1)]
    pub _op_12: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub imm1_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SMLSL_SME_ZA_array_off2x2_SME_Znx2_SME_Zm_INDEX3_2 {
    #[bits(2)]
    pub imm2_0: u32,
    #[bits(1)]
    pub imm1_2: u32,
    #[bits(3)]
    pub _op_3: u32,
    #[bits(4)]
    pub sme_zn2: u32,
    #[bits(2)]
    pub imm2_10: u32,
    #[bits(1)]
    pub _op_12: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SMLSL_SME_ZA_array_off2x2_SME_Znx4_SME_Zm_INDEX3_2 {
    #[bits(2)]
    pub imm2_0: u32,
    #[bits(1)]
    pub imm1_2: u32,
    #[bits(4)]
    pub _op_3: u32,
    #[bits(3)]
    pub sme_zn4: u32,
    #[bits(2)]
    pub imm2_10: u32,
    #[bits(1)]
    pub _op_12: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SMLSL_SME_ZA_array_off2x2_SVE_ZnxN_SME_Zm {
    #[bits(2)]
    pub imm2_0: u32,
    #[bits(3)]
    pub _op_2: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SMLSL_SME_ZA_array_off2x2_S_S_SVE_ZnxN_S_H_SME_Zm_S_H {
    #[bits(2)]
    pub imm2_0: u32,
    #[bits(3)]
    pub _op_2: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SMLSL_SME_ZA_array_off2x2_SME_Znx2_SME_Zmx2 {
    #[bits(2)]
    pub imm2_0: u32,
    #[bits(4)]
    pub _op_2: u32,
    #[bits(4)]
    pub sme_zn2: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(2)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm2: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SMLSL_SME_ZA_array_off2x2_SME_Znx4_SME_Zmx4 {
    #[bits(2)]
    pub imm2_0: u32,
    #[bits(5)]
    pub _op_2: u32,
    #[bits(3)]
    pub sme_zn4: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(3)]
    pub _op_15: u32,
    #[bits(3)]
    pub sme_zm4: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SMLSL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm {
    #[bits(3)]
    pub imm3_0: u32,
    #[bits(2)]
    pub _op_3: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SMLSL_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SMLSL_Vd_Vn_Em16 {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SMLSL2_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SMLSL2_Vd_Vn_Em16 {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SMLSLB_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SMLSLB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(1)]
    pub _op_10: u32,
    #[bits(1)]
    pub sve_i3l: u32,
    #[bits(4)]
    pub _op_12: u32,
    #[bits(3)]
    pub sve_imm3: u32,
    #[bits(2)]
    pub sve_i3h2: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SMLSLB_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(1)]
    pub _op_10: u32,
    #[bits(1)]
    pub sve_i3l: u32,
    #[bits(4)]
    pub _op_12: u32,
    #[bits(4)]
    pub sve_imm4: u32,
    #[bits(1)]
    pub sve_i2h: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SMLSLL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm_INDEX4_10 {
    #[bits(2)]
    pub imm2_0: u32,
    #[bits(3)]
    pub _op_2: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub imm3_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub imm1_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SMLSLL_SME_ZA_array_off1x4_SME_Znx2_SME_Zm_INDEX4_1 {
    #[bits(1)]
    pub imm1_0: u32,
    #[bits(2)]
    pub imm2_1: u32,
    #[bits(3)]
    pub _op_3: u32,
    #[bits(4)]
    pub sme_zn2: u32,
    #[bits(2)]
    pub imm2_10: u32,
    #[bits(1)]
    pub _op_12: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SMLSLL_SME_ZA_array_off1x4_SME_Znx4_SME_Zm_INDEX4_1 {
    #[bits(1)]
    pub imm1_0: u32,
    #[bits(2)]
    pub imm2_1: u32,
    #[bits(4)]
    pub _op_3: u32,
    #[bits(3)]
    pub sme_zn4: u32,
    #[bits(2)]
    pub imm2_10: u32,
    #[bits(1)]
    pub _op_12: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SMLSLL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm_INDEX3_10 {
    #[bits(2)]
    pub imm2_0: u32,
    #[bits(3)]
    pub _op_2: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(2)]
    pub imm2_10: u32,
    #[bits(1)]
    pub _op_12: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub imm1_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SMLSLL_SME_ZA_array_off1x4_SME_Znx2_SME_Zm_INDEX3_1 {
    #[bits(1)]
    pub imm1_0: u32,
    #[bits(2)]
    pub imm2_1: u32,
    #[bits(3)]
    pub _op_3: u32,
    #[bits(4)]
    pub sme_zn2: u32,
    #[bits(1)]
    pub imm1_10: u32,
    #[bits(2)]
    pub _op_11: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SMLSLL_SME_ZA_array_off1x4_SME_Znx4_SME_Zm_INDEX3_1 {
    #[bits(1)]
    pub imm1_0: u32,
    #[bits(2)]
    pub imm2_1: u32,
    #[bits(4)]
    pub _op_3: u32,
    #[bits(3)]
    pub sme_zn4: u32,
    #[bits(1)]
    pub imm1_10: u32,
    #[bits(2)]
    pub _op_11: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SMLSLL_SME_ZA_array_off1x4_SVE_ZnxN_SME_Zm {
    #[bits(1)]
    pub imm1_0: u32,
    #[bits(4)]
    pub _op_1: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SMLSLL_SME_ZA_array_off1x4_S_S_SVE_ZnxN_S_B_SME_Zm_S_B {
    #[bits(1)]
    pub imm1_0: u32,
    #[bits(4)]
    pub _op_1: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SMLSLL_SME_ZA_array_off1x4_SME_Znx2_SME_Zmx2 {
    #[bits(1)]
    pub imm1_0: u32,
    #[bits(5)]
    pub _op_1: u32,
    #[bits(4)]
    pub sme_zn2: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(2)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm2: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SMLSLL_SME_ZA_array_off1x4_SME_Znx4_SME_Zmx4 {
    #[bits(1)]
    pub imm1_0: u32,
    #[bits(6)]
    pub _op_1: u32,
    #[bits(3)]
    pub sme_zn4: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(3)]
    pub _op_15: u32,
    #[bits(3)]
    pub sme_zm4: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SMLSLL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm {
    #[bits(2)]
    pub imm2_0: u32,
    #[bits(3)]
    pub _op_2: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SMLSLT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SMLSLT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(1)]
    pub _op_10: u32,
    #[bits(1)]
    pub sve_i3l: u32,
    #[bits(4)]
    pub _op_12: u32,
    #[bits(3)]
    pub sve_imm3: u32,
    #[bits(2)]
    pub sve_i3h2: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SMLSLT_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(1)]
    pub _op_10: u32,
    #[bits(1)]
    pub sve_i3l: u32,
    #[bits(4)]
    pub _op_12: u32,
    #[bits(4)]
    pub sve_imm4: u32,
    #[bits(1)]
    pub sve_i2h: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SMMLA_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SMMLA_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SMOPA_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16 {
    #[bits(2)]
    pub sme_zada_2b: u32,
    #[bits(3)]
    pub _op_2: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub sme_pm: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SMOPA_SME_ZAda_2b_S_S_SVE_Pg3_P_M_SME_Pm_P_M_SVE_Zn_S_H_SVE_Zm_16_S_H {
    #[bits(2)]
    pub sme_zada_2b: u32,
    #[bits(3)]
    pub _op_2: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub sme_pm: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SMOPA_SME_ZAda_3b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16 {
    #[bits(3)]
    pub sme_zada_3b: u32,
    #[bits(2)]
    pub _op_3: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub sme_pm: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SMOPS_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16 {
    #[bits(2)]
    pub sme_zada_2b: u32,
    #[bits(3)]
    pub _op_2: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub sme_pm: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SMOPS_SME_ZAda_2b_S_S_SVE_Pg3_P_M_SME_Pm_P_M_SVE_Zn_S_H_SVE_Zm_16_S_H {
    #[bits(2)]
    pub sme_zada_2b: u32,
    #[bits(3)]
    pub _op_2: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub sme_pm: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SMOPS_SME_ZAda_3b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16 {
    #[bits(3)]
    pub sme_zada_3b: u32,
    #[bits(2)]
    pub _op_3: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub sme_pm: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SMOV_Rd_En {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SMSTART {
    #[bits(32)]
    pub _op_0: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SMSTART_SME_SM_ZA {
    #[bits(8)]
    pub _op_0: u32,
    #[bits(4)]
    pub crm: u32,
    #[bits(20)]
    pub _op_12: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SMSTOP {
    #[bits(32)]
    pub _op_0: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SMSTOP_SME_SM_ZA {
    #[bits(8)]
    pub _op_0: u32,
    #[bits(4)]
    pub crm: u32,
    #[bits(20)]
    pub _op_12: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SMSUBL_Rd_Rn_Rm_Ra {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(5)]
    pub ra: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SMULH_Rd_Rn_Rm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SMULH_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zm_5: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SMULH_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SMULL_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SMULL_Vd_Vn_Em16 {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SMULL2_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SMULL2_Vd_Vn_Em16 {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SMULLB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(1)]
    pub _op_10: u32,
    #[bits(1)]
    pub sve_i3l: u32,
    #[bits(4)]
    pub _op_12: u32,
    #[bits(3)]
    pub sve_imm3: u32,
    #[bits(2)]
    pub sve_i3h2: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SMULLB_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(1)]
    pub _op_10: u32,
    #[bits(1)]
    pub sve_i3l: u32,
    #[bits(4)]
    pub _op_12: u32,
    #[bits(4)]
    pub sve_imm4: u32,
    #[bits(1)]
    pub sve_i2h: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SMULLB_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SMULLT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(1)]
    pub _op_10: u32,
    #[bits(1)]
    pub sve_i3l: u32,
    #[bits(4)]
    pub _op_12: u32,
    #[bits(3)]
    pub sve_imm3: u32,
    #[bits(2)]
    pub sve_i3h2: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SMULLT_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(1)]
    pub _op_10: u32,
    #[bits(1)]
    pub sve_i3l: u32,
    #[bits(4)]
    pub _op_12: u32,
    #[bits(4)]
    pub sve_imm4: u32,
    #[bits(1)]
    pub sve_i2h: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SMULLT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SPLICE_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zm_5: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SPLICE_SVE_Zd_SVE_Pg3_SVE_ZnxN {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQABS_SVE_Zd_SVE_Pg3_SVE_Zn {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQABS_Vd_Vn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQABS_Sd_Sn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQADD_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQADD_SVE_Zd_SVE_Zd_SVE_AIMM {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(9)]
    pub sve_imm9: u32,
    #[bits(18)]
    pub _op_14: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQADD_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQADD_Sd_Sn_Sm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQCADD_SVE_Zd_SVE_Zd_SVE_Zn_SVE_IMM_ROT3 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(1)]
    pub sve_rot3: u32,
    #[bits(21)]
    pub _op_11: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQCVT_SVE_Zd_SME_Znx2 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(1)]
    pub _op_5: u32,
    #[bits(4)]
    pub sme_zn2: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQCVT_SVE_Zd_SME_Znx4 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(2)]
    pub _op_5: u32,
    #[bits(3)]
    pub sme_zn4: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQCVTN_SVE_Zd_SME_Znx4 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(2)]
    pub _op_5: u32,
    #[bits(3)]
    pub sme_zn4: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQCVTN_SVE_Zd_SME_Znx2 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(1)]
    pub _op_5: u32,
    #[bits(4)]
    pub sme_zn2: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQCVTU_SVE_Zd_SME_Znx2 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(1)]
    pub _op_5: u32,
    #[bits(4)]
    pub sme_zn2: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQCVTU_SVE_Zd_SME_Znx4 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(2)]
    pub _op_5: u32,
    #[bits(3)]
    pub sme_zn4: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQCVTUN_SVE_Zd_SME_Znx4 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(2)]
    pub _op_5: u32,
    #[bits(3)]
    pub sme_zn4: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQCVTUN_SVE_Zd_SME_Znx2 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(1)]
    pub _op_5: u32,
    #[bits(4)]
    pub sme_zn2: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQDECB_Rd_Rd_SVE_PATTERN_SCALED {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub sve_pattern: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQDECB_Rd_SVE_PATTERN_SCALED {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub sve_pattern: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQDECD_SVE_Zd_SVE_PATTERN_SCALED {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_pattern: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQDECD_Rd_Rd_SVE_PATTERN_SCALED {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub sve_pattern: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQDECD_Rd_SVE_PATTERN_SCALED {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub sve_pattern: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQDECH_SVE_Zd_SVE_PATTERN_SCALED {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_pattern: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQDECH_Rd_Rd_SVE_PATTERN_SCALED {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub sve_pattern: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQDECH_Rd_SVE_PATTERN_SCALED {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub sve_pattern: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQDECP_SVE_Zd_SVE_Pg4_5 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(4)]
    pub sve_pg4_5: u32,
    #[bits(23)]
    pub _op_9: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQDECP_Rd_SVE_Pg4_5_Rd {
    #[bits(5)]
    pub rd: u32,
    #[bits(4)]
    pub sve_pg4_5: u32,
    #[bits(23)]
    pub _op_9: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQDECP_Rd_SVE_Pg4_5 {
    #[bits(5)]
    pub rd: u32,
    #[bits(4)]
    pub sve_pg4_5: u32,
    #[bits(23)]
    pub _op_9: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQDECW_SVE_Zd_SVE_PATTERN_SCALED {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_pattern: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQDECW_Rd_Rd_SVE_PATTERN_SCALED {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub sve_pattern: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQDECW_Rd_SVE_PATTERN_SCALED {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub sve_pattern: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQDMLAL_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQDMLAL_Sd_Sn_Sm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQDMLAL_Vd_Vn_Em16 {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQDMLAL_Sd_Sn_Em16 {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQDMLAL2_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQDMLAL2_Vd_Vn_Em16 {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQDMLALB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(1)]
    pub _op_10: u32,
    #[bits(1)]
    pub sve_i3l: u32,
    #[bits(4)]
    pub _op_12: u32,
    #[bits(3)]
    pub sve_imm3: u32,
    #[bits(2)]
    pub sve_i3h2: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQDMLALB_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(1)]
    pub _op_10: u32,
    #[bits(1)]
    pub sve_i3l: u32,
    #[bits(4)]
    pub _op_12: u32,
    #[bits(4)]
    pub sve_imm4: u32,
    #[bits(1)]
    pub sve_i2h: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQDMLALB_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQDMLALBT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQDMLALT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(1)]
    pub _op_10: u32,
    #[bits(1)]
    pub sve_i3l: u32,
    #[bits(4)]
    pub _op_12: u32,
    #[bits(3)]
    pub sve_imm3: u32,
    #[bits(2)]
    pub sve_i3h2: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQDMLALT_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(1)]
    pub _op_10: u32,
    #[bits(1)]
    pub sve_i3l: u32,
    #[bits(4)]
    pub _op_12: u32,
    #[bits(4)]
    pub sve_imm4: u32,
    #[bits(1)]
    pub sve_i2h: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQDMLALT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQDMLSL_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQDMLSL_Sd_Sn_Sm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQDMLSL_Vd_Vn_Em16 {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQDMLSL_Sd_Sn_Em16 {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQDMLSL2_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQDMLSL2_Vd_Vn_Em16 {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQDMLSLB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(1)]
    pub _op_10: u32,
    #[bits(1)]
    pub sve_i3l: u32,
    #[bits(4)]
    pub _op_12: u32,
    #[bits(3)]
    pub sve_imm3: u32,
    #[bits(2)]
    pub sve_i3h2: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQDMLSLB_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(1)]
    pub _op_10: u32,
    #[bits(1)]
    pub sve_i3l: u32,
    #[bits(4)]
    pub _op_12: u32,
    #[bits(4)]
    pub sve_imm4: u32,
    #[bits(1)]
    pub sve_i2h: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQDMLSLB_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQDMLSLBT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQDMLSLT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(1)]
    pub _op_10: u32,
    #[bits(1)]
    pub sve_i3l: u32,
    #[bits(4)]
    pub _op_12: u32,
    #[bits(3)]
    pub sve_imm3: u32,
    #[bits(2)]
    pub sve_i3h2: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQDMLSLT_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(1)]
    pub _op_10: u32,
    #[bits(1)]
    pub sve_i3l: u32,
    #[bits(4)]
    pub _op_12: u32,
    #[bits(4)]
    pub sve_imm4: u32,
    #[bits(1)]
    pub sve_i2h: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQDMLSLT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQDMULH_SME_Zdnx2_SME_Zdnx2_SME_Zm {
    #[bits(1)]
    pub _op_0: u32,
    #[bits(4)]
    pub sme_zdn2: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQDMULH_SME_Zdnx2_SME_Zdnx2_SME_Zmx2 {
    #[bits(1)]
    pub _op_0: u32,
    #[bits(4)]
    pub sme_zdn2: u32,
    #[bits(12)]
    pub _op_5: u32,
    #[bits(4)]
    pub sme_zm2: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQDMULH_SME_Zdnx4_SME_Zdnx4_SME_Zm {
    #[bits(2)]
    pub _op_0: u32,
    #[bits(3)]
    pub sme_zdn4: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQDMULH_SME_Zdnx4_SME_Zdnx4_SME_Zmx4 {
    #[bits(2)]
    pub _op_0: u32,
    #[bits(3)]
    pub sme_zdn4: u32,
    #[bits(13)]
    pub _op_5: u32,
    #[bits(3)]
    pub sme_zm4: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQDMULH_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQDMULH_SVE_Zd_SVE_Zn_SVE_Zm3_22_INDEX {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(1)]
    pub _op_21: u32,
    #[bits(1)]
    pub sve_i3h: u32,
    #[bits(9)]
    pub _op_23: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQDMULH_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQDMULH_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQDMULH_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQDMULH_Sd_Sn_Sm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQDMULH_Vd_Vn_Em16 {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQDMULH_Sd_Sn_Em16 {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQDMULL_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQDMULL_Sd_Sn_Sm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQDMULL_Vd_Vn_Em16 {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQDMULL_Sd_Sn_Em16 {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQDMULL2_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQDMULL2_Vd_Vn_Em16 {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQDMULLB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(1)]
    pub _op_10: u32,
    #[bits(1)]
    pub sve_i3l: u32,
    #[bits(4)]
    pub _op_12: u32,
    #[bits(3)]
    pub sve_imm3: u32,
    #[bits(2)]
    pub sve_i3h2: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQDMULLB_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(1)]
    pub _op_10: u32,
    #[bits(1)]
    pub sve_i3l: u32,
    #[bits(4)]
    pub _op_12: u32,
    #[bits(4)]
    pub sve_imm4: u32,
    #[bits(1)]
    pub sve_i2h: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQDMULLB_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQDMULLT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(1)]
    pub _op_10: u32,
    #[bits(1)]
    pub sve_i3l: u32,
    #[bits(4)]
    pub _op_12: u32,
    #[bits(3)]
    pub sve_imm3: u32,
    #[bits(2)]
    pub sve_i3h2: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQDMULLT_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(1)]
    pub _op_10: u32,
    #[bits(1)]
    pub sve_i3l: u32,
    #[bits(4)]
    pub _op_12: u32,
    #[bits(4)]
    pub sve_imm4: u32,
    #[bits(1)]
    pub sve_i2h: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQDMULLT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQINCB_Rd_Rd_SVE_PATTERN_SCALED {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub sve_pattern: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQINCB_Rd_SVE_PATTERN_SCALED {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub sve_pattern: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQINCD_SVE_Zd_SVE_PATTERN_SCALED {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_pattern: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQINCD_Rd_Rd_SVE_PATTERN_SCALED {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub sve_pattern: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQINCD_Rd_SVE_PATTERN_SCALED {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub sve_pattern: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQINCH_SVE_Zd_SVE_PATTERN_SCALED {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_pattern: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQINCH_Rd_Rd_SVE_PATTERN_SCALED {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub sve_pattern: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQINCH_Rd_SVE_PATTERN_SCALED {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub sve_pattern: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQINCP_SVE_Zd_SVE_Pg4_5 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(4)]
    pub sve_pg4_5: u32,
    #[bits(23)]
    pub _op_9: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQINCP_Rd_SVE_Pg4_5_Rd {
    #[bits(5)]
    pub rd: u32,
    #[bits(4)]
    pub sve_pg4_5: u32,
    #[bits(23)]
    pub _op_9: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQINCP_Rd_SVE_Pg4_5 {
    #[bits(5)]
    pub rd: u32,
    #[bits(4)]
    pub sve_pg4_5: u32,
    #[bits(23)]
    pub _op_9: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQINCW_SVE_Zd_SVE_PATTERN_SCALED {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_pattern: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQINCW_Rd_Rd_SVE_PATTERN_SCALED {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub sve_pattern: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQINCW_Rd_SVE_PATTERN_SCALED {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub sve_pattern: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQNEG_SVE_Zd_SVE_Pg3_SVE_Zn {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQNEG_Vd_Vn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQNEG_Sd_Sn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQRDCMLAH_SVE_Zd_SVE_Zn_SVE_Zm_16_SVE_IMM_ROT2 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(2)]
    pub sve_rot2: u32,
    #[bits(4)]
    pub _op_12: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQRDCMLAH_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX_SVE_IMM_ROT2 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(2)]
    pub sve_rot2: u32,
    #[bits(4)]
    pub _op_12: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQRDCMLAH_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX_SVE_IMM_ROT2 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(2)]
    pub sve_rot2: u32,
    #[bits(4)]
    pub _op_12: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQRDMLAH_SVE_Zd_SVE_Zn_SVE_Zm3_22_INDEX {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(1)]
    pub _op_21: u32,
    #[bits(1)]
    pub sve_i3h: u32,
    #[bits(9)]
    pub _op_23: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQRDMLAH_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQRDMLAH_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQRDMLAH_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQRDMLAH_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQRDMLAH_Sd_Sn_Sm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQRDMLAH_Vd_Vn_Em16 {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQRDMLAH_Sd_Sn_Em16 {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQRDMLSH_SVE_Zd_SVE_Zn_SVE_Zm3_22_INDEX {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(1)]
    pub _op_21: u32,
    #[bits(1)]
    pub sve_i3h: u32,
    #[bits(9)]
    pub _op_23: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQRDMLSH_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQRDMLSH_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQRDMLSH_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQRDMLSH_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQRDMLSH_Sd_Sn_Sm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQRDMLSH_Vd_Vn_Em16 {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQRDMLSH_Sd_Sn_Em16 {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQRDMULH_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQRDMULH_SVE_Zd_SVE_Zn_SVE_Zm3_22_INDEX {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(1)]
    pub _op_21: u32,
    #[bits(1)]
    pub sve_i3h: u32,
    #[bits(9)]
    pub _op_23: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQRDMULH_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQRDMULH_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQRDMULH_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQRDMULH_Sd_Sn_Sm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQRDMULH_Vd_Vn_Em16 {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQRDMULH_Sd_Sn_Em16 {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQRSHL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQRSHL_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQRSHL_Sd_Sn_Sm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQRSHLR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQRSHR_SVE_Zd_SME_Znx4_SME_SHRIMM5 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(2)]
    pub _op_5: u32,
    #[bits(3)]
    pub sme_zn4: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_imm5b: u32,
    #[bits(1)]
    pub _op_21: u32,
    #[bits(2)]
    pub sve_tszh: u32,
    #[bits(8)]
    pub _op_24: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQRSHR_SVE_Zd_SME_Znx2_SME_SHRIMM4 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(1)]
    pub _op_5: u32,
    #[bits(4)]
    pub sme_zn2: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(4)]
    pub sve_imm4: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQRSHRN_SVE_Zd_SME_Znx4_SME_SHRIMM5 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(2)]
    pub _op_5: u32,
    #[bits(3)]
    pub sme_zn4: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_imm5b: u32,
    #[bits(1)]
    pub _op_21: u32,
    #[bits(2)]
    pub sve_tszh: u32,
    #[bits(8)]
    pub _op_24: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQRSHRN_SVE_Zd_SME_Znx2_SME_SHRIMM4 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(1)]
    pub _op_5: u32,
    #[bits(4)]
    pub sme_zn2: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(4)]
    pub sve_imm4: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQRSHRN_Vd_Vn_IMM_VLSR {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQRSHRN_Sd_Sn_IMM_VLSR {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQRSHRN2_Vd_Vn_IMM_VLSR {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQRSHRNB_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(3)]
    pub sve_imm3: u32,
    #[bits(2)]
    pub sve_tszl_19: u32,
    #[bits(1)]
    pub _op_21: u32,
    #[bits(1)]
    pub sve_sz: u32,
    #[bits(9)]
    pub _op_23: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQRSHRNT_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(3)]
    pub sve_imm3: u32,
    #[bits(2)]
    pub sve_tszl_19: u32,
    #[bits(1)]
    pub _op_21: u32,
    #[bits(1)]
    pub sve_sz: u32,
    #[bits(9)]
    pub _op_23: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQRSHRU_SVE_Zd_SME_Znx4_SME_SHRIMM5 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(2)]
    pub _op_5: u32,
    #[bits(3)]
    pub sme_zn4: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_imm5b: u32,
    #[bits(1)]
    pub _op_21: u32,
    #[bits(2)]
    pub sve_tszh: u32,
    #[bits(8)]
    pub _op_24: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQRSHRU_SVE_Zd_SME_Znx2_SME_SHRIMM4 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(1)]
    pub _op_5: u32,
    #[bits(4)]
    pub sme_zn2: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(4)]
    pub sve_imm4: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQRSHRUN_SVE_Zd_SME_Znx4_SME_SHRIMM5 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(2)]
    pub _op_5: u32,
    #[bits(3)]
    pub sme_zn4: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_imm5b: u32,
    #[bits(1)]
    pub _op_21: u32,
    #[bits(2)]
    pub sve_tszh: u32,
    #[bits(8)]
    pub _op_24: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQRSHRUN_SVE_Zd_SME_Znx2_SME_SHRIMM4 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(1)]
    pub _op_5: u32,
    #[bits(4)]
    pub sme_zn2: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(4)]
    pub sve_imm4: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQRSHRUN_Vd_Vn_IMM_VLSR {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQRSHRUN_Sd_Sn_IMM_VLSR {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQRSHRUN2_Vd_Vn_IMM_VLSR {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQRSHRUNB_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(3)]
    pub sve_imm3: u32,
    #[bits(2)]
    pub sve_tszl_19: u32,
    #[bits(1)]
    pub _op_21: u32,
    #[bits(1)]
    pub sve_sz: u32,
    #[bits(9)]
    pub _op_23: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQRSHRUNT_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(3)]
    pub sve_imm3: u32,
    #[bits(2)]
    pub sve_tszl_19: u32,
    #[bits(1)]
    pub _op_21: u32,
    #[bits(1)]
    pub sve_sz: u32,
    #[bits(9)]
    pub _op_23: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQSHL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQSHL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_SHLIMM_PRED {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_imm5: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(9)]
    pub _op_13: u32,
    #[bits(2)]
    pub sve_tszh: u32,
    #[bits(8)]
    pub _op_24: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQSHL_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQSHL_Sd_Sn_Sm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQSHL_Vd_Vn_IMM_VLSL {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQSHL_Sd_Sn_IMM_VLSL {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQSHLR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQSHLU_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_SHLIMM_PRED {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_imm5: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(9)]
    pub _op_13: u32,
    #[bits(2)]
    pub sve_tszh: u32,
    #[bits(8)]
    pub _op_24: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQSHLU_Vd_Vn_IMM_VLSL {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQSHLU_Sd_Sn_IMM_VLSL {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQSHRN_Vd_Vn_IMM_VLSR {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQSHRN_Sd_Sn_IMM_VLSR {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQSHRN2_Vd_Vn_IMM_VLSR {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQSHRNB_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(3)]
    pub sve_imm3: u32,
    #[bits(2)]
    pub sve_tszl_19: u32,
    #[bits(1)]
    pub _op_21: u32,
    #[bits(1)]
    pub sve_sz: u32,
    #[bits(9)]
    pub _op_23: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQSHRNT_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(3)]
    pub sve_imm3: u32,
    #[bits(2)]
    pub sve_tszl_19: u32,
    #[bits(1)]
    pub _op_21: u32,
    #[bits(1)]
    pub sve_sz: u32,
    #[bits(9)]
    pub _op_23: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQSHRUN_Vd_Vn_IMM_VLSR {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQSHRUN_Sd_Sn_IMM_VLSR {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQSHRUN2_Vd_Vn_IMM_VLSR {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQSHRUNB_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(3)]
    pub sve_imm3: u32,
    #[bits(2)]
    pub sve_tszl_19: u32,
    #[bits(1)]
    pub _op_21: u32,
    #[bits(1)]
    pub sve_sz: u32,
    #[bits(9)]
    pub _op_23: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQSHRUNT_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(3)]
    pub sve_imm3: u32,
    #[bits(2)]
    pub sve_tszl_19: u32,
    #[bits(1)]
    pub _op_21: u32,
    #[bits(1)]
    pub sve_sz: u32,
    #[bits(9)]
    pub _op_23: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQSUB_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQSUB_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQSUB_SVE_Zd_SVE_Zd_SVE_AIMM {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(9)]
    pub sve_imm9: u32,
    #[bits(18)]
    pub _op_14: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQSUB_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQSUB_Sd_Sn_Sm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQSUBR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQXTN_Vd_Vn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQXTN_Sd_Sn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQXTN2_Vd_Vn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQXTNB_SVE_Zd_SVE_Zn {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQXTNT_SVE_Zd_SVE_Zn {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQXTUN_Vd_Vn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQXTUN_Sd_Sn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQXTUN2_Vd_Vn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQXTUNB_SVE_Zd_SVE_Zn {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SQXTUNT_SVE_Zd_SVE_Zn {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SRHADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SRHADD_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SRI_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub imm5: u32,
    #[bits(1)]
    pub _op_21: u32,
    #[bits(2)]
    pub sve_tszh: u32,
    #[bits(8)]
    pub _op_24: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SRI_Vd_Vn_IMM_VLSR {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SRI_Sd_Sn_IMM_VLSR {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SRSHL_SME_Zdnx2_SME_Zdnx2_SME_Zm {
    #[bits(1)]
    pub _op_0: u32,
    #[bits(4)]
    pub sme_zdn2: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SRSHL_SME_Zdnx2_SME_Zdnx2_SME_Zmx2 {
    #[bits(1)]
    pub _op_0: u32,
    #[bits(4)]
    pub sme_zdn2: u32,
    #[bits(12)]
    pub _op_5: u32,
    #[bits(4)]
    pub sme_zm2: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SRSHL_SME_Zdnx4_SME_Zdnx4_SME_Zm {
    #[bits(2)]
    pub _op_0: u32,
    #[bits(3)]
    pub sme_zdn4: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SRSHL_SME_Zdnx4_SME_Zdnx4_SME_Zmx4 {
    #[bits(2)]
    pub _op_0: u32,
    #[bits(3)]
    pub sme_zdn4: u32,
    #[bits(13)]
    pub _op_5: u32,
    #[bits(3)]
    pub sme_zm4: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SRSHL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SRSHL_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SRSHL_Sd_Sn_Sm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SRSHLR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SRSHR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_SHRIMM_PRED {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_imm5: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(9)]
    pub _op_13: u32,
    #[bits(2)]
    pub sve_tszh: u32,
    #[bits(8)]
    pub _op_24: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SRSHR_Vd_Vn_IMM_VLSR {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SRSHR_Sd_Sn_IMM_VLSR {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SRSRA_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub imm5: u32,
    #[bits(1)]
    pub _op_21: u32,
    #[bits(2)]
    pub sve_tszh: u32,
    #[bits(8)]
    pub _op_24: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SRSRA_Vd_Vn_IMM_VLSR {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SRSRA_Sd_Sn_IMM_VLSR {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SSHL_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SSHL_Sd_Sn_Sm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SSHLL_Vd_Vn_IMM_VLSL {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SSHLL2_Vd_Vn_IMM_VLSL {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SSHLLB_SVE_Zd_SVE_Zn_SVE_SHLIMM_UNPRED_22 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(3)]
    pub sve_imm3: u32,
    #[bits(2)]
    pub sve_tszl_19: u32,
    #[bits(1)]
    pub _op_21: u32,
    #[bits(1)]
    pub sve_sz: u32,
    #[bits(9)]
    pub _op_23: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SSHLLT_SVE_Zd_SVE_Zn_SVE_SHLIMM_UNPRED_22 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(3)]
    pub sve_imm3: u32,
    #[bits(2)]
    pub sve_tszl_19: u32,
    #[bits(1)]
    pub _op_21: u32,
    #[bits(1)]
    pub sve_sz: u32,
    #[bits(9)]
    pub _op_23: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SSHR_Vd_Vn_IMM_VLSR {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SSHR_Sd_Sn_IMM_VLSR {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SSRA_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub imm5: u32,
    #[bits(1)]
    pub _op_21: u32,
    #[bits(2)]
    pub sve_tszh: u32,
    #[bits(8)]
    pub _op_24: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SSRA_Vd_Vn_IMM_VLSR {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SSRA_Sd_Sn_IMM_VLSR {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SSUBL_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SSUBL2_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SSUBLB_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SSUBLBT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SSUBLT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SSUBLTB_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SSUBW_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SSUBW2_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SSUBWB_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SSUBWT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST1_LVt_SIMD_ADDR_SIMPLE {
    #[bits(32)]
    pub _op_0: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST1_LEt_SIMD_ADDR_SIMPLE {
    #[bits(32)]
    pub _op_0: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST1_LVt_SIMD_ADDR_POST {
    #[bits(32)]
    pub _op_0: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST1_LEt_SIMD_ADDR_POST {
    #[bits(32)]
    pub _op_0: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST1B_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR {
    #[bits(1)]
    pub _op_0: u32,
    #[bits(4)]
    pub sme_zdn2: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST1B_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR {
    #[bits(2)]
    pub _op_0: u32,
    #[bits(3)]
    pub sme_zdn4: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST1B_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_RR {
    #[bits(4)]
    pub imm4_0: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub sme_v: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(1)]
    pub _op_21: u32,
    #[bits(2)]
    pub sme_size_22: u32,
    #[bits(1)]
    pub index2: u32,
    #[bits(7)]
    pub _op_25: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST1B_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_R {
    #[bits(4)]
    pub imm4_0: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub sme_v: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(1)]
    pub _op_21: u32,
    #[bits(2)]
    pub sme_size_22: u32,
    #[bits(1)]
    pub index2: u32,
    #[bits(7)]
    pub _op_25: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST1B_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL {
    #[bits(1)]
    pub _op_0: u32,
    #[bits(4)]
    pub sme_zdn2: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST1B_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL {
    #[bits(2)]
    pub _op_0: u32,
    #[bits(3)]
    pub sme_zdn4: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST1B_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR {
    #[bits(3)]
    pub sme_zt3: u32,
    #[bits(1)]
    pub _op_3: u32,
    #[bits(1)]
    pub sme_ztt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST1B_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR {
    #[bits(2)]
    pub sme_zt2: u32,
    #[bits(2)]
    pub _op_2: u32,
    #[bits(1)]
    pub sme_ztt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST1B_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL {
    #[bits(3)]
    pub sme_zt3: u32,
    #[bits(1)]
    pub _op_3: u32,
    #[bits(1)]
    pub sme_ztt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST1B_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL {
    #[bits(2)]
    pub sme_zt2: u32,
    #[bits(2)]
    pub _op_2: u32,
    #[bits(1)]
    pub sme_ztt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST1B_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_RX {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_14 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(1)]
    pub _op_13: u32,
    #[bits(1)]
    pub sve_xs_14: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST1B_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_RZ_XTW_14 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(1)]
    pub _op_13: u32,
    #[bits(1)]
    pub sve_xs_14: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST1B_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_RI_S4xVL {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST1B_SVE_ZtxN_S_H_SVE_Pg3_SVE_ADDR_RX {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST1B_SVE_ZtxN_S_D_SVE_Pg3_SVE_ADDR_RX {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST1B_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_ZI_U5 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST1B_SVE_ZtxN_S_H_SVE_Pg3_SVE_ADDR_RI_S4xVL {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST1B_SVE_ZtxN_S_D_SVE_Pg3_SVE_ADDR_RI_S4xVL {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST1D_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR_LSL3 {
    #[bits(1)]
    pub _op_0: u32,
    #[bits(4)]
    pub sme_zdn2: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST1D_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR_LSL3 {
    #[bits(2)]
    pub _op_0: u32,
    #[bits(3)]
    pub sme_zdn4: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST1D_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL {
    #[bits(1)]
    pub _op_0: u32,
    #[bits(4)]
    pub sme_zdn2: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST1D_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL {
    #[bits(2)]
    pub _op_0: u32,
    #[bits(3)]
    pub sme_zdn4: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST1D_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_RR_LSL3 {
    #[bits(4)]
    pub imm4_0: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub sme_v: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(1)]
    pub _op_21: u32,
    #[bits(2)]
    pub sme_size_22: u32,
    #[bits(1)]
    pub index2: u32,
    #[bits(7)]
    pub _op_25: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST1D_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_R {
    #[bits(4)]
    pub imm4_0: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub sme_v: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(1)]
    pub _op_21: u32,
    #[bits(2)]
    pub sme_size_22: u32,
    #[bits(1)]
    pub index2: u32,
    #[bits(7)]
    pub _op_25: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST1D_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL3 {
    #[bits(3)]
    pub sme_zt3: u32,
    #[bits(1)]
    pub _op_3: u32,
    #[bits(1)]
    pub sme_ztt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST1D_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL3 {
    #[bits(2)]
    pub sme_zt2: u32,
    #[bits(2)]
    pub _op_2: u32,
    #[bits(1)]
    pub sme_ztt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST1D_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL {
    #[bits(3)]
    pub sme_zt3: u32,
    #[bits(1)]
    pub _op_3: u32,
    #[bits(1)]
    pub sme_ztt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST1D_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL {
    #[bits(2)]
    pub sme_zt2: u32,
    #[bits(2)]
    pub _op_2: u32,
    #[bits(1)]
    pub sme_ztt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL3 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_14 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(1)]
    pub _op_13: u32,
    #[bits(1)]
    pub sve_xs_14: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x8 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW3_14 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(1)]
    pub _op_13: u32,
    #[bits(1)]
    pub sve_xs_14: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL3 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST1H_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR_LSL1 {
    #[bits(1)]
    pub _op_0: u32,
    #[bits(4)]
    pub sme_zdn2: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST1H_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR_LSL1 {
    #[bits(2)]
    pub _op_0: u32,
    #[bits(3)]
    pub sme_zdn4: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST1H_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL {
    #[bits(1)]
    pub _op_0: u32,
    #[bits(4)]
    pub sme_zdn2: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST1H_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL {
    #[bits(2)]
    pub _op_0: u32,
    #[bits(3)]
    pub sme_zdn4: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST1H_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_RR_LSL1 {
    #[bits(4)]
    pub imm4_0: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub sme_v: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(1)]
    pub _op_21: u32,
    #[bits(2)]
    pub sme_size_22: u32,
    #[bits(1)]
    pub index2: u32,
    #[bits(7)]
    pub _op_25: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST1H_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_R {
    #[bits(4)]
    pub imm4_0: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub sme_v: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(1)]
    pub _op_21: u32,
    #[bits(2)]
    pub sme_size_22: u32,
    #[bits(1)]
    pub index2: u32,
    #[bits(7)]
    pub _op_25: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST1H_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL1 {
    #[bits(3)]
    pub sme_zt3: u32,
    #[bits(1)]
    pub _op_3: u32,
    #[bits(1)]
    pub sme_ztt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST1H_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL1 {
    #[bits(2)]
    pub sme_zt2: u32,
    #[bits(2)]
    pub _op_2: u32,
    #[bits(1)]
    pub sme_ztt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST1H_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL {
    #[bits(3)]
    pub sme_zt3: u32,
    #[bits(1)]
    pub _op_3: u32,
    #[bits(1)]
    pub sme_ztt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST1H_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL {
    #[bits(2)]
    pub sme_zt2: u32,
    #[bits(2)]
    pub _op_2: u32,
    #[bits(1)]
    pub sme_ztt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_14 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(1)]
    pub _op_13: u32,
    #[bits(1)]
    pub sve_xs_14: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST1H_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_RZ_XTW_14 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(1)]
    pub _op_13: u32,
    #[bits(1)]
    pub sve_xs_14: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x2 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST1H_SVE_ZtxN_S_H_SVE_Pg3_SVE_ADDR_RX_LSL1 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST1H_SVE_ZtxN_S_D_SVE_Pg3_SVE_ADDR_RX_LSL1 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW1_14 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(1)]
    pub _op_13: u32,
    #[bits(1)]
    pub sve_xs_14: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST1H_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_RZ_XTW1_14 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(1)]
    pub _op_13: u32,
    #[bits(1)]
    pub sve_xs_14: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL1 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST1H_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_ZI_U5x2 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST1H_SVE_ZtxN_S_H_SVE_Pg3_SVE_ADDR_RI_S4xVL {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST1H_SVE_ZtxN_S_D_SVE_Pg3_SVE_ADDR_RI_S4xVL {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST1Q_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_RR_LSL4 {
    #[bits(4)]
    pub imm4_0: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub sme_v: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(1)]
    pub _op_21: u32,
    #[bits(2)]
    pub sme_size_22: u32,
    #[bits(1)]
    pub index2: u32,
    #[bits(7)]
    pub _op_25: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST1Q_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_R {
    #[bits(4)]
    pub imm4_0: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub sme_v: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(1)]
    pub _op_21: u32,
    #[bits(2)]
    pub sme_size_22: u32,
    #[bits(1)]
    pub index2: u32,
    #[bits(7)]
    pub _op_25: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST1Q_SVE_Zt_SVE_Pg3_SVE_ADDR_ZX {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST1W_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR_LSL2 {
    #[bits(1)]
    pub _op_0: u32,
    #[bits(4)]
    pub sme_zdn2: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST1W_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR_LSL2 {
    #[bits(2)]
    pub _op_0: u32,
    #[bits(3)]
    pub sme_zdn4: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST1W_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_RR_LSL2 {
    #[bits(4)]
    pub imm4_0: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub sme_v: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(1)]
    pub _op_21: u32,
    #[bits(2)]
    pub sme_size_22: u32,
    #[bits(1)]
    pub index2: u32,
    #[bits(7)]
    pub _op_25: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST1W_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_R {
    #[bits(4)]
    pub imm4_0: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub sme_v: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(1)]
    pub _op_21: u32,
    #[bits(2)]
    pub sme_size_22: u32,
    #[bits(1)]
    pub index2: u32,
    #[bits(7)]
    pub _op_25: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST1W_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL {
    #[bits(1)]
    pub _op_0: u32,
    #[bits(4)]
    pub sme_zdn2: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST1W_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL {
    #[bits(2)]
    pub _op_0: u32,
    #[bits(3)]
    pub sme_zdn4: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST1W_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL2 {
    #[bits(3)]
    pub sme_zt3: u32,
    #[bits(1)]
    pub _op_3: u32,
    #[bits(1)]
    pub sme_ztt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST1W_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL2 {
    #[bits(2)]
    pub sme_zt2: u32,
    #[bits(2)]
    pub _op_2: u32,
    #[bits(1)]
    pub sme_ztt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST1W_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL {
    #[bits(3)]
    pub sme_zt3: u32,
    #[bits(1)]
    pub _op_3: u32,
    #[bits(1)]
    pub sme_ztt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST1W_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL {
    #[bits(2)]
    pub sme_zt2: u32,
    #[bits(2)]
    pub _op_2: u32,
    #[bits(1)]
    pub sme_ztt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST1W_SVE_ZtxN_S_D_SVE_Pg3_SVE_ADDR_RX_LSL2 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_14 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(1)]
    pub _op_13: u32,
    #[bits(1)]
    pub sve_xs_14: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST1W_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_RZ_XTW_14 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(1)]
    pub _op_13: u32,
    #[bits(1)]
    pub sve_xs_14: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x4 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW2_14 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(1)]
    pub _op_13: u32,
    #[bits(1)]
    pub sve_xs_14: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST1W_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_RZ_XTW2_14 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(1)]
    pub _op_13: u32,
    #[bits(1)]
    pub sve_xs_14: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL2 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST1W_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_ZI_U5x4 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST1W_SVE_ZtxN_S_D_SVE_Pg3_SVE_ADDR_RI_S4xVL {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST2_LVt_SIMD_ADDR_SIMPLE {
    #[bits(32)]
    pub _op_0: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST2_LEt_SIMD_ADDR_SIMPLE {
    #[bits(32)]
    pub _op_0: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST2_LVt_SIMD_ADDR_POST {
    #[bits(32)]
    pub _op_0: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST2_LEt_SIMD_ADDR_POST {
    #[bits(32)]
    pub _op_0: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST2B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST2B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x2xVL {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST2D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL3 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST2D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x2xVL {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST2G_Rt_SP_ADDR_SIMM13 {
    #[bits(5)]
    pub rt: u32,
    #[bits(6)]
    pub _op_5: u32,
    #[bits(1)]
    pub index: u32,
    #[bits(9)]
    pub imm9: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST2G_Rt_SP_X_ADDR_SIMM13_imm_tag {
    #[bits(5)]
    pub rt: u32,
    #[bits(6)]
    pub _op_5: u32,
    #[bits(1)]
    pub index: u32,
    #[bits(9)]
    pub imm9: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST2H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST2H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x2xVL {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST2Q_SME_Zt2_SVE_Pg3_SVE_ADDR_RI_S4x2xVL {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST2Q_SME_Zt2_SVE_Pg3_SVE_ADDR_RR_LSL4 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST2W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST2W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x2xVL {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST3_LVt_SIMD_ADDR_SIMPLE {
    #[bits(32)]
    pub _op_0: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST3_LEt_SIMD_ADDR_SIMPLE {
    #[bits(32)]
    pub _op_0: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST3_LVt_SIMD_ADDR_POST {
    #[bits(32)]
    pub _op_0: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST3_LEt_SIMD_ADDR_POST {
    #[bits(32)]
    pub _op_0: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST3B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST3B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x3xVL {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST3D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL3 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST3D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x3xVL {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST3H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST3H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x3xVL {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST3Q_SME_Zt3_SVE_Pg3_SVE_ADDR_RI_S4x2xVL {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST3Q_SME_Zt3_SVE_Pg3_SVE_ADDR_RR_LSL4 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST3W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST3W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x3xVL {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST4_LVt_SIMD_ADDR_SIMPLE {
    #[bits(32)]
    pub _op_0: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST4_LEt_SIMD_ADDR_SIMPLE {
    #[bits(32)]
    pub _op_0: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST4_LVt_SIMD_ADDR_POST {
    #[bits(32)]
    pub _op_0: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST4_LEt_SIMD_ADDR_POST {
    #[bits(32)]
    pub _op_0: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST4B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST4B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x4xVL {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST4D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL3 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST4D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x4xVL {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST4H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST4H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x4xVL {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST4Q_SME_Zt4_SVE_Pg3_SVE_ADDR_RI_S4x2xVL {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST4Q_SME_Zt4_SVE_Pg3_SVE_ADDR_RR_LSL4 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST4W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST4W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x4xVL {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST64B_Rt_LS64_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(27)]
    pub _op_5: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST64BV_Rs_Rt_LS64_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ST64BV0_Rs_Rt_LS64_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct STG_Rt_SP_ADDR_SIMM13 {
    #[bits(5)]
    pub rt: u32,
    #[bits(6)]
    pub _op_5: u32,
    #[bits(1)]
    pub index: u32,
    #[bits(9)]
    pub imm9: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct STG_Rt_SP_X_ADDR_SIMM13_imm_tag {
    #[bits(5)]
    pub rt: u32,
    #[bits(6)]
    pub _op_5: u32,
    #[bits(1)]
    pub index: u32,
    #[bits(9)]
    pub imm9: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct STGM_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(27)]
    pub _op_5: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct STGP_Rt_Rt2_ADDR_SIMM11 {
    #[bits(5)]
    pub rt: u32,
    #[bits(5)]
    pub _op_5: u32,
    #[bits(5)]
    pub rt2: u32,
    #[bits(7)]
    pub imm7: u32,
    #[bits(2)]
    pub _op_22: u32,
    #[bits(1)]
    pub index2: u32,
    #[bits(7)]
    pub _op_25: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct STGP_Rt_X_Rt2_X_ADDR_SIMM11_imm_tag {
    #[bits(5)]
    pub rt: u32,
    #[bits(5)]
    pub _op_5: u32,
    #[bits(5)]
    pub rt2: u32,
    #[bits(7)]
    pub imm7: u32,
    #[bits(2)]
    pub _op_22: u32,
    #[bits(1)]
    pub index2: u32,
    #[bits(7)]
    pub _op_25: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct STILP_Rt_Rs_RCPC3_ADDR_OPT_PREIND_WB {
    #[bits(5)]
    pub rt: u32,
    #[bits(7)]
    pub _op_5: u32,
    #[bits(4)]
    pub opc2: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct STL1_LEt_SIMD_ADDR_SIMPLE {
    #[bits(32)]
    pub _op_0: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct STLLR_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(27)]
    pub _op_5: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct STLLRB_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(27)]
    pub _op_5: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct STLLRH_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(27)]
    pub _op_5: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct STLR_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(27)]
    pub _op_5: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct STLR_Rt_RCPC3_ADDR_PREIND_WB {
    #[bits(5)]
    pub rt: u32,
    #[bits(27)]
    pub _op_5: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct STLRB_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(27)]
    pub _op_5: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct STLRH_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(27)]
    pub _op_5: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct STLUR_Rt_ADDR_OFFSET {
    #[bits(5)]
    pub rt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(1)]
    pub _op_10: u32,
    #[bits(1)]
    pub index: u32,
    #[bits(9)]
    pub imm9: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct STLUR_Rt_X_ADDR_OFFSET {
    #[bits(5)]
    pub rt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(1)]
    pub _op_10: u32,
    #[bits(1)]
    pub index: u32,
    #[bits(9)]
    pub imm9: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct STLUR_Ft_RCPC3_ADDR_OFFSET {
    #[bits(5)]
    pub rt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(2)]
    pub _op_10: u32,
    #[bits(9)]
    pub imm9: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct STLURB_Rt_ADDR_OFFSET {
    #[bits(5)]
    pub rt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(1)]
    pub _op_10: u32,
    #[bits(1)]
    pub index: u32,
    #[bits(9)]
    pub imm9: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct STLURH_Rt_ADDR_OFFSET {
    #[bits(5)]
    pub rt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(1)]
    pub _op_10: u32,
    #[bits(1)]
    pub index: u32,
    #[bits(9)]
    pub imm9: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct STLXP_Rs_Rt_Rt2_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(5)]
    pub _op_5: u32,
    #[bits(5)]
    pub rt2: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct STLXR_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct STLXRB_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct STLXRH_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct STNP_Rt_Rt2_ADDR_SIMM7 {
    #[bits(5)]
    pub rt: u32,
    #[bits(5)]
    pub _op_5: u32,
    #[bits(5)]
    pub rt2: u32,
    #[bits(7)]
    pub imm7: u32,
    #[bits(2)]
    pub _op_22: u32,
    #[bits(1)]
    pub index2: u32,
    #[bits(7)]
    pub _op_25: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct STNP_Ft_Ft2_ADDR_SIMM7 {
    #[bits(5)]
    pub rt: u32,
    #[bits(5)]
    pub _op_5: u32,
    #[bits(5)]
    pub rt2: u32,
    #[bits(7)]
    pub imm7: u32,
    #[bits(2)]
    pub _op_22: u32,
    #[bits(1)]
    pub index2: u32,
    #[bits(7)]
    pub _op_25: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct STNT1B_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR {
    #[bits(1)]
    pub _op_0: u32,
    #[bits(4)]
    pub sme_zdn2: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct STNT1B_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR {
    #[bits(2)]
    pub _op_0: u32,
    #[bits(3)]
    pub sme_zdn4: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct STNT1B_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL {
    #[bits(1)]
    pub _op_0: u32,
    #[bits(4)]
    pub sme_zdn2: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct STNT1B_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL {
    #[bits(2)]
    pub _op_0: u32,
    #[bits(3)]
    pub sme_zdn4: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct STNT1B_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR {
    #[bits(3)]
    pub sme_zt3: u32,
    #[bits(1)]
    pub _op_3: u32,
    #[bits(1)]
    pub sme_ztt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct STNT1B_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR {
    #[bits(2)]
    pub sme_zt2: u32,
    #[bits(2)]
    pub _op_2: u32,
    #[bits(1)]
    pub sme_ztt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct STNT1B_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL {
    #[bits(3)]
    pub sme_zt3: u32,
    #[bits(1)]
    pub _op_3: u32,
    #[bits(1)]
    pub sme_ztt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct STNT1B_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL {
    #[bits(2)]
    pub sme_zt2: u32,
    #[bits(2)]
    pub _op_2: u32,
    #[bits(1)]
    pub sme_ztt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct STNT1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZX {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct STNT1B_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_ZX {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct STNT1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct STNT1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct STNT1D_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR_LSL3 {
    #[bits(1)]
    pub _op_0: u32,
    #[bits(4)]
    pub sme_zdn2: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct STNT1D_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR_LSL3 {
    #[bits(2)]
    pub _op_0: u32,
    #[bits(3)]
    pub sme_zdn4: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct STNT1D_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL {
    #[bits(1)]
    pub _op_0: u32,
    #[bits(4)]
    pub sme_zdn2: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct STNT1D_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL {
    #[bits(2)]
    pub _op_0: u32,
    #[bits(3)]
    pub sme_zdn4: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct STNT1D_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL3 {
    #[bits(3)]
    pub sme_zt3: u32,
    #[bits(1)]
    pub _op_3: u32,
    #[bits(1)]
    pub sme_ztt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct STNT1D_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL3 {
    #[bits(2)]
    pub sme_zt2: u32,
    #[bits(2)]
    pub _op_2: u32,
    #[bits(1)]
    pub sme_ztt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct STNT1D_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL {
    #[bits(3)]
    pub sme_zt3: u32,
    #[bits(1)]
    pub _op_3: u32,
    #[bits(1)]
    pub sme_ztt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct STNT1D_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL {
    #[bits(2)]
    pub sme_zt2: u32,
    #[bits(2)]
    pub _op_2: u32,
    #[bits(1)]
    pub sme_ztt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct STNT1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZX {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct STNT1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL3 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct STNT1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct STNT1H_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR_LSL1 {
    #[bits(1)]
    pub _op_0: u32,
    #[bits(4)]
    pub sme_zdn2: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct STNT1H_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR_LSL1 {
    #[bits(2)]
    pub _op_0: u32,
    #[bits(3)]
    pub sme_zdn4: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct STNT1H_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL {
    #[bits(1)]
    pub _op_0: u32,
    #[bits(4)]
    pub sme_zdn2: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct STNT1H_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL {
    #[bits(2)]
    pub _op_0: u32,
    #[bits(3)]
    pub sme_zdn4: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct STNT1H_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL1 {
    #[bits(3)]
    pub sme_zt3: u32,
    #[bits(1)]
    pub _op_3: u32,
    #[bits(1)]
    pub sme_ztt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct STNT1H_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL1 {
    #[bits(2)]
    pub sme_zt2: u32,
    #[bits(2)]
    pub _op_2: u32,
    #[bits(1)]
    pub sme_ztt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct STNT1H_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL {
    #[bits(3)]
    pub sme_zt3: u32,
    #[bits(1)]
    pub _op_3: u32,
    #[bits(1)]
    pub sme_ztt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct STNT1H_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL {
    #[bits(2)]
    pub sme_zt2: u32,
    #[bits(2)]
    pub _op_2: u32,
    #[bits(1)]
    pub sme_ztt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct STNT1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZX {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct STNT1H_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_ZX {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct STNT1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct STNT1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct STNT1W_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR_LSL2 {
    #[bits(1)]
    pub _op_0: u32,
    #[bits(4)]
    pub sme_zdn2: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct STNT1W_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR_LSL2 {
    #[bits(2)]
    pub _op_0: u32,
    #[bits(3)]
    pub sme_zdn4: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct STNT1W_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL {
    #[bits(1)]
    pub _op_0: u32,
    #[bits(4)]
    pub sme_zdn2: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct STNT1W_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL {
    #[bits(2)]
    pub _op_0: u32,
    #[bits(3)]
    pub sme_zdn4: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct STNT1W_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL2 {
    #[bits(3)]
    pub sme_zt3: u32,
    #[bits(1)]
    pub _op_3: u32,
    #[bits(1)]
    pub sme_ztt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct STNT1W_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL2 {
    #[bits(2)]
    pub sme_zt2: u32,
    #[bits(2)]
    pub _op_2: u32,
    #[bits(1)]
    pub sme_ztt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct STNT1W_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL {
    #[bits(3)]
    pub sme_zt3: u32,
    #[bits(1)]
    pub _op_3: u32,
    #[bits(1)]
    pub sme_ztt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct STNT1W_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL {
    #[bits(2)]
    pub sme_zt2: u32,
    #[bits(2)]
    pub _op_2: u32,
    #[bits(1)]
    pub sme_ztt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct STNT1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZX {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct STNT1W_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_ZX {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct STNT1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2 {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub _op_13: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct STNT1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct STP_Rt_Rt2_ADDR_SIMM7 {
    #[bits(5)]
    pub rt: u32,
    #[bits(5)]
    pub _op_5: u32,
    #[bits(5)]
    pub rt2: u32,
    #[bits(7)]
    pub imm7: u32,
    #[bits(2)]
    pub _op_22: u32,
    #[bits(1)]
    pub index2: u32,
    #[bits(7)]
    pub _op_25: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct STP_Rt_W_Rt2_W_ADDR_SIMM7_S_S {
    #[bits(5)]
    pub rt: u32,
    #[bits(5)]
    pub _op_5: u32,
    #[bits(5)]
    pub rt2: u32,
    #[bits(7)]
    pub imm7: u32,
    #[bits(2)]
    pub _op_22: u32,
    #[bits(1)]
    pub index2: u32,
    #[bits(7)]
    pub _op_25: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct STP_Ft_Ft2_ADDR_SIMM7 {
    #[bits(5)]
    pub rt: u32,
    #[bits(5)]
    pub _op_5: u32,
    #[bits(5)]
    pub rt2: u32,
    #[bits(7)]
    pub imm7: u32,
    #[bits(2)]
    pub _op_22: u32,
    #[bits(1)]
    pub index2: u32,
    #[bits(7)]
    pub _op_25: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct STP_Ft_S_S_Ft2_S_S_ADDR_SIMM7_S_S {
    #[bits(5)]
    pub rt: u32,
    #[bits(5)]
    pub _op_5: u32,
    #[bits(5)]
    pub rt2: u32,
    #[bits(7)]
    pub imm7: u32,
    #[bits(2)]
    pub _op_22: u32,
    #[bits(1)]
    pub index2: u32,
    #[bits(7)]
    pub _op_25: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct STR_SME_ZA_array_off4_SME_ADDR_RI_U4xVL {
    #[bits(4)]
    pub imm4_0: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(17)]
    pub _op_15: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct STR_SME_ZT0_SIMD_ADDR_SIMPLE {
    #[bits(32)]
    pub _op_0: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct STR_Rt_ADDR_REGOFF {
    #[bits(5)]
    pub rt: u32,
    #[bits(27)]
    pub _op_5: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct STR_Rt_ADDR_SIMM9 {
    #[bits(5)]
    pub rt: u32,
    #[bits(6)]
    pub _op_5: u32,
    #[bits(1)]
    pub index: u32,
    #[bits(9)]
    pub imm9: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct STR_Rt_ADDR_UIMM12 {
    #[bits(5)]
    pub rt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(12)]
    pub imm12: u32,
    #[bits(10)]
    pub _op_22: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct STR_SVE_Pt_SVE_ADDR_RI_S9xVL {
    #[bits(4)]
    pub sve_pt: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct STR_SVE_PNt_SVE_ADDR_RI_S9xVL {
    #[bits(4)]
    pub sve_pt: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct STR_SVE_Zt_SVE_ADDR_RI_S9xVL {
    #[bits(5)]
    pub sve_zt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct STR_Ft_ADDR_REGOFF {
    #[bits(5)]
    pub rt: u32,
    #[bits(27)]
    pub _op_5: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct STR_Ft_ADDR_SIMM9 {
    #[bits(5)]
    pub rt: u32,
    #[bits(6)]
    pub _op_5: u32,
    #[bits(1)]
    pub index: u32,
    #[bits(9)]
    pub imm9: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct STR_Ft_ADDR_UIMM12 {
    #[bits(5)]
    pub rt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(12)]
    pub imm12: u32,
    #[bits(10)]
    pub _op_22: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct STRB_Rt_ADDR_REGOFF {
    #[bits(5)]
    pub rt: u32,
    #[bits(27)]
    pub _op_5: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct STRB_Rt_ADDR_SIMM9 {
    #[bits(5)]
    pub rt: u32,
    #[bits(6)]
    pub _op_5: u32,
    #[bits(1)]
    pub index: u32,
    #[bits(9)]
    pub imm9: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct STRB_Rt_ADDR_UIMM12 {
    #[bits(5)]
    pub rt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(12)]
    pub imm12: u32,
    #[bits(10)]
    pub _op_22: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct STRH_Rt_ADDR_REGOFF {
    #[bits(5)]
    pub rt: u32,
    #[bits(27)]
    pub _op_5: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct STRH_Rt_ADDR_SIMM9 {
    #[bits(5)]
    pub rt: u32,
    #[bits(6)]
    pub _op_5: u32,
    #[bits(1)]
    pub index: u32,
    #[bits(9)]
    pub imm9: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct STRH_Rt_ADDR_UIMM12 {
    #[bits(5)]
    pub rt: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(12)]
    pub imm12: u32,
    #[bits(10)]
    pub _op_22: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct STTR_Rt_ADDR_SIMM9 {
    #[bits(5)]
    pub rt: u32,
    #[bits(6)]
    pub _op_5: u32,
    #[bits(1)]
    pub index: u32,
    #[bits(9)]
    pub imm9: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct STTRB_Rt_ADDR_SIMM9 {
    #[bits(5)]
    pub rt: u32,
    #[bits(6)]
    pub _op_5: u32,
    #[bits(1)]
    pub index: u32,
    #[bits(9)]
    pub imm9: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct STTRH_Rt_ADDR_SIMM9 {
    #[bits(5)]
    pub rt: u32,
    #[bits(6)]
    pub _op_5: u32,
    #[bits(1)]
    pub index: u32,
    #[bits(9)]
    pub imm9: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct STUR_Rt_ADDR_SIMM9 {
    #[bits(5)]
    pub rt: u32,
    #[bits(6)]
    pub _op_5: u32,
    #[bits(1)]
    pub index: u32,
    #[bits(9)]
    pub imm9: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct STUR_Ft_ADDR_SIMM9 {
    #[bits(5)]
    pub rt: u32,
    #[bits(6)]
    pub _op_5: u32,
    #[bits(1)]
    pub index: u32,
    #[bits(9)]
    pub imm9: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct STURB_Rt_ADDR_SIMM9 {
    #[bits(5)]
    pub rt: u32,
    #[bits(6)]
    pub _op_5: u32,
    #[bits(1)]
    pub index: u32,
    #[bits(9)]
    pub imm9: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct STURH_Rt_ADDR_SIMM9 {
    #[bits(5)]
    pub rt: u32,
    #[bits(6)]
    pub _op_5: u32,
    #[bits(1)]
    pub index: u32,
    #[bits(9)]
    pub imm9: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct STXP_Rs_Rt_Rt2_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(5)]
    pub _op_5: u32,
    #[bits(5)]
    pub rt2: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct STXR_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct STXRB_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct STXRH_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct STZ2G_Rt_SP_ADDR_SIMM13 {
    #[bits(5)]
    pub rt: u32,
    #[bits(6)]
    pub _op_5: u32,
    #[bits(1)]
    pub index: u32,
    #[bits(9)]
    pub imm9: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct STZ2G_Rt_SP_X_ADDR_SIMM13_imm_tag {
    #[bits(5)]
    pub rt: u32,
    #[bits(6)]
    pub _op_5: u32,
    #[bits(1)]
    pub index: u32,
    #[bits(9)]
    pub imm9: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct STZG_Rt_SP_ADDR_SIMM13 {
    #[bits(5)]
    pub rt: u32,
    #[bits(6)]
    pub _op_5: u32,
    #[bits(1)]
    pub index: u32,
    #[bits(9)]
    pub imm9: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct STZG_Rt_SP_X_ADDR_SIMM13_imm_tag {
    #[bits(5)]
    pub rt: u32,
    #[bits(6)]
    pub _op_5: u32,
    #[bits(1)]
    pub index: u32,
    #[bits(9)]
    pub imm9: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct STZGM_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(27)]
    pub _op_5: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SUB_SME_ZA_array_off3_0_SVE_ZnxN_SME_Zm {
    #[bits(3)]
    pub imm3_0: u32,
    #[bits(2)]
    pub _op_3: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SUB_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_S_SME_Zm_S_S {
    #[bits(3)]
    pub imm3_0: u32,
    #[bits(2)]
    pub _op_3: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SUB_SME_ZA_array_off3_0_SME_Znx2_SME_Zmx2 {
    #[bits(3)]
    pub imm3_0: u32,
    #[bits(3)]
    pub _op_3: u32,
    #[bits(4)]
    pub sme_zn2: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(2)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm2: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SUB_SME_ZA_array_off3_0_SME_Znx4_SME_Zmx4 {
    #[bits(3)]
    pub imm3_0: u32,
    #[bits(4)]
    pub _op_3: u32,
    #[bits(3)]
    pub sme_zn4: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(3)]
    pub _op_15: u32,
    #[bits(3)]
    pub sme_zm4: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SUB_SME_ZA_array_off3_0_SME_Znx2 {
    #[bits(3)]
    pub imm3_0: u32,
    #[bits(3)]
    pub _op_3: u32,
    #[bits(4)]
    pub sme_zn2: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(17)]
    pub _op_15: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SUB_SME_ZA_array_off3_0_SME_Znx4 {
    #[bits(3)]
    pub imm3_0: u32,
    #[bits(4)]
    pub _op_3: u32,
    #[bits(3)]
    pub sme_zn4: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(17)]
    pub _op_15: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SUB_Rd_SP_Rn_SP_AIMM {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(12)]
    pub imm12: u32,
    #[bits(2)]
    pub shift: u32,
    #[bits(8)]
    pub _op_24: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SUB_Rd_Rn_Rm_SFT {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SUB_Rd_SP_Rn_SP_Rm_EXT {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SUB_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zm_5: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SUB_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SUB_SVE_Zd_SVE_Zd_SVE_AIMM {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(9)]
    pub sve_imm9: u32,
    #[bits(18)]
    pub _op_14: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SUB_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SUB_Sd_Sn_Sm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SUBG_Rd_SP_Rn_SP_UIMM10_UIMM4_ADDG {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(4)]
    pub imm4_10: u32,
    #[bits(2)]
    pub _op_14: u32,
    #[bits(6)]
    pub immr: u32,
    #[bits(10)]
    pub _op_22: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SUBHN_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SUBHN2_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SUBHNB_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SUBHNT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SUBP_Rd_Rn_SP_Rm_SP {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SUBPS_Rd_Rn_SP_Rm_SP {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SUBR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zm_5: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SUBR_SVE_Zd_SVE_Zd_SVE_AIMM {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(9)]
    pub sve_imm9: u32,
    #[bits(18)]
    pub _op_14: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SUBS_Rd_Rn_SP_AIMM {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(12)]
    pub imm12: u32,
    #[bits(2)]
    pub shift: u32,
    #[bits(8)]
    pub _op_24: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SUBS_Rd_Rn_Rm_SFT {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SUBS_Rd_Rn_SP_Rm_EXT {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SUDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2 {
    #[bits(3)]
    pub imm3_0: u32,
    #[bits(3)]
    pub _op_3: u32,
    #[bits(4)]
    pub sme_zn2: u32,
    #[bits(2)]
    pub imm2_10: u32,
    #[bits(1)]
    pub _op_12: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SUDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2 {
    #[bits(3)]
    pub imm3_0: u32,
    #[bits(4)]
    pub _op_3: u32,
    #[bits(3)]
    pub sme_zn4: u32,
    #[bits(2)]
    pub imm2_10: u32,
    #[bits(1)]
    pub _op_12: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SUDOT_SME_ZA_array_off3_0_SVE_ZnxN_SME_Zm {
    #[bits(3)]
    pub imm3_0: u32,
    #[bits(2)]
    pub _op_3: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SUDOT_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_B_SME_Zm_S_B {
    #[bits(3)]
    pub imm3_0: u32,
    #[bits(2)]
    pub _op_3: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SUDOT_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SUDOT_Vd_Vn_Em {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SUMLALL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm_INDEX4_10 {
    #[bits(2)]
    pub imm2_0: u32,
    #[bits(3)]
    pub _op_2: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub imm3_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub imm1_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SUMLALL_SME_ZA_array_off1x4_SME_Znx2_SME_Zm_INDEX4_1 {
    #[bits(1)]
    pub imm1_0: u32,
    #[bits(2)]
    pub imm2_1: u32,
    #[bits(3)]
    pub _op_3: u32,
    #[bits(4)]
    pub sme_zn2: u32,
    #[bits(2)]
    pub imm2_10: u32,
    #[bits(1)]
    pub _op_12: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SUMLALL_SME_ZA_array_off1x4_SME_Znx4_SME_Zm_INDEX4_1 {
    #[bits(1)]
    pub imm1_0: u32,
    #[bits(2)]
    pub imm2_1: u32,
    #[bits(4)]
    pub _op_3: u32,
    #[bits(3)]
    pub sme_zn4: u32,
    #[bits(2)]
    pub imm2_10: u32,
    #[bits(1)]
    pub _op_12: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SUMLALL_SME_ZA_array_off1x4_SVE_ZnxN_SME_Zm {
    #[bits(1)]
    pub imm1_0: u32,
    #[bits(4)]
    pub _op_1: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SUMLALL_SME_ZA_array_off1x4_S_S_SVE_ZnxN_S_B_SME_Zm_S_B {
    #[bits(1)]
    pub imm1_0: u32,
    #[bits(4)]
    pub _op_1: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SUMOPA_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16 {
    #[bits(2)]
    pub sme_zada_2b: u32,
    #[bits(3)]
    pub _op_2: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub sme_pm: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SUMOPA_SME_ZAda_3b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16 {
    #[bits(3)]
    pub sme_zada_3b: u32,
    #[bits(2)]
    pub _op_3: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub sme_pm: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SUMOPS_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16 {
    #[bits(2)]
    pub sme_zada_2b: u32,
    #[bits(3)]
    pub _op_2: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub sme_pm: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SUMOPS_SME_ZAda_3b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16 {
    #[bits(3)]
    pub sme_zada_3b: u32,
    #[bits(2)]
    pub _op_3: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub sme_pm: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SUNPK_SME_Zdnx2_SVE_Zn {
    #[bits(1)]
    pub _op_0: u32,
    #[bits(4)]
    pub sme_zdn2: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SUNPK_SME_Zdnx4_SME_Znx2 {
    #[bits(2)]
    pub _op_0: u32,
    #[bits(3)]
    pub sme_zdn4: u32,
    #[bits(1)]
    pub _op_5: u32,
    #[bits(4)]
    pub sme_zn2: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SUNPKHI_SVE_Zd_SVE_Zn {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SUNPKLO_SVE_Zd_SVE_Zn {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SUQADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SUQADD_Vd_Vn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SUQADD_Sd_Sn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SUVDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2 {
    #[bits(3)]
    pub imm3_0: u32,
    #[bits(4)]
    pub _op_3: u32,
    #[bits(3)]
    pub sme_zn4: u32,
    #[bits(2)]
    pub imm2_10: u32,
    #[bits(1)]
    pub _op_12: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SVC_EXCEPTION {
    #[bits(5)]
    pub _op_0: u32,
    #[bits(16)]
    pub imm16_5: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SVDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2 {
    #[bits(3)]
    pub imm3_0: u32,
    #[bits(3)]
    pub _op_3: u32,
    #[bits(4)]
    pub sme_zn2: u32,
    #[bits(2)]
    pub imm2_10: u32,
    #[bits(1)]
    pub _op_12: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SVDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2 {
    #[bits(3)]
    pub imm3_0: u32,
    #[bits(4)]
    pub _op_3: u32,
    #[bits(3)]
    pub sme_zn4: u32,
    #[bits(2)]
    pub imm2_10: u32,
    #[bits(1)]
    pub _op_12: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SVDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX1 {
    #[bits(3)]
    pub imm3_0: u32,
    #[bits(4)]
    pub _op_3: u32,
    #[bits(3)]
    pub sme_zn4: u32,
    #[bits(1)]
    pub imm1_10: u32,
    #[bits(2)]
    pub _op_11: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SWP_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SWPA_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SWPAB_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SWPAH_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SWPAL_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SWPALB_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SWPALH_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SWPB_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SWPH_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SWPL_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SWPLB_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SWPLH_Rs_Rt_ADDR_SIMPLE {
    #[bits(5)]
    pub rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub rs: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SWPP_LSE128_Rt_LSE128_Rt2_ADDR_SIMPLE {
    #[bits(5)]
    pub lse128_rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub lse128_rt2: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SWPPA_LSE128_Rt_LSE128_Rt2_ADDR_SIMPLE {
    #[bits(5)]
    pub lse128_rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub lse128_rt2: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SWPPAL_LSE128_Rt_LSE128_Rt2_ADDR_SIMPLE {
    #[bits(5)]
    pub lse128_rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub lse128_rt2: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SWPPL_LSE128_Rt_LSE128_Rt2_ADDR_SIMPLE {
    #[bits(5)]
    pub lse128_rt: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(5)]
    pub lse128_rt2: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SXTB_SVE_Zd_SVE_Pg3_SVE_Zn {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SXTH_SVE_Zd_SVE_Pg3_SVE_Zn {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SXTW_SVE_Zd_SVE_Pg3_SVE_Zn {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SYS_UIMM3_OP1_CRn_CRm_UIMM3_OP2_Rt {
    #[bits(5)]
    pub rt: u32,
    #[bits(3)]
    pub op2: u32,
    #[bits(4)]
    pub crm: u32,
    #[bits(4)]
    pub crn: u32,
    #[bits(3)]
    pub op1: u32,
    #[bits(13)]
    pub _op_19: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SYSL_Rt_UIMM3_OP1_CRn_CRm_UIMM3_OP2 {
    #[bits(5)]
    pub rt: u32,
    #[bits(3)]
    pub op2: u32,
    #[bits(4)]
    pub crm: u32,
    #[bits(4)]
    pub crn: u32,
    #[bits(3)]
    pub op1: u32,
    #[bits(13)]
    pub _op_19: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct SYSP_UIMM3_OP1_CRn_CRm_UIMM3_OP2_Rt_PAIRREG_OR_XZR {
    #[bits(5)]
    pub rt: u32,
    #[bits(3)]
    pub op2: u32,
    #[bits(4)]
    pub crm: u32,
    #[bits(4)]
    pub crn: u32,
    #[bits(3)]
    pub op1: u32,
    #[bits(13)]
    pub _op_19: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct TBL_SVE_Zd_SVE_ZnxN_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct TBL_SVE_Zd_S_B_SVE_ZnxN_S_B_SVE_Zm_16_S_B {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct TBL_Vd_LVn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct TBNZ_Rt_BIT_NUM_ADDR_PCREL14 {
    #[bits(5)]
    pub rt: u32,
    #[bits(14)]
    pub imm14: u32,
    #[bits(5)]
    pub b40: u32,
    #[bits(7)]
    pub _op_24: u32,
    #[bits(1)]
    pub b5: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct TBX_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct TBX_Vd_LVn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct TBZ_Rt_BIT_NUM_ADDR_PCREL14 {
    #[bits(5)]
    pub rt: u32,
    #[bits(14)]
    pub imm14: u32,
    #[bits(5)]
    pub b40: u32,
    #[bits(7)]
    pub _op_24: u32,
    #[bits(1)]
    pub b5: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct TCANCEL_TME_UIMM16 {
    #[bits(5)]
    pub _op_0: u32,
    #[bits(16)]
    pub imm16_5: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct TCOMMIT {
    #[bits(32)]
    pub _op_0: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct TRN1_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct TRN1_SVE_Pd_SVE_Pn_SVE_Pm {
    #[bits(4)]
    pub sve_pd: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(4)]
    pub sve_pn: u32,
    #[bits(7)]
    pub _op_9: u32,
    #[bits(4)]
    pub sve_pm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct TRN1_SVE_Zd_S_B_SVE_Zn_S_B_SVE_Zm_16_S_B {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct TRN1_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct TRN2_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct TRN2_SVE_Pd_SVE_Pn_SVE_Pm {
    #[bits(4)]
    pub sve_pd: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(4)]
    pub sve_pn: u32,
    #[bits(7)]
    pub _op_9: u32,
    #[bits(4)]
    pub sve_pm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct TRN2_SVE_Zd_S_B_SVE_Zn_S_B_SVE_Zm_16_S_B {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct TRN2_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct TSTART_Rd {
    #[bits(5)]
    pub rd: u32,
    #[bits(27)]
    pub _op_5: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct TTEST_Rd {
    #[bits(5)]
    pub rd: u32,
    #[bits(27)]
    pub _op_5: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UABA_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UABA_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UABAL_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UABAL2_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UABALB_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UABALT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UABD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zm_5: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UABD_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UABDL_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UABDL2_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UABDLB_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UABDLT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UADALP_SVE_Zd_SVE_Pg3_SVE_Zn {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UADALP_Vd_Vn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UADDL_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UADDL2_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UADDLB_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UADDLP_Vd_Vn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UADDLT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UADDLV_Fd_Vn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UADDV_SVE_Vd_SVE_Pg3_SVE_Zn {
    #[bits(5)]
    pub sve_vd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UADDW_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UADDW2_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UADDWB_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UADDWT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UBFM_Rd_Rn_IMMR_IMMS {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub imm6_10: u32,
    #[bits(6)]
    pub immr: u32,
    #[bits(10)]
    pub _op_22: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UCLAMP_SME_Zdnx2_SVE_Zn_SVE_Zm_16 {
    #[bits(1)]
    pub _op_0: u32,
    #[bits(4)]
    pub sme_zdn2: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UCLAMP_SME_Zdnx4_SVE_Zn_SVE_Zm_16 {
    #[bits(2)]
    pub _op_0: u32,
    #[bits(3)]
    pub sme_zdn4: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UCLAMP_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UCVTF_SME_Zdnx2_SME_Znx2 {
    #[bits(1)]
    pub _op_0: u32,
    #[bits(4)]
    pub sme_zdn2: u32,
    #[bits(1)]
    pub _op_5: u32,
    #[bits(4)]
    pub sme_zn2: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UCVTF_SME_Zdnx4_SME_Znx4 {
    #[bits(2)]
    pub _op_0: u32,
    #[bits(3)]
    pub sme_zdn4: u32,
    #[bits(2)]
    pub _op_5: u32,
    #[bits(3)]
    pub sme_zn4: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UCVTF_SVE_Zd_SVE_Pg3_SVE_Zn {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UCVTF_SVE_Zd_S_S_SVE_Pg3_P_M_SVE_Zn_S_S {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UCVTF_SVE_Zd_S_H_SVE_Pg3_P_M_SVE_Zn_S_S {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UCVTF_SVE_Zd_S_S_SVE_Pg3_P_M_SVE_Zn_S_D {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UCVTF_SVE_Zd_S_H_SVE_Pg3_P_M_SVE_Zn_S_H {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UCVTF_SVE_Zd_S_H_SVE_Pg3_P_M_SVE_Zn_S_D {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UCVTF_SVE_Zd_S_D_SVE_Pg3_P_M_SVE_Zn_S_D {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UCVTF_Fd_Rn_FBITS {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub scale: u32,
    #[bits(16)]
    pub _op_16: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UCVTF_Fd_S_D_Rn_W_FBITS_imm_1_32 {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub scale: u32,
    #[bits(16)]
    pub _op_16: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UCVTF_Vd_Vn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UCVTF_Vd_V_4H_Vn_V_4H {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UCVTF_Fd_Rn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UCVTF_Fd_S_D_Rn_W {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UCVTF_Sd_Sn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UCVTF_Sd_S_H_Sn_S_H {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UCVTF_Vd_Vn_IMM_VLSR {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UCVTF_Vd_V_2S_Vn_V_2S_IMM_VLSR_V_2S {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UCVTF_Sd_Sn_IMM_VLSR {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UCVTF_Sd_S_S_Sn_S_S_IMM_VLSR_S_S {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UDF_UNDEFINED {
    #[bits(16)]
    pub imm16_0: u32,
    #[bits(16)]
    pub _op_16: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UDIV_Rd_Rn_Rm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UDIV_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zm_5: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UDIVR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zm_5: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2 {
    #[bits(3)]
    pub imm3_0: u32,
    #[bits(3)]
    pub _op_3: u32,
    #[bits(4)]
    pub sme_zn2: u32,
    #[bits(2)]
    pub imm2_10: u32,
    #[bits(1)]
    pub _op_12: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UDOT_SME_ZA_array_off3_0_S_S_SME_Znx2_S_B_SME_Zm_INDEX2_S_B {
    #[bits(3)]
    pub imm3_0: u32,
    #[bits(3)]
    pub _op_3: u32,
    #[bits(4)]
    pub sme_zn2: u32,
    #[bits(2)]
    pub imm2_10: u32,
    #[bits(1)]
    pub _op_12: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2 {
    #[bits(3)]
    pub imm3_0: u32,
    #[bits(4)]
    pub _op_3: u32,
    #[bits(3)]
    pub sme_zn4: u32,
    #[bits(2)]
    pub imm2_10: u32,
    #[bits(1)]
    pub _op_12: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UDOT_SME_ZA_array_off3_0_S_S_SME_Znx4_S_B_SME_Zm_INDEX2_S_B {
    #[bits(3)]
    pub imm3_0: u32,
    #[bits(4)]
    pub _op_3: u32,
    #[bits(3)]
    pub sme_zn4: u32,
    #[bits(2)]
    pub imm2_10: u32,
    #[bits(1)]
    pub _op_12: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX1 {
    #[bits(3)]
    pub imm3_0: u32,
    #[bits(3)]
    pub _op_3: u32,
    #[bits(4)]
    pub sme_zn2: u32,
    #[bits(1)]
    pub imm1_10: u32,
    #[bits(2)]
    pub _op_11: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX1 {
    #[bits(3)]
    pub imm3_0: u32,
    #[bits(4)]
    pub _op_3: u32,
    #[bits(3)]
    pub sme_zn4: u32,
    #[bits(1)]
    pub imm1_10: u32,
    #[bits(2)]
    pub _op_11: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UDOT_SME_ZA_array_off3_0_SVE_ZnxN_SME_Zm {
    #[bits(3)]
    pub imm3_0: u32,
    #[bits(2)]
    pub _op_3: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UDOT_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_B_SME_Zm_S_B {
    #[bits(3)]
    pub imm3_0: u32,
    #[bits(2)]
    pub _op_3: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zmx2 {
    #[bits(3)]
    pub imm3_0: u32,
    #[bits(3)]
    pub _op_3: u32,
    #[bits(4)]
    pub sme_zn2: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(2)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm2: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zmx4 {
    #[bits(3)]
    pub imm3_0: u32,
    #[bits(4)]
    pub _op_3: u32,
    #[bits(3)]
    pub sme_zn4: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(3)]
    pub _op_15: u32,
    #[bits(3)]
    pub sme_zm4: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UDOT_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_H_SME_Zm_S_H {
    #[bits(3)]
    pub imm3_0: u32,
    #[bits(2)]
    pub _op_3: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UDOT_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_H_SME_Zm_S_H_c1701418 {
    #[bits(3)]
    pub imm3_0: u32,
    #[bits(2)]
    pub _op_3: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UDOT_SME_ZA_array_off3_0_S_S_SME_Znx2_S_H_SME_Zmx2_S_H {
    #[bits(3)]
    pub imm3_0: u32,
    #[bits(3)]
    pub _op_3: u32,
    #[bits(4)]
    pub sme_zn2: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(2)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm2: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UDOT_SME_ZA_array_off3_0_S_S_SME_Znx4_S_H_SME_Zmx4_S_H {
    #[bits(3)]
    pub imm3_0: u32,
    #[bits(4)]
    pub _op_3: u32,
    #[bits(3)]
    pub sme_zn4: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(3)]
    pub _op_15: u32,
    #[bits(3)]
    pub sme_zm4: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UDOT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UDOT_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UDOT_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UDOT_SVE_Zd_S_S_SVE_Zn_S_H_SVE_Zm_16_S_H {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UDOT_SVE_Zd_SVE_Zn_SVE_Zm3_19_INDEX {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(3)]
    pub sve_imm3: u32,
    #[bits(2)]
    pub imm2_19: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UDOT_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UDOT_Vd_Vn_Em {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UHADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UHADD_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UHSUB_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UHSUB_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UHSUBR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UMADDL_Rd_Rn_Rm_Ra {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(5)]
    pub ra: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UMAX_SME_Zdnx2_SME_Zdnx2_SME_Zm {
    #[bits(1)]
    pub _op_0: u32,
    #[bits(4)]
    pub sme_zdn2: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UMAX_SME_Zdnx2_SME_Zdnx2_SME_Zmx2 {
    #[bits(1)]
    pub _op_0: u32,
    #[bits(4)]
    pub sme_zdn2: u32,
    #[bits(12)]
    pub _op_5: u32,
    #[bits(4)]
    pub sme_zm2: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UMAX_SME_Zdnx4_SME_Zdnx4_SME_Zm {
    #[bits(2)]
    pub _op_0: u32,
    #[bits(3)]
    pub sme_zdn4: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UMAX_SME_Zdnx4_SME_Zdnx4_SME_Zmx4 {
    #[bits(2)]
    pub _op_0: u32,
    #[bits(3)]
    pub sme_zdn4: u32,
    #[bits(13)]
    pub _op_5: u32,
    #[bits(3)]
    pub sme_zm4: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UMAX_Rd_Rn_CSSC_UIMM8 {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(8)]
    pub cssc_imm8: u32,
    #[bits(14)]
    pub _op_18: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UMAX_Rd_Rn_Rm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UMAX_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zm_5: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UMAX_SVE_Zd_SVE_Zd_SVE_UIMM8 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(8)]
    pub sve_imm8: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UMAX_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UMAXP_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UMAXP_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UMAXQV_Vd_SVE_Pg3_SVE_Zn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UMAXV_SVE_Vd_SVE_Pg3_SVE_Zn {
    #[bits(5)]
    pub sve_vd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UMAXV_Fd_Vn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UMIN_SME_Zdnx2_SME_Zdnx2_SME_Zm {
    #[bits(1)]
    pub _op_0: u32,
    #[bits(4)]
    pub sme_zdn2: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UMIN_SME_Zdnx2_SME_Zdnx2_SME_Zmx2 {
    #[bits(1)]
    pub _op_0: u32,
    #[bits(4)]
    pub sme_zdn2: u32,
    #[bits(12)]
    pub _op_5: u32,
    #[bits(4)]
    pub sme_zm2: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UMIN_SME_Zdnx4_SME_Zdnx4_SME_Zm {
    #[bits(2)]
    pub _op_0: u32,
    #[bits(3)]
    pub sme_zdn4: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UMIN_SME_Zdnx4_SME_Zdnx4_SME_Zmx4 {
    #[bits(2)]
    pub _op_0: u32,
    #[bits(3)]
    pub sme_zdn4: u32,
    #[bits(13)]
    pub _op_5: u32,
    #[bits(3)]
    pub sme_zm4: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UMIN_Rd_Rn_CSSC_UIMM8 {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(8)]
    pub cssc_imm8: u32,
    #[bits(14)]
    pub _op_18: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UMIN_Rd_Rn_Rm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UMIN_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zm_5: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UMIN_SVE_Zd_SVE_Zd_SVE_UIMM8 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(8)]
    pub sve_imm8: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UMIN_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UMINP_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UMINP_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UMINQV_Vd_SVE_Pg3_SVE_Zn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UMINV_SVE_Vd_SVE_Pg3_SVE_Zn {
    #[bits(5)]
    pub sve_vd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UMINV_Fd_Vn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UMLAL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm_INDEX3_10 {
    #[bits(3)]
    pub imm3_0: u32,
    #[bits(2)]
    pub _op_3: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(2)]
    pub imm2_10: u32,
    #[bits(1)]
    pub _op_12: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub imm1_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UMLAL_SME_ZA_array_off2x2_SME_Znx2_SME_Zm_INDEX3_2 {
    #[bits(2)]
    pub imm2_0: u32,
    #[bits(1)]
    pub imm1_2: u32,
    #[bits(3)]
    pub _op_3: u32,
    #[bits(4)]
    pub sme_zn2: u32,
    #[bits(2)]
    pub imm2_10: u32,
    #[bits(1)]
    pub _op_12: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UMLAL_SME_ZA_array_off2x2_SME_Znx4_SME_Zm_INDEX3_2 {
    #[bits(2)]
    pub imm2_0: u32,
    #[bits(1)]
    pub imm1_2: u32,
    #[bits(4)]
    pub _op_3: u32,
    #[bits(3)]
    pub sme_zn4: u32,
    #[bits(2)]
    pub imm2_10: u32,
    #[bits(1)]
    pub _op_12: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UMLAL_SME_ZA_array_off2x2_SVE_ZnxN_SME_Zm {
    #[bits(2)]
    pub imm2_0: u32,
    #[bits(3)]
    pub _op_2: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UMLAL_SME_ZA_array_off2x2_S_S_SVE_ZnxN_S_H_SME_Zm_S_H {
    #[bits(2)]
    pub imm2_0: u32,
    #[bits(3)]
    pub _op_2: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UMLAL_SME_ZA_array_off2x2_SME_Znx2_SME_Zmx2 {
    #[bits(2)]
    pub imm2_0: u32,
    #[bits(4)]
    pub _op_2: u32,
    #[bits(4)]
    pub sme_zn2: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(2)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm2: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UMLAL_SME_ZA_array_off2x2_SME_Znx4_SME_Zmx4 {
    #[bits(2)]
    pub imm2_0: u32,
    #[bits(5)]
    pub _op_2: u32,
    #[bits(3)]
    pub sme_zn4: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(3)]
    pub _op_15: u32,
    #[bits(3)]
    pub sme_zm4: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UMLAL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm {
    #[bits(3)]
    pub imm3_0: u32,
    #[bits(2)]
    pub _op_3: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UMLAL_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UMLAL_Vd_Vn_Em16 {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UMLAL2_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UMLAL2_Vd_Vn_Em16 {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UMLALB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(1)]
    pub _op_10: u32,
    #[bits(1)]
    pub sve_i3l: u32,
    #[bits(4)]
    pub _op_12: u32,
    #[bits(3)]
    pub sve_imm3: u32,
    #[bits(2)]
    pub sve_i3h2: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UMLALB_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(1)]
    pub _op_10: u32,
    #[bits(1)]
    pub sve_i3l: u32,
    #[bits(4)]
    pub _op_12: u32,
    #[bits(4)]
    pub sve_imm4: u32,
    #[bits(1)]
    pub sve_i2h: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UMLALB_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UMLALL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm_INDEX4_10 {
    #[bits(2)]
    pub imm2_0: u32,
    #[bits(3)]
    pub _op_2: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub imm3_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub imm1_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UMLALL_SME_ZA_array_off1x4_SME_Znx2_SME_Zm_INDEX4_1 {
    #[bits(1)]
    pub imm1_0: u32,
    #[bits(2)]
    pub imm2_1: u32,
    #[bits(3)]
    pub _op_3: u32,
    #[bits(4)]
    pub sme_zn2: u32,
    #[bits(2)]
    pub imm2_10: u32,
    #[bits(1)]
    pub _op_12: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UMLALL_SME_ZA_array_off1x4_SME_Znx4_SME_Zm_INDEX4_1 {
    #[bits(1)]
    pub imm1_0: u32,
    #[bits(2)]
    pub imm2_1: u32,
    #[bits(4)]
    pub _op_3: u32,
    #[bits(3)]
    pub sme_zn4: u32,
    #[bits(2)]
    pub imm2_10: u32,
    #[bits(1)]
    pub _op_12: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UMLALL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm_INDEX3_10 {
    #[bits(2)]
    pub imm2_0: u32,
    #[bits(3)]
    pub _op_2: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(2)]
    pub imm2_10: u32,
    #[bits(1)]
    pub _op_12: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub imm1_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UMLALL_SME_ZA_array_off1x4_SME_Znx2_SME_Zm_INDEX3_1 {
    #[bits(1)]
    pub imm1_0: u32,
    #[bits(2)]
    pub imm2_1: u32,
    #[bits(3)]
    pub _op_3: u32,
    #[bits(4)]
    pub sme_zn2: u32,
    #[bits(1)]
    pub imm1_10: u32,
    #[bits(2)]
    pub _op_11: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UMLALL_SME_ZA_array_off1x4_SME_Znx4_SME_Zm_INDEX3_1 {
    #[bits(1)]
    pub imm1_0: u32,
    #[bits(2)]
    pub imm2_1: u32,
    #[bits(4)]
    pub _op_3: u32,
    #[bits(3)]
    pub sme_zn4: u32,
    #[bits(1)]
    pub imm1_10: u32,
    #[bits(2)]
    pub _op_11: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UMLALL_SME_ZA_array_off1x4_SVE_ZnxN_SME_Zm {
    #[bits(1)]
    pub imm1_0: u32,
    #[bits(4)]
    pub _op_1: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UMLALL_SME_ZA_array_off1x4_S_S_SVE_ZnxN_S_B_SME_Zm_S_B {
    #[bits(1)]
    pub imm1_0: u32,
    #[bits(4)]
    pub _op_1: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UMLALL_SME_ZA_array_off1x4_SME_Znx2_SME_Zmx2 {
    #[bits(1)]
    pub imm1_0: u32,
    #[bits(5)]
    pub _op_1: u32,
    #[bits(4)]
    pub sme_zn2: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(2)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm2: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UMLALL_SME_ZA_array_off1x4_SME_Znx4_SME_Zmx4 {
    #[bits(1)]
    pub imm1_0: u32,
    #[bits(6)]
    pub _op_1: u32,
    #[bits(3)]
    pub sme_zn4: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(3)]
    pub _op_15: u32,
    #[bits(3)]
    pub sme_zm4: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UMLALL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm {
    #[bits(2)]
    pub imm2_0: u32,
    #[bits(3)]
    pub _op_2: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UMLALT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(1)]
    pub _op_10: u32,
    #[bits(1)]
    pub sve_i3l: u32,
    #[bits(4)]
    pub _op_12: u32,
    #[bits(3)]
    pub sve_imm3: u32,
    #[bits(2)]
    pub sve_i3h2: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UMLALT_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(1)]
    pub _op_10: u32,
    #[bits(1)]
    pub sve_i3l: u32,
    #[bits(4)]
    pub _op_12: u32,
    #[bits(4)]
    pub sve_imm4: u32,
    #[bits(1)]
    pub sve_i2h: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UMLALT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UMLSL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm_INDEX3_10 {
    #[bits(3)]
    pub imm3_0: u32,
    #[bits(2)]
    pub _op_3: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(2)]
    pub imm2_10: u32,
    #[bits(1)]
    pub _op_12: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub imm1_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UMLSL_SME_ZA_array_off2x2_SME_Znx2_SME_Zm_INDEX3_2 {
    #[bits(2)]
    pub imm2_0: u32,
    #[bits(1)]
    pub imm1_2: u32,
    #[bits(3)]
    pub _op_3: u32,
    #[bits(4)]
    pub sme_zn2: u32,
    #[bits(2)]
    pub imm2_10: u32,
    #[bits(1)]
    pub _op_12: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UMLSL_SME_ZA_array_off2x2_SME_Znx4_SME_Zm_INDEX3_2 {
    #[bits(2)]
    pub imm2_0: u32,
    #[bits(1)]
    pub imm1_2: u32,
    #[bits(4)]
    pub _op_3: u32,
    #[bits(3)]
    pub sme_zn4: u32,
    #[bits(2)]
    pub imm2_10: u32,
    #[bits(1)]
    pub _op_12: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UMLSL_SME_ZA_array_off2x2_SVE_ZnxN_SME_Zm {
    #[bits(2)]
    pub imm2_0: u32,
    #[bits(3)]
    pub _op_2: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UMLSL_SME_ZA_array_off2x2_S_S_SVE_ZnxN_S_H_SME_Zm_S_H {
    #[bits(2)]
    pub imm2_0: u32,
    #[bits(3)]
    pub _op_2: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UMLSL_SME_ZA_array_off2x2_SME_Znx2_SME_Zmx2 {
    #[bits(2)]
    pub imm2_0: u32,
    #[bits(4)]
    pub _op_2: u32,
    #[bits(4)]
    pub sme_zn2: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(2)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm2: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UMLSL_SME_ZA_array_off2x2_SME_Znx4_SME_Zmx4 {
    #[bits(2)]
    pub imm2_0: u32,
    #[bits(5)]
    pub _op_2: u32,
    #[bits(3)]
    pub sme_zn4: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(3)]
    pub _op_15: u32,
    #[bits(3)]
    pub sme_zm4: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UMLSL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm {
    #[bits(3)]
    pub imm3_0: u32,
    #[bits(2)]
    pub _op_3: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UMLSL_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UMLSL_Vd_Vn_Em16 {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UMLSL2_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UMLSL2_Vd_Vn_Em16 {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UMLSLB_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UMLSLB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(1)]
    pub _op_10: u32,
    #[bits(1)]
    pub sve_i3l: u32,
    #[bits(4)]
    pub _op_12: u32,
    #[bits(3)]
    pub sve_imm3: u32,
    #[bits(2)]
    pub sve_i3h2: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UMLSLB_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(1)]
    pub _op_10: u32,
    #[bits(1)]
    pub sve_i3l: u32,
    #[bits(4)]
    pub _op_12: u32,
    #[bits(4)]
    pub sve_imm4: u32,
    #[bits(1)]
    pub sve_i2h: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UMLSLL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm_INDEX4_10 {
    #[bits(2)]
    pub imm2_0: u32,
    #[bits(3)]
    pub _op_2: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub imm3_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub imm1_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UMLSLL_SME_ZA_array_off1x4_SME_Znx2_SME_Zm_INDEX4_1 {
    #[bits(1)]
    pub imm1_0: u32,
    #[bits(2)]
    pub imm2_1: u32,
    #[bits(3)]
    pub _op_3: u32,
    #[bits(4)]
    pub sme_zn2: u32,
    #[bits(2)]
    pub imm2_10: u32,
    #[bits(1)]
    pub _op_12: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UMLSLL_SME_ZA_array_off1x4_SME_Znx4_SME_Zm_INDEX4_1 {
    #[bits(1)]
    pub imm1_0: u32,
    #[bits(2)]
    pub imm2_1: u32,
    #[bits(4)]
    pub _op_3: u32,
    #[bits(3)]
    pub sme_zn4: u32,
    #[bits(2)]
    pub imm2_10: u32,
    #[bits(1)]
    pub _op_12: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UMLSLL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm_INDEX3_10 {
    #[bits(2)]
    pub imm2_0: u32,
    #[bits(3)]
    pub _op_2: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(2)]
    pub imm2_10: u32,
    #[bits(1)]
    pub _op_12: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub imm1_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UMLSLL_SME_ZA_array_off1x4_SME_Znx2_SME_Zm_INDEX3_1 {
    #[bits(1)]
    pub imm1_0: u32,
    #[bits(2)]
    pub imm2_1: u32,
    #[bits(3)]
    pub _op_3: u32,
    #[bits(4)]
    pub sme_zn2: u32,
    #[bits(1)]
    pub imm1_10: u32,
    #[bits(2)]
    pub _op_11: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UMLSLL_SME_ZA_array_off1x4_SME_Znx4_SME_Zm_INDEX3_1 {
    #[bits(1)]
    pub imm1_0: u32,
    #[bits(2)]
    pub imm2_1: u32,
    #[bits(4)]
    pub _op_3: u32,
    #[bits(3)]
    pub sme_zn4: u32,
    #[bits(1)]
    pub imm1_10: u32,
    #[bits(2)]
    pub _op_11: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UMLSLL_SME_ZA_array_off1x4_SVE_ZnxN_SME_Zm {
    #[bits(1)]
    pub imm1_0: u32,
    #[bits(4)]
    pub _op_1: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UMLSLL_SME_ZA_array_off1x4_S_S_SVE_ZnxN_S_B_SME_Zm_S_B {
    #[bits(1)]
    pub imm1_0: u32,
    #[bits(4)]
    pub _op_1: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UMLSLL_SME_ZA_array_off1x4_SME_Znx2_SME_Zmx2 {
    #[bits(1)]
    pub imm1_0: u32,
    #[bits(5)]
    pub _op_1: u32,
    #[bits(4)]
    pub sme_zn2: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(2)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm2: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UMLSLL_SME_ZA_array_off1x4_SME_Znx4_SME_Zmx4 {
    #[bits(1)]
    pub imm1_0: u32,
    #[bits(6)]
    pub _op_1: u32,
    #[bits(3)]
    pub sme_zn4: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(3)]
    pub _op_15: u32,
    #[bits(3)]
    pub sme_zm4: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UMLSLL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm {
    #[bits(2)]
    pub imm2_0: u32,
    #[bits(3)]
    pub _op_2: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UMLSLT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UMLSLT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(1)]
    pub _op_10: u32,
    #[bits(1)]
    pub sve_i3l: u32,
    #[bits(4)]
    pub _op_12: u32,
    #[bits(3)]
    pub sve_imm3: u32,
    #[bits(2)]
    pub sve_i3h2: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UMLSLT_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(1)]
    pub _op_10: u32,
    #[bits(1)]
    pub sve_i3l: u32,
    #[bits(4)]
    pub _op_12: u32,
    #[bits(4)]
    pub sve_imm4: u32,
    #[bits(1)]
    pub sve_i2h: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UMMLA_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UMMLA_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UMOPA_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16 {
    #[bits(2)]
    pub sme_zada_2b: u32,
    #[bits(3)]
    pub _op_2: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub sme_pm: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UMOPA_SME_ZAda_2b_S_S_SVE_Pg3_P_M_SME_Pm_P_M_SVE_Zn_S_B_SVE_Zm_16_S_B {
    #[bits(2)]
    pub sme_zada_2b: u32,
    #[bits(3)]
    pub _op_2: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub sme_pm: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UMOPA_SME_ZAda_3b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16 {
    #[bits(3)]
    pub sme_zada_3b: u32,
    #[bits(2)]
    pub _op_3: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub sme_pm: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UMOPS_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16 {
    #[bits(2)]
    pub sme_zada_2b: u32,
    #[bits(3)]
    pub _op_2: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub sme_pm: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UMOPS_SME_ZAda_2b_S_S_SVE_Pg3_P_M_SME_Pm_P_M_SVE_Zn_S_B_SVE_Zm_16_S_B {
    #[bits(2)]
    pub sme_zada_2b: u32,
    #[bits(3)]
    pub _op_2: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub sme_pm: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UMOPS_SME_ZAda_3b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16 {
    #[bits(3)]
    pub sme_zada_3b: u32,
    #[bits(2)]
    pub _op_3: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub sme_pm: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UMOV_Rd_En {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UMSUBL_Rd_Rn_Rm_Ra {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(5)]
    pub ra: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UMULH_Rd_Rn_Rm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UMULH_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zm_5: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UMULH_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UMULL_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UMULL_Vd_Vn_Em16 {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UMULL2_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UMULL2_Vd_Vn_Em16 {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UMULLB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(1)]
    pub _op_10: u32,
    #[bits(1)]
    pub sve_i3l: u32,
    #[bits(4)]
    pub _op_12: u32,
    #[bits(3)]
    pub sve_imm3: u32,
    #[bits(2)]
    pub sve_i3h2: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UMULLB_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(1)]
    pub _op_10: u32,
    #[bits(1)]
    pub sve_i3l: u32,
    #[bits(4)]
    pub _op_12: u32,
    #[bits(4)]
    pub sve_imm4: u32,
    #[bits(1)]
    pub sve_i2h: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UMULLB_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UMULLT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(1)]
    pub _op_10: u32,
    #[bits(1)]
    pub sve_i3l: u32,
    #[bits(4)]
    pub _op_12: u32,
    #[bits(3)]
    pub sve_imm3: u32,
    #[bits(2)]
    pub sve_i3h2: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UMULLT_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(1)]
    pub _op_10: u32,
    #[bits(1)]
    pub sve_i3l: u32,
    #[bits(4)]
    pub _op_12: u32,
    #[bits(4)]
    pub sve_imm4: u32,
    #[bits(1)]
    pub sve_i2h: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UMULLT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UQADD_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UQADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UQADD_SVE_Zd_SVE_Zd_SVE_AIMM {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(9)]
    pub sve_imm9: u32,
    #[bits(18)]
    pub _op_14: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UQADD_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UQADD_Sd_Sn_Sm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UQCVT_SVE_Zd_SME_Znx2 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(1)]
    pub _op_5: u32,
    #[bits(4)]
    pub sme_zn2: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UQCVT_SVE_Zd_SME_Znx4 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(2)]
    pub _op_5: u32,
    #[bits(3)]
    pub sme_zn4: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UQCVTN_SVE_Zd_SME_Znx4 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(2)]
    pub _op_5: u32,
    #[bits(3)]
    pub sme_zn4: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UQCVTN_SVE_Zd_SME_Znx2 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(1)]
    pub _op_5: u32,
    #[bits(4)]
    pub sme_zn2: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UQDECB_Rd_SVE_PATTERN_SCALED {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub sve_pattern: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UQDECB_Rd_X_SVE_PATTERN_SCALED {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub sve_pattern: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UQDECD_SVE_Zd_SVE_PATTERN_SCALED {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_pattern: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UQDECD_Rd_SVE_PATTERN_SCALED {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub sve_pattern: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UQDECD_Rd_X_SVE_PATTERN_SCALED {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub sve_pattern: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UQDECH_SVE_Zd_SVE_PATTERN_SCALED {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_pattern: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UQDECH_Rd_SVE_PATTERN_SCALED {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub sve_pattern: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UQDECH_Rd_X_SVE_PATTERN_SCALED {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub sve_pattern: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UQDECP_SVE_Zd_SVE_Pg4_5 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(4)]
    pub sve_pg4_5: u32,
    #[bits(23)]
    pub _op_9: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UQDECP_Rd_SVE_Pg4_5 {
    #[bits(5)]
    pub rd: u32,
    #[bits(4)]
    pub sve_pg4_5: u32,
    #[bits(23)]
    pub _op_9: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UQDECP_Rd_X_SVE_Pg4_5_S_B {
    #[bits(5)]
    pub rd: u32,
    #[bits(4)]
    pub sve_pg4_5: u32,
    #[bits(23)]
    pub _op_9: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UQDECW_SVE_Zd_SVE_PATTERN_SCALED {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_pattern: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UQDECW_Rd_SVE_PATTERN_SCALED {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub sve_pattern: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UQDECW_Rd_X_SVE_PATTERN_SCALED {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub sve_pattern: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UQINCB_Rd_SVE_PATTERN_SCALED {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub sve_pattern: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UQINCB_Rd_X_SVE_PATTERN_SCALED {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub sve_pattern: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UQINCD_SVE_Zd_SVE_PATTERN_SCALED {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_pattern: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UQINCD_Rd_SVE_PATTERN_SCALED {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub sve_pattern: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UQINCD_Rd_X_SVE_PATTERN_SCALED {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub sve_pattern: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UQINCH_SVE_Zd_SVE_PATTERN_SCALED {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_pattern: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UQINCH_Rd_SVE_PATTERN_SCALED {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub sve_pattern: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UQINCH_Rd_X_SVE_PATTERN_SCALED {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub sve_pattern: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UQINCP_SVE_Zd_SVE_Pg4_5 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(4)]
    pub sve_pg4_5: u32,
    #[bits(23)]
    pub _op_9: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UQINCP_Rd_SVE_Pg4_5 {
    #[bits(5)]
    pub rd: u32,
    #[bits(4)]
    pub sve_pg4_5: u32,
    #[bits(23)]
    pub _op_9: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UQINCP_Rd_X_SVE_Pg4_5_S_B {
    #[bits(5)]
    pub rd: u32,
    #[bits(4)]
    pub sve_pg4_5: u32,
    #[bits(23)]
    pub _op_9: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UQINCW_SVE_Zd_SVE_PATTERN_SCALED {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_pattern: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UQINCW_Rd_SVE_PATTERN_SCALED {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub sve_pattern: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UQINCW_Rd_X_SVE_PATTERN_SCALED {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub sve_pattern: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UQRSHL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UQRSHL_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UQRSHL_Sd_Sn_Sm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UQRSHLR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UQRSHR_SVE_Zd_SME_Znx4_SME_SHRIMM5 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(2)]
    pub _op_5: u32,
    #[bits(3)]
    pub sme_zn4: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_imm5b: u32,
    #[bits(1)]
    pub _op_21: u32,
    #[bits(2)]
    pub sve_tszh: u32,
    #[bits(8)]
    pub _op_24: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UQRSHR_SVE_Zd_SME_Znx2_SME_SHRIMM4 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(1)]
    pub _op_5: u32,
    #[bits(4)]
    pub sme_zn2: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(4)]
    pub sve_imm4: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UQRSHRN_SVE_Zd_SME_Znx4_SME_SHRIMM5 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(2)]
    pub _op_5: u32,
    #[bits(3)]
    pub sme_zn4: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_imm5b: u32,
    #[bits(1)]
    pub _op_21: u32,
    #[bits(2)]
    pub sve_tszh: u32,
    #[bits(8)]
    pub _op_24: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UQRSHRN_SVE_Zd_SME_Znx2_SME_SHRIMM4 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(1)]
    pub _op_5: u32,
    #[bits(4)]
    pub sme_zn2: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(4)]
    pub sve_imm4: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UQRSHRN_Vd_Vn_IMM_VLSR {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UQRSHRN_Sd_Sn_IMM_VLSR {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UQRSHRN2_Vd_Vn_IMM_VLSR {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UQRSHRNB_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(3)]
    pub sve_imm3: u32,
    #[bits(2)]
    pub sve_tszl_19: u32,
    #[bits(1)]
    pub _op_21: u32,
    #[bits(1)]
    pub sve_sz: u32,
    #[bits(9)]
    pub _op_23: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UQRSHRNT_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(3)]
    pub sve_imm3: u32,
    #[bits(2)]
    pub sve_tszl_19: u32,
    #[bits(1)]
    pub _op_21: u32,
    #[bits(1)]
    pub sve_sz: u32,
    #[bits(9)]
    pub _op_23: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UQSHL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UQSHL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_SHLIMM_PRED {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_imm5: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(9)]
    pub _op_13: u32,
    #[bits(2)]
    pub sve_tszh: u32,
    #[bits(8)]
    pub _op_24: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UQSHL_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UQSHL_Sd_Sn_Sm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UQSHL_Vd_Vn_IMM_VLSL {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UQSHL_Sd_Sn_IMM_VLSL {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UQSHLR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UQSHRN_Vd_Vn_IMM_VLSR {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UQSHRN_Sd_Sn_IMM_VLSR {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UQSHRN2_Vd_Vn_IMM_VLSR {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UQSHRNB_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(3)]
    pub sve_imm3: u32,
    #[bits(2)]
    pub sve_tszl_19: u32,
    #[bits(1)]
    pub _op_21: u32,
    #[bits(1)]
    pub sve_sz: u32,
    #[bits(9)]
    pub _op_23: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UQSHRNT_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(3)]
    pub sve_imm3: u32,
    #[bits(2)]
    pub sve_tszl_19: u32,
    #[bits(1)]
    pub _op_21: u32,
    #[bits(1)]
    pub sve_sz: u32,
    #[bits(9)]
    pub _op_23: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UQSUB_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UQSUB_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UQSUB_SVE_Zd_SVE_Zd_SVE_AIMM {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(9)]
    pub sve_imm9: u32,
    #[bits(18)]
    pub _op_14: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UQSUB_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UQSUB_Sd_Sn_Sm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UQSUBR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UQXTN_Vd_Vn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UQXTN_Sd_Sn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UQXTN2_Vd_Vn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UQXTNB_SVE_Zd_SVE_Zn {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UQXTNT_SVE_Zd_SVE_Zn {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct URECPE_SVE_Zd_SVE_Pg3_SVE_Zn {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct URECPE_Vd_Vn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct URHADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct URHADD_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct URSHL_SME_Zdnx2_SME_Zdnx2_SME_Zm {
    #[bits(1)]
    pub _op_0: u32,
    #[bits(4)]
    pub sme_zdn2: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct URSHL_SME_Zdnx2_SME_Zdnx2_SME_Zmx2 {
    #[bits(1)]
    pub _op_0: u32,
    #[bits(4)]
    pub sme_zdn2: u32,
    #[bits(12)]
    pub _op_5: u32,
    #[bits(4)]
    pub sme_zm2: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct URSHL_SME_Zdnx4_SME_Zdnx4_SME_Zm {
    #[bits(2)]
    pub _op_0: u32,
    #[bits(3)]
    pub sme_zdn4: u32,
    #[bits(11)]
    pub _op_5: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct URSHL_SME_Zdnx4_SME_Zdnx4_SME_Zmx4 {
    #[bits(2)]
    pub _op_0: u32,
    #[bits(3)]
    pub sme_zdn4: u32,
    #[bits(13)]
    pub _op_5: u32,
    #[bits(3)]
    pub sme_zm4: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct URSHL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct URSHL_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct URSHL_Sd_Sn_Sm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct URSHLR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct URSHR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_SHRIMM_PRED {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_imm5: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(9)]
    pub _op_13: u32,
    #[bits(2)]
    pub sve_tszh: u32,
    #[bits(8)]
    pub _op_24: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct URSHR_Vd_Vn_IMM_VLSR {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct URSHR_Sd_Sn_IMM_VLSR {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct URSQRTE_SVE_Zd_SVE_Pg3_SVE_Zn {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct URSQRTE_Vd_Vn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct URSRA_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub imm5: u32,
    #[bits(1)]
    pub _op_21: u32,
    #[bits(2)]
    pub sve_tszh: u32,
    #[bits(8)]
    pub _op_24: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct URSRA_Vd_Vn_IMM_VLSR {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct URSRA_Sd_Sn_IMM_VLSR {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct USDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2 {
    #[bits(3)]
    pub imm3_0: u32,
    #[bits(3)]
    pub _op_3: u32,
    #[bits(4)]
    pub sme_zn2: u32,
    #[bits(2)]
    pub imm2_10: u32,
    #[bits(1)]
    pub _op_12: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct USDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2 {
    #[bits(3)]
    pub imm3_0: u32,
    #[bits(4)]
    pub _op_3: u32,
    #[bits(3)]
    pub sme_zn4: u32,
    #[bits(2)]
    pub imm2_10: u32,
    #[bits(1)]
    pub _op_12: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct USDOT_SME_ZA_array_off3_0_SVE_ZnxN_SME_Zm {
    #[bits(3)]
    pub imm3_0: u32,
    #[bits(2)]
    pub _op_3: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct USDOT_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_B_SME_Zm_S_B {
    #[bits(3)]
    pub imm3_0: u32,
    #[bits(2)]
    pub _op_3: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct USDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zmx2 {
    #[bits(3)]
    pub imm3_0: u32,
    #[bits(3)]
    pub _op_3: u32,
    #[bits(4)]
    pub sme_zn2: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(2)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm2: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct USDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zmx4 {
    #[bits(3)]
    pub imm3_0: u32,
    #[bits(4)]
    pub _op_3: u32,
    #[bits(3)]
    pub sme_zn4: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(3)]
    pub _op_15: u32,
    #[bits(3)]
    pub sme_zm4: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct USDOT_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct USDOT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct USDOT_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct USDOT_Vd_Vn_Em {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct USHL_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct USHL_Sd_Sn_Sm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct USHLL_Vd_Vn_IMM_VLSL {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct USHLL2_Vd_Vn_IMM_VLSL {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct USHLLB_SVE_Zd_SVE_Zn_SVE_SHLIMM_UNPRED_22 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(3)]
    pub sve_imm3: u32,
    #[bits(2)]
    pub sve_tszl_19: u32,
    #[bits(1)]
    pub _op_21: u32,
    #[bits(1)]
    pub sve_sz: u32,
    #[bits(9)]
    pub _op_23: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct USHLLT_SVE_Zd_SVE_Zn_SVE_SHLIMM_UNPRED_22 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(3)]
    pub sve_imm3: u32,
    #[bits(2)]
    pub sve_tszl_19: u32,
    #[bits(1)]
    pub _op_21: u32,
    #[bits(1)]
    pub sve_sz: u32,
    #[bits(9)]
    pub _op_23: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct USHR_Vd_Vn_IMM_VLSR {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct USHR_Sd_Sn_IMM_VLSR {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct USMLALL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm_INDEX4_10 {
    #[bits(2)]
    pub imm2_0: u32,
    #[bits(3)]
    pub _op_2: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub imm3_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub imm1_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct USMLALL_SME_ZA_array_off1x4_SME_Znx2_SME_Zm_INDEX4_1 {
    #[bits(1)]
    pub imm1_0: u32,
    #[bits(2)]
    pub imm2_1: u32,
    #[bits(3)]
    pub _op_3: u32,
    #[bits(4)]
    pub sme_zn2: u32,
    #[bits(2)]
    pub imm2_10: u32,
    #[bits(1)]
    pub _op_12: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct USMLALL_SME_ZA_array_off1x4_SME_Znx4_SME_Zm_INDEX4_1 {
    #[bits(1)]
    pub imm1_0: u32,
    #[bits(2)]
    pub imm2_1: u32,
    #[bits(4)]
    pub _op_3: u32,
    #[bits(3)]
    pub sme_zn4: u32,
    #[bits(2)]
    pub imm2_10: u32,
    #[bits(1)]
    pub _op_12: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct USMLALL_SME_ZA_array_off1x4_SVE_ZnxN_SME_Zm {
    #[bits(1)]
    pub imm1_0: u32,
    #[bits(4)]
    pub _op_1: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct USMLALL_SME_ZA_array_off1x4_S_S_SVE_ZnxN_S_B_SME_Zm_S_B {
    #[bits(1)]
    pub imm1_0: u32,
    #[bits(4)]
    pub _op_1: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct USMLALL_SME_ZA_array_off1x4_SME_Znx2_SME_Zmx2 {
    #[bits(1)]
    pub imm1_0: u32,
    #[bits(5)]
    pub _op_1: u32,
    #[bits(4)]
    pub sme_zn2: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(2)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm2: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct USMLALL_SME_ZA_array_off1x4_SME_Znx4_SME_Zmx4 {
    #[bits(1)]
    pub imm1_0: u32,
    #[bits(6)]
    pub _op_1: u32,
    #[bits(3)]
    pub sme_zn4: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(3)]
    pub _op_15: u32,
    #[bits(3)]
    pub sme_zm4: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct USMLALL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm {
    #[bits(2)]
    pub imm2_0: u32,
    #[bits(3)]
    pub _op_2: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct USMMLA_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct USMMLA_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct USMOPA_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16 {
    #[bits(2)]
    pub sme_zada_2b: u32,
    #[bits(3)]
    pub _op_2: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub sme_pm: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct USMOPA_SME_ZAda_3b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16 {
    #[bits(3)]
    pub sme_zada_3b: u32,
    #[bits(2)]
    pub _op_3: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub sme_pm: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct USMOPS_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16 {
    #[bits(2)]
    pub sme_zada_2b: u32,
    #[bits(3)]
    pub _op_2: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub sme_pm: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct USMOPS_SME_ZAda_3b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16 {
    #[bits(3)]
    pub sme_zada_3b: u32,
    #[bits(2)]
    pub _op_3: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(3)]
    pub sme_pm: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct USQADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct USQADD_Vd_Vn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct USQADD_Sd_Sn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct USRA_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub imm5: u32,
    #[bits(1)]
    pub _op_21: u32,
    #[bits(2)]
    pub sve_tszh: u32,
    #[bits(8)]
    pub _op_24: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct USRA_Vd_Vn_IMM_VLSR {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct USRA_Sd_Sn_IMM_VLSR {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct USUBL_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct USUBL2_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct USUBLB_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct USUBLT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct USUBW_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct USUBW2_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct USUBWB_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct USUBWT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct USVDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2 {
    #[bits(3)]
    pub imm3_0: u32,
    #[bits(4)]
    pub _op_3: u32,
    #[bits(3)]
    pub sme_zn4: u32,
    #[bits(2)]
    pub imm2_10: u32,
    #[bits(1)]
    pub _op_12: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UUNPK_SME_Zdnx2_SVE_Zn {
    #[bits(1)]
    pub _op_0: u32,
    #[bits(4)]
    pub sme_zdn2: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UUNPK_SME_Zdnx4_SME_Znx2 {
    #[bits(2)]
    pub _op_0: u32,
    #[bits(3)]
    pub sme_zdn4: u32,
    #[bits(1)]
    pub _op_5: u32,
    #[bits(4)]
    pub sme_zn2: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UUNPKHI_SVE_Zd_SVE_Zn {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UUNPKLO_SVE_Zd_SVE_Zn {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UVDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2 {
    #[bits(3)]
    pub imm3_0: u32,
    #[bits(3)]
    pub _op_3: u32,
    #[bits(4)]
    pub sme_zn2: u32,
    #[bits(2)]
    pub imm2_10: u32,
    #[bits(1)]
    pub _op_12: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UVDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2 {
    #[bits(3)]
    pub imm3_0: u32,
    #[bits(4)]
    pub _op_3: u32,
    #[bits(3)]
    pub sme_zn4: u32,
    #[bits(2)]
    pub imm2_10: u32,
    #[bits(1)]
    pub _op_12: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UVDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX1 {
    #[bits(3)]
    pub imm3_0: u32,
    #[bits(4)]
    pub _op_3: u32,
    #[bits(3)]
    pub sme_zn4: u32,
    #[bits(1)]
    pub imm1_10: u32,
    #[bits(2)]
    pub _op_11: u32,
    #[bits(2)]
    pub sme_rv: u32,
    #[bits(1)]
    pub _op_15: u32,
    #[bits(4)]
    pub sme_zm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UXTB_SVE_Zd_SVE_Pg3_SVE_Zn {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UXTH_SVE_Zd_SVE_Pg3_SVE_Zn {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UXTW_SVE_Zd_SVE_Pg3_SVE_Zn {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(3)]
    pub sve_pg3: u32,
    #[bits(19)]
    pub _op_13: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UZP_SME_Zdnx2_SVE_Zn_SVE_Zm_16 {
    #[bits(1)]
    pub _op_0: u32,
    #[bits(4)]
    pub sme_zdn2: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UZP_SME_Zdnx2_S_Q_SVE_Zn_S_Q_SVE_Zm_16_S_Q {
    #[bits(1)]
    pub _op_0: u32,
    #[bits(4)]
    pub sme_zdn2: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UZP_SME_Zdnx4_SME_Znx4 {
    #[bits(2)]
    pub _op_0: u32,
    #[bits(3)]
    pub sme_zdn4: u32,
    #[bits(2)]
    pub _op_5: u32,
    #[bits(3)]
    pub sme_zn4: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UZP_SME_Zdnx4_S_Q_SME_Znx4_S_Q {
    #[bits(2)]
    pub _op_0: u32,
    #[bits(3)]
    pub sme_zdn4: u32,
    #[bits(2)]
    pub _op_5: u32,
    #[bits(3)]
    pub sme_zn4: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UZP1_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UZP1_SVE_Pd_SVE_Pn_SVE_Pm {
    #[bits(4)]
    pub sve_pd: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(4)]
    pub sve_pn: u32,
    #[bits(7)]
    pub _op_9: u32,
    #[bits(4)]
    pub sve_pm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UZP1_SVE_Zd_S_B_SVE_Zn_S_B_SVE_Zm_16_S_B {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UZP1_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UZP2_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UZP2_SVE_Pd_SVE_Pn_SVE_Pm {
    #[bits(4)]
    pub sve_pd: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(4)]
    pub sve_pn: u32,
    #[bits(7)]
    pub _op_9: u32,
    #[bits(4)]
    pub sve_pm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UZP2_SVE_Zd_S_B_SVE_Zn_S_B_SVE_Zm_16_S_B {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct UZP2_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct WFET_Rd {
    #[bits(5)]
    pub rd: u32,
    #[bits(27)]
    pub _op_5: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct WFIT_Rd {
    #[bits(5)]
    pub rd: u32,
    #[bits(27)]
    pub _op_5: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct WHILEGE_SVE_Pd_Rn_Rm {
    #[bits(4)]
    pub sve_pd: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct WHILEGE_SVE_Pd_S_B_Rn_X_Rm_X {
    #[bits(4)]
    pub sve_pd: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct WHILEGE_SME_PNd3_Rn_Rm_SME_VLxN_13 {
    #[bits(3)]
    pub sme_pnd3: u32,
    #[bits(2)]
    pub _op_3: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(1)]
    pub sme_vl_13: u32,
    #[bits(2)]
    pub _op_14: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct WHILEGE_SME_Pdx2_Rn_Rm {
    #[bits(1)]
    pub _op_0: u32,
    #[bits(3)]
    pub sme_pdx2: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct WHILEGT_SVE_Pd_Rn_Rm {
    #[bits(4)]
    pub sve_pd: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct WHILEGT_SVE_Pd_S_B_Rn_X_Rm_X {
    #[bits(4)]
    pub sve_pd: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct WHILEGT_SME_PNd3_Rn_Rm_SME_VLxN_13 {
    #[bits(3)]
    pub sme_pnd3: u32,
    #[bits(2)]
    pub _op_3: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(1)]
    pub sme_vl_13: u32,
    #[bits(2)]
    pub _op_14: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct WHILEGT_SME_Pdx2_Rn_Rm {
    #[bits(1)]
    pub _op_0: u32,
    #[bits(3)]
    pub sme_pdx2: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct WHILEHI_SVE_Pd_Rn_Rm {
    #[bits(4)]
    pub sve_pd: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct WHILEHI_SVE_Pd_S_B_Rn_X_Rm_X {
    #[bits(4)]
    pub sve_pd: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct WHILEHI_SME_PNd3_Rn_Rm_SME_VLxN_13 {
    #[bits(3)]
    pub sme_pnd3: u32,
    #[bits(2)]
    pub _op_3: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(1)]
    pub sme_vl_13: u32,
    #[bits(2)]
    pub _op_14: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct WHILEHI_SME_Pdx2_Rn_Rm {
    #[bits(1)]
    pub _op_0: u32,
    #[bits(3)]
    pub sme_pdx2: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct WHILEHS_SVE_Pd_Rn_Rm {
    #[bits(4)]
    pub sve_pd: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct WHILEHS_SVE_Pd_S_B_Rn_X_Rm_X {
    #[bits(4)]
    pub sve_pd: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct WHILEHS_SME_PNd3_Rn_Rm_SME_VLxN_13 {
    #[bits(3)]
    pub sme_pnd3: u32,
    #[bits(2)]
    pub _op_3: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(1)]
    pub sme_vl_13: u32,
    #[bits(2)]
    pub _op_14: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct WHILEHS_SME_Pdx2_Rn_Rm {
    #[bits(1)]
    pub _op_0: u32,
    #[bits(3)]
    pub sme_pdx2: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct WHILELE_SVE_Pd_Rn_Rm {
    #[bits(4)]
    pub sve_pd: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct WHILELE_SVE_Pd_S_B_Rn_X_Rm_X {
    #[bits(4)]
    pub sve_pd: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct WHILELE_SME_PNd3_Rn_Rm_SME_VLxN_13 {
    #[bits(3)]
    pub sme_pnd3: u32,
    #[bits(2)]
    pub _op_3: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(1)]
    pub sme_vl_13: u32,
    #[bits(2)]
    pub _op_14: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct WHILELE_SME_Pdx2_Rn_Rm {
    #[bits(1)]
    pub _op_0: u32,
    #[bits(3)]
    pub sme_pdx2: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct WHILELO_SVE_Pd_Rn_Rm {
    #[bits(4)]
    pub sve_pd: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct WHILELO_SVE_Pd_S_B_Rn_X_Rm_X {
    #[bits(4)]
    pub sve_pd: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct WHILELO_SME_PNd3_Rn_Rm_SME_VLxN_13 {
    #[bits(3)]
    pub sme_pnd3: u32,
    #[bits(2)]
    pub _op_3: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(1)]
    pub sme_vl_13: u32,
    #[bits(2)]
    pub _op_14: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct WHILELO_SME_Pdx2_Rn_Rm {
    #[bits(1)]
    pub _op_0: u32,
    #[bits(3)]
    pub sme_pdx2: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct WHILELS_SVE_Pd_Rn_Rm {
    #[bits(4)]
    pub sve_pd: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct WHILELS_SVE_Pd_S_B_Rn_X_Rm_X {
    #[bits(4)]
    pub sve_pd: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct WHILELS_SME_PNd3_Rn_Rm_SME_VLxN_13 {
    #[bits(3)]
    pub sme_pnd3: u32,
    #[bits(2)]
    pub _op_3: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(1)]
    pub sme_vl_13: u32,
    #[bits(2)]
    pub _op_14: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct WHILELS_SME_Pdx2_Rn_Rm {
    #[bits(1)]
    pub _op_0: u32,
    #[bits(3)]
    pub sme_pdx2: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct WHILELT_SVE_Pd_Rn_Rm {
    #[bits(4)]
    pub sve_pd: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct WHILELT_SVE_Pd_S_B_Rn_X_Rm_X {
    #[bits(4)]
    pub sve_pd: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct WHILELT_SME_PNd3_Rn_Rm_SME_VLxN_13 {
    #[bits(3)]
    pub sme_pnd3: u32,
    #[bits(2)]
    pub _op_3: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(3)]
    pub _op_10: u32,
    #[bits(1)]
    pub sme_vl_13: u32,
    #[bits(2)]
    pub _op_14: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct WHILELT_SME_Pdx2_Rn_Rm {
    #[bits(1)]
    pub _op_0: u32,
    #[bits(3)]
    pub sme_pdx2: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct WHILERW_SVE_Pd_Rn_Rm {
    #[bits(4)]
    pub sve_pd: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct WHILEWR_SVE_Pd_Rn_Rm {
    #[bits(4)]
    pub sve_pd: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct WRFFR_SVE_Pn {
    #[bits(5)]
    pub _op_0: u32,
    #[bits(4)]
    pub sve_pn: u32,
    #[bits(23)]
    pub _op_9: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct XAFLAG {
    #[bits(32)]
    pub _op_0: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct XAR_SVE_Zd_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub imm5: u32,
    #[bits(1)]
    pub _op_21: u32,
    #[bits(2)]
    pub sve_tszh: u32,
    #[bits(8)]
    pub _op_24: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct XAR_Vd_Vn_Vm_IMM {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub imm6_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct XPACD_Rd {
    #[bits(5)]
    pub rd: u32,
    #[bits(27)]
    pub _op_5: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct XPACI_Rd {
    #[bits(5)]
    pub rd: u32,
    #[bits(27)]
    pub _op_5: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct XTN_Vd_Vn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct XTN2_Vd_Vn {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ZERO_SME_list_of_64bit_tiles {
    #[bits(8)]
    pub sme_zero_mask: u32,
    #[bits(24)]
    pub _op_8: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ZERO_SME_ZT0_LIST {
    #[bits(32)]
    pub _op_0: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ZIP_SME_Zdnx2_SVE_Zn_SVE_Zm_16 {
    #[bits(1)]
    pub _op_0: u32,
    #[bits(4)]
    pub sme_zdn2: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ZIP_SME_Zdnx2_S_Q_SVE_Zn_S_Q_SVE_Zm_16_S_Q {
    #[bits(1)]
    pub _op_0: u32,
    #[bits(4)]
    pub sme_zdn2: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ZIP_SME_Zdnx4_SME_Znx4 {
    #[bits(2)]
    pub _op_0: u32,
    #[bits(3)]
    pub sme_zdn4: u32,
    #[bits(2)]
    pub _op_5: u32,
    #[bits(3)]
    pub sme_zn4: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ZIP_SME_Zdnx4_S_Q_SME_Znx4_S_Q {
    #[bits(2)]
    pub _op_0: u32,
    #[bits(3)]
    pub sme_zdn4: u32,
    #[bits(2)]
    pub _op_5: u32,
    #[bits(3)]
    pub sme_zn4: u32,
    #[bits(22)]
    pub _op_10: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ZIP1_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ZIP1_SVE_Pd_SVE_Pn_SVE_Pm {
    #[bits(4)]
    pub sve_pd: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(4)]
    pub sve_pn: u32,
    #[bits(7)]
    pub _op_9: u32,
    #[bits(4)]
    pub sve_pm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ZIP1_SVE_Zd_S_B_SVE_Zn_S_B_SVE_Zm_16_S_B {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ZIP1_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ZIP2_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ZIP2_SVE_Pd_SVE_Pn_SVE_Pm {
    #[bits(4)]
    pub sve_pd: u32,
    #[bits(1)]
    pub _op_4: u32,
    #[bits(4)]
    pub sve_pn: u32,
    #[bits(7)]
    pub _op_9: u32,
    #[bits(4)]
    pub sve_pm: u32,
    #[bits(12)]
    pub _op_20: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ZIP2_SVE_Zd_S_B_SVE_Zn_S_B_SVE_Zm_16_S_B {
    #[bits(5)]
    pub sve_zd: u32,
    #[bits(5)]
    pub sve_zn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub sve_zm_16: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[bitfield(u32)]
#[derive(PartialEq, Eq)]
pub struct ZIP2_Vd_Vn_Vm {
    #[bits(5)]
    pub rd: u32,
    #[bits(5)]
    pub rn: u32,
    #[bits(6)]
    pub _op_10: u32,
    #[bits(5)]
    pub rm: u32,
    #[bits(11)]
    pub _op_21: u32,
}
#[derive(Debug, PartialEq, Eq, Copy, Clone)]
pub enum SME_SIZE_22_HSD {
    FCLAMP_SME_Zdnx2_SVE_Zn_SVE_Zm_16(FCLAMP_SME_Zdnx2_SVE_Zn_SVE_Zm_16),
    FCLAMP_SME_Zdnx4_SVE_Zn_SVE_Zm_16(FCLAMP_SME_Zdnx4_SVE_Zn_SVE_Zm_16),
    FCLAMP_SVE_Zd_SVE_Zn_SVE_Zm_16(FCLAMP_SVE_Zd_SVE_Zn_SVE_Zm_16),
    FMAXNM_SME_Zdnx2_SME_Zdnx2_SME_Zm(FMAXNM_SME_Zdnx2_SME_Zdnx2_SME_Zm),
    FMAXNM_SME_Zdnx2_SME_Zdnx2_SME_Zmx2(FMAXNM_SME_Zdnx2_SME_Zdnx2_SME_Zmx2),
    FMAXNM_SME_Zdnx4_SME_Zdnx4_SME_Zm(FMAXNM_SME_Zdnx4_SME_Zdnx4_SME_Zm),
    FMAXNM_SME_Zdnx4_SME_Zdnx4_SME_Zmx4(FMAXNM_SME_Zdnx4_SME_Zdnx4_SME_Zmx4),
    FMAX_SME_Zdnx2_SME_Zdnx2_SME_Zm(FMAX_SME_Zdnx2_SME_Zdnx2_SME_Zm),
    FMAX_SME_Zdnx2_SME_Zdnx2_SME_Zmx2(FMAX_SME_Zdnx2_SME_Zdnx2_SME_Zmx2),
    FMAX_SME_Zdnx4_SME_Zdnx4_SME_Zm(FMAX_SME_Zdnx4_SME_Zdnx4_SME_Zm),
    FMAX_SME_Zdnx4_SME_Zdnx4_SME_Zmx4(FMAX_SME_Zdnx4_SME_Zdnx4_SME_Zmx4),
    FMINNM_SME_Zdnx2_SME_Zdnx2_SME_Zm(FMINNM_SME_Zdnx2_SME_Zdnx2_SME_Zm),
    FMINNM_SME_Zdnx2_SME_Zdnx2_SME_Zmx2(FMINNM_SME_Zdnx2_SME_Zdnx2_SME_Zmx2),
    FMINNM_SME_Zdnx4_SME_Zdnx4_SME_Zm(FMINNM_SME_Zdnx4_SME_Zdnx4_SME_Zm),
    FMINNM_SME_Zdnx4_SME_Zdnx4_SME_Zmx4(FMINNM_SME_Zdnx4_SME_Zdnx4_SME_Zmx4),
    FMIN_SME_Zdnx2_SME_Zdnx2_SME_Zm(FMIN_SME_Zdnx2_SME_Zdnx2_SME_Zm),
    FMIN_SME_Zdnx2_SME_Zdnx2_SME_Zmx2(FMIN_SME_Zdnx2_SME_Zdnx2_SME_Zmx2),
    FMIN_SME_Zdnx4_SME_Zdnx4_SME_Zm(FMIN_SME_Zdnx4_SME_Zdnx4_SME_Zm),
    FMIN_SME_Zdnx4_SME_Zdnx4_SME_Zmx4(FMIN_SME_Zdnx4_SME_Zdnx4_SME_Zmx4),
    SUNPK_SME_Zdnx2_SVE_Zn(SUNPK_SME_Zdnx2_SVE_Zn),
    SUNPK_SME_Zdnx4_SME_Znx2(SUNPK_SME_Zdnx4_SME_Znx2),
    UUNPK_SME_Zdnx2_SVE_Zn(UUNPK_SME_Zdnx2_SVE_Zn),
    UUNPK_SME_Zdnx4_SME_Znx2(UUNPK_SME_Zdnx4_SME_Znx2),
}
#[derive(Debug, PartialEq, Eq, Copy, Clone)]
pub enum DP_3SRC {
    MADD_Rd_Rn_Rm_Ra(MADD_Rd_Rn_Rm_Ra),
    MSUB_Rd_Rn_Rm_Ra(MSUB_Rd_Rn_Rm_Ra),
    SMADDL_Rd_Rn_Rm_Ra(SMADDL_Rd_Rn_Rm_Ra),
    SMSUBL_Rd_Rn_Rm_Ra(SMSUBL_Rd_Rn_Rm_Ra),
    SMULH_Rd_Rn_Rm(SMULH_Rd_Rn_Rm),
    UMADDL_Rd_Rn_Rm_Ra(UMADDL_Rd_Rn_Rm_Ra),
    UMSUBL_Rd_Rn_Rm_Ra(UMSUBL_Rd_Rn_Rm_Ra),
    UMULH_Rd_Rn_Rm(UMULH_Rd_Rn_Rm),
}
#[derive(Debug, PartialEq, Eq, Copy, Clone)]
pub enum SME_START {
    SMSTART(SMSTART),
    SMSTART_SME_SM_ZA(SMSTART_SME_SM_ZA),
}
#[derive(Debug, PartialEq, Eq, Copy, Clone)]
pub enum ASIMDIMM {
    BIC_Vd_SIMD_IMM_SFT(BIC_Vd_SIMD_IMM_SFT),
    BIC_Vd_V_4H_SIMD_IMM_SFT_LSL(BIC_Vd_V_4H_SIMD_IMM_SFT_LSL),
    FMOV_Vd_SIMD_FPIMM(FMOV_Vd_SIMD_FPIMM),
    FMOV_Vd_V_2D_SIMD_FPIMM(FMOV_Vd_V_2D_SIMD_FPIMM),
    FMOV_Vd_V_4H_SIMD_FPIMM(FMOV_Vd_V_4H_SIMD_FPIMM),
    MOVI_Sd_SIMD_IMM(MOVI_Sd_SIMD_IMM),
    MOVI_Vd_SIMD_IMM(MOVI_Vd_SIMD_IMM),
    MOVI_Vd_SIMD_IMM_SFT(MOVI_Vd_SIMD_IMM_SFT),
    MOVI_Vd_V_2S_SIMD_IMM_SFT_MSL(MOVI_Vd_V_2S_SIMD_IMM_SFT_MSL),
    MOVI_Vd_V_4H_SIMD_IMM_SFT_LSL(MOVI_Vd_V_4H_SIMD_IMM_SFT_LSL),
    MOVI_Vd_V_8B_SIMD_IMM_SFT_LSL(MOVI_Vd_V_8B_SIMD_IMM_SFT_LSL),
    MVNI_Vd_SIMD_IMM_SFT(MVNI_Vd_SIMD_IMM_SFT),
    MVNI_Vd_V_2S_SIMD_IMM_SFT_MSL(MVNI_Vd_V_2S_SIMD_IMM_SFT_MSL),
    MVNI_Vd_V_4H_SIMD_IMM_SFT_LSL(MVNI_Vd_V_4H_SIMD_IMM_SFT_LSL),
    ORR_Vd_SIMD_IMM_SFT(ORR_Vd_SIMD_IMM_SFT),
    ORR_Vd_V_4H_SIMD_IMM_SFT_LSL(ORR_Vd_V_4H_SIMD_IMM_SFT_LSL),
}
#[derive(Debug, PartialEq, Eq, Copy, Clone)]
pub enum ASIMDTBL {
    TBL_Vd_LVn_Vm(TBL_Vd_LVn_Vm),
    TBX_Vd_LVn_Vm(TBX_Vd_LVn_Vm),
}
#[derive(Debug, PartialEq, Eq, Copy, Clone)]
pub enum SVE_LIMM {
    AND_SVE_Zd_SVE_Zd_SVE_LIMM(AND_SVE_Zd_SVE_Zd_SVE_LIMM),
    DUPM_SVE_Zd_SVE_LIMM(DUPM_SVE_Zd_SVE_LIMM),
    EOR_SVE_Zd_SVE_Zd_SVE_LIMM(EOR_SVE_Zd_SVE_Zd_SVE_LIMM),
    ORR_SVE_Zd_SVE_Zd_SVE_LIMM(ORR_SVE_Zd_SVE_Zd_SVE_LIMM),
}
#[derive(Debug, PartialEq, Eq, Copy, Clone)]
pub enum LDST_POS {
    LDRB_Rt_ADDR_UIMM12(LDRB_Rt_ADDR_UIMM12),
    LDRH_Rt_ADDR_UIMM12(LDRH_Rt_ADDR_UIMM12),
    LDRSB_Rt_ADDR_UIMM12(LDRSB_Rt_ADDR_UIMM12),
    LDRSH_Rt_ADDR_UIMM12(LDRSH_Rt_ADDR_UIMM12),
    LDRSW_Rt_ADDR_UIMM12(LDRSW_Rt_ADDR_UIMM12),
    LDR_Ft_ADDR_UIMM12(LDR_Ft_ADDR_UIMM12),
    LDR_Rt_ADDR_UIMM12(LDR_Rt_ADDR_UIMM12),
    PRFM_PRFOP_ADDR_UIMM12(PRFM_PRFOP_ADDR_UIMM12),
    STRB_Rt_ADDR_UIMM12(STRB_Rt_ADDR_UIMM12),
    STRH_Rt_ADDR_UIMM12(STRH_Rt_ADDR_UIMM12),
    STR_Ft_ADDR_UIMM12(STR_Ft_ADDR_UIMM12),
    STR_Rt_ADDR_UIMM12(STR_Rt_ADDR_UIMM12),
}
#[derive(Debug, PartialEq, Eq, Copy, Clone)]
pub enum ADDSUB_SHIFT {
    ADDS_Rd_Rn_Rm_SFT(ADDS_Rd_Rn_Rm_SFT),
    ADD_Rd_Rn_Rm_SFT(ADD_Rd_Rn_Rm_SFT),
    SUBS_Rd_Rn_Rm_SFT(SUBS_Rd_Rn_Rm_SFT),
    SUB_Rd_Rn_Rm_SFT(SUB_Rd_Rn_Rm_SFT),
}
#[derive(Debug, PartialEq, Eq, Copy, Clone)]
pub enum ASIMDSAME {
    ADDP_Vd_Vn_Vm(ADDP_Vd_Vn_Vm),
    ADD_Vd_Vn_Vm(ADD_Vd_Vn_Vm),
    AND_Vd_Vn_Vm(AND_Vd_Vn_Vm),
    BIC_Vd_Vn_Vm(BIC_Vd_Vn_Vm),
    BIF_Vd_Vn_Vm(BIF_Vd_Vn_Vm),
    BIT_Vd_Vn_Vm(BIT_Vd_Vn_Vm),
    BSL_Vd_Vn_Vm(BSL_Vd_Vn_Vm),
    CMEQ_Vd_Vn_Vm(CMEQ_Vd_Vn_Vm),
    CMGE_Vd_Vn_Vm(CMGE_Vd_Vn_Vm),
    CMGT_Vd_Vn_Vm(CMGT_Vd_Vn_Vm),
    CMHI_Vd_Vn_Vm(CMHI_Vd_Vn_Vm),
    CMHS_Vd_Vn_Vm(CMHS_Vd_Vn_Vm),
    CMTST_Vd_Vn_Vm(CMTST_Vd_Vn_Vm),
    EOR_Vd_Vn_Vm(EOR_Vd_Vn_Vm),
    FABD_Vd_V_2S_Vn_V_2S_Vm_V_2S(FABD_Vd_V_2S_Vn_V_2S_Vm_V_2S),
    FABD_Vd_Vn_Vm(FABD_Vd_Vn_Vm),
    FACGE_Vd_V_2S_Vn_V_2S_Vm_V_2S(FACGE_Vd_V_2S_Vn_V_2S_Vm_V_2S),
    FACGE_Vd_Vn_Vm(FACGE_Vd_Vn_Vm),
    FACGT_Vd_V_2S_Vn_V_2S_Vm_V_2S(FACGT_Vd_V_2S_Vn_V_2S_Vm_V_2S),
    FACGT_Vd_Vn_Vm(FACGT_Vd_Vn_Vm),
    FADDP_Vd_V_2S_Vn_V_2S_Vm_V_2S(FADDP_Vd_V_2S_Vn_V_2S_Vm_V_2S),
    FADDP_Vd_Vn_Vm(FADDP_Vd_Vn_Vm),
    FADD_Vd_V_2S_Vn_V_2S_Vm_V_2S(FADD_Vd_V_2S_Vn_V_2S_Vm_V_2S),
    FADD_Vd_Vn_Vm(FADD_Vd_Vn_Vm),
    FCADD_Vd_Vn_Vm_IMM_ROT3(FCADD_Vd_Vn_Vm_IMM_ROT3),
    FCMEQ_Vd_V_2S_Vn_V_2S_Vm_V_2S(FCMEQ_Vd_V_2S_Vn_V_2S_Vm_V_2S),
    FCMEQ_Vd_Vn_Vm(FCMEQ_Vd_Vn_Vm),
    FCMGE_Vd_V_2S_Vn_V_2S_Vm_V_2S(FCMGE_Vd_V_2S_Vn_V_2S_Vm_V_2S),
    FCMGE_Vd_Vn_Vm(FCMGE_Vd_Vn_Vm),
    FCMGT_Vd_V_2S_Vn_V_2S_Vm_V_2S(FCMGT_Vd_V_2S_Vn_V_2S_Vm_V_2S),
    FCMGT_Vd_Vn_Vm(FCMGT_Vd_Vn_Vm),
    FCMLA_Vd_Vn_Vm_IMM_ROT1(FCMLA_Vd_Vn_Vm_IMM_ROT1),
    FDIV_Vd_V_2S_Vn_V_2S_Vm_V_2S(FDIV_Vd_V_2S_Vn_V_2S_Vm_V_2S),
    FDIV_Vd_Vn_Vm(FDIV_Vd_Vn_Vm),
    FMAXNMP_Vd_V_2S_Vn_V_2S_Vm_V_2S(FMAXNMP_Vd_V_2S_Vn_V_2S_Vm_V_2S),
    FMAXNMP_Vd_Vn_Vm(FMAXNMP_Vd_Vn_Vm),
    FMAXNM_Vd_V_2S_Vn_V_2S_Vm_V_2S(FMAXNM_Vd_V_2S_Vn_V_2S_Vm_V_2S),
    FMAXNM_Vd_Vn_Vm(FMAXNM_Vd_Vn_Vm),
    FMAXP_Vd_V_2S_Vn_V_2S_Vm_V_2S(FMAXP_Vd_V_2S_Vn_V_2S_Vm_V_2S),
    FMAXP_Vd_Vn_Vm(FMAXP_Vd_Vn_Vm),
    FMAX_Vd_V_2S_Vn_V_2S_Vm_V_2S(FMAX_Vd_V_2S_Vn_V_2S_Vm_V_2S),
    FMAX_Vd_Vn_Vm(FMAX_Vd_Vn_Vm),
    FMINNMP_Vd_V_2S_Vn_V_2S_Vm_V_2S(FMINNMP_Vd_V_2S_Vn_V_2S_Vm_V_2S),
    FMINNMP_Vd_Vn_Vm(FMINNMP_Vd_Vn_Vm),
    FMINNM_Vd_V_2S_Vn_V_2S_Vm_V_2S(FMINNM_Vd_V_2S_Vn_V_2S_Vm_V_2S),
    FMINNM_Vd_Vn_Vm(FMINNM_Vd_Vn_Vm),
    FMINP_Vd_V_2S_Vn_V_2S_Vm_V_2S(FMINP_Vd_V_2S_Vn_V_2S_Vm_V_2S),
    FMINP_Vd_Vn_Vm(FMINP_Vd_Vn_Vm),
    FMIN_Vd_V_2S_Vn_V_2S_Vm_V_2S(FMIN_Vd_V_2S_Vn_V_2S_Vm_V_2S),
    FMIN_Vd_Vn_Vm(FMIN_Vd_Vn_Vm),
    FMLAL2_Vd_V_4S_Vn_V_4H_Vm_V_4H(FMLAL2_Vd_V_4S_Vn_V_4H_Vm_V_4H),
    FMLAL2_Vd_Vn_Vm(FMLAL2_Vd_Vn_Vm),
    FMLAL_Vd_V_4S_Vn_V_4H_Vm_V_4H(FMLAL_Vd_V_4S_Vn_V_4H_Vm_V_4H),
    FMLAL_Vd_Vn_Vm(FMLAL_Vd_Vn_Vm),
    FMLA_Vd_V_2S_Vn_V_2S_Vm_V_2S(FMLA_Vd_V_2S_Vn_V_2S_Vm_V_2S),
    FMLA_Vd_Vn_Vm(FMLA_Vd_Vn_Vm),
    FMLSL2_Vd_V_4S_Vn_V_4H_Vm_V_4H(FMLSL2_Vd_V_4S_Vn_V_4H_Vm_V_4H),
    FMLSL2_Vd_Vn_Vm(FMLSL2_Vd_Vn_Vm),
    FMLSL_Vd_V_4S_Vn_V_4H_Vm_V_4H(FMLSL_Vd_V_4S_Vn_V_4H_Vm_V_4H),
    FMLSL_Vd_Vn_Vm(FMLSL_Vd_Vn_Vm),
    FMLS_Vd_V_2S_Vn_V_2S_Vm_V_2S(FMLS_Vd_V_2S_Vn_V_2S_Vm_V_2S),
    FMLS_Vd_Vn_Vm(FMLS_Vd_Vn_Vm),
    FMULX_Vd_V_2S_Vn_V_2S_Vm_V_2S(FMULX_Vd_V_2S_Vn_V_2S_Vm_V_2S),
    FMULX_Vd_Vn_Vm(FMULX_Vd_Vn_Vm),
    FMUL_Vd_V_2S_Vn_V_2S_Vm_V_2S(FMUL_Vd_V_2S_Vn_V_2S_Vm_V_2S),
    FMUL_Vd_Vn_Vm(FMUL_Vd_Vn_Vm),
    FRECPS_Vd_V_2S_Vn_V_2S_Vm_V_2S(FRECPS_Vd_V_2S_Vn_V_2S_Vm_V_2S),
    FRECPS_Vd_Vn_Vm(FRECPS_Vd_Vn_Vm),
    FRSQRTS_Vd_V_2S_Vn_V_2S_Vm_V_2S(FRSQRTS_Vd_V_2S_Vn_V_2S_Vm_V_2S),
    FRSQRTS_Vd_Vn_Vm(FRSQRTS_Vd_Vn_Vm),
    FSUB_Vd_V_2S_Vn_V_2S_Vm_V_2S(FSUB_Vd_V_2S_Vn_V_2S_Vm_V_2S),
    FSUB_Vd_Vn_Vm(FSUB_Vd_Vn_Vm),
    MLA_Vd_Vn_Vm(MLA_Vd_Vn_Vm),
    MLS_Vd_Vn_Vm(MLS_Vd_Vn_Vm),
    MUL_Vd_Vn_Vm(MUL_Vd_Vn_Vm),
    ORN_Vd_Vn_Vm(ORN_Vd_Vn_Vm),
    ORR_Vd_Vn_Vm(ORR_Vd_Vn_Vm),
    PMUL_Vd_Vn_Vm(PMUL_Vd_Vn_Vm),
    SABA_Vd_Vn_Vm(SABA_Vd_Vn_Vm),
    SABD_Vd_Vn_Vm(SABD_Vd_Vn_Vm),
    SHADD_Vd_Vn_Vm(SHADD_Vd_Vn_Vm),
    SHSUB_Vd_Vn_Vm(SHSUB_Vd_Vn_Vm),
    SMAXP_Vd_Vn_Vm(SMAXP_Vd_Vn_Vm),
    SMAX_Vd_Vn_Vm(SMAX_Vd_Vn_Vm),
    SMINP_Vd_Vn_Vm(SMINP_Vd_Vn_Vm),
    SMIN_Vd_Vn_Vm(SMIN_Vd_Vn_Vm),
    SQADD_Vd_Vn_Vm(SQADD_Vd_Vn_Vm),
    SQDMULH_Vd_Vn_Vm(SQDMULH_Vd_Vn_Vm),
    SQRDMLAH_Sd_Sn_Sm(SQRDMLAH_Sd_Sn_Sm),
    SQRDMLAH_Vd_Vn_Vm(SQRDMLAH_Vd_Vn_Vm),
    SQRDMLSH_Sd_Sn_Sm(SQRDMLSH_Sd_Sn_Sm),
    SQRDMLSH_Vd_Vn_Vm(SQRDMLSH_Vd_Vn_Vm),
    SQRDMULH_Vd_Vn_Vm(SQRDMULH_Vd_Vn_Vm),
    SQRSHL_Vd_Vn_Vm(SQRSHL_Vd_Vn_Vm),
    SQSHL_Vd_Vn_Vm(SQSHL_Vd_Vn_Vm),
    SQSUB_Vd_Vn_Vm(SQSUB_Vd_Vn_Vm),
    SRHADD_Vd_Vn_Vm(SRHADD_Vd_Vn_Vm),
    SRSHL_Vd_Vn_Vm(SRSHL_Vd_Vn_Vm),
    SSHL_Vd_Vn_Vm(SSHL_Vd_Vn_Vm),
    SUB_Vd_Vn_Vm(SUB_Vd_Vn_Vm),
    UABA_Vd_Vn_Vm(UABA_Vd_Vn_Vm),
    UABD_Vd_Vn_Vm(UABD_Vd_Vn_Vm),
    UHADD_Vd_Vn_Vm(UHADD_Vd_Vn_Vm),
    UHSUB_Vd_Vn_Vm(UHSUB_Vd_Vn_Vm),
    UMAXP_Vd_Vn_Vm(UMAXP_Vd_Vn_Vm),
    UMAX_Vd_Vn_Vm(UMAX_Vd_Vn_Vm),
    UMINP_Vd_Vn_Vm(UMINP_Vd_Vn_Vm),
    UMIN_Vd_Vn_Vm(UMIN_Vd_Vn_Vm),
    UQADD_Vd_Vn_Vm(UQADD_Vd_Vn_Vm),
    UQRSHL_Vd_Vn_Vm(UQRSHL_Vd_Vn_Vm),
    UQSHL_Vd_Vn_Vm(UQSHL_Vd_Vn_Vm),
    UQSUB_Vd_Vn_Vm(UQSUB_Vd_Vn_Vm),
    URHADD_Vd_Vn_Vm(URHADD_Vd_Vn_Vm),
    URSHL_Vd_Vn_Vm(URSHL_Vd_Vn_Vm),
    USHL_Vd_Vn_Vm(USHL_Vd_Vn_Vm),
}
#[derive(Debug, PartialEq, Eq, Copy, Clone)]
pub enum SVE_SIZE_BHS {
    ASR_SVE_Zd_SVE_Zn_SVE_Zm_16(ASR_SVE_Zd_SVE_Zn_SVE_Zm_16),
    ASR_SVE_Zd_S_B_SVE_Pg3_P_M_SVE_Zd_S_B_SVE_Zm_5_S_D(
        ASR_SVE_Zd_S_B_SVE_Pg3_P_M_SVE_Zd_S_B_SVE_Zm_5_S_D,
    ),
    CMPEQ_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16(CMPEQ_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16),
    CMPGE_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16(CMPGE_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16),
    CMPGT_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16(CMPGT_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16),
    CMPHI_SVE_Pd_S_B_SVE_Pg3_P_Z_SVE_Zn_S_B_SVE_Zm_16_S_D(
        CMPHI_SVE_Pd_S_B_SVE_Pg3_P_Z_SVE_Zn_S_B_SVE_Zm_16_S_D,
    ),
    CMPHS_SVE_Pd_S_B_SVE_Pg3_P_Z_SVE_Zn_S_B_SVE_Zm_16_S_D(
        CMPHS_SVE_Pd_S_B_SVE_Pg3_P_Z_SVE_Zn_S_B_SVE_Zm_16_S_D,
    ),
    CMPLE_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16(CMPLE_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16),
    CMPLO_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16(CMPLO_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16),
    CMPLS_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16(CMPLS_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16),
    CMPLT_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16(CMPLT_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16),
    CMPNE_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16(CMPNE_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16),
    LSL_SVE_Zd_SVE_Zn_SVE_Zm_16(LSL_SVE_Zd_SVE_Zn_SVE_Zm_16),
    LSL_SVE_Zd_S_B_SVE_Pg3_P_M_SVE_Zd_S_B_SVE_Zm_5_S_D(
        LSL_SVE_Zd_S_B_SVE_Pg3_P_M_SVE_Zd_S_B_SVE_Zm_5_S_D,
    ),
    LSR_SVE_Zd_SVE_Zn_SVE_Zm_16(LSR_SVE_Zd_SVE_Zn_SVE_Zm_16),
    LSR_SVE_Zd_S_B_SVE_Pg3_P_M_SVE_Zd_S_B_SVE_Zm_5_S_D(
        LSR_SVE_Zd_S_B_SVE_Pg3_P_M_SVE_Zd_S_B_SVE_Zm_5_S_D,
    ),
    SADDV_SVE_Vd_SVE_Pg3_SVE_Zn(SADDV_SVE_Vd_SVE_Pg3_SVE_Zn),
}
#[derive(Debug, PartialEq, Eq, Copy, Clone)]
pub enum FLOAT2INT {
    FCVTAS_Rd_Fn(FCVTAS_Rd_Fn),
    FCVTAS_Rd_W_Fn_S_D(FCVTAS_Rd_W_Fn_S_D),
    FCVTAU_Rd_Fn(FCVTAU_Rd_Fn),
    FCVTAU_Rd_W_Fn_S_D(FCVTAU_Rd_W_Fn_S_D),
    FCVTMS_Rd_Fn(FCVTMS_Rd_Fn),
    FCVTMS_Rd_W_Fn_S_D(FCVTMS_Rd_W_Fn_S_D),
    FCVTMU_Rd_Fn(FCVTMU_Rd_Fn),
    FCVTMU_Rd_W_Fn_S_D(FCVTMU_Rd_W_Fn_S_D),
    FCVTNS_Rd_Fn(FCVTNS_Rd_Fn),
    FCVTNS_Rd_W_Fn_S_D(FCVTNS_Rd_W_Fn_S_D),
    FCVTNU_Rd_Fn(FCVTNU_Rd_Fn),
    FCVTNU_Rd_W_Fn_S_D(FCVTNU_Rd_W_Fn_S_D),
    FCVTPS_Rd_Fn(FCVTPS_Rd_Fn),
    FCVTPS_Rd_W_Fn_S_D(FCVTPS_Rd_W_Fn_S_D),
    FCVTPU_Rd_Fn(FCVTPU_Rd_Fn),
    FCVTPU_Rd_W_Fn_S_D(FCVTPU_Rd_W_Fn_S_D),
    FCVTZS_Rd_Fn(FCVTZS_Rd_Fn),
    FCVTZS_Rd_W_Fn_S_D(FCVTZS_Rd_W_Fn_S_D),
    FCVTZU_Rd_Fn(FCVTZU_Rd_Fn),
    FCVTZU_Rd_W_Fn_S_D(FCVTZU_Rd_W_Fn_S_D),
    FJCVTZS_Rd_Fn(FJCVTZS_Rd_Fn),
    FMOV_Fd_Rn(FMOV_Fd_Rn),
    FMOV_Fd_S_S_Rn_W(FMOV_Fd_S_S_Rn_W),
    FMOV_Rd_Fn(FMOV_Rd_Fn),
    FMOV_Rd_VnD1(FMOV_Rd_VnD1),
    FMOV_Rd_W_Fn_S_S(FMOV_Rd_W_Fn_S_S),
    FMOV_VdD1_Rn(FMOV_VdD1_Rn),
    SCVTF_Fd_Rn(SCVTF_Fd_Rn),
    SCVTF_Fd_S_D_Rn_W(SCVTF_Fd_S_D_Rn_W),
    UCVTF_Fd_Rn(UCVTF_Fd_Rn),
    UCVTF_Fd_S_D_Rn_W(UCVTF_Fd_S_D_Rn_W),
}
#[derive(Debug, PartialEq, Eq, Copy, Clone)]
pub enum LDST_UNSCALED {
    LDAPURB_Rt_ADDR_OFFSET(LDAPURB_Rt_ADDR_OFFSET),
    LDAPURH_Rt_ADDR_OFFSET(LDAPURH_Rt_ADDR_OFFSET),
    LDAPURSB_Rt_ADDR_OFFSET(LDAPURSB_Rt_ADDR_OFFSET),
    LDAPURSB_Rt_W_ADDR_OFFSET(LDAPURSB_Rt_W_ADDR_OFFSET),
    LDAPURSH_Rt_ADDR_OFFSET(LDAPURSH_Rt_ADDR_OFFSET),
    LDAPURSH_Rt_W_ADDR_OFFSET(LDAPURSH_Rt_W_ADDR_OFFSET),
    LDAPURSW_Rt_ADDR_OFFSET(LDAPURSW_Rt_ADDR_OFFSET),
    LDAPUR_Rt_ADDR_OFFSET(LDAPUR_Rt_ADDR_OFFSET),
    LDAPUR_Rt_X_ADDR_OFFSET(LDAPUR_Rt_X_ADDR_OFFSET),
    LDG_Rt_ADDR_SIMM13(LDG_Rt_ADDR_SIMM13),
    LDURB_Rt_ADDR_SIMM9(LDURB_Rt_ADDR_SIMM9),
    LDURH_Rt_ADDR_SIMM9(LDURH_Rt_ADDR_SIMM9),
    LDURSB_Rt_ADDR_SIMM9(LDURSB_Rt_ADDR_SIMM9),
    LDURSH_Rt_ADDR_SIMM9(LDURSH_Rt_ADDR_SIMM9),
    LDURSW_Rt_ADDR_SIMM9(LDURSW_Rt_ADDR_SIMM9),
    LDUR_Ft_ADDR_SIMM9(LDUR_Ft_ADDR_SIMM9),
    LDUR_Rt_ADDR_SIMM9(LDUR_Rt_ADDR_SIMM9),
    PRFUM_PRFOP_ADDR_SIMM9(PRFUM_PRFOP_ADDR_SIMM9),
    ST2G_Rt_SP_ADDR_SIMM13(ST2G_Rt_SP_ADDR_SIMM13),
    STG_Rt_SP_ADDR_SIMM13(STG_Rt_SP_ADDR_SIMM13),
    STLURB_Rt_ADDR_OFFSET(STLURB_Rt_ADDR_OFFSET),
    STLURH_Rt_ADDR_OFFSET(STLURH_Rt_ADDR_OFFSET),
    STLUR_Rt_ADDR_OFFSET(STLUR_Rt_ADDR_OFFSET),
    STLUR_Rt_X_ADDR_OFFSET(STLUR_Rt_X_ADDR_OFFSET),
    STURB_Rt_ADDR_SIMM9(STURB_Rt_ADDR_SIMM9),
    STURH_Rt_ADDR_SIMM9(STURH_Rt_ADDR_SIMM9),
    STUR_Ft_ADDR_SIMM9(STUR_Ft_ADDR_SIMM9),
    STUR_Rt_ADDR_SIMM9(STUR_Rt_ADDR_SIMM9),
    STZ2G_Rt_SP_ADDR_SIMM13(STZ2G_Rt_SP_ADDR_SIMM13),
    STZG_Rt_SP_ADDR_SIMM13(STZG_Rt_SP_ADDR_SIMM13),
}
#[derive(Debug, PartialEq, Eq, Copy, Clone)]
pub enum ASISDSAME {
    ADD_Sd_Sn_Sm(ADD_Sd_Sn_Sm),
    CMEQ_Sd_Sn_Sm(CMEQ_Sd_Sn_Sm),
    CMGE_Sd_Sn_Sm(CMGE_Sd_Sn_Sm),
    CMGT_Sd_Sn_Sm(CMGT_Sd_Sn_Sm),
    CMHI_Sd_Sn_Sm(CMHI_Sd_Sn_Sm),
    CMHS_Sd_Sn_Sm(CMHS_Sd_Sn_Sm),
    CMTST_Sd_Sn_Sm(CMTST_Sd_Sn_Sm),
    FABD_Sd_S_S_Sn_S_S_Sm_S_S(FABD_Sd_S_S_Sn_S_S_Sm_S_S),
    FABD_Sd_Sn_Sm(FABD_Sd_Sn_Sm),
    FACGE_Sd_S_S_Sn_S_S_Sm_S_S(FACGE_Sd_S_S_Sn_S_S_Sm_S_S),
    FACGE_Sd_Sn_Sm(FACGE_Sd_Sn_Sm),
    FACGT_Sd_S_S_Sn_S_S_Sm_S_S(FACGT_Sd_S_S_Sn_S_S_Sm_S_S),
    FACGT_Sd_Sn_Sm(FACGT_Sd_Sn_Sm),
    FCMEQ_Sd_S_S_Sn_S_S_Sm_S_S(FCMEQ_Sd_S_S_Sn_S_S_Sm_S_S),
    FCMEQ_Sd_Sn_Sm(FCMEQ_Sd_Sn_Sm),
    FCMGE_Sd_S_S_Sn_S_S_Sm_S_S(FCMGE_Sd_S_S_Sn_S_S_Sm_S_S),
    FCMGE_Sd_Sn_Sm(FCMGE_Sd_Sn_Sm),
    FCMGT_Sd_S_S_Sn_S_S_Sm_S_S(FCMGT_Sd_S_S_Sn_S_S_Sm_S_S),
    FCMGT_Sd_Sn_Sm(FCMGT_Sd_Sn_Sm),
    FMULX_Sd_S_S_Sn_S_S_Sm_S_S(FMULX_Sd_S_S_Sn_S_S_Sm_S_S),
    FMULX_Sd_Sn_Sm(FMULX_Sd_Sn_Sm),
    FRECPS_Sd_S_S_Sn_S_S_Sm_S_S(FRECPS_Sd_S_S_Sn_S_S_Sm_S_S),
    FRECPS_Sd_Sn_Sm(FRECPS_Sd_Sn_Sm),
    FRSQRTS_Sd_S_S_Sn_S_S_Sm_S_S(FRSQRTS_Sd_S_S_Sn_S_S_Sm_S_S),
    FRSQRTS_Sd_Sn_Sm(FRSQRTS_Sd_Sn_Sm),
    SQADD_Sd_Sn_Sm(SQADD_Sd_Sn_Sm),
    SQDMULH_Sd_Sn_Sm(SQDMULH_Sd_Sn_Sm),
    SQRDMULH_Sd_Sn_Sm(SQRDMULH_Sd_Sn_Sm),
    SQRSHL_Sd_Sn_Sm(SQRSHL_Sd_Sn_Sm),
    SQSHL_Sd_Sn_Sm(SQSHL_Sd_Sn_Sm),
    SQSUB_Sd_Sn_Sm(SQSUB_Sd_Sn_Sm),
    SRSHL_Sd_Sn_Sm(SRSHL_Sd_Sn_Sm),
    SSHL_Sd_Sn_Sm(SSHL_Sd_Sn_Sm),
    SUB_Sd_Sn_Sm(SUB_Sd_Sn_Sm),
    UQADD_Sd_Sn_Sm(UQADD_Sd_Sn_Sm),
    UQRSHL_Sd_Sn_Sm(UQRSHL_Sd_Sn_Sm),
    UQSHL_Sd_Sn_Sm(UQSHL_Sd_Sn_Sm),
    UQSUB_Sd_Sn_Sm(UQSUB_Sd_Sn_Sm),
    URSHL_Sd_Sn_Sm(URSHL_Sd_Sn_Sm),
    USHL_Sd_Sn_Sm(USHL_Sd_Sn_Sm),
}
#[derive(Debug, PartialEq, Eq, Copy, Clone)]
pub enum ASIMDDIFF {
    ADDHN2_Vd_Vn_Vm(ADDHN2_Vd_Vn_Vm),
    ADDHN_Vd_Vn_Vm(ADDHN_Vd_Vn_Vm),
    PMULL2_Vd_V_1Q_Vn_V_2D_Vm_V_2D(PMULL2_Vd_V_1Q_Vn_V_2D_Vm_V_2D),
    PMULL2_Vd_Vn_Vm(PMULL2_Vd_Vn_Vm),
    PMULL_Vd_V_1Q_Vn_V_1D_Vm_V_1D(PMULL_Vd_V_1Q_Vn_V_1D_Vm_V_1D),
    PMULL_Vd_Vn_Vm(PMULL_Vd_Vn_Vm),
    RADDHN2_Vd_Vn_Vm(RADDHN2_Vd_Vn_Vm),
    RADDHN_Vd_Vn_Vm(RADDHN_Vd_Vn_Vm),
    RSUBHN2_Vd_Vn_Vm(RSUBHN2_Vd_Vn_Vm),
    RSUBHN_Vd_Vn_Vm(RSUBHN_Vd_Vn_Vm),
    SABAL2_Vd_Vn_Vm(SABAL2_Vd_Vn_Vm),
    SABAL_Vd_Vn_Vm(SABAL_Vd_Vn_Vm),
    SABDL2_Vd_Vn_Vm(SABDL2_Vd_Vn_Vm),
    SABDL_Vd_Vn_Vm(SABDL_Vd_Vn_Vm),
    SADDL2_Vd_Vn_Vm(SADDL2_Vd_Vn_Vm),
    SADDL_Vd_Vn_Vm(SADDL_Vd_Vn_Vm),
    SADDW2_Vd_Vn_Vm(SADDW2_Vd_Vn_Vm),
    SADDW_Vd_Vn_Vm(SADDW_Vd_Vn_Vm),
    SMLAL2_Vd_Vn_Vm(SMLAL2_Vd_Vn_Vm),
    SMLAL_Vd_Vn_Vm(SMLAL_Vd_Vn_Vm),
    SMLSL2_Vd_Vn_Vm(SMLSL2_Vd_Vn_Vm),
    SMLSL_Vd_Vn_Vm(SMLSL_Vd_Vn_Vm),
    SMULL2_Vd_Vn_Vm(SMULL2_Vd_Vn_Vm),
    SMULL_Vd_Vn_Vm(SMULL_Vd_Vn_Vm),
    SQDMLAL2_Vd_Vn_Vm(SQDMLAL2_Vd_Vn_Vm),
    SQDMLAL_Vd_Vn_Vm(SQDMLAL_Vd_Vn_Vm),
    SQDMLSL2_Vd_Vn_Vm(SQDMLSL2_Vd_Vn_Vm),
    SQDMLSL_Vd_Vn_Vm(SQDMLSL_Vd_Vn_Vm),
    SQDMULL2_Vd_Vn_Vm(SQDMULL2_Vd_Vn_Vm),
    SQDMULL_Vd_Vn_Vm(SQDMULL_Vd_Vn_Vm),
    SSUBL2_Vd_Vn_Vm(SSUBL2_Vd_Vn_Vm),
    SSUBL_Vd_Vn_Vm(SSUBL_Vd_Vn_Vm),
    SSUBW2_Vd_Vn_Vm(SSUBW2_Vd_Vn_Vm),
    SSUBW_Vd_Vn_Vm(SSUBW_Vd_Vn_Vm),
    SUBHN2_Vd_Vn_Vm(SUBHN2_Vd_Vn_Vm),
    SUBHN_Vd_Vn_Vm(SUBHN_Vd_Vn_Vm),
    UABAL2_Vd_Vn_Vm(UABAL2_Vd_Vn_Vm),
    UABAL_Vd_Vn_Vm(UABAL_Vd_Vn_Vm),
    UABDL2_Vd_Vn_Vm(UABDL2_Vd_Vn_Vm),
    UABDL_Vd_Vn_Vm(UABDL_Vd_Vn_Vm),
    UADDL2_Vd_Vn_Vm(UADDL2_Vd_Vn_Vm),
    UADDL_Vd_Vn_Vm(UADDL_Vd_Vn_Vm),
    UADDW2_Vd_Vn_Vm(UADDW2_Vd_Vn_Vm),
    UADDW_Vd_Vn_Vm(UADDW_Vd_Vn_Vm),
    UMLAL2_Vd_Vn_Vm(UMLAL2_Vd_Vn_Vm),
    UMLAL_Vd_Vn_Vm(UMLAL_Vd_Vn_Vm),
    UMLSL2_Vd_Vn_Vm(UMLSL2_Vd_Vn_Vm),
    UMLSL_Vd_Vn_Vm(UMLSL_Vd_Vn_Vm),
    UMULL2_Vd_Vn_Vm(UMULL2_Vd_Vn_Vm),
    UMULL_Vd_Vn_Vm(UMULL_Vd_Vn_Vm),
    USUBL2_Vd_Vn_Vm(USUBL2_Vd_Vn_Vm),
    USUBL_Vd_Vn_Vm(USUBL_Vd_Vn_Vm),
    USUBW2_Vd_Vn_Vm(USUBW2_Vd_Vn_Vm),
    USUBW_Vd_Vn_Vm(USUBW_Vd_Vn_Vm),
}
#[derive(Debug, PartialEq, Eq, Copy, Clone)]
pub enum CONDCMP_IMM {
    CCMN_Rn_CCMP_IMM_NZCV_COND(CCMN_Rn_CCMP_IMM_NZCV_COND),
    CCMP_Rn_CCMP_IMM_NZCV_COND(CCMP_Rn_CCMP_IMM_NZCV_COND),
}
#[derive(Debug, PartialEq, Eq, Copy, Clone)]
pub enum SME_FP_SD {
    FADD_SME_ZA_array_off3_0_SME_Znx2(FADD_SME_ZA_array_off3_0_SME_Znx2),
    FADD_SME_ZA_array_off3_0_SME_Znx4(FADD_SME_ZA_array_off3_0_SME_Znx4),
    FMLA_SME_ZA_array_off3_0_SME_Znx2_SME_Zmx2(FMLA_SME_ZA_array_off3_0_SME_Znx2_SME_Zmx2),
    FMLA_SME_ZA_array_off3_0_SME_Znx4_SME_Zmx4(FMLA_SME_ZA_array_off3_0_SME_Znx4_SME_Zmx4),
    FMLA_SME_ZA_array_off3_0_SVE_ZnxN_SME_Zm(FMLA_SME_ZA_array_off3_0_SVE_ZnxN_SME_Zm),
    FMLA_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_S_SME_Zm_S_S(
        FMLA_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_S_SME_Zm_S_S,
    ),
    FMLS_SME_ZA_array_off3_0_SME_Znx2_SME_Zmx2(FMLS_SME_ZA_array_off3_0_SME_Znx2_SME_Zmx2),
    FMLS_SME_ZA_array_off3_0_SME_Znx4_SME_Zmx4(FMLS_SME_ZA_array_off3_0_SME_Znx4_SME_Zmx4),
    FMLS_SME_ZA_array_off3_0_SVE_ZnxN_SME_Zm(FMLS_SME_ZA_array_off3_0_SVE_ZnxN_SME_Zm),
    FMLS_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_S_SME_Zm_S_S(
        FMLS_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_S_SME_Zm_S_S,
    ),
    FSUB_SME_ZA_array_off3_0_SME_Znx2(FSUB_SME_ZA_array_off3_0_SME_Znx2),
    FSUB_SME_ZA_array_off3_0_SME_Znx4(FSUB_SME_ZA_array_off3_0_SME_Znx4),
}
#[derive(Debug, PartialEq, Eq, Copy, Clone)]
pub enum SVE_SIZE_HSD {
    ADDHNB_SVE_Zd_SVE_Zn_SVE_Zm_16(ADDHNB_SVE_Zd_SVE_Zn_SVE_Zm_16),
    ADDHNT_SVE_Zd_SVE_Zn_SVE_Zm_16(ADDHNT_SVE_Zd_SVE_Zn_SVE_Zm_16),
    DECP_SVE_Zd_SVE_Pg4_5(DECP_SVE_Zd_SVE_Pg4_5),
    FABD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(FABD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5),
    FABS_SVE_Zd_SVE_Pg3_SVE_Zn(FABS_SVE_Zd_SVE_Pg3_SVE_Zn),
    FACGE_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16(FACGE_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16),
    FACGT_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16(FACGT_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16),
    FADDA_SVE_Vd_SVE_Pg3_SVE_Vd_SVE_Zm_5(FADDA_SVE_Vd_SVE_Pg3_SVE_Vd_SVE_Zm_5),
    FADDP_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(FADDP_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn),
    FADDV_SVE_Vd_SVE_Pg3_SVE_Zn(FADDV_SVE_Vd_SVE_Pg3_SVE_Zn),
    FADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_I1_HALF_ONE(FADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_I1_HALF_ONE),
    FADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(FADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5),
    FADD_SVE_Zd_SVE_Zn_SVE_Zm_16(FADD_SVE_Zd_SVE_Zn_SVE_Zm_16),
    FCADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5_SVE_IMM_ROT1(
        FCADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5_SVE_IMM_ROT1,
    ),
    FCMEQ_SVE_Pd_SVE_Pg3_SVE_Zn_FPIMM0(FCMEQ_SVE_Pd_SVE_Pg3_SVE_Zn_FPIMM0),
    FCMEQ_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16(FCMEQ_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16),
    FCMGE_SVE_Pd_SVE_Pg3_SVE_Zn_FPIMM0(FCMGE_SVE_Pd_SVE_Pg3_SVE_Zn_FPIMM0),
    FCMGE_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16(FCMGE_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16),
    FCMGT_SVE_Pd_SVE_Pg3_SVE_Zn_FPIMM0(FCMGT_SVE_Pd_SVE_Pg3_SVE_Zn_FPIMM0),
    FCMGT_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16(FCMGT_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16),
    FCMLA_SVE_Zd_SVE_Pg3_SVE_Zn_SVE_Zm_16_IMM_ROT2(FCMLA_SVE_Zd_SVE_Pg3_SVE_Zn_SVE_Zm_16_IMM_ROT2),
    FCMLE_SVE_Pd_SVE_Pg3_SVE_Zn_FPIMM0(FCMLE_SVE_Pd_SVE_Pg3_SVE_Zn_FPIMM0),
    FCMLT_SVE_Pd_SVE_Pg3_SVE_Zn_FPIMM0(FCMLT_SVE_Pd_SVE_Pg3_SVE_Zn_FPIMM0),
    FCMNE_SVE_Pd_SVE_Pg3_SVE_Zn_FPIMM0(FCMNE_SVE_Pd_SVE_Pg3_SVE_Zn_FPIMM0),
    FCMNE_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16(FCMNE_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16),
    FCMUO_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16(FCMUO_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16),
    FCPY_SVE_Zd_SVE_Pg4_16_SVE_FPIMM8(FCPY_SVE_Zd_SVE_Pg4_16_SVE_FPIMM8),
    FDIVR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(FDIVR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5),
    FDIV_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(FDIV_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5),
    FDUP_SVE_Zd_SVE_FPIMM8(FDUP_SVE_Zd_SVE_FPIMM8),
    FEXPA_SVE_Zd_SVE_Zn(FEXPA_SVE_Zd_SVE_Zn),
    FMAD_SVE_Zd_SVE_Pg3_SVE_Zm_5_SVE_Za_16(FMAD_SVE_Zd_SVE_Pg3_SVE_Zm_5_SVE_Za_16),
    FMAXNMP_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(FMAXNMP_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn),
    FMAXNMV_SVE_Vd_SVE_Pg3_SVE_Zn(FMAXNMV_SVE_Vd_SVE_Pg3_SVE_Zn),
    FMAXNM_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_I1_ZERO_ONE(FMAXNM_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_I1_ZERO_ONE),
    FMAXNM_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(FMAXNM_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5),
    FMAXP_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(FMAXP_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn),
    FMAXV_SVE_Vd_SVE_Pg3_SVE_Zn(FMAXV_SVE_Vd_SVE_Pg3_SVE_Zn),
    FMAX_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_I1_ZERO_ONE(FMAX_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_I1_ZERO_ONE),
    FMAX_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(FMAX_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5),
    FMINNMP_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(FMINNMP_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn),
    FMINNMV_SVE_Vd_SVE_Pg3_SVE_Zn(FMINNMV_SVE_Vd_SVE_Pg3_SVE_Zn),
    FMINNM_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_I1_ZERO_ONE(FMINNM_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_I1_ZERO_ONE),
    FMINNM_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(FMINNM_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5),
    FMINP_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(FMINP_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn),
    FMINV_SVE_Vd_SVE_Pg3_SVE_Zn(FMINV_SVE_Vd_SVE_Pg3_SVE_Zn),
    FMIN_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_I1_ZERO_ONE(FMIN_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_I1_ZERO_ONE),
    FMIN_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(FMIN_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5),
    FMLA_SVE_Zd_SVE_Pg3_SVE_Zn_SVE_Zm_16(FMLA_SVE_Zd_SVE_Pg3_SVE_Zn_SVE_Zm_16),
    FMLS_SVE_Zd_SVE_Pg3_SVE_Zn_SVE_Zm_16(FMLS_SVE_Zd_SVE_Pg3_SVE_Zn_SVE_Zm_16),
    FMSB_SVE_Zd_SVE_Pg3_SVE_Zm_5_SVE_Za_16(FMSB_SVE_Zd_SVE_Pg3_SVE_Zm_5_SVE_Za_16),
    FMULX_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(FMULX_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5),
    FMUL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_I1_HALF_TWO(FMUL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_I1_HALF_TWO),
    FMUL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(FMUL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5),
    FMUL_SVE_Zd_SVE_Zn_SVE_Zm_16(FMUL_SVE_Zd_SVE_Zn_SVE_Zm_16),
    FNEG_SVE_Zd_SVE_Pg3_SVE_Zn(FNEG_SVE_Zd_SVE_Pg3_SVE_Zn),
    FNMAD_SVE_Zd_SVE_Pg3_SVE_Zm_5_SVE_Za_16(FNMAD_SVE_Zd_SVE_Pg3_SVE_Zm_5_SVE_Za_16),
    FNMLA_SVE_Zd_SVE_Pg3_SVE_Zn_SVE_Zm_16(FNMLA_SVE_Zd_SVE_Pg3_SVE_Zn_SVE_Zm_16),
    FNMLS_SVE_Zd_SVE_Pg3_SVE_Zn_SVE_Zm_16(FNMLS_SVE_Zd_SVE_Pg3_SVE_Zn_SVE_Zm_16),
    FNMSB_SVE_Zd_SVE_Pg3_SVE_Zm_5_SVE_Za_16(FNMSB_SVE_Zd_SVE_Pg3_SVE_Zm_5_SVE_Za_16),
    FRECPE_SVE_Zd_SVE_Zn(FRECPE_SVE_Zd_SVE_Zn),
    FRECPS_SVE_Zd_SVE_Zn_SVE_Zm_16(FRECPS_SVE_Zd_SVE_Zn_SVE_Zm_16),
    FRECPX_SVE_Zd_SVE_Pg3_SVE_Zn(FRECPX_SVE_Zd_SVE_Pg3_SVE_Zn),
    FRINTA_SVE_Zd_SVE_Pg3_SVE_Zn(FRINTA_SVE_Zd_SVE_Pg3_SVE_Zn),
    FRINTI_SVE_Zd_SVE_Pg3_SVE_Zn(FRINTI_SVE_Zd_SVE_Pg3_SVE_Zn),
    FRINTM_SVE_Zd_SVE_Pg3_SVE_Zn(FRINTM_SVE_Zd_SVE_Pg3_SVE_Zn),
    FRINTN_SVE_Zd_SVE_Pg3_SVE_Zn(FRINTN_SVE_Zd_SVE_Pg3_SVE_Zn),
    FRINTP_SVE_Zd_SVE_Pg3_SVE_Zn(FRINTP_SVE_Zd_SVE_Pg3_SVE_Zn),
    FRINTX_SVE_Zd_SVE_Pg3_SVE_Zn(FRINTX_SVE_Zd_SVE_Pg3_SVE_Zn),
    FRINTZ_SVE_Zd_SVE_Pg3_SVE_Zn(FRINTZ_SVE_Zd_SVE_Pg3_SVE_Zn),
    FRSQRTE_SVE_Zd_SVE_Zn(FRSQRTE_SVE_Zd_SVE_Zn),
    FRSQRTS_SVE_Zd_SVE_Zn_SVE_Zm_16(FRSQRTS_SVE_Zd_SVE_Zn_SVE_Zm_16),
    FSCALE_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(FSCALE_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5),
    FSQRT_SVE_Zd_SVE_Pg3_SVE_Zn(FSQRT_SVE_Zd_SVE_Pg3_SVE_Zn),
    FSUBR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_I1_HALF_ONE(FSUBR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_I1_HALF_ONE),
    FSUBR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(FSUBR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5),
    FSUB_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_I1_HALF_ONE(FSUB_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_I1_HALF_ONE),
    FSUB_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(FSUB_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5),
    FSUB_SVE_Zd_SVE_Zn_SVE_Zm_16(FSUB_SVE_Zd_SVE_Zn_SVE_Zm_16),
    FTMAD_SVE_Zd_SVE_Zd_SVE_Zm_5_SVE_UIMM3(FTMAD_SVE_Zd_SVE_Zd_SVE_Zm_5_SVE_UIMM3),
    FTSMUL_SVE_Zd_SVE_Zn_SVE_Zm_16(FTSMUL_SVE_Zd_SVE_Zn_SVE_Zm_16),
    FTSSEL_SVE_Zd_SVE_Zn_SVE_Zm_16(FTSSEL_SVE_Zd_SVE_Zn_SVE_Zm_16),
    INCP_SVE_Zd_SVE_Pg4_5(INCP_SVE_Zd_SVE_Pg4_5),
    RADDHNB_SVE_Zd_SVE_Zn_SVE_Zm_16(RADDHNB_SVE_Zd_SVE_Zn_SVE_Zm_16),
    RADDHNT_SVE_Zd_SVE_Zn_SVE_Zm_16(RADDHNT_SVE_Zd_SVE_Zn_SVE_Zm_16),
    REVB_SVE_Zd_SVE_Pg3_SVE_Zn(REVB_SVE_Zd_SVE_Pg3_SVE_Zn),
    RSUBHNB_SVE_Zd_SVE_Zn_SVE_Zm_16(RSUBHNB_SVE_Zd_SVE_Zn_SVE_Zm_16),
    RSUBHNT_SVE_Zd_SVE_Zn_SVE_Zm_16(RSUBHNT_SVE_Zd_SVE_Zn_SVE_Zm_16),
    SABALB_SVE_Zd_SVE_Zn_SVE_Zm_16(SABALB_SVE_Zd_SVE_Zn_SVE_Zm_16),
    SABALT_SVE_Zd_SVE_Zn_SVE_Zm_16(SABALT_SVE_Zd_SVE_Zn_SVE_Zm_16),
    SABDLB_SVE_Zd_SVE_Zn_SVE_Zm_16(SABDLB_SVE_Zd_SVE_Zn_SVE_Zm_16),
    SABDLT_SVE_Zd_SVE_Zn_SVE_Zm_16(SABDLT_SVE_Zd_SVE_Zn_SVE_Zm_16),
    SADALP_SVE_Zd_SVE_Pg3_SVE_Zn(SADALP_SVE_Zd_SVE_Pg3_SVE_Zn),
    SADDLBT_SVE_Zd_SVE_Zn_SVE_Zm_16(SADDLBT_SVE_Zd_SVE_Zn_SVE_Zm_16),
    SADDLB_SVE_Zd_SVE_Zn_SVE_Zm_16(SADDLB_SVE_Zd_SVE_Zn_SVE_Zm_16),
    SADDLT_SVE_Zd_SVE_Zn_SVE_Zm_16(SADDLT_SVE_Zd_SVE_Zn_SVE_Zm_16),
    SADDWB_SVE_Zd_SVE_Zn_SVE_Zm_16(SADDWB_SVE_Zd_SVE_Zn_SVE_Zm_16),
    SADDWT_SVE_Zd_SVE_Zn_SVE_Zm_16(SADDWT_SVE_Zd_SVE_Zn_SVE_Zm_16),
    SMLALB_SVE_Zd_SVE_Zn_SVE_Zm_16(SMLALB_SVE_Zd_SVE_Zn_SVE_Zm_16),
    SMLALT_SVE_Zd_SVE_Zn_SVE_Zm_16(SMLALT_SVE_Zd_SVE_Zn_SVE_Zm_16),
    SMLSLB_SVE_Zd_SVE_Zn_SVE_Zm_16(SMLSLB_SVE_Zd_SVE_Zn_SVE_Zm_16),
    SMLSLT_SVE_Zd_SVE_Zn_SVE_Zm_16(SMLSLT_SVE_Zd_SVE_Zn_SVE_Zm_16),
    SMULLB_SVE_Zd_SVE_Zn_SVE_Zm_16(SMULLB_SVE_Zd_SVE_Zn_SVE_Zm_16),
    SMULLT_SVE_Zd_SVE_Zn_SVE_Zm_16(SMULLT_SVE_Zd_SVE_Zn_SVE_Zm_16),
    SQDECP_SVE_Zd_SVE_Pg4_5(SQDECP_SVE_Zd_SVE_Pg4_5),
    SQDMLALBT_SVE_Zd_SVE_Zn_SVE_Zm_16(SQDMLALBT_SVE_Zd_SVE_Zn_SVE_Zm_16),
    SQDMLALB_SVE_Zd_SVE_Zn_SVE_Zm_16(SQDMLALB_SVE_Zd_SVE_Zn_SVE_Zm_16),
    SQDMLALT_SVE_Zd_SVE_Zn_SVE_Zm_16(SQDMLALT_SVE_Zd_SVE_Zn_SVE_Zm_16),
    SQDMLSLBT_SVE_Zd_SVE_Zn_SVE_Zm_16(SQDMLSLBT_SVE_Zd_SVE_Zn_SVE_Zm_16),
    SQDMLSLB_SVE_Zd_SVE_Zn_SVE_Zm_16(SQDMLSLB_SVE_Zd_SVE_Zn_SVE_Zm_16),
    SQDMLSLT_SVE_Zd_SVE_Zn_SVE_Zm_16(SQDMLSLT_SVE_Zd_SVE_Zn_SVE_Zm_16),
    SQDMULLB_SVE_Zd_SVE_Zn_SVE_Zm_16(SQDMULLB_SVE_Zd_SVE_Zn_SVE_Zm_16),
    SQDMULLT_SVE_Zd_SVE_Zn_SVE_Zm_16(SQDMULLT_SVE_Zd_SVE_Zn_SVE_Zm_16),
    SQINCP_SVE_Zd_SVE_Pg4_5(SQINCP_SVE_Zd_SVE_Pg4_5),
    SSUBLBT_SVE_Zd_SVE_Zn_SVE_Zm_16(SSUBLBT_SVE_Zd_SVE_Zn_SVE_Zm_16),
    SSUBLB_SVE_Zd_SVE_Zn_SVE_Zm_16(SSUBLB_SVE_Zd_SVE_Zn_SVE_Zm_16),
    SSUBLTB_SVE_Zd_SVE_Zn_SVE_Zm_16(SSUBLTB_SVE_Zd_SVE_Zn_SVE_Zm_16),
    SSUBLT_SVE_Zd_SVE_Zn_SVE_Zm_16(SSUBLT_SVE_Zd_SVE_Zn_SVE_Zm_16),
    SSUBWB_SVE_Zd_SVE_Zn_SVE_Zm_16(SSUBWB_SVE_Zd_SVE_Zn_SVE_Zm_16),
    SSUBWT_SVE_Zd_SVE_Zn_SVE_Zm_16(SSUBWT_SVE_Zd_SVE_Zn_SVE_Zm_16),
    SUBHNB_SVE_Zd_SVE_Zn_SVE_Zm_16(SUBHNB_SVE_Zd_SVE_Zn_SVE_Zm_16),
    SUBHNT_SVE_Zd_SVE_Zn_SVE_Zm_16(SUBHNT_SVE_Zd_SVE_Zn_SVE_Zm_16),
    SUNPKHI_SVE_Zd_SVE_Zn(SUNPKHI_SVE_Zd_SVE_Zn),
    SUNPKLO_SVE_Zd_SVE_Zn(SUNPKLO_SVE_Zd_SVE_Zn),
    SXTB_SVE_Zd_SVE_Pg3_SVE_Zn(SXTB_SVE_Zd_SVE_Pg3_SVE_Zn),
    UABALB_SVE_Zd_SVE_Zn_SVE_Zm_16(UABALB_SVE_Zd_SVE_Zn_SVE_Zm_16),
    UABALT_SVE_Zd_SVE_Zn_SVE_Zm_16(UABALT_SVE_Zd_SVE_Zn_SVE_Zm_16),
    UABDLB_SVE_Zd_SVE_Zn_SVE_Zm_16(UABDLB_SVE_Zd_SVE_Zn_SVE_Zm_16),
    UABDLT_SVE_Zd_SVE_Zn_SVE_Zm_16(UABDLT_SVE_Zd_SVE_Zn_SVE_Zm_16),
    UADALP_SVE_Zd_SVE_Pg3_SVE_Zn(UADALP_SVE_Zd_SVE_Pg3_SVE_Zn),
    UADDLB_SVE_Zd_SVE_Zn_SVE_Zm_16(UADDLB_SVE_Zd_SVE_Zn_SVE_Zm_16),
    UADDLT_SVE_Zd_SVE_Zn_SVE_Zm_16(UADDLT_SVE_Zd_SVE_Zn_SVE_Zm_16),
    UADDWB_SVE_Zd_SVE_Zn_SVE_Zm_16(UADDWB_SVE_Zd_SVE_Zn_SVE_Zm_16),
    UADDWT_SVE_Zd_SVE_Zn_SVE_Zm_16(UADDWT_SVE_Zd_SVE_Zn_SVE_Zm_16),
    UMLALB_SVE_Zd_SVE_Zn_SVE_Zm_16(UMLALB_SVE_Zd_SVE_Zn_SVE_Zm_16),
    UMLALT_SVE_Zd_SVE_Zn_SVE_Zm_16(UMLALT_SVE_Zd_SVE_Zn_SVE_Zm_16),
    UMLSLB_SVE_Zd_SVE_Zn_SVE_Zm_16(UMLSLB_SVE_Zd_SVE_Zn_SVE_Zm_16),
    UMLSLT_SVE_Zd_SVE_Zn_SVE_Zm_16(UMLSLT_SVE_Zd_SVE_Zn_SVE_Zm_16),
    UMULLB_SVE_Zd_SVE_Zn_SVE_Zm_16(UMULLB_SVE_Zd_SVE_Zn_SVE_Zm_16),
    UMULLT_SVE_Zd_SVE_Zn_SVE_Zm_16(UMULLT_SVE_Zd_SVE_Zn_SVE_Zm_16),
    UQDECP_SVE_Zd_SVE_Pg4_5(UQDECP_SVE_Zd_SVE_Pg4_5),
    UQINCP_SVE_Zd_SVE_Pg4_5(UQINCP_SVE_Zd_SVE_Pg4_5),
    USUBLB_SVE_Zd_SVE_Zn_SVE_Zm_16(USUBLB_SVE_Zd_SVE_Zn_SVE_Zm_16),
    USUBLT_SVE_Zd_SVE_Zn_SVE_Zm_16(USUBLT_SVE_Zd_SVE_Zn_SVE_Zm_16),
    USUBWB_SVE_Zd_SVE_Zn_SVE_Zm_16(USUBWB_SVE_Zd_SVE_Zn_SVE_Zm_16),
    USUBWT_SVE_Zd_SVE_Zn_SVE_Zm_16(USUBWT_SVE_Zd_SVE_Zn_SVE_Zm_16),
    UUNPKHI_SVE_Zd_SVE_Zn(UUNPKHI_SVE_Zd_SVE_Zn),
    UUNPKLO_SVE_Zd_SVE_Zn(UUNPKLO_SVE_Zd_SVE_Zn),
    UXTB_SVE_Zd_SVE_Pg3_SVE_Zn(UXTB_SVE_Zd_SVE_Pg3_SVE_Zn),
}
#[derive(Debug, PartialEq, Eq, Copy, Clone)]
pub enum FLOATCMP {
    FCMPE_Fn_FPIMM0(FCMPE_Fn_FPIMM0),
    FCMPE_Fn_Fm(FCMPE_Fn_Fm),
    FCMPE_Fn_S_S_FPIMM0(FCMPE_Fn_S_S_FPIMM0),
    FCMPE_Fn_S_S_Fm_S_S(FCMPE_Fn_S_S_Fm_S_S),
    FCMP_Fn_FPIMM0(FCMP_Fn_FPIMM0),
    FCMP_Fn_Fm(FCMP_Fn_Fm),
    FCMP_Fn_S_S_FPIMM0(FCMP_Fn_S_S_FPIMM0),
    FCMP_Fn_S_S_Fm_S_S(FCMP_Fn_S_S_Fm_S_S),
}
#[derive(Debug, PartialEq, Eq, Copy, Clone)]
pub enum LSE128_ATOMIC {
    LDCLRPAL_LSE128_Rt_LSE128_Rt2_ADDR_SIMPLE(LDCLRPAL_LSE128_Rt_LSE128_Rt2_ADDR_SIMPLE),
    LDCLRPA_LSE128_Rt_LSE128_Rt2_ADDR_SIMPLE(LDCLRPA_LSE128_Rt_LSE128_Rt2_ADDR_SIMPLE),
    LDCLRPL_LSE128_Rt_LSE128_Rt2_ADDR_SIMPLE(LDCLRPL_LSE128_Rt_LSE128_Rt2_ADDR_SIMPLE),
    LDCLRP_LSE128_Rt_LSE128_Rt2_ADDR_SIMPLE(LDCLRP_LSE128_Rt_LSE128_Rt2_ADDR_SIMPLE),
    LDSETPAL_LSE128_Rt_LSE128_Rt2_ADDR_SIMPLE(LDSETPAL_LSE128_Rt_LSE128_Rt2_ADDR_SIMPLE),
    LDSETPA_LSE128_Rt_LSE128_Rt2_ADDR_SIMPLE(LDSETPA_LSE128_Rt_LSE128_Rt2_ADDR_SIMPLE),
    LDSETPL_LSE128_Rt_LSE128_Rt2_ADDR_SIMPLE(LDSETPL_LSE128_Rt_LSE128_Rt2_ADDR_SIMPLE),
    LDSETP_LSE128_Rt_LSE128_Rt2_ADDR_SIMPLE(LDSETP_LSE128_Rt_LSE128_Rt2_ADDR_SIMPLE),
    SWPPAL_LSE128_Rt_LSE128_Rt2_ADDR_SIMPLE(SWPPAL_LSE128_Rt_LSE128_Rt2_ADDR_SIMPLE),
    SWPPA_LSE128_Rt_LSE128_Rt2_ADDR_SIMPLE(SWPPA_LSE128_Rt_LSE128_Rt2_ADDR_SIMPLE),
    SWPPL_LSE128_Rt_LSE128_Rt2_ADDR_SIMPLE(SWPPL_LSE128_Rt_LSE128_Rt2_ADDR_SIMPLE),
    SWPP_LSE128_Rt_LSE128_Rt2_ADDR_SIMPLE(SWPP_LSE128_Rt_LSE128_Rt2_ADDR_SIMPLE),
}
#[derive(Debug, PartialEq, Eq, Copy, Clone)]
pub enum CONDBRANCH {
    BC__ADDR_PCREL19(BC__ADDR_PCREL19),
    B__ADDR_PCREL19(B__ADDR_PCREL19),
}
#[derive(Debug, PartialEq, Eq, Copy, Clone)]
pub enum SVE_SIZE_SD2 {
    LDNT1SB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZX(LDNT1SB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZX),
    LDNT1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZX(LDNT1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZX),
}
#[derive(Debug, PartialEq, Eq, Copy, Clone)]
pub enum FLOATDP1 {
    FABS_Fd_Fn(FABS_Fd_Fn),
    FABS_Fd_S_S_Fn_S_S(FABS_Fd_S_S_Fn_S_S),
    FCVT_Fd_Fn(FCVT_Fd_Fn),
    FMOV_Fd_Fn(FMOV_Fd_Fn),
    FMOV_Fd_S_S_Fn_S_S(FMOV_Fd_S_S_Fn_S_S),
    FNEG_Fd_Fn(FNEG_Fd_Fn),
    FNEG_Fd_S_S_Fn_S_S(FNEG_Fd_S_S_Fn_S_S),
    FRINT32X_Fd_Fn(FRINT32X_Fd_Fn),
    FRINT32Z_Fd_Fn(FRINT32Z_Fd_Fn),
    FRINT64X_Fd_Fn(FRINT64X_Fd_Fn),
    FRINT64Z_Fd_Fn(FRINT64Z_Fd_Fn),
    FRINTA_Fd_Fn(FRINTA_Fd_Fn),
    FRINTA_Fd_S_S_Fn_S_S(FRINTA_Fd_S_S_Fn_S_S),
    FRINTI_Fd_Fn(FRINTI_Fd_Fn),
    FRINTI_Fd_S_S_Fn_S_S(FRINTI_Fd_S_S_Fn_S_S),
    FRINTM_Fd_Fn(FRINTM_Fd_Fn),
    FRINTM_Fd_S_S_Fn_S_S(FRINTM_Fd_S_S_Fn_S_S),
    FRINTN_Fd_Fn(FRINTN_Fd_Fn),
    FRINTN_Fd_S_S_Fn_S_S(FRINTN_Fd_S_S_Fn_S_S),
    FRINTP_Fd_Fn(FRINTP_Fd_Fn),
    FRINTP_Fd_S_S_Fn_S_S(FRINTP_Fd_S_S_Fn_S_S),
    FRINTX_Fd_Fn(FRINTX_Fd_Fn),
    FRINTX_Fd_S_S_Fn_S_S(FRINTX_Fd_S_S_Fn_S_S),
    FRINTZ_Fd_Fn(FRINTZ_Fd_Fn),
    FRINTZ_Fd_S_S_Fn_S_S(FRINTZ_Fd_S_S_Fn_S_S),
    FSQRT_Fd_Fn(FSQRT_Fd_Fn),
    FSQRT_Fd_S_S_Fn_S_S(FSQRT_Fd_S_S_Fn_S_S),
}
#[derive(Debug, PartialEq, Eq, Copy, Clone)]
pub enum PCRELADDR {
    ADRP_Rd_ADDR_ADRP(ADRP_Rd_ADDR_ADRP),
    ADR_Rd_ADDR_PCREL21(ADR_Rd_ADDR_PCREL21),
}
#[derive(Debug, PartialEq, Eq, Copy, Clone)]
pub enum BITFIELD {
    BFM_Rd_Rn_IMMR_IMMS(BFM_Rd_Rn_IMMR_IMMS),
    SBFM_Rd_Rn_IMMR_IMMS(SBFM_Rd_Rn_IMMR_IMMS),
    UBFM_Rd_Rn_IMMR_IMMS(UBFM_Rd_Rn_IMMR_IMMS),
}
#[derive(Debug, PartialEq, Eq, Copy, Clone)]
pub enum LOG_IMM {
    ANDS_Rd_Rn_LIMM(ANDS_Rd_Rn_LIMM),
    AND_Rd_SP_Rn_LIMM(AND_Rd_SP_Rn_LIMM),
    EOR_Rd_SP_Rn_LIMM(EOR_Rd_SP_Rn_LIMM),
    ORR_Rd_SP_Rn_LIMM(ORR_Rd_SP_Rn_LIMM),
}
#[derive(Debug, PartialEq, Eq, Copy, Clone)]
pub enum ASISDONE {
    DUP_Sd_En(DUP_Sd_En),
}
#[derive(Debug, PartialEq, Eq, Copy, Clone)]
pub enum CONDSEL {
    CSEL_Rd_Rn_Rm_COND(CSEL_Rd_Rn_Rm_COND),
    CSINC_Rd_Rn_Rm_COND(CSINC_Rd_Rn_Rm_COND),
    CSINV_Rd_Rn_Rm_COND(CSINV_Rd_Rn_Rm_COND),
    CSNEG_Rd_Rn_Rm_COND(CSNEG_Rd_Rn_Rm_COND),
}
#[derive(Debug, PartialEq, Eq, Copy, Clone)]
pub enum CONDCMP_REG {
    CCMN_Rn_Rm_NZCV_COND(CCMN_Rn_Rm_NZCV_COND),
    CCMP_Rn_Rm_NZCV_COND(CCMP_Rn_Rm_NZCV_COND),
}
#[derive(Debug, PartialEq, Eq, Copy, Clone)]
pub enum ASIMDELEM {
    FCMLA_Vd_Vn_Em_IMM_ROT2(FCMLA_Vd_Vn_Em_IMM_ROT2),
    FMLAL2_Vd_V_4S_Vn_V_4H_Em16_S_H(FMLAL2_Vd_V_4S_Vn_V_4H_Em16_S_H),
    FMLAL2_Vd_Vn_Em16(FMLAL2_Vd_Vn_Em16),
    FMLAL_Vd_V_4S_Vn_V_4H_Em16_S_H(FMLAL_Vd_V_4S_Vn_V_4H_Em16_S_H),
    FMLAL_Vd_Vn_Em16(FMLAL_Vd_Vn_Em16),
    FMLA_Vd_Vn_Em(FMLA_Vd_Vn_Em),
    FMLA_Vd_Vn_Em16(FMLA_Vd_Vn_Em16),
    FMLSL2_Vd_V_4S_Vn_V_4H_Em16_S_H(FMLSL2_Vd_V_4S_Vn_V_4H_Em16_S_H),
    FMLSL2_Vd_Vn_Em16(FMLSL2_Vd_Vn_Em16),
    FMLSL_Vd_V_4S_Vn_V_4H_Em16_S_H(FMLSL_Vd_V_4S_Vn_V_4H_Em16_S_H),
    FMLSL_Vd_Vn_Em16(FMLSL_Vd_Vn_Em16),
    FMLS_Vd_Vn_Em(FMLS_Vd_Vn_Em),
    FMLS_Vd_Vn_Em16(FMLS_Vd_Vn_Em16),
    FMULX_Vd_Vn_Em(FMULX_Vd_Vn_Em),
    FMULX_Vd_Vn_Em16(FMULX_Vd_Vn_Em16),
    FMUL_Vd_Vn_Em(FMUL_Vd_Vn_Em),
    FMUL_Vd_Vn_Em16(FMUL_Vd_Vn_Em16),
    MLA_Vd_Vn_Em16(MLA_Vd_Vn_Em16),
    MLS_Vd_Vn_Em16(MLS_Vd_Vn_Em16),
    MUL_Vd_Vn_Em16(MUL_Vd_Vn_Em16),
    SMLAL2_Vd_Vn_Em16(SMLAL2_Vd_Vn_Em16),
    SMLAL_Vd_Vn_Em16(SMLAL_Vd_Vn_Em16),
    SMLSL2_Vd_Vn_Em16(SMLSL2_Vd_Vn_Em16),
    SMLSL_Vd_Vn_Em16(SMLSL_Vd_Vn_Em16),
    SMULL2_Vd_Vn_Em16(SMULL2_Vd_Vn_Em16),
    SMULL_Vd_Vn_Em16(SMULL_Vd_Vn_Em16),
    SQDMLAL2_Vd_Vn_Em16(SQDMLAL2_Vd_Vn_Em16),
    SQDMLAL_Vd_Vn_Em16(SQDMLAL_Vd_Vn_Em16),
    SQDMLSL2_Vd_Vn_Em16(SQDMLSL2_Vd_Vn_Em16),
    SQDMLSL_Vd_Vn_Em16(SQDMLSL_Vd_Vn_Em16),
    SQDMULH_Vd_Vn_Em16(SQDMULH_Vd_Vn_Em16),
    SQDMULL2_Vd_Vn_Em16(SQDMULL2_Vd_Vn_Em16),
    SQDMULL_Vd_Vn_Em16(SQDMULL_Vd_Vn_Em16),
    SQRDMLAH_Vd_Vn_Em16(SQRDMLAH_Vd_Vn_Em16),
    SQRDMLSH_Vd_Vn_Em16(SQRDMLSH_Vd_Vn_Em16),
    SQRDMULH_Vd_Vn_Em16(SQRDMULH_Vd_Vn_Em16),
    UMLAL2_Vd_Vn_Em16(UMLAL2_Vd_Vn_Em16),
    UMLAL_Vd_Vn_Em16(UMLAL_Vd_Vn_Em16),
    UMLSL2_Vd_Vn_Em16(UMLSL2_Vd_Vn_Em16),
    UMLSL_Vd_Vn_Em16(UMLSL_Vd_Vn_Em16),
    UMULL2_Vd_Vn_Em16(UMULL2_Vd_Vn_Em16),
    UMULL_Vd_Vn_Em16(UMULL_Vd_Vn_Em16),
}
#[derive(Debug, PartialEq, Eq, Copy, Clone)]
pub enum ADDSUB_CARRY {
    ADCS_Rd_Rn_Rm(ADCS_Rd_Rn_Rm),
    ADC_Rd_Rn_Rm(ADC_Rd_Rn_Rm),
    SBCS_Rd_Rn_Rm(SBCS_Rd_Rn_Rm),
    SBC_Rd_Rn_Rm(SBC_Rd_Rn_Rm),
}
#[derive(Debug, PartialEq, Eq, Copy, Clone)]
pub enum SVE_SHIFT_TSZ_BHSD {
    SLI_SVE_Zd_SVE_Zn_SVE_SHLIMM_UNPRED(SLI_SVE_Zd_SVE_Zn_SVE_SHLIMM_UNPRED),
    SRI_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED(SRI_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED),
    SRSRA_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED(SRSRA_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED),
    SSRA_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED(SSRA_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED),
    URSRA_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED(URSRA_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED),
    USRA_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED(USRA_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED),
    XAR_SVE_Zd_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED(XAR_SVE_Zd_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED),
}
#[derive(Debug, PartialEq, Eq, Copy, Clone)]
pub enum CRYPTOSM4 {
    SM4EKEY_Vd_Vn_Vm(SM4EKEY_Vd_Vn_Vm),
    SM4E_Vd_Vn(SM4E_Vd_Vn),
}
#[derive(Debug, PartialEq, Eq, Copy, Clone)]
pub enum SME_SHIFT {
    SQRSHRN_SVE_Zd_SME_Znx4_SME_SHRIMM5(SQRSHRN_SVE_Zd_SME_Znx4_SME_SHRIMM5),
    SQRSHRUN_SVE_Zd_SME_Znx4_SME_SHRIMM5(SQRSHRUN_SVE_Zd_SME_Znx4_SME_SHRIMM5),
    SQRSHRU_SVE_Zd_SME_Znx4_SME_SHRIMM5(SQRSHRU_SVE_Zd_SME_Znx4_SME_SHRIMM5),
    SQRSHR_SVE_Zd_SME_Znx4_SME_SHRIMM5(SQRSHR_SVE_Zd_SME_Znx4_SME_SHRIMM5),
    UQRSHRN_SVE_Zd_SME_Znx4_SME_SHRIMM5(UQRSHRN_SVE_Zd_SME_Znx4_SME_SHRIMM5),
    UQRSHR_SVE_Zd_SME_Znx4_SME_SHRIMM5(UQRSHR_SVE_Zd_SME_Znx4_SME_SHRIMM5),
}
#[derive(Debug, PartialEq, Eq, Copy, Clone)]
pub enum ASIMDEXT {
    EXT_Vd_Vn_Vm_IDX(EXT_Vd_Vn_Vm_IDX),
}
#[derive(Debug, PartialEq, Eq, Copy, Clone)]
pub enum CRYPTOSM3 {
    SM3PARTW1_Vd_Vn_Vm(SM3PARTW1_Vd_Vn_Vm),
    SM3PARTW2_Vd_Vn_Vm(SM3PARTW2_Vd_Vn_Vm),
    SM3SS1_Vd_Vn_Vm_Va(SM3SS1_Vd_Vn_Vm_Va),
    SM3TT1A_Vd_Vn_Em(SM3TT1A_Vd_Vn_Em),
    SM3TT1B_Vd_Vn_Em(SM3TT1B_Vd_Vn_Em),
    SM3TT2A_Vd_Vn_Em(SM3TT2A_Vd_Vn_Em),
    SM3TT2B_Vd_Vn_Em(SM3TT2B_Vd_Vn_Em),
}
#[derive(Debug, PartialEq, Eq, Copy, Clone)]
pub enum ASISDELEM {
    FMLA_Sd_Sn_Em(FMLA_Sd_Sn_Em),
    FMLA_Sd_Sn_Em16(FMLA_Sd_Sn_Em16),
    FMLS_Sd_Sn_Em(FMLS_Sd_Sn_Em),
    FMLS_Sd_Sn_Em16(FMLS_Sd_Sn_Em16),
    FMULX_Sd_Sn_Em(FMULX_Sd_Sn_Em),
    FMULX_Sd_Sn_Em16(FMULX_Sd_Sn_Em16),
    FMUL_Sd_Sn_Em(FMUL_Sd_Sn_Em),
    FMUL_Sd_Sn_Em16(FMUL_Sd_Sn_Em16),
    SQDMLAL_Sd_Sn_Em16(SQDMLAL_Sd_Sn_Em16),
    SQDMLSL_Sd_Sn_Em16(SQDMLSL_Sd_Sn_Em16),
    SQDMULH_Sd_Sn_Em16(SQDMULH_Sd_Sn_Em16),
    SQDMULL_Sd_Sn_Em16(SQDMULL_Sd_Sn_Em16),
    SQRDMLAH_Sd_Sn_Em16(SQRDMLAH_Sd_Sn_Em16),
    SQRDMLSH_Sd_Sn_Em16(SQRDMLSH_Sd_Sn_Em16),
    SQRDMULH_Sd_Sn_Em16(SQRDMULH_Sd_Sn_Em16),
}
#[derive(Debug, PartialEq, Eq, Copy, Clone)]
pub enum LSE_ATOMIC {
    CASAB_Rs_Rt_ADDR_SIMPLE(CASAB_Rs_Rt_ADDR_SIMPLE),
    CASAH_Rs_Rt_ADDR_SIMPLE(CASAH_Rs_Rt_ADDR_SIMPLE),
    CASALB_Rs_Rt_ADDR_SIMPLE(CASALB_Rs_Rt_ADDR_SIMPLE),
    CASALH_Rs_Rt_ADDR_SIMPLE(CASALH_Rs_Rt_ADDR_SIMPLE),
    CASAL_Rs_Rt_ADDR_SIMPLE(CASAL_Rs_Rt_ADDR_SIMPLE),
    CASA_Rs_Rt_ADDR_SIMPLE(CASA_Rs_Rt_ADDR_SIMPLE),
    CASB_Rs_Rt_ADDR_SIMPLE(CASB_Rs_Rt_ADDR_SIMPLE),
    CASH_Rs_Rt_ADDR_SIMPLE(CASH_Rs_Rt_ADDR_SIMPLE),
    CASLB_Rs_Rt_ADDR_SIMPLE(CASLB_Rs_Rt_ADDR_SIMPLE),
    CASLH_Rs_Rt_ADDR_SIMPLE(CASLH_Rs_Rt_ADDR_SIMPLE),
    CASL_Rs_Rt_ADDR_SIMPLE(CASL_Rs_Rt_ADDR_SIMPLE),
    CASPAL_Rs_PAIRREG_Rt_PAIRREG_ADDR_SIMPLE(CASPAL_Rs_PAIRREG_Rt_PAIRREG_ADDR_SIMPLE),
    CASPA_Rs_PAIRREG_Rt_PAIRREG_ADDR_SIMPLE(CASPA_Rs_PAIRREG_Rt_PAIRREG_ADDR_SIMPLE),
    CASPL_Rs_PAIRREG_Rt_PAIRREG_ADDR_SIMPLE(CASPL_Rs_PAIRREG_Rt_PAIRREG_ADDR_SIMPLE),
    CASP_Rs_PAIRREG_Rt_PAIRREG_ADDR_SIMPLE(CASP_Rs_PAIRREG_Rt_PAIRREG_ADDR_SIMPLE),
    CAS_Rs_Rt_ADDR_SIMPLE(CAS_Rs_Rt_ADDR_SIMPLE),
    LD64B_Rt_LS64_ADDR_SIMPLE(LD64B_Rt_LS64_ADDR_SIMPLE),
    LDADDAB_Rs_Rt_ADDR_SIMPLE(LDADDAB_Rs_Rt_ADDR_SIMPLE),
    LDADDAH_Rs_Rt_ADDR_SIMPLE(LDADDAH_Rs_Rt_ADDR_SIMPLE),
    LDADDALB_Rs_Rt_ADDR_SIMPLE(LDADDALB_Rs_Rt_ADDR_SIMPLE),
    LDADDALH_Rs_Rt_ADDR_SIMPLE(LDADDALH_Rs_Rt_ADDR_SIMPLE),
    LDADDAL_Rs_Rt_ADDR_SIMPLE(LDADDAL_Rs_Rt_ADDR_SIMPLE),
    LDADDA_Rs_Rt_ADDR_SIMPLE(LDADDA_Rs_Rt_ADDR_SIMPLE),
    LDADDB_Rs_Rt_ADDR_SIMPLE(LDADDB_Rs_Rt_ADDR_SIMPLE),
    LDADDH_Rs_Rt_ADDR_SIMPLE(LDADDH_Rs_Rt_ADDR_SIMPLE),
    LDADDLB_Rs_Rt_ADDR_SIMPLE(LDADDLB_Rs_Rt_ADDR_SIMPLE),
    LDADDLH_Rs_Rt_ADDR_SIMPLE(LDADDLH_Rs_Rt_ADDR_SIMPLE),
    LDADDL_Rs_Rt_ADDR_SIMPLE(LDADDL_Rs_Rt_ADDR_SIMPLE),
    LDADD_Rs_Rt_ADDR_SIMPLE(LDADD_Rs_Rt_ADDR_SIMPLE),
    LDCLRAB_Rs_Rt_ADDR_SIMPLE(LDCLRAB_Rs_Rt_ADDR_SIMPLE),
    LDCLRAH_Rs_Rt_ADDR_SIMPLE(LDCLRAH_Rs_Rt_ADDR_SIMPLE),
    LDCLRALB_Rs_Rt_ADDR_SIMPLE(LDCLRALB_Rs_Rt_ADDR_SIMPLE),
    LDCLRALH_Rs_Rt_ADDR_SIMPLE(LDCLRALH_Rs_Rt_ADDR_SIMPLE),
    LDCLRAL_Rs_Rt_ADDR_SIMPLE(LDCLRAL_Rs_Rt_ADDR_SIMPLE),
    LDCLRA_Rs_Rt_ADDR_SIMPLE(LDCLRA_Rs_Rt_ADDR_SIMPLE),
    LDCLRB_Rs_Rt_ADDR_SIMPLE(LDCLRB_Rs_Rt_ADDR_SIMPLE),
    LDCLRH_Rs_Rt_ADDR_SIMPLE(LDCLRH_Rs_Rt_ADDR_SIMPLE),
    LDCLRLB_Rs_Rt_ADDR_SIMPLE(LDCLRLB_Rs_Rt_ADDR_SIMPLE),
    LDCLRLH_Rs_Rt_ADDR_SIMPLE(LDCLRLH_Rs_Rt_ADDR_SIMPLE),
    LDCLRL_Rs_Rt_ADDR_SIMPLE(LDCLRL_Rs_Rt_ADDR_SIMPLE),
    LDCLR_Rs_Rt_ADDR_SIMPLE(LDCLR_Rs_Rt_ADDR_SIMPLE),
    LDEORAB_Rs_Rt_ADDR_SIMPLE(LDEORAB_Rs_Rt_ADDR_SIMPLE),
    LDEORAH_Rs_Rt_ADDR_SIMPLE(LDEORAH_Rs_Rt_ADDR_SIMPLE),
    LDEORALB_Rs_Rt_ADDR_SIMPLE(LDEORALB_Rs_Rt_ADDR_SIMPLE),
    LDEORALH_Rs_Rt_ADDR_SIMPLE(LDEORALH_Rs_Rt_ADDR_SIMPLE),
    LDEORAL_Rs_Rt_ADDR_SIMPLE(LDEORAL_Rs_Rt_ADDR_SIMPLE),
    LDEORA_Rs_Rt_ADDR_SIMPLE(LDEORA_Rs_Rt_ADDR_SIMPLE),
    LDEORB_Rs_Rt_ADDR_SIMPLE(LDEORB_Rs_Rt_ADDR_SIMPLE),
    LDEORH_Rs_Rt_ADDR_SIMPLE(LDEORH_Rs_Rt_ADDR_SIMPLE),
    LDEORLB_Rs_Rt_ADDR_SIMPLE(LDEORLB_Rs_Rt_ADDR_SIMPLE),
    LDEORLH_Rs_Rt_ADDR_SIMPLE(LDEORLH_Rs_Rt_ADDR_SIMPLE),
    LDEORL_Rs_Rt_ADDR_SIMPLE(LDEORL_Rs_Rt_ADDR_SIMPLE),
    LDEOR_Rs_Rt_ADDR_SIMPLE(LDEOR_Rs_Rt_ADDR_SIMPLE),
    LDSETAB_Rs_Rt_ADDR_SIMPLE(LDSETAB_Rs_Rt_ADDR_SIMPLE),
    LDSETAH_Rs_Rt_ADDR_SIMPLE(LDSETAH_Rs_Rt_ADDR_SIMPLE),
    LDSETALB_Rs_Rt_ADDR_SIMPLE(LDSETALB_Rs_Rt_ADDR_SIMPLE),
    LDSETALH_Rs_Rt_ADDR_SIMPLE(LDSETALH_Rs_Rt_ADDR_SIMPLE),
    LDSETAL_Rs_Rt_ADDR_SIMPLE(LDSETAL_Rs_Rt_ADDR_SIMPLE),
    LDSETA_Rs_Rt_ADDR_SIMPLE(LDSETA_Rs_Rt_ADDR_SIMPLE),
    LDSETB_Rs_Rt_ADDR_SIMPLE(LDSETB_Rs_Rt_ADDR_SIMPLE),
    LDSETH_Rs_Rt_ADDR_SIMPLE(LDSETH_Rs_Rt_ADDR_SIMPLE),
    LDSETLB_Rs_Rt_ADDR_SIMPLE(LDSETLB_Rs_Rt_ADDR_SIMPLE),
    LDSETLH_Rs_Rt_ADDR_SIMPLE(LDSETLH_Rs_Rt_ADDR_SIMPLE),
    LDSETL_Rs_Rt_ADDR_SIMPLE(LDSETL_Rs_Rt_ADDR_SIMPLE),
    LDSET_Rs_Rt_ADDR_SIMPLE(LDSET_Rs_Rt_ADDR_SIMPLE),
    LDSMAXAB_Rs_Rt_ADDR_SIMPLE(LDSMAXAB_Rs_Rt_ADDR_SIMPLE),
    LDSMAXAH_Rs_Rt_ADDR_SIMPLE(LDSMAXAH_Rs_Rt_ADDR_SIMPLE),
    LDSMAXALB_Rs_Rt_ADDR_SIMPLE(LDSMAXALB_Rs_Rt_ADDR_SIMPLE),
    LDSMAXALH_Rs_Rt_ADDR_SIMPLE(LDSMAXALH_Rs_Rt_ADDR_SIMPLE),
    LDSMAXAL_Rs_Rt_ADDR_SIMPLE(LDSMAXAL_Rs_Rt_ADDR_SIMPLE),
    LDSMAXA_Rs_Rt_ADDR_SIMPLE(LDSMAXA_Rs_Rt_ADDR_SIMPLE),
    LDSMAXB_Rs_Rt_ADDR_SIMPLE(LDSMAXB_Rs_Rt_ADDR_SIMPLE),
    LDSMAXH_Rs_Rt_ADDR_SIMPLE(LDSMAXH_Rs_Rt_ADDR_SIMPLE),
    LDSMAXLB_Rs_Rt_ADDR_SIMPLE(LDSMAXLB_Rs_Rt_ADDR_SIMPLE),
    LDSMAXLH_Rs_Rt_ADDR_SIMPLE(LDSMAXLH_Rs_Rt_ADDR_SIMPLE),
    LDSMAXL_Rs_Rt_ADDR_SIMPLE(LDSMAXL_Rs_Rt_ADDR_SIMPLE),
    LDSMAX_Rs_Rt_ADDR_SIMPLE(LDSMAX_Rs_Rt_ADDR_SIMPLE),
    LDSMINAB_Rs_Rt_ADDR_SIMPLE(LDSMINAB_Rs_Rt_ADDR_SIMPLE),
    LDSMINAH_Rs_Rt_ADDR_SIMPLE(LDSMINAH_Rs_Rt_ADDR_SIMPLE),
    LDSMINALB_Rs_Rt_ADDR_SIMPLE(LDSMINALB_Rs_Rt_ADDR_SIMPLE),
    LDSMINALH_Rs_Rt_ADDR_SIMPLE(LDSMINALH_Rs_Rt_ADDR_SIMPLE),
    LDSMINAL_Rs_Rt_ADDR_SIMPLE(LDSMINAL_Rs_Rt_ADDR_SIMPLE),
    LDSMINA_Rs_Rt_ADDR_SIMPLE(LDSMINA_Rs_Rt_ADDR_SIMPLE),
    LDSMINB_Rs_Rt_ADDR_SIMPLE(LDSMINB_Rs_Rt_ADDR_SIMPLE),
    LDSMINH_Rs_Rt_ADDR_SIMPLE(LDSMINH_Rs_Rt_ADDR_SIMPLE),
    LDSMINLB_Rs_Rt_ADDR_SIMPLE(LDSMINLB_Rs_Rt_ADDR_SIMPLE),
    LDSMINLH_Rs_Rt_ADDR_SIMPLE(LDSMINLH_Rs_Rt_ADDR_SIMPLE),
    LDSMINL_Rs_Rt_ADDR_SIMPLE(LDSMINL_Rs_Rt_ADDR_SIMPLE),
    LDSMIN_Rs_Rt_ADDR_SIMPLE(LDSMIN_Rs_Rt_ADDR_SIMPLE),
    LDUMAXAB_Rs_Rt_ADDR_SIMPLE(LDUMAXAB_Rs_Rt_ADDR_SIMPLE),
    LDUMAXAH_Rs_Rt_ADDR_SIMPLE(LDUMAXAH_Rs_Rt_ADDR_SIMPLE),
    LDUMAXALB_Rs_Rt_ADDR_SIMPLE(LDUMAXALB_Rs_Rt_ADDR_SIMPLE),
    LDUMAXALH_Rs_Rt_ADDR_SIMPLE(LDUMAXALH_Rs_Rt_ADDR_SIMPLE),
    LDUMAXAL_Rs_Rt_ADDR_SIMPLE(LDUMAXAL_Rs_Rt_ADDR_SIMPLE),
    LDUMAXA_Rs_Rt_ADDR_SIMPLE(LDUMAXA_Rs_Rt_ADDR_SIMPLE),
    LDUMAXB_Rs_Rt_ADDR_SIMPLE(LDUMAXB_Rs_Rt_ADDR_SIMPLE),
    LDUMAXH_Rs_Rt_ADDR_SIMPLE(LDUMAXH_Rs_Rt_ADDR_SIMPLE),
    LDUMAXLB_Rs_Rt_ADDR_SIMPLE(LDUMAXLB_Rs_Rt_ADDR_SIMPLE),
    LDUMAXLH_Rs_Rt_ADDR_SIMPLE(LDUMAXLH_Rs_Rt_ADDR_SIMPLE),
    LDUMAXL_Rs_Rt_ADDR_SIMPLE(LDUMAXL_Rs_Rt_ADDR_SIMPLE),
    LDUMAX_Rs_Rt_ADDR_SIMPLE(LDUMAX_Rs_Rt_ADDR_SIMPLE),
    LDUMINAB_Rs_Rt_ADDR_SIMPLE(LDUMINAB_Rs_Rt_ADDR_SIMPLE),
    LDUMINAH_Rs_Rt_ADDR_SIMPLE(LDUMINAH_Rs_Rt_ADDR_SIMPLE),
    LDUMINALB_Rs_Rt_ADDR_SIMPLE(LDUMINALB_Rs_Rt_ADDR_SIMPLE),
    LDUMINALH_Rs_Rt_ADDR_SIMPLE(LDUMINALH_Rs_Rt_ADDR_SIMPLE),
    LDUMINAL_Rs_Rt_ADDR_SIMPLE(LDUMINAL_Rs_Rt_ADDR_SIMPLE),
    LDUMINA_Rs_Rt_ADDR_SIMPLE(LDUMINA_Rs_Rt_ADDR_SIMPLE),
    LDUMINB_Rs_Rt_ADDR_SIMPLE(LDUMINB_Rs_Rt_ADDR_SIMPLE),
    LDUMINH_Rs_Rt_ADDR_SIMPLE(LDUMINH_Rs_Rt_ADDR_SIMPLE),
    LDUMINLB_Rs_Rt_ADDR_SIMPLE(LDUMINLB_Rs_Rt_ADDR_SIMPLE),
    LDUMINLH_Rs_Rt_ADDR_SIMPLE(LDUMINLH_Rs_Rt_ADDR_SIMPLE),
    LDUMINL_Rs_Rt_ADDR_SIMPLE(LDUMINL_Rs_Rt_ADDR_SIMPLE),
    LDUMIN_Rs_Rt_ADDR_SIMPLE(LDUMIN_Rs_Rt_ADDR_SIMPLE),
    ST64BV0_Rs_Rt_LS64_ADDR_SIMPLE(ST64BV0_Rs_Rt_LS64_ADDR_SIMPLE),
    ST64BV_Rs_Rt_LS64_ADDR_SIMPLE(ST64BV_Rs_Rt_LS64_ADDR_SIMPLE),
    ST64B_Rt_LS64_ADDR_SIMPLE(ST64B_Rt_LS64_ADDR_SIMPLE),
    SWPAB_Rs_Rt_ADDR_SIMPLE(SWPAB_Rs_Rt_ADDR_SIMPLE),
    SWPAH_Rs_Rt_ADDR_SIMPLE(SWPAH_Rs_Rt_ADDR_SIMPLE),
    SWPALB_Rs_Rt_ADDR_SIMPLE(SWPALB_Rs_Rt_ADDR_SIMPLE),
    SWPALH_Rs_Rt_ADDR_SIMPLE(SWPALH_Rs_Rt_ADDR_SIMPLE),
    SWPAL_Rs_Rt_ADDR_SIMPLE(SWPAL_Rs_Rt_ADDR_SIMPLE),
    SWPA_Rs_Rt_ADDR_SIMPLE(SWPA_Rs_Rt_ADDR_SIMPLE),
    SWPB_Rs_Rt_ADDR_SIMPLE(SWPB_Rs_Rt_ADDR_SIMPLE),
    SWPH_Rs_Rt_ADDR_SIMPLE(SWPH_Rs_Rt_ADDR_SIMPLE),
    SWPLB_Rs_Rt_ADDR_SIMPLE(SWPLB_Rs_Rt_ADDR_SIMPLE),
    SWPLH_Rs_Rt_ADDR_SIMPLE(SWPLH_Rs_Rt_ADDR_SIMPLE),
    SWPL_Rs_Rt_ADDR_SIMPLE(SWPL_Rs_Rt_ADDR_SIMPLE),
    SWP_Rs_Rt_ADDR_SIMPLE(SWP_Rs_Rt_ADDR_SIMPLE),
}
#[derive(Debug, PartialEq, Eq, Copy, Clone)]
pub enum ASIMDPERM {
    TRN1_Vd_Vn_Vm(TRN1_Vd_Vn_Vm),
    TRN2_Vd_Vn_Vm(TRN2_Vd_Vn_Vm),
    UZP1_Vd_Vn_Vm(UZP1_Vd_Vn_Vm),
    UZP2_Vd_Vn_Vm(UZP2_Vd_Vn_Vm),
    ZIP1_Vd_Vn_Vm(ZIP1_Vd_Vn_Vm),
    ZIP2_Vd_Vn_Vm(ZIP2_Vd_Vn_Vm),
}
#[derive(Debug, PartialEq, Eq, Copy, Clone)]
pub enum LDSTNAPAIR_OFFS {
    LDNP_Ft_Ft2_ADDR_SIMM7(LDNP_Ft_Ft2_ADDR_SIMM7),
    LDNP_Rt_Rt2_ADDR_SIMM7(LDNP_Rt_Rt2_ADDR_SIMM7),
    STNP_Ft_Ft2_ADDR_SIMM7(STNP_Ft_Ft2_ADDR_SIMM7),
    STNP_Rt_Rt2_ADDR_SIMM7(STNP_Rt_Rt2_ADDR_SIMM7),
}
#[derive(Debug, PartialEq, Eq, Copy, Clone)]
pub enum CSSC {
    ABS_Rd_Rn(ABS_Rd_Rn),
    CNT_Rd_Rn(CNT_Rd_Rn),
    CTZ_Rd_Rn(CTZ_Rd_Rn),
    SMAX_Rd_Rn_CSSC_SIMM8(SMAX_Rd_Rn_CSSC_SIMM8),
    SMAX_Rd_Rn_Rm(SMAX_Rd_Rn_Rm),
    SMIN_Rd_Rn_CSSC_SIMM8(SMIN_Rd_Rn_CSSC_SIMM8),
    SMIN_Rd_Rn_Rm(SMIN_Rd_Rn_Rm),
    UMAX_Rd_Rn_CSSC_UIMM8(UMAX_Rd_Rn_CSSC_UIMM8),
    UMAX_Rd_Rn_Rm(UMAX_Rd_Rn_Rm),
    UMIN_Rd_Rn_CSSC_UIMM8(UMIN_Rd_Rn_CSSC_UIMM8),
    UMIN_Rd_Rn_Rm(UMIN_Rd_Rn_Rm),
}
#[derive(Debug, PartialEq, Eq, Copy, Clone)]
pub enum CRYPTOSHA2 {
    SHA1H_Fd_Fn(SHA1H_Fd_Fn),
    SHA1SU1_Vd_Vn(SHA1SU1_Vd_Vn),
    SHA256SU0_Vd_Vn(SHA256SU0_Vd_Vn),
    SHA512H2_Fd_Fn_Vm(SHA512H2_Fd_Fn_Vm),
    SHA512H_Fd_Fn_Vm(SHA512H_Fd_Fn_Vm),
    SHA512SU0_Vd_Vn(SHA512SU0_Vd_Vn),
    SHA512SU1_Vd_Vn_Vm(SHA512SU1_Vd_Vn_Vm),
}
#[derive(Debug, PartialEq, Eq, Copy, Clone)]
pub enum MOVEWIDE {
    MOVK_Rd_HALF(MOVK_Rd_HALF),
    MOVN_Rd_HALF(MOVN_Rd_HALF),
    MOVZ_Rd_HALF(MOVZ_Rd_HALF),
}
#[derive(Debug, PartialEq, Eq, Copy, Clone)]
pub enum ASISDLSOP {
    LD1R_LVt_AL_SIMD_ADDR_POST(LD1R_LVt_AL_SIMD_ADDR_POST),
    LD1_LEt_SIMD_ADDR_POST(LD1_LEt_SIMD_ADDR_POST),
    LD2R_LVt_AL_SIMD_ADDR_POST(LD2R_LVt_AL_SIMD_ADDR_POST),
    LD2_LEt_SIMD_ADDR_POST(LD2_LEt_SIMD_ADDR_POST),
    LD3R_LVt_AL_SIMD_ADDR_POST(LD3R_LVt_AL_SIMD_ADDR_POST),
    LD3_LEt_SIMD_ADDR_POST(LD3_LEt_SIMD_ADDR_POST),
    LD4R_LVt_AL_SIMD_ADDR_POST(LD4R_LVt_AL_SIMD_ADDR_POST),
    LD4_LEt_SIMD_ADDR_POST(LD4_LEt_SIMD_ADDR_POST),
    ST1_LEt_SIMD_ADDR_POST(ST1_LEt_SIMD_ADDR_POST),
    ST2_LEt_SIMD_ADDR_POST(ST2_LEt_SIMD_ADDR_POST),
    ST3_LEt_SIMD_ADDR_POST(ST3_LEt_SIMD_ADDR_POST),
    ST4_LEt_SIMD_ADDR_POST(ST4_LEt_SIMD_ADDR_POST),
}
#[derive(Debug, PartialEq, Eq, Copy, Clone)]
pub enum ASIMDALL {
    ADDV_Fd_Vn(ADDV_Fd_Vn),
    FMAXNMV_Fd_S_S_Vn_V_4S(FMAXNMV_Fd_S_S_Vn_V_4S),
    FMAXNMV_Fd_Vn(FMAXNMV_Fd_Vn),
    FMAXV_Fd_S_S_Vn_V_4S(FMAXV_Fd_S_S_Vn_V_4S),
    FMAXV_Fd_Vn(FMAXV_Fd_Vn),
    FMINNMV_Fd_S_S_Vn_V_4S(FMINNMV_Fd_S_S_Vn_V_4S),
    FMINNMV_Fd_Vn(FMINNMV_Fd_Vn),
    FMINV_Fd_S_S_Vn_V_4S(FMINV_Fd_S_S_Vn_V_4S),
    FMINV_Fd_Vn(FMINV_Fd_Vn),
    SADDLV_Fd_Vn(SADDLV_Fd_Vn),
    SMAXV_Fd_Vn(SMAXV_Fd_Vn),
    SMINV_Fd_Vn(SMINV_Fd_Vn),
    UADDLV_Fd_Vn(UADDLV_Fd_Vn),
    UMAXV_Fd_Vn(UMAXV_Fd_Vn),
    UMINV_Fd_Vn(UMINV_Fd_Vn),
}
#[derive(Debug, PartialEq, Eq, Copy, Clone)]
pub enum SVE_SHIFT_PRED {
    ASRD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_SHRIMM_PRED(ASRD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_SHRIMM_PRED),
    ASR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_SHRIMM_PRED(ASR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_SHRIMM_PRED),
    LSL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_SHLIMM_PRED(LSL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_SHLIMM_PRED),
    LSR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_SHRIMM_PRED(LSR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_SHRIMM_PRED),
    SQSHLU_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_SHLIMM_PRED(SQSHLU_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_SHLIMM_PRED),
    SQSHL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_SHLIMM_PRED(SQSHL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_SHLIMM_PRED),
    SRSHR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_SHRIMM_PRED(SRSHR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_SHRIMM_PRED),
    UQSHL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_SHLIMM_PRED(UQSHL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_SHLIMM_PRED),
    URSHR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_SHRIMM_PRED(URSHR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_SHRIMM_PRED),
}
#[derive(Debug, PartialEq, Eq, Copy, Clone)]
pub enum SVE_SHIFT_UNPRED {
    ASR_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED(ASR_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED),
    LSL_SVE_Zd_SVE_Zn_SVE_SHLIMM_UNPRED(LSL_SVE_Zd_SVE_Zn_SVE_SHLIMM_UNPRED),
    LSR_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED(LSR_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED),
}
#[derive(Debug, PartialEq, Eq, Copy, Clone)]
pub enum SME_LDR {
    LDR_SME_ZA_array_off4_SME_ADDR_RI_U4xVL(LDR_SME_ZA_array_off4_SME_ADDR_RI_U4xVL),
}
#[derive(Debug, PartialEq, Eq, Copy, Clone)]
pub enum SVE_SHIFT_TSZ_HSD {
    RSHRNB_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22(RSHRNB_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22),
    RSHRNT_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22(RSHRNT_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22),
    SHRNB_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22(SHRNB_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22),
    SHRNT_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22(SHRNT_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22),
    SQRSHRNB_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22(SQRSHRNB_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22),
    SQRSHRNT_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22(SQRSHRNT_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22),
    SQRSHRUNB_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22(SQRSHRUNB_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22),
    SQRSHRUNT_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22(SQRSHRUNT_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22),
    SQSHRNB_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22(SQSHRNB_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22),
    SQSHRNT_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22(SQSHRNT_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22),
    SQSHRUNB_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22(SQSHRUNB_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22),
    SQSHRUNT_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22(SQSHRUNT_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22),
    SSHLLB_SVE_Zd_SVE_Zn_SVE_SHLIMM_UNPRED_22(SSHLLB_SVE_Zd_SVE_Zn_SVE_SHLIMM_UNPRED_22),
    SSHLLT_SVE_Zd_SVE_Zn_SVE_SHLIMM_UNPRED_22(SSHLLT_SVE_Zd_SVE_Zn_SVE_SHLIMM_UNPRED_22),
    UQRSHRNB_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22(UQRSHRNB_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22),
    UQRSHRNT_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22(UQRSHRNT_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22),
    UQSHRNB_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22(UQSHRNB_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22),
    UQSHRNT_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22(UQSHRNT_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22),
    USHLLB_SVE_Zd_SVE_Zn_SVE_SHLIMM_UNPRED_22(USHLLB_SVE_Zd_SVE_Zn_SVE_SHLIMM_UNPRED_22),
    USHLLT_SVE_Zd_SVE_Zn_SVE_SHLIMM_UNPRED_22(USHLLT_SVE_Zd_SVE_Zn_SVE_SHLIMM_UNPRED_22),
}
#[derive(Debug, PartialEq, Eq, Copy, Clone)]
pub enum CRYPTOSHA3 {
    BCAX_Vd_Vn_Vm_Va(BCAX_Vd_Vn_Vm_Va),
    EOR3_Vd_Vn_Vm_Va(EOR3_Vd_Vn_Vm_Va),
    RAX1_Vd_Vn_Vm(RAX1_Vd_Vn_Vm),
    SHA1C_Fd_Fn_Vm(SHA1C_Fd_Fn_Vm),
    SHA1M_Fd_Fn_Vm(SHA1M_Fd_Fn_Vm),
    SHA1P_Fd_Fn_Vm(SHA1P_Fd_Fn_Vm),
    SHA1SU0_Vd_Vn_Vm(SHA1SU0_Vd_Vn_Vm),
    SHA256H2_Fd_Fn_Vm(SHA256H2_Fd_Fn_Vm),
    SHA256H_Fd_Fn_Vm(SHA256H_Fd_Fn_Vm),
    SHA256SU1_Vd_Vn_Vm(SHA256SU1_Vd_Vn_Vm),
    XAR_Vd_Vn_Vm_IMM(XAR_Vd_Vn_Vm_IMM),
}
#[derive(Debug, PartialEq, Eq, Copy, Clone)]
pub enum AARCH64_MISC {
    AXFLAG(AXFLAG),
    CPYEN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(CPYEN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn),
    CPYERN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(CPYERN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn),
    CPYERTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(CPYERTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn),
    CPYERTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(CPYERTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn),
    CPYERTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(CPYERTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn),
    CPYERT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(CPYERT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn),
    CPYETN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(CPYETN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn),
    CPYETRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(CPYETRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn),
    CPYETWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(CPYETWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn),
    CPYET_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(CPYET_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn),
    CPYEWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(CPYEWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn),
    CPYEWTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(CPYEWTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn),
    CPYEWTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(CPYEWTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn),
    CPYEWTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(CPYEWTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn),
    CPYEWT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(CPYEWT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn),
    CPYE_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(CPYE_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn),
    CPYFEN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(CPYFEN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn),
    CPYFERN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(CPYFERN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn),
    CPYFERTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(CPYFERTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn),
    CPYFERTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(CPYFERTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn),
    CPYFERTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(CPYFERTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn),
    CPYFERT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(CPYFERT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn),
    CPYFETN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(CPYFETN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn),
    CPYFETRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(CPYFETRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn),
    CPYFETWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(CPYFETWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn),
    CPYFET_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(CPYFET_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn),
    CPYFEWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(CPYFEWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn),
    CPYFEWTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(CPYFEWTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn),
    CPYFEWTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(CPYFEWTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn),
    CPYFEWTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(CPYFEWTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn),
    CPYFEWT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(CPYFEWT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn),
    CPYFE_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(CPYFE_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn),
    CPYFMN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(CPYFMN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn),
    CPYFMRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(CPYFMRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn),
    CPYFMRTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(CPYFMRTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn),
    CPYFMRTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(CPYFMRTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn),
    CPYFMRTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(CPYFMRTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn),
    CPYFMRT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(CPYFMRT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn),
    CPYFMTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(CPYFMTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn),
    CPYFMTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(CPYFMTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn),
    CPYFMTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(CPYFMTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn),
    CPYFMT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(CPYFMT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn),
    CPYFMWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(CPYFMWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn),
    CPYFMWTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(CPYFMWTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn),
    CPYFMWTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(CPYFMWTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn),
    CPYFMWTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(CPYFMWTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn),
    CPYFMWT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(CPYFMWT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn),
    CPYFM_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(CPYFM_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn),
    CPYFPN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(CPYFPN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn),
    CPYFPRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(CPYFPRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn),
    CPYFPRTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(CPYFPRTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn),
    CPYFPRTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(CPYFPRTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn),
    CPYFPRTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(CPYFPRTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn),
    CPYFPRT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(CPYFPRT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn),
    CPYFPTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(CPYFPTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn),
    CPYFPTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(CPYFPTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn),
    CPYFPTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(CPYFPTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn),
    CPYFPT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(CPYFPT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn),
    CPYFPWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(CPYFPWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn),
    CPYFPWTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(CPYFPWTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn),
    CPYFPWTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(CPYFPWTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn),
    CPYFPWTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(CPYFPWTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn),
    CPYFPWT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(CPYFPWT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn),
    CPYFP_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(CPYFP_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn),
    CPYMN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(CPYMN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn),
    CPYMRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(CPYMRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn),
    CPYMRTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(CPYMRTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn),
    CPYMRTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(CPYMRTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn),
    CPYMRTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(CPYMRTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn),
    CPYMRT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(CPYMRT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn),
    CPYMTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(CPYMTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn),
    CPYMTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(CPYMTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn),
    CPYMTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(CPYMTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn),
    CPYMT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(CPYMT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn),
    CPYMWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(CPYMWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn),
    CPYMWTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(CPYMWTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn),
    CPYMWTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(CPYMWTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn),
    CPYMWTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(CPYMWTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn),
    CPYMWT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(CPYMWT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn),
    CPYM_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(CPYM_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn),
    CPYPN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(CPYPN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn),
    CPYPRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(CPYPRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn),
    CPYPRTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(CPYPRTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn),
    CPYPRTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(CPYPRTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn),
    CPYPRTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(CPYPRTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn),
    CPYPRT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(CPYPRT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn),
    CPYPTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(CPYPTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn),
    CPYPTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(CPYPTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn),
    CPYPTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(CPYPTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn),
    CPYPT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(CPYPT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn),
    CPYPWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(CPYPWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn),
    CPYPWTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(CPYPWTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn),
    CPYPWTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(CPYPWTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn),
    CPYPWTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(CPYPWTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn),
    CPYPWT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(CPYPWT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn),
    CPYP_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(CPYP_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn),
    SETEN_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm(SETEN_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm),
    SETETN_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm(SETETN_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm),
    SETET_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm(SETET_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm),
    SETE_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm(SETE_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm),
    SETGEN_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm(SETGEN_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm),
    SETGETN_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm(SETGETN_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm),
    SETGET_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm(SETGET_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm),
    SETGE_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm(SETGE_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm),
    SETGMN_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm(SETGMN_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm),
    SETGMTN_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm(SETGMTN_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm),
    SETGMT_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm(SETGMT_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm),
    SETGM_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm(SETGM_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm),
    SETGPN_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm(SETGPN_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm),
    SETGPTN_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm(SETGPTN_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm),
    SETGPT_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm(SETGPT_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm),
    SETGP_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm(SETGP_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm),
    SETMN_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm(SETMN_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm),
    SETMTN_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm(SETMTN_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm),
    SETMT_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm(SETMT_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm),
    SETM_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm(SETM_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm),
    SETPN_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm(SETPN_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm),
    SETPTN_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm(SETPTN_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm),
    SETPT_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm(SETPT_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm),
    SETP_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm(SETP_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm),
    SMMLA_Vd_Vn_Vm(SMMLA_Vd_Vn_Vm),
    TCANCEL_TME_UIMM16(TCANCEL_TME_UIMM16),
    TCOMMIT(TCOMMIT),
    TSTART_Rd(TSTART_Rd),
    TTEST_Rd(TTEST_Rd),
    UMMLA_Vd_Vn_Vm(UMMLA_Vd_Vn_Vm),
    USDOT_Vd_Vn_Vm(USDOT_Vd_Vn_Vm),
    USMMLA_Vd_Vn_Vm(USMMLA_Vd_Vn_Vm),
    XAFLAG(XAFLAG),
}
#[derive(Debug, PartialEq, Eq, Copy, Clone)]
pub enum THE {
    RCWCASAL_Rs_Rt_ADDR_SIMPLE(RCWCASAL_Rs_Rt_ADDR_SIMPLE),
    RCWCASA_Rs_Rt_ADDR_SIMPLE(RCWCASA_Rs_Rt_ADDR_SIMPLE),
    RCWCASL_Rs_Rt_ADDR_SIMPLE(RCWCASL_Rs_Rt_ADDR_SIMPLE),
    RCWCASPAL_Rs_PAIRREG_Rt_PAIRREG_ADDR_SIMPLE(RCWCASPAL_Rs_PAIRREG_Rt_PAIRREG_ADDR_SIMPLE),
    RCWCASPA_Rs_PAIRREG_Rt_PAIRREG_ADDR_SIMPLE(RCWCASPA_Rs_PAIRREG_Rt_PAIRREG_ADDR_SIMPLE),
    RCWCASPL_Rs_PAIRREG_Rt_PAIRREG_ADDR_SIMPLE(RCWCASPL_Rs_PAIRREG_Rt_PAIRREG_ADDR_SIMPLE),
    RCWCASP_Rs_PAIRREG_Rt_PAIRREG_ADDR_SIMPLE(RCWCASP_Rs_PAIRREG_Rt_PAIRREG_ADDR_SIMPLE),
    RCWCAS_Rs_Rt_ADDR_SIMPLE(RCWCAS_Rs_Rt_ADDR_SIMPLE),
    RCWCLRAL_Rs_Rt_ADDR_SIMPLE(RCWCLRAL_Rs_Rt_ADDR_SIMPLE),
    RCWCLRA_Rs_Rt_ADDR_SIMPLE(RCWCLRA_Rs_Rt_ADDR_SIMPLE),
    RCWCLRL_Rs_Rt_ADDR_SIMPLE(RCWCLRL_Rs_Rt_ADDR_SIMPLE),
    RCWCLRPAL_Rt_Rs_ADDR_SIMPLE(RCWCLRPAL_Rt_Rs_ADDR_SIMPLE),
    RCWCLRPA_Rt_Rs_ADDR_SIMPLE(RCWCLRPA_Rt_Rs_ADDR_SIMPLE),
    RCWCLRPL_Rt_Rs_ADDR_SIMPLE(RCWCLRPL_Rt_Rs_ADDR_SIMPLE),
    RCWCLRP_Rt_Rs_ADDR_SIMPLE(RCWCLRP_Rt_Rs_ADDR_SIMPLE),
    RCWCLR_Rs_Rt_ADDR_SIMPLE(RCWCLR_Rs_Rt_ADDR_SIMPLE),
    RCWSCASAL_Rs_Rt_ADDR_SIMPLE(RCWSCASAL_Rs_Rt_ADDR_SIMPLE),
    RCWSCASA_Rs_Rt_ADDR_SIMPLE(RCWSCASA_Rs_Rt_ADDR_SIMPLE),
    RCWSCASL_Rs_Rt_ADDR_SIMPLE(RCWSCASL_Rs_Rt_ADDR_SIMPLE),
    RCWSCASPAL_Rs_PAIRREG_Rt_PAIRREG_ADDR_SIMPLE(RCWSCASPAL_Rs_PAIRREG_Rt_PAIRREG_ADDR_SIMPLE),
    RCWSCASPA_Rs_PAIRREG_Rt_PAIRREG_ADDR_SIMPLE(RCWSCASPA_Rs_PAIRREG_Rt_PAIRREG_ADDR_SIMPLE),
    RCWSCASPL_Rs_PAIRREG_Rt_PAIRREG_ADDR_SIMPLE(RCWSCASPL_Rs_PAIRREG_Rt_PAIRREG_ADDR_SIMPLE),
    RCWSCASP_Rs_PAIRREG_Rt_PAIRREG_ADDR_SIMPLE(RCWSCASP_Rs_PAIRREG_Rt_PAIRREG_ADDR_SIMPLE),
    RCWSCAS_Rs_Rt_ADDR_SIMPLE(RCWSCAS_Rs_Rt_ADDR_SIMPLE),
    RCWSCLRAL_Rs_Rt_ADDR_SIMPLE(RCWSCLRAL_Rs_Rt_ADDR_SIMPLE),
    RCWSCLRA_Rs_Rt_ADDR_SIMPLE(RCWSCLRA_Rs_Rt_ADDR_SIMPLE),
    RCWSCLRL_Rs_Rt_ADDR_SIMPLE(RCWSCLRL_Rs_Rt_ADDR_SIMPLE),
    RCWSCLRPAL_Rt_Rs_ADDR_SIMPLE(RCWSCLRPAL_Rt_Rs_ADDR_SIMPLE),
    RCWSCLRPA_Rt_Rs_ADDR_SIMPLE(RCWSCLRPA_Rt_Rs_ADDR_SIMPLE),
    RCWSCLRPL_Rt_Rs_ADDR_SIMPLE(RCWSCLRPL_Rt_Rs_ADDR_SIMPLE),
    RCWSCLRP_Rt_Rs_ADDR_SIMPLE(RCWSCLRP_Rt_Rs_ADDR_SIMPLE),
    RCWSCLR_Rs_Rt_ADDR_SIMPLE(RCWSCLR_Rs_Rt_ADDR_SIMPLE),
    RCWSETAL_Rs_Rt_ADDR_SIMPLE(RCWSETAL_Rs_Rt_ADDR_SIMPLE),
    RCWSETA_Rs_Rt_ADDR_SIMPLE(RCWSETA_Rs_Rt_ADDR_SIMPLE),
    RCWSETL_Rs_Rt_ADDR_SIMPLE(RCWSETL_Rs_Rt_ADDR_SIMPLE),
    RCWSETPAL_Rt_Rs_ADDR_SIMPLE(RCWSETPAL_Rt_Rs_ADDR_SIMPLE),
    RCWSETPA_Rt_Rs_ADDR_SIMPLE(RCWSETPA_Rt_Rs_ADDR_SIMPLE),
    RCWSETPL_Rt_Rs_ADDR_SIMPLE(RCWSETPL_Rt_Rs_ADDR_SIMPLE),
    RCWSETP_Rt_Rs_ADDR_SIMPLE(RCWSETP_Rt_Rs_ADDR_SIMPLE),
    RCWSET_Rs_Rt_ADDR_SIMPLE(RCWSET_Rs_Rt_ADDR_SIMPLE),
    RCWSSETAL_Rs_Rt_ADDR_SIMPLE(RCWSSETAL_Rs_Rt_ADDR_SIMPLE),
    RCWSSETA_Rs_Rt_ADDR_SIMPLE(RCWSSETA_Rs_Rt_ADDR_SIMPLE),
    RCWSSETL_Rs_Rt_ADDR_SIMPLE(RCWSSETL_Rs_Rt_ADDR_SIMPLE),
    RCWSSETPAL_Rt_Rs_ADDR_SIMPLE(RCWSSETPAL_Rt_Rs_ADDR_SIMPLE),
    RCWSSETPA_Rt_Rs_ADDR_SIMPLE(RCWSSETPA_Rt_Rs_ADDR_SIMPLE),
    RCWSSETPL_Rt_Rs_ADDR_SIMPLE(RCWSSETPL_Rt_Rs_ADDR_SIMPLE),
    RCWSSETP_Rt_Rs_ADDR_SIMPLE(RCWSSETP_Rt_Rs_ADDR_SIMPLE),
    RCWSSET_Rs_Rt_ADDR_SIMPLE(RCWSSET_Rs_Rt_ADDR_SIMPLE),
    RCWSSWPAL_Rs_Rt_ADDR_SIMPLE(RCWSSWPAL_Rs_Rt_ADDR_SIMPLE),
    RCWSSWPA_Rs_Rt_ADDR_SIMPLE(RCWSSWPA_Rs_Rt_ADDR_SIMPLE),
    RCWSSWPL_Rs_Rt_ADDR_SIMPLE(RCWSSWPL_Rs_Rt_ADDR_SIMPLE),
    RCWSSWPPAL_Rt_Rs_ADDR_SIMPLE(RCWSSWPPAL_Rt_Rs_ADDR_SIMPLE),
    RCWSSWPPA_Rt_Rs_ADDR_SIMPLE(RCWSSWPPA_Rt_Rs_ADDR_SIMPLE),
    RCWSSWPPL_Rt_Rs_ADDR_SIMPLE(RCWSSWPPL_Rt_Rs_ADDR_SIMPLE),
    RCWSSWPP_Rt_Rs_ADDR_SIMPLE(RCWSSWPP_Rt_Rs_ADDR_SIMPLE),
    RCWSSWP_Rs_Rt_ADDR_SIMPLE(RCWSSWP_Rs_Rt_ADDR_SIMPLE),
    RCWSWPAL_Rs_Rt_ADDR_SIMPLE(RCWSWPAL_Rs_Rt_ADDR_SIMPLE),
    RCWSWPA_Rs_Rt_ADDR_SIMPLE(RCWSWPA_Rs_Rt_ADDR_SIMPLE),
    RCWSWPL_Rs_Rt_ADDR_SIMPLE(RCWSWPL_Rs_Rt_ADDR_SIMPLE),
    RCWSWPPAL_Rt_Rs_ADDR_SIMPLE(RCWSWPPAL_Rt_Rs_ADDR_SIMPLE),
    RCWSWPPA_Rt_Rs_ADDR_SIMPLE(RCWSWPPA_Rt_Rs_ADDR_SIMPLE),
    RCWSWPPL_Rt_Rs_ADDR_SIMPLE(RCWSWPPL_Rt_Rs_ADDR_SIMPLE),
    RCWSWPP_Rt_Rs_ADDR_SIMPLE(RCWSWPP_Rt_Rs_ADDR_SIMPLE),
    RCWSWP_Rs_Rt_ADDR_SIMPLE(RCWSWP_Rs_Rt_ADDR_SIMPLE),
}
#[derive(Debug, PartialEq, Eq, Copy, Clone)]
pub enum SVE_SIZE_BH {
    MATCH_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16(MATCH_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16),
    NMATCH_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16(NMATCH_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16),
}
#[derive(Debug, PartialEq, Eq, Copy, Clone)]
pub enum SVE_CPY {
    CPY_SVE_Zd_SVE_Pg4_16_SVE_ASIMM(CPY_SVE_Zd_SVE_Pg4_16_SVE_ASIMM),
}
#[derive(Debug, PartialEq, Eq, Copy, Clone)]
pub enum SME2_MOV {
    MOVA_SME_ZA_array_off3_0_SME_Znx2(MOVA_SME_ZA_array_off3_0_SME_Znx2),
    MOVA_SME_ZA_array_off3_0_SME_Znx4(MOVA_SME_ZA_array_off3_0_SME_Znx4),
    MOVA_SME_Zdnx2_SME_ZA_array_off3_5(MOVA_SME_Zdnx2_SME_ZA_array_off3_5),
    MOVA_SME_Zdnx4_SME_ZA_array_off3_5(MOVA_SME_Zdnx4_SME_ZA_array_off3_5),
    MOV_SME_ZA_array_off3_0_SME_Znx2(MOV_SME_ZA_array_off3_0_SME_Znx2),
    MOV_SME_ZA_array_off3_0_SME_Znx4(MOV_SME_ZA_array_off3_0_SME_Znx4),
    MOV_SME_Zdnx2_SME_ZA_array_off3_5(MOV_SME_Zdnx2_SME_ZA_array_off3_5),
    MOV_SME_Zdnx4_SME_ZA_array_off3_5(MOV_SME_Zdnx4_SME_ZA_array_off3_5),
}
#[derive(Debug, PartialEq, Eq, Copy, Clone)]
pub enum LOG_SHIFT {
    ANDS_Rd_Rn_Rm_SFT(ANDS_Rd_Rn_Rm_SFT),
    AND_Rd_Rn_Rm_SFT(AND_Rd_Rn_Rm_SFT),
    BICS_Rd_Rn_Rm_SFT(BICS_Rd_Rn_Rm_SFT),
    BIC_Rd_Rn_Rm_SFT(BIC_Rd_Rn_Rm_SFT),
    EON_Rd_Rn_Rm_SFT(EON_Rd_Rn_Rm_SFT),
    EOR_Rd_Rn_Rm_SFT(EOR_Rd_Rn_Rm_SFT),
    ORN_Rd_Rn_Rm_SFT(ORN_Rd_Rn_Rm_SFT),
    ORR_Rd_Rn_Rm_SFT(ORR_Rd_Rn_Rm_SFT),
}
#[derive(Debug, PartialEq, Eq, Copy, Clone)]
pub enum SME_PSEL {
    PSEL_SVE_PNd_SVE_PNg4_10_SME_PnT_Wm_imm(PSEL_SVE_PNd_SVE_PNg4_10_SME_PnT_Wm_imm),
    PSEL_SVE_Pd_SVE_Pg4_10_SME_PnT_Wm_imm(PSEL_SVE_Pd_SVE_Pg4_10_SME_PnT_Wm_imm),
}
#[derive(Debug, PartialEq, Eq, Copy, Clone)]
pub enum SME_SIZE_22 {
    ADD_SME_Zdnx2_SME_Zdnx2_SME_Zm(ADD_SME_Zdnx2_SME_Zdnx2_SME_Zm),
    ADD_SME_Zdnx4_SME_Zdnx4_SME_Zm(ADD_SME_Zdnx4_SME_Zdnx4_SME_Zm),
    CNTP_Rd_SME_PNn_SME_VLxN_10(CNTP_Rd_SME_PNn_SME_VLxN_10),
    MOVA_SME_ZA_HV_idx_destxN_SME_Znx2(MOVA_SME_ZA_HV_idx_destxN_SME_Znx2),
    MOVA_SME_ZA_HV_idx_destxN_SME_Znx4(MOVA_SME_ZA_HV_idx_destxN_SME_Znx4),
    MOVA_SME_Zdnx2_SME_ZA_HV_idx_srcxN(MOVA_SME_Zdnx2_SME_ZA_HV_idx_srcxN),
    MOVA_SME_Zdnx4_SME_ZA_HV_idx_srcxN(MOVA_SME_Zdnx4_SME_ZA_HV_idx_srcxN),
    MOV_SME_ZA_HV_idx_destxN_SME_Znx2(MOV_SME_ZA_HV_idx_destxN_SME_Znx2),
    MOV_SME_ZA_HV_idx_destxN_SME_Znx4(MOV_SME_ZA_HV_idx_destxN_SME_Znx4),
    MOV_SME_Zdnx2_SME_ZA_HV_idx_srcxN(MOV_SME_Zdnx2_SME_ZA_HV_idx_srcxN),
    MOV_SME_Zdnx4_SME_ZA_HV_idx_srcxN(MOV_SME_Zdnx4_SME_ZA_HV_idx_srcxN),
    PEXT_SME_PdxN_SME_PNn3_INDEX1(PEXT_SME_PdxN_SME_PNn3_INDEX1),
    PEXT_SVE_Pd_SME_PNn3_INDEX2(PEXT_SVE_Pd_SME_PNn3_INDEX2),
    PTRUE_SME_PNd3(PTRUE_SME_PNd3),
    SCLAMP_SME_Zdnx2_SVE_Zn_SVE_Zm_16(SCLAMP_SME_Zdnx2_SVE_Zn_SVE_Zm_16),
    SCLAMP_SME_Zdnx4_SVE_Zn_SVE_Zm_16(SCLAMP_SME_Zdnx4_SVE_Zn_SVE_Zm_16),
    SEL_SME_Zdnx2_SME_PNg3_SME_Znx2_SME_Zmx2(SEL_SME_Zdnx2_SME_PNg3_SME_Znx2_SME_Zmx2),
    SEL_SME_Zdnx4_SME_PNg3_SME_Znx4_SME_Zmx4(SEL_SME_Zdnx4_SME_PNg3_SME_Znx4_SME_Zmx4),
    SMAX_SME_Zdnx2_SME_Zdnx2_SME_Zm(SMAX_SME_Zdnx2_SME_Zdnx2_SME_Zm),
    SMAX_SME_Zdnx2_SME_Zdnx2_SME_Zmx2(SMAX_SME_Zdnx2_SME_Zdnx2_SME_Zmx2),
    SMAX_SME_Zdnx4_SME_Zdnx4_SME_Zm(SMAX_SME_Zdnx4_SME_Zdnx4_SME_Zm),
    SMAX_SME_Zdnx4_SME_Zdnx4_SME_Zmx4(SMAX_SME_Zdnx4_SME_Zdnx4_SME_Zmx4),
    SMIN_SME_Zdnx2_SME_Zdnx2_SME_Zm(SMIN_SME_Zdnx2_SME_Zdnx2_SME_Zm),
    SMIN_SME_Zdnx2_SME_Zdnx2_SME_Zmx2(SMIN_SME_Zdnx2_SME_Zdnx2_SME_Zmx2),
    SMIN_SME_Zdnx4_SME_Zdnx4_SME_Zm(SMIN_SME_Zdnx4_SME_Zdnx4_SME_Zm),
    SMIN_SME_Zdnx4_SME_Zdnx4_SME_Zmx4(SMIN_SME_Zdnx4_SME_Zdnx4_SME_Zmx4),
    SQDMULH_SME_Zdnx2_SME_Zdnx2_SME_Zm(SQDMULH_SME_Zdnx2_SME_Zdnx2_SME_Zm),
    SQDMULH_SME_Zdnx2_SME_Zdnx2_SME_Zmx2(SQDMULH_SME_Zdnx2_SME_Zdnx2_SME_Zmx2),
    SQDMULH_SME_Zdnx4_SME_Zdnx4_SME_Zm(SQDMULH_SME_Zdnx4_SME_Zdnx4_SME_Zm),
    SQDMULH_SME_Zdnx4_SME_Zdnx4_SME_Zmx4(SQDMULH_SME_Zdnx4_SME_Zdnx4_SME_Zmx4),
    SRSHL_SME_Zdnx2_SME_Zdnx2_SME_Zm(SRSHL_SME_Zdnx2_SME_Zdnx2_SME_Zm),
    SRSHL_SME_Zdnx2_SME_Zdnx2_SME_Zmx2(SRSHL_SME_Zdnx2_SME_Zdnx2_SME_Zmx2),
    SRSHL_SME_Zdnx4_SME_Zdnx4_SME_Zm(SRSHL_SME_Zdnx4_SME_Zdnx4_SME_Zm),
    SRSHL_SME_Zdnx4_SME_Zdnx4_SME_Zmx4(SRSHL_SME_Zdnx4_SME_Zdnx4_SME_Zmx4),
    UCLAMP_SME_Zdnx2_SVE_Zn_SVE_Zm_16(UCLAMP_SME_Zdnx2_SVE_Zn_SVE_Zm_16),
    UCLAMP_SME_Zdnx4_SVE_Zn_SVE_Zm_16(UCLAMP_SME_Zdnx4_SVE_Zn_SVE_Zm_16),
    UMAX_SME_Zdnx2_SME_Zdnx2_SME_Zm(UMAX_SME_Zdnx2_SME_Zdnx2_SME_Zm),
    UMAX_SME_Zdnx2_SME_Zdnx2_SME_Zmx2(UMAX_SME_Zdnx2_SME_Zdnx2_SME_Zmx2),
    UMAX_SME_Zdnx4_SME_Zdnx4_SME_Zm(UMAX_SME_Zdnx4_SME_Zdnx4_SME_Zm),
    UMAX_SME_Zdnx4_SME_Zdnx4_SME_Zmx4(UMAX_SME_Zdnx4_SME_Zdnx4_SME_Zmx4),
    UMIN_SME_Zdnx2_SME_Zdnx2_SME_Zm(UMIN_SME_Zdnx2_SME_Zdnx2_SME_Zm),
    UMIN_SME_Zdnx2_SME_Zdnx2_SME_Zmx2(UMIN_SME_Zdnx2_SME_Zdnx2_SME_Zmx2),
    UMIN_SME_Zdnx4_SME_Zdnx4_SME_Zm(UMIN_SME_Zdnx4_SME_Zdnx4_SME_Zm),
    UMIN_SME_Zdnx4_SME_Zdnx4_SME_Zmx4(UMIN_SME_Zdnx4_SME_Zdnx4_SME_Zmx4),
    URSHL_SME_Zdnx2_SME_Zdnx2_SME_Zm(URSHL_SME_Zdnx2_SME_Zdnx2_SME_Zm),
    URSHL_SME_Zdnx2_SME_Zdnx2_SME_Zmx2(URSHL_SME_Zdnx2_SME_Zdnx2_SME_Zmx2),
    URSHL_SME_Zdnx4_SME_Zdnx4_SME_Zm(URSHL_SME_Zdnx4_SME_Zdnx4_SME_Zm),
    URSHL_SME_Zdnx4_SME_Zdnx4_SME_Zmx4(URSHL_SME_Zdnx4_SME_Zdnx4_SME_Zmx4),
    UZP_SME_Zdnx2_SVE_Zn_SVE_Zm_16(UZP_SME_Zdnx2_SVE_Zn_SVE_Zm_16),
    UZP_SME_Zdnx4_SME_Znx4(UZP_SME_Zdnx4_SME_Znx4),
    WHILEGE_SME_PNd3_Rn_Rm_SME_VLxN_13(WHILEGE_SME_PNd3_Rn_Rm_SME_VLxN_13),
    WHILEGE_SME_Pdx2_Rn_Rm(WHILEGE_SME_Pdx2_Rn_Rm),
    WHILEGT_SME_PNd3_Rn_Rm_SME_VLxN_13(WHILEGT_SME_PNd3_Rn_Rm_SME_VLxN_13),
    WHILEGT_SME_Pdx2_Rn_Rm(WHILEGT_SME_Pdx2_Rn_Rm),
    WHILEHI_SME_PNd3_Rn_Rm_SME_VLxN_13(WHILEHI_SME_PNd3_Rn_Rm_SME_VLxN_13),
    WHILEHI_SME_Pdx2_Rn_Rm(WHILEHI_SME_Pdx2_Rn_Rm),
    WHILEHS_SME_PNd3_Rn_Rm_SME_VLxN_13(WHILEHS_SME_PNd3_Rn_Rm_SME_VLxN_13),
    WHILEHS_SME_Pdx2_Rn_Rm(WHILEHS_SME_Pdx2_Rn_Rm),
    WHILELE_SME_PNd3_Rn_Rm_SME_VLxN_13(WHILELE_SME_PNd3_Rn_Rm_SME_VLxN_13),
    WHILELE_SME_Pdx2_Rn_Rm(WHILELE_SME_Pdx2_Rn_Rm),
    WHILELO_SME_PNd3_Rn_Rm_SME_VLxN_13(WHILELO_SME_PNd3_Rn_Rm_SME_VLxN_13),
    WHILELO_SME_Pdx2_Rn_Rm(WHILELO_SME_Pdx2_Rn_Rm),
    WHILELS_SME_PNd3_Rn_Rm_SME_VLxN_13(WHILELS_SME_PNd3_Rn_Rm_SME_VLxN_13),
    WHILELS_SME_Pdx2_Rn_Rm(WHILELS_SME_Pdx2_Rn_Rm),
    WHILELT_SME_PNd3_Rn_Rm_SME_VLxN_13(WHILELT_SME_PNd3_Rn_Rm_SME_VLxN_13),
    WHILELT_SME_Pdx2_Rn_Rm(WHILELT_SME_Pdx2_Rn_Rm),
    ZIP_SME_Zdnx2_SVE_Zn_SVE_Zm_16(ZIP_SME_Zdnx2_SVE_Zn_SVE_Zm_16),
    ZIP_SME_Zdnx4_SME_Znx4(ZIP_SME_Zdnx4_SME_Znx4),
}
#[derive(Debug, PartialEq, Eq, Copy, Clone)]
pub enum SME_STOP {
    SMSTOP(SMSTOP),
    SMSTOP_SME_SM_ZA(SMSTOP_SME_SM_ZA),
}
#[derive(Debug, PartialEq, Eq, Copy, Clone)]
pub enum BFLOAT16 {
    BFCVTN2_Vd_Vn(BFCVTN2_Vd_Vn),
    BFCVTN_Vd_Vn(BFCVTN_Vd_Vn),
    BFCVT_Fd_Fn(BFCVT_Fd_Fn),
    BFDOT_Vd_Vn_Vm(BFDOT_Vd_Vn_Vm),
    BFMLALB_Vd_Vn_Em16(BFMLALB_Vd_Vn_Em16),
    BFMLALB_Vd_Vn_Vm(BFMLALB_Vd_Vn_Vm),
    BFMLALT_Vd_Vn_Em16(BFMLALT_Vd_Vn_Em16),
    BFMLALT_Vd_Vn_Vm(BFMLALT_Vd_Vn_Vm),
    BFMMLA_Vd_Vn_Vm(BFMMLA_Vd_Vn_Vm),
}
#[derive(Debug, PartialEq, Eq, Copy, Clone)]
pub enum ADDSUB_EXT {
    ADDS_Rd_Rn_SP_Rm_EXT(ADDS_Rd_Rn_SP_Rm_EXT),
    ADD_Rd_SP_Rn_SP_Rm_EXT(ADD_Rd_SP_Rn_SP_Rm_EXT),
    SUBS_Rd_Rn_SP_Rm_EXT(SUBS_Rd_Rn_SP_Rm_EXT),
    SUB_Rd_SP_Rn_SP_Rm_EXT(SUB_Rd_SP_Rn_SP_Rm_EXT),
}
#[derive(Debug, PartialEq, Eq, Copy, Clone)]
pub enum ASISDLSO {
    LD1R_LVt_AL_SIMD_ADDR_SIMPLE(LD1R_LVt_AL_SIMD_ADDR_SIMPLE),
    LD1_LEt_SIMD_ADDR_SIMPLE(LD1_LEt_SIMD_ADDR_SIMPLE),
    LD2R_LVt_AL_SIMD_ADDR_SIMPLE(LD2R_LVt_AL_SIMD_ADDR_SIMPLE),
    LD2_LEt_SIMD_ADDR_SIMPLE(LD2_LEt_SIMD_ADDR_SIMPLE),
    LD3R_LVt_AL_SIMD_ADDR_SIMPLE(LD3R_LVt_AL_SIMD_ADDR_SIMPLE),
    LD3_LEt_SIMD_ADDR_SIMPLE(LD3_LEt_SIMD_ADDR_SIMPLE),
    LD4R_LVt_AL_SIMD_ADDR_SIMPLE(LD4R_LVt_AL_SIMD_ADDR_SIMPLE),
    LD4_LEt_SIMD_ADDR_SIMPLE(LD4_LEt_SIMD_ADDR_SIMPLE),
    ST1_LEt_SIMD_ADDR_SIMPLE(ST1_LEt_SIMD_ADDR_SIMPLE),
    ST2_LEt_SIMD_ADDR_SIMPLE(ST2_LEt_SIMD_ADDR_SIMPLE),
    ST3_LEt_SIMD_ADDR_SIMPLE(ST3_LEt_SIMD_ADDR_SIMPLE),
    ST4_LEt_SIMD_ADDR_SIMPLE(ST4_LEt_SIMD_ADDR_SIMPLE),
}
#[derive(Debug, PartialEq, Eq, Copy, Clone)]
pub enum LDSTPAIR_OFF {
    LDPSW_Rt_Rt2_ADDR_SIMM7(LDPSW_Rt_Rt2_ADDR_SIMM7),
    LDP_Ft_Ft2_ADDR_SIMM7(LDP_Ft_Ft2_ADDR_SIMM7),
    LDP_Rt_Rt2_ADDR_SIMM7(LDP_Rt_Rt2_ADDR_SIMM7),
    STGP_Rt_Rt2_ADDR_SIMM11(STGP_Rt_Rt2_ADDR_SIMM11),
    STP_Ft_Ft2_ADDR_SIMM7(STP_Ft_Ft2_ADDR_SIMM7),
    STP_Rt_Rt2_ADDR_SIMM7(STP_Rt_Rt2_ADDR_SIMM7),
}
#[derive(Debug, PartialEq, Eq, Copy, Clone)]
pub enum FLOATDP2 {
    FADD_Fd_Fn_Fm(FADD_Fd_Fn_Fm),
    FADD_Fd_S_S_Fn_S_S_Fm_S_S(FADD_Fd_S_S_Fn_S_S_Fm_S_S),
    FDIV_Fd_Fn_Fm(FDIV_Fd_Fn_Fm),
    FDIV_Fd_S_S_Fn_S_S_Fm_S_S(FDIV_Fd_S_S_Fn_S_S_Fm_S_S),
    FMAXNM_Fd_Fn_Fm(FMAXNM_Fd_Fn_Fm),
    FMAXNM_Fd_S_S_Fn_S_S_Fm_S_S(FMAXNM_Fd_S_S_Fn_S_S_Fm_S_S),
    FMAX_Fd_Fn_Fm(FMAX_Fd_Fn_Fm),
    FMAX_Fd_S_S_Fn_S_S_Fm_S_S(FMAX_Fd_S_S_Fn_S_S_Fm_S_S),
    FMINNM_Fd_Fn_Fm(FMINNM_Fd_Fn_Fm),
    FMINNM_Fd_S_S_Fn_S_S_Fm_S_S(FMINNM_Fd_S_S_Fn_S_S_Fm_S_S),
    FMIN_Fd_Fn_Fm(FMIN_Fd_Fn_Fm),
    FMIN_Fd_S_S_Fn_S_S_Fm_S_S(FMIN_Fd_S_S_Fn_S_S_Fm_S_S),
    FMUL_Fd_Fn_Fm(FMUL_Fd_Fn_Fm),
    FMUL_Fd_S_S_Fn_S_S_Fm_S_S(FMUL_Fd_S_S_Fn_S_S_Fm_S_S),
    FNMUL_Fd_Fn_Fm(FNMUL_Fd_Fn_Fm),
    FNMUL_Fd_S_S_Fn_S_S_Fm_S_S(FNMUL_Fd_S_S_Fn_S_S_Fm_S_S),
    FSUB_Fd_Fn_Fm(FSUB_Fd_Fn_Fm),
    FSUB_Fd_S_S_Fn_S_S_Fm_S_S(FSUB_Fd_S_S_Fn_S_S_Fm_S_S),
}
#[derive(Debug, PartialEq, Eq, Copy, Clone)]
pub enum ASIMDMISC {
    ABS_Vd_Vn(ABS_Vd_Vn),
    CLS_Vd_Vn(CLS_Vd_Vn),
    CLZ_Vd_Vn(CLZ_Vd_Vn),
    CMEQ_Vd_Vn_IMM0(CMEQ_Vd_Vn_IMM0),
    CMGE_Vd_Vn_IMM0(CMGE_Vd_Vn_IMM0),
    CMGT_Vd_Vn_IMM0(CMGT_Vd_Vn_IMM0),
    CMLE_Vd_Vn_IMM0(CMLE_Vd_Vn_IMM0),
    CMLT_Vd_Vn_IMM0(CMLT_Vd_Vn_IMM0),
    CNT_Vd_Vn(CNT_Vd_Vn),
    FABS_Vd_V_4H_Vn_V_4H(FABS_Vd_V_4H_Vn_V_4H),
    FABS_Vd_Vn(FABS_Vd_Vn),
    FCMEQ_Vd_V_4H_Vn_V_4H_FPIMM0(FCMEQ_Vd_V_4H_Vn_V_4H_FPIMM0),
    FCMEQ_Vd_Vn_FPIMM0(FCMEQ_Vd_Vn_FPIMM0),
    FCMGE_Vd_V_4H_Vn_V_4H_FPIMM0(FCMGE_Vd_V_4H_Vn_V_4H_FPIMM0),
    FCMGE_Vd_Vn_FPIMM0(FCMGE_Vd_Vn_FPIMM0),
    FCMGT_Vd_V_4H_Vn_V_4H_FPIMM0(FCMGT_Vd_V_4H_Vn_V_4H_FPIMM0),
    FCMGT_Vd_Vn_FPIMM0(FCMGT_Vd_Vn_FPIMM0),
    FCMLE_Vd_V_4H_Vn_V_4H_FPIMM0(FCMLE_Vd_V_4H_Vn_V_4H_FPIMM0),
    FCMLE_Vd_Vn_FPIMM0(FCMLE_Vd_Vn_FPIMM0),
    FCMLT_Vd_V_4H_Vn_V_4H_FPIMM0(FCMLT_Vd_V_4H_Vn_V_4H_FPIMM0),
    FCMLT_Vd_Vn_FPIMM0(FCMLT_Vd_Vn_FPIMM0),
    FCVTAS_Vd_V_4H_Vn_V_4H(FCVTAS_Vd_V_4H_Vn_V_4H),
    FCVTAS_Vd_Vn(FCVTAS_Vd_Vn),
    FCVTAU_Vd_V_4H_Vn_V_4H(FCVTAU_Vd_V_4H_Vn_V_4H),
    FCVTAU_Vd_Vn(FCVTAU_Vd_Vn),
    FCVTL2_Vd_Vn(FCVTL2_Vd_Vn),
    FCVTL_Vd_Vn(FCVTL_Vd_Vn),
    FCVTMS_Vd_V_4H_Vn_V_4H(FCVTMS_Vd_V_4H_Vn_V_4H),
    FCVTMS_Vd_Vn(FCVTMS_Vd_Vn),
    FCVTMU_Vd_V_4H_Vn_V_4H(FCVTMU_Vd_V_4H_Vn_V_4H),
    FCVTMU_Vd_Vn(FCVTMU_Vd_Vn),
    FCVTN2_Vd_Vn(FCVTN2_Vd_Vn),
    FCVTNS_Vd_V_4H_Vn_V_4H(FCVTNS_Vd_V_4H_Vn_V_4H),
    FCVTNS_Vd_Vn(FCVTNS_Vd_Vn),
    FCVTNU_Vd_V_4H_Vn_V_4H(FCVTNU_Vd_V_4H_Vn_V_4H),
    FCVTNU_Vd_Vn(FCVTNU_Vd_Vn),
    FCVTN_Vd_Vn(FCVTN_Vd_Vn),
    FCVTPS_Vd_V_4H_Vn_V_4H(FCVTPS_Vd_V_4H_Vn_V_4H),
    FCVTPS_Vd_Vn(FCVTPS_Vd_Vn),
    FCVTPU_Vd_V_4H_Vn_V_4H(FCVTPU_Vd_V_4H_Vn_V_4H),
    FCVTPU_Vd_Vn(FCVTPU_Vd_Vn),
    FCVTXN2_Vd_Vn(FCVTXN2_Vd_Vn),
    FCVTXN_Vd_Vn(FCVTXN_Vd_Vn),
    FCVTZS_Vd_V_4H_Vn_V_4H(FCVTZS_Vd_V_4H_Vn_V_4H),
    FCVTZS_Vd_Vn(FCVTZS_Vd_Vn),
    FCVTZU_Vd_V_4H_Vn_V_4H(FCVTZU_Vd_V_4H_Vn_V_4H),
    FCVTZU_Vd_Vn(FCVTZU_Vd_Vn),
    FNEG_Vd_V_4H_Vn_V_4H(FNEG_Vd_V_4H_Vn_V_4H),
    FNEG_Vd_Vn(FNEG_Vd_Vn),
    FRECPE_Vd_V_4H_Vn_V_4H(FRECPE_Vd_V_4H_Vn_V_4H),
    FRECPE_Vd_Vn(FRECPE_Vd_Vn),
    FRINT32X_Vd_Vn(FRINT32X_Vd_Vn),
    FRINT32Z_Vd_Vn(FRINT32Z_Vd_Vn),
    FRINT64X_Vd_Vn(FRINT64X_Vd_Vn),
    FRINT64Z_Vd_Vn(FRINT64Z_Vd_Vn),
    FRINTA_Vd_V_4H_Vn_V_4H(FRINTA_Vd_V_4H_Vn_V_4H),
    FRINTA_Vd_Vn(FRINTA_Vd_Vn),
    FRINTI_Vd_V_4H_Vn_V_4H(FRINTI_Vd_V_4H_Vn_V_4H),
    FRINTI_Vd_Vn(FRINTI_Vd_Vn),
    FRINTM_Vd_V_4H_Vn_V_4H(FRINTM_Vd_V_4H_Vn_V_4H),
    FRINTM_Vd_Vn(FRINTM_Vd_Vn),
    FRINTN_Vd_V_4H_Vn_V_4H(FRINTN_Vd_V_4H_Vn_V_4H),
    FRINTN_Vd_Vn(FRINTN_Vd_Vn),
    FRINTP_Vd_V_4H_Vn_V_4H(FRINTP_Vd_V_4H_Vn_V_4H),
    FRINTP_Vd_Vn(FRINTP_Vd_Vn),
    FRINTX_Vd_V_4H_Vn_V_4H(FRINTX_Vd_V_4H_Vn_V_4H),
    FRINTX_Vd_Vn(FRINTX_Vd_Vn),
    FRINTZ_Vd_V_4H_Vn_V_4H(FRINTZ_Vd_V_4H_Vn_V_4H),
    FRINTZ_Vd_Vn(FRINTZ_Vd_Vn),
    FRSQRTE_Vd_V_4H_Vn_V_4H(FRSQRTE_Vd_V_4H_Vn_V_4H),
    FRSQRTE_Vd_Vn(FRSQRTE_Vd_Vn),
    FSQRT_Vd_V_4H_Vn_V_4H(FSQRT_Vd_V_4H_Vn_V_4H),
    FSQRT_Vd_Vn(FSQRT_Vd_Vn),
    NEG_Vd_Vn(NEG_Vd_Vn),
    NOT_Vd_Vn(NOT_Vd_Vn),
    RBIT_Vd_Vn(RBIT_Vd_Vn),
    REV16_Vd_Vn(REV16_Vd_Vn),
    REV32_Vd_Vn(REV32_Vd_Vn),
    REV64_Vd_Vn(REV64_Vd_Vn),
    SADALP_Vd_Vn(SADALP_Vd_Vn),
    SADDLP_Vd_Vn(SADDLP_Vd_Vn),
    SCVTF_Vd_V_4H_Vn_V_4H(SCVTF_Vd_V_4H_Vn_V_4H),
    SCVTF_Vd_Vn(SCVTF_Vd_Vn),
    SHLL2_Vd_Vn_SHLL_IMM(SHLL2_Vd_Vn_SHLL_IMM),
    SHLL_Vd_Vn_SHLL_IMM(SHLL_Vd_Vn_SHLL_IMM),
    SQABS_Vd_Vn(SQABS_Vd_Vn),
    SQNEG_Vd_Vn(SQNEG_Vd_Vn),
    SQXTN2_Vd_Vn(SQXTN2_Vd_Vn),
    SQXTN_Vd_Vn(SQXTN_Vd_Vn),
    SQXTUN2_Vd_Vn(SQXTUN2_Vd_Vn),
    SQXTUN_Vd_Vn(SQXTUN_Vd_Vn),
    SUQADD_Vd_Vn(SUQADD_Vd_Vn),
    UADALP_Vd_Vn(UADALP_Vd_Vn),
    UADDLP_Vd_Vn(UADDLP_Vd_Vn),
    UCVTF_Vd_V_4H_Vn_V_4H(UCVTF_Vd_V_4H_Vn_V_4H),
    UCVTF_Vd_Vn(UCVTF_Vd_Vn),
    UQXTN2_Vd_Vn(UQXTN2_Vd_Vn),
    UQXTN_Vd_Vn(UQXTN_Vd_Vn),
    URECPE_Vd_Vn(URECPE_Vd_Vn),
    URSQRTE_Vd_Vn(URSQRTE_Vd_Vn),
    USQADD_Vd_Vn(USQADD_Vd_Vn),
    XTN2_Vd_Vn(XTN2_Vd_Vn),
    XTN_Vd_Vn(XTN_Vd_Vn),
}
#[derive(Debug, PartialEq, Eq, Copy, Clone)]
pub enum EXTRACT {
    EXTR_Rd_Rn_Rm_IMMS(EXTR_Rd_Rn_Rm_IMMS),
}
#[derive(Debug, PartialEq, Eq, Copy, Clone)]
pub enum SVE_SIZE_SD {
    ADCLB_SVE_Zd_SVE_Zn_SVE_Zm_16(ADCLB_SVE_Zd_SVE_Zn_SVE_Zm_16),
    ADCLT_SVE_Zd_SVE_Zn_SVE_Zm_16(ADCLT_SVE_Zd_SVE_Zn_SVE_Zm_16),
    ADR_SVE_Zd_SVE_ADDR_ZZ_LSL(ADR_SVE_Zd_SVE_ADDR_ZZ_LSL),
    CDOT_SVE_Zd_SVE_Zn_SVE_Zm_16_SVE_IMM_ROT2(CDOT_SVE_Zd_SVE_Zn_SVE_Zm_16_SVE_IMM_ROT2),
    COMPACT_SVE_Zd_SVE_Pg3_SVE_Zn(COMPACT_SVE_Zd_SVE_Pg3_SVE_Zn),
    CTERMEQ_Rn_Rm(CTERMEQ_Rn_Rm),
    CTERMNE_Rn_Rm(CTERMNE_Rn_Rm),
    HISTCNT_SVE_Zd_SVE_Pg3_SVE_Zn_SVE_Zm_16(HISTCNT_SVE_Zd_SVE_Pg3_SVE_Zn_SVE_Zm_16),
    REVH_SVE_Zd_SVE_Pg3_SVE_Zn(REVH_SVE_Zd_SVE_Pg3_SVE_Zn),
    SBCLB_SVE_Zd_SVE_Zn_SVE_Zm_16(SBCLB_SVE_Zd_SVE_Zn_SVE_Zm_16),
    SBCLT_SVE_Zd_SVE_Zn_SVE_Zm_16(SBCLT_SVE_Zd_SVE_Zn_SVE_Zm_16),
    SDIVR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(SDIVR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5),
    SDIV_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(SDIV_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5),
    SDOT_SVE_Zd_SVE_Zn_SVE_Zm_16(SDOT_SVE_Zd_SVE_Zn_SVE_Zm_16),
    SXTH_SVE_Zd_SVE_Pg3_SVE_Zn(SXTH_SVE_Zd_SVE_Pg3_SVE_Zn),
    UDIVR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(UDIVR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5),
    UDIV_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(UDIV_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5),
    UDOT_SVE_Zd_SVE_Zn_SVE_Zm_16(UDOT_SVE_Zd_SVE_Zn_SVE_Zm_16),
    UXTH_SVE_Zd_SVE_Pg3_SVE_Zn(UXTH_SVE_Zd_SVE_Pg3_SVE_Zn),
}
#[derive(Debug, PartialEq, Eq, Copy, Clone)]
pub enum SVE_SIZE_BHSD {
    ABS_SVE_Zd_SVE_Pg3_SVE_Zn(ABS_SVE_Zd_SVE_Pg3_SVE_Zn),
    ADDP_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(ADDP_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn),
    ADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(ADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5),
    ADD_SVE_Zd_SVE_Zd_SVE_AIMM(ADD_SVE_Zd_SVE_Zd_SVE_AIMM),
    ADD_SVE_Zd_SVE_Zn_SVE_Zm_16(ADD_SVE_Zd_SVE_Zn_SVE_Zm_16),
    ANDV_SVE_Vd_SVE_Pg3_SVE_Zn(ANDV_SVE_Vd_SVE_Pg3_SVE_Zn),
    AND_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(AND_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5),
    ASRR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(ASRR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5),
    ASR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(ASR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5),
    BDEP_SVE_Zd_SVE_Zn_SVE_Zm_16(BDEP_SVE_Zd_SVE_Zn_SVE_Zm_16),
    BEXT_SVE_Zd_SVE_Zn_SVE_Zm_16(BEXT_SVE_Zd_SVE_Zn_SVE_Zm_16),
    BGRP_SVE_Zd_SVE_Zn_SVE_Zm_16(BGRP_SVE_Zd_SVE_Zn_SVE_Zm_16),
    BIC_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(BIC_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5),
    CADD_SVE_Zd_SVE_Zd_SVE_Zn_SVE_IMM_ROT3(CADD_SVE_Zd_SVE_Zd_SVE_Zn_SVE_IMM_ROT3),
    CLASTA_Rd_SVE_Pg3_Rd_SVE_Zm_5(CLASTA_Rd_SVE_Pg3_Rd_SVE_Zm_5),
    CLASTA_SVE_Vd_SVE_Pg3_SVE_Vd_SVE_Zm_5(CLASTA_SVE_Vd_SVE_Pg3_SVE_Vd_SVE_Zm_5),
    CLASTA_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(CLASTA_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5),
    CLASTB_Rd_SVE_Pg3_Rd_SVE_Zm_5(CLASTB_Rd_SVE_Pg3_Rd_SVE_Zm_5),
    CLASTB_SVE_Vd_SVE_Pg3_SVE_Vd_SVE_Zm_5(CLASTB_SVE_Vd_SVE_Pg3_SVE_Vd_SVE_Zm_5),
    CLASTB_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(CLASTB_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5),
    CLS_SVE_Zd_SVE_Pg3_SVE_Zn(CLS_SVE_Zd_SVE_Pg3_SVE_Zn),
    CLZ_SVE_Zd_SVE_Pg3_SVE_Zn(CLZ_SVE_Zd_SVE_Pg3_SVE_Zn),
    CMLA_SVE_Zd_SVE_Zn_SVE_Zm_16_SVE_IMM_ROT2(CMLA_SVE_Zd_SVE_Zn_SVE_Zm_16_SVE_IMM_ROT2),
    CMPEQ_SVE_Pd_SVE_Pg3_SVE_Zn_SIMM5(CMPEQ_SVE_Pd_SVE_Pg3_SVE_Zn_SIMM5),
    CMPEQ_SVE_Pd_S_B_SVE_Pg3_P_Z_SVE_Zn_S_B_SVE_Zm_16_S_B(
        CMPEQ_SVE_Pd_S_B_SVE_Pg3_P_Z_SVE_Zn_S_B_SVE_Zm_16_S_B,
    ),
    CMPGE_SVE_Pd_SVE_Pg3_SVE_Zn_SIMM5(CMPGE_SVE_Pd_SVE_Pg3_SVE_Zn_SIMM5),
    CMPGE_SVE_Pd_S_B_SVE_Pg3_P_Z_SVE_Zn_S_B_SVE_Zm_16_S_B(
        CMPGE_SVE_Pd_S_B_SVE_Pg3_P_Z_SVE_Zn_S_B_SVE_Zm_16_S_B,
    ),
    CMPGT_SVE_Pd_SVE_Pg3_SVE_Zn_SIMM5(CMPGT_SVE_Pd_SVE_Pg3_SVE_Zn_SIMM5),
    CMPGT_SVE_Pd_S_B_SVE_Pg3_P_Z_SVE_Zn_S_B_SVE_Zm_16_S_B(
        CMPGT_SVE_Pd_S_B_SVE_Pg3_P_Z_SVE_Zn_S_B_SVE_Zm_16_S_B,
    ),
    CMPHI_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_UIMM7(CMPHI_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_UIMM7),
    CMPHI_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16(CMPHI_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16),
    CMPHS_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_UIMM7(CMPHS_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_UIMM7),
    CMPHS_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16(CMPHS_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16),
    CMPLE_SVE_Pd_SVE_Pg3_SVE_Zn_SIMM5(CMPLE_SVE_Pd_SVE_Pg3_SVE_Zn_SIMM5),
    CMPLO_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_UIMM7(CMPLO_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_UIMM7),
    CMPLS_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_UIMM7(CMPLS_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_UIMM7),
    CMPLT_SVE_Pd_SVE_Pg3_SVE_Zn_SIMM5(CMPLT_SVE_Pd_SVE_Pg3_SVE_Zn_SIMM5),
    CMPNE_SVE_Pd_SVE_Pg3_SVE_Zn_SIMM5(CMPNE_SVE_Pd_SVE_Pg3_SVE_Zn_SIMM5),
    CMPNE_SVE_Pd_S_B_SVE_Pg3_P_Z_SVE_Zn_S_B_SVE_Zm_16_S_B(
        CMPNE_SVE_Pd_S_B_SVE_Pg3_P_Z_SVE_Zn_S_B_SVE_Zm_16_S_B,
    ),
    CNOT_SVE_Zd_SVE_Pg3_SVE_Zn(CNOT_SVE_Zd_SVE_Pg3_SVE_Zn),
    CNTP_Rd_SVE_Pg4_10_SVE_Pn(CNTP_Rd_SVE_Pg4_10_SVE_Pn),
    CNT_SVE_Zd_SVE_Pg3_SVE_Zn(CNT_SVE_Zd_SVE_Pg3_SVE_Zn),
    CPY_SVE_Zd_SVE_Pg3_Rn_SP(CPY_SVE_Zd_SVE_Pg3_Rn_SP),
    CPY_SVE_Zd_SVE_Pg3_SVE_Vn(CPY_SVE_Zd_SVE_Pg3_SVE_Vn),
    DECP_Rd_SVE_Pg4_5(DECP_Rd_SVE_Pg4_5),
    DUP_SVE_Zd_Rn_SP(DUP_SVE_Zd_Rn_SP),
    DUP_SVE_Zd_SVE_ASIMM(DUP_SVE_Zd_SVE_ASIMM),
    EORBT_SVE_Zd_SVE_Zn_SVE_Zm_16(EORBT_SVE_Zd_SVE_Zn_SVE_Zm_16),
    EORTB_SVE_Zd_SVE_Zn_SVE_Zm_16(EORTB_SVE_Zd_SVE_Zn_SVE_Zm_16),
    EORV_SVE_Vd_SVE_Pg3_SVE_Zn(EORV_SVE_Vd_SVE_Pg3_SVE_Zn),
    EOR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(EOR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5),
    INCP_Rd_SVE_Pg4_5(INCP_Rd_SVE_Pg4_5),
    INDEX_SVE_Zd_Rn_Rm(INDEX_SVE_Zd_Rn_Rm),
    INDEX_SVE_Zd_Rn_SIMM5(INDEX_SVE_Zd_Rn_SIMM5),
    INDEX_SVE_Zd_SVE_SIMM5_Rm(INDEX_SVE_Zd_SVE_SIMM5_Rm),
    INDEX_SVE_Zd_SVE_SIMM5_SVE_SIMM5B(INDEX_SVE_Zd_SVE_SIMM5_SVE_SIMM5B),
    INSR_SVE_Zd_SVE_Rm(INSR_SVE_Zd_SVE_Rm),
    INSR_SVE_Zd_SVE_Vm(INSR_SVE_Zd_SVE_Vm),
    LASTA_Rd_SVE_Pg3_SVE_Zn(LASTA_Rd_SVE_Pg3_SVE_Zn),
    LASTA_SVE_Vd_SVE_Pg3_SVE_Zn(LASTA_SVE_Vd_SVE_Pg3_SVE_Zn),
    LASTB_Rd_SVE_Pg3_SVE_Zn(LASTB_Rd_SVE_Pg3_SVE_Zn),
    LASTB_SVE_Vd_SVE_Pg3_SVE_Zn(LASTB_SVE_Vd_SVE_Pg3_SVE_Zn),
    LSLR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(LSLR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5),
    LSL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(LSL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5),
    LSRR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(LSRR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5),
    LSR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(LSR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5),
    MAD_SVE_Zd_SVE_Pg3_SVE_Zm_16_SVE_Za_5(MAD_SVE_Zd_SVE_Pg3_SVE_Zm_16_SVE_Za_5),
    MLA_SVE_Zd_SVE_Pg3_SVE_Zn_SVE_Zm_16(MLA_SVE_Zd_SVE_Pg3_SVE_Zn_SVE_Zm_16),
    MLS_SVE_Zd_SVE_Pg3_SVE_Zn_SVE_Zm_16(MLS_SVE_Zd_SVE_Pg3_SVE_Zn_SVE_Zm_16),
    MSB_SVE_Zd_SVE_Pg3_SVE_Zm_16_SVE_Za_5(MSB_SVE_Zd_SVE_Pg3_SVE_Zm_16_SVE_Za_5),
    MUL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(MUL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5),
    MUL_SVE_Zd_SVE_Zd_SVE_SIMM8(MUL_SVE_Zd_SVE_Zd_SVE_SIMM8),
    MUL_SVE_Zd_SVE_Zn_SVE_Zm_16(MUL_SVE_Zd_SVE_Zn_SVE_Zm_16),
    NEG_SVE_Zd_SVE_Pg3_SVE_Zn(NEG_SVE_Zd_SVE_Pg3_SVE_Zn),
    NOT_SVE_Zd_SVE_Pg3_SVE_Zn(NOT_SVE_Zd_SVE_Pg3_SVE_Zn),
    ORR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(ORR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5),
    ORV_SVE_Vd_SVE_Pg3_SVE_Zn(ORV_SVE_Vd_SVE_Pg3_SVE_Zn),
    PNEXT_SVE_Pd_SVE_Pg4_5_SVE_Pd(PNEXT_SVE_Pd_SVE_Pg4_5_SVE_Pd),
    PTRUES_SVE_Pd_SVE_PATTERN(PTRUES_SVE_Pd_SVE_PATTERN),
    PTRUE_SVE_Pd_SVE_PATTERN(PTRUE_SVE_Pd_SVE_PATTERN),
    RBIT_SVE_Zd_SVE_Pg3_SVE_Zn(RBIT_SVE_Zd_SVE_Pg3_SVE_Zn),
    REV_SVE_Pd_SVE_Pn(REV_SVE_Pd_SVE_Pn),
    REV_SVE_Zd_SVE_Zn(REV_SVE_Zd_SVE_Zn),
    SABA_SVE_Zd_SVE_Zn_SVE_Zm_16(SABA_SVE_Zd_SVE_Zn_SVE_Zm_16),
    SABD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(SABD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5),
    SCLAMP_SVE_Zd_SVE_Zn_SVE_Zm_16(SCLAMP_SVE_Zd_SVE_Zn_SVE_Zm_16),
    SEL_SVE_Zd_SVE_Pg4_10_SVE_Zn_SVE_Zm_16(SEL_SVE_Zd_SVE_Pg4_10_SVE_Zn_SVE_Zm_16),
    SHADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(SHADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn),
    SHSUBR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(SHSUBR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn),
    SHSUB_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(SHSUB_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn),
    SMAXP_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(SMAXP_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn),
    SMAXV_SVE_Vd_SVE_Pg3_SVE_Zn(SMAXV_SVE_Vd_SVE_Pg3_SVE_Zn),
    SMAX_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(SMAX_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5),
    SMAX_SVE_Zd_SVE_Zd_SVE_SIMM8(SMAX_SVE_Zd_SVE_Zd_SVE_SIMM8),
    SMINP_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(SMINP_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn),
    SMINV_SVE_Vd_SVE_Pg3_SVE_Zn(SMINV_SVE_Vd_SVE_Pg3_SVE_Zn),
    SMIN_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(SMIN_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5),
    SMIN_SVE_Zd_SVE_Zd_SVE_SIMM8(SMIN_SVE_Zd_SVE_Zd_SVE_SIMM8),
    SMULH_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(SMULH_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5),
    SMULH_SVE_Zd_SVE_Zn_SVE_Zm_16(SMULH_SVE_Zd_SVE_Zn_SVE_Zm_16),
    SPLICE_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(SPLICE_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5),
    SPLICE_SVE_Zd_SVE_Pg3_SVE_ZnxN(SPLICE_SVE_Zd_SVE_Pg3_SVE_ZnxN),
    SQABS_SVE_Zd_SVE_Pg3_SVE_Zn(SQABS_SVE_Zd_SVE_Pg3_SVE_Zn),
    SQADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(SQADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn),
    SQADD_SVE_Zd_SVE_Zd_SVE_AIMM(SQADD_SVE_Zd_SVE_Zd_SVE_AIMM),
    SQADD_SVE_Zd_SVE_Zn_SVE_Zm_16(SQADD_SVE_Zd_SVE_Zn_SVE_Zm_16),
    SQCADD_SVE_Zd_SVE_Zd_SVE_Zn_SVE_IMM_ROT3(SQCADD_SVE_Zd_SVE_Zd_SVE_Zn_SVE_IMM_ROT3),
    SQDECP_Rd_SVE_Pg4_5(SQDECP_Rd_SVE_Pg4_5),
    SQDECP_Rd_SVE_Pg4_5_Rd(SQDECP_Rd_SVE_Pg4_5_Rd),
    SQDMULH_SVE_Zd_SVE_Zn_SVE_Zm_16(SQDMULH_SVE_Zd_SVE_Zn_SVE_Zm_16),
    SQINCP_Rd_SVE_Pg4_5(SQINCP_Rd_SVE_Pg4_5),
    SQINCP_Rd_SVE_Pg4_5_Rd(SQINCP_Rd_SVE_Pg4_5_Rd),
    SQNEG_SVE_Zd_SVE_Pg3_SVE_Zn(SQNEG_SVE_Zd_SVE_Pg3_SVE_Zn),
    SQRDCMLAH_SVE_Zd_SVE_Zn_SVE_Zm_16_SVE_IMM_ROT2(SQRDCMLAH_SVE_Zd_SVE_Zn_SVE_Zm_16_SVE_IMM_ROT2),
    SQRDMLAH_SVE_Zd_SVE_Zn_SVE_Zm_16(SQRDMLAH_SVE_Zd_SVE_Zn_SVE_Zm_16),
    SQRDMLSH_SVE_Zd_SVE_Zn_SVE_Zm_16(SQRDMLSH_SVE_Zd_SVE_Zn_SVE_Zm_16),
    SQRDMULH_SVE_Zd_SVE_Zn_SVE_Zm_16(SQRDMULH_SVE_Zd_SVE_Zn_SVE_Zm_16),
    SQRSHLR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(SQRSHLR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn),
    SQRSHL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(SQRSHL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn),
    SQSHLR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(SQSHLR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn),
    SQSHL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(SQSHL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn),
    SQSUBR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(SQSUBR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn),
    SQSUB_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(SQSUB_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn),
    SQSUB_SVE_Zd_SVE_Zd_SVE_AIMM(SQSUB_SVE_Zd_SVE_Zd_SVE_AIMM),
    SQSUB_SVE_Zd_SVE_Zn_SVE_Zm_16(SQSUB_SVE_Zd_SVE_Zn_SVE_Zm_16),
    SRHADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(SRHADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn),
    SRSHLR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(SRSHLR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn),
    SRSHL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(SRSHL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn),
    SUBR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(SUBR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5),
    SUBR_SVE_Zd_SVE_Zd_SVE_AIMM(SUBR_SVE_Zd_SVE_Zd_SVE_AIMM),
    SUB_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(SUB_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5),
    SUB_SVE_Zd_SVE_Zd_SVE_AIMM(SUB_SVE_Zd_SVE_Zd_SVE_AIMM),
    SUB_SVE_Zd_SVE_Zn_SVE_Zm_16(SUB_SVE_Zd_SVE_Zn_SVE_Zm_16),
    SUQADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(SUQADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn),
    TBL_SVE_Zd_SVE_ZnxN_SVE_Zm_16(TBL_SVE_Zd_SVE_ZnxN_SVE_Zm_16),
    TBL_SVE_Zd_S_B_SVE_ZnxN_S_B_SVE_Zm_16_S_B(TBL_SVE_Zd_S_B_SVE_ZnxN_S_B_SVE_Zm_16_S_B),
    TBX_SVE_Zd_SVE_Zn_SVE_Zm_16(TBX_SVE_Zd_SVE_Zn_SVE_Zm_16),
    TRN1_SVE_Pd_SVE_Pn_SVE_Pm(TRN1_SVE_Pd_SVE_Pn_SVE_Pm),
    TRN1_SVE_Zd_S_B_SVE_Zn_S_B_SVE_Zm_16_S_B(TRN1_SVE_Zd_S_B_SVE_Zn_S_B_SVE_Zm_16_S_B),
    TRN2_SVE_Pd_SVE_Pn_SVE_Pm(TRN2_SVE_Pd_SVE_Pn_SVE_Pm),
    TRN2_SVE_Zd_S_B_SVE_Zn_S_B_SVE_Zm_16_S_B(TRN2_SVE_Zd_S_B_SVE_Zn_S_B_SVE_Zm_16_S_B),
    UABA_SVE_Zd_SVE_Zn_SVE_Zm_16(UABA_SVE_Zd_SVE_Zn_SVE_Zm_16),
    UABD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(UABD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5),
    UADDV_SVE_Vd_SVE_Pg3_SVE_Zn(UADDV_SVE_Vd_SVE_Pg3_SVE_Zn),
    UCLAMP_SVE_Zd_SVE_Zn_SVE_Zm_16(UCLAMP_SVE_Zd_SVE_Zn_SVE_Zm_16),
    UHADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(UHADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn),
    UHSUBR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(UHSUBR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn),
    UHSUB_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(UHSUB_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn),
    UMAXP_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(UMAXP_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn),
    UMAXV_SVE_Vd_SVE_Pg3_SVE_Zn(UMAXV_SVE_Vd_SVE_Pg3_SVE_Zn),
    UMAX_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(UMAX_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5),
    UMAX_SVE_Zd_SVE_Zd_SVE_UIMM8(UMAX_SVE_Zd_SVE_Zd_SVE_UIMM8),
    UMINP_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(UMINP_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn),
    UMINV_SVE_Vd_SVE_Pg3_SVE_Zn(UMINV_SVE_Vd_SVE_Pg3_SVE_Zn),
    UMIN_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(UMIN_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5),
    UMIN_SVE_Zd_SVE_Zd_SVE_UIMM8(UMIN_SVE_Zd_SVE_Zd_SVE_UIMM8),
    UMULH_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(UMULH_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5),
    UMULH_SVE_Zd_SVE_Zn_SVE_Zm_16(UMULH_SVE_Zd_SVE_Zn_SVE_Zm_16),
    UQADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(UQADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn),
    UQADD_SVE_Zd_SVE_Zd_SVE_AIMM(UQADD_SVE_Zd_SVE_Zd_SVE_AIMM),
    UQADD_SVE_Zd_SVE_Zn_SVE_Zm_16(UQADD_SVE_Zd_SVE_Zn_SVE_Zm_16),
    UQDECP_Rd_SVE_Pg4_5(UQDECP_Rd_SVE_Pg4_5),
    UQDECP_Rd_X_SVE_Pg4_5_S_B(UQDECP_Rd_X_SVE_Pg4_5_S_B),
    UQINCP_Rd_SVE_Pg4_5(UQINCP_Rd_SVE_Pg4_5),
    UQINCP_Rd_X_SVE_Pg4_5_S_B(UQINCP_Rd_X_SVE_Pg4_5_S_B),
    UQRSHLR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(UQRSHLR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn),
    UQRSHL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(UQRSHL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn),
    UQSHLR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(UQSHLR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn),
    UQSHL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(UQSHL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn),
    UQSUBR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(UQSUBR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn),
    UQSUB_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(UQSUB_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn),
    UQSUB_SVE_Zd_SVE_Zd_SVE_AIMM(UQSUB_SVE_Zd_SVE_Zd_SVE_AIMM),
    UQSUB_SVE_Zd_SVE_Zn_SVE_Zm_16(UQSUB_SVE_Zd_SVE_Zn_SVE_Zm_16),
    URHADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(URHADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn),
    URSHLR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(URSHLR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn),
    URSHL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(URSHL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn),
    USQADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(USQADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn),
    UZP1_SVE_Pd_SVE_Pn_SVE_Pm(UZP1_SVE_Pd_SVE_Pn_SVE_Pm),
    UZP1_SVE_Zd_S_B_SVE_Zn_S_B_SVE_Zm_16_S_B(UZP1_SVE_Zd_S_B_SVE_Zn_S_B_SVE_Zm_16_S_B),
    UZP2_SVE_Pd_SVE_Pn_SVE_Pm(UZP2_SVE_Pd_SVE_Pn_SVE_Pm),
    UZP2_SVE_Zd_S_B_SVE_Zn_S_B_SVE_Zm_16_S_B(UZP2_SVE_Zd_S_B_SVE_Zn_S_B_SVE_Zm_16_S_B),
    WHILEGE_SVE_Pd_Rn_Rm(WHILEGE_SVE_Pd_Rn_Rm),
    WHILEGE_SVE_Pd_S_B_Rn_X_Rm_X(WHILEGE_SVE_Pd_S_B_Rn_X_Rm_X),
    WHILEGT_SVE_Pd_Rn_Rm(WHILEGT_SVE_Pd_Rn_Rm),
    WHILEGT_SVE_Pd_S_B_Rn_X_Rm_X(WHILEGT_SVE_Pd_S_B_Rn_X_Rm_X),
    WHILEHI_SVE_Pd_Rn_Rm(WHILEHI_SVE_Pd_Rn_Rm),
    WHILEHI_SVE_Pd_S_B_Rn_X_Rm_X(WHILEHI_SVE_Pd_S_B_Rn_X_Rm_X),
    WHILEHS_SVE_Pd_Rn_Rm(WHILEHS_SVE_Pd_Rn_Rm),
    WHILEHS_SVE_Pd_S_B_Rn_X_Rm_X(WHILEHS_SVE_Pd_S_B_Rn_X_Rm_X),
    WHILELE_SVE_Pd_Rn_Rm(WHILELE_SVE_Pd_Rn_Rm),
    WHILELE_SVE_Pd_S_B_Rn_X_Rm_X(WHILELE_SVE_Pd_S_B_Rn_X_Rm_X),
    WHILELO_SVE_Pd_Rn_Rm(WHILELO_SVE_Pd_Rn_Rm),
    WHILELO_SVE_Pd_S_B_Rn_X_Rm_X(WHILELO_SVE_Pd_S_B_Rn_X_Rm_X),
    WHILELS_SVE_Pd_Rn_Rm(WHILELS_SVE_Pd_Rn_Rm),
    WHILELS_SVE_Pd_S_B_Rn_X_Rm_X(WHILELS_SVE_Pd_S_B_Rn_X_Rm_X),
    WHILELT_SVE_Pd_Rn_Rm(WHILELT_SVE_Pd_Rn_Rm),
    WHILELT_SVE_Pd_S_B_Rn_X_Rm_X(WHILELT_SVE_Pd_S_B_Rn_X_Rm_X),
    WHILERW_SVE_Pd_Rn_Rm(WHILERW_SVE_Pd_Rn_Rm),
    WHILEWR_SVE_Pd_Rn_Rm(WHILEWR_SVE_Pd_Rn_Rm),
    ZIP1_SVE_Pd_SVE_Pn_SVE_Pm(ZIP1_SVE_Pd_SVE_Pn_SVE_Pm),
    ZIP1_SVE_Zd_S_B_SVE_Zn_S_B_SVE_Zm_16_S_B(ZIP1_SVE_Zd_S_B_SVE_Zn_S_B_SVE_Zm_16_S_B),
    ZIP2_SVE_Pd_SVE_Pn_SVE_Pm(ZIP2_SVE_Pd_SVE_Pn_SVE_Pm),
    ZIP2_SVE_Zd_S_B_SVE_Zn_S_B_SVE_Zm_16_S_B(ZIP2_SVE_Zd_S_B_SVE_Zn_S_B_SVE_Zm_16_S_B),
}
#[derive(Debug, PartialEq, Eq, Copy, Clone)]
pub enum SVE_SIZE_HSD2 {
    FLOGB_SVE_Zd_SVE_Pg3_SVE_Zn(FLOGB_SVE_Zd_SVE_Pg3_SVE_Zn),
}
#[derive(Debug, PartialEq, Eq, Copy, Clone)]
pub enum ADDSUB_IMM {
    ADDG_Rd_SP_Rn_SP_UIMM10_UIMM4_ADDG(ADDG_Rd_SP_Rn_SP_UIMM10_UIMM4_ADDG),
    ADDS_Rd_Rn_SP_AIMM(ADDS_Rd_Rn_SP_AIMM),
    ADD_Rd_SP_Rn_SP_AIMM(ADD_Rd_SP_Rn_SP_AIMM),
    SUBG_Rd_SP_Rn_SP_UIMM10_UIMM4_ADDG(SUBG_Rd_SP_Rn_SP_UIMM10_UIMM4_ADDG),
    SUBS_Rd_Rn_SP_AIMM(SUBS_Rd_Rn_SP_AIMM),
    SUB_Rd_SP_Rn_SP_AIMM(SUB_Rd_SP_Rn_SP_AIMM),
}
#[derive(Debug, PartialEq, Eq, Copy, Clone)]
pub enum ASISDPAIR {
    ADDP_Sd_Vn(ADDP_Sd_Vn),
    FADDP_Sd_S_S_Vn_V_2S(FADDP_Sd_S_S_Vn_V_2S),
    FADDP_Sd_Vn(FADDP_Sd_Vn),
    FMAXNMP_Sd_S_S_Vn_V_2S(FMAXNMP_Sd_S_S_Vn_V_2S),
    FMAXNMP_Sd_Vn(FMAXNMP_Sd_Vn),
    FMAXP_Sd_S_S_Vn_V_2S(FMAXP_Sd_S_S_Vn_V_2S),
    FMAXP_Sd_Vn(FMAXP_Sd_Vn),
    FMINNMP_Sd_S_S_Vn_V_2S(FMINNMP_Sd_S_S_Vn_V_2S),
    FMINNMP_Sd_Vn(FMINNMP_Sd_Vn),
    FMINP_Sd_S_S_Vn_V_2S(FMINP_Sd_S_S_Vn_V_2S),
    FMINP_Sd_Vn(FMINP_Sd_Vn),
}
#[derive(Debug, PartialEq, Eq, Copy, Clone)]
pub enum SME_SZ_23 {
    SQCVTN_SVE_Zd_SME_Znx4(SQCVTN_SVE_Zd_SME_Znx4),
    SQCVTUN_SVE_Zd_SME_Znx4(SQCVTUN_SVE_Zd_SME_Znx4),
    SQCVTU_SVE_Zd_SME_Znx4(SQCVTU_SVE_Zd_SME_Znx4),
    SQCVT_SVE_Zd_SME_Znx4(SQCVT_SVE_Zd_SME_Znx4),
    UQCVTN_SVE_Zd_SME_Znx4(UQCVTN_SVE_Zd_SME_Znx4),
    UQCVT_SVE_Zd_SME_Znx4(UQCVT_SVE_Zd_SME_Znx4),
}
#[derive(Debug, PartialEq, Eq, Copy, Clone)]
pub enum SME_MISC {
    ADDHA_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn(ADDHA_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn),
    ADDHA_SME_ZAda_3b_SVE_Pg3_SME_Pm_SVE_Zn(ADDHA_SME_ZAda_3b_SVE_Pg3_SME_Pm_SVE_Zn),
    ADDSPL_Rd_SP_SVE_Rn_SP_SVE_SIMM6(ADDSPL_Rd_SP_SVE_Rn_SP_SVE_SIMM6),
    ADDSVL_Rd_SP_SVE_Rn_SP_SVE_SIMM6(ADDSVL_Rd_SP_SVE_Rn_SP_SVE_SIMM6),
    ADDVA_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn(ADDVA_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn),
    ADDVA_SME_ZAda_3b_SVE_Pg3_SME_Pm_SVE_Zn(ADDVA_SME_ZAda_3b_SVE_Pg3_SME_Pm_SVE_Zn),
    BFCVTN_SVE_Zd_SME_Znx2(BFCVTN_SVE_Zd_SME_Znx2),
    BFCVT_SVE_Zd_SME_Znx2(BFCVT_SVE_Zd_SME_Znx2),
    BFDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2(
        BFDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2,
    ),
    BFDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zmx2(BFDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zmx2),
    BFDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2(
        BFDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2,
    ),
    BFDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zmx4(BFDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zmx4),
    BFDOT_SME_ZA_array_off3_0_SVE_ZnxN_SME_Zm(BFDOT_SME_ZA_array_off3_0_SVE_ZnxN_SME_Zm),
    BFDOT_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_H_SME_Zm_S_H(
        BFDOT_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_H_SME_Zm_S_H,
    ),
    BFMLAL_SME_ZA_array_off2x2_SME_Znx2_SME_Zm_INDEX3_2(
        BFMLAL_SME_ZA_array_off2x2_SME_Znx2_SME_Zm_INDEX3_2,
    ),
    BFMLAL_SME_ZA_array_off2x2_SME_Znx2_SME_Zmx2(BFMLAL_SME_ZA_array_off2x2_SME_Znx2_SME_Zmx2),
    BFMLAL_SME_ZA_array_off2x2_SME_Znx4_SME_Zm_INDEX3_2(
        BFMLAL_SME_ZA_array_off2x2_SME_Znx4_SME_Zm_INDEX3_2,
    ),
    BFMLAL_SME_ZA_array_off2x2_SME_Znx4_SME_Zmx4(BFMLAL_SME_ZA_array_off2x2_SME_Znx4_SME_Zmx4),
    BFMLAL_SME_ZA_array_off2x2_SVE_ZnxN_SME_Zm(BFMLAL_SME_ZA_array_off2x2_SVE_ZnxN_SME_Zm),
    BFMLAL_SME_ZA_array_off2x2_S_S_SVE_ZnxN_S_H_SME_Zm_S_H(
        BFMLAL_SME_ZA_array_off2x2_S_S_SVE_ZnxN_S_H_SME_Zm_S_H,
    ),
    BFMLAL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm(BFMLAL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm),
    BFMLAL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm_INDEX3_10(
        BFMLAL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm_INDEX3_10,
    ),
    BFMLSL_SME_ZA_array_off2x2_SME_Znx2_SME_Zm_INDEX3_2(
        BFMLSL_SME_ZA_array_off2x2_SME_Znx2_SME_Zm_INDEX3_2,
    ),
    BFMLSL_SME_ZA_array_off2x2_SME_Znx2_SME_Zmx2(BFMLSL_SME_ZA_array_off2x2_SME_Znx2_SME_Zmx2),
    BFMLSL_SME_ZA_array_off2x2_SME_Znx4_SME_Zm_INDEX3_2(
        BFMLSL_SME_ZA_array_off2x2_SME_Znx4_SME_Zm_INDEX3_2,
    ),
    BFMLSL_SME_ZA_array_off2x2_SME_Znx4_SME_Zmx4(BFMLSL_SME_ZA_array_off2x2_SME_Znx4_SME_Zmx4),
    BFMLSL_SME_ZA_array_off2x2_SVE_ZnxN_SME_Zm(BFMLSL_SME_ZA_array_off2x2_SVE_ZnxN_SME_Zm),
    BFMLSL_SME_ZA_array_off2x2_S_S_SVE_ZnxN_S_H_SME_Zm_S_H(
        BFMLSL_SME_ZA_array_off2x2_S_S_SVE_ZnxN_S_H_SME_Zm_S_H,
    ),
    BFMLSL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm(BFMLSL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm),
    BFMLSL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm_INDEX3_10(
        BFMLSL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm_INDEX3_10,
    ),
    BFMOPA_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16(
        BFMOPA_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16,
    ),
    BFMOPS_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16(
        BFMOPS_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16,
    ),
    BFVDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2(
        BFVDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2,
    ),
    BMOPA_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16(
        BMOPA_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16,
    ),
    BMOPS_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16(
        BMOPS_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16,
    ),
    FDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2(
        FDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2,
    ),
    FDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zmx2(FDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zmx2),
    FDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2(
        FDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2,
    ),
    FDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zmx4(FDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zmx4),
    FDOT_SME_ZA_array_off3_0_SVE_ZnxN_SME_Zm(FDOT_SME_ZA_array_off3_0_SVE_ZnxN_SME_Zm),
    FDOT_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_H_SME_Zm_S_H(
        FDOT_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_H_SME_Zm_S_H,
    ),
    FMLAL_SME_ZA_array_off2x2_SME_Znx2_SME_Zm_INDEX3_2(
        FMLAL_SME_ZA_array_off2x2_SME_Znx2_SME_Zm_INDEX3_2,
    ),
    FMLAL_SME_ZA_array_off2x2_SME_Znx2_SME_Zmx2(FMLAL_SME_ZA_array_off2x2_SME_Znx2_SME_Zmx2),
    FMLAL_SME_ZA_array_off2x2_SME_Znx4_SME_Zm_INDEX3_2(
        FMLAL_SME_ZA_array_off2x2_SME_Znx4_SME_Zm_INDEX3_2,
    ),
    FMLAL_SME_ZA_array_off2x2_SME_Znx4_SME_Zmx4(FMLAL_SME_ZA_array_off2x2_SME_Znx4_SME_Zmx4),
    FMLAL_SME_ZA_array_off2x2_SVE_ZnxN_SME_Zm(FMLAL_SME_ZA_array_off2x2_SVE_ZnxN_SME_Zm),
    FMLAL_SME_ZA_array_off2x2_S_S_SVE_ZnxN_S_H_SME_Zm_S_H(
        FMLAL_SME_ZA_array_off2x2_S_S_SVE_ZnxN_S_H_SME_Zm_S_H,
    ),
    FMLAL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm(FMLAL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm),
    FMLAL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm_INDEX3_10(
        FMLAL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm_INDEX3_10,
    ),
    FMLA_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX1(
        FMLA_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX1,
    ),
    FMLA_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2(
        FMLA_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2,
    ),
    FMLA_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX1(
        FMLA_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX1,
    ),
    FMLA_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2(
        FMLA_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2,
    ),
    FMLSL_SME_ZA_array_off2x2_SME_Znx2_SME_Zm_INDEX3_2(
        FMLSL_SME_ZA_array_off2x2_SME_Znx2_SME_Zm_INDEX3_2,
    ),
    FMLSL_SME_ZA_array_off2x2_SME_Znx2_SME_Zmx2(FMLSL_SME_ZA_array_off2x2_SME_Znx2_SME_Zmx2),
    FMLSL_SME_ZA_array_off2x2_SME_Znx4_SME_Zm_INDEX3_2(
        FMLSL_SME_ZA_array_off2x2_SME_Znx4_SME_Zm_INDEX3_2,
    ),
    FMLSL_SME_ZA_array_off2x2_SME_Znx4_SME_Zmx4(FMLSL_SME_ZA_array_off2x2_SME_Znx4_SME_Zmx4),
    FMLSL_SME_ZA_array_off2x2_SVE_ZnxN_SME_Zm(FMLSL_SME_ZA_array_off2x2_SVE_ZnxN_SME_Zm),
    FMLSL_SME_ZA_array_off2x2_S_S_SVE_ZnxN_S_H_SME_Zm_S_H(
        FMLSL_SME_ZA_array_off2x2_S_S_SVE_ZnxN_S_H_SME_Zm_S_H,
    ),
    FMLSL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm(FMLSL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm),
    FMLSL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm_INDEX3_10(
        FMLSL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm_INDEX3_10,
    ),
    FMLS_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX1(
        FMLS_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX1,
    ),
    FMLS_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2(
        FMLS_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2,
    ),
    FMLS_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX1(
        FMLS_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX1,
    ),
    FMLS_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2(
        FMLS_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2,
    ),
    FMOPA_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16(
        FMOPA_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16,
    ),
    FMOPA_SME_ZAda_2b_S_S_SVE_Pg3_P_M_SME_Pm_P_M_SVE_Zn_S_H_SVE_Zm_16_S_H(
        FMOPA_SME_ZAda_2b_S_S_SVE_Pg3_P_M_SME_Pm_P_M_SVE_Zn_S_H_SVE_Zm_16_S_H,
    ),
    FMOPA_SME_ZAda_3b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16(
        FMOPA_SME_ZAda_3b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16,
    ),
    FMOPS_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16(
        FMOPS_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16,
    ),
    FMOPS_SME_ZAda_2b_S_S_SVE_Pg3_P_M_SME_Pm_P_M_SVE_Zn_S_H_SVE_Zm_16_S_H(
        FMOPS_SME_ZAda_2b_S_S_SVE_Pg3_P_M_SME_Pm_P_M_SVE_Zn_S_H_SVE_Zm_16_S_H,
    ),
    FMOPS_SME_ZAda_3b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16(
        FMOPS_SME_ZAda_3b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16,
    ),
    FVDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2(
        FVDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2,
    ),
    LDR_SME_ZT0_SIMD_ADDR_SIMPLE(LDR_SME_ZT0_SIMD_ADDR_SIMPLE),
    MOVT_Rt_SME_ZT0_INDEX(MOVT_Rt_SME_ZT0_INDEX),
    MOVT_SME_ZT0_INDEX_Rt(MOVT_SME_ZT0_INDEX_Rt),
    RDSVL_Rd_SVE_SIMM6(RDSVL_Rd_SVE_SIMM6),
    REVD_SVE_Zd_SVE_Pg3_SVE_Zn(REVD_SVE_Zd_SVE_Pg3_SVE_Zn),
    RPRFM_RPRFMOP_Rm_SIMD_ADDR_SIMPLE(RPRFM_RPRFMOP_Rm_SIMD_ADDR_SIMPLE),
    SDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX1(
        SDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX1,
    ),
    SDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2(
        SDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2,
    ),
    SDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX1(
        SDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX1,
    ),
    SDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2(
        SDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2,
    ),
    SDOT_SME_ZA_array_off3_0_S_S_SME_Znx2_S_B_SME_Zm_INDEX2_S_B(
        SDOT_SME_ZA_array_off3_0_S_S_SME_Znx2_S_B_SME_Zm_INDEX2_S_B,
    ),
    SDOT_SME_ZA_array_off3_0_S_S_SME_Znx2_S_H_SME_Zmx2_S_H(
        SDOT_SME_ZA_array_off3_0_S_S_SME_Znx2_S_H_SME_Zmx2_S_H,
    ),
    SDOT_SME_ZA_array_off3_0_S_S_SME_Znx4_S_B_SME_Zm_INDEX2_S_B(
        SDOT_SME_ZA_array_off3_0_S_S_SME_Znx4_S_B_SME_Zm_INDEX2_S_B,
    ),
    SDOT_SME_ZA_array_off3_0_S_S_SME_Znx4_S_H_SME_Zmx4_S_H(
        SDOT_SME_ZA_array_off3_0_S_S_SME_Znx4_S_H_SME_Zmx4_S_H,
    ),
    SDOT_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_H_SME_Zm_S_H(
        SDOT_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_H_SME_Zm_S_H,
    ),
    SDOT_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_H_SME_Zm_S_H_c1701408(
        SDOT_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_H_SME_Zm_S_H_c1701408,
    ),
    SMLALL_SME_ZA_array_off1x4_SME_Znx2_SME_Zm_INDEX3_1(
        SMLALL_SME_ZA_array_off1x4_SME_Znx2_SME_Zm_INDEX3_1,
    ),
    SMLALL_SME_ZA_array_off1x4_SME_Znx2_SME_Zm_INDEX4_1(
        SMLALL_SME_ZA_array_off1x4_SME_Znx2_SME_Zm_INDEX4_1,
    ),
    SMLALL_SME_ZA_array_off1x4_SME_Znx4_SME_Zm_INDEX3_1(
        SMLALL_SME_ZA_array_off1x4_SME_Znx4_SME_Zm_INDEX3_1,
    ),
    SMLALL_SME_ZA_array_off1x4_SME_Znx4_SME_Zm_INDEX4_1(
        SMLALL_SME_ZA_array_off1x4_SME_Znx4_SME_Zm_INDEX4_1,
    ),
    SMLALL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm_INDEX3_10(
        SMLALL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm_INDEX3_10,
    ),
    SMLALL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm_INDEX4_10(
        SMLALL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm_INDEX4_10,
    ),
    SMLAL_SME_ZA_array_off2x2_SME_Znx2_SME_Zm_INDEX3_2(
        SMLAL_SME_ZA_array_off2x2_SME_Znx2_SME_Zm_INDEX3_2,
    ),
    SMLAL_SME_ZA_array_off2x2_SME_Znx2_SME_Zmx2(SMLAL_SME_ZA_array_off2x2_SME_Znx2_SME_Zmx2),
    SMLAL_SME_ZA_array_off2x2_SME_Znx4_SME_Zm_INDEX3_2(
        SMLAL_SME_ZA_array_off2x2_SME_Znx4_SME_Zm_INDEX3_2,
    ),
    SMLAL_SME_ZA_array_off2x2_SME_Znx4_SME_Zmx4(SMLAL_SME_ZA_array_off2x2_SME_Znx4_SME_Zmx4),
    SMLAL_SME_ZA_array_off2x2_SVE_ZnxN_SME_Zm(SMLAL_SME_ZA_array_off2x2_SVE_ZnxN_SME_Zm),
    SMLAL_SME_ZA_array_off2x2_S_S_SVE_ZnxN_S_H_SME_Zm_S_H(
        SMLAL_SME_ZA_array_off2x2_S_S_SVE_ZnxN_S_H_SME_Zm_S_H,
    ),
    SMLAL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm(SMLAL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm),
    SMLAL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm_INDEX3_10(
        SMLAL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm_INDEX3_10,
    ),
    SMLSLL_SME_ZA_array_off1x4_SME_Znx2_SME_Zm_INDEX3_1(
        SMLSLL_SME_ZA_array_off1x4_SME_Znx2_SME_Zm_INDEX3_1,
    ),
    SMLSLL_SME_ZA_array_off1x4_SME_Znx2_SME_Zm_INDEX4_1(
        SMLSLL_SME_ZA_array_off1x4_SME_Znx2_SME_Zm_INDEX4_1,
    ),
    SMLSLL_SME_ZA_array_off1x4_SME_Znx4_SME_Zm_INDEX3_1(
        SMLSLL_SME_ZA_array_off1x4_SME_Znx4_SME_Zm_INDEX3_1,
    ),
    SMLSLL_SME_ZA_array_off1x4_SME_Znx4_SME_Zm_INDEX4_1(
        SMLSLL_SME_ZA_array_off1x4_SME_Znx4_SME_Zm_INDEX4_1,
    ),
    SMLSLL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm_INDEX3_10(
        SMLSLL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm_INDEX3_10,
    ),
    SMLSLL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm_INDEX4_10(
        SMLSLL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm_INDEX4_10,
    ),
    SMLSL_SME_ZA_array_off2x2_SME_Znx2_SME_Zm_INDEX3_2(
        SMLSL_SME_ZA_array_off2x2_SME_Znx2_SME_Zm_INDEX3_2,
    ),
    SMLSL_SME_ZA_array_off2x2_SME_Znx2_SME_Zmx2(SMLSL_SME_ZA_array_off2x2_SME_Znx2_SME_Zmx2),
    SMLSL_SME_ZA_array_off2x2_SME_Znx4_SME_Zm_INDEX3_2(
        SMLSL_SME_ZA_array_off2x2_SME_Znx4_SME_Zm_INDEX3_2,
    ),
    SMLSL_SME_ZA_array_off2x2_SME_Znx4_SME_Zmx4(SMLSL_SME_ZA_array_off2x2_SME_Znx4_SME_Zmx4),
    SMLSL_SME_ZA_array_off2x2_SVE_ZnxN_SME_Zm(SMLSL_SME_ZA_array_off2x2_SVE_ZnxN_SME_Zm),
    SMLSL_SME_ZA_array_off2x2_S_S_SVE_ZnxN_S_H_SME_Zm_S_H(
        SMLSL_SME_ZA_array_off2x2_S_S_SVE_ZnxN_S_H_SME_Zm_S_H,
    ),
    SMLSL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm(SMLSL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm),
    SMLSL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm_INDEX3_10(
        SMLSL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm_INDEX3_10,
    ),
    SMOPA_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16(
        SMOPA_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16,
    ),
    SMOPA_SME_ZAda_2b_S_S_SVE_Pg3_P_M_SME_Pm_P_M_SVE_Zn_S_H_SVE_Zm_16_S_H(
        SMOPA_SME_ZAda_2b_S_S_SVE_Pg3_P_M_SME_Pm_P_M_SVE_Zn_S_H_SVE_Zm_16_S_H,
    ),
    SMOPA_SME_ZAda_3b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16(
        SMOPA_SME_ZAda_3b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16,
    ),
    SMOPS_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16(
        SMOPS_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16,
    ),
    SMOPS_SME_ZAda_2b_S_S_SVE_Pg3_P_M_SME_Pm_P_M_SVE_Zn_S_H_SVE_Zm_16_S_H(
        SMOPS_SME_ZAda_2b_S_S_SVE_Pg3_P_M_SME_Pm_P_M_SVE_Zn_S_H_SVE_Zm_16_S_H,
    ),
    SMOPS_SME_ZAda_3b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16(
        SMOPS_SME_ZAda_3b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16,
    ),
    SQCVTU_SVE_Zd_SME_Znx2(SQCVTU_SVE_Zd_SME_Znx2),
    SQCVT_SVE_Zd_SME_Znx2(SQCVT_SVE_Zd_SME_Znx2),
    SQRSHRN_SVE_Zd_SME_Znx2_SME_SHRIMM4(SQRSHRN_SVE_Zd_SME_Znx2_SME_SHRIMM4),
    SQRSHRUN_SVE_Zd_SME_Znx2_SME_SHRIMM4(SQRSHRUN_SVE_Zd_SME_Znx2_SME_SHRIMM4),
    SQRSHRU_SVE_Zd_SME_Znx2_SME_SHRIMM4(SQRSHRU_SVE_Zd_SME_Znx2_SME_SHRIMM4),
    SQRSHR_SVE_Zd_SME_Znx2_SME_SHRIMM4(SQRSHR_SVE_Zd_SME_Znx2_SME_SHRIMM4),
    STR_SME_ZT0_SIMD_ADDR_SIMPLE(STR_SME_ZT0_SIMD_ADDR_SIMPLE),
    SUDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2(
        SUDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2,
    ),
    SUDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2(
        SUDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2,
    ),
    SUDOT_SME_ZA_array_off3_0_SVE_ZnxN_SME_Zm(SUDOT_SME_ZA_array_off3_0_SVE_ZnxN_SME_Zm),
    SUDOT_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_B_SME_Zm_S_B(
        SUDOT_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_B_SME_Zm_S_B,
    ),
    SUMLALL_SME_ZA_array_off1x4_SME_Znx2_SME_Zm_INDEX4_1(
        SUMLALL_SME_ZA_array_off1x4_SME_Znx2_SME_Zm_INDEX4_1,
    ),
    SUMLALL_SME_ZA_array_off1x4_SME_Znx4_SME_Zm_INDEX4_1(
        SUMLALL_SME_ZA_array_off1x4_SME_Znx4_SME_Zm_INDEX4_1,
    ),
    SUMLALL_SME_ZA_array_off1x4_SVE_ZnxN_SME_Zm(SUMLALL_SME_ZA_array_off1x4_SVE_ZnxN_SME_Zm),
    SUMLALL_SME_ZA_array_off1x4_S_S_SVE_ZnxN_S_B_SME_Zm_S_B(
        SUMLALL_SME_ZA_array_off1x4_S_S_SVE_ZnxN_S_B_SME_Zm_S_B,
    ),
    SUMLALL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm_INDEX4_10(
        SUMLALL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm_INDEX4_10,
    ),
    SUMOPA_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16(
        SUMOPA_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16,
    ),
    SUMOPA_SME_ZAda_3b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16(
        SUMOPA_SME_ZAda_3b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16,
    ),
    SUMOPS_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16(
        SUMOPS_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16,
    ),
    SUMOPS_SME_ZAda_3b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16(
        SUMOPS_SME_ZAda_3b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16,
    ),
    SUVDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2(
        SUVDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2,
    ),
    SVDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2(
        SVDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2,
    ),
    SVDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX1(
        SVDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX1,
    ),
    SVDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2(
        SVDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2,
    ),
    UDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX1(
        UDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX1,
    ),
    UDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2(
        UDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2,
    ),
    UDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX1(
        UDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX1,
    ),
    UDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2(
        UDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2,
    ),
    UDOT_SME_ZA_array_off3_0_S_S_SME_Znx2_S_B_SME_Zm_INDEX2_S_B(
        UDOT_SME_ZA_array_off3_0_S_S_SME_Znx2_S_B_SME_Zm_INDEX2_S_B,
    ),
    UDOT_SME_ZA_array_off3_0_S_S_SME_Znx2_S_H_SME_Zmx2_S_H(
        UDOT_SME_ZA_array_off3_0_S_S_SME_Znx2_S_H_SME_Zmx2_S_H,
    ),
    UDOT_SME_ZA_array_off3_0_S_S_SME_Znx4_S_B_SME_Zm_INDEX2_S_B(
        UDOT_SME_ZA_array_off3_0_S_S_SME_Znx4_S_B_SME_Zm_INDEX2_S_B,
    ),
    UDOT_SME_ZA_array_off3_0_S_S_SME_Znx4_S_H_SME_Zmx4_S_H(
        UDOT_SME_ZA_array_off3_0_S_S_SME_Znx4_S_H_SME_Zmx4_S_H,
    ),
    UDOT_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_H_SME_Zm_S_H(
        UDOT_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_H_SME_Zm_S_H,
    ),
    UDOT_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_H_SME_Zm_S_H_c1701418(
        UDOT_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_H_SME_Zm_S_H_c1701418,
    ),
    UMLALL_SME_ZA_array_off1x4_SME_Znx2_SME_Zm_INDEX3_1(
        UMLALL_SME_ZA_array_off1x4_SME_Znx2_SME_Zm_INDEX3_1,
    ),
    UMLALL_SME_ZA_array_off1x4_SME_Znx2_SME_Zm_INDEX4_1(
        UMLALL_SME_ZA_array_off1x4_SME_Znx2_SME_Zm_INDEX4_1,
    ),
    UMLALL_SME_ZA_array_off1x4_SME_Znx4_SME_Zm_INDEX3_1(
        UMLALL_SME_ZA_array_off1x4_SME_Znx4_SME_Zm_INDEX3_1,
    ),
    UMLALL_SME_ZA_array_off1x4_SME_Znx4_SME_Zm_INDEX4_1(
        UMLALL_SME_ZA_array_off1x4_SME_Znx4_SME_Zm_INDEX4_1,
    ),
    UMLALL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm_INDEX3_10(
        UMLALL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm_INDEX3_10,
    ),
    UMLALL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm_INDEX4_10(
        UMLALL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm_INDEX4_10,
    ),
    UMLAL_SME_ZA_array_off2x2_SME_Znx2_SME_Zm_INDEX3_2(
        UMLAL_SME_ZA_array_off2x2_SME_Znx2_SME_Zm_INDEX3_2,
    ),
    UMLAL_SME_ZA_array_off2x2_SME_Znx2_SME_Zmx2(UMLAL_SME_ZA_array_off2x2_SME_Znx2_SME_Zmx2),
    UMLAL_SME_ZA_array_off2x2_SME_Znx4_SME_Zm_INDEX3_2(
        UMLAL_SME_ZA_array_off2x2_SME_Znx4_SME_Zm_INDEX3_2,
    ),
    UMLAL_SME_ZA_array_off2x2_SME_Znx4_SME_Zmx4(UMLAL_SME_ZA_array_off2x2_SME_Znx4_SME_Zmx4),
    UMLAL_SME_ZA_array_off2x2_SVE_ZnxN_SME_Zm(UMLAL_SME_ZA_array_off2x2_SVE_ZnxN_SME_Zm),
    UMLAL_SME_ZA_array_off2x2_S_S_SVE_ZnxN_S_H_SME_Zm_S_H(
        UMLAL_SME_ZA_array_off2x2_S_S_SVE_ZnxN_S_H_SME_Zm_S_H,
    ),
    UMLAL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm(UMLAL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm),
    UMLAL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm_INDEX3_10(
        UMLAL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm_INDEX3_10,
    ),
    UMLSLL_SME_ZA_array_off1x4_SME_Znx2_SME_Zm_INDEX3_1(
        UMLSLL_SME_ZA_array_off1x4_SME_Znx2_SME_Zm_INDEX3_1,
    ),
    UMLSLL_SME_ZA_array_off1x4_SME_Znx2_SME_Zm_INDEX4_1(
        UMLSLL_SME_ZA_array_off1x4_SME_Znx2_SME_Zm_INDEX4_1,
    ),
    UMLSLL_SME_ZA_array_off1x4_SME_Znx4_SME_Zm_INDEX3_1(
        UMLSLL_SME_ZA_array_off1x4_SME_Znx4_SME_Zm_INDEX3_1,
    ),
    UMLSLL_SME_ZA_array_off1x4_SME_Znx4_SME_Zm_INDEX4_1(
        UMLSLL_SME_ZA_array_off1x4_SME_Znx4_SME_Zm_INDEX4_1,
    ),
    UMLSLL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm_INDEX3_10(
        UMLSLL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm_INDEX3_10,
    ),
    UMLSLL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm_INDEX4_10(
        UMLSLL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm_INDEX4_10,
    ),
    UMLSL_SME_ZA_array_off2x2_SME_Znx2_SME_Zm_INDEX3_2(
        UMLSL_SME_ZA_array_off2x2_SME_Znx2_SME_Zm_INDEX3_2,
    ),
    UMLSL_SME_ZA_array_off2x2_SME_Znx2_SME_Zmx2(UMLSL_SME_ZA_array_off2x2_SME_Znx2_SME_Zmx2),
    UMLSL_SME_ZA_array_off2x2_SME_Znx4_SME_Zm_INDEX3_2(
        UMLSL_SME_ZA_array_off2x2_SME_Znx4_SME_Zm_INDEX3_2,
    ),
    UMLSL_SME_ZA_array_off2x2_SME_Znx4_SME_Zmx4(UMLSL_SME_ZA_array_off2x2_SME_Znx4_SME_Zmx4),
    UMLSL_SME_ZA_array_off2x2_SVE_ZnxN_SME_Zm(UMLSL_SME_ZA_array_off2x2_SVE_ZnxN_SME_Zm),
    UMLSL_SME_ZA_array_off2x2_S_S_SVE_ZnxN_S_H_SME_Zm_S_H(
        UMLSL_SME_ZA_array_off2x2_S_S_SVE_ZnxN_S_H_SME_Zm_S_H,
    ),
    UMLSL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm(UMLSL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm),
    UMLSL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm_INDEX3_10(
        UMLSL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm_INDEX3_10,
    ),
    UMOPA_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16(
        UMOPA_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16,
    ),
    UMOPA_SME_ZAda_2b_S_S_SVE_Pg3_P_M_SME_Pm_P_M_SVE_Zn_S_B_SVE_Zm_16_S_B(
        UMOPA_SME_ZAda_2b_S_S_SVE_Pg3_P_M_SME_Pm_P_M_SVE_Zn_S_B_SVE_Zm_16_S_B,
    ),
    UMOPA_SME_ZAda_3b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16(
        UMOPA_SME_ZAda_3b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16,
    ),
    UMOPS_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16(
        UMOPS_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16,
    ),
    UMOPS_SME_ZAda_2b_S_S_SVE_Pg3_P_M_SME_Pm_P_M_SVE_Zn_S_B_SVE_Zm_16_S_B(
        UMOPS_SME_ZAda_2b_S_S_SVE_Pg3_P_M_SME_Pm_P_M_SVE_Zn_S_B_SVE_Zm_16_S_B,
    ),
    UMOPS_SME_ZAda_3b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16(
        UMOPS_SME_ZAda_3b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16,
    ),
    UQCVT_SVE_Zd_SME_Znx2(UQCVT_SVE_Zd_SME_Znx2),
    UQRSHRN_SVE_Zd_SME_Znx2_SME_SHRIMM4(UQRSHRN_SVE_Zd_SME_Znx2_SME_SHRIMM4),
    UQRSHR_SVE_Zd_SME_Znx2_SME_SHRIMM4(UQRSHR_SVE_Zd_SME_Znx2_SME_SHRIMM4),
    USDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2(
        USDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2,
    ),
    USDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zmx2(USDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zmx2),
    USDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2(
        USDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2,
    ),
    USDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zmx4(USDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zmx4),
    USDOT_SME_ZA_array_off3_0_SVE_ZnxN_SME_Zm(USDOT_SME_ZA_array_off3_0_SVE_ZnxN_SME_Zm),
    USDOT_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_B_SME_Zm_S_B(
        USDOT_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_B_SME_Zm_S_B,
    ),
    USMLALL_SME_ZA_array_off1x4_SME_Znx2_SME_Zm_INDEX4_1(
        USMLALL_SME_ZA_array_off1x4_SME_Znx2_SME_Zm_INDEX4_1,
    ),
    USMLALL_SME_ZA_array_off1x4_SME_Znx2_SME_Zmx2(USMLALL_SME_ZA_array_off1x4_SME_Znx2_SME_Zmx2),
    USMLALL_SME_ZA_array_off1x4_SME_Znx4_SME_Zm_INDEX4_1(
        USMLALL_SME_ZA_array_off1x4_SME_Znx4_SME_Zm_INDEX4_1,
    ),
    USMLALL_SME_ZA_array_off1x4_SME_Znx4_SME_Zmx4(USMLALL_SME_ZA_array_off1x4_SME_Znx4_SME_Zmx4),
    USMLALL_SME_ZA_array_off1x4_SVE_ZnxN_SME_Zm(USMLALL_SME_ZA_array_off1x4_SVE_ZnxN_SME_Zm),
    USMLALL_SME_ZA_array_off1x4_S_S_SVE_ZnxN_S_B_SME_Zm_S_B(
        USMLALL_SME_ZA_array_off1x4_S_S_SVE_ZnxN_S_B_SME_Zm_S_B,
    ),
    USMLALL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm(USMLALL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm),
    USMLALL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm_INDEX4_10(
        USMLALL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm_INDEX4_10,
    ),
    USMOPA_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16(
        USMOPA_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16,
    ),
    USMOPA_SME_ZAda_3b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16(
        USMOPA_SME_ZAda_3b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16,
    ),
    USMOPS_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16(
        USMOPS_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16,
    ),
    USMOPS_SME_ZAda_3b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16(
        USMOPS_SME_ZAda_3b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16,
    ),
    USVDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2(
        USVDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2,
    ),
    UVDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2(
        UVDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2,
    ),
    UVDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX1(
        UVDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX1,
    ),
    UVDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2(
        UVDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2,
    ),
    UZP_SME_Zdnx2_S_Q_SVE_Zn_S_Q_SVE_Zm_16_S_Q(UZP_SME_Zdnx2_S_Q_SVE_Zn_S_Q_SVE_Zm_16_S_Q),
    UZP_SME_Zdnx4_S_Q_SME_Znx4_S_Q(UZP_SME_Zdnx4_S_Q_SME_Znx4_S_Q),
    ZERO_SME_ZT0_LIST(ZERO_SME_ZT0_LIST),
    ZERO_SME_list_of_64bit_tiles(ZERO_SME_list_of_64bit_tiles),
    ZIP_SME_Zdnx2_S_Q_SVE_Zn_S_Q_SVE_Zm_16_S_Q(ZIP_SME_Zdnx2_S_Q_SVE_Zn_S_Q_SVE_Zm_16_S_Q),
    ZIP_SME_Zdnx4_S_Q_SME_Znx4_S_Q(ZIP_SME_Zdnx4_S_Q_SME_Znx4_S_Q),
}
#[derive(Debug, PartialEq, Eq, Copy, Clone)]
pub enum DP_1SRC {
    AUTDA_Rd_Rn_SP(AUTDA_Rd_Rn_SP),
    AUTDB_Rd_Rn_SP(AUTDB_Rd_Rn_SP),
    AUTDZA_Rd(AUTDZA_Rd),
    AUTDZB_Rd(AUTDZB_Rd),
    AUTIA_Rd_Rn_SP(AUTIA_Rd_Rn_SP),
    AUTIB_Rd_Rn_SP(AUTIB_Rd_Rn_SP),
    AUTIZA_Rd(AUTIZA_Rd),
    AUTIZB_Rd(AUTIZB_Rd),
    CLS_Rd_Rn(CLS_Rd_Rn),
    CLZ_Rd_Rn(CLZ_Rd_Rn),
    PACDA_Rd_Rn_SP(PACDA_Rd_Rn_SP),
    PACDB_Rd_Rn_SP(PACDB_Rd_Rn_SP),
    PACDZA_Rd(PACDZA_Rd),
    PACDZB_Rd(PACDZB_Rd),
    PACIA_Rd_Rn_SP(PACIA_Rd_Rn_SP),
    PACIB_Rd_Rn_SP(PACIB_Rd_Rn_SP),
    PACIZA_Rd(PACIZA_Rd),
    PACIZB_Rd(PACIZB_Rd),
    RBIT_Rd_Rn(RBIT_Rd_Rn),
    REV16_Rd_Rn(REV16_Rd_Rn),
    REV32_Rd_Rn(REV32_Rd_Rn),
    REV_Rd_Rn(REV_Rd_Rn),
    REV_Rd_X_Rn_X(REV_Rd_X_Rn_X),
    XPACD_Rd(XPACD_Rd),
    XPACI_Rd(XPACI_Rd),
}
#[derive(Debug, PartialEq, Eq, Copy, Clone)]
pub enum CRYPTOAES {
    AESD_Vd_Vn(AESD_Vd_Vn),
    AESE_Vd_Vn(AESE_Vd_Vn),
    AESIMC_Vd_Vn(AESIMC_Vd_Vn),
    AESMC_Vd_Vn(AESMC_Vd_Vn),
}
#[derive(Debug, PartialEq, Eq, Copy, Clone)]
pub enum SVE_MISC {
    ADDPL_Rd_SP_SVE_Rn_SP_SVE_SIMM6(ADDPL_Rd_SP_SVE_Rn_SP_SVE_SIMM6),
    ADDVL_Rd_SP_SVE_Rn_SP_SVE_SIMM6(ADDVL_Rd_SP_SVE_Rn_SP_SVE_SIMM6),
    ADR_SVE_Zd_SVE_ADDR_ZZ_SXTW(ADR_SVE_Zd_SVE_ADDR_ZZ_SXTW),
    ADR_SVE_Zd_SVE_ADDR_ZZ_UXTW(ADR_SVE_Zd_SVE_ADDR_ZZ_UXTW),
    AESD_SVE_Zd_SVE_Zd_SVE_Zn(AESD_SVE_Zd_SVE_Zd_SVE_Zn),
    AESE_SVE_Zd_SVE_Zd_SVE_Zn(AESE_SVE_Zd_SVE_Zd_SVE_Zn),
    AESIMC_SVE_Zd_SVE_Zd(AESIMC_SVE_Zd_SVE_Zd),
    AESMC_SVE_Zd_SVE_Zd(AESMC_SVE_Zd_SVE_Zd),
    ANDS_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm(ANDS_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm),
    AND_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm(AND_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm),
    AND_SVE_Zd_SVE_Zn_SVE_Zm_16(AND_SVE_Zd_SVE_Zn_SVE_Zm_16),
    BCAX_SVE_Zd_SVE_Zd_SVE_Zm_16_SVE_Zn(BCAX_SVE_Zd_SVE_Zd_SVE_Zm_16_SVE_Zn),
    BFADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(BFADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5),
    BFADD_SVE_Zd_SVE_Zn_SVE_Zm_16(BFADD_SVE_Zd_SVE_Zn_SVE_Zm_16),
    BFCLAMP_SVE_Zd_SVE_Zn_SVE_Zm_16(BFCLAMP_SVE_Zd_SVE_Zn_SVE_Zm_16),
    BFCVTNT_SVE_Zd_SVE_Pg3_SVE_Zn(BFCVTNT_SVE_Zd_SVE_Pg3_SVE_Zn),
    BFCVT_SVE_Zd_SVE_Pg3_SVE_Zn(BFCVT_SVE_Zd_SVE_Pg3_SVE_Zn),
    BFDOT_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX(BFDOT_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX),
    BFDOT_SVE_Zd_SVE_Zn_SVE_Zm_16(BFDOT_SVE_Zd_SVE_Zn_SVE_Zm_16),
    BFMAXNM_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(BFMAXNM_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5),
    BFMAX_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(BFMAX_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5),
    BFMINNM_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(BFMINNM_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5),
    BFMIN_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(BFMIN_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5),
    BFMLALB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX(BFMLALB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX),
    BFMLALB_SVE_Zd_SVE_Zn_SVE_Zm_16(BFMLALB_SVE_Zd_SVE_Zn_SVE_Zm_16),
    BFMLALT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX(BFMLALT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX),
    BFMLALT_SVE_Zd_SVE_Zn_SVE_Zm_16(BFMLALT_SVE_Zd_SVE_Zn_SVE_Zm_16),
    BFMLA_SVE_Zd_SVE_Pg3_SVE_Zn_SVE_Zm_16(BFMLA_SVE_Zd_SVE_Pg3_SVE_Zn_SVE_Zm_16),
    BFMLA_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX(BFMLA_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX),
    BFMLSLB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX(BFMLSLB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX),
    BFMLSLB_SVE_Zd_SVE_Zn_SVE_Zm_16(BFMLSLB_SVE_Zd_SVE_Zn_SVE_Zm_16),
    BFMLSLT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX(BFMLSLT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX),
    BFMLSLT_SVE_Zd_SVE_Zn_SVE_Zm_16(BFMLSLT_SVE_Zd_SVE_Zn_SVE_Zm_16),
    BFMLS_SVE_Zd_SVE_Pg3_SVE_Zn_SVE_Zm_16(BFMLS_SVE_Zd_SVE_Pg3_SVE_Zn_SVE_Zm_16),
    BFMLS_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX(BFMLS_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX),
    BFMMLA_SVE_Zd_SVE_Zn_SVE_Zm_16(BFMMLA_SVE_Zd_SVE_Zn_SVE_Zm_16),
    BFMUL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(BFMUL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5),
    BFMUL_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX(BFMUL_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX),
    BFMUL_SVE_Zd_SVE_Zn_SVE_Zm_16(BFMUL_SVE_Zd_SVE_Zn_SVE_Zm_16),
    BFSUB_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(BFSUB_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5),
    BFSUB_SVE_Zd_SVE_Zn_SVE_Zm_16(BFSUB_SVE_Zd_SVE_Zn_SVE_Zm_16),
    BICS_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm(BICS_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm),
    BIC_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm(BIC_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm),
    BIC_SVE_Zd_SVE_Zn_SVE_Zm_16(BIC_SVE_Zd_SVE_Zn_SVE_Zm_16),
    BRKAS_SVE_Pd_SVE_Pg4_10_SVE_Pn(BRKAS_SVE_Pd_SVE_Pg4_10_SVE_Pn),
    BRKBS_SVE_Pd_SVE_Pg4_10_SVE_Pn(BRKBS_SVE_Pd_SVE_Pg4_10_SVE_Pn),
    BRKNS_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pd(BRKNS_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pd),
    BRKN_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pd(BRKN_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pd),
    BRKPAS_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm(BRKPAS_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm),
    BRKPA_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm(BRKPA_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm),
    BRKPBS_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm(BRKPBS_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm),
    BRKPB_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm(BRKPB_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm),
    BSL1N_SVE_Zd_SVE_Zd_SVE_Zm_16_SVE_Zn(BSL1N_SVE_Zd_SVE_Zd_SVE_Zm_16_SVE_Zn),
    BSL2N_SVE_Zd_SVE_Zd_SVE_Zm_16_SVE_Zn(BSL2N_SVE_Zd_SVE_Zd_SVE_Zm_16_SVE_Zn),
    BSL_SVE_Zd_SVE_Zd_SVE_Zm_16_SVE_Zn(BSL_SVE_Zd_SVE_Zd_SVE_Zm_16_SVE_Zn),
    CDOT_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX_SVE_IMM_ROT2(CDOT_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX_SVE_IMM_ROT2),
    CDOT_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX_SVE_IMM_ROT2(CDOT_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX_SVE_IMM_ROT2),
    CMLA_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX_SVE_IMM_ROT2(CMLA_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX_SVE_IMM_ROT2),
    CMLA_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX_SVE_IMM_ROT2(CMLA_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX_SVE_IMM_ROT2),
    CNTB_Rd_SVE_PATTERN_SCALED(CNTB_Rd_SVE_PATTERN_SCALED),
    CNTD_Rd_SVE_PATTERN_SCALED(CNTD_Rd_SVE_PATTERN_SCALED),
    CNTH_Rd_SVE_PATTERN_SCALED(CNTH_Rd_SVE_PATTERN_SCALED),
    CNTW_Rd_SVE_PATTERN_SCALED(CNTW_Rd_SVE_PATTERN_SCALED),
    DECB_Rd_SVE_PATTERN_SCALED(DECB_Rd_SVE_PATTERN_SCALED),
    DECD_Rd_SVE_PATTERN_SCALED(DECD_Rd_SVE_PATTERN_SCALED),
    DECD_SVE_Zd_SVE_PATTERN_SCALED(DECD_SVE_Zd_SVE_PATTERN_SCALED),
    DECH_Rd_SVE_PATTERN_SCALED(DECH_Rd_SVE_PATTERN_SCALED),
    DECH_SVE_Zd_SVE_PATTERN_SCALED(DECH_SVE_Zd_SVE_PATTERN_SCALED),
    DECW_Rd_SVE_PATTERN_SCALED(DECW_Rd_SVE_PATTERN_SCALED),
    DECW_SVE_Zd_SVE_PATTERN_SCALED(DECW_SVE_Zd_SVE_PATTERN_SCALED),
    EOR3_SVE_Zd_SVE_Zd_SVE_Zm_16_SVE_Zn(EOR3_SVE_Zd_SVE_Zd_SVE_Zm_16_SVE_Zn),
    EORS_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm(EORS_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm),
    EOR_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm(EOR_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm),
    EOR_SVE_Zd_SVE_Zn_SVE_Zm_16(EOR_SVE_Zd_SVE_Zn_SVE_Zm_16),
    EXTQ_SVE_Zd_SVE_Zd_SVE_Zm_imm4(EXTQ_SVE_Zd_SVE_Zd_SVE_Zm_imm4),
    EXT_SVE_Zd_SVE_Zd_SVE_Zm_5_SVE_UIMM8_53(EXT_SVE_Zd_SVE_Zd_SVE_Zm_5_SVE_UIMM8_53),
    EXT_SVE_Zd_SVE_ZnxN_SVE_UIMM8_53(EXT_SVE_Zd_SVE_ZnxN_SVE_UIMM8_53),
    FCMLA_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX_SVE_IMM_ROT2(FCMLA_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX_SVE_IMM_ROT2),
    FCMLA_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX_SVE_IMM_ROT2(FCMLA_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX_SVE_IMM_ROT2),
    FCVTLT_SVE_Zd_SVE_Pg3_SVE_Zn(FCVTLT_SVE_Zd_SVE_Pg3_SVE_Zn),
    FCVTLT_SVE_Zd_S_D_SVE_Pg3_P_M_SVE_Zn_S_S(FCVTLT_SVE_Zd_S_D_SVE_Pg3_P_M_SVE_Zn_S_S),
    FCVTNT_SVE_Zd_SVE_Pg3_SVE_Zn(FCVTNT_SVE_Zd_SVE_Pg3_SVE_Zn),
    FCVTNT_SVE_Zd_S_S_SVE_Pg3_P_M_SVE_Zn_S_D(FCVTNT_SVE_Zd_S_S_SVE_Pg3_P_M_SVE_Zn_S_D),
    FCVTN_SVE_Zd_SME_Znx2(FCVTN_SVE_Zd_SME_Znx2),
    FCVTXNT_SVE_Zd_SVE_Pg3_SVE_Zn(FCVTXNT_SVE_Zd_SVE_Pg3_SVE_Zn),
    FCVTX_SVE_Zd_SVE_Pg3_SVE_Zn(FCVTX_SVE_Zd_SVE_Pg3_SVE_Zn),
    FCVTZS_SME_Zdnx2_SME_Znx2(FCVTZS_SME_Zdnx2_SME_Znx2),
    FCVTZS_SME_Zdnx4_SME_Znx4(FCVTZS_SME_Zdnx4_SME_Znx4),
    FCVTZS_SVE_Zd_SVE_Pg3_SVE_Zn(FCVTZS_SVE_Zd_SVE_Pg3_SVE_Zn),
    FCVTZS_SVE_Zd_S_D_SVE_Pg3_P_M_SVE_Zn_S_D(FCVTZS_SVE_Zd_S_D_SVE_Pg3_P_M_SVE_Zn_S_D),
    FCVTZS_SVE_Zd_S_D_SVE_Pg3_P_M_SVE_Zn_S_H(FCVTZS_SVE_Zd_S_D_SVE_Pg3_P_M_SVE_Zn_S_H),
    FCVTZS_SVE_Zd_S_D_SVE_Pg3_P_M_SVE_Zn_S_S(FCVTZS_SVE_Zd_S_D_SVE_Pg3_P_M_SVE_Zn_S_S),
    FCVTZS_SVE_Zd_S_H_SVE_Pg3_P_M_SVE_Zn_S_H(FCVTZS_SVE_Zd_S_H_SVE_Pg3_P_M_SVE_Zn_S_H),
    FCVTZS_SVE_Zd_S_S_SVE_Pg3_P_M_SVE_Zn_S_D(FCVTZS_SVE_Zd_S_S_SVE_Pg3_P_M_SVE_Zn_S_D),
    FCVTZS_SVE_Zd_S_S_SVE_Pg3_P_M_SVE_Zn_S_H(FCVTZS_SVE_Zd_S_S_SVE_Pg3_P_M_SVE_Zn_S_H),
    FCVTZU_SME_Zdnx2_SME_Znx2(FCVTZU_SME_Zdnx2_SME_Znx2),
    FCVTZU_SME_Zdnx4_SME_Znx4(FCVTZU_SME_Zdnx4_SME_Znx4),
    FCVTZU_SVE_Zd_SVE_Pg3_SVE_Zn(FCVTZU_SVE_Zd_SVE_Pg3_SVE_Zn),
    FCVTZU_SVE_Zd_S_D_SVE_Pg3_P_M_SVE_Zn_S_D(FCVTZU_SVE_Zd_S_D_SVE_Pg3_P_M_SVE_Zn_S_D),
    FCVTZU_SVE_Zd_S_D_SVE_Pg3_P_M_SVE_Zn_S_H(FCVTZU_SVE_Zd_S_D_SVE_Pg3_P_M_SVE_Zn_S_H),
    FCVTZU_SVE_Zd_S_D_SVE_Pg3_P_M_SVE_Zn_S_S(FCVTZU_SVE_Zd_S_D_SVE_Pg3_P_M_SVE_Zn_S_S),
    FCVTZU_SVE_Zd_S_H_SVE_Pg3_P_M_SVE_Zn_S_H(FCVTZU_SVE_Zd_S_H_SVE_Pg3_P_M_SVE_Zn_S_H),
    FCVTZU_SVE_Zd_S_S_SVE_Pg3_P_M_SVE_Zn_S_H(FCVTZU_SVE_Zd_S_S_SVE_Pg3_P_M_SVE_Zn_S_H),
    FCVTZU_SVE_Zd_S_S_SVE_Pg3_P_M_SVE_Zn_S_S(FCVTZU_SVE_Zd_S_S_SVE_Pg3_P_M_SVE_Zn_S_S),
    FCVT_SVE_Zd_SME_Znx2(FCVT_SVE_Zd_SME_Znx2),
    FCVT_SVE_Zd_SVE_Pg3_SVE_Zn(FCVT_SVE_Zd_SVE_Pg3_SVE_Zn),
    FCVT_SVE_Zd_S_D_SVE_Pg3_P_M_SVE_Zn_S_H(FCVT_SVE_Zd_S_D_SVE_Pg3_P_M_SVE_Zn_S_H),
    FCVT_SVE_Zd_S_D_SVE_Pg3_P_M_SVE_Zn_S_S(FCVT_SVE_Zd_S_D_SVE_Pg3_P_M_SVE_Zn_S_S),
    FCVT_SVE_Zd_S_H_SVE_Pg3_P_M_SVE_Zn_S_D(FCVT_SVE_Zd_S_H_SVE_Pg3_P_M_SVE_Zn_S_D),
    FCVT_SVE_Zd_S_S_SVE_Pg3_P_M_SVE_Zn_S_D(FCVT_SVE_Zd_S_S_SVE_Pg3_P_M_SVE_Zn_S_D),
    FCVT_SVE_Zd_S_S_SVE_Pg3_P_M_SVE_Zn_S_H(FCVT_SVE_Zd_S_S_SVE_Pg3_P_M_SVE_Zn_S_H),
    FDOT_SVE_Zd_SVE_Zn_SVE_Zm3_19_INDEX(FDOT_SVE_Zd_SVE_Zn_SVE_Zm3_19_INDEX),
    FDOT_SVE_Zd_SVE_Zn_SVE_Zm_16(FDOT_SVE_Zd_SVE_Zn_SVE_Zm_16),
    FMLALB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX(FMLALB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX),
    FMLALB_SVE_Zd_SVE_Zn_SVE_Zm_16(FMLALB_SVE_Zd_SVE_Zn_SVE_Zm_16),
    FMLALT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX(FMLALT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX),
    FMLALT_SVE_Zd_SVE_Zn_SVE_Zm_16(FMLALT_SVE_Zd_SVE_Zn_SVE_Zm_16),
    FMLA_SVE_Zd_SVE_Zn_SVE_Zm3_22_INDEX(FMLA_SVE_Zd_SVE_Zn_SVE_Zm3_22_INDEX),
    FMLA_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX(FMLA_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX),
    FMLA_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX(FMLA_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX),
    FMLSLB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX(FMLSLB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX),
    FMLSLB_SVE_Zd_SVE_Zn_SVE_Zm_16(FMLSLB_SVE_Zd_SVE_Zn_SVE_Zm_16),
    FMLSLT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX(FMLSLT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX),
    FMLSLT_SVE_Zd_SVE_Zn_SVE_Zm_16(FMLSLT_SVE_Zd_SVE_Zn_SVE_Zm_16),
    FMLS_SVE_Zd_SVE_Zn_SVE_Zm3_22_INDEX(FMLS_SVE_Zd_SVE_Zn_SVE_Zm3_22_INDEX),
    FMLS_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX(FMLS_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX),
    FMLS_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX(FMLS_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX),
    FMMLA_SVE_Zd_SVE_Zn_SVE_Zm_16(FMMLA_SVE_Zd_SVE_Zn_SVE_Zm_16),
    FMMLA_SVE_Zd_S_D_SVE_Zn_S_D_SVE_Zm_16_S_D(FMMLA_SVE_Zd_S_D_SVE_Zn_S_D_SVE_Zm_16_S_D),
    FMUL_SVE_Zd_SVE_Zn_SVE_Zm3_22_INDEX(FMUL_SVE_Zd_SVE_Zn_SVE_Zm3_22_INDEX),
    FMUL_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX(FMUL_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX),
    FMUL_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX(FMUL_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX),
    FRINTA_SME_Zdnx2_SME_Znx2(FRINTA_SME_Zdnx2_SME_Znx2),
    FRINTA_SME_Zdnx4_SME_Znx4(FRINTA_SME_Zdnx4_SME_Znx4),
    FRINTM_SME_Zdnx2_SME_Znx2(FRINTM_SME_Zdnx2_SME_Znx2),
    FRINTM_SME_Zdnx4_SME_Znx4(FRINTM_SME_Zdnx4_SME_Znx4),
    FRINTN_SME_Zdnx2_SME_Znx2(FRINTN_SME_Zdnx2_SME_Znx2),
    FRINTN_SME_Zdnx4_SME_Znx4(FRINTN_SME_Zdnx4_SME_Znx4),
    FRINTP_SME_Zdnx2_SME_Znx2(FRINTP_SME_Zdnx2_SME_Znx2),
    FRINTP_SME_Zdnx4_SME_Znx4(FRINTP_SME_Zdnx4_SME_Znx4),
    HISTSEG_SVE_Zd_SVE_Zn_SVE_Zm_16(HISTSEG_SVE_Zd_SVE_Zn_SVE_Zm_16),
    INCB_Rd_SVE_PATTERN_SCALED(INCB_Rd_SVE_PATTERN_SCALED),
    INCD_Rd_SVE_PATTERN_SCALED(INCD_Rd_SVE_PATTERN_SCALED),
    INCD_SVE_Zd_SVE_PATTERN_SCALED(INCD_SVE_Zd_SVE_PATTERN_SCALED),
    INCH_Rd_SVE_PATTERN_SCALED(INCH_Rd_SVE_PATTERN_SCALED),
    INCH_SVE_Zd_SVE_PATTERN_SCALED(INCH_SVE_Zd_SVE_PATTERN_SCALED),
    INCW_Rd_SVE_PATTERN_SCALED(INCW_Rd_SVE_PATTERN_SCALED),
    INCW_SVE_Zd_SVE_PATTERN_SCALED(INCW_SVE_Zd_SVE_PATTERN_SCALED),
    LD1B_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_R(LD1B_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_R),
    LD1B_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_RR(LD1B_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_RR),
    LD1B_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL(LD1B_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL),
    LD1B_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR(LD1B_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR),
    LD1B_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL(LD1B_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL),
    LD1B_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR(LD1B_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR),
    LD1B_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL(
        LD1B_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL,
    ),
    LD1B_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR(LD1B_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR),
    LD1B_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL(
        LD1B_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL,
    ),
    LD1B_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR(LD1B_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR),
    LD1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL(LD1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL),
    LD1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX(LD1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX),
    LD1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ(LD1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ),
    LD1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22(LD1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22),
    LD1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5(LD1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5),
    LD1B_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL(
        LD1B_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL,
    ),
    LD1B_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RX(LD1B_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RX),
    LD1B_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW_22_S_D(
        LD1B_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW_22_S_D,
    ),
    LD1B_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_ZI_U5_S_D(
        LD1B_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_ZI_U5_S_D,
    ),
    LD1B_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL(
        LD1B_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL,
    ),
    LD1B_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RX(LD1B_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RX),
    LD1B_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL(
        LD1B_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL,
    ),
    LD1B_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RX(LD1B_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RX),
    LD1D_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_R(LD1D_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_R),
    LD1D_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_RR_LSL3(
        LD1D_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_RR_LSL3,
    ),
    LD1D_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL(LD1D_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL),
    LD1D_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR_LSL3(LD1D_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR_LSL3),
    LD1D_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL(LD1D_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL),
    LD1D_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR_LSL3(LD1D_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR_LSL3),
    LD1D_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL(
        LD1D_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL,
    ),
    LD1D_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL3(
        LD1D_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL3,
    ),
    LD1D_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL(
        LD1D_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL,
    ),
    LD1D_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL3(
        LD1D_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL3,
    ),
    LD1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL(LD1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL),
    LD1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL3(LD1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL3),
    LD1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ(LD1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ),
    LD1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL3(LD1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL3),
    LD1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW3_22(LD1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW3_22),
    LD1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22(LD1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22),
    LD1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x8(LD1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x8),
    LD1H_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_R(LD1H_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_R),
    LD1H_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_RR_LSL1(
        LD1H_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_RR_LSL1,
    ),
    LD1H_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL(LD1H_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL),
    LD1H_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR_LSL1(LD1H_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR_LSL1),
    LD1H_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL(LD1H_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL),
    LD1H_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR_LSL1(LD1H_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR_LSL1),
    LD1H_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL(
        LD1H_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL,
    ),
    LD1H_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL1(
        LD1H_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL1,
    ),
    LD1H_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL(
        LD1H_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL,
    ),
    LD1H_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL1(
        LD1H_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL1,
    ),
    LD1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL(LD1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL),
    LD1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1(LD1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1),
    LD1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ(LD1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ),
    LD1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL1(LD1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL1),
    LD1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW1_22(LD1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW1_22),
    LD1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22(LD1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22),
    LD1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x2(LD1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x2),
    LD1H_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL(
        LD1H_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL,
    ),
    LD1H_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RX_LSL1(LD1H_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RX_LSL1),
    LD1H_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW1_22_S_D(
        LD1H_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW1_22_S_D,
    ),
    LD1H_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW_22_S_D(
        LD1H_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW_22_S_D,
    ),
    LD1H_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_ZI_U5x2_S_D(
        LD1H_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_ZI_U5x2_S_D,
    ),
    LD1H_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL(
        LD1H_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL,
    ),
    LD1H_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RX_LSL1(LD1H_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RX_LSL1),
    LD1Q_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_R(LD1Q_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_R),
    LD1Q_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_RR_LSL4(
        LD1Q_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_RR_LSL4,
    ),
    LD1Q_SVE_Zt_SVE_Pg3_SVE_ADDR_ZX(LD1Q_SVE_Zt_SVE_Pg3_SVE_ADDR_ZX),
    LD1RB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_U6(LD1RB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_U6),
    LD1RB_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RI_U6(LD1RB_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RI_U6),
    LD1RB_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RI_U6(LD1RB_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RI_U6),
    LD1RB_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RI_U6(LD1RB_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RI_U6),
    LD1RD_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_U6x8(LD1RD_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_U6x8),
    LD1RH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_U6x2(LD1RH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_U6x2),
    LD1RH_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RI_U6x2(
        LD1RH_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RI_U6x2,
    ),
    LD1RH_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RI_U6x2(
        LD1RH_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RI_U6x2,
    ),
    LD1ROB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x32(LD1ROB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x32),
    LD1ROB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX(LD1ROB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX),
    LD1ROD_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x32(LD1ROD_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x32),
    LD1ROD_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL3(LD1ROD_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL3),
    LD1ROH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x32(LD1ROH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x32),
    LD1ROH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1(LD1ROH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1),
    LD1ROW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x32(LD1ROW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x32),
    LD1ROW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2(LD1ROW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2),
    LD1RQB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x16(LD1RQB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x16),
    LD1RQB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX(LD1RQB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX),
    LD1RQD_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x16(LD1RQD_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x16),
    LD1RQD_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL3(LD1RQD_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL3),
    LD1RQH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x16(LD1RQH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x16),
    LD1RQH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1(LD1RQH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1),
    LD1RQW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x16(LD1RQW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x16),
    LD1RQW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2(LD1RQW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2),
    LD1RSB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_U6(LD1RSB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_U6),
    LD1RSB_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RI_U6(LD1RSB_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RI_U6),
    LD1RSB_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RI_U6(LD1RSB_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RI_U6),
    LD1RSH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_U6x2(LD1RSH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_U6x2),
    LD1RSH_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RI_U6x2(
        LD1RSH_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RI_U6x2,
    ),
    LD1RSW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_U6x4(LD1RSW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_U6x4),
    LD1RW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_U6x4(LD1RW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_U6x4),
    LD1RW_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RI_U6x4(
        LD1RW_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RI_U6x4,
    ),
    LD1SB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL(LD1SB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL),
    LD1SB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX(LD1SB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX),
    LD1SB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ(LD1SB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ),
    LD1SB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22(LD1SB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22),
    LD1SB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5(LD1SB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5),
    LD1SB_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW_22_S_D(
        LD1SB_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW_22_S_D,
    ),
    LD1SB_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_ZI_U5_S_D(
        LD1SB_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_ZI_U5_S_D,
    ),
    LD1SB_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL(
        LD1SB_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL,
    ),
    LD1SB_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RX(LD1SB_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RX),
    LD1SB_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL(
        LD1SB_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL,
    ),
    LD1SB_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RX(LD1SB_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RX),
    LD1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL(LD1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL),
    LD1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1(LD1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1),
    LD1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ(LD1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ),
    LD1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL1(LD1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL1),
    LD1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW1_22(LD1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW1_22),
    LD1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22(LD1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22),
    LD1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x2(LD1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x2),
    LD1SH_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW1_22_S_D(
        LD1SH_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW1_22_S_D,
    ),
    LD1SH_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW_22_S_D(
        LD1SH_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW_22_S_D,
    ),
    LD1SH_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_ZI_U5x2_S_D(
        LD1SH_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_ZI_U5x2_S_D,
    ),
    LD1SH_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL(
        LD1SH_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL,
    ),
    LD1SH_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RX_LSL1(
        LD1SH_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RX_LSL1,
    ),
    LD1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL(LD1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL),
    LD1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2(LD1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2),
    LD1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ(LD1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ),
    LD1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL2(LD1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL2),
    LD1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW2_22(LD1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW2_22),
    LD1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22(LD1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22),
    LD1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x4(LD1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x4),
    LD1W_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_R(LD1W_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_R),
    LD1W_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_RR_LSL2(
        LD1W_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_RR_LSL2,
    ),
    LD1W_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL(LD1W_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL),
    LD1W_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR_LSL2(LD1W_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR_LSL2),
    LD1W_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL(LD1W_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL),
    LD1W_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR_LSL2(LD1W_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR_LSL2),
    LD1W_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL(
        LD1W_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL,
    ),
    LD1W_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL2(
        LD1W_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL2,
    ),
    LD1W_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL(
        LD1W_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL,
    ),
    LD1W_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL2(
        LD1W_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL2,
    ),
    LD1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL(LD1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL),
    LD1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2(LD1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2),
    LD1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ(LD1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ),
    LD1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL2(LD1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL2),
    LD1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW2_22(LD1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW2_22),
    LD1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22(LD1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22),
    LD1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x4(LD1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x4),
    LD1W_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL(
        LD1W_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL,
    ),
    LD1W_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RX_LSL2(LD1W_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RX_LSL2),
    LD1W_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW2_22_S_D(
        LD1W_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW2_22_S_D,
    ),
    LD1W_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW_22_S_D(
        LD1W_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW_22_S_D,
    ),
    LD1W_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_ZI_U5x4_S_D(
        LD1W_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_ZI_U5x4_S_D,
    ),
    LD2B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x2xVL(LD2B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x2xVL),
    LD2B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX(LD2B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX),
    LD2D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x2xVL(LD2D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x2xVL),
    LD2D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL3(LD2D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL3),
    LD2H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x2xVL(LD2H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x2xVL),
    LD2H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1(LD2H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1),
    LD2Q_SME_Zt2_SVE_Pg3_SVE_ADDR_RI_S4x2xVL(LD2Q_SME_Zt2_SVE_Pg3_SVE_ADDR_RI_S4x2xVL),
    LD2Q_SME_Zt2_SVE_Pg3_SVE_ADDR_RR_LSL4(LD2Q_SME_Zt2_SVE_Pg3_SVE_ADDR_RR_LSL4),
    LD2W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x2xVL(LD2W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x2xVL),
    LD2W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2(LD2W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2),
    LD3B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x3xVL(LD3B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x3xVL),
    LD3B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX(LD3B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX),
    LD3D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x3xVL(LD3D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x3xVL),
    LD3D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL3(LD3D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL3),
    LD3H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x3xVL(LD3H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x3xVL),
    LD3H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1(LD3H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1),
    LD3Q_SME_Zt3_SVE_Pg3_SVE_ADDR_RI_S4x2xVL(LD3Q_SME_Zt3_SVE_Pg3_SVE_ADDR_RI_S4x2xVL),
    LD3Q_SME_Zt3_SVE_Pg3_SVE_ADDR_RR_LSL4(LD3Q_SME_Zt3_SVE_Pg3_SVE_ADDR_RR_LSL4),
    LD3W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x3xVL(LD3W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x3xVL),
    LD3W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2(LD3W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2),
    LD4B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x4xVL(LD4B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x4xVL),
    LD4B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX(LD4B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX),
    LD4D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x4xVL(LD4D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x4xVL),
    LD4D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL3(LD4D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL3),
    LD4H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x4xVL(LD4H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x4xVL),
    LD4H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1(LD4H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1),
    LD4Q_SME_Zt4_SVE_Pg3_SVE_ADDR_RI_S4x2xVL(LD4Q_SME_Zt4_SVE_Pg3_SVE_ADDR_RI_S4x2xVL),
    LD4Q_SME_Zt4_SVE_Pg3_SVE_ADDR_RR_LSL4(LD4Q_SME_Zt4_SVE_Pg3_SVE_ADDR_RR_LSL4),
    LD4W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x4xVL(LD4W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x4xVL),
    LD4W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2(LD4W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2),
    LDFF1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_R(LDFF1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_R),
    LDFF1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RR(LDFF1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RR),
    LDFF1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ(LDFF1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ),
    LDFF1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22(LDFF1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22),
    LDFF1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5(LDFF1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5),
    LDFF1B_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_R(LDFF1B_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_R),
    LDFF1B_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RR(LDFF1B_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RR),
    LDFF1B_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW_22_S_D(
        LDFF1B_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW_22_S_D,
    ),
    LDFF1B_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_ZI_U5_S_D(
        LDFF1B_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_ZI_U5_S_D,
    ),
    LDFF1B_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_R(LDFF1B_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_R),
    LDFF1B_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RR(LDFF1B_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RR),
    LDFF1B_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_R(LDFF1B_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_R),
    LDFF1B_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RR(LDFF1B_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RR),
    LDFF1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_R(LDFF1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_R),
    LDFF1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RR_LSL3(LDFF1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RR_LSL3),
    LDFF1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ(LDFF1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ),
    LDFF1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL3(LDFF1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL3),
    LDFF1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW3_22(LDFF1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW3_22),
    LDFF1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22(LDFF1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22),
    LDFF1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x8(LDFF1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x8),
    LDFF1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_R(LDFF1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_R),
    LDFF1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RR_LSL1(LDFF1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RR_LSL1),
    LDFF1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ(LDFF1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ),
    LDFF1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL1(LDFF1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL1),
    LDFF1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW1_22(LDFF1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW1_22),
    LDFF1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22(LDFF1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22),
    LDFF1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x2(LDFF1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x2),
    LDFF1H_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_R(LDFF1H_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_R),
    LDFF1H_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RR_LSL1(
        LDFF1H_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RR_LSL1,
    ),
    LDFF1H_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW1_22_S_D(
        LDFF1H_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW1_22_S_D,
    ),
    LDFF1H_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW_22_S_D(
        LDFF1H_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW_22_S_D,
    ),
    LDFF1H_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_ZI_U5x2_S_D(
        LDFF1H_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_ZI_U5x2_S_D,
    ),
    LDFF1H_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_R(LDFF1H_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_R),
    LDFF1H_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RR_LSL1(
        LDFF1H_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RR_LSL1,
    ),
    LDFF1SB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_R(LDFF1SB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_R),
    LDFF1SB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RR(LDFF1SB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RR),
    LDFF1SB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ(LDFF1SB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ),
    LDFF1SB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22(LDFF1SB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22),
    LDFF1SB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5(LDFF1SB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5),
    LDFF1SB_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW_22_S_D(
        LDFF1SB_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW_22_S_D,
    ),
    LDFF1SB_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_ZI_U5_S_D(
        LDFF1SB_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_ZI_U5_S_D,
    ),
    LDFF1SB_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_R(LDFF1SB_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_R),
    LDFF1SB_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RR(LDFF1SB_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RR),
    LDFF1SB_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_R(LDFF1SB_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_R),
    LDFF1SB_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RR(LDFF1SB_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RR),
    LDFF1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_R(LDFF1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_R),
    LDFF1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RR_LSL1(LDFF1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RR_LSL1),
    LDFF1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ(LDFF1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ),
    LDFF1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL1(LDFF1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL1),
    LDFF1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW1_22(LDFF1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW1_22),
    LDFF1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22(LDFF1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22),
    LDFF1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x2(LDFF1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x2),
    LDFF1SH_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW1_22_S_D(
        LDFF1SH_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW1_22_S_D,
    ),
    LDFF1SH_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW_22_S_D(
        LDFF1SH_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW_22_S_D,
    ),
    LDFF1SH_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_ZI_U5x2_S_D(
        LDFF1SH_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_ZI_U5x2_S_D,
    ),
    LDFF1SH_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_R(LDFF1SH_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_R),
    LDFF1SH_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RR_LSL1(
        LDFF1SH_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RR_LSL1,
    ),
    LDFF1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_R(LDFF1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_R),
    LDFF1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RR_LSL2(LDFF1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RR_LSL2),
    LDFF1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ(LDFF1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ),
    LDFF1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL2(LDFF1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL2),
    LDFF1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW2_22(LDFF1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW2_22),
    LDFF1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22(LDFF1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22),
    LDFF1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x4(LDFF1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x4),
    LDFF1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_R(LDFF1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_R),
    LDFF1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RR_LSL2(LDFF1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RR_LSL2),
    LDFF1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ(LDFF1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ),
    LDFF1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL2(LDFF1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL2),
    LDFF1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW2_22(LDFF1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW2_22),
    LDFF1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22(LDFF1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22),
    LDFF1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x4(LDFF1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x4),
    LDFF1W_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_R(LDFF1W_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_R),
    LDFF1W_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RR_LSL2(
        LDFF1W_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RR_LSL2,
    ),
    LDFF1W_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW2_22_S_D(
        LDFF1W_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW2_22_S_D,
    ),
    LDFF1W_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW_22_S_D(
        LDFF1W_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW_22_S_D,
    ),
    LDFF1W_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_ZI_U5x4_S_D(
        LDFF1W_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_ZI_U5x4_S_D,
    ),
    LDNF1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL(LDNF1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL),
    LDNF1B_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL(
        LDNF1B_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL,
    ),
    LDNF1B_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL(
        LDNF1B_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL,
    ),
    LDNF1B_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL(
        LDNF1B_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL,
    ),
    LDNF1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL(LDNF1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL),
    LDNF1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL(LDNF1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL),
    LDNF1H_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL(
        LDNF1H_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL,
    ),
    LDNF1H_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL(
        LDNF1H_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL,
    ),
    LDNF1SB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL(LDNF1SB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL),
    LDNF1SB_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL(
        LDNF1SB_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL,
    ),
    LDNF1SB_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL(
        LDNF1SB_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL,
    ),
    LDNF1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL(LDNF1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL),
    LDNF1SH_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL(
        LDNF1SH_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL,
    ),
    LDNF1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL(LDNF1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL),
    LDNF1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL(LDNF1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL),
    LDNF1W_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL(
        LDNF1W_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL,
    ),
    LDNT1B_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL(LDNT1B_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL),
    LDNT1B_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR(LDNT1B_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR),
    LDNT1B_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL(LDNT1B_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL),
    LDNT1B_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR(LDNT1B_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR),
    LDNT1B_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL(
        LDNT1B_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL,
    ),
    LDNT1B_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR(LDNT1B_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR),
    LDNT1B_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL(
        LDNT1B_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL,
    ),
    LDNT1B_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR(LDNT1B_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR),
    LDNT1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL(LDNT1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL),
    LDNT1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX(LDNT1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX),
    LDNT1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZX(LDNT1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZX),
    LDNT1B_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_ZX_S_S(
        LDNT1B_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_ZX_S_S,
    ),
    LDNT1D_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL(LDNT1D_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL),
    LDNT1D_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR_LSL3(LDNT1D_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR_LSL3),
    LDNT1D_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL(LDNT1D_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL),
    LDNT1D_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR_LSL3(LDNT1D_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR_LSL3),
    LDNT1D_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL(
        LDNT1D_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL,
    ),
    LDNT1D_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL3(
        LDNT1D_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL3,
    ),
    LDNT1D_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL(
        LDNT1D_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL,
    ),
    LDNT1D_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL3(
        LDNT1D_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL3,
    ),
    LDNT1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL(LDNT1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL),
    LDNT1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL3(LDNT1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL3),
    LDNT1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZX(LDNT1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZX),
    LDNT1H_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL(LDNT1H_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL),
    LDNT1H_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR_LSL1(LDNT1H_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR_LSL1),
    LDNT1H_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL(LDNT1H_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL),
    LDNT1H_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR_LSL1(LDNT1H_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR_LSL1),
    LDNT1H_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL(
        LDNT1H_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL,
    ),
    LDNT1H_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL1(
        LDNT1H_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL1,
    ),
    LDNT1H_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL(
        LDNT1H_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL,
    ),
    LDNT1H_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL1(
        LDNT1H_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL1,
    ),
    LDNT1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL(LDNT1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL),
    LDNT1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1(LDNT1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1),
    LDNT1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZX(LDNT1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZX),
    LDNT1H_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_ZX_S_S(
        LDNT1H_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_ZX_S_S,
    ),
    LDNT1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZX(LDNT1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZX),
    LDNT1W_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL(LDNT1W_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL),
    LDNT1W_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR_LSL2(LDNT1W_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR_LSL2),
    LDNT1W_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL(LDNT1W_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL),
    LDNT1W_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR_LSL2(LDNT1W_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR_LSL2),
    LDNT1W_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL(
        LDNT1W_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL,
    ),
    LDNT1W_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL2(
        LDNT1W_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL2,
    ),
    LDNT1W_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL(
        LDNT1W_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL,
    ),
    LDNT1W_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL2(
        LDNT1W_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL2,
    ),
    LDNT1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL(LDNT1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL),
    LDNT1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2(LDNT1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2),
    LDNT1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZX(LDNT1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZX),
    LDNT1W_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_ZX_S_D(
        LDNT1W_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_ZX_S_D,
    ),
    LDR_SVE_PNt_SVE_ADDR_RI_S9xVL(LDR_SVE_PNt_SVE_ADDR_RI_S9xVL),
    LDR_SVE_Pt_SVE_ADDR_RI_S9xVL(LDR_SVE_Pt_SVE_ADDR_RI_S9xVL),
    LDR_SVE_Zt_SVE_ADDR_RI_S9xVL(LDR_SVE_Zt_SVE_ADDR_RI_S9xVL),
    MLA_SVE_Zd_SVE_Zn_SVE_Zm3_22_INDEX(MLA_SVE_Zd_SVE_Zn_SVE_Zm3_22_INDEX),
    MLA_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX(MLA_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX),
    MLA_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX(MLA_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX),
    MLS_SVE_Zd_SVE_Zn_SVE_Zm3_22_INDEX(MLS_SVE_Zd_SVE_Zn_SVE_Zm3_22_INDEX),
    MLS_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX(MLS_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX),
    MLS_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX(MLS_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX),
    MOVPRFX_SVE_Zd_SVE_Zn(MOVPRFX_SVE_Zd_SVE_Zn),
    MUL_SVE_Zd_SVE_Zn_SVE_Zm3_22_INDEX(MUL_SVE_Zd_SVE_Zn_SVE_Zm3_22_INDEX),
    MUL_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX(MUL_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX),
    MUL_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX(MUL_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX),
    NANDS_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm(NANDS_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm),
    NAND_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm(NAND_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm),
    NBSL_SVE_Zd_SVE_Zd_SVE_Zm_16_SVE_Zn(NBSL_SVE_Zd_SVE_Zd_SVE_Zm_16_SVE_Zn),
    NORS_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm(NORS_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm),
    NOR_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm(NOR_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm),
    ORNS_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm(ORNS_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm),
    ORN_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm(ORN_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm),
    ORRS_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm(ORRS_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm),
    ORR_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm(ORR_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm),
    ORR_SVE_Zd_SVE_Zn_SVE_Zm_16(ORR_SVE_Zd_SVE_Zn_SVE_Zm_16),
    PFALSE_SVE_PNd(PFALSE_SVE_PNd),
    PFALSE_SVE_Pd(PFALSE_SVE_Pd),
    PFIRST_SVE_Pd_SVE_Pg4_5_SVE_Pd(PFIRST_SVE_Pd_SVE_Pg4_5_SVE_Pd),
    PMULLB_SVE_Zd_SVE_Zn_SVE_Zm_16(PMULLB_SVE_Zd_SVE_Zn_SVE_Zm_16),
    PMULLT_SVE_Zd_SVE_Zn_SVE_Zm_16(PMULLT_SVE_Zd_SVE_Zn_SVE_Zm_16),
    PMUL_SVE_Zd_SVE_Zn_SVE_Zm_16(PMUL_SVE_Zd_SVE_Zn_SVE_Zm_16),
    PRFB_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RI_S6xVL(PRFB_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RI_S6xVL),
    PRFB_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RX(PRFB_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RX),
    PRFB_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RZ(PRFB_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RZ),
    PRFB_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RZ_XTW_22(PRFB_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RZ_XTW_22),
    PRFB_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RZ_XTW_22_c4200000(
        PRFB_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RZ_XTW_22_c4200000,
    ),
    PRFB_SVE_PRFOP_SVE_Pg3_SVE_ADDR_ZI_U5(PRFB_SVE_PRFOP_SVE_Pg3_SVE_ADDR_ZI_U5),
    PRFB_SVE_PRFOP_SVE_Pg3_SVE_ADDR_ZI_U5_c400e000(PRFB_SVE_PRFOP_SVE_Pg3_SVE_ADDR_ZI_U5_c400e000),
    PRFD_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RI_S6xVL(PRFD_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RI_S6xVL),
    PRFD_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RX_LSL3(PRFD_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RX_LSL3),
    PRFD_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RZ_LSL3(PRFD_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RZ_LSL3),
    PRFD_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RZ_XTW3_22(PRFD_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RZ_XTW3_22),
    PRFD_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RZ_XTW3_22_c4206000(
        PRFD_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RZ_XTW3_22_c4206000,
    ),
    PRFD_SVE_PRFOP_SVE_Pg3_SVE_ADDR_ZI_U5x8(PRFD_SVE_PRFOP_SVE_Pg3_SVE_ADDR_ZI_U5x8),
    PRFD_SVE_PRFOP_SVE_Pg3_SVE_ADDR_ZI_U5x8_c580e000(
        PRFD_SVE_PRFOP_SVE_Pg3_SVE_ADDR_ZI_U5x8_c580e000,
    ),
    PRFH_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RI_S6xVL(PRFH_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RI_S6xVL),
    PRFH_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RX_LSL1(PRFH_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RX_LSL1),
    PRFH_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RZ_LSL1(PRFH_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RZ_LSL1),
    PRFH_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RZ_XTW1_22(PRFH_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RZ_XTW1_22),
    PRFH_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RZ_XTW1_22_c4202000(
        PRFH_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RZ_XTW1_22_c4202000,
    ),
    PRFH_SVE_PRFOP_SVE_Pg3_SVE_ADDR_ZI_U5x2(PRFH_SVE_PRFOP_SVE_Pg3_SVE_ADDR_ZI_U5x2),
    PRFH_SVE_PRFOP_SVE_Pg3_SVE_ADDR_ZI_U5x2_c480e000(
        PRFH_SVE_PRFOP_SVE_Pg3_SVE_ADDR_ZI_U5x2_c480e000,
    ),
    PRFW_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RI_S6xVL(PRFW_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RI_S6xVL),
    PRFW_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RX_LSL2(PRFW_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RX_LSL2),
    PRFW_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RZ_LSL2(PRFW_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RZ_LSL2),
    PRFW_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RZ_XTW2_22(PRFW_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RZ_XTW2_22),
    PRFW_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RZ_XTW2_22_c4204000(
        PRFW_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RZ_XTW2_22_c4204000,
    ),
    PRFW_SVE_PRFOP_SVE_Pg3_SVE_ADDR_ZI_U5x4(PRFW_SVE_PRFOP_SVE_Pg3_SVE_ADDR_ZI_U5x4),
    PRFW_SVE_PRFOP_SVE_Pg3_SVE_ADDR_ZI_U5x4_c500e000(
        PRFW_SVE_PRFOP_SVE_Pg3_SVE_ADDR_ZI_U5x4_c500e000,
    ),
    PTEST_SVE_Pg4_10_SVE_Pn(PTEST_SVE_Pg4_10_SVE_Pn),
    PUNPKHI_SVE_Pd_SVE_Pn(PUNPKHI_SVE_Pd_SVE_Pn),
    PUNPKLO_SVE_Pd_SVE_Pn(PUNPKLO_SVE_Pd_SVE_Pn),
    RAX1_SVE_Zd_SVE_Zn_SVE_Zm_16(RAX1_SVE_Zd_SVE_Zn_SVE_Zm_16),
    RDFFRS_SVE_Pd_SVE_Pg4_5(RDFFRS_SVE_Pd_SVE_Pg4_5),
    RDFFR_SVE_Pd(RDFFR_SVE_Pd),
    RDFFR_SVE_Pd_SVE_Pg4_5(RDFFR_SVE_Pd_SVE_Pg4_5),
    RDVL_Rd_SVE_SIMM6(RDVL_Rd_SVE_SIMM6),
    REVW_SVE_Zd_SVE_Pg3_SVE_Zn(REVW_SVE_Zd_SVE_Pg3_SVE_Zn),
    SCVTF_SME_Zdnx2_SME_Znx2(SCVTF_SME_Zdnx2_SME_Znx2),
    SCVTF_SME_Zdnx4_SME_Znx4(SCVTF_SME_Zdnx4_SME_Znx4),
    SCVTF_SVE_Zd_SVE_Pg3_SVE_Zn(SCVTF_SVE_Zd_SVE_Pg3_SVE_Zn),
    SCVTF_SVE_Zd_S_D_SVE_Pg3_P_M_SVE_Zn_S_D(SCVTF_SVE_Zd_S_D_SVE_Pg3_P_M_SVE_Zn_S_D),
    SCVTF_SVE_Zd_S_H_SVE_Pg3_P_M_SVE_Zn_S_D(SCVTF_SVE_Zd_S_H_SVE_Pg3_P_M_SVE_Zn_S_D),
    SCVTF_SVE_Zd_S_H_SVE_Pg3_P_M_SVE_Zn_S_H(SCVTF_SVE_Zd_S_H_SVE_Pg3_P_M_SVE_Zn_S_H),
    SCVTF_SVE_Zd_S_H_SVE_Pg3_P_M_SVE_Zn_S_S(SCVTF_SVE_Zd_S_H_SVE_Pg3_P_M_SVE_Zn_S_S),
    SCVTF_SVE_Zd_S_S_SVE_Pg3_P_M_SVE_Zn_S_D(SCVTF_SVE_Zd_S_S_SVE_Pg3_P_M_SVE_Zn_S_D),
    SCVTF_SVE_Zd_S_S_SVE_Pg3_P_M_SVE_Zn_S_S(SCVTF_SVE_Zd_S_S_SVE_Pg3_P_M_SVE_Zn_S_S),
    SDOT_SVE_Zd_SVE_Zn_SVE_Zm3_19_INDEX(SDOT_SVE_Zd_SVE_Zn_SVE_Zm3_19_INDEX),
    SDOT_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX(SDOT_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX),
    SDOT_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX(SDOT_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX),
    SDOT_SVE_Zd_S_S_SVE_Zn_S_H_SVE_Zm_16_S_H(SDOT_SVE_Zd_S_S_SVE_Zn_S_H_SVE_Zm_16_S_H),
    SEL_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm(SEL_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm),
    SETFFR(SETFFR),
    SM4EKEY_SVE_Zd_SVE_Zn_SVE_Zm_16(SM4EKEY_SVE_Zd_SVE_Zn_SVE_Zm_16),
    SM4E_SVE_Zd_SVE_Zd_SVE_Zn(SM4E_SVE_Zd_SVE_Zd_SVE_Zn),
    SMLALB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX(SMLALB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX),
    SMLALB_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX(SMLALB_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX),
    SMLALT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX(SMLALT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX),
    SMLALT_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX(SMLALT_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX),
    SMLSLB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX(SMLSLB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX),
    SMLSLB_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX(SMLSLB_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX),
    SMLSLT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX(SMLSLT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX),
    SMLSLT_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX(SMLSLT_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX),
    SMMLA_SVE_Zd_SVE_Zn_SVE_Zm_16(SMMLA_SVE_Zd_SVE_Zn_SVE_Zm_16),
    SMULLB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX(SMULLB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX),
    SMULLB_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX(SMULLB_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX),
    SMULLT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX(SMULLT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX),
    SMULLT_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX(SMULLT_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX),
    SQCVTN_SVE_Zd_SME_Znx2(SQCVTN_SVE_Zd_SME_Znx2),
    SQCVTUN_SVE_Zd_SME_Znx2(SQCVTUN_SVE_Zd_SME_Znx2),
    SQDECB_Rd_Rd_SVE_PATTERN_SCALED(SQDECB_Rd_Rd_SVE_PATTERN_SCALED),
    SQDECB_Rd_SVE_PATTERN_SCALED(SQDECB_Rd_SVE_PATTERN_SCALED),
    SQDECD_Rd_Rd_SVE_PATTERN_SCALED(SQDECD_Rd_Rd_SVE_PATTERN_SCALED),
    SQDECD_Rd_SVE_PATTERN_SCALED(SQDECD_Rd_SVE_PATTERN_SCALED),
    SQDECD_SVE_Zd_SVE_PATTERN_SCALED(SQDECD_SVE_Zd_SVE_PATTERN_SCALED),
    SQDECH_Rd_Rd_SVE_PATTERN_SCALED(SQDECH_Rd_Rd_SVE_PATTERN_SCALED),
    SQDECH_Rd_SVE_PATTERN_SCALED(SQDECH_Rd_SVE_PATTERN_SCALED),
    SQDECH_SVE_Zd_SVE_PATTERN_SCALED(SQDECH_SVE_Zd_SVE_PATTERN_SCALED),
    SQDECW_Rd_Rd_SVE_PATTERN_SCALED(SQDECW_Rd_Rd_SVE_PATTERN_SCALED),
    SQDECW_Rd_SVE_PATTERN_SCALED(SQDECW_Rd_SVE_PATTERN_SCALED),
    SQDECW_SVE_Zd_SVE_PATTERN_SCALED(SQDECW_SVE_Zd_SVE_PATTERN_SCALED),
    SQDMLALB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX(SQDMLALB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX),
    SQDMLALB_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX(SQDMLALB_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX),
    SQDMLALT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX(SQDMLALT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX),
    SQDMLALT_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX(SQDMLALT_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX),
    SQDMLSLB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX(SQDMLSLB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX),
    SQDMLSLB_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX(SQDMLSLB_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX),
    SQDMLSLT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX(SQDMLSLT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX),
    SQDMLSLT_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX(SQDMLSLT_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX),
    SQDMULH_SVE_Zd_SVE_Zn_SVE_Zm3_22_INDEX(SQDMULH_SVE_Zd_SVE_Zn_SVE_Zm3_22_INDEX),
    SQDMULH_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX(SQDMULH_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX),
    SQDMULH_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX(SQDMULH_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX),
    SQDMULLB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX(SQDMULLB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX),
    SQDMULLB_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX(SQDMULLB_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX),
    SQDMULLT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX(SQDMULLT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX),
    SQDMULLT_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX(SQDMULLT_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX),
    SQINCB_Rd_Rd_SVE_PATTERN_SCALED(SQINCB_Rd_Rd_SVE_PATTERN_SCALED),
    SQINCB_Rd_SVE_PATTERN_SCALED(SQINCB_Rd_SVE_PATTERN_SCALED),
    SQINCD_Rd_Rd_SVE_PATTERN_SCALED(SQINCD_Rd_Rd_SVE_PATTERN_SCALED),
    SQINCD_Rd_SVE_PATTERN_SCALED(SQINCD_Rd_SVE_PATTERN_SCALED),
    SQINCD_SVE_Zd_SVE_PATTERN_SCALED(SQINCD_SVE_Zd_SVE_PATTERN_SCALED),
    SQINCH_Rd_Rd_SVE_PATTERN_SCALED(SQINCH_Rd_Rd_SVE_PATTERN_SCALED),
    SQINCH_Rd_SVE_PATTERN_SCALED(SQINCH_Rd_SVE_PATTERN_SCALED),
    SQINCH_SVE_Zd_SVE_PATTERN_SCALED(SQINCH_SVE_Zd_SVE_PATTERN_SCALED),
    SQINCW_Rd_Rd_SVE_PATTERN_SCALED(SQINCW_Rd_Rd_SVE_PATTERN_SCALED),
    SQINCW_Rd_SVE_PATTERN_SCALED(SQINCW_Rd_SVE_PATTERN_SCALED),
    SQINCW_SVE_Zd_SVE_PATTERN_SCALED(SQINCW_SVE_Zd_SVE_PATTERN_SCALED),
    SQRDCMLAH_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX_SVE_IMM_ROT2(
        SQRDCMLAH_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX_SVE_IMM_ROT2,
    ),
    SQRDCMLAH_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX_SVE_IMM_ROT2(
        SQRDCMLAH_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX_SVE_IMM_ROT2,
    ),
    SQRDMLAH_SVE_Zd_SVE_Zn_SVE_Zm3_22_INDEX(SQRDMLAH_SVE_Zd_SVE_Zn_SVE_Zm3_22_INDEX),
    SQRDMLAH_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX(SQRDMLAH_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX),
    SQRDMLAH_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX(SQRDMLAH_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX),
    SQRDMLSH_SVE_Zd_SVE_Zn_SVE_Zm3_22_INDEX(SQRDMLSH_SVE_Zd_SVE_Zn_SVE_Zm3_22_INDEX),
    SQRDMLSH_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX(SQRDMLSH_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX),
    SQRDMLSH_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX(SQRDMLSH_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX),
    SQRDMULH_SVE_Zd_SVE_Zn_SVE_Zm3_22_INDEX(SQRDMULH_SVE_Zd_SVE_Zn_SVE_Zm3_22_INDEX),
    SQRDMULH_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX(SQRDMULH_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX),
    SQRDMULH_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX(SQRDMULH_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX),
    ST1B_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_R(ST1B_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_R),
    ST1B_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_RR(ST1B_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_RR),
    ST1B_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL(ST1B_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL),
    ST1B_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR(ST1B_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR),
    ST1B_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL(ST1B_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL),
    ST1B_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR(ST1B_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR),
    ST1B_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL(
        ST1B_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL,
    ),
    ST1B_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR(ST1B_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR),
    ST1B_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL(
        ST1B_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL,
    ),
    ST1B_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR(ST1B_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR),
    ST1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL(ST1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL),
    ST1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX(ST1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX),
    ST1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ(ST1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ),
    ST1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_14(ST1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_14),
    ST1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5(ST1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5),
    ST1B_SVE_ZtxN_S_D_SVE_Pg3_SVE_ADDR_RI_S4xVL(ST1B_SVE_ZtxN_S_D_SVE_Pg3_SVE_ADDR_RI_S4xVL),
    ST1B_SVE_ZtxN_S_D_SVE_Pg3_SVE_ADDR_RX(ST1B_SVE_ZtxN_S_D_SVE_Pg3_SVE_ADDR_RX),
    ST1B_SVE_ZtxN_S_H_SVE_Pg3_SVE_ADDR_RI_S4xVL(ST1B_SVE_ZtxN_S_H_SVE_Pg3_SVE_ADDR_RI_S4xVL),
    ST1B_SVE_ZtxN_S_H_SVE_Pg3_SVE_ADDR_RX(ST1B_SVE_ZtxN_S_H_SVE_Pg3_SVE_ADDR_RX),
    ST1B_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_RI_S4xVL(ST1B_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_RI_S4xVL),
    ST1B_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_RX(ST1B_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_RX),
    ST1B_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_RZ_XTW_14(ST1B_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_RZ_XTW_14),
    ST1B_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_ZI_U5(ST1B_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_ZI_U5),
    ST1D_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_R(ST1D_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_R),
    ST1D_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_RR_LSL3(
        ST1D_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_RR_LSL3,
    ),
    ST1D_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL(ST1D_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL),
    ST1D_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR_LSL3(ST1D_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR_LSL3),
    ST1D_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL(ST1D_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL),
    ST1D_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR_LSL3(ST1D_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR_LSL3),
    ST1D_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL(
        ST1D_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL,
    ),
    ST1D_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL3(
        ST1D_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL3,
    ),
    ST1D_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL(
        ST1D_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL,
    ),
    ST1D_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL3(
        ST1D_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL3,
    ),
    ST1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL(ST1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL),
    ST1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL3(ST1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL3),
    ST1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ(ST1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ),
    ST1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL3(ST1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL3),
    ST1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW3_14(ST1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW3_14),
    ST1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_14(ST1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_14),
    ST1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x8(ST1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x8),
    ST1H_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_R(ST1H_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_R),
    ST1H_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_RR_LSL1(
        ST1H_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_RR_LSL1,
    ),
    ST1H_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL(ST1H_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL),
    ST1H_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR_LSL1(ST1H_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR_LSL1),
    ST1H_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL(ST1H_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL),
    ST1H_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR_LSL1(ST1H_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR_LSL1),
    ST1H_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL(
        ST1H_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL,
    ),
    ST1H_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL1(
        ST1H_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL1,
    ),
    ST1H_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL(
        ST1H_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL,
    ),
    ST1H_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL1(
        ST1H_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL1,
    ),
    ST1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL(ST1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL),
    ST1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1(ST1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1),
    ST1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ(ST1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ),
    ST1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL1(ST1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL1),
    ST1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW1_14(ST1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW1_14),
    ST1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_14(ST1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_14),
    ST1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x2(ST1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x2),
    ST1H_SVE_ZtxN_S_D_SVE_Pg3_SVE_ADDR_RI_S4xVL(ST1H_SVE_ZtxN_S_D_SVE_Pg3_SVE_ADDR_RI_S4xVL),
    ST1H_SVE_ZtxN_S_D_SVE_Pg3_SVE_ADDR_RX_LSL1(ST1H_SVE_ZtxN_S_D_SVE_Pg3_SVE_ADDR_RX_LSL1),
    ST1H_SVE_ZtxN_S_H_SVE_Pg3_SVE_ADDR_RI_S4xVL(ST1H_SVE_ZtxN_S_H_SVE_Pg3_SVE_ADDR_RI_S4xVL),
    ST1H_SVE_ZtxN_S_H_SVE_Pg3_SVE_ADDR_RX_LSL1(ST1H_SVE_ZtxN_S_H_SVE_Pg3_SVE_ADDR_RX_LSL1),
    ST1H_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_RZ_XTW1_14(ST1H_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_RZ_XTW1_14),
    ST1H_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_RZ_XTW_14(ST1H_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_RZ_XTW_14),
    ST1H_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_ZI_U5x2(ST1H_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_ZI_U5x2),
    ST1Q_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_R(ST1Q_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_R),
    ST1Q_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_RR_LSL4(
        ST1Q_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_RR_LSL4,
    ),
    ST1Q_SVE_Zt_SVE_Pg3_SVE_ADDR_ZX(ST1Q_SVE_Zt_SVE_Pg3_SVE_ADDR_ZX),
    ST1W_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_R(ST1W_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_R),
    ST1W_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_RR_LSL2(
        ST1W_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_RR_LSL2,
    ),
    ST1W_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL(ST1W_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL),
    ST1W_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR_LSL2(ST1W_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR_LSL2),
    ST1W_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL(ST1W_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL),
    ST1W_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR_LSL2(ST1W_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR_LSL2),
    ST1W_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL(
        ST1W_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL,
    ),
    ST1W_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL2(
        ST1W_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL2,
    ),
    ST1W_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL(
        ST1W_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL,
    ),
    ST1W_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL2(
        ST1W_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL2,
    ),
    ST1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL(ST1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL),
    ST1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2(ST1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2),
    ST1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ(ST1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ),
    ST1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL2(ST1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL2),
    ST1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW2_14(ST1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW2_14),
    ST1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_14(ST1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_14),
    ST1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x4(ST1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x4),
    ST1W_SVE_ZtxN_S_D_SVE_Pg3_SVE_ADDR_RI_S4xVL(ST1W_SVE_ZtxN_S_D_SVE_Pg3_SVE_ADDR_RI_S4xVL),
    ST1W_SVE_ZtxN_S_D_SVE_Pg3_SVE_ADDR_RX_LSL2(ST1W_SVE_ZtxN_S_D_SVE_Pg3_SVE_ADDR_RX_LSL2),
    ST1W_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_RZ_XTW2_14(ST1W_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_RZ_XTW2_14),
    ST1W_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_RZ_XTW_14(ST1W_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_RZ_XTW_14),
    ST1W_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_ZI_U5x4(ST1W_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_ZI_U5x4),
    ST2B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x2xVL(ST2B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x2xVL),
    ST2B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX(ST2B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX),
    ST2D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x2xVL(ST2D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x2xVL),
    ST2D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL3(ST2D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL3),
    ST2H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x2xVL(ST2H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x2xVL),
    ST2H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1(ST2H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1),
    ST2Q_SME_Zt2_SVE_Pg3_SVE_ADDR_RI_S4x2xVL(ST2Q_SME_Zt2_SVE_Pg3_SVE_ADDR_RI_S4x2xVL),
    ST2Q_SME_Zt2_SVE_Pg3_SVE_ADDR_RR_LSL4(ST2Q_SME_Zt2_SVE_Pg3_SVE_ADDR_RR_LSL4),
    ST2W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x2xVL(ST2W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x2xVL),
    ST2W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2(ST2W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2),
    ST3B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x3xVL(ST3B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x3xVL),
    ST3B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX(ST3B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX),
    ST3D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x3xVL(ST3D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x3xVL),
    ST3D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL3(ST3D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL3),
    ST3H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x3xVL(ST3H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x3xVL),
    ST3H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1(ST3H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1),
    ST3Q_SME_Zt3_SVE_Pg3_SVE_ADDR_RI_S4x2xVL(ST3Q_SME_Zt3_SVE_Pg3_SVE_ADDR_RI_S4x2xVL),
    ST3Q_SME_Zt3_SVE_Pg3_SVE_ADDR_RR_LSL4(ST3Q_SME_Zt3_SVE_Pg3_SVE_ADDR_RR_LSL4),
    ST3W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x3xVL(ST3W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x3xVL),
    ST3W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2(ST3W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2),
    ST4B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x4xVL(ST4B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x4xVL),
    ST4B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX(ST4B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX),
    ST4D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x4xVL(ST4D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x4xVL),
    ST4D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL3(ST4D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL3),
    ST4H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x4xVL(ST4H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x4xVL),
    ST4H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1(ST4H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1),
    ST4Q_SME_Zt4_SVE_Pg3_SVE_ADDR_RI_S4x2xVL(ST4Q_SME_Zt4_SVE_Pg3_SVE_ADDR_RI_S4x2xVL),
    ST4Q_SME_Zt4_SVE_Pg3_SVE_ADDR_RR_LSL4(ST4Q_SME_Zt4_SVE_Pg3_SVE_ADDR_RR_LSL4),
    ST4W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x4xVL(ST4W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x4xVL),
    ST4W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2(ST4W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2),
    STNT1B_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL(STNT1B_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL),
    STNT1B_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR(STNT1B_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR),
    STNT1B_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL(STNT1B_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL),
    STNT1B_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR(STNT1B_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR),
    STNT1B_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL(
        STNT1B_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL,
    ),
    STNT1B_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR(STNT1B_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR),
    STNT1B_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL(
        STNT1B_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL,
    ),
    STNT1B_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR(STNT1B_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR),
    STNT1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL(STNT1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL),
    STNT1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX(STNT1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX),
    STNT1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZX(STNT1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZX),
    STNT1B_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_ZX(STNT1B_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_ZX),
    STNT1D_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL(STNT1D_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL),
    STNT1D_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR_LSL3(STNT1D_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR_LSL3),
    STNT1D_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL(STNT1D_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL),
    STNT1D_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR_LSL3(STNT1D_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR_LSL3),
    STNT1D_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL(
        STNT1D_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL,
    ),
    STNT1D_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL3(
        STNT1D_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL3,
    ),
    STNT1D_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL(
        STNT1D_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL,
    ),
    STNT1D_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL3(
        STNT1D_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL3,
    ),
    STNT1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL(STNT1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL),
    STNT1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL3(STNT1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL3),
    STNT1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZX(STNT1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZX),
    STNT1H_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL(STNT1H_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL),
    STNT1H_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR_LSL1(STNT1H_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR_LSL1),
    STNT1H_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL(STNT1H_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL),
    STNT1H_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR_LSL1(STNT1H_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR_LSL1),
    STNT1H_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL(
        STNT1H_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL,
    ),
    STNT1H_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL1(
        STNT1H_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL1,
    ),
    STNT1H_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL(
        STNT1H_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL,
    ),
    STNT1H_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL1(
        STNT1H_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL1,
    ),
    STNT1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL(STNT1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL),
    STNT1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1(STNT1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1),
    STNT1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZX(STNT1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZX),
    STNT1H_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_ZX(STNT1H_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_ZX),
    STNT1W_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL(STNT1W_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL),
    STNT1W_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR_LSL2(STNT1W_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR_LSL2),
    STNT1W_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL(STNT1W_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL),
    STNT1W_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR_LSL2(STNT1W_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR_LSL2),
    STNT1W_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL(
        STNT1W_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL,
    ),
    STNT1W_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL2(
        STNT1W_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL2,
    ),
    STNT1W_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL(
        STNT1W_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL,
    ),
    STNT1W_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL2(
        STNT1W_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL2,
    ),
    STNT1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL(STNT1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL),
    STNT1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2(STNT1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2),
    STNT1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZX(STNT1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZX),
    STNT1W_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_ZX(STNT1W_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_ZX),
    STR_SVE_PNt_SVE_ADDR_RI_S9xVL(STR_SVE_PNt_SVE_ADDR_RI_S9xVL),
    STR_SVE_Pt_SVE_ADDR_RI_S9xVL(STR_SVE_Pt_SVE_ADDR_RI_S9xVL),
    STR_SVE_Zt_SVE_ADDR_RI_S9xVL(STR_SVE_Zt_SVE_ADDR_RI_S9xVL),
    SUDOT_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX(SUDOT_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX),
    SXTW_SVE_Zd_SVE_Pg3_SVE_Zn(SXTW_SVE_Zd_SVE_Pg3_SVE_Zn),
    TRN1_SVE_Zd_SVE_Zn_SVE_Zm_16(TRN1_SVE_Zd_SVE_Zn_SVE_Zm_16),
    TRN2_SVE_Zd_SVE_Zn_SVE_Zm_16(TRN2_SVE_Zd_SVE_Zn_SVE_Zm_16),
    UCVTF_SME_Zdnx2_SME_Znx2(UCVTF_SME_Zdnx2_SME_Znx2),
    UCVTF_SME_Zdnx4_SME_Znx4(UCVTF_SME_Zdnx4_SME_Znx4),
    UCVTF_SVE_Zd_SVE_Pg3_SVE_Zn(UCVTF_SVE_Zd_SVE_Pg3_SVE_Zn),
    UCVTF_SVE_Zd_S_D_SVE_Pg3_P_M_SVE_Zn_S_D(UCVTF_SVE_Zd_S_D_SVE_Pg3_P_M_SVE_Zn_S_D),
    UCVTF_SVE_Zd_S_H_SVE_Pg3_P_M_SVE_Zn_S_D(UCVTF_SVE_Zd_S_H_SVE_Pg3_P_M_SVE_Zn_S_D),
    UCVTF_SVE_Zd_S_H_SVE_Pg3_P_M_SVE_Zn_S_H(UCVTF_SVE_Zd_S_H_SVE_Pg3_P_M_SVE_Zn_S_H),
    UCVTF_SVE_Zd_S_H_SVE_Pg3_P_M_SVE_Zn_S_S(UCVTF_SVE_Zd_S_H_SVE_Pg3_P_M_SVE_Zn_S_S),
    UCVTF_SVE_Zd_S_S_SVE_Pg3_P_M_SVE_Zn_S_D(UCVTF_SVE_Zd_S_S_SVE_Pg3_P_M_SVE_Zn_S_D),
    UCVTF_SVE_Zd_S_S_SVE_Pg3_P_M_SVE_Zn_S_S(UCVTF_SVE_Zd_S_S_SVE_Pg3_P_M_SVE_Zn_S_S),
    UDOT_SVE_Zd_SVE_Zn_SVE_Zm3_19_INDEX(UDOT_SVE_Zd_SVE_Zn_SVE_Zm3_19_INDEX),
    UDOT_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX(UDOT_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX),
    UDOT_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX(UDOT_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX),
    UDOT_SVE_Zd_S_S_SVE_Zn_S_H_SVE_Zm_16_S_H(UDOT_SVE_Zd_S_S_SVE_Zn_S_H_SVE_Zm_16_S_H),
    UMLALB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX(UMLALB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX),
    UMLALB_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX(UMLALB_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX),
    UMLALT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX(UMLALT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX),
    UMLALT_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX(UMLALT_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX),
    UMLSLB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX(UMLSLB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX),
    UMLSLB_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX(UMLSLB_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX),
    UMLSLT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX(UMLSLT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX),
    UMLSLT_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX(UMLSLT_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX),
    UMMLA_SVE_Zd_SVE_Zn_SVE_Zm_16(UMMLA_SVE_Zd_SVE_Zn_SVE_Zm_16),
    UMULLB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX(UMULLB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX),
    UMULLB_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX(UMULLB_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX),
    UMULLT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX(UMULLT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX),
    UMULLT_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX(UMULLT_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX),
    UQCVTN_SVE_Zd_SME_Znx2(UQCVTN_SVE_Zd_SME_Znx2),
    UQDECB_Rd_SVE_PATTERN_SCALED(UQDECB_Rd_SVE_PATTERN_SCALED),
    UQDECB_Rd_X_SVE_PATTERN_SCALED(UQDECB_Rd_X_SVE_PATTERN_SCALED),
    UQDECD_Rd_SVE_PATTERN_SCALED(UQDECD_Rd_SVE_PATTERN_SCALED),
    UQDECD_Rd_X_SVE_PATTERN_SCALED(UQDECD_Rd_X_SVE_PATTERN_SCALED),
    UQDECD_SVE_Zd_SVE_PATTERN_SCALED(UQDECD_SVE_Zd_SVE_PATTERN_SCALED),
    UQDECH_Rd_SVE_PATTERN_SCALED(UQDECH_Rd_SVE_PATTERN_SCALED),
    UQDECH_Rd_X_SVE_PATTERN_SCALED(UQDECH_Rd_X_SVE_PATTERN_SCALED),
    UQDECH_SVE_Zd_SVE_PATTERN_SCALED(UQDECH_SVE_Zd_SVE_PATTERN_SCALED),
    UQDECW_Rd_SVE_PATTERN_SCALED(UQDECW_Rd_SVE_PATTERN_SCALED),
    UQDECW_Rd_X_SVE_PATTERN_SCALED(UQDECW_Rd_X_SVE_PATTERN_SCALED),
    UQDECW_SVE_Zd_SVE_PATTERN_SCALED(UQDECW_SVE_Zd_SVE_PATTERN_SCALED),
    UQINCB_Rd_SVE_PATTERN_SCALED(UQINCB_Rd_SVE_PATTERN_SCALED),
    UQINCB_Rd_X_SVE_PATTERN_SCALED(UQINCB_Rd_X_SVE_PATTERN_SCALED),
    UQINCD_Rd_SVE_PATTERN_SCALED(UQINCD_Rd_SVE_PATTERN_SCALED),
    UQINCD_Rd_X_SVE_PATTERN_SCALED(UQINCD_Rd_X_SVE_PATTERN_SCALED),
    UQINCD_SVE_Zd_SVE_PATTERN_SCALED(UQINCD_SVE_Zd_SVE_PATTERN_SCALED),
    UQINCH_Rd_SVE_PATTERN_SCALED(UQINCH_Rd_SVE_PATTERN_SCALED),
    UQINCH_Rd_X_SVE_PATTERN_SCALED(UQINCH_Rd_X_SVE_PATTERN_SCALED),
    UQINCH_SVE_Zd_SVE_PATTERN_SCALED(UQINCH_SVE_Zd_SVE_PATTERN_SCALED),
    UQINCW_Rd_SVE_PATTERN_SCALED(UQINCW_Rd_SVE_PATTERN_SCALED),
    UQINCW_Rd_X_SVE_PATTERN_SCALED(UQINCW_Rd_X_SVE_PATTERN_SCALED),
    UQINCW_SVE_Zd_SVE_PATTERN_SCALED(UQINCW_SVE_Zd_SVE_PATTERN_SCALED),
    URECPE_SVE_Zd_SVE_Pg3_SVE_Zn(URECPE_SVE_Zd_SVE_Pg3_SVE_Zn),
    URSQRTE_SVE_Zd_SVE_Pg3_SVE_Zn(URSQRTE_SVE_Zd_SVE_Pg3_SVE_Zn),
    USDOT_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX(USDOT_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX),
    USDOT_SVE_Zd_SVE_Zn_SVE_Zm_16(USDOT_SVE_Zd_SVE_Zn_SVE_Zm_16),
    USMMLA_SVE_Zd_SVE_Zn_SVE_Zm_16(USMMLA_SVE_Zd_SVE_Zn_SVE_Zm_16),
    UXTW_SVE_Zd_SVE_Pg3_SVE_Zn(UXTW_SVE_Zd_SVE_Pg3_SVE_Zn),
    UZP1_SVE_Zd_SVE_Zn_SVE_Zm_16(UZP1_SVE_Zd_SVE_Zn_SVE_Zm_16),
    UZP2_SVE_Zd_SVE_Zn_SVE_Zm_16(UZP2_SVE_Zd_SVE_Zn_SVE_Zm_16),
    WRFFR_SVE_Pn(WRFFR_SVE_Pn),
    ZIP1_SVE_Zd_SVE_Zn_SVE_Zm_16(ZIP1_SVE_Zd_SVE_Zn_SVE_Zm_16),
    ZIP2_SVE_Zd_SVE_Zn_SVE_Zm_16(ZIP2_SVE_Zd_SVE_Zn_SVE_Zm_16),
}
#[derive(Debug, PartialEq, Eq, Copy, Clone)]
pub enum SME_INT_SD {
    ADD_SME_ZA_array_off3_0_SME_Znx2(ADD_SME_ZA_array_off3_0_SME_Znx2),
    ADD_SME_ZA_array_off3_0_SME_Znx2_SME_Zmx2(ADD_SME_ZA_array_off3_0_SME_Znx2_SME_Zmx2),
    ADD_SME_ZA_array_off3_0_SME_Znx4(ADD_SME_ZA_array_off3_0_SME_Znx4),
    ADD_SME_ZA_array_off3_0_SME_Znx4_SME_Zmx4(ADD_SME_ZA_array_off3_0_SME_Znx4_SME_Zmx4),
    ADD_SME_ZA_array_off3_0_SVE_ZnxN_SME_Zm(ADD_SME_ZA_array_off3_0_SVE_ZnxN_SME_Zm),
    ADD_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_S_SME_Zm_S_S(
        ADD_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_S_SME_Zm_S_S,
    ),
    SDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zmx2(SDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zmx2),
    SDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zmx4(SDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zmx4),
    SDOT_SME_ZA_array_off3_0_SVE_ZnxN_SME_Zm(SDOT_SME_ZA_array_off3_0_SVE_ZnxN_SME_Zm),
    SDOT_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_B_SME_Zm_S_B(
        SDOT_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_B_SME_Zm_S_B,
    ),
    SMLALL_SME_ZA_array_off1x4_SME_Znx2_SME_Zmx2(SMLALL_SME_ZA_array_off1x4_SME_Znx2_SME_Zmx2),
    SMLALL_SME_ZA_array_off1x4_SME_Znx4_SME_Zmx4(SMLALL_SME_ZA_array_off1x4_SME_Znx4_SME_Zmx4),
    SMLALL_SME_ZA_array_off1x4_SVE_ZnxN_SME_Zm(SMLALL_SME_ZA_array_off1x4_SVE_ZnxN_SME_Zm),
    SMLALL_SME_ZA_array_off1x4_S_S_SVE_ZnxN_S_B_SME_Zm_S_B(
        SMLALL_SME_ZA_array_off1x4_S_S_SVE_ZnxN_S_B_SME_Zm_S_B,
    ),
    SMLALL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm(SMLALL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm),
    SMLSLL_SME_ZA_array_off1x4_SME_Znx2_SME_Zmx2(SMLSLL_SME_ZA_array_off1x4_SME_Znx2_SME_Zmx2),
    SMLSLL_SME_ZA_array_off1x4_SME_Znx4_SME_Zmx4(SMLSLL_SME_ZA_array_off1x4_SME_Znx4_SME_Zmx4),
    SMLSLL_SME_ZA_array_off1x4_SVE_ZnxN_SME_Zm(SMLSLL_SME_ZA_array_off1x4_SVE_ZnxN_SME_Zm),
    SMLSLL_SME_ZA_array_off1x4_S_S_SVE_ZnxN_S_B_SME_Zm_S_B(
        SMLSLL_SME_ZA_array_off1x4_S_S_SVE_ZnxN_S_B_SME_Zm_S_B,
    ),
    SMLSLL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm(SMLSLL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm),
    SUB_SME_ZA_array_off3_0_SME_Znx2(SUB_SME_ZA_array_off3_0_SME_Znx2),
    SUB_SME_ZA_array_off3_0_SME_Znx2_SME_Zmx2(SUB_SME_ZA_array_off3_0_SME_Znx2_SME_Zmx2),
    SUB_SME_ZA_array_off3_0_SME_Znx4(SUB_SME_ZA_array_off3_0_SME_Znx4),
    SUB_SME_ZA_array_off3_0_SME_Znx4_SME_Zmx4(SUB_SME_ZA_array_off3_0_SME_Znx4_SME_Zmx4),
    SUB_SME_ZA_array_off3_0_SVE_ZnxN_SME_Zm(SUB_SME_ZA_array_off3_0_SVE_ZnxN_SME_Zm),
    SUB_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_S_SME_Zm_S_S(
        SUB_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_S_SME_Zm_S_S,
    ),
    UDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zmx2(UDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zmx2),
    UDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zmx4(UDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zmx4),
    UDOT_SME_ZA_array_off3_0_SVE_ZnxN_SME_Zm(UDOT_SME_ZA_array_off3_0_SVE_ZnxN_SME_Zm),
    UDOT_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_B_SME_Zm_S_B(
        UDOT_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_B_SME_Zm_S_B,
    ),
    UMLALL_SME_ZA_array_off1x4_SME_Znx2_SME_Zmx2(UMLALL_SME_ZA_array_off1x4_SME_Znx2_SME_Zmx2),
    UMLALL_SME_ZA_array_off1x4_SME_Znx4_SME_Zmx4(UMLALL_SME_ZA_array_off1x4_SME_Znx4_SME_Zmx4),
    UMLALL_SME_ZA_array_off1x4_SVE_ZnxN_SME_Zm(UMLALL_SME_ZA_array_off1x4_SVE_ZnxN_SME_Zm),
    UMLALL_SME_ZA_array_off1x4_S_S_SVE_ZnxN_S_B_SME_Zm_S_B(
        UMLALL_SME_ZA_array_off1x4_S_S_SVE_ZnxN_S_B_SME_Zm_S_B,
    ),
    UMLALL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm(UMLALL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm),
    UMLSLL_SME_ZA_array_off1x4_SME_Znx2_SME_Zmx2(UMLSLL_SME_ZA_array_off1x4_SME_Znx2_SME_Zmx2),
    UMLSLL_SME_ZA_array_off1x4_SME_Znx4_SME_Zmx4(UMLSLL_SME_ZA_array_off1x4_SME_Znx4_SME_Zmx4),
    UMLSLL_SME_ZA_array_off1x4_SVE_ZnxN_SME_Zm(UMLSLL_SME_ZA_array_off1x4_SVE_ZnxN_SME_Zm),
    UMLSLL_SME_ZA_array_off1x4_S_S_SVE_ZnxN_S_B_SME_Zm_S_B(
        UMLSLL_SME_ZA_array_off1x4_S_S_SVE_ZnxN_S_B_SME_Zm_S_B,
    ),
    UMLSLL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm(UMLSLL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm),
}
#[derive(Debug, PartialEq, Eq, Copy, Clone)]
pub enum FLOATCCMP {
    FCCMPE_Fn_Fm_NZCV_COND(FCCMPE_Fn_Fm_NZCV_COND),
    FCCMPE_Fn_S_S_Fm_S_S_NZCV_COND(FCCMPE_Fn_S_S_Fm_S_S_NZCV_COND),
    FCCMP_Fn_Fm_NZCV_COND(FCCMP_Fn_Fm_NZCV_COND),
    FCCMP_Fn_S_S_Fm_S_S_NZCV_COND(FCCMP_Fn_S_S_Fm_S_S_NZCV_COND),
}
#[derive(Debug, PartialEq, Eq, Copy, Clone)]
pub enum SME2_MOVAZ {
    MOVAZ_SME_Zdnx2_SME_ZA_array_vrsb_1(MOVAZ_SME_Zdnx2_SME_ZA_array_vrsb_1),
    MOVAZ_SME_Zdnx2_SME_ZA_array_vrsd_1(MOVAZ_SME_Zdnx2_SME_ZA_array_vrsd_1),
    MOVAZ_SME_Zdnx2_SME_ZA_array_vrsh_1(MOVAZ_SME_Zdnx2_SME_ZA_array_vrsh_1),
    MOVAZ_SME_Zdnx2_SME_ZA_array_vrss_1(MOVAZ_SME_Zdnx2_SME_ZA_array_vrss_1),
    MOVAZ_SME_Zdnx4_SME_ZA_array_vrsb_2(MOVAZ_SME_Zdnx4_SME_ZA_array_vrsb_2),
    MOVAZ_SME_Zdnx4_SME_ZA_array_vrsd_2(MOVAZ_SME_Zdnx4_SME_ZA_array_vrsd_2),
    MOVAZ_SME_Zdnx4_SME_ZA_array_vrsh_2(MOVAZ_SME_Zdnx4_SME_ZA_array_vrsh_2),
    MOVAZ_SME_Zdnx4_SME_ZA_array_vrss_2(MOVAZ_SME_Zdnx4_SME_ZA_array_vrss_2),
}
#[derive(Debug, PartialEq, Eq, Copy, Clone)]
pub enum TESTBRANCH {
    TBNZ_Rt_BIT_NUM_ADDR_PCREL14(TBNZ_Rt_BIT_NUM_ADDR_PCREL14),
    TBZ_Rt_BIT_NUM_ADDR_PCREL14(TBZ_Rt_BIT_NUM_ADDR_PCREL14),
}
#[derive(Debug, PartialEq, Eq, Copy, Clone)]
pub enum LDST_REGOFF {
    LDRB_Rt_ADDR_REGOFF(LDRB_Rt_ADDR_REGOFF),
    LDRH_Rt_ADDR_REGOFF(LDRH_Rt_ADDR_REGOFF),
    LDRSB_Rt_ADDR_REGOFF(LDRSB_Rt_ADDR_REGOFF),
    LDRSH_Rt_ADDR_REGOFF(LDRSH_Rt_ADDR_REGOFF),
    LDRSW_Rt_ADDR_REGOFF(LDRSW_Rt_ADDR_REGOFF),
    LDR_Ft_ADDR_REGOFF(LDR_Ft_ADDR_REGOFF),
    LDR_Rt_ADDR_REGOFF(LDR_Rt_ADDR_REGOFF),
    PRFM_PRFOP_ADDR_REGOFF(PRFM_PRFOP_ADDR_REGOFF),
    STRB_Rt_ADDR_REGOFF(STRB_Rt_ADDR_REGOFF),
    STRH_Rt_ADDR_REGOFF(STRH_Rt_ADDR_REGOFF),
    STR_Ft_ADDR_REGOFF(STR_Ft_ADDR_REGOFF),
    STR_Rt_ADDR_REGOFF(STR_Rt_ADDR_REGOFF),
}
#[derive(Debug, PartialEq, Eq, Copy, Clone)]
pub enum SVE_SIZE_TSZ_BHS {
    SQXTNB_SVE_Zd_SVE_Zn(SQXTNB_SVE_Zd_SVE_Zn),
    SQXTNT_SVE_Zd_SVE_Zn(SQXTNT_SVE_Zd_SVE_Zn),
    SQXTUNB_SVE_Zd_SVE_Zn(SQXTUNB_SVE_Zd_SVE_Zn),
    SQXTUNT_SVE_Zd_SVE_Zn(SQXTUNT_SVE_Zd_SVE_Zn),
    UQXTNB_SVE_Zd_SVE_Zn(UQXTNB_SVE_Zd_SVE_Zn),
    UQXTNT_SVE_Zd_SVE_Zn(UQXTNT_SVE_Zd_SVE_Zn),
}
#[derive(Debug, PartialEq, Eq, Copy, Clone)]
pub enum ASIMDSHF {
    FCVTZS_Vd_V_2S_Vn_V_2S_IMM_VLSR_V_2S(FCVTZS_Vd_V_2S_Vn_V_2S_IMM_VLSR_V_2S),
    FCVTZS_Vd_Vn_IMM_VLSR(FCVTZS_Vd_Vn_IMM_VLSR),
    FCVTZU_Vd_V_2S_Vn_V_2S_IMM_VLSR_V_2S(FCVTZU_Vd_V_2S_Vn_V_2S_IMM_VLSR_V_2S),
    FCVTZU_Vd_Vn_IMM_VLSR(FCVTZU_Vd_Vn_IMM_VLSR),
    RSHRN2_Vd_Vn_IMM_VLSR(RSHRN2_Vd_Vn_IMM_VLSR),
    RSHRN_Vd_Vn_IMM_VLSR(RSHRN_Vd_Vn_IMM_VLSR),
    SCVTF_Vd_V_2S_Vn_V_2S_IMM_VLSR_V_2S(SCVTF_Vd_V_2S_Vn_V_2S_IMM_VLSR_V_2S),
    SCVTF_Vd_Vn_IMM_VLSR(SCVTF_Vd_Vn_IMM_VLSR),
    SHL_Vd_Vn_IMM_VLSL(SHL_Vd_Vn_IMM_VLSL),
    SHRN2_Vd_Vn_IMM_VLSR(SHRN2_Vd_Vn_IMM_VLSR),
    SHRN_Vd_Vn_IMM_VLSR(SHRN_Vd_Vn_IMM_VLSR),
    SLI_Vd_Vn_IMM_VLSL(SLI_Vd_Vn_IMM_VLSL),
    SQRSHRN2_Vd_Vn_IMM_VLSR(SQRSHRN2_Vd_Vn_IMM_VLSR),
    SQRSHRN_Vd_Vn_IMM_VLSR(SQRSHRN_Vd_Vn_IMM_VLSR),
    SQRSHRUN2_Vd_Vn_IMM_VLSR(SQRSHRUN2_Vd_Vn_IMM_VLSR),
    SQRSHRUN_Vd_Vn_IMM_VLSR(SQRSHRUN_Vd_Vn_IMM_VLSR),
    SQSHLU_Vd_Vn_IMM_VLSL(SQSHLU_Vd_Vn_IMM_VLSL),
    SQSHL_Vd_Vn_IMM_VLSL(SQSHL_Vd_Vn_IMM_VLSL),
    SQSHRN2_Vd_Vn_IMM_VLSR(SQSHRN2_Vd_Vn_IMM_VLSR),
    SQSHRN_Vd_Vn_IMM_VLSR(SQSHRN_Vd_Vn_IMM_VLSR),
    SQSHRUN2_Vd_Vn_IMM_VLSR(SQSHRUN2_Vd_Vn_IMM_VLSR),
    SQSHRUN_Vd_Vn_IMM_VLSR(SQSHRUN_Vd_Vn_IMM_VLSR),
    SRI_Vd_Vn_IMM_VLSR(SRI_Vd_Vn_IMM_VLSR),
    SRSHR_Vd_Vn_IMM_VLSR(SRSHR_Vd_Vn_IMM_VLSR),
    SRSRA_Vd_Vn_IMM_VLSR(SRSRA_Vd_Vn_IMM_VLSR),
    SSHLL2_Vd_Vn_IMM_VLSL(SSHLL2_Vd_Vn_IMM_VLSL),
    SSHLL_Vd_Vn_IMM_VLSL(SSHLL_Vd_Vn_IMM_VLSL),
    SSHR_Vd_Vn_IMM_VLSR(SSHR_Vd_Vn_IMM_VLSR),
    SSRA_Vd_Vn_IMM_VLSR(SSRA_Vd_Vn_IMM_VLSR),
    UCVTF_Vd_V_2S_Vn_V_2S_IMM_VLSR_V_2S(UCVTF_Vd_V_2S_Vn_V_2S_IMM_VLSR_V_2S),
    UCVTF_Vd_Vn_IMM_VLSR(UCVTF_Vd_Vn_IMM_VLSR),
    UQRSHRN2_Vd_Vn_IMM_VLSR(UQRSHRN2_Vd_Vn_IMM_VLSR),
    UQRSHRN_Vd_Vn_IMM_VLSR(UQRSHRN_Vd_Vn_IMM_VLSR),
    UQSHL_Vd_Vn_IMM_VLSL(UQSHL_Vd_Vn_IMM_VLSL),
    UQSHRN2_Vd_Vn_IMM_VLSR(UQSHRN2_Vd_Vn_IMM_VLSR),
    UQSHRN_Vd_Vn_IMM_VLSR(UQSHRN_Vd_Vn_IMM_VLSR),
    URSHR_Vd_Vn_IMM_VLSR(URSHR_Vd_Vn_IMM_VLSR),
    URSRA_Vd_Vn_IMM_VLSR(URSRA_Vd_Vn_IMM_VLSR),
    USHLL2_Vd_Vn_IMM_VLSL(USHLL2_Vd_Vn_IMM_VLSL),
    USHLL_Vd_Vn_IMM_VLSL(USHLL_Vd_Vn_IMM_VLSL),
    USHR_Vd_Vn_IMM_VLSR(USHR_Vd_Vn_IMM_VLSR),
    USRA_Vd_Vn_IMM_VLSR(USRA_Vd_Vn_IMM_VLSR),
}
#[derive(Debug, PartialEq, Eq, Copy, Clone)]
pub enum LDST_IMM10 {
    LDRAA_Rt_ADDR_SIMM10(LDRAA_Rt_ADDR_SIMM10),
    LDRAB_Rt_ADDR_SIMM10(LDRAB_Rt_ADDR_SIMM10),
}
#[derive(Debug, PartialEq, Eq, Copy, Clone)]
pub enum LOADLIT {
    LDRSW_Rt_ADDR_PCREL19(LDRSW_Rt_ADDR_PCREL19),
    LDR_Ft_ADDR_PCREL19(LDR_Ft_ADDR_PCREL19),
    LDR_Rt_ADDR_PCREL19(LDR_Rt_ADDR_PCREL19),
    PRFM_PRFOP_ADDR_PCREL19(PRFM_PRFOP_ADDR_PCREL19),
}
#[derive(Debug, PartialEq, Eq, Copy, Clone)]
pub enum ASIMDINS {
    DUP_Vd_En(DUP_Vd_En),
    DUP_Vd_Rn(DUP_Vd_Rn),
    INS_Ed_En(INS_Ed_En),
    INS_Ed_Rn(INS_Ed_Rn),
    SMOV_Rd_En(SMOV_Rd_En),
    UMOV_Rd_En(UMOV_Rd_En),
}
#[derive(Debug, PartialEq, Eq, Copy, Clone)]
pub enum LDSTPAIR_INDEXED {
    LDPSW_Rt_X_Rt2_X_ADDR_SIMM7_S_S(LDPSW_Rt_X_Rt2_X_ADDR_SIMM7_S_S),
    LDP_Ft_S_S_Ft2_S_S_ADDR_SIMM7_S_S(LDP_Ft_S_S_Ft2_S_S_ADDR_SIMM7_S_S),
    LDP_Rt_W_Rt2_W_ADDR_SIMM7_S_S(LDP_Rt_W_Rt2_W_ADDR_SIMM7_S_S),
    STGP_Rt_X_Rt2_X_ADDR_SIMM11_imm_tag(STGP_Rt_X_Rt2_X_ADDR_SIMM11_imm_tag),
    STP_Ft_S_S_Ft2_S_S_ADDR_SIMM7_S_S(STP_Ft_S_S_Ft2_S_S_ADDR_SIMM7_S_S),
    STP_Rt_W_Rt2_W_ADDR_SIMM7_S_S(STP_Rt_W_Rt2_W_ADDR_SIMM7_S_S),
}
#[derive(Debug, PartialEq, Eq, Copy, Clone)]
pub enum DP_2SRC {
    ASRV_Rd_Rn_Rm(ASRV_Rd_Rn_Rm),
    CRC32B_Rd_Rn_Rm(CRC32B_Rd_Rn_Rm),
    CRC32CB_Rd_Rn_Rm(CRC32CB_Rd_Rn_Rm),
    CRC32CH_Rd_Rn_Rm(CRC32CH_Rd_Rn_Rm),
    CRC32CW_Rd_Rn_Rm(CRC32CW_Rd_Rn_Rm),
    CRC32CX_Rd_Rn_Rm(CRC32CX_Rd_Rn_Rm),
    CRC32H_Rd_Rn_Rm(CRC32H_Rd_Rn_Rm),
    CRC32W_Rd_Rn_Rm(CRC32W_Rd_Rn_Rm),
    CRC32X_Rd_Rn_Rm(CRC32X_Rd_Rn_Rm),
    GMI_Rd_Rn_SP_Rm(GMI_Rd_Rn_SP_Rm),
    IRG_Rd_SP_Rn_SP_Rm(IRG_Rd_SP_Rn_SP_Rm),
    LSLV_Rd_Rn_Rm(LSLV_Rd_Rn_Rm),
    LSRV_Rd_Rn_Rm(LSRV_Rd_Rn_Rm),
    PACGA_Rd_Rn_Rm_SP(PACGA_Rd_Rn_Rm_SP),
    RORV_Rd_Rn_Rm(RORV_Rd_Rn_Rm),
    SDIV_Rd_Rn_Rm(SDIV_Rd_Rn_Rm),
    SUBPS_Rd_Rn_SP_Rm_SP(SUBPS_Rd_Rn_SP_Rm_SP),
    SUBP_Rd_Rn_SP_Rm_SP(SUBP_Rd_Rn_SP_Rm_SP),
    UDIV_Rd_Rn_Rm(UDIV_Rd_Rn_Rm),
}
#[derive(Debug, PartialEq, Eq, Copy, Clone)]
pub enum COMPBRANCH {
    CBNZ_Rt_ADDR_PCREL19(CBNZ_Rt_ADDR_PCREL19),
    CBZ_Rt_ADDR_PCREL19(CBZ_Rt_ADDR_PCREL19),
}
#[derive(Debug, PartialEq, Eq, Copy, Clone)]
pub enum ASISDSHF {
    FCVTZS_Sd_S_S_Sn_S_S_IMM_VLSR_S_S(FCVTZS_Sd_S_S_Sn_S_S_IMM_VLSR_S_S),
    FCVTZS_Sd_Sn_IMM_VLSR(FCVTZS_Sd_Sn_IMM_VLSR),
    FCVTZU_Sd_S_S_Sn_S_S_IMM_VLSR_S_S(FCVTZU_Sd_S_S_Sn_S_S_IMM_VLSR_S_S),
    FCVTZU_Sd_Sn_IMM_VLSR(FCVTZU_Sd_Sn_IMM_VLSR),
    SCVTF_Sd_S_S_Sn_S_S_IMM_VLSR_S_S(SCVTF_Sd_S_S_Sn_S_S_IMM_VLSR_S_S),
    SCVTF_Sd_Sn_IMM_VLSR(SCVTF_Sd_Sn_IMM_VLSR),
    SHL_Sd_Sn_IMM_VLSL(SHL_Sd_Sn_IMM_VLSL),
    SLI_Sd_Sn_IMM_VLSL(SLI_Sd_Sn_IMM_VLSL),
    SQRSHRN_Sd_Sn_IMM_VLSR(SQRSHRN_Sd_Sn_IMM_VLSR),
    SQRSHRUN_Sd_Sn_IMM_VLSR(SQRSHRUN_Sd_Sn_IMM_VLSR),
    SQSHLU_Sd_Sn_IMM_VLSL(SQSHLU_Sd_Sn_IMM_VLSL),
    SQSHL_Sd_Sn_IMM_VLSL(SQSHL_Sd_Sn_IMM_VLSL),
    SQSHRN_Sd_Sn_IMM_VLSR(SQSHRN_Sd_Sn_IMM_VLSR),
    SQSHRUN_Sd_Sn_IMM_VLSR(SQSHRUN_Sd_Sn_IMM_VLSR),
    SRI_Sd_Sn_IMM_VLSR(SRI_Sd_Sn_IMM_VLSR),
    SRSHR_Sd_Sn_IMM_VLSR(SRSHR_Sd_Sn_IMM_VLSR),
    SRSRA_Sd_Sn_IMM_VLSR(SRSRA_Sd_Sn_IMM_VLSR),
    SSHR_Sd_Sn_IMM_VLSR(SSHR_Sd_Sn_IMM_VLSR),
    SSRA_Sd_Sn_IMM_VLSR(SSRA_Sd_Sn_IMM_VLSR),
    UCVTF_Sd_S_S_Sn_S_S_IMM_VLSR_S_S(UCVTF_Sd_S_S_Sn_S_S_IMM_VLSR_S_S),
    UCVTF_Sd_Sn_IMM_VLSR(UCVTF_Sd_Sn_IMM_VLSR),
    UQRSHRN_Sd_Sn_IMM_VLSR(UQRSHRN_Sd_Sn_IMM_VLSR),
    UQSHL_Sd_Sn_IMM_VLSL(UQSHL_Sd_Sn_IMM_VLSL),
    UQSHRN_Sd_Sn_IMM_VLSR(UQSHRN_Sd_Sn_IMM_VLSR),
    URSHR_Sd_Sn_IMM_VLSR(URSHR_Sd_Sn_IMM_VLSR),
    URSRA_Sd_Sn_IMM_VLSR(URSRA_Sd_Sn_IMM_VLSR),
    USHR_Sd_Sn_IMM_VLSR(USHR_Sd_Sn_IMM_VLSR),
    USRA_Sd_Sn_IMM_VLSR(USRA_Sd_Sn_IMM_VLSR),
}
#[derive(Debug, PartialEq, Eq, Copy, Clone)]
pub enum SME_SIZE_12_HS {
    LUTI4_SME_Zdnx4_SME_ZT0_SME_Zn_INDEX1_16(LUTI4_SME_Zdnx4_SME_ZT0_SME_Zn_INDEX1_16),
}
#[derive(Debug, PartialEq, Eq, Copy, Clone)]
pub enum IC_SYSTEM {
    CFINV(CFINV),
    CHKFEAT_X16(CHKFEAT_X16),
    CLREX_UIMM4(CLREX_UIMM4),
    DGH(DGH),
    DMB_BARRIER(DMB_BARRIER),
    DSB_BARRIER(DSB_BARRIER),
    DSB_BARRIER_DSB_NXS(DSB_BARRIER_DSB_NXS),
    HINT_UIMM7(HINT_UIMM7),
    ISB_BARRIER_ISB(ISB_BARRIER_ISB),
    MRRS_Rt_PAIRREG_SYSREG128(MRRS_Rt_PAIRREG_SYSREG128),
    MRS_Rt_SYSREG(MRS_Rt_SYSREG),
    MSRR_SYSREG128_Rt_PAIRREG(MSRR_SYSREG128_Rt_PAIRREG),
    MSR_PSTATEFIELD_UIMM4(MSR_PSTATEFIELD_UIMM4),
    MSR_SYSREG_Rt(MSR_SYSREG_Rt),
    RMIF_Rn_IMM_2_MASK(RMIF_Rn_IMM_2_MASK),
    SB(SB),
    SETF16_Rn(SETF16_Rn),
    SETF8_Rn(SETF8_Rn),
    SYSL_Rt_UIMM3_OP1_CRn_CRm_UIMM3_OP2(SYSL_Rt_UIMM3_OP1_CRn_CRm_UIMM3_OP2),
    SYSP_UIMM3_OP1_CRn_CRm_UIMM3_OP2_Rt_PAIRREG_OR_XZR(
        SYSP_UIMM3_OP1_CRn_CRm_UIMM3_OP2_Rt_PAIRREG_OR_XZR,
    ),
    SYS_UIMM3_OP1_CRn_CRm_UIMM3_OP2_Rt(SYS_UIMM3_OP1_CRn_CRm_UIMM3_OP2_Rt),
    WFET_Rd(WFET_Rd),
    WFIT_Rd(WFIT_Rd),
}
#[derive(Debug, PartialEq, Eq, Copy, Clone)]
pub enum FLOATDP3 {
    FMADD_Fd_Fn_Fm_Fa(FMADD_Fd_Fn_Fm_Fa),
    FMADD_Fd_S_S_Fn_S_S_Fm_S_S_Fa_S_S(FMADD_Fd_S_S_Fn_S_S_Fm_S_S_Fa_S_S),
    FMSUB_Fd_Fn_Fm_Fa(FMSUB_Fd_Fn_Fm_Fa),
    FMSUB_Fd_S_S_Fn_S_S_Fm_S_S_Fa_S_S(FMSUB_Fd_S_S_Fn_S_S_Fm_S_S_Fa_S_S),
    FNMADD_Fd_Fn_Fm_Fa(FNMADD_Fd_Fn_Fm_Fa),
    FNMADD_Fd_S_S_Fn_S_S_Fm_S_S_Fa_S_S(FNMADD_Fd_S_S_Fn_S_S_Fm_S_S_Fa_S_S),
    FNMSUB_Fd_Fn_Fm_Fa(FNMSUB_Fd_Fn_Fm_Fa),
    FNMSUB_Fd_S_S_Fn_S_S_Fm_S_S_Fa_S_S(FNMSUB_Fd_S_S_Fn_S_S_Fm_S_S_Fa_S_S),
}
#[derive(Debug, PartialEq, Eq, Copy, Clone)]
pub enum SVE2_URQVS {
    ADDQV_Vd_SVE_Pg3_SVE_Zn(ADDQV_Vd_SVE_Pg3_SVE_Zn),
    ANDQV_Vd_SVE_Pg3_SVE_Zn(ANDQV_Vd_SVE_Pg3_SVE_Zn),
    EORQV_Vd_SVE_Pg3_SVE_Zn(EORQV_Vd_SVE_Pg3_SVE_Zn),
    FADDQV_Vd_SVE_Pg3_SVE_Zn(FADDQV_Vd_SVE_Pg3_SVE_Zn),
    FMAXNMQV_Vd_SVE_Pg3_SVE_Zn(FMAXNMQV_Vd_SVE_Pg3_SVE_Zn),
    FMAXQV_Vd_SVE_Pg3_SVE_Zn(FMAXQV_Vd_SVE_Pg3_SVE_Zn),
    FMINNMQV_Vd_SVE_Pg3_SVE_Zn(FMINNMQV_Vd_SVE_Pg3_SVE_Zn),
    FMINQV_Vd_SVE_Pg3_SVE_Zn(FMINQV_Vd_SVE_Pg3_SVE_Zn),
    SMAXQV_Vd_SVE_Pg3_SVE_Zn(SMAXQV_Vd_SVE_Pg3_SVE_Zn),
    SMINQV_Vd_SVE_Pg3_SVE_Zn(SMINQV_Vd_SVE_Pg3_SVE_Zn),
    UMAXQV_Vd_SVE_Pg3_SVE_Zn(UMAXQV_Vd_SVE_Pg3_SVE_Zn),
    UMINQV_Vd_SVE_Pg3_SVE_Zn(UMINQV_Vd_SVE_Pg3_SVE_Zn),
}
#[derive(Debug, PartialEq, Eq, Copy, Clone)]
pub enum SVE_INDEX {
    DUP_SVE_Zd_SVE_Zn_INDEX(DUP_SVE_Zd_SVE_Zn_INDEX),
}
#[derive(Debug, PartialEq, Eq, Copy, Clone)]
pub enum LDST_IMM9 {
    LDRB_Rt_ADDR_SIMM9(LDRB_Rt_ADDR_SIMM9),
    LDRH_Rt_ADDR_SIMM9(LDRH_Rt_ADDR_SIMM9),
    LDRSB_Rt_ADDR_SIMM9(LDRSB_Rt_ADDR_SIMM9),
    LDRSH_Rt_ADDR_SIMM9(LDRSH_Rt_ADDR_SIMM9),
    LDRSW_Rt_ADDR_SIMM9(LDRSW_Rt_ADDR_SIMM9),
    LDR_Ft_ADDR_SIMM9(LDR_Ft_ADDR_SIMM9),
    LDR_Rt_ADDR_SIMM9(LDR_Rt_ADDR_SIMM9),
    ST2G_Rt_SP_X_ADDR_SIMM13_imm_tag(ST2G_Rt_SP_X_ADDR_SIMM13_imm_tag),
    STG_Rt_SP_X_ADDR_SIMM13_imm_tag(STG_Rt_SP_X_ADDR_SIMM13_imm_tag),
    STRB_Rt_ADDR_SIMM9(STRB_Rt_ADDR_SIMM9),
    STRH_Rt_ADDR_SIMM9(STRH_Rt_ADDR_SIMM9),
    STR_Ft_ADDR_SIMM9(STR_Ft_ADDR_SIMM9),
    STR_Rt_ADDR_SIMM9(STR_Rt_ADDR_SIMM9),
    STZ2G_Rt_SP_X_ADDR_SIMM13_imm_tag(STZ2G_Rt_SP_X_ADDR_SIMM13_imm_tag),
    STZG_Rt_SP_X_ADDR_SIMM13_imm_tag(STZG_Rt_SP_X_ADDR_SIMM13_imm_tag),
}
#[derive(Debug, PartialEq, Eq, Copy, Clone)]
pub enum SME_MOV {
    MOVA_SME_ZA_HV_idx_dest_SVE_Pg3_SVE_Zn(MOVA_SME_ZA_HV_idx_dest_SVE_Pg3_SVE_Zn),
    MOVA_SVE_Zd_SVE_Pg3_SME_ZA_HV_idx_src(MOVA_SVE_Zd_SVE_Pg3_SME_ZA_HV_idx_src),
    MOV_SME_ZA_HV_idx_dest_SVE_Pg3_SVE_Zn(MOV_SME_ZA_HV_idx_dest_SVE_Pg3_SVE_Zn),
    MOV_SVE_Zd_SVE_Pg3_SME_ZA_HV_idx_src(MOV_SVE_Zd_SVE_Pg3_SME_ZA_HV_idx_src),
}
#[derive(Debug, PartialEq, Eq, Copy, Clone)]
pub enum BRANCH_IMM {
    BL_ADDR_PCREL26(BL_ADDR_PCREL26),
    B_ADDR_PCREL26(B_ADDR_PCREL26),
}
#[derive(Debug, PartialEq, Eq, Copy, Clone)]
pub enum FLOAT2FIX {
    FCVTZS_Rd_Fn_FBITS(FCVTZS_Rd_Fn_FBITS),
    FCVTZS_Rd_W_Fn_S_D_FBITS_imm_1_32(FCVTZS_Rd_W_Fn_S_D_FBITS_imm_1_32),
    FCVTZU_Rd_Fn_FBITS(FCVTZU_Rd_Fn_FBITS),
    FCVTZU_Rd_W_Fn_S_D_FBITS_imm_1_32(FCVTZU_Rd_W_Fn_S_D_FBITS_imm_1_32),
    SCVTF_Fd_Rn_FBITS(SCVTF_Fd_Rn_FBITS),
    SCVTF_Fd_S_D_Rn_W_FBITS_imm_1_32(SCVTF_Fd_S_D_Rn_W_FBITS_imm_1_32),
    UCVTF_Fd_Rn_FBITS(UCVTF_Fd_Rn_FBITS),
    UCVTF_Fd_S_D_Rn_W_FBITS_imm_1_32(UCVTF_Fd_S_D_Rn_W_FBITS_imm_1_32),
}
#[derive(Debug, PartialEq, Eq, Copy, Clone)]
pub enum ASISDDIFF {
    SQDMLAL_Sd_Sn_Sm(SQDMLAL_Sd_Sn_Sm),
    SQDMLSL_Sd_Sn_Sm(SQDMLSL_Sd_Sn_Sm),
    SQDMULL_Sd_Sn_Sm(SQDMULL_Sd_Sn_Sm),
}
#[derive(Debug, PartialEq, Eq, Copy, Clone)]
pub enum ASISDLSE {
    LD1_LVt_SIMD_ADDR_SIMPLE(LD1_LVt_SIMD_ADDR_SIMPLE),
    LD2_LVt_SIMD_ADDR_SIMPLE(LD2_LVt_SIMD_ADDR_SIMPLE),
    LD3_LVt_SIMD_ADDR_SIMPLE(LD3_LVt_SIMD_ADDR_SIMPLE),
    LD4_LVt_SIMD_ADDR_SIMPLE(LD4_LVt_SIMD_ADDR_SIMPLE),
    ST1_LVt_SIMD_ADDR_SIMPLE(ST1_LVt_SIMD_ADDR_SIMPLE),
    ST2_LVt_SIMD_ADDR_SIMPLE(ST2_LVt_SIMD_ADDR_SIMPLE),
    ST3_LVt_SIMD_ADDR_SIMPLE(ST3_LVt_SIMD_ADDR_SIMPLE),
    ST4_LVt_SIMD_ADDR_SIMPLE(ST4_LVt_SIMD_ADDR_SIMPLE),
}
#[derive(Debug, PartialEq, Eq, Copy, Clone)]
pub enum SME_STR {
    STR_SME_ZA_array_off4_SME_ADDR_RI_U4xVL(STR_SME_ZA_array_off4_SME_ADDR_RI_U4xVL),
}
#[derive(Debug, PartialEq, Eq, Copy, Clone)]
pub enum GCS {
    GCSPOPCX(GCSPOPCX),
    GCSPOPM(GCSPOPM),
    GCSPOPM_Rt(GCSPOPM_Rt),
    GCSPOPX(GCSPOPX),
    GCSPUSHM_Rt(GCSPUSHM_Rt),
    GCSPUSHX(GCSPUSHX),
    GCSSS1_Rt(GCSSS1_Rt),
    GCSSS2_Rt(GCSSS2_Rt),
    GCSSTR_Rt_Rn_SP(GCSSTR_Rt_Rn_SP),
    GCSSTTR_Rt_Rn_SP(GCSSTTR_Rt_Rn_SP),
}
#[derive(Debug, PartialEq, Eq, Copy, Clone)]
pub enum EXCEPTION {
    BRK_EXCEPTION(BRK_EXCEPTION),
    DCPS1_EXCEPTION(DCPS1_EXCEPTION),
    DCPS2_EXCEPTION(DCPS2_EXCEPTION),
    DCPS3_EXCEPTION(DCPS3_EXCEPTION),
    HLT_EXCEPTION(HLT_EXCEPTION),
    HVC_EXCEPTION(HVC_EXCEPTION),
    SMC_EXCEPTION(SMC_EXCEPTION),
    SVC_EXCEPTION(SVC_EXCEPTION),
    UDF_UNDEFINED(UDF_UNDEFINED),
}
#[derive(Debug, PartialEq, Eq, Copy, Clone)]
pub enum DOTPRODUCT {
    BFDOT_Vd_Vn_Em(BFDOT_Vd_Vn_Em),
    SDOT_Vd_Vn_Em(SDOT_Vd_Vn_Em),
    SDOT_Vd_Vn_Vm(SDOT_Vd_Vn_Vm),
    SUDOT_Vd_Vn_Em(SUDOT_Vd_Vn_Em),
    UDOT_Vd_Vn_Em(UDOT_Vd_Vn_Em),
    UDOT_Vd_Vn_Vm(UDOT_Vd_Vn_Vm),
    USDOT_Vd_Vn_Em(USDOT_Vd_Vn_Em),
}
#[derive(Debug, PartialEq, Eq, Copy, Clone)]
pub enum BRANCH_REG {
    BLRAAZ_Rn(BLRAAZ_Rn),
    BLRAA_Rn_Rd_SP(BLRAA_Rn_Rd_SP),
    BLRABZ_Rn(BLRABZ_Rn),
    BLRAB_Rn_Rd_SP(BLRAB_Rn_Rd_SP),
    BLR_Rn(BLR_Rn),
    BRAAZ_Rn(BRAAZ_Rn),
    BRAA_Rn_Rd_SP(BRAA_Rn_Rd_SP),
    BRABZ_Rn(BRABZ_Rn),
    BRAB_Rn_Rd_SP(BRAB_Rn_Rd_SP),
    BR_Rn(BR_Rn),
    DRPS(DRPS),
    ERET(ERET),
    ERETAA(ERETAA),
    ERETAB(ERETAB),
    RETAA(RETAA),
    RETAB(RETAB),
    RET_Rn(RET_Rn),
}
#[derive(Debug, PartialEq, Eq, Copy, Clone)]
pub enum SVE_SIZE_13 {
    PMULLB_SVE_Zd_S_H_SVE_Zn_S_B_SVE_Zm_16_S_B(PMULLB_SVE_Zd_S_H_SVE_Zn_S_B_SVE_Zm_16_S_B),
    PMULLT_SVE_Zd_S_H_SVE_Zn_S_B_SVE_Zm_16_S_B(PMULLT_SVE_Zd_S_H_SVE_Zn_S_B_SVE_Zm_16_S_B),
}
#[derive(Debug, PartialEq, Eq, Copy, Clone)]
pub enum LDSTEXCL {
    LDAPRB_Rt_ADDR_SIMPLE(LDAPRB_Rt_ADDR_SIMPLE),
    LDAPRH_Rt_ADDR_SIMPLE(LDAPRH_Rt_ADDR_SIMPLE),
    LDAPR_Rt_ADDR_SIMPLE(LDAPR_Rt_ADDR_SIMPLE),
    LDARB_Rt_ADDR_SIMPLE(LDARB_Rt_ADDR_SIMPLE),
    LDARH_Rt_ADDR_SIMPLE(LDARH_Rt_ADDR_SIMPLE),
    LDAR_Rt_ADDR_SIMPLE(LDAR_Rt_ADDR_SIMPLE),
    LDAXP_Rt_Rt2_ADDR_SIMPLE(LDAXP_Rt_Rt2_ADDR_SIMPLE),
    LDAXRB_Rt_ADDR_SIMPLE(LDAXRB_Rt_ADDR_SIMPLE),
    LDAXRH_Rt_ADDR_SIMPLE(LDAXRH_Rt_ADDR_SIMPLE),
    LDAXR_Rt_ADDR_SIMPLE(LDAXR_Rt_ADDR_SIMPLE),
    LDGM_Rt_ADDR_SIMPLE(LDGM_Rt_ADDR_SIMPLE),
    LDLARB_Rt_ADDR_SIMPLE(LDLARB_Rt_ADDR_SIMPLE),
    LDLARH_Rt_ADDR_SIMPLE(LDLARH_Rt_ADDR_SIMPLE),
    LDLAR_Rt_ADDR_SIMPLE(LDLAR_Rt_ADDR_SIMPLE),
    LDXP_Rt_Rt2_ADDR_SIMPLE(LDXP_Rt_Rt2_ADDR_SIMPLE),
    LDXRB_Rt_ADDR_SIMPLE(LDXRB_Rt_ADDR_SIMPLE),
    LDXRH_Rt_ADDR_SIMPLE(LDXRH_Rt_ADDR_SIMPLE),
    LDXR_Rt_ADDR_SIMPLE(LDXR_Rt_ADDR_SIMPLE),
    STGM_Rt_ADDR_SIMPLE(STGM_Rt_ADDR_SIMPLE),
    STLLRB_Rt_ADDR_SIMPLE(STLLRB_Rt_ADDR_SIMPLE),
    STLLRH_Rt_ADDR_SIMPLE(STLLRH_Rt_ADDR_SIMPLE),
    STLLR_Rt_ADDR_SIMPLE(STLLR_Rt_ADDR_SIMPLE),
    STLRB_Rt_ADDR_SIMPLE(STLRB_Rt_ADDR_SIMPLE),
    STLRH_Rt_ADDR_SIMPLE(STLRH_Rt_ADDR_SIMPLE),
    STLR_Rt_ADDR_SIMPLE(STLR_Rt_ADDR_SIMPLE),
    STLXP_Rs_Rt_Rt2_ADDR_SIMPLE(STLXP_Rs_Rt_Rt2_ADDR_SIMPLE),
    STLXRB_Rs_Rt_ADDR_SIMPLE(STLXRB_Rs_Rt_ADDR_SIMPLE),
    STLXRH_Rs_Rt_ADDR_SIMPLE(STLXRH_Rs_Rt_ADDR_SIMPLE),
    STLXR_Rs_Rt_ADDR_SIMPLE(STLXR_Rs_Rt_ADDR_SIMPLE),
    STXP_Rs_Rt_Rt2_ADDR_SIMPLE(STXP_Rs_Rt_Rt2_ADDR_SIMPLE),
    STXRB_Rs_Rt_ADDR_SIMPLE(STXRB_Rs_Rt_ADDR_SIMPLE),
    STXRH_Rs_Rt_ADDR_SIMPLE(STXRH_Rs_Rt_ADDR_SIMPLE),
    STXR_Rs_Rt_ADDR_SIMPLE(STXR_Rs_Rt_ADDR_SIMPLE),
    STZGM_Rt_ADDR_SIMPLE(STZGM_Rt_ADDR_SIMPLE),
}
#[derive(Debug, PartialEq, Eq, Copy, Clone)]
pub enum LDST_UNPRIV {
    LDTRB_Rt_ADDR_SIMM9(LDTRB_Rt_ADDR_SIMM9),
    LDTRH_Rt_ADDR_SIMM9(LDTRH_Rt_ADDR_SIMM9),
    LDTRSB_Rt_ADDR_SIMM9(LDTRSB_Rt_ADDR_SIMM9),
    LDTRSH_Rt_ADDR_SIMM9(LDTRSH_Rt_ADDR_SIMM9),
    LDTRSW_Rt_ADDR_SIMM9(LDTRSW_Rt_ADDR_SIMM9),
    LDTR_Rt_ADDR_SIMM9(LDTR_Rt_ADDR_SIMM9),
    STTRB_Rt_ADDR_SIMM9(STTRB_Rt_ADDR_SIMM9),
    STTRH_Rt_ADDR_SIMM9(STTRH_Rt_ADDR_SIMM9),
    STTR_Rt_ADDR_SIMM9(STTR_Rt_ADDR_SIMM9),
}
#[derive(Debug, PartialEq, Eq, Copy, Clone)]
pub enum FLOATIMM {
    FMOV_Fd_FPIMM(FMOV_Fd_FPIMM),
    FMOV_Fd_S_S_FPIMM(FMOV_Fd_S_S_FPIMM),
}
#[derive(Debug, PartialEq, Eq, Copy, Clone)]
pub enum SVE_MOVPRFX {
    MOVPRFX_SVE_Zd_SVE_Pg3_SVE_Zn(MOVPRFX_SVE_Zd_SVE_Pg3_SVE_Zn),
}
#[derive(Debug, PartialEq, Eq, Copy, Clone)]
pub enum ASISDLSEP {
    LD1_LVt_SIMD_ADDR_POST(LD1_LVt_SIMD_ADDR_POST),
    LD2_LVt_SIMD_ADDR_POST(LD2_LVt_SIMD_ADDR_POST),
    LD3_LVt_SIMD_ADDR_POST(LD3_LVt_SIMD_ADDR_POST),
    LD4_LVt_SIMD_ADDR_POST(LD4_LVt_SIMD_ADDR_POST),
    ST1_LVt_SIMD_ADDR_POST(ST1_LVt_SIMD_ADDR_POST),
    ST2_LVt_SIMD_ADDR_POST(ST2_LVt_SIMD_ADDR_POST),
    ST3_LVt_SIMD_ADDR_POST(ST3_LVt_SIMD_ADDR_POST),
    ST4_LVt_SIMD_ADDR_POST(ST4_LVt_SIMD_ADDR_POST),
}
#[derive(Debug, PartialEq, Eq, Copy, Clone)]
pub enum RCPC3 {
    LDAP1_LEt_SIMD_ADDR_SIMPLE(LDAP1_LEt_SIMD_ADDR_SIMPLE),
    LDAPR_Rt_RCPC3_ADDR_POSTIND(LDAPR_Rt_RCPC3_ADDR_POSTIND),
    LDAPUR_Ft_RCPC3_ADDR_OFFSET(LDAPUR_Ft_RCPC3_ADDR_OFFSET),
    LDIAPP_Rt_Rs_RCPC3_ADDR_OPT_POSTIND(LDIAPP_Rt_Rs_RCPC3_ADDR_OPT_POSTIND),
    STILP_Rt_Rs_RCPC3_ADDR_OPT_PREIND_WB(STILP_Rt_Rs_RCPC3_ADDR_OPT_PREIND_WB),
    STL1_LEt_SIMD_ADDR_SIMPLE(STL1_LEt_SIMD_ADDR_SIMPLE),
    STLR_Rt_RCPC3_ADDR_PREIND_WB(STLR_Rt_RCPC3_ADDR_PREIND_WB),
    STLUR_Ft_RCPC3_ADDR_OFFSET(STLUR_Ft_RCPC3_ADDR_OFFSET),
}
#[derive(Debug, PartialEq, Eq, Copy, Clone)]
pub enum SVE_PRED_ZM {
    BRKA_SVE_Pd_SVE_Pg4_10_SVE_Pn(BRKA_SVE_Pd_SVE_Pg4_10_SVE_Pn),
    BRKB_SVE_Pd_SVE_Pg4_10_SVE_Pn(BRKB_SVE_Pd_SVE_Pg4_10_SVE_Pn),
}
#[derive(Debug, PartialEq, Eq, Copy, Clone)]
pub enum SME_SIZE_12_BHS {
    LUTI2_SME_Zdnx2_SME_ZT0_SME_Zn_INDEX3_15(LUTI2_SME_Zdnx2_SME_ZT0_SME_Zn_INDEX3_15),
    LUTI2_SME_Zdnx4_SME_ZT0_SME_Zn_INDEX2_16(LUTI2_SME_Zdnx4_SME_ZT0_SME_Zn_INDEX2_16),
    LUTI2_SVE_Zd_SME_ZT0_SME_Zn_INDEX4_14(LUTI2_SVE_Zd_SME_ZT0_SME_Zn_INDEX4_14),
    LUTI4_SME_Zdnx2_SME_ZT0_SME_Zn_INDEX2_15(LUTI4_SME_Zdnx2_SME_ZT0_SME_Zn_INDEX2_15),
    LUTI4_SVE_Zd_SME_ZT0_SME_Zn_INDEX3_14(LUTI4_SVE_Zd_SME_ZT0_SME_Zn_INDEX3_14),
}
#[derive(Debug, PartialEq, Eq, Copy, Clone)]
pub enum FLOATSEL {
    FCSEL_Fd_Fn_Fm_COND(FCSEL_Fd_Fn_Fm_COND),
    FCSEL_Fd_S_S_Fn_S_S_Fm_S_S_COND(FCSEL_Fd_S_S_Fn_S_S_Fm_S_S_COND),
}
#[derive(Debug, PartialEq, Eq, Copy, Clone)]
pub enum SVE_INDEX1 {
    DUPQ_SVE_Zd_SVE_Zn_5_INDEX(DUPQ_SVE_Zd_SVE_Zn_5_INDEX),
}
#[derive(Debug, PartialEq, Eq, Copy, Clone)]
pub enum ASISDMISC {
    ABS_Sd_Sn(ABS_Sd_Sn),
    CMEQ_Sd_Sn_IMM0(CMEQ_Sd_Sn_IMM0),
    CMGE_Sd_Sn_IMM0(CMGE_Sd_Sn_IMM0),
    CMGT_Sd_Sn_IMM0(CMGT_Sd_Sn_IMM0),
    CMLE_Sd_Sn_IMM0(CMLE_Sd_Sn_IMM0),
    CMLT_Sd_Sn_IMM0(CMLT_Sd_Sn_IMM0),
    FCMEQ_Sd_S_H_Sn_S_H_FPIMM0(FCMEQ_Sd_S_H_Sn_S_H_FPIMM0),
    FCMEQ_Sd_Sn_FPIMM0(FCMEQ_Sd_Sn_FPIMM0),
    FCMGE_Sd_S_H_Sn_S_H_FPIMM0(FCMGE_Sd_S_H_Sn_S_H_FPIMM0),
    FCMGE_Sd_Sn_FPIMM0(FCMGE_Sd_Sn_FPIMM0),
    FCMGT_Sd_S_H_Sn_S_H_FPIMM0(FCMGT_Sd_S_H_Sn_S_H_FPIMM0),
    FCMGT_Sd_Sn_FPIMM0(FCMGT_Sd_Sn_FPIMM0),
    FCMLE_Sd_S_H_Sn_S_H_FPIMM0(FCMLE_Sd_S_H_Sn_S_H_FPIMM0),
    FCMLE_Sd_Sn_FPIMM0(FCMLE_Sd_Sn_FPIMM0),
    FCMLT_Sd_S_H_Sn_S_H_FPIMM0(FCMLT_Sd_S_H_Sn_S_H_FPIMM0),
    FCMLT_Sd_Sn_FPIMM0(FCMLT_Sd_Sn_FPIMM0),
    FCVTAS_Sd_S_H_Sn_S_H(FCVTAS_Sd_S_H_Sn_S_H),
    FCVTAS_Sd_Sn(FCVTAS_Sd_Sn),
    FCVTAU_Sd_S_H_Sn_S_H(FCVTAU_Sd_S_H_Sn_S_H),
    FCVTAU_Sd_Sn(FCVTAU_Sd_Sn),
    FCVTMS_Sd_S_H_Sn_S_H(FCVTMS_Sd_S_H_Sn_S_H),
    FCVTMS_Sd_Sn(FCVTMS_Sd_Sn),
    FCVTMU_Sd_S_H_Sn_S_H(FCVTMU_Sd_S_H_Sn_S_H),
    FCVTMU_Sd_Sn(FCVTMU_Sd_Sn),
    FCVTNS_Sd_S_H_Sn_S_H(FCVTNS_Sd_S_H_Sn_S_H),
    FCVTNS_Sd_Sn(FCVTNS_Sd_Sn),
    FCVTNU_Sd_S_H_Sn_S_H(FCVTNU_Sd_S_H_Sn_S_H),
    FCVTNU_Sd_Sn(FCVTNU_Sd_Sn),
    FCVTPS_Sd_S_H_Sn_S_H(FCVTPS_Sd_S_H_Sn_S_H),
    FCVTPS_Sd_Sn(FCVTPS_Sd_Sn),
    FCVTPU_Sd_S_H_Sn_S_H(FCVTPU_Sd_S_H_Sn_S_H),
    FCVTPU_Sd_Sn(FCVTPU_Sd_Sn),
    FCVTXN_Sd_Sn(FCVTXN_Sd_Sn),
    FCVTZS_Sd_S_H_Sn_S_H(FCVTZS_Sd_S_H_Sn_S_H),
    FCVTZS_Sd_Sn(FCVTZS_Sd_Sn),
    FCVTZU_Sd_S_H_Sn_S_H(FCVTZU_Sd_S_H_Sn_S_H),
    FCVTZU_Sd_Sn(FCVTZU_Sd_Sn),
    FRECPE_Sd_S_H_Sn_S_H(FRECPE_Sd_S_H_Sn_S_H),
    FRECPE_Sd_Sn(FRECPE_Sd_Sn),
    FRECPX_Sd_S_H_Sn_S_H(FRECPX_Sd_S_H_Sn_S_H),
    FRECPX_Sd_Sn(FRECPX_Sd_Sn),
    FRSQRTE_Sd_S_H_Sn_S_H(FRSQRTE_Sd_S_H_Sn_S_H),
    FRSQRTE_Sd_Sn(FRSQRTE_Sd_Sn),
    NEG_Sd_Sn(NEG_Sd_Sn),
    SCVTF_Sd_S_H_Sn_S_H(SCVTF_Sd_S_H_Sn_S_H),
    SCVTF_Sd_Sn(SCVTF_Sd_Sn),
    SQABS_Sd_Sn(SQABS_Sd_Sn),
    SQNEG_Sd_Sn(SQNEG_Sd_Sn),
    SQXTN_Sd_Sn(SQXTN_Sd_Sn),
    SQXTUN_Sd_Sn(SQXTUN_Sd_Sn),
    SUQADD_Sd_Sn(SUQADD_Sd_Sn),
    UCVTF_Sd_S_H_Sn_S_H(UCVTF_Sd_S_H_Sn_S_H),
    UCVTF_Sd_Sn(UCVTF_Sd_Sn),
    UQXTN_Sd_Sn(UQXTN_Sd_Sn),
    USQADD_Sd_Sn(USQADD_Sd_Sn),
}
#[derive(Debug, PartialEq, Eq, Copy, Clone)]
pub enum Opcode {
    SME_SIZE_22_HSD(SME_SIZE_22_HSD),
    DP_3SRC(DP_3SRC),
    SME_START(SME_START),
    ASIMDIMM(ASIMDIMM),
    ASIMDTBL(ASIMDTBL),
    SVE_LIMM(SVE_LIMM),
    LDST_POS(LDST_POS),
    ADDSUB_SHIFT(ADDSUB_SHIFT),
    ASIMDSAME(ASIMDSAME),
    SVE_SIZE_BHS(SVE_SIZE_BHS),
    FLOAT2INT(FLOAT2INT),
    LDST_UNSCALED(LDST_UNSCALED),
    ASISDSAME(ASISDSAME),
    ASIMDDIFF(ASIMDDIFF),
    CONDCMP_IMM(CONDCMP_IMM),
    SME_FP_SD(SME_FP_SD),
    SVE_SIZE_HSD(SVE_SIZE_HSD),
    FLOATCMP(FLOATCMP),
    LSE128_ATOMIC(LSE128_ATOMIC),
    CONDBRANCH(CONDBRANCH),
    SVE_SIZE_SD2(SVE_SIZE_SD2),
    FLOATDP1(FLOATDP1),
    PCRELADDR(PCRELADDR),
    BITFIELD(BITFIELD),
    LOG_IMM(LOG_IMM),
    ASISDONE(ASISDONE),
    CONDSEL(CONDSEL),
    CONDCMP_REG(CONDCMP_REG),
    ASIMDELEM(ASIMDELEM),
    ADDSUB_CARRY(ADDSUB_CARRY),
    SVE_SHIFT_TSZ_BHSD(SVE_SHIFT_TSZ_BHSD),
    CRYPTOSM4(CRYPTOSM4),
    SME_SHIFT(SME_SHIFT),
    ASIMDEXT(ASIMDEXT),
    CRYPTOSM3(CRYPTOSM3),
    ASISDELEM(ASISDELEM),
    LSE_ATOMIC(LSE_ATOMIC),
    ASIMDPERM(ASIMDPERM),
    LDSTNAPAIR_OFFS(LDSTNAPAIR_OFFS),
    CSSC(CSSC),
    CRYPTOSHA2(CRYPTOSHA2),
    MOVEWIDE(MOVEWIDE),
    ASISDLSOP(ASISDLSOP),
    ASIMDALL(ASIMDALL),
    SVE_SHIFT_PRED(SVE_SHIFT_PRED),
    SVE_SHIFT_UNPRED(SVE_SHIFT_UNPRED),
    SME_LDR(SME_LDR),
    SVE_SHIFT_TSZ_HSD(SVE_SHIFT_TSZ_HSD),
    CRYPTOSHA3(CRYPTOSHA3),
    AARCH64_MISC(AARCH64_MISC),
    THE(THE),
    SVE_SIZE_BH(SVE_SIZE_BH),
    SVE_CPY(SVE_CPY),
    SME2_MOV(SME2_MOV),
    LOG_SHIFT(LOG_SHIFT),
    SME_PSEL(SME_PSEL),
    SME_SIZE_22(SME_SIZE_22),
    SME_STOP(SME_STOP),
    BFLOAT16(BFLOAT16),
    ADDSUB_EXT(ADDSUB_EXT),
    ASISDLSO(ASISDLSO),
    LDSTPAIR_OFF(LDSTPAIR_OFF),
    FLOATDP2(FLOATDP2),
    ASIMDMISC(ASIMDMISC),
    EXTRACT(EXTRACT),
    SVE_SIZE_SD(SVE_SIZE_SD),
    SVE_SIZE_BHSD(SVE_SIZE_BHSD),
    SVE_SIZE_HSD2(SVE_SIZE_HSD2),
    ADDSUB_IMM(ADDSUB_IMM),
    ASISDPAIR(ASISDPAIR),
    SME_SZ_23(SME_SZ_23),
    SME_MISC(SME_MISC),
    DP_1SRC(DP_1SRC),
    CRYPTOAES(CRYPTOAES),
    SVE_MISC(SVE_MISC),
    SME_INT_SD(SME_INT_SD),
    FLOATCCMP(FLOATCCMP),
    SME2_MOVAZ(SME2_MOVAZ),
    TESTBRANCH(TESTBRANCH),
    LDST_REGOFF(LDST_REGOFF),
    SVE_SIZE_TSZ_BHS(SVE_SIZE_TSZ_BHS),
    ASIMDSHF(ASIMDSHF),
    LDST_IMM10(LDST_IMM10),
    LOADLIT(LOADLIT),
    ASIMDINS(ASIMDINS),
    LDSTPAIR_INDEXED(LDSTPAIR_INDEXED),
    DP_2SRC(DP_2SRC),
    COMPBRANCH(COMPBRANCH),
    ASISDSHF(ASISDSHF),
    SME_SIZE_12_HS(SME_SIZE_12_HS),
    IC_SYSTEM(IC_SYSTEM),
    FLOATDP3(FLOATDP3),
    SVE2_URQVS(SVE2_URQVS),
    SVE_INDEX(SVE_INDEX),
    LDST_IMM9(LDST_IMM9),
    SME_MOV(SME_MOV),
    BRANCH_IMM(BRANCH_IMM),
    FLOAT2FIX(FLOAT2FIX),
    ASISDDIFF(ASISDDIFF),
    ASISDLSE(ASISDLSE),
    SME_STR(SME_STR),
    GCS(GCS),
    EXCEPTION(EXCEPTION),
    DOTPRODUCT(DOTPRODUCT),
    BRANCH_REG(BRANCH_REG),
    SVE_SIZE_13(SVE_SIZE_13),
    LDSTEXCL(LDSTEXCL),
    LDST_UNPRIV(LDST_UNPRIV),
    FLOATIMM(FLOATIMM),
    SVE_MOVPRFX(SVE_MOVPRFX),
    ASISDLSEP(ASISDLSEP),
    RCPC3(RCPC3),
    SVE_PRED_ZM(SVE_PRED_ZM),
    SME_SIZE_12_BHS(SME_SIZE_12_BHS),
    FLOATSEL(FLOATSEL),
    SVE_INDEX1(SVE_INDEX1),
    ASISDMISC(ASISDMISC),
}
impl ABS_Rd_Rn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "abs",
        aliases: &[],
        opcode: 0x5ac02000,
        mask: 0x7ffffc00,
        class: InsnClass::CSSC,
        feature_set: InsnFeatureSet::CSSC,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SF_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::CSSC(CSSC::ABS_Rd_Rn(ABS_Rd_Rn::from(bits)))
    }
}
impl InsnOpcode for ABS_Rd_Rn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ABS_SVE_Zd_SVE_Pg3_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "abs",
        aliases: &[],
        opcode: 0x416a000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M, InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::ABS_SVE_Zd_SVE_Pg3_SVE_Zn(
            ABS_SVE_Zd_SVE_Pg3_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for ABS_SVE_Zd_SVE_Pg3_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ABS_Vd_Vn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "abs",
        aliases: &[],
        opcode: 0xe20b800,
        mask: 0xbf3ffc00,
        class: InsnClass::ASIMDMISC,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDMISC(ASIMDMISC::ABS_Vd_Vn(ABS_Vd_Vn::from(bits)))
    }
}
impl InsnOpcode for ABS_Vd_Vn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ABS_Sd_Sn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "abs",
        aliases: &[],
        opcode: 0x5e20b800,
        mask: 0xff3ffc00,
        class: InsnClass::ASISDMISC,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMD_SCALAR_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDMISC(ASISDMISC::ABS_Sd_Sn(ABS_Sd_Sn::from(bits)))
    }
}
impl InsnOpcode for ABS_Sd_Sn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ADC_Rd_Rn_Rm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "adc",
        aliases: &[],
        opcode: 0x1a000000,
        mask: 0x7fe0fc00,
        class: InsnClass::ADDSUB_CARRY,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rm,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SF_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ADDSUB_CARRY(ADDSUB_CARRY::ADC_Rd_Rn_Rm(ADC_Rd_Rn_Rm::from(bits)))
    }
}
impl InsnOpcode for ADC_Rd_Rn_Rm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ADCLB_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "adclb",
        aliases: &[],
        opcode: 0x4500d000,
        mask: 0xffa0fc00,
        class: InsnClass::SVE_SIZE_SD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_SD(SVE_SIZE_SD::ADCLB_SVE_Zd_SVE_Zn_SVE_Zm_16(
            ADCLB_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for ADCLB_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ADCLT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "adclt",
        aliases: &[],
        opcode: 0x4500d400,
        mask: 0xffa0fc00,
        class: InsnClass::SVE_SIZE_SD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_SD(SVE_SIZE_SD::ADCLT_SVE_Zd_SVE_Zn_SVE_Zm_16(
            ADCLT_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for ADCLT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ADCS_Rd_Rn_Rm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "adcs",
        aliases: &[],
        opcode: 0x3a000000,
        mask: 0x7fe0fc00,
        class: InsnClass::ADDSUB_CARRY,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rm,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SF_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ADDSUB_CARRY(ADDSUB_CARRY::ADCS_Rd_Rn_Rm(ADCS_Rd_Rn_Rm::from(bits)))
    }
}
impl InsnOpcode for ADCS_Rd_Rn_Rm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ADD_SME_ZA_array_off3_0_SVE_ZnxN_SME_Zm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "add",
        aliases: &[],
        opcode: 0xc1201810,
        mask: 0xffb09c18,
        class: InsnClass::SME_INT_SD,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off3_0,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_0,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ZnxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm,
                    lsb: 16,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_INT_SD(SME_INT_SD::ADD_SME_ZA_array_off3_0_SVE_ZnxN_SME_Zm(
            ADD_SME_ZA_array_off3_0_SVE_ZnxN_SME_Zm::from(bits),
        ))
    }
}
impl InsnOpcode for ADD_SME_ZA_array_off3_0_SVE_ZnxN_SME_Zm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ADD_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_S_SME_Zm_S_S {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "add",
        aliases: &[],
        opcode: 0xc1301810,
        mask: 0xffb09c18,
        class: InsnClass::SME_INT_SD,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off3_0,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_0,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ZnxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm,
                    lsb: 16,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_4.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_INT_SD(
            SME_INT_SD::ADD_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_S_SME_Zm_S_S(
                ADD_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_S_SME_Zm_S_S::from(bits),
            ),
        )
    }
}
impl InsnOpcode for ADD_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_S_SME_Zm_S_S {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ADD_SME_ZA_array_off3_0_SME_Znx2_SME_Zmx2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "add",
        aliases: &[],
        opcode: 0xc1a01810,
        mask: 0xffa19c38,
        class: InsnClass::SME_INT_SD,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off3_0,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_0,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn2,
                    lsb: 6,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zmx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm2,
                    lsb: 17,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_INT_SD(SME_INT_SD::ADD_SME_ZA_array_off3_0_SME_Znx2_SME_Zmx2(
            ADD_SME_ZA_array_off3_0_SME_Znx2_SME_Zmx2::from(bits),
        ))
    }
}
impl InsnOpcode for ADD_SME_ZA_array_off3_0_SME_Znx2_SME_Zmx2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ADD_SME_ZA_array_off3_0_SME_Znx4_SME_Zmx4 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "add",
        aliases: &[],
        opcode: 0xc1a11810,
        mask: 0xffa39c78,
        class: InsnClass::SME_INT_SD,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off3_0,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_0,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn4,
                    lsb: 7,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zmx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm4,
                    lsb: 18,
                    width: 3,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_4.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_INT_SD(SME_INT_SD::ADD_SME_ZA_array_off3_0_SME_Znx4_SME_Zmx4(
            ADD_SME_ZA_array_off3_0_SME_Znx4_SME_Zmx4::from(bits),
        ))
    }
}
impl InsnOpcode for ADD_SME_ZA_array_off3_0_SME_Znx4_SME_Zmx4 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ADD_SME_ZA_array_off3_0_SME_Znx2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "add",
        aliases: &[],
        opcode: 0xc1a01c10,
        mask: 0xffbf9c38,
        class: InsnClass::SME_INT_SD,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off3_0,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_0,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn2,
                    lsb: 6,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_INT_SD(SME_INT_SD::ADD_SME_ZA_array_off3_0_SME_Znx2(
            ADD_SME_ZA_array_off3_0_SME_Znx2::from(bits),
        ))
    }
}
impl InsnOpcode for ADD_SME_ZA_array_off3_0_SME_Znx2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ADD_SME_ZA_array_off3_0_SME_Znx4 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "add",
        aliases: &[],
        opcode: 0xc1a11c10,
        mask: 0xffbf9c78,
        class: InsnClass::SME_INT_SD,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off3_0,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_0,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn4,
                    lsb: 7,
                    width: 3,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_4.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_INT_SD(SME_INT_SD::ADD_SME_ZA_array_off3_0_SME_Znx4(
            ADD_SME_ZA_array_off3_0_SME_Znx4::from(bits),
        ))
    }
}
impl InsnOpcode for ADD_SME_ZA_array_off3_0_SME_Znx4 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ADD_SME_Zdnx2_SME_Zdnx2_SME_Zm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "add",
        aliases: &[],
        opcode: 0xc120a300,
        mask: 0xff30ffe1,
        class: InsnClass::SME_SIZE_22,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn2,
                    lsb: 1,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn2,
                    lsb: 1,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm,
                    lsb: 16,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_SIZE_22(SME_SIZE_22::ADD_SME_Zdnx2_SME_Zdnx2_SME_Zm(
            ADD_SME_Zdnx2_SME_Zdnx2_SME_Zm::from(bits),
        ))
    }
}
impl InsnOpcode for ADD_SME_Zdnx2_SME_Zdnx2_SME_Zm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ADD_SME_Zdnx4_SME_Zdnx4_SME_Zm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "add",
        aliases: &[],
        opcode: 0xc120ab00,
        mask: 0xff30ffe3,
        class: InsnClass::SME_SIZE_22,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn4,
                    lsb: 2,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn4,
                    lsb: 2,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm,
                    lsb: 16,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_SIZE_22(SME_SIZE_22::ADD_SME_Zdnx4_SME_Zdnx4_SME_Zm(
            ADD_SME_Zdnx4_SME_Zdnx4_SME_Zm::from(bits),
        ))
    }
}
impl InsnOpcode for ADD_SME_Zdnx4_SME_Zdnx4_SME_Zm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ADD_Rd_SP_Rn_SP_AIMM {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "add",
        aliases: &[],
        opcode: 0x11000000,
        mask: 0x7f800000,
        class: InsnClass::ADDSUB_IMM,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd_SP,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn_SP,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::AIMM,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::shift,
                        lsb: 22,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm12,
                        lsb: 10,
                        width: 12,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_ALIAS.bits() | InsnFlags::HAS_SF_FIELD.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ADDSUB_IMM(ADDSUB_IMM::ADD_Rd_SP_Rn_SP_AIMM(
            ADD_Rd_SP_Rn_SP_AIMM::from(bits),
        ))
    }
}
impl InsnOpcode for ADD_Rd_SP_Rn_SP_AIMM {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ADD_Rd_Rn_Rm_SFT {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "add",
        aliases: &[],
        opcode: 0xb000000,
        mask: 0x7f200000,
        class: InsnClass::ADDSUB_SHIFT,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rm_SFT,
                class: InsnOperandClass::MODIFIED_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SF_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ADDSUB_SHIFT(ADDSUB_SHIFT::ADD_Rd_Rn_Rm_SFT(ADD_Rd_Rn_Rm_SFT::from(bits)))
    }
}
impl InsnOpcode for ADD_Rd_Rn_Rm_SFT {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ADD_Rd_SP_Rn_SP_Rm_EXT {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "add",
        aliases: &[],
        opcode: 0xb200000,
        mask: 0x7fe00000,
        class: InsnClass::ADDSUB_EXT,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd_SP,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn_SP,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rm_EXT,
                class: InsnOperandClass::MODIFIED_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::W],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SF_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ADDSUB_EXT(ADDSUB_EXT::ADD_Rd_SP_Rn_SP_Rm_EXT(
            ADD_Rd_SP_Rn_SP_Rm_EXT::from(bits),
        ))
    }
}
impl InsnOpcode for ADD_Rd_SP_Rn_SP_Rm_EXT {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "add",
        aliases: &[],
        opcode: 0x4000000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_5,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_5,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::ADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(
            ADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5::from(bits),
        ))
    }
}
impl InsnOpcode for ADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ADD_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "add",
        aliases: &[],
        opcode: 0x4200000,
        mask: 0xff20fc00,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::ADD_SVE_Zd_SVE_Zn_SVE_Zm_16(
            ADD_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for ADD_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ADD_SVE_Zd_SVE_Zd_SVE_AIMM {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "add",
        aliases: &[],
        opcode: 0x2520c000,
        mask: 0xff3fc000,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_AIMM,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_imm9,
                    lsb: 5,
                    width: 9,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::ADD_SVE_Zd_SVE_Zd_SVE_AIMM(
            ADD_SVE_Zd_SVE_Zd_SVE_AIMM::from(bits),
        ))
    }
}
impl InsnOpcode for ADD_SVE_Zd_SVE_Zd_SVE_AIMM {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ADD_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "add",
        aliases: &[],
        opcode: 0xe208400,
        mask: 0xbf20fc00,
        class: InsnClass::ASIMDSAME,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSAME(ASIMDSAME::ADD_Vd_Vn_Vm(ADD_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for ADD_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ADD_Sd_Sn_Sm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "add",
        aliases: &[],
        opcode: 0x5ee08400,
        mask: 0xffe0fc00,
        class: InsnClass::ASISDSAME,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sm,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMD_SCALAR_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDSAME(ASISDSAME::ADD_Sd_Sn_Sm(ADD_Sd_Sn_Sm::from(bits)))
    }
}
impl InsnOpcode for ADD_Sd_Sn_Sm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ADDG_Rd_SP_Rn_SP_UIMM10_UIMM4_ADDG {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "addg",
        aliases: &[],
        opcode: 0x91800000,
        mask: 0xffc0c000,
        class: InsnClass::ADDSUB_IMM,
        feature_set: InsnFeatureSet::MEMTAG,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd_SP,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn_SP,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::UIMM10,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::immr,
                    lsb: 16,
                    width: 6,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::UIMM4_ADDG,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::imm4_10,
                    lsb: 10,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ADDSUB_IMM(ADDSUB_IMM::ADDG_Rd_SP_Rn_SP_UIMM10_UIMM4_ADDG(
            ADDG_Rd_SP_Rn_SP_UIMM10_UIMM4_ADDG::from(bits),
        ))
    }
}
impl InsnOpcode for ADDG_Rd_SP_Rn_SP_UIMM10_UIMM4_ADDG {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ADDHA_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "addha",
        aliases: &[],
        opcode: 0xc0900000,
        mask: 0xffff001c,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZAda_2b,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_ZAda_2b,
                    lsb: 0,
                    width: 2,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Pm,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Pm,
                    lsb: 13,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::ADDHA_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn(
            ADDHA_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for ADDHA_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ADDHA_SME_ZAda_3b_SVE_Pg3_SME_Pm_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "addha",
        aliases: &[],
        opcode: 0xc0d00000,
        mask: 0xffff0018,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME_I16I64,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZAda_3b,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_ZAda_3b,
                    lsb: 0,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Pm,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Pm,
                    lsb: 13,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::ADDHA_SME_ZAda_3b_SVE_Pg3_SME_Pm_SVE_Zn(
            ADDHA_SME_ZAda_3b_SVE_Pg3_SME_Pm_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for ADDHA_SME_ZAda_3b_SVE_Pg3_SME_Pm_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ADDHN_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "addhn",
        aliases: &[],
        opcode: 0xe204000,
        mask: 0xff20fc00,
        class: InsnClass::ASIMDDIFF,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_4H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8H, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8H, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDDIFF(ASIMDDIFF::ADDHN_Vd_Vn_Vm(ADDHN_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for ADDHN_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ADDHN2_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "addhn2",
        aliases: &[],
        opcode: 0x4e204000,
        mask: 0xff20fc00,
        class: InsnClass::ASIMDDIFF,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_16B, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8H, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8H, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDDIFF(ASIMDDIFF::ADDHN2_Vd_Vn_Vm(ADDHN2_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for ADDHN2_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ADDHNB_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "addhnb",
        aliases: &[],
        opcode: 0x45206000,
        mask: 0xff20fc00,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::ADDHNB_SVE_Zd_SVE_Zn_SVE_Zm_16(
            ADDHNB_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for ADDHNB_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ADDHNT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "addhnt",
        aliases: &[],
        opcode: 0x45206400,
        mask: 0xff20fc00,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::ADDHNT_SVE_Zd_SVE_Zn_SVE_Zm_16(
            ADDHNT_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for ADDHNT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ADDP_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "addp",
        aliases: &[],
        opcode: 0x4411a000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::ADDP_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(
            ADDP_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for ADDP_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ADDP_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "addp",
        aliases: &[],
        opcode: 0xe20bc00,
        mask: 0xbf20fc00,
        class: InsnClass::ASIMDSAME,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSAME(ASIMDSAME::ADDP_Vd_Vn_Vm(ADDP_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for ADDP_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ADDP_Sd_Vn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "addp",
        aliases: &[],
        opcode: 0x5e31b800,
        mask: 0xff3ffc00,
        class: InsnClass::ASISDPAIR,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDPAIR(ASISDPAIR::ADDP_Sd_Vn(ADDP_Sd_Vn::from(bits)))
    }
}
impl InsnOpcode for ADDP_Sd_Vn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ADDPL_Rd_SP_SVE_Rn_SP_SVE_SIMM6 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "addpl",
        aliases: &[],
        opcode: 0x4605000,
        mask: 0xffe0f800,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd_SP,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Rn_SP,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Rn,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_SIMM6,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_imms,
                    lsb: 5,
                    width: 6,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::ADDPL_Rd_SP_SVE_Rn_SP_SVE_SIMM6(
            ADDPL_Rd_SP_SVE_Rn_SP_SVE_SIMM6::from(bits),
        ))
    }
}
impl InsnOpcode for ADDPL_Rd_SP_SVE_Rn_SP_SVE_SIMM6 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ADDQV_Vd_SVE_Pg3_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "addqv",
        aliases: &[],
        opcode: 0x4052000,
        mask: 0xff3fe000,
        class: InsnClass::SVE2_URQVS,
        feature_set: InsnFeatureSet::SVE2P1,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_16B, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE2_URQVS(SVE2_URQVS::ADDQV_Vd_SVE_Pg3_SVE_Zn(
            ADDQV_Vd_SVE_Pg3_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for ADDQV_Vd_SVE_Pg3_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ADDS_Rd_Rn_SP_AIMM {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "adds",
        aliases: &[],
        opcode: 0x31000000,
        mask: 0x7f800000,
        class: InsnClass::ADDSUB_IMM,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn_SP,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::AIMM,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::shift,
                        lsb: 22,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm12,
                        lsb: 10,
                        width: 12,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_ALIAS.bits() | InsnFlags::HAS_SF_FIELD.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ADDSUB_IMM(ADDSUB_IMM::ADDS_Rd_Rn_SP_AIMM(ADDS_Rd_Rn_SP_AIMM::from(
            bits,
        )))
    }
}
impl InsnOpcode for ADDS_Rd_Rn_SP_AIMM {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ADDS_Rd_Rn_Rm_SFT {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "adds",
        aliases: &[],
        opcode: 0x2b000000,
        mask: 0x7f200000,
        class: InsnClass::ADDSUB_SHIFT,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rm_SFT,
                class: InsnOperandClass::MODIFIED_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_ALIAS.bits() | InsnFlags::HAS_SF_FIELD.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ADDSUB_SHIFT(ADDSUB_SHIFT::ADDS_Rd_Rn_Rm_SFT(ADDS_Rd_Rn_Rm_SFT::from(
            bits,
        )))
    }
}
impl InsnOpcode for ADDS_Rd_Rn_Rm_SFT {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ADDS_Rd_Rn_SP_Rm_EXT {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "adds",
        aliases: &[],
        opcode: 0x2b200000,
        mask: 0x7fe00000,
        class: InsnClass::ADDSUB_EXT,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn_SP,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rm_EXT,
                class: InsnOperandClass::MODIFIED_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::W],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_ALIAS.bits() | InsnFlags::HAS_SF_FIELD.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ADDSUB_EXT(ADDSUB_EXT::ADDS_Rd_Rn_SP_Rm_EXT(
            ADDS_Rd_Rn_SP_Rm_EXT::from(bits),
        ))
    }
}
impl InsnOpcode for ADDS_Rd_Rn_SP_Rm_EXT {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ADDSPL_Rd_SP_SVE_Rn_SP_SVE_SIMM6 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "addspl",
        aliases: &[],
        opcode: 0x4605800,
        mask: 0xffe0f800,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd_SP,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Rn_SP,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Rn,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_SIMM6,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_imms,
                    lsb: 5,
                    width: 6,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::ADDSPL_Rd_SP_SVE_Rn_SP_SVE_SIMM6(
            ADDSPL_Rd_SP_SVE_Rn_SP_SVE_SIMM6::from(bits),
        ))
    }
}
impl InsnOpcode for ADDSPL_Rd_SP_SVE_Rn_SP_SVE_SIMM6 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ADDSVL_Rd_SP_SVE_Rn_SP_SVE_SIMM6 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "addsvl",
        aliases: &[],
        opcode: 0x4205800,
        mask: 0xffe0f800,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd_SP,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Rn_SP,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Rn,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_SIMM6,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_imms,
                    lsb: 5,
                    width: 6,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::ADDSVL_Rd_SP_SVE_Rn_SP_SVE_SIMM6(
            ADDSVL_Rd_SP_SVE_Rn_SP_SVE_SIMM6::from(bits),
        ))
    }
}
impl InsnOpcode for ADDSVL_Rd_SP_SVE_Rn_SP_SVE_SIMM6 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ADDV_Fd_Vn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "addv",
        aliases: &[],
        opcode: 0xe31b800,
        mask: 0xbf3ffc00,
        class: InsnClass::ASIMDALL,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Fd,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDALL(ASIMDALL::ADDV_Fd_Vn(ADDV_Fd_Vn::from(bits)))
    }
}
impl InsnOpcode for ADDV_Fd_Vn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ADDVA_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "addva",
        aliases: &[],
        opcode: 0xc0910000,
        mask: 0xffff001c,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZAda_2b,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_ZAda_2b,
                    lsb: 0,
                    width: 2,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Pm,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Pm,
                    lsb: 13,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::ADDVA_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn(
            ADDVA_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for ADDVA_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ADDVA_SME_ZAda_3b_SVE_Pg3_SME_Pm_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "addva",
        aliases: &[],
        opcode: 0xc0d10000,
        mask: 0xffff0018,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME_I16I64,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZAda_3b,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_ZAda_3b,
                    lsb: 0,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Pm,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Pm,
                    lsb: 13,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::ADDVA_SME_ZAda_3b_SVE_Pg3_SME_Pm_SVE_Zn(
            ADDVA_SME_ZAda_3b_SVE_Pg3_SME_Pm_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for ADDVA_SME_ZAda_3b_SVE_Pg3_SME_Pm_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ADDVL_Rd_SP_SVE_Rn_SP_SVE_SIMM6 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "addvl",
        aliases: &[],
        opcode: 0x4205000,
        mask: 0xffe0f800,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd_SP,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Rn_SP,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Rn,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_SIMM6,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_imms,
                    lsb: 5,
                    width: 6,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::ADDVL_Rd_SP_SVE_Rn_SP_SVE_SIMM6(
            ADDVL_Rd_SP_SVE_Rn_SP_SVE_SIMM6::from(bits),
        ))
    }
}
impl InsnOpcode for ADDVL_Rd_SP_SVE_Rn_SP_SVE_SIMM6 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ADR_Rd_ADDR_PCREL21 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "adr",
        aliases: &[],
        opcode: 0x10000000,
        mask: 0x9f000000,
        class: InsnClass::PCRELADDR,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_PCREL21,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::immhi,
                        lsb: 5,
                        width: 19,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::immlo,
                        lsb: 29,
                        width: 2,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::PCRELADDR(PCRELADDR::ADR_Rd_ADDR_PCREL21(ADR_Rd_ADDR_PCREL21::from(
            bits,
        )))
    }
}
impl InsnOpcode for ADR_Rd_ADDR_PCREL21 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ADR_SVE_Zd_SVE_ADDR_ZZ_SXTW {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "adr",
        aliases: &[],
        opcode: 0x420a000,
        mask: 0xffe0f000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_ZZ_SXTW,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zm_16,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::ADR_SVE_Zd_SVE_ADDR_ZZ_SXTW(
            ADR_SVE_Zd_SVE_ADDR_ZZ_SXTW::from(bits),
        ))
    }
}
impl InsnOpcode for ADR_SVE_Zd_SVE_ADDR_ZZ_SXTW {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ADR_SVE_Zd_SVE_ADDR_ZZ_UXTW {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "adr",
        aliases: &[],
        opcode: 0x460a000,
        mask: 0xffe0f000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_ZZ_UXTW,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zm_16,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::ADR_SVE_Zd_SVE_ADDR_ZZ_UXTW(
            ADR_SVE_Zd_SVE_ADDR_ZZ_UXTW::from(bits),
        ))
    }
}
impl InsnOpcode for ADR_SVE_Zd_SVE_ADDR_ZZ_UXTW {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ADR_SVE_Zd_SVE_ADDR_ZZ_LSL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "adr",
        aliases: &[],
        opcode: 0x4a0a000,
        mask: 0xffa0f000,
        class: InsnClass::SVE_SIZE_SD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_ZZ_LSL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zm_16,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_SD(SVE_SIZE_SD::ADR_SVE_Zd_SVE_ADDR_ZZ_LSL(
            ADR_SVE_Zd_SVE_ADDR_ZZ_LSL::from(bits),
        ))
    }
}
impl InsnOpcode for ADR_SVE_Zd_SVE_ADDR_ZZ_LSL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ADRP_Rd_ADDR_ADRP {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "adrp",
        aliases: &[],
        opcode: 0x90000000,
        mask: 0x9f000000,
        class: InsnClass::PCRELADDR,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_ADRP,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::immhi,
                        lsb: 5,
                        width: 19,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::immlo,
                        lsb: 29,
                        width: 2,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::PCRELADDR(PCRELADDR::ADRP_Rd_ADDR_ADRP(ADRP_Rd_ADDR_ADRP::from(bits)))
    }
}
impl InsnOpcode for ADRP_Rd_ADDR_ADRP {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl AESD_SVE_Zd_SVE_Zd_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "aesd",
        aliases: &[],
        opcode: 0x4522e400,
        mask: 0xfffffc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE2AES,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::AESD_SVE_Zd_SVE_Zd_SVE_Zn(
            AESD_SVE_Zd_SVE_Zd_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for AESD_SVE_Zd_SVE_Zd_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl AESD_Vd_Vn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "aesd",
        aliases: &[],
        opcode: 0x4e285800,
        mask: 0xfffffc00,
        class: InsnClass::CRYPTOAES,
        feature_set: InsnFeatureSet::AES,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::CRYPTOAES(CRYPTOAES::AESD_Vd_Vn(AESD_Vd_Vn::from(bits)))
    }
}
impl InsnOpcode for AESD_Vd_Vn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl AESE_SVE_Zd_SVE_Zd_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "aese",
        aliases: &[],
        opcode: 0x4522e000,
        mask: 0xfffffc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE2AES,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::AESE_SVE_Zd_SVE_Zd_SVE_Zn(
            AESE_SVE_Zd_SVE_Zd_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for AESE_SVE_Zd_SVE_Zd_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl AESE_Vd_Vn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "aese",
        aliases: &[],
        opcode: 0x4e284800,
        mask: 0xfffffc00,
        class: InsnClass::CRYPTOAES,
        feature_set: InsnFeatureSet::AES,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::CRYPTOAES(CRYPTOAES::AESE_Vd_Vn(AESE_Vd_Vn::from(bits)))
    }
}
impl InsnOpcode for AESE_Vd_Vn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl AESIMC_SVE_Zd_SVE_Zd {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "aesimc",
        aliases: &[],
        opcode: 0x4520e400,
        mask: 0xffffffe0,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE2AES,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::AESIMC_SVE_Zd_SVE_Zd(AESIMC_SVE_Zd_SVE_Zd::from(
            bits,
        )))
    }
}
impl InsnOpcode for AESIMC_SVE_Zd_SVE_Zd {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl AESIMC_Vd_Vn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "aesimc",
        aliases: &[],
        opcode: 0x4e287800,
        mask: 0xfffffc00,
        class: InsnClass::CRYPTOAES,
        feature_set: InsnFeatureSet::AES,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::CRYPTOAES(CRYPTOAES::AESIMC_Vd_Vn(AESIMC_Vd_Vn::from(bits)))
    }
}
impl InsnOpcode for AESIMC_Vd_Vn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl AESMC_SVE_Zd_SVE_Zd {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "aesmc",
        aliases: &[],
        opcode: 0x4520e000,
        mask: 0xffffffe0,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE2AES,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::AESMC_SVE_Zd_SVE_Zd(AESMC_SVE_Zd_SVE_Zd::from(
            bits,
        )))
    }
}
impl InsnOpcode for AESMC_SVE_Zd_SVE_Zd {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl AESMC_Vd_Vn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "aesmc",
        aliases: &[],
        opcode: 0x4e286800,
        mask: 0xfffffc00,
        class: InsnClass::CRYPTOAES,
        feature_set: InsnFeatureSet::AES,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::CRYPTOAES(CRYPTOAES::AESMC_Vd_Vn(AESMC_Vd_Vn::from(bits)))
    }
}
impl InsnOpcode for AESMC_Vd_Vn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl AND_Rd_SP_Rn_LIMM {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "and",
        aliases: &[],
        opcode: 0x12000000,
        mask: 0x7f800000,
        class: InsnClass::LOG_IMM,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd_SP,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::LIMM,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::N,
                        lsb: 22,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::immr,
                        lsb: 16,
                        width: 6,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imms,
                        lsb: 10,
                        width: 6,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_ALIAS.bits() | InsnFlags::HAS_SF_FIELD.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LOG_IMM(LOG_IMM::AND_Rd_SP_Rn_LIMM(AND_Rd_SP_Rn_LIMM::from(bits)))
    }
}
impl InsnOpcode for AND_Rd_SP_Rn_LIMM {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl AND_Rd_Rn_Rm_SFT {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "and",
        aliases: &[],
        opcode: 0xa000000,
        mask: 0x7f200000,
        class: InsnClass::LOG_SHIFT,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rm_SFT,
                class: InsnOperandClass::MODIFIED_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SF_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LOG_SHIFT(LOG_SHIFT::AND_Rd_Rn_Rm_SFT(AND_Rd_Rn_Rm_SFT::from(bits)))
    }
}
impl InsnOpcode for AND_Rd_Rn_Rm_SFT {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl AND_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "and",
        aliases: &[],
        opcode: 0x41a0000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_5,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_5,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::AND_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(
            AND_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5::from(bits),
        ))
    }
}
impl InsnOpcode for AND_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl AND_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "and",
        aliases: &[],
        opcode: 0x4203000,
        mask: 0xffe0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::AND_SVE_Zd_SVE_Zn_SVE_Zm_16(
            AND_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for AND_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl AND_SVE_Zd_SVE_Zd_SVE_LIMM {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "and",
        aliases: &[],
        opcode: 0x5800000,
        mask: 0xfffc0000,
        class: InsnClass::SVE_LIMM,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_LIMM,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_N,
                        lsb: 17,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_immr,
                        lsb: 11,
                        width: 6,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_imms,
                        lsb: 5,
                        width: 6,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ALIAS.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_LIMM(SVE_LIMM::AND_SVE_Zd_SVE_Zd_SVE_LIMM(
            AND_SVE_Zd_SVE_Zd_SVE_LIMM::from(bits),
        ))
    }
}
impl InsnOpcode for AND_SVE_Zd_SVE_Zd_SVE_LIMM {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl AND_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "and",
        aliases: &[],
        opcode: 0x25004000,
        mask: 0xfff0c210,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Pd,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pd,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg4_10,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg4_10,
                    lsb: 10,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pn,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pn,
                    lsb: 5,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pm,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pm,
                    lsb: 16,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ALIAS.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::AND_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm(
            AND_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm::from(bits),
        ))
    }
}
impl InsnOpcode for AND_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl AND_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "and",
        aliases: &[],
        opcode: 0xe201c00,
        mask: 0xbfe0fc00,
        class: InsnClass::ASIMDSAME,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSAME(ASIMDSAME::AND_Vd_Vn_Vm(AND_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for AND_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ANDQV_Vd_SVE_Pg3_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "andqv",
        aliases: &[],
        opcode: 0x41e2000,
        mask: 0xff3fe000,
        class: InsnClass::SVE2_URQVS,
        feature_set: InsnFeatureSet::SVE2P1,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_16B, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE2_URQVS(SVE2_URQVS::ANDQV_Vd_SVE_Pg3_SVE_Zn(
            ANDQV_Vd_SVE_Pg3_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for ANDQV_Vd_SVE_Pg3_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ANDS_Rd_Rn_LIMM {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ands",
        aliases: &[],
        opcode: 0x72000000,
        mask: 0x7f800000,
        class: InsnClass::LOG_IMM,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::LIMM,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::N,
                        lsb: 22,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::immr,
                        lsb: 16,
                        width: 6,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imms,
                        lsb: 10,
                        width: 6,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_ALIAS.bits() | InsnFlags::HAS_SF_FIELD.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LOG_IMM(LOG_IMM::ANDS_Rd_Rn_LIMM(ANDS_Rd_Rn_LIMM::from(bits)))
    }
}
impl InsnOpcode for ANDS_Rd_Rn_LIMM {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ANDS_Rd_Rn_Rm_SFT {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ands",
        aliases: &[],
        opcode: 0x6a000000,
        mask: 0x7f200000,
        class: InsnClass::LOG_SHIFT,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rm_SFT,
                class: InsnOperandClass::MODIFIED_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_ALIAS.bits() | InsnFlags::HAS_SF_FIELD.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LOG_SHIFT(LOG_SHIFT::ANDS_Rd_Rn_Rm_SFT(ANDS_Rd_Rn_Rm_SFT::from(bits)))
    }
}
impl InsnOpcode for ANDS_Rd_Rn_Rm_SFT {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ANDS_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ands",
        aliases: &[],
        opcode: 0x25404000,
        mask: 0xfff0c210,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Pd,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pd,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg4_10,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg4_10,
                    lsb: 10,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pn,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pn,
                    lsb: 5,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pm,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pm,
                    lsb: 16,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ALIAS.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::ANDS_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm(
            ANDS_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm::from(bits),
        ))
    }
}
impl InsnOpcode for ANDS_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ANDV_SVE_Vd_SVE_Pg3_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "andv",
        aliases: &[],
        opcode: 0x41a2000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Vd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::ANDV_SVE_Vd_SVE_Pg3_SVE_Zn(
            ANDV_SVE_Vd_SVE_Pg3_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for ANDV_SVE_Vd_SVE_Pg3_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ASR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_SHRIMM_PRED {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "asr",
        aliases: &[],
        opcode: 0x4008000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SHIFT_PRED,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_SHRIMM_PRED,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_tszh,
                        lsb: 22,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_imm5,
                        lsb: 5,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SHIFT_PRED(SVE_SHIFT_PRED::ASR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_SHRIMM_PRED(
            ASR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_SHRIMM_PRED::from(bits),
        ))
    }
}
impl InsnOpcode for ASR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_SHRIMM_PRED {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ASR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "asr",
        aliases: &[],
        opcode: 0x4108000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_5,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_5,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::ASR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(
            ASR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5::from(bits),
        ))
    }
}
impl InsnOpcode for ASR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ASR_SVE_Zd_S_B_SVE_Pg3_P_M_SVE_Zd_S_B_SVE_Zm_5_S_D {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "asr",
        aliases: &[],
        opcode: 0x4188000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_BHS,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_5,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_D,
                    InsnOperandQualifier::S_D,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_5,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHS(
            SVE_SIZE_BHS::ASR_SVE_Zd_S_B_SVE_Pg3_P_M_SVE_Zd_S_B_SVE_Zm_5_S_D(
                ASR_SVE_Zd_S_B_SVE_Pg3_P_M_SVE_Zd_S_B_SVE_Zm_5_S_D::from(bits),
            ),
        )
    }
}
impl InsnOpcode for ASR_SVE_Zd_S_B_SVE_Pg3_P_M_SVE_Zd_S_B_SVE_Zm_5_S_D {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ASR_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "asr",
        aliases: &[],
        opcode: 0x4208000,
        mask: 0xff20fc00,
        class: InsnClass::SVE_SIZE_BHS,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHS(SVE_SIZE_BHS::ASR_SVE_Zd_SVE_Zn_SVE_Zm_16(
            ASR_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for ASR_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ASR_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "asr",
        aliases: &[],
        opcode: 0x4209000,
        mask: 0xff20fc00,
        class: InsnClass::SVE_SHIFT_UNPRED,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_SHRIMM_UNPRED,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_tszh,
                        lsb: 22,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm5,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SHIFT_UNPRED(SVE_SHIFT_UNPRED::ASR_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED(
            ASR_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED::from(bits),
        ))
    }
}
impl InsnOpcode for ASR_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ASRD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_SHRIMM_PRED {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "asrd",
        aliases: &[],
        opcode: 0x4048000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SHIFT_PRED,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_SHRIMM_PRED,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_tszh,
                        lsb: 22,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_imm5,
                        lsb: 5,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SHIFT_PRED(SVE_SHIFT_PRED::ASRD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_SHRIMM_PRED(
            ASRD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_SHRIMM_PRED::from(bits),
        ))
    }
}
impl InsnOpcode for ASRD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_SHRIMM_PRED {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ASRR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "asrr",
        aliases: &[],
        opcode: 0x4148000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_5,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_5,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::ASRR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(
            ASRR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5::from(bits),
        ))
    }
}
impl InsnOpcode for ASRR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ASRV_Rd_Rn_Rm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "asrv",
        aliases: &[],
        opcode: 0x1ac02800,
        mask: 0x7fe0fc00,
        class: InsnClass::DP_2SRC,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rm,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_ALIAS.bits() | InsnFlags::HAS_SF_FIELD.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::DP_2SRC(DP_2SRC::ASRV_Rd_Rn_Rm(ASRV_Rd_Rn_Rm::from(bits)))
    }
}
impl InsnOpcode for ASRV_Rd_Rn_Rm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl AUTDA_Rd_Rn_SP {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "autda",
        aliases: &[],
        opcode: 0xdac11800,
        mask: 0xfffffc00,
        class: InsnClass::DP_1SRC,
        feature_set: InsnFeatureSet::PAC,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn_SP,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::DP_1SRC(DP_1SRC::AUTDA_Rd_Rn_SP(AUTDA_Rd_Rn_SP::from(bits)))
    }
}
impl InsnOpcode for AUTDA_Rd_Rn_SP {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl AUTDB_Rd_Rn_SP {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "autdb",
        aliases: &[],
        opcode: 0xdac11c00,
        mask: 0xfffffc00,
        class: InsnClass::DP_1SRC,
        feature_set: InsnFeatureSet::PAC,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn_SP,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::DP_1SRC(DP_1SRC::AUTDB_Rd_Rn_SP(AUTDB_Rd_Rn_SP::from(bits)))
    }
}
impl InsnOpcode for AUTDB_Rd_Rn_SP {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl AUTDZA_Rd {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "autdza",
        aliases: &[],
        opcode: 0xdac13be0,
        mask: 0xffffffe0,
        class: InsnClass::DP_1SRC,
        feature_set: InsnFeatureSet::PAC,
        operands: &[InsnOperand {
            kind: InsnOperandKind::Rd,
            class: InsnOperandClass::INT_REG,
            qualifiers: &[],
            bit_fields: &[BitfieldSpec {
                bitfield: InsnBitField::Rd,
                lsb: 0,
                width: 5,
            }],
        }],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::DP_1SRC(DP_1SRC::AUTDZA_Rd(AUTDZA_Rd::from(bits)))
    }
}
impl InsnOpcode for AUTDZA_Rd {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl AUTDZB_Rd {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "autdzb",
        aliases: &[],
        opcode: 0xdac13fe0,
        mask: 0xffffffe0,
        class: InsnClass::DP_1SRC,
        feature_set: InsnFeatureSet::PAC,
        operands: &[InsnOperand {
            kind: InsnOperandKind::Rd,
            class: InsnOperandClass::INT_REG,
            qualifiers: &[],
            bit_fields: &[BitfieldSpec {
                bitfield: InsnBitField::Rd,
                lsb: 0,
                width: 5,
            }],
        }],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::DP_1SRC(DP_1SRC::AUTDZB_Rd(AUTDZB_Rd::from(bits)))
    }
}
impl InsnOpcode for AUTDZB_Rd {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl AUTIA_Rd_Rn_SP {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "autia",
        aliases: &[],
        opcode: 0xdac11000,
        mask: 0xfffffc00,
        class: InsnClass::DP_1SRC,
        feature_set: InsnFeatureSet::PAC,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn_SP,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::DP_1SRC(DP_1SRC::AUTIA_Rd_Rn_SP(AUTIA_Rd_Rn_SP::from(bits)))
    }
}
impl InsnOpcode for AUTIA_Rd_Rn_SP {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl AUTIB_Rd_Rn_SP {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "autib",
        aliases: &[],
        opcode: 0xdac11400,
        mask: 0xfffffc00,
        class: InsnClass::DP_1SRC,
        feature_set: InsnFeatureSet::PAC,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn_SP,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::DP_1SRC(DP_1SRC::AUTIB_Rd_Rn_SP(AUTIB_Rd_Rn_SP::from(bits)))
    }
}
impl InsnOpcode for AUTIB_Rd_Rn_SP {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl AUTIZA_Rd {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "autiza",
        aliases: &[],
        opcode: 0xdac133e0,
        mask: 0xffffffe0,
        class: InsnClass::DP_1SRC,
        feature_set: InsnFeatureSet::PAC,
        operands: &[InsnOperand {
            kind: InsnOperandKind::Rd,
            class: InsnOperandClass::INT_REG,
            qualifiers: &[],
            bit_fields: &[BitfieldSpec {
                bitfield: InsnBitField::Rd,
                lsb: 0,
                width: 5,
            }],
        }],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::DP_1SRC(DP_1SRC::AUTIZA_Rd(AUTIZA_Rd::from(bits)))
    }
}
impl InsnOpcode for AUTIZA_Rd {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl AUTIZB_Rd {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "autizb",
        aliases: &[],
        opcode: 0xdac137e0,
        mask: 0xffffffe0,
        class: InsnClass::DP_1SRC,
        feature_set: InsnFeatureSet::PAC,
        operands: &[InsnOperand {
            kind: InsnOperandKind::Rd,
            class: InsnOperandClass::INT_REG,
            qualifiers: &[],
            bit_fields: &[BitfieldSpec {
                bitfield: InsnBitField::Rd,
                lsb: 0,
                width: 5,
            }],
        }],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::DP_1SRC(DP_1SRC::AUTIZB_Rd(AUTIZB_Rd::from(bits)))
    }
}
impl InsnOpcode for AUTIZB_Rd {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl AXFLAG {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "axflag",
        aliases: &[],
        opcode: 0xd500405f,
        mask: 0xffffffff,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::FLAGMANIP,
        operands: &[],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(AARCH64_MISC::AXFLAG(AXFLAG::from(bits)))
    }
}
impl InsnOpcode for AXFLAG {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl B_ADDR_PCREL26 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "b",
        aliases: &[],
        opcode: 0x14000000,
        mask: 0xfc000000,
        class: InsnClass::BRANCH_IMM,
        feature_set: InsnFeatureSet::V8,
        operands: &[InsnOperand {
            kind: InsnOperandKind::ADDR_PCREL26,
            class: InsnOperandClass::ADDRESS,
            qualifiers: &[],
            bit_fields: &[BitfieldSpec {
                bitfield: InsnBitField::imm26,
                lsb: 0,
                width: 26,
            }],
        }],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::BRANCH_IMM(BRANCH_IMM::B_ADDR_PCREL26(B_ADDR_PCREL26::from(bits)))
    }
}
impl InsnOpcode for B_ADDR_PCREL26 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl B__ADDR_PCREL19 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "b.",
        aliases: &[],
        opcode: 0x54000000,
        mask: 0xff000010,
        class: InsnClass::CONDBRANCH,
        feature_set: InsnFeatureSet::V8,
        operands: &[InsnOperand {
            kind: InsnOperandKind::ADDR_PCREL19,
            class: InsnOperandClass::ADDRESS,
            qualifiers: &[],
            bit_fields: &[
                BitfieldSpec {
                    bitfield: InsnBitField::imm19,
                    lsb: 5,
                    width: 19,
                },
                BitfieldSpec {
                    bitfield: InsnBitField::cond,
                    lsb: 0,
                    width: 4,
                },
            ],
        }],
        flags: InsnFlags::const_from_bits(InsnFlags::IS_COND.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::CONDBRANCH(CONDBRANCH::B__ADDR_PCREL19(B__ADDR_PCREL19::from(bits)))
    }
}
impl InsnOpcode for B__ADDR_PCREL19 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl BC__ADDR_PCREL19 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "bc.",
        aliases: &[],
        opcode: 0x54000010,
        mask: 0xff000010,
        class: InsnClass::CONDBRANCH,
        feature_set: InsnFeatureSet::HBC,
        operands: &[InsnOperand {
            kind: InsnOperandKind::ADDR_PCREL19,
            class: InsnOperandClass::ADDRESS,
            qualifiers: &[],
            bit_fields: &[
                BitfieldSpec {
                    bitfield: InsnBitField::imm19,
                    lsb: 5,
                    width: 19,
                },
                BitfieldSpec {
                    bitfield: InsnBitField::cond,
                    lsb: 0,
                    width: 4,
                },
            ],
        }],
        flags: InsnFlags::const_from_bits(InsnFlags::IS_COND.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::CONDBRANCH(CONDBRANCH::BC__ADDR_PCREL19(BC__ADDR_PCREL19::from(bits)))
    }
}
impl InsnOpcode for BC__ADDR_PCREL19 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl BCAX_SVE_Zd_SVE_Zd_SVE_Zm_16_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "bcax",
        aliases: &[],
        opcode: 0x4603800,
        mask: 0xffe0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::BCAX_SVE_Zd_SVE_Zd_SVE_Zm_16_SVE_Zn(
            BCAX_SVE_Zd_SVE_Zd_SVE_Zm_16_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for BCAX_SVE_Zd_SVE_Zd_SVE_Zm_16_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl BCAX_Vd_Vn_Vm_Va {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "bcax",
        aliases: &[],
        opcode: 0xce200000,
        mask: 0xffe08000,
        class: InsnClass::CRYPTOSHA3,
        feature_set: InsnFeatureSet::SHA3,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Va,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Ra,
                    lsb: 10,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::CRYPTOSHA3(CRYPTOSHA3::BCAX_Vd_Vn_Vm_Va(BCAX_Vd_Vn_Vm_Va::from(bits)))
    }
}
impl InsnOpcode for BCAX_Vd_Vn_Vm_Va {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl BDEP_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "bdep",
        aliases: &[],
        opcode: 0x4500b400,
        mask: 0xff20fc00,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE2BITPERM,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::BDEP_SVE_Zd_SVE_Zn_SVE_Zm_16(
            BDEP_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for BDEP_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl BEXT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "bext",
        aliases: &[],
        opcode: 0x4500b000,
        mask: 0xff20fc00,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE2BITPERM,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::BEXT_SVE_Zd_SVE_Zn_SVE_Zm_16(
            BEXT_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for BEXT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl BFADD_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "bfadd",
        aliases: &[],
        opcode: 0x65000000,
        mask: 0xffe0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::B16B16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::BFADD_SVE_Zd_SVE_Zn_SVE_Zm_16(
            BFADD_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for BFADD_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl BFADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "bfadd",
        aliases: &[],
        opcode: 0x65008000,
        mask: 0xffffe000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::B16B16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_5,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_5,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::BFADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(
            BFADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5::from(bits),
        ))
    }
}
impl InsnOpcode for BFADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl BFCLAMP_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "bfclamp",
        aliases: &[],
        opcode: 0x64202400,
        mask: 0xffe0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::B16B16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::BFCLAMP_SVE_Zd_SVE_Zn_SVE_Zm_16(
            BFCLAMP_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for BFCLAMP_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl BFCVT_SVE_Zd_SME_Znx2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "bfcvt",
        aliases: &[],
        opcode: 0xc160e000,
        mask: 0xfffffc20,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn2,
                    lsb: 6,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::BFCVT_SVE_Zd_SME_Znx2(
            BFCVT_SVE_Zd_SME_Znx2::from(bits),
        ))
    }
}
impl InsnOpcode for BFCVT_SVE_Zd_SME_Znx2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl BFCVT_SVE_Zd_SVE_Pg3_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "bfcvt",
        aliases: &[],
        opcode: 0x658aa000,
        mask: 0xffffe000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::BFLOAT16_SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::BFCVT_SVE_Zd_SVE_Pg3_SVE_Zn(
            BFCVT_SVE_Zd_SVE_Pg3_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for BFCVT_SVE_Zd_SVE_Pg3_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl BFCVT_Fd_Fn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "bfcvt",
        aliases: &[],
        opcode: 0x1e634000,
        mask: 0xfffffc00,
        class: InsnClass::BFLOAT16,
        feature_set: InsnFeatureSet::BFLOAT16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Fd,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fn,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::BFLOAT16(BFLOAT16::BFCVT_Fd_Fn(BFCVT_Fd_Fn::from(bits)))
    }
}
impl InsnOpcode for BFCVT_Fd_Fn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl BFCVTN_SVE_Zd_SME_Znx2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "bfcvtn",
        aliases: &[],
        opcode: 0xc160e020,
        mask: 0xfffffc20,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn2,
                    lsb: 6,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::BFCVTN_SVE_Zd_SME_Znx2(
            BFCVTN_SVE_Zd_SME_Znx2::from(bits),
        ))
    }
}
impl InsnOpcode for BFCVTN_SVE_Zd_SME_Znx2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl BFCVTN_Vd_Vn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "bfcvtn",
        aliases: &[],
        opcode: 0xea16800,
        mask: 0xfffffc00,
        class: InsnClass::BFLOAT16,
        feature_set: InsnFeatureSet::BFLOAT16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::BFLOAT16(BFLOAT16::BFCVTN_Vd_Vn(BFCVTN_Vd_Vn::from(bits)))
    }
}
impl InsnOpcode for BFCVTN_Vd_Vn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl BFCVTN2_Vd_Vn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "bfcvtn2",
        aliases: &[],
        opcode: 0x4ea16800,
        mask: 0xfffffc00,
        class: InsnClass::BFLOAT16,
        feature_set: InsnFeatureSet::BFLOAT16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::BFLOAT16(BFLOAT16::BFCVTN2_Vd_Vn(BFCVTN2_Vd_Vn::from(bits)))
    }
}
impl InsnOpcode for BFCVTN2_Vd_Vn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl BFCVTNT_SVE_Zd_SVE_Pg3_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "bfcvtnt",
        aliases: &[],
        opcode: 0x648aa000,
        mask: 0xffffe000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::BFLOAT16_SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::BFCVTNT_SVE_Zd_SVE_Pg3_SVE_Zn(
            BFCVTNT_SVE_Zd_SVE_Pg3_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for BFCVTNT_SVE_Zd_SVE_Pg3_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl BFDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "bfdot",
        aliases: &[],
        opcode: 0xc1501018,
        mask: 0xfff09038,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off3_0,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_0,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn2,
                    lsb: 6,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm_INDEX2,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zm,
                        lsb: 16,
                        width: 4,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_10,
                        lsb: 10,
                        width: 2,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::BFDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2(
            BFDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2::from(bits),
        ))
    }
}
impl InsnOpcode for BFDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl BFDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "bfdot",
        aliases: &[],
        opcode: 0xc1509018,
        mask: 0xfff09078,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off3_0,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_0,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn4,
                    lsb: 7,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm_INDEX2,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zm,
                        lsb: 16,
                        width: 4,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_10,
                        lsb: 10,
                        width: 2,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_4.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::BFDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2(
            BFDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2::from(bits),
        ))
    }
}
impl InsnOpcode for BFDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl BFDOT_SME_ZA_array_off3_0_SVE_ZnxN_SME_Zm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "bfdot",
        aliases: &[],
        opcode: 0xc1201010,
        mask: 0xfff09c18,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off3_0,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_0,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ZnxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm,
                    lsb: 16,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::BFDOT_SME_ZA_array_off3_0_SVE_ZnxN_SME_Zm(
            BFDOT_SME_ZA_array_off3_0_SVE_ZnxN_SME_Zm::from(bits),
        ))
    }
}
impl InsnOpcode for BFDOT_SME_ZA_array_off3_0_SVE_ZnxN_SME_Zm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl BFDOT_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_H_SME_Zm_S_H {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "bfdot",
        aliases: &[],
        opcode: 0xc1301010,
        mask: 0xfff09c18,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off3_0,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_0,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ZnxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm,
                    lsb: 16,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_4.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(
            SME_MISC::BFDOT_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_H_SME_Zm_S_H(
                BFDOT_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_H_SME_Zm_S_H::from(bits),
            ),
        )
    }
}
impl InsnOpcode for BFDOT_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_H_SME_Zm_S_H {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl BFDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zmx2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "bfdot",
        aliases: &[],
        opcode: 0xc1a01010,
        mask: 0xffe19c38,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off3_0,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_0,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn2,
                    lsb: 6,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zmx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm2,
                    lsb: 17,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::BFDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zmx2(
            BFDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zmx2::from(bits),
        ))
    }
}
impl InsnOpcode for BFDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zmx2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl BFDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zmx4 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "bfdot",
        aliases: &[],
        opcode: 0xc1a11010,
        mask: 0xffe39c78,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off3_0,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_0,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn4,
                    lsb: 7,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zmx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm4,
                    lsb: 18,
                    width: 3,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_4.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::BFDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zmx4(
            BFDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zmx4::from(bits),
        ))
    }
}
impl InsnOpcode for BFDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zmx4 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl BFDOT_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "bfdot",
        aliases: &[],
        opcode: 0x64604000,
        mask: 0xffe0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::BFLOAT16_SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm3_INDEX,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::BFDOT_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX(
            BFDOT_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX::from(bits),
        ))
    }
}
impl InsnOpcode for BFDOT_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl BFDOT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "bfdot",
        aliases: &[],
        opcode: 0x64608000,
        mask: 0xffe0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::BFLOAT16_SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::BFDOT_SVE_Zd_SVE_Zn_SVE_Zm_16(
            BFDOT_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for BFDOT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl BFDOT_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "bfdot",
        aliases: &[],
        opcode: 0x2e40fc00,
        mask: 0xbfe0fc00,
        class: InsnClass::BFLOAT16,
        feature_set: InsnFeatureSet::BFLOAT16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::BFLOAT16(BFLOAT16::BFDOT_Vd_Vn_Vm(BFDOT_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for BFDOT_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl BFDOT_Vd_Vn_Em {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "bfdot",
        aliases: &[],
        opcode: 0xf40f000,
        mask: 0xbfc0f400,
        class: InsnClass::DOTPRODUCT,
        feature_set: InsnFeatureSet::BFLOAT16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Em,
                class: InsnOperandClass::SIMD_ELEMENT,
                qualifiers: &[InsnOperandQualifier::S_2H, InsnOperandQualifier::S_2H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::DOTPRODUCT(DOTPRODUCT::BFDOT_Vd_Vn_Em(BFDOT_Vd_Vn_Em::from(bits)))
    }
}
impl InsnOpcode for BFDOT_Vd_Vn_Em {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl BFM_Rd_Rn_IMMR_IMMS {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "bfm",
        aliases: &[],
        opcode: 0x33000000,
        mask: 0x7f800000,
        class: InsnClass::BITFIELD,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::IMMR,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[
                    InsnOperandQualifier::imm_0_31,
                    InsnOperandQualifier::imm_0_63,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::immr,
                    lsb: 16,
                    width: 6,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::IMMS,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[
                    InsnOperandQualifier::imm_0_31,
                    InsnOperandQualifier::imm_0_63,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::imm6_10,
                    lsb: 10,
                    width: 6,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_ALIAS.bits()
                | InsnFlags::HAS_N_FIELD.bits()
                | InsnFlags::HAS_SF_FIELD.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::BITFIELD(BITFIELD::BFM_Rd_Rn_IMMR_IMMS(BFM_Rd_Rn_IMMR_IMMS::from(
            bits,
        )))
    }
}
impl InsnOpcode for BFM_Rd_Rn_IMMR_IMMS {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl BFMAX_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "bfmax",
        aliases: &[],
        opcode: 0x65068000,
        mask: 0xffffe000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::B16B16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_5,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_5,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::BFMAX_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(
            BFMAX_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5::from(bits),
        ))
    }
}
impl InsnOpcode for BFMAX_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl BFMAXNM_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "bfmaxnm",
        aliases: &[],
        opcode: 0x65048000,
        mask: 0xffffe000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::B16B16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_5,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_5,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::BFMAXNM_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(
            BFMAXNM_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5::from(bits),
        ))
    }
}
impl InsnOpcode for BFMAXNM_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl BFMIN_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "bfmin",
        aliases: &[],
        opcode: 0x65078000,
        mask: 0xffffe000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::B16B16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_5,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_5,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::BFMIN_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(
            BFMIN_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5::from(bits),
        ))
    }
}
impl InsnOpcode for BFMIN_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl BFMINNM_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "bfminnm",
        aliases: &[],
        opcode: 0x65058000,
        mask: 0xffffe000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::B16B16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_5,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_5,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::BFMINNM_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(
            BFMINNM_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5::from(bits),
        ))
    }
}
impl InsnOpcode for BFMINNM_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl BFMLA_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "bfmla",
        aliases: &[],
        opcode: 0x64200800,
        mask: 0xffa0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::B16B16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm3_11_INDEX,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_i3h2,
                        lsb: 19,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_i3l,
                        lsb: 11,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_imm3,
                        lsb: 16,
                        width: 3,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::BFMLA_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX(
            BFMLA_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX::from(bits),
        ))
    }
}
impl InsnOpcode for BFMLA_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl BFMLA_SVE_Zd_SVE_Pg3_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "bfmla",
        aliases: &[],
        opcode: 0x65200000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::B16B16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::BFMLA_SVE_Zd_SVE_Pg3_SVE_Zn_SVE_Zm_16(
            BFMLA_SVE_Zd_SVE_Pg3_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for BFMLA_SVE_Zd_SVE_Pg3_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl BFMLAL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm_INDEX3_10 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "bfmlal",
        aliases: &[],
        opcode: 0xc1801010,
        mask: 0xfff01018,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off3x2,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_0,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm_INDEX3_10,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zm,
                        lsb: 16,
                        width: 4,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm1_15,
                        lsb: 15,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_10,
                        lsb: 10,
                        width: 2,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(
            SME_MISC::BFMLAL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm_INDEX3_10(
                BFMLAL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm_INDEX3_10::from(bits),
            ),
        )
    }
}
impl InsnOpcode for BFMLAL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm_INDEX3_10 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl BFMLAL_SME_ZA_array_off2x2_SME_Znx2_SME_Zm_INDEX3_2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "bfmlal",
        aliases: &[],
        opcode: 0xc1901010,
        mask: 0xfff09038,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off2x2,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_0,
                        lsb: 0,
                        width: 2,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn2,
                    lsb: 6,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm_INDEX3_2,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zm,
                        lsb: 16,
                        width: 4,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_10,
                        lsb: 10,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm1_2,
                        lsb: 2,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(
            SME_MISC::BFMLAL_SME_ZA_array_off2x2_SME_Znx2_SME_Zm_INDEX3_2(
                BFMLAL_SME_ZA_array_off2x2_SME_Znx2_SME_Zm_INDEX3_2::from(bits),
            ),
        )
    }
}
impl InsnOpcode for BFMLAL_SME_ZA_array_off2x2_SME_Znx2_SME_Zm_INDEX3_2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl BFMLAL_SME_ZA_array_off2x2_SME_Znx4_SME_Zm_INDEX3_2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "bfmlal",
        aliases: &[],
        opcode: 0xc1909010,
        mask: 0xfff09078,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off2x2,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_0,
                        lsb: 0,
                        width: 2,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn4,
                    lsb: 7,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm_INDEX3_2,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zm,
                        lsb: 16,
                        width: 4,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_10,
                        lsb: 10,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm1_2,
                        lsb: 2,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_4.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(
            SME_MISC::BFMLAL_SME_ZA_array_off2x2_SME_Znx4_SME_Zm_INDEX3_2(
                BFMLAL_SME_ZA_array_off2x2_SME_Znx4_SME_Zm_INDEX3_2::from(bits),
            ),
        )
    }
}
impl InsnOpcode for BFMLAL_SME_ZA_array_off2x2_SME_Znx4_SME_Zm_INDEX3_2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl BFMLAL_SME_ZA_array_off2x2_SVE_ZnxN_SME_Zm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "bfmlal",
        aliases: &[],
        opcode: 0xc1200810,
        mask: 0xfff09c1c,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off2x2,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_0,
                        lsb: 0,
                        width: 2,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ZnxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm,
                    lsb: 16,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::BFMLAL_SME_ZA_array_off2x2_SVE_ZnxN_SME_Zm(
            BFMLAL_SME_ZA_array_off2x2_SVE_ZnxN_SME_Zm::from(bits),
        ))
    }
}
impl InsnOpcode for BFMLAL_SME_ZA_array_off2x2_SVE_ZnxN_SME_Zm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl BFMLAL_SME_ZA_array_off2x2_S_S_SVE_ZnxN_S_H_SME_Zm_S_H {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "bfmlal",
        aliases: &[],
        opcode: 0xc1300810,
        mask: 0xfff09c1c,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off2x2,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_0,
                        lsb: 0,
                        width: 2,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ZnxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm,
                    lsb: 16,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_4.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(
            SME_MISC::BFMLAL_SME_ZA_array_off2x2_S_S_SVE_ZnxN_S_H_SME_Zm_S_H(
                BFMLAL_SME_ZA_array_off2x2_S_S_SVE_ZnxN_S_H_SME_Zm_S_H::from(bits),
            ),
        )
    }
}
impl InsnOpcode for BFMLAL_SME_ZA_array_off2x2_S_S_SVE_ZnxN_S_H_SME_Zm_S_H {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl BFMLAL_SME_ZA_array_off2x2_SME_Znx2_SME_Zmx2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "bfmlal",
        aliases: &[],
        opcode: 0xc1a00810,
        mask: 0xffe19c3c,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off2x2,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_0,
                        lsb: 0,
                        width: 2,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn2,
                    lsb: 6,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zmx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm2,
                    lsb: 17,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::BFMLAL_SME_ZA_array_off2x2_SME_Znx2_SME_Zmx2(
            BFMLAL_SME_ZA_array_off2x2_SME_Znx2_SME_Zmx2::from(bits),
        ))
    }
}
impl InsnOpcode for BFMLAL_SME_ZA_array_off2x2_SME_Znx2_SME_Zmx2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl BFMLAL_SME_ZA_array_off2x2_SME_Znx4_SME_Zmx4 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "bfmlal",
        aliases: &[],
        opcode: 0xc1a10810,
        mask: 0xffe39c7c,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off2x2,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_0,
                        lsb: 0,
                        width: 2,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn4,
                    lsb: 7,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zmx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm4,
                    lsb: 18,
                    width: 3,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_4.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::BFMLAL_SME_ZA_array_off2x2_SME_Znx4_SME_Zmx4(
            BFMLAL_SME_ZA_array_off2x2_SME_Znx4_SME_Zmx4::from(bits),
        ))
    }
}
impl InsnOpcode for BFMLAL_SME_ZA_array_off2x2_SME_Znx4_SME_Zmx4 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl BFMLAL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "bfmlal",
        aliases: &[],
        opcode: 0xc1200c10,
        mask: 0xfff09c18,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off3x2,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_0,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm,
                    lsb: 16,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::BFMLAL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm(
            BFMLAL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm::from(bits),
        ))
    }
}
impl InsnOpcode for BFMLAL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl BFMLALB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "bfmlalb",
        aliases: &[],
        opcode: 0x64e04000,
        mask: 0xffe0f400,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::BFLOAT16_SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm3_11_INDEX,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_i3h2,
                        lsb: 19,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_i3l,
                        lsb: 11,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_imm3,
                        lsb: 16,
                        width: 3,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::BFMLALB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX(
            BFMLALB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX::from(bits),
        ))
    }
}
impl InsnOpcode for BFMLALB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl BFMLALB_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "bfmlalb",
        aliases: &[],
        opcode: 0x64e08000,
        mask: 0xffe0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::BFLOAT16_SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::BFMLALB_SVE_Zd_SVE_Zn_SVE_Zm_16(
            BFMLALB_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for BFMLALB_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl BFMLALB_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "bfmlalb",
        aliases: &[],
        opcode: 0x2ec0fc00,
        mask: 0xffe0fc00,
        class: InsnClass::BFLOAT16,
        feature_set: InsnFeatureSet::BFLOAT16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::BFLOAT16(BFLOAT16::BFMLALB_Vd_Vn_Vm(BFMLALB_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for BFMLALB_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl BFMLALB_Vd_Vn_Em16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "bfmlalb",
        aliases: &[],
        opcode: 0xfc0f000,
        mask: 0xffc0f400,
        class: InsnClass::BFLOAT16,
        feature_set: InsnFeatureSet::BFLOAT16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Em16,
                class: InsnOperandClass::SIMD_ELEMENT,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::BFLOAT16(BFLOAT16::BFMLALB_Vd_Vn_Em16(BFMLALB_Vd_Vn_Em16::from(bits)))
    }
}
impl InsnOpcode for BFMLALB_Vd_Vn_Em16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl BFMLALT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "bfmlalt",
        aliases: &[],
        opcode: 0x64e04400,
        mask: 0xffe0f400,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::BFLOAT16_SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm3_11_INDEX,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_i3h2,
                        lsb: 19,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_i3l,
                        lsb: 11,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_imm3,
                        lsb: 16,
                        width: 3,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::BFMLALT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX(
            BFMLALT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX::from(bits),
        ))
    }
}
impl InsnOpcode for BFMLALT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl BFMLALT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "bfmlalt",
        aliases: &[],
        opcode: 0x64e08400,
        mask: 0xffe0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::BFLOAT16_SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::BFMLALT_SVE_Zd_SVE_Zn_SVE_Zm_16(
            BFMLALT_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for BFMLALT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl BFMLALT_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "bfmlalt",
        aliases: &[],
        opcode: 0x6ec0fc00,
        mask: 0xffe0fc00,
        class: InsnClass::BFLOAT16,
        feature_set: InsnFeatureSet::BFLOAT16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::BFLOAT16(BFLOAT16::BFMLALT_Vd_Vn_Vm(BFMLALT_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for BFMLALT_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl BFMLALT_Vd_Vn_Em16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "bfmlalt",
        aliases: &[],
        opcode: 0x4fc0f000,
        mask: 0xffc0f400,
        class: InsnClass::BFLOAT16,
        feature_set: InsnFeatureSet::BFLOAT16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Em16,
                class: InsnOperandClass::SIMD_ELEMENT,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::BFLOAT16(BFLOAT16::BFMLALT_Vd_Vn_Em16(BFMLALT_Vd_Vn_Em16::from(bits)))
    }
}
impl InsnOpcode for BFMLALT_Vd_Vn_Em16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl BFMLS_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "bfmls",
        aliases: &[],
        opcode: 0x64200c00,
        mask: 0xffa0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::B16B16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm3_11_INDEX,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_i3h2,
                        lsb: 19,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_i3l,
                        lsb: 11,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_imm3,
                        lsb: 16,
                        width: 3,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::BFMLS_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX(
            BFMLS_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX::from(bits),
        ))
    }
}
impl InsnOpcode for BFMLS_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl BFMLS_SVE_Zd_SVE_Pg3_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "bfmls",
        aliases: &[],
        opcode: 0x65202000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::B16B16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::BFMLS_SVE_Zd_SVE_Pg3_SVE_Zn_SVE_Zm_16(
            BFMLS_SVE_Zd_SVE_Pg3_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for BFMLS_SVE_Zd_SVE_Pg3_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl BFMLSL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm_INDEX3_10 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "bfmlsl",
        aliases: &[],
        opcode: 0xc1801018,
        mask: 0xfff01018,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off3x2,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_0,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm_INDEX3_10,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zm,
                        lsb: 16,
                        width: 4,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm1_15,
                        lsb: 15,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_10,
                        lsb: 10,
                        width: 2,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(
            SME_MISC::BFMLSL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm_INDEX3_10(
                BFMLSL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm_INDEX3_10::from(bits),
            ),
        )
    }
}
impl InsnOpcode for BFMLSL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm_INDEX3_10 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl BFMLSL_SME_ZA_array_off2x2_SME_Znx2_SME_Zm_INDEX3_2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "bfmlsl",
        aliases: &[],
        opcode: 0xc1901018,
        mask: 0xfff09038,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off2x2,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_0,
                        lsb: 0,
                        width: 2,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn2,
                    lsb: 6,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm_INDEX3_2,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zm,
                        lsb: 16,
                        width: 4,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_10,
                        lsb: 10,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm1_2,
                        lsb: 2,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(
            SME_MISC::BFMLSL_SME_ZA_array_off2x2_SME_Znx2_SME_Zm_INDEX3_2(
                BFMLSL_SME_ZA_array_off2x2_SME_Znx2_SME_Zm_INDEX3_2::from(bits),
            ),
        )
    }
}
impl InsnOpcode for BFMLSL_SME_ZA_array_off2x2_SME_Znx2_SME_Zm_INDEX3_2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl BFMLSL_SME_ZA_array_off2x2_SME_Znx4_SME_Zm_INDEX3_2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "bfmlsl",
        aliases: &[],
        opcode: 0xc1909018,
        mask: 0xfff09078,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off2x2,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_0,
                        lsb: 0,
                        width: 2,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn4,
                    lsb: 7,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm_INDEX3_2,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zm,
                        lsb: 16,
                        width: 4,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_10,
                        lsb: 10,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm1_2,
                        lsb: 2,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_4.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(
            SME_MISC::BFMLSL_SME_ZA_array_off2x2_SME_Znx4_SME_Zm_INDEX3_2(
                BFMLSL_SME_ZA_array_off2x2_SME_Znx4_SME_Zm_INDEX3_2::from(bits),
            ),
        )
    }
}
impl InsnOpcode for BFMLSL_SME_ZA_array_off2x2_SME_Znx4_SME_Zm_INDEX3_2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl BFMLSL_SME_ZA_array_off2x2_SVE_ZnxN_SME_Zm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "bfmlsl",
        aliases: &[],
        opcode: 0xc1200818,
        mask: 0xfff09c1c,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off2x2,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_0,
                        lsb: 0,
                        width: 2,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ZnxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm,
                    lsb: 16,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::BFMLSL_SME_ZA_array_off2x2_SVE_ZnxN_SME_Zm(
            BFMLSL_SME_ZA_array_off2x2_SVE_ZnxN_SME_Zm::from(bits),
        ))
    }
}
impl InsnOpcode for BFMLSL_SME_ZA_array_off2x2_SVE_ZnxN_SME_Zm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl BFMLSL_SME_ZA_array_off2x2_S_S_SVE_ZnxN_S_H_SME_Zm_S_H {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "bfmlsl",
        aliases: &[],
        opcode: 0xc1300818,
        mask: 0xfff09c1c,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off2x2,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_0,
                        lsb: 0,
                        width: 2,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ZnxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm,
                    lsb: 16,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_4.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(
            SME_MISC::BFMLSL_SME_ZA_array_off2x2_S_S_SVE_ZnxN_S_H_SME_Zm_S_H(
                BFMLSL_SME_ZA_array_off2x2_S_S_SVE_ZnxN_S_H_SME_Zm_S_H::from(bits),
            ),
        )
    }
}
impl InsnOpcode for BFMLSL_SME_ZA_array_off2x2_S_S_SVE_ZnxN_S_H_SME_Zm_S_H {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl BFMLSL_SME_ZA_array_off2x2_SME_Znx2_SME_Zmx2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "bfmlsl",
        aliases: &[],
        opcode: 0xc1a00818,
        mask: 0xffe19c3c,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off2x2,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_0,
                        lsb: 0,
                        width: 2,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn2,
                    lsb: 6,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zmx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm2,
                    lsb: 17,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::BFMLSL_SME_ZA_array_off2x2_SME_Znx2_SME_Zmx2(
            BFMLSL_SME_ZA_array_off2x2_SME_Znx2_SME_Zmx2::from(bits),
        ))
    }
}
impl InsnOpcode for BFMLSL_SME_ZA_array_off2x2_SME_Znx2_SME_Zmx2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl BFMLSL_SME_ZA_array_off2x2_SME_Znx4_SME_Zmx4 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "bfmlsl",
        aliases: &[],
        opcode: 0xc1a10818,
        mask: 0xffe39c7c,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off2x2,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_0,
                        lsb: 0,
                        width: 2,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn4,
                    lsb: 7,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zmx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm4,
                    lsb: 18,
                    width: 3,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_4.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::BFMLSL_SME_ZA_array_off2x2_SME_Znx4_SME_Zmx4(
            BFMLSL_SME_ZA_array_off2x2_SME_Znx4_SME_Zmx4::from(bits),
        ))
    }
}
impl InsnOpcode for BFMLSL_SME_ZA_array_off2x2_SME_Znx4_SME_Zmx4 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl BFMLSL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "bfmlsl",
        aliases: &[],
        opcode: 0xc1200c18,
        mask: 0xfff09c18,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off3x2,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_0,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm,
                    lsb: 16,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::BFMLSL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm(
            BFMLSL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm::from(bits),
        ))
    }
}
impl InsnOpcode for BFMLSL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl BFMLSLB_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "bfmlslb",
        aliases: &[],
        opcode: 0x64e0a000,
        mask: 0xffe0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::BFMLSLB_SVE_Zd_SVE_Zn_SVE_Zm_16(
            BFMLSLB_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for BFMLSLB_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl BFMLSLB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "bfmlslb",
        aliases: &[],
        opcode: 0x64e06000,
        mask: 0xffe0f400,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm3_11_INDEX,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_i3h2,
                        lsb: 19,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_i3l,
                        lsb: 11,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_imm3,
                        lsb: 16,
                        width: 3,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::BFMLSLB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX(
            BFMLSLB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX::from(bits),
        ))
    }
}
impl InsnOpcode for BFMLSLB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl BFMLSLT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "bfmlslt",
        aliases: &[],
        opcode: 0x64e0a400,
        mask: 0xffe0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::BFMLSLT_SVE_Zd_SVE_Zn_SVE_Zm_16(
            BFMLSLT_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for BFMLSLT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl BFMLSLT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "bfmlslt",
        aliases: &[],
        opcode: 0x64e06400,
        mask: 0xffe0f400,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm3_11_INDEX,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_i3h2,
                        lsb: 19,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_i3l,
                        lsb: 11,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_imm3,
                        lsb: 16,
                        width: 3,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::BFMLSLT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX(
            BFMLSLT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX::from(bits),
        ))
    }
}
impl InsnOpcode for BFMLSLT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl BFMMLA_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "bfmmla",
        aliases: &[],
        opcode: 0x6460e400,
        mask: 0xffe0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::BFLOAT16_SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::BFMMLA_SVE_Zd_SVE_Zn_SVE_Zm_16(
            BFMMLA_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for BFMMLA_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl BFMMLA_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "bfmmla",
        aliases: &[],
        opcode: 0x6e40ec00,
        mask: 0xffe0fc00,
        class: InsnClass::BFLOAT16,
        feature_set: InsnFeatureSet::BFLOAT16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::BFLOAT16(BFLOAT16::BFMMLA_Vd_Vn_Vm(BFMMLA_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for BFMMLA_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl BFMOPA_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "bfmopa",
        aliases: &[],
        opcode: 0x81800000,
        mask: 0xffe0001c,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZAda_2b,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_ZAda_2b,
                    lsb: 0,
                    width: 2,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Pm,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Pm,
                    lsb: 13,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(
            SME_MISC::BFMOPA_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16(
                BFMOPA_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16::from(bits),
            ),
        )
    }
}
impl InsnOpcode for BFMOPA_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl BFMOPS_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "bfmops",
        aliases: &[],
        opcode: 0x81800010,
        mask: 0xffe0001c,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZAda_2b,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_ZAda_2b,
                    lsb: 0,
                    width: 2,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Pm,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Pm,
                    lsb: 13,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(
            SME_MISC::BFMOPS_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16(
                BFMOPS_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16::from(bits),
            ),
        )
    }
}
impl InsnOpcode for BFMOPS_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl BFMUL_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "bfmul",
        aliases: &[],
        opcode: 0x64202800,
        mask: 0xffa0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::B16B16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm3_11_INDEX,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_i3h2,
                        lsb: 19,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_i3l,
                        lsb: 11,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_imm3,
                        lsb: 16,
                        width: 3,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::BFMUL_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX(
            BFMUL_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX::from(bits),
        ))
    }
}
impl InsnOpcode for BFMUL_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl BFMUL_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "bfmul",
        aliases: &[],
        opcode: 0x65000800,
        mask: 0xffe0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::B16B16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::BFMUL_SVE_Zd_SVE_Zn_SVE_Zm_16(
            BFMUL_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for BFMUL_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl BFMUL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "bfmul",
        aliases: &[],
        opcode: 0x65028000,
        mask: 0xffffe000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::B16B16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_5,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_5,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::BFMUL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(
            BFMUL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5::from(bits),
        ))
    }
}
impl InsnOpcode for BFMUL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl BFSUB_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "bfsub",
        aliases: &[],
        opcode: 0x65000400,
        mask: 0xffe0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::B16B16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::BFSUB_SVE_Zd_SVE_Zn_SVE_Zm_16(
            BFSUB_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for BFSUB_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl BFSUB_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "bfsub",
        aliases: &[],
        opcode: 0x65018000,
        mask: 0xffffe000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::B16B16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_5,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_5,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::BFSUB_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(
            BFSUB_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5::from(bits),
        ))
    }
}
impl InsnOpcode for BFSUB_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl BFVDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "bfvdot",
        aliases: &[],
        opcode: 0xc1500018,
        mask: 0xfff09038,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off3_0,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_0,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn2,
                    lsb: 6,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm_INDEX2,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zm,
                        lsb: 16,
                        width: 4,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_10,
                        lsb: 10,
                        width: 2,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::BFVDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2(
            BFVDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2::from(bits),
        ))
    }
}
impl InsnOpcode for BFVDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl BGRP_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "bgrp",
        aliases: &[],
        opcode: 0x4500b800,
        mask: 0xff20fc00,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE2BITPERM,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::BGRP_SVE_Zd_SVE_Zn_SVE_Zm_16(
            BGRP_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for BGRP_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl BIC_Rd_Rn_Rm_SFT {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "bic",
        aliases: &[],
        opcode: 0xa200000,
        mask: 0x7f200000,
        class: InsnClass::LOG_SHIFT,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rm_SFT,
                class: InsnOperandClass::MODIFIED_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SF_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LOG_SHIFT(LOG_SHIFT::BIC_Rd_Rn_Rm_SFT(BIC_Rd_Rn_Rm_SFT::from(bits)))
    }
}
impl InsnOpcode for BIC_Rd_Rn_Rm_SFT {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl BIC_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "bic",
        aliases: &[],
        opcode: 0x41b0000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_5,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_5,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::BIC_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(
            BIC_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5::from(bits),
        ))
    }
}
impl InsnOpcode for BIC_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl BIC_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "bic",
        aliases: &[],
        opcode: 0x4e03000,
        mask: 0xffe0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::BIC_SVE_Zd_SVE_Zn_SVE_Zm_16(
            BIC_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for BIC_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl BIC_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "bic",
        aliases: &[],
        opcode: 0x25004010,
        mask: 0xfff0c210,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Pd,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pd,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg4_10,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg4_10,
                    lsb: 10,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pn,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pn,
                    lsb: 5,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pm,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pm,
                    lsb: 16,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::BIC_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm(
            BIC_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm::from(bits),
        ))
    }
}
impl InsnOpcode for BIC_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl BIC_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "bic",
        aliases: &[],
        opcode: 0xe601c00,
        mask: 0xbfe0fc00,
        class: InsnClass::ASIMDSAME,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSAME(ASIMDSAME::BIC_Vd_Vn_Vm(BIC_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for BIC_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl BIC_Vd_SIMD_IMM_SFT {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "bic",
        aliases: &[],
        opcode: 0x2f001400,
        mask: 0xbff89c00,
        class: InsnClass::ASIMDIMM,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SIMD_IMM_SFT,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[InsnOperandQualifier::LSL],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDIMM(ASIMDIMM::BIC_Vd_SIMD_IMM_SFT(BIC_Vd_SIMD_IMM_SFT::from(
            bits,
        )))
    }
}
impl InsnOpcode for BIC_Vd_SIMD_IMM_SFT {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl BIC_Vd_V_4H_SIMD_IMM_SFT_LSL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "bic",
        aliases: &[],
        opcode: 0x2f009400,
        mask: 0xbff8dc00,
        class: InsnClass::ASIMDIMM,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SIMD_IMM_SFT,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[InsnOperandQualifier::LSL],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDIMM(ASIMDIMM::BIC_Vd_V_4H_SIMD_IMM_SFT_LSL(
            BIC_Vd_V_4H_SIMD_IMM_SFT_LSL::from(bits),
        ))
    }
}
impl InsnOpcode for BIC_Vd_V_4H_SIMD_IMM_SFT_LSL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl BICS_Rd_Rn_Rm_SFT {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "bics",
        aliases: &[],
        opcode: 0x6a200000,
        mask: 0x7f200000,
        class: InsnClass::LOG_SHIFT,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rm_SFT,
                class: InsnOperandClass::MODIFIED_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SF_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LOG_SHIFT(LOG_SHIFT::BICS_Rd_Rn_Rm_SFT(BICS_Rd_Rn_Rm_SFT::from(bits)))
    }
}
impl InsnOpcode for BICS_Rd_Rn_Rm_SFT {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl BICS_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "bics",
        aliases: &[],
        opcode: 0x25404010,
        mask: 0xfff0c210,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Pd,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pd,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg4_10,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg4_10,
                    lsb: 10,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pn,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pn,
                    lsb: 5,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pm,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pm,
                    lsb: 16,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::BICS_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm(
            BICS_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm::from(bits),
        ))
    }
}
impl InsnOpcode for BICS_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl BIF_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "bif",
        aliases: &[],
        opcode: 0x2ee01c00,
        mask: 0xbfe0fc00,
        class: InsnClass::ASIMDSAME,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSAME(ASIMDSAME::BIF_Vd_Vn_Vm(BIF_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for BIF_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl BIT_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "bit",
        aliases: &[],
        opcode: 0x2ea01c00,
        mask: 0xbfe0fc00,
        class: InsnClass::ASIMDSAME,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSAME(ASIMDSAME::BIT_Vd_Vn_Vm(BIT_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for BIT_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl BL_ADDR_PCREL26 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "bl",
        aliases: &[],
        opcode: 0x94000000,
        mask: 0xfc000000,
        class: InsnClass::BRANCH_IMM,
        feature_set: InsnFeatureSet::V8,
        operands: &[InsnOperand {
            kind: InsnOperandKind::ADDR_PCREL26,
            class: InsnOperandClass::ADDRESS,
            qualifiers: &[],
            bit_fields: &[BitfieldSpec {
                bitfield: InsnBitField::imm26,
                lsb: 0,
                width: 26,
            }],
        }],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::BRANCH_IMM(BRANCH_IMM::BL_ADDR_PCREL26(BL_ADDR_PCREL26::from(bits)))
    }
}
impl InsnOpcode for BL_ADDR_PCREL26 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl BLR_Rn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "blr",
        aliases: &[],
        opcode: 0xd63f0000,
        mask: 0xfffffc1f,
        class: InsnClass::BRANCH_REG,
        feature_set: InsnFeatureSet::V8,
        operands: &[InsnOperand {
            kind: InsnOperandKind::Rn,
            class: InsnOperandClass::INT_REG,
            qualifiers: &[],
            bit_fields: &[BitfieldSpec {
                bitfield: InsnBitField::Rn,
                lsb: 5,
                width: 5,
            }],
        }],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::BRANCH_REG(BRANCH_REG::BLR_Rn(BLR_Rn::from(bits)))
    }
}
impl InsnOpcode for BLR_Rn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl BLRAA_Rn_Rd_SP {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "blraa",
        aliases: &[],
        opcode: 0xd73f0800,
        mask: 0xfffffc00,
        class: InsnClass::BRANCH_REG,
        feature_set: InsnFeatureSet::PAC,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rd_SP,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::BRANCH_REG(BRANCH_REG::BLRAA_Rn_Rd_SP(BLRAA_Rn_Rd_SP::from(bits)))
    }
}
impl InsnOpcode for BLRAA_Rn_Rd_SP {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl BLRAAZ_Rn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "blraaz",
        aliases: &[],
        opcode: 0xd63f081f,
        mask: 0xfffffc1f,
        class: InsnClass::BRANCH_REG,
        feature_set: InsnFeatureSet::PAC,
        operands: &[InsnOperand {
            kind: InsnOperandKind::Rn,
            class: InsnOperandClass::INT_REG,
            qualifiers: &[],
            bit_fields: &[BitfieldSpec {
                bitfield: InsnBitField::Rn,
                lsb: 5,
                width: 5,
            }],
        }],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::BRANCH_REG(BRANCH_REG::BLRAAZ_Rn(BLRAAZ_Rn::from(bits)))
    }
}
impl InsnOpcode for BLRAAZ_Rn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl BLRAB_Rn_Rd_SP {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "blrab",
        aliases: &[],
        opcode: 0xd73f0c00,
        mask: 0xfffffc00,
        class: InsnClass::BRANCH_REG,
        feature_set: InsnFeatureSet::PAC,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rd_SP,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::BRANCH_REG(BRANCH_REG::BLRAB_Rn_Rd_SP(BLRAB_Rn_Rd_SP::from(bits)))
    }
}
impl InsnOpcode for BLRAB_Rn_Rd_SP {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl BLRABZ_Rn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "blrabz",
        aliases: &[],
        opcode: 0xd63f0c1f,
        mask: 0xfffffc1f,
        class: InsnClass::BRANCH_REG,
        feature_set: InsnFeatureSet::PAC,
        operands: &[InsnOperand {
            kind: InsnOperandKind::Rn,
            class: InsnOperandClass::INT_REG,
            qualifiers: &[],
            bit_fields: &[BitfieldSpec {
                bitfield: InsnBitField::Rn,
                lsb: 5,
                width: 5,
            }],
        }],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::BRANCH_REG(BRANCH_REG::BLRABZ_Rn(BLRABZ_Rn::from(bits)))
    }
}
impl InsnOpcode for BLRABZ_Rn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl BMOPA_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "bmopa",
        aliases: &[],
        opcode: 0x80800008,
        mask: 0xffe0001c,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZAda_2b,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_ZAda_2b,
                    lsb: 0,
                    width: 2,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Pm,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Pm,
                    lsb: 13,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::BMOPA_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16(
            BMOPA_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for BMOPA_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl BMOPS_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "bmops",
        aliases: &[],
        opcode: 0x80800018,
        mask: 0xffe0001c,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZAda_2b,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_ZAda_2b,
                    lsb: 0,
                    width: 2,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Pm,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Pm,
                    lsb: 13,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::BMOPS_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16(
            BMOPS_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for BMOPS_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl BR_Rn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "br",
        aliases: &[],
        opcode: 0xd61f0000,
        mask: 0xfffffc1f,
        class: InsnClass::BRANCH_REG,
        feature_set: InsnFeatureSet::V8,
        operands: &[InsnOperand {
            kind: InsnOperandKind::Rn,
            class: InsnOperandClass::INT_REG,
            qualifiers: &[],
            bit_fields: &[BitfieldSpec {
                bitfield: InsnBitField::Rn,
                lsb: 5,
                width: 5,
            }],
        }],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::BRANCH_REG(BRANCH_REG::BR_Rn(BR_Rn::from(bits)))
    }
}
impl InsnOpcode for BR_Rn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl BRAA_Rn_Rd_SP {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "braa",
        aliases: &[],
        opcode: 0xd71f0800,
        mask: 0xfffffc00,
        class: InsnClass::BRANCH_REG,
        feature_set: InsnFeatureSet::PAC,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rd_SP,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::BRANCH_REG(BRANCH_REG::BRAA_Rn_Rd_SP(BRAA_Rn_Rd_SP::from(bits)))
    }
}
impl InsnOpcode for BRAA_Rn_Rd_SP {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl BRAAZ_Rn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "braaz",
        aliases: &[],
        opcode: 0xd61f081f,
        mask: 0xfffffc1f,
        class: InsnClass::BRANCH_REG,
        feature_set: InsnFeatureSet::PAC,
        operands: &[InsnOperand {
            kind: InsnOperandKind::Rn,
            class: InsnOperandClass::INT_REG,
            qualifiers: &[],
            bit_fields: &[BitfieldSpec {
                bitfield: InsnBitField::Rn,
                lsb: 5,
                width: 5,
            }],
        }],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::BRANCH_REG(BRANCH_REG::BRAAZ_Rn(BRAAZ_Rn::from(bits)))
    }
}
impl InsnOpcode for BRAAZ_Rn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl BRAB_Rn_Rd_SP {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "brab",
        aliases: &[],
        opcode: 0xd71f0c00,
        mask: 0xfffffc00,
        class: InsnClass::BRANCH_REG,
        feature_set: InsnFeatureSet::PAC,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rd_SP,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::BRANCH_REG(BRANCH_REG::BRAB_Rn_Rd_SP(BRAB_Rn_Rd_SP::from(bits)))
    }
}
impl InsnOpcode for BRAB_Rn_Rd_SP {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl BRABZ_Rn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "brabz",
        aliases: &[],
        opcode: 0xd61f0c1f,
        mask: 0xfffffc1f,
        class: InsnClass::BRANCH_REG,
        feature_set: InsnFeatureSet::PAC,
        operands: &[InsnOperand {
            kind: InsnOperandKind::Rn,
            class: InsnOperandClass::INT_REG,
            qualifiers: &[],
            bit_fields: &[BitfieldSpec {
                bitfield: InsnBitField::Rn,
                lsb: 5,
                width: 5,
            }],
        }],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::BRANCH_REG(BRANCH_REG::BRABZ_Rn(BRABZ_Rn::from(bits)))
    }
}
impl InsnOpcode for BRABZ_Rn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl BRK_EXCEPTION {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "brk",
        aliases: &[],
        opcode: 0xd4200000,
        mask: 0xffe0001f,
        class: InsnClass::EXCEPTION,
        feature_set: InsnFeatureSet::V8,
        operands: &[InsnOperand {
            kind: InsnOperandKind::EXCEPTION,
            class: InsnOperandClass::IMMEDIATE,
            qualifiers: &[],
            bit_fields: &[BitfieldSpec {
                bitfield: InsnBitField::imm16_5,
                lsb: 5,
                width: 16,
            }],
        }],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::EXCEPTION(EXCEPTION::BRK_EXCEPTION(BRK_EXCEPTION::from(bits)))
    }
}
impl InsnOpcode for BRK_EXCEPTION {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl BRKA_SVE_Pd_SVE_Pg4_10_SVE_Pn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "brka",
        aliases: &[],
        opcode: 0x25104000,
        mask: 0xffffc200,
        class: InsnClass::SVE_PRED_ZM,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Pd,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pd,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg4_10,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z, InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg4_10,
                    lsb: 10,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pn,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pn,
                    lsb: 5,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_PRED_ZM(SVE_PRED_ZM::BRKA_SVE_Pd_SVE_Pg4_10_SVE_Pn(
            BRKA_SVE_Pd_SVE_Pg4_10_SVE_Pn::from(bits),
        ))
    }
}
impl InsnOpcode for BRKA_SVE_Pd_SVE_Pg4_10_SVE_Pn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl BRKAS_SVE_Pd_SVE_Pg4_10_SVE_Pn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "brkas",
        aliases: &[],
        opcode: 0x25504000,
        mask: 0xffffc210,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Pd,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pd,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg4_10,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg4_10,
                    lsb: 10,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pn,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pn,
                    lsb: 5,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::BRKAS_SVE_Pd_SVE_Pg4_10_SVE_Pn(
            BRKAS_SVE_Pd_SVE_Pg4_10_SVE_Pn::from(bits),
        ))
    }
}
impl InsnOpcode for BRKAS_SVE_Pd_SVE_Pg4_10_SVE_Pn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl BRKB_SVE_Pd_SVE_Pg4_10_SVE_Pn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "brkb",
        aliases: &[],
        opcode: 0x25904000,
        mask: 0xffffc200,
        class: InsnClass::SVE_PRED_ZM,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Pd,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pd,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg4_10,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z, InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg4_10,
                    lsb: 10,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pn,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pn,
                    lsb: 5,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_PRED_ZM(SVE_PRED_ZM::BRKB_SVE_Pd_SVE_Pg4_10_SVE_Pn(
            BRKB_SVE_Pd_SVE_Pg4_10_SVE_Pn::from(bits),
        ))
    }
}
impl InsnOpcode for BRKB_SVE_Pd_SVE_Pg4_10_SVE_Pn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl BRKBS_SVE_Pd_SVE_Pg4_10_SVE_Pn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "brkbs",
        aliases: &[],
        opcode: 0x25d04000,
        mask: 0xffffc210,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Pd,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pd,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg4_10,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg4_10,
                    lsb: 10,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pn,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pn,
                    lsb: 5,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::BRKBS_SVE_Pd_SVE_Pg4_10_SVE_Pn(
            BRKBS_SVE_Pd_SVE_Pg4_10_SVE_Pn::from(bits),
        ))
    }
}
impl InsnOpcode for BRKBS_SVE_Pd_SVE_Pg4_10_SVE_Pn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl BRKN_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pd {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "brkn",
        aliases: &[],
        opcode: 0x25184000,
        mask: 0xffffc210,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Pd,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pd,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg4_10,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg4_10,
                    lsb: 10,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pn,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pn,
                    lsb: 5,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pd,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pd,
                    lsb: 0,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::BRKN_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pd(
            BRKN_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pd::from(bits),
        ))
    }
}
impl InsnOpcode for BRKN_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pd {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl BRKNS_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pd {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "brkns",
        aliases: &[],
        opcode: 0x25584000,
        mask: 0xffffc210,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Pd,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pd,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg4_10,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg4_10,
                    lsb: 10,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pn,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pn,
                    lsb: 5,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pd,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pd,
                    lsb: 0,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::BRKNS_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pd(
            BRKNS_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pd::from(bits),
        ))
    }
}
impl InsnOpcode for BRKNS_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pd {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl BRKPA_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "brkpa",
        aliases: &[],
        opcode: 0x2500c000,
        mask: 0xfff0c210,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Pd,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pd,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg4_10,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg4_10,
                    lsb: 10,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pn,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pn,
                    lsb: 5,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pm,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pm,
                    lsb: 16,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::BRKPA_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm(
            BRKPA_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm::from(bits),
        ))
    }
}
impl InsnOpcode for BRKPA_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl BRKPAS_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "brkpas",
        aliases: &[],
        opcode: 0x2540c000,
        mask: 0xfff0c210,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Pd,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pd,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg4_10,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg4_10,
                    lsb: 10,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pn,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pn,
                    lsb: 5,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pm,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pm,
                    lsb: 16,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::BRKPAS_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm(
            BRKPAS_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm::from(bits),
        ))
    }
}
impl InsnOpcode for BRKPAS_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl BRKPB_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "brkpb",
        aliases: &[],
        opcode: 0x2500c010,
        mask: 0xfff0c210,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Pd,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pd,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg4_10,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg4_10,
                    lsb: 10,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pn,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pn,
                    lsb: 5,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pm,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pm,
                    lsb: 16,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::BRKPB_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm(
            BRKPB_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm::from(bits),
        ))
    }
}
impl InsnOpcode for BRKPB_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl BRKPBS_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "brkpbs",
        aliases: &[],
        opcode: 0x2540c010,
        mask: 0xfff0c210,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Pd,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pd,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg4_10,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg4_10,
                    lsb: 10,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pn,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pn,
                    lsb: 5,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pm,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pm,
                    lsb: 16,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::BRKPBS_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm(
            BRKPBS_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm::from(bits),
        ))
    }
}
impl InsnOpcode for BRKPBS_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl BSL_SVE_Zd_SVE_Zd_SVE_Zm_16_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "bsl",
        aliases: &[],
        opcode: 0x4203c00,
        mask: 0xffe0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::BSL_SVE_Zd_SVE_Zd_SVE_Zm_16_SVE_Zn(
            BSL_SVE_Zd_SVE_Zd_SVE_Zm_16_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for BSL_SVE_Zd_SVE_Zd_SVE_Zm_16_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl BSL_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "bsl",
        aliases: &[],
        opcode: 0x2e601c00,
        mask: 0xbfe0fc00,
        class: InsnClass::ASIMDSAME,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSAME(ASIMDSAME::BSL_Vd_Vn_Vm(BSL_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for BSL_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl BSL1N_SVE_Zd_SVE_Zd_SVE_Zm_16_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "bsl1n",
        aliases: &[],
        opcode: 0x4603c00,
        mask: 0xffe0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::BSL1N_SVE_Zd_SVE_Zd_SVE_Zm_16_SVE_Zn(
            BSL1N_SVE_Zd_SVE_Zd_SVE_Zm_16_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for BSL1N_SVE_Zd_SVE_Zd_SVE_Zm_16_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl BSL2N_SVE_Zd_SVE_Zd_SVE_Zm_16_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "bsl2n",
        aliases: &[],
        opcode: 0x4a03c00,
        mask: 0xffe0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::BSL2N_SVE_Zd_SVE_Zd_SVE_Zm_16_SVE_Zn(
            BSL2N_SVE_Zd_SVE_Zd_SVE_Zm_16_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for BSL2N_SVE_Zd_SVE_Zd_SVE_Zm_16_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CADD_SVE_Zd_SVE_Zd_SVE_Zn_SVE_IMM_ROT3 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cadd",
        aliases: &[],
        opcode: 0x4500d800,
        mask: 0xff3ff800,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_IMM_ROT3,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_rot3,
                    lsb: 10,
                    width: 1,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::CADD_SVE_Zd_SVE_Zd_SVE_Zn_SVE_IMM_ROT3(
            CADD_SVE_Zd_SVE_Zd_SVE_Zn_SVE_IMM_ROT3::from(bits),
        ))
    }
}
impl InsnOpcode for CADD_SVE_Zd_SVE_Zd_SVE_Zn_SVE_IMM_ROT3 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CAS_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cas",
        aliases: &[],
        opcode: 0x88a07c00,
        mask: 0xbfe0fc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LSE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_LSE_SZ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::CAS_Rs_Rt_ADDR_SIMPLE(
            CAS_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for CAS_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CASA_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "casa",
        aliases: &[],
        opcode: 0x88e07c00,
        mask: 0xbfe0fc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LSE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_LSE_SZ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::CASA_Rs_Rt_ADDR_SIMPLE(
            CASA_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for CASA_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CASAB_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "casab",
        aliases: &[],
        opcode: 0x8e07c00,
        mask: 0xffe0fc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LSE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::CASAB_Rs_Rt_ADDR_SIMPLE(
            CASAB_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for CASAB_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CASAH_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "casah",
        aliases: &[],
        opcode: 0x48e07c00,
        mask: 0xffe0fc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LSE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::CASAH_Rs_Rt_ADDR_SIMPLE(
            CASAH_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for CASAH_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CASAL_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "casal",
        aliases: &[],
        opcode: 0x88e0fc00,
        mask: 0xbfe0fc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LSE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_LSE_SZ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::CASAL_Rs_Rt_ADDR_SIMPLE(
            CASAL_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for CASAL_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CASALB_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "casalb",
        aliases: &[],
        opcode: 0x8e0fc00,
        mask: 0xffe0fc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LSE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::CASALB_Rs_Rt_ADDR_SIMPLE(
            CASALB_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for CASALB_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CASALH_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "casalh",
        aliases: &[],
        opcode: 0x48e0fc00,
        mask: 0xffe0fc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LSE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::CASALH_Rs_Rt_ADDR_SIMPLE(
            CASALH_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for CASALH_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CASB_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "casb",
        aliases: &[],
        opcode: 0x8a07c00,
        mask: 0xffe0fc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LSE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::CASB_Rs_Rt_ADDR_SIMPLE(
            CASB_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for CASB_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CASH_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cash",
        aliases: &[],
        opcode: 0x48a07c00,
        mask: 0xffe0fc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LSE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::CASH_Rs_Rt_ADDR_SIMPLE(
            CASH_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for CASH_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CASL_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "casl",
        aliases: &[],
        opcode: 0x88a0fc00,
        mask: 0xbfe0fc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LSE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_LSE_SZ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::CASL_Rs_Rt_ADDR_SIMPLE(
            CASL_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for CASL_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CASLB_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "caslb",
        aliases: &[],
        opcode: 0x8a0fc00,
        mask: 0xffe0fc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LSE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::CASLB_Rs_Rt_ADDR_SIMPLE(
            CASLB_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for CASLB_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CASLH_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "caslh",
        aliases: &[],
        opcode: 0x48a0fc00,
        mask: 0xffe0fc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LSE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::CASLH_Rs_Rt_ADDR_SIMPLE(
            CASLH_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for CASLH_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CASP_Rs_PAIRREG_Rt_PAIRREG_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "casp",
        aliases: &[],
        opcode: 0x8207c00,
        mask: 0xbfe0fc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LSE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::PAIRREG,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::PAIRREG,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_LSE_SZ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::CASP_Rs_PAIRREG_Rt_PAIRREG_ADDR_SIMPLE(
            CASP_Rs_PAIRREG_Rt_PAIRREG_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for CASP_Rs_PAIRREG_Rt_PAIRREG_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CASPA_Rs_PAIRREG_Rt_PAIRREG_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "caspa",
        aliases: &[],
        opcode: 0x8607c00,
        mask: 0xbfe0fc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LSE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::PAIRREG,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::PAIRREG,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_LSE_SZ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::CASPA_Rs_PAIRREG_Rt_PAIRREG_ADDR_SIMPLE(
            CASPA_Rs_PAIRREG_Rt_PAIRREG_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for CASPA_Rs_PAIRREG_Rt_PAIRREG_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CASPAL_Rs_PAIRREG_Rt_PAIRREG_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "caspal",
        aliases: &[],
        opcode: 0x860fc00,
        mask: 0xbfe0fc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LSE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::PAIRREG,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::PAIRREG,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_LSE_SZ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::CASPAL_Rs_PAIRREG_Rt_PAIRREG_ADDR_SIMPLE(
            CASPAL_Rs_PAIRREG_Rt_PAIRREG_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for CASPAL_Rs_PAIRREG_Rt_PAIRREG_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CASPL_Rs_PAIRREG_Rt_PAIRREG_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "caspl",
        aliases: &[],
        opcode: 0x820fc00,
        mask: 0xbfe0fc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LSE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::PAIRREG,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::PAIRREG,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_LSE_SZ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::CASPL_Rs_PAIRREG_Rt_PAIRREG_ADDR_SIMPLE(
            CASPL_Rs_PAIRREG_Rt_PAIRREG_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for CASPL_Rs_PAIRREG_Rt_PAIRREG_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CBNZ_Rt_ADDR_PCREL19 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cbnz",
        aliases: &[],
        opcode: 0x35000000,
        mask: 0x7f000000,
        class: InsnClass::COMPBRANCH,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_PCREL19,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::imm19,
                    lsb: 5,
                    width: 19,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SF_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::COMPBRANCH(COMPBRANCH::CBNZ_Rt_ADDR_PCREL19(
            CBNZ_Rt_ADDR_PCREL19::from(bits),
        ))
    }
}
impl InsnOpcode for CBNZ_Rt_ADDR_PCREL19 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CBZ_Rt_ADDR_PCREL19 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cbz",
        aliases: &[],
        opcode: 0x34000000,
        mask: 0x7f000000,
        class: InsnClass::COMPBRANCH,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_PCREL19,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::imm19,
                    lsb: 5,
                    width: 19,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SF_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::COMPBRANCH(COMPBRANCH::CBZ_Rt_ADDR_PCREL19(CBZ_Rt_ADDR_PCREL19::from(
            bits,
        )))
    }
}
impl InsnOpcode for CBZ_Rt_ADDR_PCREL19 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CCMN_Rn_Rm_NZCV_COND {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ccmn",
        aliases: &[],
        opcode: 0x3a400000,
        mask: 0x7fe00c10,
        class: InsnClass::CONDCMP_REG,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rm,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::NZCV,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::nzcv,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::COND,
                class: InsnOperandClass::COND,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SF_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::CONDCMP_REG(CONDCMP_REG::CCMN_Rn_Rm_NZCV_COND(
            CCMN_Rn_Rm_NZCV_COND::from(bits),
        ))
    }
}
impl InsnOpcode for CCMN_Rn_Rm_NZCV_COND {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CCMN_Rn_CCMP_IMM_NZCV_COND {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ccmn",
        aliases: &[],
        opcode: 0x3a400800,
        mask: 0x7fe00c10,
        class: InsnClass::CONDCMP_IMM,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::CCMP_IMM,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::imm5,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::NZCV,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::nzcv,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::COND,
                class: InsnOperandClass::COND,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SF_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::CONDCMP_IMM(CONDCMP_IMM::CCMN_Rn_CCMP_IMM_NZCV_COND(
            CCMN_Rn_CCMP_IMM_NZCV_COND::from(bits),
        ))
    }
}
impl InsnOpcode for CCMN_Rn_CCMP_IMM_NZCV_COND {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CCMP_Rn_Rm_NZCV_COND {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ccmp",
        aliases: &[],
        opcode: 0x7a400000,
        mask: 0x7fe00c10,
        class: InsnClass::CONDCMP_REG,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rm,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::NZCV,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::nzcv,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::COND,
                class: InsnOperandClass::COND,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SF_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::CONDCMP_REG(CONDCMP_REG::CCMP_Rn_Rm_NZCV_COND(
            CCMP_Rn_Rm_NZCV_COND::from(bits),
        ))
    }
}
impl InsnOpcode for CCMP_Rn_Rm_NZCV_COND {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CCMP_Rn_CCMP_IMM_NZCV_COND {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ccmp",
        aliases: &[],
        opcode: 0x7a400800,
        mask: 0x7fe00c10,
        class: InsnClass::CONDCMP_IMM,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::CCMP_IMM,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::imm5,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::NZCV,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::nzcv,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::COND,
                class: InsnOperandClass::COND,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SF_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::CONDCMP_IMM(CONDCMP_IMM::CCMP_Rn_CCMP_IMM_NZCV_COND(
            CCMP_Rn_CCMP_IMM_NZCV_COND::from(bits),
        ))
    }
}
impl InsnOpcode for CCMP_Rn_CCMP_IMM_NZCV_COND {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CDOT_SVE_Zd_SVE_Zn_SVE_Zm_16_SVE_IMM_ROT2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cdot",
        aliases: &[],
        opcode: 0x44801000,
        mask: 0xffa0f000,
        class: InsnClass::SVE_SIZE_SD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_IMM_ROT2,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_rot2,
                    lsb: 10,
                    width: 2,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_SD(SVE_SIZE_SD::CDOT_SVE_Zd_SVE_Zn_SVE_Zm_16_SVE_IMM_ROT2(
            CDOT_SVE_Zd_SVE_Zn_SVE_Zm_16_SVE_IMM_ROT2::from(bits),
        ))
    }
}
impl InsnOpcode for CDOT_SVE_Zd_SVE_Zn_SVE_Zm_16_SVE_IMM_ROT2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CDOT_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX_SVE_IMM_ROT2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cdot",
        aliases: &[],
        opcode: 0x44a04000,
        mask: 0xffe0f000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm3_INDEX,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_IMM_ROT2,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_rot2,
                    lsb: 10,
                    width: 2,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::CDOT_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX_SVE_IMM_ROT2(
            CDOT_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX_SVE_IMM_ROT2::from(bits),
        ))
    }
}
impl InsnOpcode for CDOT_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX_SVE_IMM_ROT2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CDOT_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX_SVE_IMM_ROT2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cdot",
        aliases: &[],
        opcode: 0x44e04000,
        mask: 0xffe0f000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm4_INDEX,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_IMM_ROT2,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_rot2,
                    lsb: 10,
                    width: 2,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::CDOT_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX_SVE_IMM_ROT2(
            CDOT_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX_SVE_IMM_ROT2::from(bits),
        ))
    }
}
impl InsnOpcode for CDOT_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX_SVE_IMM_ROT2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CFINV {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cfinv",
        aliases: &[],
        opcode: 0xd500401f,
        mask: 0xffffffff,
        class: InsnClass::IC_SYSTEM,
        feature_set: InsnFeatureSet::FLAGM,
        operands: &[],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::IC_SYSTEM(IC_SYSTEM::CFINV(CFINV::from(bits)))
    }
}
impl InsnOpcode for CFINV {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CHKFEAT_X16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "chkfeat",
        aliases: &[],
        opcode: 0xd503251f,
        mask: 0xffffffff,
        class: InsnClass::IC_SYSTEM,
        feature_set: InsnFeatureSet::CHK,
        operands: &[InsnOperand {
            kind: InsnOperandKind::X16,
            class: InsnOperandClass::INT_REG,
            qualifiers: &[],
            bit_fields: &[],
        }],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::IC_SYSTEM(IC_SYSTEM::CHKFEAT_X16(CHKFEAT_X16::from(bits)))
    }
}
impl InsnOpcode for CHKFEAT_X16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CLASTA_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "clasta",
        aliases: &[],
        opcode: 0x5288000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_5,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_5,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::CLASTA_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(
            CLASTA_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5::from(bits),
        ))
    }
}
impl InsnOpcode for CLASTA_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CLASTA_SVE_Vd_SVE_Pg3_SVE_Vd_SVE_Zm_5 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "clasta",
        aliases: &[],
        opcode: 0x52a8000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Vd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Vd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_5,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_5,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::CLASTA_SVE_Vd_SVE_Pg3_SVE_Vd_SVE_Zm_5(
            CLASTA_SVE_Vd_SVE_Pg3_SVE_Vd_SVE_Zm_5::from(bits),
        ))
    }
}
impl InsnOpcode for CLASTA_SVE_Vd_SVE_Pg3_SVE_Vd_SVE_Zm_5 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CLASTA_Rd_SVE_Pg3_Rd_SVE_Zm_5 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "clasta",
        aliases: &[],
        opcode: 0x530a000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[
                    InsnOperandQualifier::W,
                    InsnOperandQualifier::W,
                    InsnOperandQualifier::W,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_5,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_5,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::CLASTA_Rd_SVE_Pg3_Rd_SVE_Zm_5(
            CLASTA_Rd_SVE_Pg3_Rd_SVE_Zm_5::from(bits),
        ))
    }
}
impl InsnOpcode for CLASTA_Rd_SVE_Pg3_Rd_SVE_Zm_5 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CLASTB_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "clastb",
        aliases: &[],
        opcode: 0x5298000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_5,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_5,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::CLASTB_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(
            CLASTB_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5::from(bits),
        ))
    }
}
impl InsnOpcode for CLASTB_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CLASTB_SVE_Vd_SVE_Pg3_SVE_Vd_SVE_Zm_5 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "clastb",
        aliases: &[],
        opcode: 0x52b8000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Vd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Vd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_5,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_5,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::CLASTB_SVE_Vd_SVE_Pg3_SVE_Vd_SVE_Zm_5(
            CLASTB_SVE_Vd_SVE_Pg3_SVE_Vd_SVE_Zm_5::from(bits),
        ))
    }
}
impl InsnOpcode for CLASTB_SVE_Vd_SVE_Pg3_SVE_Vd_SVE_Zm_5 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CLASTB_Rd_SVE_Pg3_Rd_SVE_Zm_5 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "clastb",
        aliases: &[],
        opcode: 0x531a000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[
                    InsnOperandQualifier::W,
                    InsnOperandQualifier::W,
                    InsnOperandQualifier::W,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_5,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_5,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::CLASTB_Rd_SVE_Pg3_Rd_SVE_Zm_5(
            CLASTB_Rd_SVE_Pg3_Rd_SVE_Zm_5::from(bits),
        ))
    }
}
impl InsnOpcode for CLASTB_Rd_SVE_Pg3_Rd_SVE_Zm_5 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CLREX_UIMM4 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "clrex",
        aliases: &[],
        opcode: 0xd503305f,
        mask: 0xfffff0ff,
        class: InsnClass::IC_SYSTEM,
        feature_set: InsnFeatureSet::V8,
        operands: &[InsnOperand {
            kind: InsnOperandKind::UIMM4,
            class: InsnOperandClass::IMMEDIATE,
            qualifiers: &[],
            bit_fields: &[BitfieldSpec {
                bitfield: InsnBitField::CRm,
                lsb: 8,
                width: 4,
            }],
        }],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::IC_SYSTEM(IC_SYSTEM::CLREX_UIMM4(CLREX_UIMM4::from(bits)))
    }
}
impl InsnOpcode for CLREX_UIMM4 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CLS_Rd_Rn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cls",
        aliases: &[],
        opcode: 0x5ac01400,
        mask: 0x7ffffc00,
        class: InsnClass::DP_1SRC,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SF_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::DP_1SRC(DP_1SRC::CLS_Rd_Rn(CLS_Rd_Rn::from(bits)))
    }
}
impl InsnOpcode for CLS_Rd_Rn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CLS_SVE_Zd_SVE_Pg3_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cls",
        aliases: &[],
        opcode: 0x418a000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M, InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::CLS_SVE_Zd_SVE_Pg3_SVE_Zn(
            CLS_SVE_Zd_SVE_Pg3_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for CLS_SVE_Zd_SVE_Pg3_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CLS_Vd_Vn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cls",
        aliases: &[],
        opcode: 0xe204800,
        mask: 0xbf3ffc00,
        class: InsnClass::ASIMDMISC,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDMISC(ASIMDMISC::CLS_Vd_Vn(CLS_Vd_Vn::from(bits)))
    }
}
impl InsnOpcode for CLS_Vd_Vn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CLZ_Rd_Rn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "clz",
        aliases: &[],
        opcode: 0x5ac01000,
        mask: 0x7ffffc00,
        class: InsnClass::DP_1SRC,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SF_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::DP_1SRC(DP_1SRC::CLZ_Rd_Rn(CLZ_Rd_Rn::from(bits)))
    }
}
impl InsnOpcode for CLZ_Rd_Rn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CLZ_SVE_Zd_SVE_Pg3_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "clz",
        aliases: &[],
        opcode: 0x419a000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M, InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::CLZ_SVE_Zd_SVE_Pg3_SVE_Zn(
            CLZ_SVE_Zd_SVE_Pg3_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for CLZ_SVE_Zd_SVE_Pg3_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CLZ_Vd_Vn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "clz",
        aliases: &[],
        opcode: 0x2e204800,
        mask: 0xbf3ffc00,
        class: InsnClass::ASIMDMISC,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDMISC(ASIMDMISC::CLZ_Vd_Vn(CLZ_Vd_Vn::from(bits)))
    }
}
impl InsnOpcode for CLZ_Vd_Vn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CMEQ_Vd_Vn_IMM0 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cmeq",
        aliases: &[],
        opcode: 0xe209800,
        mask: 0xbf3ffc00,
        class: InsnClass::ASIMDMISC,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::IMM0,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDMISC(ASIMDMISC::CMEQ_Vd_Vn_IMM0(CMEQ_Vd_Vn_IMM0::from(bits)))
    }
}
impl InsnOpcode for CMEQ_Vd_Vn_IMM0 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CMEQ_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cmeq",
        aliases: &[],
        opcode: 0x2e208c00,
        mask: 0xbf20fc00,
        class: InsnClass::ASIMDSAME,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSAME(ASIMDSAME::CMEQ_Vd_Vn_Vm(CMEQ_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for CMEQ_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CMEQ_Sd_Sn_IMM0 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cmeq",
        aliases: &[],
        opcode: 0x5e209800,
        mask: 0xff3ffc00,
        class: InsnClass::ASISDMISC,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::IMM0,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMD_SCALAR_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDMISC(ASISDMISC::CMEQ_Sd_Sn_IMM0(CMEQ_Sd_Sn_IMM0::from(bits)))
    }
}
impl InsnOpcode for CMEQ_Sd_Sn_IMM0 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CMEQ_Sd_Sn_Sm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cmeq",
        aliases: &[],
        opcode: 0x7ee08c00,
        mask: 0xffe0fc00,
        class: InsnClass::ASISDSAME,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sm,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMD_SCALAR_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDSAME(ASISDSAME::CMEQ_Sd_Sn_Sm(CMEQ_Sd_Sn_Sm::from(bits)))
    }
}
impl InsnOpcode for CMEQ_Sd_Sn_Sm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CMGE_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cmge",
        aliases: &[],
        opcode: 0xe203c00,
        mask: 0xbf20fc00,
        class: InsnClass::ASIMDSAME,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSAME(ASIMDSAME::CMGE_Vd_Vn_Vm(CMGE_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for CMGE_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CMGE_Vd_Vn_IMM0 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cmge",
        aliases: &[],
        opcode: 0x2e208800,
        mask: 0xbf3ffc00,
        class: InsnClass::ASIMDMISC,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::IMM0,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDMISC(ASIMDMISC::CMGE_Vd_Vn_IMM0(CMGE_Vd_Vn_IMM0::from(bits)))
    }
}
impl InsnOpcode for CMGE_Vd_Vn_IMM0 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CMGE_Sd_Sn_IMM0 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cmge",
        aliases: &[],
        opcode: 0x7e208800,
        mask: 0xff3ffc00,
        class: InsnClass::ASISDMISC,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::IMM0,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMD_SCALAR_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDMISC(ASISDMISC::CMGE_Sd_Sn_IMM0(CMGE_Sd_Sn_IMM0::from(bits)))
    }
}
impl InsnOpcode for CMGE_Sd_Sn_IMM0 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CMGE_Sd_Sn_Sm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cmge",
        aliases: &[],
        opcode: 0x5ee03c00,
        mask: 0xffe0fc00,
        class: InsnClass::ASISDSAME,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sm,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMD_SCALAR_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDSAME(ASISDSAME::CMGE_Sd_Sn_Sm(CMGE_Sd_Sn_Sm::from(bits)))
    }
}
impl InsnOpcode for CMGE_Sd_Sn_Sm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CMGT_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cmgt",
        aliases: &[],
        opcode: 0xe203400,
        mask: 0xbf20fc00,
        class: InsnClass::ASIMDSAME,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSAME(ASIMDSAME::CMGT_Vd_Vn_Vm(CMGT_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for CMGT_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CMGT_Vd_Vn_IMM0 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cmgt",
        aliases: &[],
        opcode: 0xe208800,
        mask: 0xbf3ffc00,
        class: InsnClass::ASIMDMISC,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::IMM0,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDMISC(ASIMDMISC::CMGT_Vd_Vn_IMM0(CMGT_Vd_Vn_IMM0::from(bits)))
    }
}
impl InsnOpcode for CMGT_Vd_Vn_IMM0 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CMGT_Sd_Sn_IMM0 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cmgt",
        aliases: &[],
        opcode: 0x5e208800,
        mask: 0xff3ffc00,
        class: InsnClass::ASISDMISC,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::IMM0,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMD_SCALAR_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDMISC(ASISDMISC::CMGT_Sd_Sn_IMM0(CMGT_Sd_Sn_IMM0::from(bits)))
    }
}
impl InsnOpcode for CMGT_Sd_Sn_IMM0 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CMGT_Sd_Sn_Sm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cmgt",
        aliases: &[],
        opcode: 0x5ee03400,
        mask: 0xffe0fc00,
        class: InsnClass::ASISDSAME,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sm,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMD_SCALAR_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDSAME(ASISDSAME::CMGT_Sd_Sn_Sm(CMGT_Sd_Sn_Sm::from(bits)))
    }
}
impl InsnOpcode for CMGT_Sd_Sn_Sm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CMHI_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cmhi",
        aliases: &[],
        opcode: 0x2e203400,
        mask: 0xbf20fc00,
        class: InsnClass::ASIMDSAME,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSAME(ASIMDSAME::CMHI_Vd_Vn_Vm(CMHI_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for CMHI_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CMHI_Sd_Sn_Sm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cmhi",
        aliases: &[],
        opcode: 0x7ee03400,
        mask: 0xffe0fc00,
        class: InsnClass::ASISDSAME,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sm,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMD_SCALAR_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDSAME(ASISDSAME::CMHI_Sd_Sn_Sm(CMHI_Sd_Sn_Sm::from(bits)))
    }
}
impl InsnOpcode for CMHI_Sd_Sn_Sm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CMHS_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cmhs",
        aliases: &[],
        opcode: 0x2e203c00,
        mask: 0xbf20fc00,
        class: InsnClass::ASIMDSAME,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSAME(ASIMDSAME::CMHS_Vd_Vn_Vm(CMHS_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for CMHS_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CMHS_Sd_Sn_Sm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cmhs",
        aliases: &[],
        opcode: 0x7ee03c00,
        mask: 0xffe0fc00,
        class: InsnClass::ASISDSAME,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sm,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMD_SCALAR_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDSAME(ASISDSAME::CMHS_Sd_Sn_Sm(CMHS_Sd_Sn_Sm::from(bits)))
    }
}
impl InsnOpcode for CMHS_Sd_Sn_Sm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CMLA_SVE_Zd_SVE_Zn_SVE_Zm_16_SVE_IMM_ROT2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cmla",
        aliases: &[],
        opcode: 0x44002000,
        mask: 0xff20f000,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_IMM_ROT2,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_rot2,
                    lsb: 10,
                    width: 2,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::CMLA_SVE_Zd_SVE_Zn_SVE_Zm_16_SVE_IMM_ROT2(
            CMLA_SVE_Zd_SVE_Zn_SVE_Zm_16_SVE_IMM_ROT2::from(bits),
        ))
    }
}
impl InsnOpcode for CMLA_SVE_Zd_SVE_Zn_SVE_Zm_16_SVE_IMM_ROT2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CMLA_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX_SVE_IMM_ROT2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cmla",
        aliases: &[],
        opcode: 0x44a06000,
        mask: 0xffe0f000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm3_INDEX,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_IMM_ROT2,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_rot2,
                    lsb: 10,
                    width: 2,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::CMLA_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX_SVE_IMM_ROT2(
            CMLA_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX_SVE_IMM_ROT2::from(bits),
        ))
    }
}
impl InsnOpcode for CMLA_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX_SVE_IMM_ROT2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CMLA_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX_SVE_IMM_ROT2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cmla",
        aliases: &[],
        opcode: 0x44e06000,
        mask: 0xffe0f000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm4_INDEX,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_IMM_ROT2,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_rot2,
                    lsb: 10,
                    width: 2,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::CMLA_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX_SVE_IMM_ROT2(
            CMLA_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX_SVE_IMM_ROT2::from(bits),
        ))
    }
}
impl InsnOpcode for CMLA_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX_SVE_IMM_ROT2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CMLE_Vd_Vn_IMM0 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cmle",
        aliases: &[],
        opcode: 0x2e209800,
        mask: 0xbf3ffc00,
        class: InsnClass::ASIMDMISC,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::IMM0,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDMISC(ASIMDMISC::CMLE_Vd_Vn_IMM0(CMLE_Vd_Vn_IMM0::from(bits)))
    }
}
impl InsnOpcode for CMLE_Vd_Vn_IMM0 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CMLE_Sd_Sn_IMM0 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cmle",
        aliases: &[],
        opcode: 0x7e209800,
        mask: 0xff3ffc00,
        class: InsnClass::ASISDMISC,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::IMM0,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMD_SCALAR_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDMISC(ASISDMISC::CMLE_Sd_Sn_IMM0(CMLE_Sd_Sn_IMM0::from(bits)))
    }
}
impl InsnOpcode for CMLE_Sd_Sn_IMM0 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CMLT_Vd_Vn_IMM0 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cmlt",
        aliases: &[],
        opcode: 0xe20a800,
        mask: 0xbf3ffc00,
        class: InsnClass::ASIMDMISC,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::IMM0,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDMISC(ASIMDMISC::CMLT_Vd_Vn_IMM0(CMLT_Vd_Vn_IMM0::from(bits)))
    }
}
impl InsnOpcode for CMLT_Vd_Vn_IMM0 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CMLT_Sd_Sn_IMM0 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cmlt",
        aliases: &[],
        opcode: 0x5e20a800,
        mask: 0xff3ffc00,
        class: InsnClass::ASISDMISC,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::IMM0,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMD_SCALAR_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDMISC(ASISDMISC::CMLT_Sd_Sn_IMM0(CMLT_Sd_Sn_IMM0::from(bits)))
    }
}
impl InsnOpcode for CMLT_Sd_Sn_IMM0 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CMPEQ_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cmpeq",
        aliases: &[],
        opcode: 0x24002000,
        mask: 0xff20e010,
        class: InsnClass::SVE_SIZE_BHS,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Pd,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pd,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_Z,
                    InsnOperandQualifier::P_Z,
                    InsnOperandQualifier::P_Z,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_D,
                    InsnOperandQualifier::S_D,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHS(SVE_SIZE_BHS::CMPEQ_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16(
            CMPEQ_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for CMPEQ_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CMPEQ_SVE_Pd_S_B_SVE_Pg3_P_Z_SVE_Zn_S_B_SVE_Zm_16_S_B {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cmpeq",
        aliases: &[],
        opcode: 0x2400a000,
        mask: 0xff20e010,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Pd,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pd,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_Z,
                    InsnOperandQualifier::P_Z,
                    InsnOperandQualifier::P_Z,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(
            SVE_SIZE_BHSD::CMPEQ_SVE_Pd_S_B_SVE_Pg3_P_Z_SVE_Zn_S_B_SVE_Zm_16_S_B(
                CMPEQ_SVE_Pd_S_B_SVE_Pg3_P_Z_SVE_Zn_S_B_SVE_Zm_16_S_B::from(bits),
            ),
        )
    }
}
impl InsnOpcode for CMPEQ_SVE_Pd_S_B_SVE_Pg3_P_Z_SVE_Zn_S_B_SVE_Zm_16_S_B {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CMPEQ_SVE_Pd_SVE_Pg3_SVE_Zn_SIMM5 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cmpeq",
        aliases: &[],
        opcode: 0x25008000,
        mask: 0xff20e010,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Pd,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pd,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_Z,
                    InsnOperandQualifier::P_Z,
                    InsnOperandQualifier::P_Z,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SIMM5,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::imm5,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::CMPEQ_SVE_Pd_SVE_Pg3_SVE_Zn_SIMM5(
            CMPEQ_SVE_Pd_SVE_Pg3_SVE_Zn_SIMM5::from(bits),
        ))
    }
}
impl InsnOpcode for CMPEQ_SVE_Pd_SVE_Pg3_SVE_Zn_SIMM5 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CMPGE_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cmpge",
        aliases: &[],
        opcode: 0x24004000,
        mask: 0xff20e010,
        class: InsnClass::SVE_SIZE_BHS,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Pd,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pd,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_Z,
                    InsnOperandQualifier::P_Z,
                    InsnOperandQualifier::P_Z,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_D,
                    InsnOperandQualifier::S_D,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHS(SVE_SIZE_BHS::CMPGE_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16(
            CMPGE_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for CMPGE_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CMPGE_SVE_Pd_S_B_SVE_Pg3_P_Z_SVE_Zn_S_B_SVE_Zm_16_S_B {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cmpge",
        aliases: &[],
        opcode: 0x24008000,
        mask: 0xff20e010,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Pd,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pd,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_Z,
                    InsnOperandQualifier::P_Z,
                    InsnOperandQualifier::P_Z,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ALIAS.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(
            SVE_SIZE_BHSD::CMPGE_SVE_Pd_S_B_SVE_Pg3_P_Z_SVE_Zn_S_B_SVE_Zm_16_S_B(
                CMPGE_SVE_Pd_S_B_SVE_Pg3_P_Z_SVE_Zn_S_B_SVE_Zm_16_S_B::from(bits),
            ),
        )
    }
}
impl InsnOpcode for CMPGE_SVE_Pd_S_B_SVE_Pg3_P_Z_SVE_Zn_S_B_SVE_Zm_16_S_B {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CMPGE_SVE_Pd_SVE_Pg3_SVE_Zn_SIMM5 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cmpge",
        aliases: &[],
        opcode: 0x25000000,
        mask: 0xff20e010,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Pd,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pd,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_Z,
                    InsnOperandQualifier::P_Z,
                    InsnOperandQualifier::P_Z,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SIMM5,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::imm5,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::CMPGE_SVE_Pd_SVE_Pg3_SVE_Zn_SIMM5(
            CMPGE_SVE_Pd_SVE_Pg3_SVE_Zn_SIMM5::from(bits),
        ))
    }
}
impl InsnOpcode for CMPGE_SVE_Pd_SVE_Pg3_SVE_Zn_SIMM5 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CMPGT_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cmpgt",
        aliases: &[],
        opcode: 0x24004010,
        mask: 0xff20e010,
        class: InsnClass::SVE_SIZE_BHS,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Pd,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pd,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_Z,
                    InsnOperandQualifier::P_Z,
                    InsnOperandQualifier::P_Z,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_D,
                    InsnOperandQualifier::S_D,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHS(SVE_SIZE_BHS::CMPGT_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16(
            CMPGT_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for CMPGT_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CMPGT_SVE_Pd_S_B_SVE_Pg3_P_Z_SVE_Zn_S_B_SVE_Zm_16_S_B {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cmpgt",
        aliases: &[],
        opcode: 0x24008010,
        mask: 0xff20e010,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Pd,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pd,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_Z,
                    InsnOperandQualifier::P_Z,
                    InsnOperandQualifier::P_Z,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ALIAS.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(
            SVE_SIZE_BHSD::CMPGT_SVE_Pd_S_B_SVE_Pg3_P_Z_SVE_Zn_S_B_SVE_Zm_16_S_B(
                CMPGT_SVE_Pd_S_B_SVE_Pg3_P_Z_SVE_Zn_S_B_SVE_Zm_16_S_B::from(bits),
            ),
        )
    }
}
impl InsnOpcode for CMPGT_SVE_Pd_S_B_SVE_Pg3_P_Z_SVE_Zn_S_B_SVE_Zm_16_S_B {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CMPGT_SVE_Pd_SVE_Pg3_SVE_Zn_SIMM5 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cmpgt",
        aliases: &[],
        opcode: 0x25000010,
        mask: 0xff20e010,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Pd,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pd,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_Z,
                    InsnOperandQualifier::P_Z,
                    InsnOperandQualifier::P_Z,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SIMM5,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::imm5,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::CMPGT_SVE_Pd_SVE_Pg3_SVE_Zn_SIMM5(
            CMPGT_SVE_Pd_SVE_Pg3_SVE_Zn_SIMM5::from(bits),
        ))
    }
}
impl InsnOpcode for CMPGT_SVE_Pd_SVE_Pg3_SVE_Zn_SIMM5 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CMPHI_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cmphi",
        aliases: &[],
        opcode: 0x24000010,
        mask: 0xff20e010,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Pd,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pd,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_Z,
                    InsnOperandQualifier::P_Z,
                    InsnOperandQualifier::P_Z,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ALIAS.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::CMPHI_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16(
            CMPHI_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for CMPHI_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CMPHI_SVE_Pd_S_B_SVE_Pg3_P_Z_SVE_Zn_S_B_SVE_Zm_16_S_D {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cmphi",
        aliases: &[],
        opcode: 0x2400c010,
        mask: 0xff20e010,
        class: InsnClass::SVE_SIZE_BHS,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Pd,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pd,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_Z,
                    InsnOperandQualifier::P_Z,
                    InsnOperandQualifier::P_Z,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_D,
                    InsnOperandQualifier::S_D,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHS(
            SVE_SIZE_BHS::CMPHI_SVE_Pd_S_B_SVE_Pg3_P_Z_SVE_Zn_S_B_SVE_Zm_16_S_D(
                CMPHI_SVE_Pd_S_B_SVE_Pg3_P_Z_SVE_Zn_S_B_SVE_Zm_16_S_D::from(bits),
            ),
        )
    }
}
impl InsnOpcode for CMPHI_SVE_Pd_S_B_SVE_Pg3_P_Z_SVE_Zn_S_B_SVE_Zm_16_S_D {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CMPHI_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_UIMM7 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cmphi",
        aliases: &[],
        opcode: 0x24200010,
        mask: 0xff202010,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Pd,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pd,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_Z,
                    InsnOperandQualifier::P_Z,
                    InsnOperandQualifier::P_Z,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_UIMM7,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_imm7,
                    lsb: 14,
                    width: 7,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::CMPHI_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_UIMM7(
            CMPHI_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_UIMM7::from(bits),
        ))
    }
}
impl InsnOpcode for CMPHI_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_UIMM7 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CMPHS_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cmphs",
        aliases: &[],
        opcode: 0x24000000,
        mask: 0xff20e010,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Pd,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pd,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_Z,
                    InsnOperandQualifier::P_Z,
                    InsnOperandQualifier::P_Z,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ALIAS.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::CMPHS_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16(
            CMPHS_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for CMPHS_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CMPHS_SVE_Pd_S_B_SVE_Pg3_P_Z_SVE_Zn_S_B_SVE_Zm_16_S_D {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cmphs",
        aliases: &[],
        opcode: 0x2400c000,
        mask: 0xff20e010,
        class: InsnClass::SVE_SIZE_BHS,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Pd,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pd,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_Z,
                    InsnOperandQualifier::P_Z,
                    InsnOperandQualifier::P_Z,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_D,
                    InsnOperandQualifier::S_D,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHS(
            SVE_SIZE_BHS::CMPHS_SVE_Pd_S_B_SVE_Pg3_P_Z_SVE_Zn_S_B_SVE_Zm_16_S_D(
                CMPHS_SVE_Pd_S_B_SVE_Pg3_P_Z_SVE_Zn_S_B_SVE_Zm_16_S_D::from(bits),
            ),
        )
    }
}
impl InsnOpcode for CMPHS_SVE_Pd_S_B_SVE_Pg3_P_Z_SVE_Zn_S_B_SVE_Zm_16_S_D {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CMPHS_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_UIMM7 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cmphs",
        aliases: &[],
        opcode: 0x24200000,
        mask: 0xff202010,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Pd,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pd,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_Z,
                    InsnOperandQualifier::P_Z,
                    InsnOperandQualifier::P_Z,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_UIMM7,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_imm7,
                    lsb: 14,
                    width: 7,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::CMPHS_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_UIMM7(
            CMPHS_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_UIMM7::from(bits),
        ))
    }
}
impl InsnOpcode for CMPHS_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_UIMM7 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CMPLE_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cmple",
        aliases: &[],
        opcode: 0x24006010,
        mask: 0xff20e010,
        class: InsnClass::SVE_SIZE_BHS,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Pd,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pd,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_Z,
                    InsnOperandQualifier::P_Z,
                    InsnOperandQualifier::P_Z,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_D,
                    InsnOperandQualifier::S_D,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHS(SVE_SIZE_BHS::CMPLE_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16(
            CMPLE_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for CMPLE_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CMPLE_SVE_Pd_SVE_Pg3_SVE_Zn_SIMM5 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cmple",
        aliases: &[],
        opcode: 0x25002010,
        mask: 0xff20e010,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Pd,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pd,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_Z,
                    InsnOperandQualifier::P_Z,
                    InsnOperandQualifier::P_Z,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SIMM5,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::imm5,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::CMPLE_SVE_Pd_SVE_Pg3_SVE_Zn_SIMM5(
            CMPLE_SVE_Pd_SVE_Pg3_SVE_Zn_SIMM5::from(bits),
        ))
    }
}
impl InsnOpcode for CMPLE_SVE_Pd_SVE_Pg3_SVE_Zn_SIMM5 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CMPLO_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cmplo",
        aliases: &[],
        opcode: 0x2400e000,
        mask: 0xff20e010,
        class: InsnClass::SVE_SIZE_BHS,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Pd,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pd,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_Z,
                    InsnOperandQualifier::P_Z,
                    InsnOperandQualifier::P_Z,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_D,
                    InsnOperandQualifier::S_D,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHS(SVE_SIZE_BHS::CMPLO_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16(
            CMPLO_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for CMPLO_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CMPLO_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_UIMM7 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cmplo",
        aliases: &[],
        opcode: 0x24202000,
        mask: 0xff202010,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Pd,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pd,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_Z,
                    InsnOperandQualifier::P_Z,
                    InsnOperandQualifier::P_Z,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_UIMM7,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_imm7,
                    lsb: 14,
                    width: 7,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::CMPLO_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_UIMM7(
            CMPLO_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_UIMM7::from(bits),
        ))
    }
}
impl InsnOpcode for CMPLO_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_UIMM7 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CMPLS_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cmpls",
        aliases: &[],
        opcode: 0x2400e010,
        mask: 0xff20e010,
        class: InsnClass::SVE_SIZE_BHS,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Pd,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pd,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_Z,
                    InsnOperandQualifier::P_Z,
                    InsnOperandQualifier::P_Z,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_D,
                    InsnOperandQualifier::S_D,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHS(SVE_SIZE_BHS::CMPLS_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16(
            CMPLS_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for CMPLS_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CMPLS_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_UIMM7 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cmpls",
        aliases: &[],
        opcode: 0x24202010,
        mask: 0xff202010,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Pd,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pd,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_Z,
                    InsnOperandQualifier::P_Z,
                    InsnOperandQualifier::P_Z,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_UIMM7,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_imm7,
                    lsb: 14,
                    width: 7,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::CMPLS_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_UIMM7(
            CMPLS_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_UIMM7::from(bits),
        ))
    }
}
impl InsnOpcode for CMPLS_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_UIMM7 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CMPLT_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cmplt",
        aliases: &[],
        opcode: 0x24006000,
        mask: 0xff20e010,
        class: InsnClass::SVE_SIZE_BHS,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Pd,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pd,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_Z,
                    InsnOperandQualifier::P_Z,
                    InsnOperandQualifier::P_Z,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_D,
                    InsnOperandQualifier::S_D,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHS(SVE_SIZE_BHS::CMPLT_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16(
            CMPLT_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for CMPLT_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CMPLT_SVE_Pd_SVE_Pg3_SVE_Zn_SIMM5 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cmplt",
        aliases: &[],
        opcode: 0x25002000,
        mask: 0xff20e010,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Pd,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pd,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_Z,
                    InsnOperandQualifier::P_Z,
                    InsnOperandQualifier::P_Z,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SIMM5,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::imm5,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::CMPLT_SVE_Pd_SVE_Pg3_SVE_Zn_SIMM5(
            CMPLT_SVE_Pd_SVE_Pg3_SVE_Zn_SIMM5::from(bits),
        ))
    }
}
impl InsnOpcode for CMPLT_SVE_Pd_SVE_Pg3_SVE_Zn_SIMM5 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CMPNE_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cmpne",
        aliases: &[],
        opcode: 0x24002010,
        mask: 0xff20e010,
        class: InsnClass::SVE_SIZE_BHS,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Pd,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pd,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_Z,
                    InsnOperandQualifier::P_Z,
                    InsnOperandQualifier::P_Z,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_D,
                    InsnOperandQualifier::S_D,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHS(SVE_SIZE_BHS::CMPNE_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16(
            CMPNE_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for CMPNE_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CMPNE_SVE_Pd_S_B_SVE_Pg3_P_Z_SVE_Zn_S_B_SVE_Zm_16_S_B {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cmpne",
        aliases: &[],
        opcode: 0x2400a010,
        mask: 0xff20e010,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Pd,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pd,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_Z,
                    InsnOperandQualifier::P_Z,
                    InsnOperandQualifier::P_Z,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(
            SVE_SIZE_BHSD::CMPNE_SVE_Pd_S_B_SVE_Pg3_P_Z_SVE_Zn_S_B_SVE_Zm_16_S_B(
                CMPNE_SVE_Pd_S_B_SVE_Pg3_P_Z_SVE_Zn_S_B_SVE_Zm_16_S_B::from(bits),
            ),
        )
    }
}
impl InsnOpcode for CMPNE_SVE_Pd_S_B_SVE_Pg3_P_Z_SVE_Zn_S_B_SVE_Zm_16_S_B {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CMPNE_SVE_Pd_SVE_Pg3_SVE_Zn_SIMM5 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cmpne",
        aliases: &[],
        opcode: 0x25008010,
        mask: 0xff20e010,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Pd,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pd,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_Z,
                    InsnOperandQualifier::P_Z,
                    InsnOperandQualifier::P_Z,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SIMM5,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::imm5,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::CMPNE_SVE_Pd_SVE_Pg3_SVE_Zn_SIMM5(
            CMPNE_SVE_Pd_SVE_Pg3_SVE_Zn_SIMM5::from(bits),
        ))
    }
}
impl InsnOpcode for CMPNE_SVE_Pd_SVE_Pg3_SVE_Zn_SIMM5 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CMTST_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cmtst",
        aliases: &[],
        opcode: 0xe208c00,
        mask: 0xbf20fc00,
        class: InsnClass::ASIMDSAME,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSAME(ASIMDSAME::CMTST_Vd_Vn_Vm(CMTST_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for CMTST_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CMTST_Sd_Sn_Sm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cmtst",
        aliases: &[],
        opcode: 0x5ee08c00,
        mask: 0xffe0fc00,
        class: InsnClass::ASISDSAME,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sm,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMD_SCALAR_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDSAME(ASISDSAME::CMTST_Sd_Sn_Sm(CMTST_Sd_Sn_Sm::from(bits)))
    }
}
impl InsnOpcode for CMTST_Sd_Sn_Sm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CNOT_SVE_Zd_SVE_Pg3_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cnot",
        aliases: &[],
        opcode: 0x41ba000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M, InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::CNOT_SVE_Zd_SVE_Pg3_SVE_Zn(
            CNOT_SVE_Zd_SVE_Pg3_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for CNOT_SVE_Zd_SVE_Pg3_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CNT_Rd_Rn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cnt",
        aliases: &[],
        opcode: 0x5ac01c00,
        mask: 0x7ffffc00,
        class: InsnClass::CSSC,
        feature_set: InsnFeatureSet::CSSC,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SF_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::CSSC(CSSC::CNT_Rd_Rn(CNT_Rd_Rn::from(bits)))
    }
}
impl InsnOpcode for CNT_Rd_Rn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CNT_SVE_Zd_SVE_Pg3_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cnt",
        aliases: &[],
        opcode: 0x41aa000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M, InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::CNT_SVE_Zd_SVE_Pg3_SVE_Zn(
            CNT_SVE_Zd_SVE_Pg3_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for CNT_SVE_Zd_SVE_Pg3_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CNT_Vd_Vn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cnt",
        aliases: &[],
        opcode: 0xe205800,
        mask: 0xbf3ffc00,
        class: InsnClass::ASIMDMISC,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDMISC(ASIMDMISC::CNT_Vd_Vn(CNT_Vd_Vn::from(bits)))
    }
}
impl InsnOpcode for CNT_Vd_Vn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CNTB_Rd_SVE_PATTERN_SCALED {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cntb",
        aliases: &[],
        opcode: 0x420e000,
        mask: 0xfff0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_PATTERN_SCALED,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_pattern,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::CNTB_Rd_SVE_PATTERN_SCALED(
            CNTB_Rd_SVE_PATTERN_SCALED::from(bits),
        ))
    }
}
impl InsnOpcode for CNTB_Rd_SVE_PATTERN_SCALED {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CNTD_Rd_SVE_PATTERN_SCALED {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cntd",
        aliases: &[],
        opcode: 0x4e0e000,
        mask: 0xfff0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_PATTERN_SCALED,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_pattern,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::CNTD_Rd_SVE_PATTERN_SCALED(
            CNTD_Rd_SVE_PATTERN_SCALED::from(bits),
        ))
    }
}
impl InsnOpcode for CNTD_Rd_SVE_PATTERN_SCALED {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CNTH_Rd_SVE_PATTERN_SCALED {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cnth",
        aliases: &[],
        opcode: 0x460e000,
        mask: 0xfff0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_PATTERN_SCALED,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_pattern,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::CNTH_Rd_SVE_PATTERN_SCALED(
            CNTH_Rd_SVE_PATTERN_SCALED::from(bits),
        ))
    }
}
impl InsnOpcode for CNTH_Rd_SVE_PATTERN_SCALED {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CNTP_Rd_SVE_Pg4_10_SVE_Pn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cntp",
        aliases: &[],
        opcode: 0x25208000,
        mask: 0xff3fc200,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg4_10,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg4_10,
                    lsb: 10,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pn,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pn,
                    lsb: 5,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::CNTP_Rd_SVE_Pg4_10_SVE_Pn(
            CNTP_Rd_SVE_Pg4_10_SVE_Pn::from(bits),
        ))
    }
}
impl InsnOpcode for CNTP_Rd_SVE_Pg4_10_SVE_Pn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CNTP_Rd_SME_PNn_SME_VLxN_10 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cntp",
        aliases: &[],
        opcode: 0x25208200,
        mask: 0xff3ffa00,
        class: InsnClass::SME_SIZE_22,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNn,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pn,
                    lsb: 5,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_VLxN_10,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_VL_10,
                    lsb: 10,
                    width: 1,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_SIZE_22(SME_SIZE_22::CNTP_Rd_SME_PNn_SME_VLxN_10(
            CNTP_Rd_SME_PNn_SME_VLxN_10::from(bits),
        ))
    }
}
impl InsnOpcode for CNTP_Rd_SME_PNn_SME_VLxN_10 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CNTW_Rd_SVE_PATTERN_SCALED {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cntw",
        aliases: &[],
        opcode: 0x4a0e000,
        mask: 0xfff0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_PATTERN_SCALED,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_pattern,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::CNTW_Rd_SVE_PATTERN_SCALED(
            CNTW_Rd_SVE_PATTERN_SCALED::from(bits),
        ))
    }
}
impl InsnOpcode for CNTW_Rd_SVE_PATTERN_SCALED {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl COMPACT_SVE_Zd_SVE_Pg3_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "compact",
        aliases: &[],
        opcode: 0x5a18000,
        mask: 0xffbfe000,
        class: InsnClass::SVE_SIZE_SD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_SD(SVE_SIZE_SD::COMPACT_SVE_Zd_SVE_Pg3_SVE_Zn(
            COMPACT_SVE_Zd_SVE_Pg3_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for COMPACT_SVE_Zd_SVE_Pg3_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CPY_SVE_Zd_SVE_Pg4_16_SVE_ASIMM {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cpy",
        aliases: &[],
        opcode: 0x5100000,
        mask: 0xff308000,
        class: InsnClass::SVE_CPY,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg4_16,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z, InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg4_16,
                    lsb: 16,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ASIMM,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_imm9,
                    lsb: 5,
                    width: 9,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ALIAS.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_CPY(SVE_CPY::CPY_SVE_Zd_SVE_Pg4_16_SVE_ASIMM(
            CPY_SVE_Zd_SVE_Pg4_16_SVE_ASIMM::from(bits),
        ))
    }
}
impl InsnOpcode for CPY_SVE_Zd_SVE_Pg4_16_SVE_ASIMM {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CPY_SVE_Zd_SVE_Pg3_SVE_Vn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cpy",
        aliases: &[],
        opcode: 0x5208000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M, InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Vn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ALIAS.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::CPY_SVE_Zd_SVE_Pg3_SVE_Vn(
            CPY_SVE_Zd_SVE_Pg3_SVE_Vn::from(bits),
        ))
    }
}
impl InsnOpcode for CPY_SVE_Zd_SVE_Pg3_SVE_Vn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CPY_SVE_Zd_SVE_Pg3_Rn_SP {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cpy",
        aliases: &[],
        opcode: 0x528a000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M, InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn_SP,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ALIAS.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::CPY_SVE_Zd_SVE_Pg3_Rn_SP(
            CPY_SVE_Zd_SVE_Pg3_Rn_SP::from(bits),
        ))
    }
}
impl InsnOpcode for CPY_SVE_Zd_SVE_Pg3_Rn_SP {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CPYE_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cpye",
        aliases: &[],
        opcode: 0x1d800400,
        mask: 0xffe0fc00,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::MOPS,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_WB_Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(AARCH64_MISC::CPYE_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(
            CPYE_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn::from(bits),
        ))
    }
}
impl InsnOpcode for CPYE_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CPYEN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cpyen",
        aliases: &[],
        opcode: 0x1d80c400,
        mask: 0xffe0fc00,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::MOPS,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_WB_Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(AARCH64_MISC::CPYEN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(
            CPYEN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn::from(bits),
        ))
    }
}
impl InsnOpcode for CPYEN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CPYERN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cpyern",
        aliases: &[],
        opcode: 0x1d808400,
        mask: 0xffe0fc00,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::MOPS,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_WB_Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(AARCH64_MISC::CPYERN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(
            CPYERN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn::from(bits),
        ))
    }
}
impl InsnOpcode for CPYERN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CPYERT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cpyert",
        aliases: &[],
        opcode: 0x1d802400,
        mask: 0xffe0fc00,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::MOPS,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_WB_Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(AARCH64_MISC::CPYERT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(
            CPYERT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn::from(bits),
        ))
    }
}
impl InsnOpcode for CPYERT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CPYERTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cpyertn",
        aliases: &[],
        opcode: 0x1d80e400,
        mask: 0xffe0fc00,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::MOPS,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_WB_Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(AARCH64_MISC::CPYERTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(
            CPYERTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn::from(bits),
        ))
    }
}
impl InsnOpcode for CPYERTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CPYERTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cpyertrn",
        aliases: &[],
        opcode: 0x1d80a400,
        mask: 0xffe0fc00,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::MOPS,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_WB_Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(AARCH64_MISC::CPYERTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(
            CPYERTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn::from(bits),
        ))
    }
}
impl InsnOpcode for CPYERTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CPYERTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cpyertwn",
        aliases: &[],
        opcode: 0x1d806400,
        mask: 0xffe0fc00,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::MOPS,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_WB_Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(AARCH64_MISC::CPYERTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(
            CPYERTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn::from(bits),
        ))
    }
}
impl InsnOpcode for CPYERTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CPYET_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cpyet",
        aliases: &[],
        opcode: 0x1d803400,
        mask: 0xffe0fc00,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::MOPS,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_WB_Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(AARCH64_MISC::CPYET_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(
            CPYET_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn::from(bits),
        ))
    }
}
impl InsnOpcode for CPYET_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CPYETN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cpyetn",
        aliases: &[],
        opcode: 0x1d80f400,
        mask: 0xffe0fc00,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::MOPS,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_WB_Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(AARCH64_MISC::CPYETN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(
            CPYETN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn::from(bits),
        ))
    }
}
impl InsnOpcode for CPYETN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CPYETRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cpyetrn",
        aliases: &[],
        opcode: 0x1d80b400,
        mask: 0xffe0fc00,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::MOPS,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_WB_Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(AARCH64_MISC::CPYETRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(
            CPYETRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn::from(bits),
        ))
    }
}
impl InsnOpcode for CPYETRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CPYETWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cpyetwn",
        aliases: &[],
        opcode: 0x1d807400,
        mask: 0xffe0fc00,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::MOPS,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_WB_Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(AARCH64_MISC::CPYETWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(
            CPYETWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn::from(bits),
        ))
    }
}
impl InsnOpcode for CPYETWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CPYEWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cpyewn",
        aliases: &[],
        opcode: 0x1d804400,
        mask: 0xffe0fc00,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::MOPS,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_WB_Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(AARCH64_MISC::CPYEWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(
            CPYEWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn::from(bits),
        ))
    }
}
impl InsnOpcode for CPYEWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CPYEWT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cpyewt",
        aliases: &[],
        opcode: 0x1d801400,
        mask: 0xffe0fc00,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::MOPS,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_WB_Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(AARCH64_MISC::CPYEWT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(
            CPYEWT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn::from(bits),
        ))
    }
}
impl InsnOpcode for CPYEWT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CPYEWTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cpyewtn",
        aliases: &[],
        opcode: 0x1d80d400,
        mask: 0xffe0fc00,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::MOPS,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_WB_Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(AARCH64_MISC::CPYEWTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(
            CPYEWTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn::from(bits),
        ))
    }
}
impl InsnOpcode for CPYEWTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CPYEWTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cpyewtrn",
        aliases: &[],
        opcode: 0x1d809400,
        mask: 0xffe0fc00,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::MOPS,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_WB_Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(AARCH64_MISC::CPYEWTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(
            CPYEWTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn::from(bits),
        ))
    }
}
impl InsnOpcode for CPYEWTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CPYEWTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cpyewtwn",
        aliases: &[],
        opcode: 0x1d805400,
        mask: 0xffe0fc00,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::MOPS,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_WB_Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(AARCH64_MISC::CPYEWTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(
            CPYEWTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn::from(bits),
        ))
    }
}
impl InsnOpcode for CPYEWTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CPYFE_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cpyfe",
        aliases: &[],
        opcode: 0x19800400,
        mask: 0xffe0fc00,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::MOPS,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_WB_Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(AARCH64_MISC::CPYFE_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(
            CPYFE_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn::from(bits),
        ))
    }
}
impl InsnOpcode for CPYFE_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CPYFEN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cpyfen",
        aliases: &[],
        opcode: 0x1980c400,
        mask: 0xffe0fc00,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::MOPS,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_WB_Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(AARCH64_MISC::CPYFEN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(
            CPYFEN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn::from(bits),
        ))
    }
}
impl InsnOpcode for CPYFEN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CPYFERN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cpyfern",
        aliases: &[],
        opcode: 0x19808400,
        mask: 0xffe0fc00,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::MOPS,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_WB_Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(AARCH64_MISC::CPYFERN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(
            CPYFERN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn::from(bits),
        ))
    }
}
impl InsnOpcode for CPYFERN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CPYFERT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cpyfert",
        aliases: &[],
        opcode: 0x19802400,
        mask: 0xffe0fc00,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::MOPS,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_WB_Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(AARCH64_MISC::CPYFERT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(
            CPYFERT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn::from(bits),
        ))
    }
}
impl InsnOpcode for CPYFERT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CPYFERTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cpyfertn",
        aliases: &[],
        opcode: 0x1980e400,
        mask: 0xffe0fc00,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::MOPS,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_WB_Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(AARCH64_MISC::CPYFERTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(
            CPYFERTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn::from(bits),
        ))
    }
}
impl InsnOpcode for CPYFERTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CPYFERTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cpyfertrn",
        aliases: &[],
        opcode: 0x1980a400,
        mask: 0xffe0fc00,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::MOPS,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_WB_Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(
            AARCH64_MISC::CPYFERTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(
                CPYFERTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn::from(bits),
            ),
        )
    }
}
impl InsnOpcode for CPYFERTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CPYFERTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cpyfertwn",
        aliases: &[],
        opcode: 0x19806400,
        mask: 0xffe0fc00,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::MOPS,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_WB_Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(
            AARCH64_MISC::CPYFERTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(
                CPYFERTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn::from(bits),
            ),
        )
    }
}
impl InsnOpcode for CPYFERTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CPYFET_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cpyfet",
        aliases: &[],
        opcode: 0x19803400,
        mask: 0xffe0fc00,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::MOPS,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_WB_Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(AARCH64_MISC::CPYFET_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(
            CPYFET_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn::from(bits),
        ))
    }
}
impl InsnOpcode for CPYFET_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CPYFETN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cpyfetn",
        aliases: &[],
        opcode: 0x1980f400,
        mask: 0xffe0fc00,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::MOPS,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_WB_Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(AARCH64_MISC::CPYFETN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(
            CPYFETN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn::from(bits),
        ))
    }
}
impl InsnOpcode for CPYFETN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CPYFETRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cpyfetrn",
        aliases: &[],
        opcode: 0x1980b400,
        mask: 0xffe0fc00,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::MOPS,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_WB_Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(AARCH64_MISC::CPYFETRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(
            CPYFETRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn::from(bits),
        ))
    }
}
impl InsnOpcode for CPYFETRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CPYFETWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cpyfetwn",
        aliases: &[],
        opcode: 0x19807400,
        mask: 0xffe0fc00,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::MOPS,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_WB_Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(AARCH64_MISC::CPYFETWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(
            CPYFETWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn::from(bits),
        ))
    }
}
impl InsnOpcode for CPYFETWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CPYFEWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cpyfewn",
        aliases: &[],
        opcode: 0x19804400,
        mask: 0xffe0fc00,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::MOPS,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_WB_Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(AARCH64_MISC::CPYFEWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(
            CPYFEWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn::from(bits),
        ))
    }
}
impl InsnOpcode for CPYFEWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CPYFEWT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cpyfewt",
        aliases: &[],
        opcode: 0x19801400,
        mask: 0xffe0fc00,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::MOPS,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_WB_Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(AARCH64_MISC::CPYFEWT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(
            CPYFEWT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn::from(bits),
        ))
    }
}
impl InsnOpcode for CPYFEWT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CPYFEWTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cpyfewtn",
        aliases: &[],
        opcode: 0x1980d400,
        mask: 0xffe0fc00,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::MOPS,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_WB_Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(AARCH64_MISC::CPYFEWTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(
            CPYFEWTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn::from(bits),
        ))
    }
}
impl InsnOpcode for CPYFEWTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CPYFEWTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cpyfewtrn",
        aliases: &[],
        opcode: 0x19809400,
        mask: 0xffe0fc00,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::MOPS,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_WB_Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(
            AARCH64_MISC::CPYFEWTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(
                CPYFEWTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn::from(bits),
            ),
        )
    }
}
impl InsnOpcode for CPYFEWTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CPYFEWTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cpyfewtwn",
        aliases: &[],
        opcode: 0x19805400,
        mask: 0xffe0fc00,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::MOPS,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_WB_Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(
            AARCH64_MISC::CPYFEWTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(
                CPYFEWTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn::from(bits),
            ),
        )
    }
}
impl InsnOpcode for CPYFEWTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CPYFM_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cpyfm",
        aliases: &[],
        opcode: 0x19400400,
        mask: 0xffe0fc00,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::MOPS,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_WB_Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(AARCH64_MISC::CPYFM_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(
            CPYFM_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn::from(bits),
        ))
    }
}
impl InsnOpcode for CPYFM_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CPYFMN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cpyfmn",
        aliases: &[],
        opcode: 0x1940c400,
        mask: 0xffe0fc00,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::MOPS,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_WB_Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(AARCH64_MISC::CPYFMN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(
            CPYFMN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn::from(bits),
        ))
    }
}
impl InsnOpcode for CPYFMN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CPYFMRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cpyfmrn",
        aliases: &[],
        opcode: 0x19408400,
        mask: 0xffe0fc00,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::MOPS,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_WB_Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(AARCH64_MISC::CPYFMRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(
            CPYFMRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn::from(bits),
        ))
    }
}
impl InsnOpcode for CPYFMRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CPYFMRT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cpyfmrt",
        aliases: &[],
        opcode: 0x19402400,
        mask: 0xffe0fc00,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::MOPS,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_WB_Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(AARCH64_MISC::CPYFMRT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(
            CPYFMRT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn::from(bits),
        ))
    }
}
impl InsnOpcode for CPYFMRT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CPYFMRTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cpyfmrtn",
        aliases: &[],
        opcode: 0x1940e400,
        mask: 0xffe0fc00,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::MOPS,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_WB_Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(AARCH64_MISC::CPYFMRTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(
            CPYFMRTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn::from(bits),
        ))
    }
}
impl InsnOpcode for CPYFMRTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CPYFMRTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cpyfmrtrn",
        aliases: &[],
        opcode: 0x1940a400,
        mask: 0xffe0fc00,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::MOPS,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_WB_Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(
            AARCH64_MISC::CPYFMRTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(
                CPYFMRTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn::from(bits),
            ),
        )
    }
}
impl InsnOpcode for CPYFMRTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CPYFMRTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cpyfmrtwn",
        aliases: &[],
        opcode: 0x19406400,
        mask: 0xffe0fc00,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::MOPS,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_WB_Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(
            AARCH64_MISC::CPYFMRTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(
                CPYFMRTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn::from(bits),
            ),
        )
    }
}
impl InsnOpcode for CPYFMRTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CPYFMT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cpyfmt",
        aliases: &[],
        opcode: 0x19403400,
        mask: 0xffe0fc00,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::MOPS,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_WB_Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(AARCH64_MISC::CPYFMT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(
            CPYFMT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn::from(bits),
        ))
    }
}
impl InsnOpcode for CPYFMT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CPYFMTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cpyfmtn",
        aliases: &[],
        opcode: 0x1940f400,
        mask: 0xffe0fc00,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::MOPS,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_WB_Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(AARCH64_MISC::CPYFMTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(
            CPYFMTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn::from(bits),
        ))
    }
}
impl InsnOpcode for CPYFMTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CPYFMTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cpyfmtrn",
        aliases: &[],
        opcode: 0x1940b400,
        mask: 0xffe0fc00,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::MOPS,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_WB_Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(AARCH64_MISC::CPYFMTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(
            CPYFMTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn::from(bits),
        ))
    }
}
impl InsnOpcode for CPYFMTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CPYFMTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cpyfmtwn",
        aliases: &[],
        opcode: 0x19407400,
        mask: 0xffe0fc00,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::MOPS,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_WB_Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(AARCH64_MISC::CPYFMTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(
            CPYFMTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn::from(bits),
        ))
    }
}
impl InsnOpcode for CPYFMTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CPYFMWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cpyfmwn",
        aliases: &[],
        opcode: 0x19404400,
        mask: 0xffe0fc00,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::MOPS,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_WB_Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(AARCH64_MISC::CPYFMWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(
            CPYFMWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn::from(bits),
        ))
    }
}
impl InsnOpcode for CPYFMWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CPYFMWT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cpyfmwt",
        aliases: &[],
        opcode: 0x19401400,
        mask: 0xffe0fc00,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::MOPS,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_WB_Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(AARCH64_MISC::CPYFMWT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(
            CPYFMWT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn::from(bits),
        ))
    }
}
impl InsnOpcode for CPYFMWT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CPYFMWTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cpyfmwtn",
        aliases: &[],
        opcode: 0x1940d400,
        mask: 0xffe0fc00,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::MOPS,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_WB_Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(AARCH64_MISC::CPYFMWTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(
            CPYFMWTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn::from(bits),
        ))
    }
}
impl InsnOpcode for CPYFMWTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CPYFMWTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cpyfmwtrn",
        aliases: &[],
        opcode: 0x19409400,
        mask: 0xffe0fc00,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::MOPS,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_WB_Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(
            AARCH64_MISC::CPYFMWTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(
                CPYFMWTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn::from(bits),
            ),
        )
    }
}
impl InsnOpcode for CPYFMWTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CPYFMWTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cpyfmwtwn",
        aliases: &[],
        opcode: 0x19405400,
        mask: 0xffe0fc00,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::MOPS,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_WB_Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(
            AARCH64_MISC::CPYFMWTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(
                CPYFMWTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn::from(bits),
            ),
        )
    }
}
impl InsnOpcode for CPYFMWTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CPYFP_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cpyfp",
        aliases: &[],
        opcode: 0x19000400,
        mask: 0xffe0fc00,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::MOPS,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_WB_Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::RESTRICTED_NEXT_INSN_SET.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(AARCH64_MISC::CPYFP_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(
            CPYFP_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn::from(bits),
        ))
    }
}
impl InsnOpcode for CPYFP_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CPYFPN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cpyfpn",
        aliases: &[],
        opcode: 0x1900c400,
        mask: 0xffe0fc00,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::MOPS,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_WB_Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::RESTRICTED_NEXT_INSN_SET.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(AARCH64_MISC::CPYFPN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(
            CPYFPN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn::from(bits),
        ))
    }
}
impl InsnOpcode for CPYFPN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CPYFPRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cpyfprn",
        aliases: &[],
        opcode: 0x19008400,
        mask: 0xffe0fc00,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::MOPS,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_WB_Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::RESTRICTED_NEXT_INSN_SET.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(AARCH64_MISC::CPYFPRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(
            CPYFPRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn::from(bits),
        ))
    }
}
impl InsnOpcode for CPYFPRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CPYFPRT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cpyfprt",
        aliases: &[],
        opcode: 0x19002400,
        mask: 0xffe0fc00,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::MOPS,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_WB_Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::RESTRICTED_NEXT_INSN_SET.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(AARCH64_MISC::CPYFPRT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(
            CPYFPRT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn::from(bits),
        ))
    }
}
impl InsnOpcode for CPYFPRT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CPYFPRTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cpyfprtn",
        aliases: &[],
        opcode: 0x1900e400,
        mask: 0xffe0fc00,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::MOPS,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_WB_Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::RESTRICTED_NEXT_INSN_SET.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(AARCH64_MISC::CPYFPRTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(
            CPYFPRTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn::from(bits),
        ))
    }
}
impl InsnOpcode for CPYFPRTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CPYFPRTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cpyfprtrn",
        aliases: &[],
        opcode: 0x1900a400,
        mask: 0xffe0fc00,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::MOPS,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_WB_Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::RESTRICTED_NEXT_INSN_SET.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(
            AARCH64_MISC::CPYFPRTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(
                CPYFPRTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn::from(bits),
            ),
        )
    }
}
impl InsnOpcode for CPYFPRTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CPYFPRTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cpyfprtwn",
        aliases: &[],
        opcode: 0x19006400,
        mask: 0xffe0fc00,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::MOPS,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_WB_Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::RESTRICTED_NEXT_INSN_SET.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(
            AARCH64_MISC::CPYFPRTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(
                CPYFPRTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn::from(bits),
            ),
        )
    }
}
impl InsnOpcode for CPYFPRTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CPYFPT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cpyfpt",
        aliases: &[],
        opcode: 0x19003400,
        mask: 0xffe0fc00,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::MOPS,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_WB_Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::RESTRICTED_NEXT_INSN_SET.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(AARCH64_MISC::CPYFPT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(
            CPYFPT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn::from(bits),
        ))
    }
}
impl InsnOpcode for CPYFPT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CPYFPTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cpyfptn",
        aliases: &[],
        opcode: 0x1900f400,
        mask: 0xffe0fc00,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::MOPS,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_WB_Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::RESTRICTED_NEXT_INSN_SET.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(AARCH64_MISC::CPYFPTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(
            CPYFPTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn::from(bits),
        ))
    }
}
impl InsnOpcode for CPYFPTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CPYFPTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cpyfptrn",
        aliases: &[],
        opcode: 0x1900b400,
        mask: 0xffe0fc00,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::MOPS,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_WB_Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::RESTRICTED_NEXT_INSN_SET.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(AARCH64_MISC::CPYFPTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(
            CPYFPTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn::from(bits),
        ))
    }
}
impl InsnOpcode for CPYFPTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CPYFPTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cpyfptwn",
        aliases: &[],
        opcode: 0x19007400,
        mask: 0xffe0fc00,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::MOPS,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_WB_Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::RESTRICTED_NEXT_INSN_SET.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(AARCH64_MISC::CPYFPTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(
            CPYFPTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn::from(bits),
        ))
    }
}
impl InsnOpcode for CPYFPTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CPYFPWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cpyfpwn",
        aliases: &[],
        opcode: 0x19004400,
        mask: 0xffe0fc00,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::MOPS,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_WB_Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::RESTRICTED_NEXT_INSN_SET.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(AARCH64_MISC::CPYFPWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(
            CPYFPWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn::from(bits),
        ))
    }
}
impl InsnOpcode for CPYFPWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CPYFPWT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cpyfpwt",
        aliases: &[],
        opcode: 0x19001400,
        mask: 0xffe0fc00,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::MOPS,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_WB_Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::RESTRICTED_NEXT_INSN_SET.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(AARCH64_MISC::CPYFPWT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(
            CPYFPWT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn::from(bits),
        ))
    }
}
impl InsnOpcode for CPYFPWT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CPYFPWTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cpyfpwtn",
        aliases: &[],
        opcode: 0x1900d400,
        mask: 0xffe0fc00,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::MOPS,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_WB_Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::RESTRICTED_NEXT_INSN_SET.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(AARCH64_MISC::CPYFPWTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(
            CPYFPWTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn::from(bits),
        ))
    }
}
impl InsnOpcode for CPYFPWTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CPYFPWTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cpyfpwtrn",
        aliases: &[],
        opcode: 0x19009400,
        mask: 0xffe0fc00,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::MOPS,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_WB_Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::RESTRICTED_NEXT_INSN_SET.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(
            AARCH64_MISC::CPYFPWTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(
                CPYFPWTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn::from(bits),
            ),
        )
    }
}
impl InsnOpcode for CPYFPWTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CPYFPWTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cpyfpwtwn",
        aliases: &[],
        opcode: 0x19005400,
        mask: 0xffe0fc00,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::MOPS,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_WB_Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::RESTRICTED_NEXT_INSN_SET.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(
            AARCH64_MISC::CPYFPWTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(
                CPYFPWTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn::from(bits),
            ),
        )
    }
}
impl InsnOpcode for CPYFPWTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CPYM_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cpym",
        aliases: &[],
        opcode: 0x1d400400,
        mask: 0xffe0fc00,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::MOPS,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_WB_Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(AARCH64_MISC::CPYM_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(
            CPYM_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn::from(bits),
        ))
    }
}
impl InsnOpcode for CPYM_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CPYMN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cpymn",
        aliases: &[],
        opcode: 0x1d40c400,
        mask: 0xffe0fc00,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::MOPS,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_WB_Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(AARCH64_MISC::CPYMN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(
            CPYMN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn::from(bits),
        ))
    }
}
impl InsnOpcode for CPYMN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CPYMRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cpymrn",
        aliases: &[],
        opcode: 0x1d408400,
        mask: 0xffe0fc00,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::MOPS,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_WB_Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(AARCH64_MISC::CPYMRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(
            CPYMRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn::from(bits),
        ))
    }
}
impl InsnOpcode for CPYMRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CPYMRT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cpymrt",
        aliases: &[],
        opcode: 0x1d402400,
        mask: 0xffe0fc00,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::MOPS,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_WB_Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(AARCH64_MISC::CPYMRT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(
            CPYMRT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn::from(bits),
        ))
    }
}
impl InsnOpcode for CPYMRT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CPYMRTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cpymrtn",
        aliases: &[],
        opcode: 0x1d40e400,
        mask: 0xffe0fc00,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::MOPS,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_WB_Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(AARCH64_MISC::CPYMRTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(
            CPYMRTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn::from(bits),
        ))
    }
}
impl InsnOpcode for CPYMRTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CPYMRTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cpymrtrn",
        aliases: &[],
        opcode: 0x1d40a400,
        mask: 0xffe0fc00,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::MOPS,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_WB_Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(AARCH64_MISC::CPYMRTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(
            CPYMRTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn::from(bits),
        ))
    }
}
impl InsnOpcode for CPYMRTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CPYMRTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cpymrtwn",
        aliases: &[],
        opcode: 0x1d406400,
        mask: 0xffe0fc00,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::MOPS,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_WB_Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(AARCH64_MISC::CPYMRTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(
            CPYMRTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn::from(bits),
        ))
    }
}
impl InsnOpcode for CPYMRTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CPYMT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cpymt",
        aliases: &[],
        opcode: 0x1d403400,
        mask: 0xffe0fc00,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::MOPS,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_WB_Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(AARCH64_MISC::CPYMT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(
            CPYMT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn::from(bits),
        ))
    }
}
impl InsnOpcode for CPYMT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CPYMTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cpymtn",
        aliases: &[],
        opcode: 0x1d40f400,
        mask: 0xffe0fc00,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::MOPS,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_WB_Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(AARCH64_MISC::CPYMTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(
            CPYMTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn::from(bits),
        ))
    }
}
impl InsnOpcode for CPYMTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CPYMTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cpymtrn",
        aliases: &[],
        opcode: 0x1d40b400,
        mask: 0xffe0fc00,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::MOPS,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_WB_Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(AARCH64_MISC::CPYMTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(
            CPYMTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn::from(bits),
        ))
    }
}
impl InsnOpcode for CPYMTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CPYMTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cpymtwn",
        aliases: &[],
        opcode: 0x1d407400,
        mask: 0xffe0fc00,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::MOPS,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_WB_Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(AARCH64_MISC::CPYMTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(
            CPYMTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn::from(bits),
        ))
    }
}
impl InsnOpcode for CPYMTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CPYMWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cpymwn",
        aliases: &[],
        opcode: 0x1d404400,
        mask: 0xffe0fc00,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::MOPS,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_WB_Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(AARCH64_MISC::CPYMWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(
            CPYMWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn::from(bits),
        ))
    }
}
impl InsnOpcode for CPYMWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CPYMWT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cpymwt",
        aliases: &[],
        opcode: 0x1d401400,
        mask: 0xffe0fc00,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::MOPS,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_WB_Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(AARCH64_MISC::CPYMWT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(
            CPYMWT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn::from(bits),
        ))
    }
}
impl InsnOpcode for CPYMWT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CPYMWTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cpymwtn",
        aliases: &[],
        opcode: 0x1d40d400,
        mask: 0xffe0fc00,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::MOPS,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_WB_Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(AARCH64_MISC::CPYMWTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(
            CPYMWTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn::from(bits),
        ))
    }
}
impl InsnOpcode for CPYMWTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CPYMWTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cpymwtrn",
        aliases: &[],
        opcode: 0x1d409400,
        mask: 0xffe0fc00,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::MOPS,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_WB_Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(AARCH64_MISC::CPYMWTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(
            CPYMWTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn::from(bits),
        ))
    }
}
impl InsnOpcode for CPYMWTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CPYMWTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cpymwtwn",
        aliases: &[],
        opcode: 0x1d405400,
        mask: 0xffe0fc00,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::MOPS,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_WB_Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(AARCH64_MISC::CPYMWTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(
            CPYMWTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn::from(bits),
        ))
    }
}
impl InsnOpcode for CPYMWTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CPYP_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cpyp",
        aliases: &[],
        opcode: 0x1d000400,
        mask: 0xffe0fc00,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::MOPS,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_WB_Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::RESTRICTED_NEXT_INSN_SET.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(AARCH64_MISC::CPYP_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(
            CPYP_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn::from(bits),
        ))
    }
}
impl InsnOpcode for CPYP_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CPYPN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cpypn",
        aliases: &[],
        opcode: 0x1d00c400,
        mask: 0xffe0fc00,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::MOPS,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_WB_Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::RESTRICTED_NEXT_INSN_SET.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(AARCH64_MISC::CPYPN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(
            CPYPN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn::from(bits),
        ))
    }
}
impl InsnOpcode for CPYPN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CPYPRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cpyprn",
        aliases: &[],
        opcode: 0x1d008400,
        mask: 0xffe0fc00,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::MOPS,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_WB_Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::RESTRICTED_NEXT_INSN_SET.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(AARCH64_MISC::CPYPRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(
            CPYPRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn::from(bits),
        ))
    }
}
impl InsnOpcode for CPYPRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CPYPRT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cpyprt",
        aliases: &[],
        opcode: 0x1d002400,
        mask: 0xffe0fc00,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::MOPS,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_WB_Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::RESTRICTED_NEXT_INSN_SET.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(AARCH64_MISC::CPYPRT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(
            CPYPRT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn::from(bits),
        ))
    }
}
impl InsnOpcode for CPYPRT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CPYPRTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cpyprtn",
        aliases: &[],
        opcode: 0x1d00e400,
        mask: 0xffe0fc00,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::MOPS,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_WB_Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::RESTRICTED_NEXT_INSN_SET.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(AARCH64_MISC::CPYPRTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(
            CPYPRTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn::from(bits),
        ))
    }
}
impl InsnOpcode for CPYPRTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CPYPRTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cpyprtrn",
        aliases: &[],
        opcode: 0x1d00a400,
        mask: 0xffe0fc00,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::MOPS,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_WB_Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::RESTRICTED_NEXT_INSN_SET.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(AARCH64_MISC::CPYPRTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(
            CPYPRTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn::from(bits),
        ))
    }
}
impl InsnOpcode for CPYPRTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CPYPRTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cpyprtwn",
        aliases: &[],
        opcode: 0x1d006400,
        mask: 0xffe0fc00,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::MOPS,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_WB_Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::RESTRICTED_NEXT_INSN_SET.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(AARCH64_MISC::CPYPRTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(
            CPYPRTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn::from(bits),
        ))
    }
}
impl InsnOpcode for CPYPRTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CPYPT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cpypt",
        aliases: &[],
        opcode: 0x1d003400,
        mask: 0xffe0fc00,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::MOPS,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_WB_Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::RESTRICTED_NEXT_INSN_SET.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(AARCH64_MISC::CPYPT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(
            CPYPT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn::from(bits),
        ))
    }
}
impl InsnOpcode for CPYPT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CPYPTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cpyptn",
        aliases: &[],
        opcode: 0x1d00f400,
        mask: 0xffe0fc00,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::MOPS,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_WB_Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::RESTRICTED_NEXT_INSN_SET.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(AARCH64_MISC::CPYPTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(
            CPYPTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn::from(bits),
        ))
    }
}
impl InsnOpcode for CPYPTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CPYPTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cpyptrn",
        aliases: &[],
        opcode: 0x1d00b400,
        mask: 0xffe0fc00,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::MOPS,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_WB_Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::RESTRICTED_NEXT_INSN_SET.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(AARCH64_MISC::CPYPTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(
            CPYPTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn::from(bits),
        ))
    }
}
impl InsnOpcode for CPYPTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CPYPTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cpyptwn",
        aliases: &[],
        opcode: 0x1d007400,
        mask: 0xffe0fc00,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::MOPS,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_WB_Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::RESTRICTED_NEXT_INSN_SET.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(AARCH64_MISC::CPYPTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(
            CPYPTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn::from(bits),
        ))
    }
}
impl InsnOpcode for CPYPTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CPYPWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cpypwn",
        aliases: &[],
        opcode: 0x1d004400,
        mask: 0xffe0fc00,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::MOPS,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_WB_Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::RESTRICTED_NEXT_INSN_SET.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(AARCH64_MISC::CPYPWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(
            CPYPWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn::from(bits),
        ))
    }
}
impl InsnOpcode for CPYPWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CPYPWT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cpypwt",
        aliases: &[],
        opcode: 0x1d001400,
        mask: 0xffe0fc00,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::MOPS,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_WB_Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::RESTRICTED_NEXT_INSN_SET.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(AARCH64_MISC::CPYPWT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(
            CPYPWT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn::from(bits),
        ))
    }
}
impl InsnOpcode for CPYPWT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CPYPWTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cpypwtn",
        aliases: &[],
        opcode: 0x1d00d400,
        mask: 0xffe0fc00,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::MOPS,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_WB_Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::RESTRICTED_NEXT_INSN_SET.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(AARCH64_MISC::CPYPWTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(
            CPYPWTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn::from(bits),
        ))
    }
}
impl InsnOpcode for CPYPWTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CPYPWTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cpypwtrn",
        aliases: &[],
        opcode: 0x1d009400,
        mask: 0xffe0fc00,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::MOPS,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_WB_Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::RESTRICTED_NEXT_INSN_SET.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(AARCH64_MISC::CPYPWTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(
            CPYPWTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn::from(bits),
        ))
    }
}
impl InsnOpcode for CPYPWTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CPYPWTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "cpypwtwn",
        aliases: &[],
        opcode: 0x1d005400,
        mask: 0xffe0fc00,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::MOPS,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_WB_Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::RESTRICTED_NEXT_INSN_SET.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(AARCH64_MISC::CPYPWTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(
            CPYPWTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn::from(bits),
        ))
    }
}
impl InsnOpcode for CPYPWTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CRC32B_Rd_Rn_Rm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "crc32b",
        aliases: &[],
        opcode: 0x1ac04000,
        mask: 0xffe0fc00,
        class: InsnClass::DP_2SRC,
        feature_set: InsnFeatureSet::CRC,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rm,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::DP_2SRC(DP_2SRC::CRC32B_Rd_Rn_Rm(CRC32B_Rd_Rn_Rm::from(bits)))
    }
}
impl InsnOpcode for CRC32B_Rd_Rn_Rm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CRC32CB_Rd_Rn_Rm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "crc32cb",
        aliases: &[],
        opcode: 0x1ac05000,
        mask: 0xffe0fc00,
        class: InsnClass::DP_2SRC,
        feature_set: InsnFeatureSet::CRC,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rm,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::DP_2SRC(DP_2SRC::CRC32CB_Rd_Rn_Rm(CRC32CB_Rd_Rn_Rm::from(bits)))
    }
}
impl InsnOpcode for CRC32CB_Rd_Rn_Rm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CRC32CH_Rd_Rn_Rm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "crc32ch",
        aliases: &[],
        opcode: 0x1ac05400,
        mask: 0xffe0fc00,
        class: InsnClass::DP_2SRC,
        feature_set: InsnFeatureSet::CRC,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rm,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::DP_2SRC(DP_2SRC::CRC32CH_Rd_Rn_Rm(CRC32CH_Rd_Rn_Rm::from(bits)))
    }
}
impl InsnOpcode for CRC32CH_Rd_Rn_Rm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CRC32CW_Rd_Rn_Rm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "crc32cw",
        aliases: &[],
        opcode: 0x1ac05800,
        mask: 0xffe0fc00,
        class: InsnClass::DP_2SRC,
        feature_set: InsnFeatureSet::CRC,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rm,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::DP_2SRC(DP_2SRC::CRC32CW_Rd_Rn_Rm(CRC32CW_Rd_Rn_Rm::from(bits)))
    }
}
impl InsnOpcode for CRC32CW_Rd_Rn_Rm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CRC32CX_Rd_Rn_Rm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "crc32cx",
        aliases: &[],
        opcode: 0x9ac05c00,
        mask: 0xffe0fc00,
        class: InsnClass::DP_2SRC,
        feature_set: InsnFeatureSet::CRC,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rm,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::DP_2SRC(DP_2SRC::CRC32CX_Rd_Rn_Rm(CRC32CX_Rd_Rn_Rm::from(bits)))
    }
}
impl InsnOpcode for CRC32CX_Rd_Rn_Rm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CRC32H_Rd_Rn_Rm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "crc32h",
        aliases: &[],
        opcode: 0x1ac04400,
        mask: 0xffe0fc00,
        class: InsnClass::DP_2SRC,
        feature_set: InsnFeatureSet::CRC,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rm,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::DP_2SRC(DP_2SRC::CRC32H_Rd_Rn_Rm(CRC32H_Rd_Rn_Rm::from(bits)))
    }
}
impl InsnOpcode for CRC32H_Rd_Rn_Rm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CRC32W_Rd_Rn_Rm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "crc32w",
        aliases: &[],
        opcode: 0x1ac04800,
        mask: 0xffe0fc00,
        class: InsnClass::DP_2SRC,
        feature_set: InsnFeatureSet::CRC,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rm,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::DP_2SRC(DP_2SRC::CRC32W_Rd_Rn_Rm(CRC32W_Rd_Rn_Rm::from(bits)))
    }
}
impl InsnOpcode for CRC32W_Rd_Rn_Rm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CRC32X_Rd_Rn_Rm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "crc32x",
        aliases: &[],
        opcode: 0x9ac04c00,
        mask: 0xffe0fc00,
        class: InsnClass::DP_2SRC,
        feature_set: InsnFeatureSet::CRC,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rm,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::DP_2SRC(DP_2SRC::CRC32X_Rd_Rn_Rm(CRC32X_Rd_Rn_Rm::from(bits)))
    }
}
impl InsnOpcode for CRC32X_Rd_Rn_Rm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CSEL_Rd_Rn_Rm_COND {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "csel",
        aliases: &[],
        opcode: 0x1a800000,
        mask: 0x7fe00c00,
        class: InsnClass::CONDSEL,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rm,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::COND,
                class: InsnOperandClass::COND,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SF_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::CONDSEL(CONDSEL::CSEL_Rd_Rn_Rm_COND(CSEL_Rd_Rn_Rm_COND::from(bits)))
    }
}
impl InsnOpcode for CSEL_Rd_Rn_Rm_COND {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CSINC_Rd_Rn_Rm_COND {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "csinc",
        aliases: &[],
        opcode: 0x1a800400,
        mask: 0x7fe00c00,
        class: InsnClass::CONDSEL,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rm,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::COND,
                class: InsnOperandClass::COND,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_ALIAS.bits() | InsnFlags::HAS_SF_FIELD.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::CONDSEL(CONDSEL::CSINC_Rd_Rn_Rm_COND(CSINC_Rd_Rn_Rm_COND::from(
            bits,
        )))
    }
}
impl InsnOpcode for CSINC_Rd_Rn_Rm_COND {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CSINV_Rd_Rn_Rm_COND {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "csinv",
        aliases: &[],
        opcode: 0x5a800000,
        mask: 0x7fe00c00,
        class: InsnClass::CONDSEL,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rm,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::COND,
                class: InsnOperandClass::COND,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_ALIAS.bits() | InsnFlags::HAS_SF_FIELD.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::CONDSEL(CONDSEL::CSINV_Rd_Rn_Rm_COND(CSINV_Rd_Rn_Rm_COND::from(
            bits,
        )))
    }
}
impl InsnOpcode for CSINV_Rd_Rn_Rm_COND {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CSNEG_Rd_Rn_Rm_COND {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "csneg",
        aliases: &[],
        opcode: 0x5a800400,
        mask: 0x7fe00c00,
        class: InsnClass::CONDSEL,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rm,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::COND,
                class: InsnOperandClass::COND,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_ALIAS.bits() | InsnFlags::HAS_SF_FIELD.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::CONDSEL(CONDSEL::CSNEG_Rd_Rn_Rm_COND(CSNEG_Rd_Rn_Rm_COND::from(
            bits,
        )))
    }
}
impl InsnOpcode for CSNEG_Rd_Rn_Rm_COND {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CTERMEQ_Rn_Rm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ctermeq",
        aliases: &[],
        opcode: 0x25a02000,
        mask: 0xffa0fc1f,
        class: InsnClass::SVE_SIZE_SD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rm,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_SD(SVE_SIZE_SD::CTERMEQ_Rn_Rm(CTERMEQ_Rn_Rm::from(bits)))
    }
}
impl InsnOpcode for CTERMEQ_Rn_Rm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CTERMNE_Rn_Rm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ctermne",
        aliases: &[],
        opcode: 0x25a02010,
        mask: 0xffa0fc1f,
        class: InsnClass::SVE_SIZE_SD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rm,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_SD(SVE_SIZE_SD::CTERMNE_Rn_Rm(CTERMNE_Rn_Rm::from(bits)))
    }
}
impl InsnOpcode for CTERMNE_Rn_Rm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl CTZ_Rd_Rn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ctz",
        aliases: &[],
        opcode: 0x5ac01800,
        mask: 0x7ffffc00,
        class: InsnClass::CSSC,
        feature_set: InsnFeatureSet::CSSC,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SF_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::CSSC(CSSC::CTZ_Rd_Rn(CTZ_Rd_Rn::from(bits)))
    }
}
impl InsnOpcode for CTZ_Rd_Rn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl DCPS1_EXCEPTION {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "dcps1",
        aliases: &[],
        opcode: 0xd4a00001,
        mask: 0xffe0001f,
        class: InsnClass::EXCEPTION,
        feature_set: InsnFeatureSet::V8,
        operands: &[InsnOperand {
            kind: InsnOperandKind::EXCEPTION,
            class: InsnOperandClass::IMMEDIATE,
            qualifiers: &[],
            bit_fields: &[BitfieldSpec {
                bitfield: InsnBitField::imm16_5,
                lsb: 5,
                width: 16,
            }],
        }],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::EXCEPTION(EXCEPTION::DCPS1_EXCEPTION(DCPS1_EXCEPTION::from(bits)))
    }
}
impl InsnOpcode for DCPS1_EXCEPTION {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl DCPS2_EXCEPTION {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "dcps2",
        aliases: &[],
        opcode: 0xd4a00002,
        mask: 0xffe0001f,
        class: InsnClass::EXCEPTION,
        feature_set: InsnFeatureSet::V8,
        operands: &[InsnOperand {
            kind: InsnOperandKind::EXCEPTION,
            class: InsnOperandClass::IMMEDIATE,
            qualifiers: &[],
            bit_fields: &[BitfieldSpec {
                bitfield: InsnBitField::imm16_5,
                lsb: 5,
                width: 16,
            }],
        }],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::EXCEPTION(EXCEPTION::DCPS2_EXCEPTION(DCPS2_EXCEPTION::from(bits)))
    }
}
impl InsnOpcode for DCPS2_EXCEPTION {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl DCPS3_EXCEPTION {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "dcps3",
        aliases: &[],
        opcode: 0xd4a00003,
        mask: 0xffe0001f,
        class: InsnClass::EXCEPTION,
        feature_set: InsnFeatureSet::V8,
        operands: &[InsnOperand {
            kind: InsnOperandKind::EXCEPTION,
            class: InsnOperandClass::IMMEDIATE,
            qualifiers: &[],
            bit_fields: &[BitfieldSpec {
                bitfield: InsnBitField::imm16_5,
                lsb: 5,
                width: 16,
            }],
        }],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::EXCEPTION(EXCEPTION::DCPS3_EXCEPTION(DCPS3_EXCEPTION::from(bits)))
    }
}
impl InsnOpcode for DCPS3_EXCEPTION {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl DECB_Rd_SVE_PATTERN_SCALED {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "decb",
        aliases: &[],
        opcode: 0x430e400,
        mask: 0xfff0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_PATTERN_SCALED,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_pattern,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::DECB_Rd_SVE_PATTERN_SCALED(
            DECB_Rd_SVE_PATTERN_SCALED::from(bits),
        ))
    }
}
impl InsnOpcode for DECB_Rd_SVE_PATTERN_SCALED {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl DECD_SVE_Zd_SVE_PATTERN_SCALED {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "decd",
        aliases: &[],
        opcode: 0x4f0c400,
        mask: 0xfff0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_PATTERN_SCALED,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_pattern,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::DECD_SVE_Zd_SVE_PATTERN_SCALED(
            DECD_SVE_Zd_SVE_PATTERN_SCALED::from(bits),
        ))
    }
}
impl InsnOpcode for DECD_SVE_Zd_SVE_PATTERN_SCALED {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl DECD_Rd_SVE_PATTERN_SCALED {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "decd",
        aliases: &[],
        opcode: 0x4f0e400,
        mask: 0xfff0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_PATTERN_SCALED,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_pattern,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::DECD_Rd_SVE_PATTERN_SCALED(
            DECD_Rd_SVE_PATTERN_SCALED::from(bits),
        ))
    }
}
impl InsnOpcode for DECD_Rd_SVE_PATTERN_SCALED {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl DECH_SVE_Zd_SVE_PATTERN_SCALED {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "dech",
        aliases: &[],
        opcode: 0x470c400,
        mask: 0xfff0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_PATTERN_SCALED,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_pattern,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::DECH_SVE_Zd_SVE_PATTERN_SCALED(
            DECH_SVE_Zd_SVE_PATTERN_SCALED::from(bits),
        ))
    }
}
impl InsnOpcode for DECH_SVE_Zd_SVE_PATTERN_SCALED {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl DECH_Rd_SVE_PATTERN_SCALED {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "dech",
        aliases: &[],
        opcode: 0x470e400,
        mask: 0xfff0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_PATTERN_SCALED,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_pattern,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::DECH_Rd_SVE_PATTERN_SCALED(
            DECH_Rd_SVE_PATTERN_SCALED::from(bits),
        ))
    }
}
impl InsnOpcode for DECH_Rd_SVE_PATTERN_SCALED {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl DECP_SVE_Zd_SVE_Pg4_5 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "decp",
        aliases: &[],
        opcode: 0x252d8000,
        mask: 0xff3ffe00,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg4_5,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg4_5,
                    lsb: 5,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::DECP_SVE_Zd_SVE_Pg4_5(
            DECP_SVE_Zd_SVE_Pg4_5::from(bits),
        ))
    }
}
impl InsnOpcode for DECP_SVE_Zd_SVE_Pg4_5 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl DECP_Rd_SVE_Pg4_5 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "decp",
        aliases: &[],
        opcode: 0x252d8800,
        mask: 0xff3ffe00,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg4_5,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg4_5,
                    lsb: 5,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::DECP_Rd_SVE_Pg4_5(DECP_Rd_SVE_Pg4_5::from(
            bits,
        )))
    }
}
impl InsnOpcode for DECP_Rd_SVE_Pg4_5 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl DECW_SVE_Zd_SVE_PATTERN_SCALED {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "decw",
        aliases: &[],
        opcode: 0x4b0c400,
        mask: 0xfff0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_PATTERN_SCALED,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_pattern,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::DECW_SVE_Zd_SVE_PATTERN_SCALED(
            DECW_SVE_Zd_SVE_PATTERN_SCALED::from(bits),
        ))
    }
}
impl InsnOpcode for DECW_SVE_Zd_SVE_PATTERN_SCALED {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl DECW_Rd_SVE_PATTERN_SCALED {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "decw",
        aliases: &[],
        opcode: 0x4b0e400,
        mask: 0xfff0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_PATTERN_SCALED,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_pattern,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::DECW_Rd_SVE_PATTERN_SCALED(
            DECW_Rd_SVE_PATTERN_SCALED::from(bits),
        ))
    }
}
impl InsnOpcode for DECW_Rd_SVE_PATTERN_SCALED {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl DGH {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "dgh",
        aliases: &[],
        opcode: 0xd50320df,
        mask: 0xffffffff,
        class: InsnClass::IC_SYSTEM,
        feature_set: InsnFeatureSet::V8,
        operands: &[],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::IC_SYSTEM(IC_SYSTEM::DGH(DGH::from(bits)))
    }
}
impl InsnOpcode for DGH {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl DMB_BARRIER {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "dmb",
        aliases: &[],
        opcode: 0xd50330bf,
        mask: 0xfffff0ff,
        class: InsnClass::IC_SYSTEM,
        feature_set: InsnFeatureSet::V8,
        operands: &[InsnOperand {
            kind: InsnOperandKind::BARRIER,
            class: InsnOperandClass::SYSTEM,
            qualifiers: &[],
            bit_fields: &[],
        }],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::IC_SYSTEM(IC_SYSTEM::DMB_BARRIER(DMB_BARRIER::from(bits)))
    }
}
impl InsnOpcode for DMB_BARRIER {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl DRPS {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "drps",
        aliases: &[],
        opcode: 0xd6bf03e0,
        mask: 0xffffffff,
        class: InsnClass::BRANCH_REG,
        feature_set: InsnFeatureSet::V8,
        operands: &[],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::BRANCH_REG(BRANCH_REG::DRPS(DRPS::from(bits)))
    }
}
impl InsnOpcode for DRPS {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl DSB_BARRIER_DSB_NXS {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "dsb",
        aliases: &[],
        opcode: 0xd503323f,
        mask: 0xfffff3ff,
        class: InsnClass::IC_SYSTEM,
        feature_set: InsnFeatureSet::XS,
        operands: &[InsnOperand {
            kind: InsnOperandKind::BARRIER_DSB_NXS,
            class: InsnOperandClass::SYSTEM,
            qualifiers: &[],
            bit_fields: &[],
        }],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ALIAS.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::IC_SYSTEM(IC_SYSTEM::DSB_BARRIER_DSB_NXS(DSB_BARRIER_DSB_NXS::from(
            bits,
        )))
    }
}
impl InsnOpcode for DSB_BARRIER_DSB_NXS {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl DSB_BARRIER {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "dsb",
        aliases: &[],
        opcode: 0xd503309f,
        mask: 0xfffff0ff,
        class: InsnClass::IC_SYSTEM,
        feature_set: InsnFeatureSet::V8,
        operands: &[InsnOperand {
            kind: InsnOperandKind::BARRIER,
            class: InsnOperandClass::SYSTEM,
            qualifiers: &[],
            bit_fields: &[],
        }],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ALIAS.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::IC_SYSTEM(IC_SYSTEM::DSB_BARRIER(DSB_BARRIER::from(bits)))
    }
}
impl InsnOpcode for DSB_BARRIER {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl DUP_SVE_Zd_SVE_Zn_INDEX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "dup",
        aliases: &[],
        opcode: 0x5202000,
        mask: 0xff20fc00,
        class: InsnClass::SVE_INDEX,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn_INDEX,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ALIAS.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_INDEX(SVE_INDEX::DUP_SVE_Zd_SVE_Zn_INDEX(
            DUP_SVE_Zd_SVE_Zn_INDEX::from(bits),
        ))
    }
}
impl InsnOpcode for DUP_SVE_Zd_SVE_Zn_INDEX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl DUP_SVE_Zd_Rn_SP {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "dup",
        aliases: &[],
        opcode: 0x5203800,
        mask: 0xff3ffc00,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn_SP,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ALIAS.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::DUP_SVE_Zd_Rn_SP(DUP_SVE_Zd_Rn_SP::from(
            bits,
        )))
    }
}
impl InsnOpcode for DUP_SVE_Zd_Rn_SP {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl DUP_SVE_Zd_SVE_ASIMM {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "dup",
        aliases: &[],
        opcode: 0x2538c000,
        mask: 0xff3fc000,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ASIMM,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_imm9,
                    lsb: 5,
                    width: 9,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ALIAS.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::DUP_SVE_Zd_SVE_ASIMM(
            DUP_SVE_Zd_SVE_ASIMM::from(bits),
        ))
    }
}
impl InsnOpcode for DUP_SVE_Zd_SVE_ASIMM {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl DUP_Vd_En {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "dup",
        aliases: &[],
        opcode: 0xe000400,
        mask: 0xbfe0fc00,
        class: InsnClass::ASIMDINS,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::En,
                class: InsnOperandClass::SIMD_ELEMENT,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMV_VEC_IN_Q.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDINS(ASIMDINS::DUP_Vd_En(DUP_Vd_En::from(bits)))
    }
}
impl InsnOpcode for DUP_Vd_En {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl DUP_Vd_Rn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "dup",
        aliases: &[],
        opcode: 0xe000c00,
        mask: 0xbfe0fc00,
        class: InsnClass::ASIMDINS,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMV_VEC_IN_Q.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDINS(ASIMDINS::DUP_Vd_Rn(DUP_Vd_Rn::from(bits)))
    }
}
impl InsnOpcode for DUP_Vd_Rn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl DUP_Sd_En {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "dup",
        aliases: &[],
        opcode: 0x5e000400,
        mask: 0xffe0fc00,
        class: InsnClass::ASISDONE,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::En,
                class: InsnOperandClass::SIMD_ELEMENT,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ALIAS.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDONE(ASISDONE::DUP_Sd_En(DUP_Sd_En::from(bits)))
    }
}
impl InsnOpcode for DUP_Sd_En {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl DUPM_SVE_Zd_SVE_LIMM {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "dupm",
        aliases: &[],
        opcode: 0x5c00000,
        mask: 0xfffc0000,
        class: InsnClass::SVE_LIMM,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_LIMM,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_N,
                        lsb: 17,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_immr,
                        lsb: 11,
                        width: 6,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_imms,
                        lsb: 5,
                        width: 6,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ALIAS.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_LIMM(SVE_LIMM::DUPM_SVE_Zd_SVE_LIMM(DUPM_SVE_Zd_SVE_LIMM::from(
            bits,
        )))
    }
}
impl InsnOpcode for DUPM_SVE_Zd_SVE_LIMM {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl DUPQ_SVE_Zd_SVE_Zn_5_INDEX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "dupq",
        aliases: &[],
        opcode: 0x5202400,
        mask: 0xffe0fc00,
        class: InsnClass::SVE_INDEX1,
        feature_set: InsnFeatureSet::SVE2P1,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn_5_INDEX,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_i2h,
                        lsb: 20,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_tsz,
                        lsb: 16,
                        width: 4,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_INDEX1(SVE_INDEX1::DUPQ_SVE_Zd_SVE_Zn_5_INDEX(
            DUPQ_SVE_Zd_SVE_Zn_5_INDEX::from(bits),
        ))
    }
}
impl InsnOpcode for DUPQ_SVE_Zd_SVE_Zn_5_INDEX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl EON_Rd_Rn_Rm_SFT {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "eon",
        aliases: &[],
        opcode: 0x4a200000,
        mask: 0x7f200000,
        class: InsnClass::LOG_SHIFT,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rm_SFT,
                class: InsnOperandClass::MODIFIED_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SF_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LOG_SHIFT(LOG_SHIFT::EON_Rd_Rn_Rm_SFT(EON_Rd_Rn_Rm_SFT::from(bits)))
    }
}
impl InsnOpcode for EON_Rd_Rn_Rm_SFT {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl EOR_Rd_SP_Rn_LIMM {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "eor",
        aliases: &[],
        opcode: 0x52000000,
        mask: 0x7f800000,
        class: InsnClass::LOG_IMM,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd_SP,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::LIMM,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::N,
                        lsb: 22,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::immr,
                        lsb: 16,
                        width: 6,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imms,
                        lsb: 10,
                        width: 6,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SF_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LOG_IMM(LOG_IMM::EOR_Rd_SP_Rn_LIMM(EOR_Rd_SP_Rn_LIMM::from(bits)))
    }
}
impl InsnOpcode for EOR_Rd_SP_Rn_LIMM {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl EOR_Rd_Rn_Rm_SFT {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "eor",
        aliases: &[],
        opcode: 0x4a000000,
        mask: 0x7f200000,
        class: InsnClass::LOG_SHIFT,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rm_SFT,
                class: InsnOperandClass::MODIFIED_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SF_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LOG_SHIFT(LOG_SHIFT::EOR_Rd_Rn_Rm_SFT(EOR_Rd_Rn_Rm_SFT::from(bits)))
    }
}
impl InsnOpcode for EOR_Rd_Rn_Rm_SFT {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl EOR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "eor",
        aliases: &[],
        opcode: 0x4190000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_5,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_5,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::EOR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(
            EOR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5::from(bits),
        ))
    }
}
impl InsnOpcode for EOR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl EOR_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "eor",
        aliases: &[],
        opcode: 0x4a03000,
        mask: 0xffe0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::EOR_SVE_Zd_SVE_Zn_SVE_Zm_16(
            EOR_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for EOR_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl EOR_SVE_Zd_SVE_Zd_SVE_LIMM {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "eor",
        aliases: &[],
        opcode: 0x5400000,
        mask: 0xfffc0000,
        class: InsnClass::SVE_LIMM,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_LIMM,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_N,
                        lsb: 17,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_immr,
                        lsb: 11,
                        width: 6,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_imms,
                        lsb: 5,
                        width: 6,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ALIAS.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_LIMM(SVE_LIMM::EOR_SVE_Zd_SVE_Zd_SVE_LIMM(
            EOR_SVE_Zd_SVE_Zd_SVE_LIMM::from(bits),
        ))
    }
}
impl InsnOpcode for EOR_SVE_Zd_SVE_Zd_SVE_LIMM {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl EOR_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "eor",
        aliases: &[],
        opcode: 0x25004200,
        mask: 0xfff0c210,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Pd,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pd,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg4_10,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg4_10,
                    lsb: 10,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pn,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pn,
                    lsb: 5,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pm,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pm,
                    lsb: 16,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ALIAS.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::EOR_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm(
            EOR_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm::from(bits),
        ))
    }
}
impl InsnOpcode for EOR_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl EOR_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "eor",
        aliases: &[],
        opcode: 0x2e201c00,
        mask: 0xbfe0fc00,
        class: InsnClass::ASIMDSAME,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSAME(ASIMDSAME::EOR_Vd_Vn_Vm(EOR_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for EOR_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl EOR3_SVE_Zd_SVE_Zd_SVE_Zm_16_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "eor3",
        aliases: &[],
        opcode: 0x4203800,
        mask: 0xffe0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::EOR3_SVE_Zd_SVE_Zd_SVE_Zm_16_SVE_Zn(
            EOR3_SVE_Zd_SVE_Zd_SVE_Zm_16_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for EOR3_SVE_Zd_SVE_Zd_SVE_Zm_16_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl EOR3_Vd_Vn_Vm_Va {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "eor3",
        aliases: &[],
        opcode: 0xce000000,
        mask: 0xffe08000,
        class: InsnClass::CRYPTOSHA3,
        feature_set: InsnFeatureSet::SHA3,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Va,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Ra,
                    lsb: 10,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::CRYPTOSHA3(CRYPTOSHA3::EOR3_Vd_Vn_Vm_Va(EOR3_Vd_Vn_Vm_Va::from(bits)))
    }
}
impl InsnOpcode for EOR3_Vd_Vn_Vm_Va {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl EORBT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "eorbt",
        aliases: &[],
        opcode: 0x45009000,
        mask: 0xff20fc00,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::EORBT_SVE_Zd_SVE_Zn_SVE_Zm_16(
            EORBT_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for EORBT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl EORQV_Vd_SVE_Pg3_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "eorqv",
        aliases: &[],
        opcode: 0x41d2000,
        mask: 0xff3fe000,
        class: InsnClass::SVE2_URQVS,
        feature_set: InsnFeatureSet::SVE2P1,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_16B, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE2_URQVS(SVE2_URQVS::EORQV_Vd_SVE_Pg3_SVE_Zn(
            EORQV_Vd_SVE_Pg3_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for EORQV_Vd_SVE_Pg3_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl EORS_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "eors",
        aliases: &[],
        opcode: 0x25404200,
        mask: 0xfff0c210,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Pd,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pd,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg4_10,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg4_10,
                    lsb: 10,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pn,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pn,
                    lsb: 5,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pm,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pm,
                    lsb: 16,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ALIAS.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::EORS_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm(
            EORS_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm::from(bits),
        ))
    }
}
impl InsnOpcode for EORS_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl EORTB_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "eortb",
        aliases: &[],
        opcode: 0x45009400,
        mask: 0xff20fc00,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::EORTB_SVE_Zd_SVE_Zn_SVE_Zm_16(
            EORTB_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for EORTB_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl EORV_SVE_Vd_SVE_Pg3_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "eorv",
        aliases: &[],
        opcode: 0x4192000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Vd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::EORV_SVE_Vd_SVE_Pg3_SVE_Zn(
            EORV_SVE_Vd_SVE_Pg3_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for EORV_SVE_Vd_SVE_Pg3_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ERET {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "eret",
        aliases: &[],
        opcode: 0xd69f03e0,
        mask: 0xffffffff,
        class: InsnClass::BRANCH_REG,
        feature_set: InsnFeatureSet::V8,
        operands: &[],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::BRANCH_REG(BRANCH_REG::ERET(ERET::from(bits)))
    }
}
impl InsnOpcode for ERET {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ERETAA {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "eretaa",
        aliases: &[],
        opcode: 0xd69f0bff,
        mask: 0xffffffff,
        class: InsnClass::BRANCH_REG,
        feature_set: InsnFeatureSet::PAC,
        operands: &[],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::BRANCH_REG(BRANCH_REG::ERETAA(ERETAA::from(bits)))
    }
}
impl InsnOpcode for ERETAA {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ERETAB {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "eretab",
        aliases: &[],
        opcode: 0xd69f0fff,
        mask: 0xffffffff,
        class: InsnClass::BRANCH_REG,
        feature_set: InsnFeatureSet::PAC,
        operands: &[],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::BRANCH_REG(BRANCH_REG::ERETAB(ERETAB::from(bits)))
    }
}
impl InsnOpcode for ERETAB {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl EXT_SVE_Zd_SVE_Zd_SVE_Zm_5_SVE_UIMM8_53 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ext",
        aliases: &[],
        opcode: 0x5200000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_5,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_5,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_UIMM8_53,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::imm5,
                        lsb: 16,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_10,
                        lsb: 10,
                        width: 3,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::EXT_SVE_Zd_SVE_Zd_SVE_Zm_5_SVE_UIMM8_53(
            EXT_SVE_Zd_SVE_Zd_SVE_Zm_5_SVE_UIMM8_53::from(bits),
        ))
    }
}
impl InsnOpcode for EXT_SVE_Zd_SVE_Zd_SVE_Zm_5_SVE_UIMM8_53 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl EXT_SVE_Zd_SVE_ZnxN_SVE_UIMM8_53 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ext",
        aliases: &[],
        opcode: 0x5600000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ZnxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_UIMM8_53,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::imm5,
                        lsb: 16,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_10,
                        lsb: 10,
                        width: 3,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::EXT_SVE_Zd_SVE_ZnxN_SVE_UIMM8_53(
            EXT_SVE_Zd_SVE_ZnxN_SVE_UIMM8_53::from(bits),
        ))
    }
}
impl InsnOpcode for EXT_SVE_Zd_SVE_ZnxN_SVE_UIMM8_53 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl EXT_Vd_Vn_Vm_IDX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ext",
        aliases: &[],
        opcode: 0x2e000000,
        mask: 0xbfe08400,
        class: InsnClass::ASIMDEXT,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::IDX,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[
                    InsnOperandQualifier::imm_0_7,
                    InsnOperandQualifier::imm_0_15,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::imm4_11,
                    lsb: 11,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDEXT(ASIMDEXT::EXT_Vd_Vn_Vm_IDX(EXT_Vd_Vn_Vm_IDX::from(bits)))
    }
}
impl InsnOpcode for EXT_Vd_Vn_Vm_IDX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl EXTQ_SVE_Zd_SVE_Zd_SVE_Zm_imm4 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "extq",
        aliases: &[],
        opcode: 0x5602400,
        mask: 0xfff0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE2P1,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_imm4,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zm_5,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_imm4,
                        lsb: 16,
                        width: 4,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::EXTQ_SVE_Zd_SVE_Zd_SVE_Zm_imm4(
            EXTQ_SVE_Zd_SVE_Zd_SVE_Zm_imm4::from(bits),
        ))
    }
}
impl InsnOpcode for EXTQ_SVE_Zd_SVE_Zd_SVE_Zm_imm4 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl EXTR_Rd_Rn_Rm_IMMS {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "extr",
        aliases: &[],
        opcode: 0x13800000,
        mask: 0x7fa00000,
        class: InsnClass::EXTRACT,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rm,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::IMMS,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[
                    InsnOperandQualifier::imm_0_31,
                    InsnOperandQualifier::imm_0_63,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::imm6_10,
                    lsb: 10,
                    width: 6,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_ALIAS.bits()
                | InsnFlags::HAS_N_FIELD.bits()
                | InsnFlags::HAS_SF_FIELD.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::EXTRACT(EXTRACT::EXTR_Rd_Rn_Rm_IMMS(EXTR_Rd_Rn_Rm_IMMS::from(bits)))
    }
}
impl InsnOpcode for EXTR_Rd_Rn_Rm_IMMS {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FABD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fabd",
        aliases: &[],
        opcode: 0x65088000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_5,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_5,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::FABD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(
            FABD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5::from(bits),
        ))
    }
}
impl InsnOpcode for FABD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FABD_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fabd",
        aliases: &[],
        opcode: 0x2ec01400,
        mask: 0xbfe0fc00,
        class: InsnClass::ASIMDSAME,
        feature_set: InsnFeatureSet::SIMD_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSAME(ASIMDSAME::FABD_Vd_Vn_Vm(FABD_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for FABD_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FABD_Sd_Sn_Sm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fabd",
        aliases: &[],
        opcode: 0x7ec01400,
        mask: 0xffe0fc00,
        class: InsnClass::ASISDSAME,
        feature_set: InsnFeatureSet::SIMD_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sm,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMD_SCALAR_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDSAME(ASISDSAME::FABD_Sd_Sn_Sm(FABD_Sd_Sn_Sm::from(bits)))
    }
}
impl InsnOpcode for FABD_Sd_Sn_Sm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FABD_Vd_V_2S_Vn_V_2S_Vm_V_2S {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fabd",
        aliases: &[],
        opcode: 0x2ea0d400,
        mask: 0xbfa0fc00,
        class: InsnClass::ASIMDSAME,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSAME(ASIMDSAME::FABD_Vd_V_2S_Vn_V_2S_Vm_V_2S(
            FABD_Vd_V_2S_Vn_V_2S_Vm_V_2S::from(bits),
        ))
    }
}
impl InsnOpcode for FABD_Vd_V_2S_Vn_V_2S_Vm_V_2S {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FABD_Sd_S_S_Sn_S_S_Sm_S_S {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fabd",
        aliases: &[],
        opcode: 0x7ea0d400,
        mask: 0xffa0fc00,
        class: InsnClass::ASISDSAME,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sm,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMD_SCALAR_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDSAME(ASISDSAME::FABD_Sd_S_S_Sn_S_S_Sm_S_S(
            FABD_Sd_S_S_Sn_S_S_Sm_S_S::from(bits),
        ))
    }
}
impl InsnOpcode for FABD_Sd_S_S_Sn_S_S_Sm_S_S {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FABS_SVE_Zd_SVE_Pg3_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fabs",
        aliases: &[],
        opcode: 0x41ca000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M, InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::FABS_SVE_Zd_SVE_Pg3_SVE_Zn(
            FABS_SVE_Zd_SVE_Pg3_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for FABS_SVE_Zd_SVE_Pg3_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FABS_Vd_Vn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fabs",
        aliases: &[],
        opcode: 0xea0f800,
        mask: 0xbfbffc00,
        class: InsnClass::ASIMDMISC,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDMISC(ASIMDMISC::FABS_Vd_Vn(FABS_Vd_Vn::from(bits)))
    }
}
impl InsnOpcode for FABS_Vd_Vn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FABS_Vd_V_4H_Vn_V_4H {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fabs",
        aliases: &[],
        opcode: 0xef8f800,
        mask: 0xbffffc00,
        class: InsnClass::ASIMDMISC,
        feature_set: InsnFeatureSet::SIMD_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDMISC(ASIMDMISC::FABS_Vd_V_4H_Vn_V_4H(FABS_Vd_V_4H_Vn_V_4H::from(
            bits,
        )))
    }
}
impl InsnOpcode for FABS_Vd_V_4H_Vn_V_4H {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FABS_Fd_Fn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fabs",
        aliases: &[],
        opcode: 0x1ee0c000,
        mask: 0xfffffc00,
        class: InsnClass::FLOATDP1,
        feature_set: InsnFeatureSet::FP_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Fd,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fn,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_FPTYPE_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::FLOATDP1(FLOATDP1::FABS_Fd_Fn(FABS_Fd_Fn::from(bits)))
    }
}
impl InsnOpcode for FABS_Fd_Fn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FABS_Fd_S_S_Fn_S_S {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fabs",
        aliases: &[],
        opcode: 0x1e20c000,
        mask: 0xff3ffc00,
        class: InsnClass::FLOATDP1,
        feature_set: InsnFeatureSet::FP,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Fd,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fn,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_FPTYPE_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::FLOATDP1(FLOATDP1::FABS_Fd_S_S_Fn_S_S(FABS_Fd_S_S_Fn_S_S::from(bits)))
    }
}
impl InsnOpcode for FABS_Fd_S_S_Fn_S_S {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FACGE_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "facge",
        aliases: &[],
        opcode: 0x6500c010,
        mask: 0xff20e010,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Pd,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pd,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_Z,
                    InsnOperandQualifier::P_Z,
                    InsnOperandQualifier::P_Z,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ALIAS.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::FACGE_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16(
            FACGE_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for FACGE_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FACGE_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "facge",
        aliases: &[],
        opcode: 0x2e402c00,
        mask: 0xbfe0fc00,
        class: InsnClass::ASIMDSAME,
        feature_set: InsnFeatureSet::SIMD_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSAME(ASIMDSAME::FACGE_Vd_Vn_Vm(FACGE_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for FACGE_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FACGE_Sd_Sn_Sm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "facge",
        aliases: &[],
        opcode: 0x7e402c00,
        mask: 0xffe0fc00,
        class: InsnClass::ASISDSAME,
        feature_set: InsnFeatureSet::SIMD_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sm,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMD_SCALAR_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDSAME(ASISDSAME::FACGE_Sd_Sn_Sm(FACGE_Sd_Sn_Sm::from(bits)))
    }
}
impl InsnOpcode for FACGE_Sd_Sn_Sm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FACGE_Vd_V_2S_Vn_V_2S_Vm_V_2S {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "facge",
        aliases: &[],
        opcode: 0x2e20ec00,
        mask: 0xbfa0fc00,
        class: InsnClass::ASIMDSAME,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSAME(ASIMDSAME::FACGE_Vd_V_2S_Vn_V_2S_Vm_V_2S(
            FACGE_Vd_V_2S_Vn_V_2S_Vm_V_2S::from(bits),
        ))
    }
}
impl InsnOpcode for FACGE_Vd_V_2S_Vn_V_2S_Vm_V_2S {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FACGE_Sd_S_S_Sn_S_S_Sm_S_S {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "facge",
        aliases: &[],
        opcode: 0x7e20ec00,
        mask: 0xffa0fc00,
        class: InsnClass::ASISDSAME,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sm,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMD_SCALAR_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDSAME(ASISDSAME::FACGE_Sd_S_S_Sn_S_S_Sm_S_S(
            FACGE_Sd_S_S_Sn_S_S_Sm_S_S::from(bits),
        ))
    }
}
impl InsnOpcode for FACGE_Sd_S_S_Sn_S_S_Sm_S_S {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FACGT_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "facgt",
        aliases: &[],
        opcode: 0x6500e010,
        mask: 0xff20e010,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Pd,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pd,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_Z,
                    InsnOperandQualifier::P_Z,
                    InsnOperandQualifier::P_Z,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ALIAS.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::FACGT_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16(
            FACGT_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for FACGT_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FACGT_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "facgt",
        aliases: &[],
        opcode: 0x2ec02c00,
        mask: 0xbfe0fc00,
        class: InsnClass::ASIMDSAME,
        feature_set: InsnFeatureSet::SIMD_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSAME(ASIMDSAME::FACGT_Vd_Vn_Vm(FACGT_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for FACGT_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FACGT_Sd_Sn_Sm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "facgt",
        aliases: &[],
        opcode: 0x7ec02c00,
        mask: 0xffe0fc00,
        class: InsnClass::ASISDSAME,
        feature_set: InsnFeatureSet::SIMD_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sm,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMD_SCALAR_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDSAME(ASISDSAME::FACGT_Sd_Sn_Sm(FACGT_Sd_Sn_Sm::from(bits)))
    }
}
impl InsnOpcode for FACGT_Sd_Sn_Sm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FACGT_Vd_V_2S_Vn_V_2S_Vm_V_2S {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "facgt",
        aliases: &[],
        opcode: 0x2ea0ec00,
        mask: 0xbfa0fc00,
        class: InsnClass::ASIMDSAME,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSAME(ASIMDSAME::FACGT_Vd_V_2S_Vn_V_2S_Vm_V_2S(
            FACGT_Vd_V_2S_Vn_V_2S_Vm_V_2S::from(bits),
        ))
    }
}
impl InsnOpcode for FACGT_Vd_V_2S_Vn_V_2S_Vm_V_2S {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FACGT_Sd_S_S_Sn_S_S_Sm_S_S {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "facgt",
        aliases: &[],
        opcode: 0x7ea0ec00,
        mask: 0xffa0fc00,
        class: InsnClass::ASISDSAME,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sm,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMD_SCALAR_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDSAME(ASISDSAME::FACGT_Sd_S_S_Sn_S_S_Sm_S_S(
            FACGT_Sd_S_S_Sn_S_S_Sm_S_S::from(bits),
        ))
    }
}
impl InsnOpcode for FACGT_Sd_S_S_Sn_S_S_Sm_S_S {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FADD_SME_ZA_array_off3_0_SME_Znx2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fadd",
        aliases: &[],
        opcode: 0xc1a01c00,
        mask: 0xffbf9c38,
        class: InsnClass::SME_FP_SD,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off3_0,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_0,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn2,
                    lsb: 6,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_FP_SD(SME_FP_SD::FADD_SME_ZA_array_off3_0_SME_Znx2(
            FADD_SME_ZA_array_off3_0_SME_Znx2::from(bits),
        ))
    }
}
impl InsnOpcode for FADD_SME_ZA_array_off3_0_SME_Znx2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FADD_SME_ZA_array_off3_0_SME_Znx4 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fadd",
        aliases: &[],
        opcode: 0xc1a11c00,
        mask: 0xffbf9c78,
        class: InsnClass::SME_FP_SD,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off3_0,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_0,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn4,
                    lsb: 7,
                    width: 3,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_4.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_FP_SD(SME_FP_SD::FADD_SME_ZA_array_off3_0_SME_Znx4(
            FADD_SME_ZA_array_off3_0_SME_Znx4::from(bits),
        ))
    }
}
impl InsnOpcode for FADD_SME_ZA_array_off3_0_SME_Znx4 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FADD_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fadd",
        aliases: &[],
        opcode: 0x65000000,
        mask: 0xff20fc00,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::FADD_SVE_Zd_SVE_Zn_SVE_Zm_16(
            FADD_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for FADD_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fadd",
        aliases: &[],
        opcode: 0x65008000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_5,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_5,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::FADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(
            FADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5::from(bits),
        ))
    }
}
impl InsnOpcode for FADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_I1_HALF_ONE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fadd",
        aliases: &[],
        opcode: 0x65188000,
        mask: 0xff3fe3c0,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_I1_HALF_ONE,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_i1,
                    lsb: 5,
                    width: 1,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::FADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_I1_HALF_ONE(
            FADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_I1_HALF_ONE::from(bits),
        ))
    }
}
impl InsnOpcode for FADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_I1_HALF_ONE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FADD_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fadd",
        aliases: &[],
        opcode: 0xe401400,
        mask: 0xbfe0fc00,
        class: InsnClass::ASIMDSAME,
        feature_set: InsnFeatureSet::SIMD_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSAME(ASIMDSAME::FADD_Vd_Vn_Vm(FADD_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for FADD_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FADD_Vd_V_2S_Vn_V_2S_Vm_V_2S {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fadd",
        aliases: &[],
        opcode: 0xe20d400,
        mask: 0xbfa0fc00,
        class: InsnClass::ASIMDSAME,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSAME(ASIMDSAME::FADD_Vd_V_2S_Vn_V_2S_Vm_V_2S(
            FADD_Vd_V_2S_Vn_V_2S_Vm_V_2S::from(bits),
        ))
    }
}
impl InsnOpcode for FADD_Vd_V_2S_Vn_V_2S_Vm_V_2S {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FADD_Fd_Fn_Fm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fadd",
        aliases: &[],
        opcode: 0x1ee02800,
        mask: 0xffe0fc00,
        class: InsnClass::FLOATDP2,
        feature_set: InsnFeatureSet::FP_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Fd,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fn,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fm,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_FPTYPE_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::FLOATDP2(FLOATDP2::FADD_Fd_Fn_Fm(FADD_Fd_Fn_Fm::from(bits)))
    }
}
impl InsnOpcode for FADD_Fd_Fn_Fm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FADD_Fd_S_S_Fn_S_S_Fm_S_S {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fadd",
        aliases: &[],
        opcode: 0x1e202800,
        mask: 0xff20fc00,
        class: InsnClass::FLOATDP2,
        feature_set: InsnFeatureSet::FP,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Fd,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fn,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fm,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_FPTYPE_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::FLOATDP2(FLOATDP2::FADD_Fd_S_S_Fn_S_S_Fm_S_S(
            FADD_Fd_S_S_Fn_S_S_Fm_S_S::from(bits),
        ))
    }
}
impl InsnOpcode for FADD_Fd_S_S_Fn_S_S_Fm_S_S {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FADDA_SVE_Vd_SVE_Pg3_SVE_Vd_SVE_Zm_5 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fadda",
        aliases: &[],
        opcode: 0x65182000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Vd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Vd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_5,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_5,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::FADDA_SVE_Vd_SVE_Pg3_SVE_Vd_SVE_Zm_5(
            FADDA_SVE_Vd_SVE_Pg3_SVE_Vd_SVE_Zm_5::from(bits),
        ))
    }
}
impl InsnOpcode for FADDA_SVE_Vd_SVE_Pg3_SVE_Vd_SVE_Zm_5 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FADDP_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "faddp",
        aliases: &[],
        opcode: 0x64108000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::FADDP_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(
            FADDP_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for FADDP_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FADDP_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "faddp",
        aliases: &[],
        opcode: 0x2e401400,
        mask: 0xbfe0fc00,
        class: InsnClass::ASIMDSAME,
        feature_set: InsnFeatureSet::SIMD_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSAME(ASIMDSAME::FADDP_Vd_Vn_Vm(FADDP_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for FADDP_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FADDP_Vd_V_2S_Vn_V_2S_Vm_V_2S {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "faddp",
        aliases: &[],
        opcode: 0x2e20d400,
        mask: 0xbfa0fc00,
        class: InsnClass::ASIMDSAME,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSAME(ASIMDSAME::FADDP_Vd_V_2S_Vn_V_2S_Vm_V_2S(
            FADDP_Vd_V_2S_Vn_V_2S_Vm_V_2S::from(bits),
        ))
    }
}
impl InsnOpcode for FADDP_Vd_V_2S_Vn_V_2S_Vm_V_2S {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FADDP_Sd_Vn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "faddp",
        aliases: &[],
        opcode: 0x5e30d800,
        mask: 0xfffffc00,
        class: InsnClass::ASISDPAIR,
        feature_set: InsnFeatureSet::SIMD_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDPAIR(ASISDPAIR::FADDP_Sd_Vn(FADDP_Sd_Vn::from(bits)))
    }
}
impl InsnOpcode for FADDP_Sd_Vn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FADDP_Sd_S_S_Vn_V_2S {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "faddp",
        aliases: &[],
        opcode: 0x7e30d800,
        mask: 0xffbffc00,
        class: InsnClass::ASISDPAIR,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDPAIR(ASISDPAIR::FADDP_Sd_S_S_Vn_V_2S(FADDP_Sd_S_S_Vn_V_2S::from(
            bits,
        )))
    }
}
impl InsnOpcode for FADDP_Sd_S_S_Vn_V_2S {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FADDQV_Vd_SVE_Pg3_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "faddqv",
        aliases: &[],
        opcode: 0x6410a000,
        mask: 0xff3fe000,
        class: InsnClass::SVE2_URQVS,
        feature_set: InsnFeatureSet::SVE2P1,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8H, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE2_URQVS(SVE2_URQVS::FADDQV_Vd_SVE_Pg3_SVE_Zn(
            FADDQV_Vd_SVE_Pg3_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for FADDQV_Vd_SVE_Pg3_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FADDV_SVE_Vd_SVE_Pg3_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "faddv",
        aliases: &[],
        opcode: 0x65002000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Vd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::FADDV_SVE_Vd_SVE_Pg3_SVE_Zn(
            FADDV_SVE_Vd_SVE_Pg3_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for FADDV_SVE_Vd_SVE_Pg3_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5_SVE_IMM_ROT1 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcadd",
        aliases: &[],
        opcode: 0x64008000,
        mask: 0xff3ee000,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_5,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_5,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_IMM_ROT1,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_rot1,
                    lsb: 16,
                    width: 1,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(
            SVE_SIZE_HSD::FCADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5_SVE_IMM_ROT1(
                FCADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5_SVE_IMM_ROT1::from(bits),
            ),
        )
    }
}
impl InsnOpcode for FCADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5_SVE_IMM_ROT1 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCADD_Vd_Vn_Vm_IMM_ROT3 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcadd",
        aliases: &[],
        opcode: 0x2e00e400,
        mask: 0xbf20ec00,
        class: InsnClass::ASIMDSAME,
        feature_set: InsnFeatureSet::COMPNUM,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[
                    InsnOperandQualifier::V_4H,
                    InsnOperandQualifier::V_8H,
                    InsnOperandQualifier::V_2S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[
                    InsnOperandQualifier::V_4H,
                    InsnOperandQualifier::V_8H,
                    InsnOperandQualifier::V_2S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[
                    InsnOperandQualifier::V_4H,
                    InsnOperandQualifier::V_8H,
                    InsnOperandQualifier::V_2S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::IMM_ROT3,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::rotate3,
                    lsb: 12,
                    width: 1,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSAME(ASIMDSAME::FCADD_Vd_Vn_Vm_IMM_ROT3(
            FCADD_Vd_Vn_Vm_IMM_ROT3::from(bits),
        ))
    }
}
impl InsnOpcode for FCADD_Vd_Vn_Vm_IMM_ROT3 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCCMP_Fn_Fm_NZCV_COND {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fccmp",
        aliases: &[],
        opcode: 0x1ee00400,
        mask: 0xffe00c10,
        class: InsnClass::FLOATCCMP,
        feature_set: InsnFeatureSet::FP_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Fn,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fm,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::NZCV,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::nzcv,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::COND,
                class: InsnOperandClass::COND,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_FPTYPE_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::FLOATCCMP(FLOATCCMP::FCCMP_Fn_Fm_NZCV_COND(
            FCCMP_Fn_Fm_NZCV_COND::from(bits),
        ))
    }
}
impl InsnOpcode for FCCMP_Fn_Fm_NZCV_COND {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCCMP_Fn_S_S_Fm_S_S_NZCV_COND {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fccmp",
        aliases: &[],
        opcode: 0x1e200400,
        mask: 0xff200c10,
        class: InsnClass::FLOATCCMP,
        feature_set: InsnFeatureSet::FP,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Fn,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fm,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::NZCV,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::nzcv,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::COND,
                class: InsnOperandClass::COND,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_FPTYPE_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::FLOATCCMP(FLOATCCMP::FCCMP_Fn_S_S_Fm_S_S_NZCV_COND(
            FCCMP_Fn_S_S_Fm_S_S_NZCV_COND::from(bits),
        ))
    }
}
impl InsnOpcode for FCCMP_Fn_S_S_Fm_S_S_NZCV_COND {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCCMPE_Fn_Fm_NZCV_COND {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fccmpe",
        aliases: &[],
        opcode: 0x1ee00410,
        mask: 0xffe00c10,
        class: InsnClass::FLOATCCMP,
        feature_set: InsnFeatureSet::FP_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Fn,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fm,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::NZCV,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::nzcv,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::COND,
                class: InsnOperandClass::COND,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_FPTYPE_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::FLOATCCMP(FLOATCCMP::FCCMPE_Fn_Fm_NZCV_COND(
            FCCMPE_Fn_Fm_NZCV_COND::from(bits),
        ))
    }
}
impl InsnOpcode for FCCMPE_Fn_Fm_NZCV_COND {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCCMPE_Fn_S_S_Fm_S_S_NZCV_COND {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fccmpe",
        aliases: &[],
        opcode: 0x1e200410,
        mask: 0xff200c10,
        class: InsnClass::FLOATCCMP,
        feature_set: InsnFeatureSet::FP,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Fn,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fm,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::NZCV,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::nzcv,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::COND,
                class: InsnOperandClass::COND,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_FPTYPE_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::FLOATCCMP(FLOATCCMP::FCCMPE_Fn_S_S_Fm_S_S_NZCV_COND(
            FCCMPE_Fn_S_S_Fm_S_S_NZCV_COND::from(bits),
        ))
    }
}
impl InsnOpcode for FCCMPE_Fn_S_S_Fm_S_S_NZCV_COND {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCLAMP_SME_Zdnx2_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fclamp",
        aliases: &[],
        opcode: 0xc120c000,
        mask: 0xff20fc01,
        class: InsnClass::SME_SIZE_22_HSD,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn2,
                    lsb: 1,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_SIZE_22_HSD(SME_SIZE_22_HSD::FCLAMP_SME_Zdnx2_SVE_Zn_SVE_Zm_16(
            FCLAMP_SME_Zdnx2_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for FCLAMP_SME_Zdnx2_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCLAMP_SME_Zdnx4_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fclamp",
        aliases: &[],
        opcode: 0xc120c800,
        mask: 0xff20fc03,
        class: InsnClass::SME_SIZE_22_HSD,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn4,
                    lsb: 2,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_SIZE_22_HSD(SME_SIZE_22_HSD::FCLAMP_SME_Zdnx4_SVE_Zn_SVE_Zm_16(
            FCLAMP_SME_Zdnx4_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for FCLAMP_SME_Zdnx4_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCLAMP_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fclamp",
        aliases: &[],
        opcode: 0x64202400,
        mask: 0xff20fc00,
        class: InsnClass::SME_SIZE_22_HSD,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_SIZE_22_HSD(SME_SIZE_22_HSD::FCLAMP_SVE_Zd_SVE_Zn_SVE_Zm_16(
            FCLAMP_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for FCLAMP_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCMEQ_SVE_Pd_SVE_Pg3_SVE_Zn_FPIMM0 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcmeq",
        aliases: &[],
        opcode: 0x65122000,
        mask: 0xff3fe010,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Pd,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pd,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_Z,
                    InsnOperandQualifier::P_Z,
                    InsnOperandQualifier::P_Z,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::FPIMM0,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::FCMEQ_SVE_Pd_SVE_Pg3_SVE_Zn_FPIMM0(
            FCMEQ_SVE_Pd_SVE_Pg3_SVE_Zn_FPIMM0::from(bits),
        ))
    }
}
impl InsnOpcode for FCMEQ_SVE_Pd_SVE_Pg3_SVE_Zn_FPIMM0 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCMEQ_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcmeq",
        aliases: &[],
        opcode: 0x65006000,
        mask: 0xff20e010,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Pd,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pd,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_Z,
                    InsnOperandQualifier::P_Z,
                    InsnOperandQualifier::P_Z,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::FCMEQ_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16(
            FCMEQ_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for FCMEQ_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCMEQ_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcmeq",
        aliases: &[],
        opcode: 0xe402400,
        mask: 0xbfe0fc00,
        class: InsnClass::ASIMDSAME,
        feature_set: InsnFeatureSet::SIMD_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSAME(ASIMDSAME::FCMEQ_Vd_Vn_Vm(FCMEQ_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for FCMEQ_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCMEQ_Sd_Sn_Sm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcmeq",
        aliases: &[],
        opcode: 0x5e402400,
        mask: 0xffe0fc00,
        class: InsnClass::ASISDSAME,
        feature_set: InsnFeatureSet::SIMD_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sm,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMD_SCALAR_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDSAME(ASISDSAME::FCMEQ_Sd_Sn_Sm(FCMEQ_Sd_Sn_Sm::from(bits)))
    }
}
impl InsnOpcode for FCMEQ_Sd_Sn_Sm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCMEQ_Vd_Vn_FPIMM0 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcmeq",
        aliases: &[],
        opcode: 0xea0d800,
        mask: 0xbfbffc00,
        class: InsnClass::ASIMDMISC,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::FPIMM0,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDMISC(ASIMDMISC::FCMEQ_Vd_Vn_FPIMM0(FCMEQ_Vd_Vn_FPIMM0::from(
            bits,
        )))
    }
}
impl InsnOpcode for FCMEQ_Vd_Vn_FPIMM0 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCMEQ_Vd_V_4H_Vn_V_4H_FPIMM0 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcmeq",
        aliases: &[],
        opcode: 0xef8d800,
        mask: 0xbffffc00,
        class: InsnClass::ASIMDMISC,
        feature_set: InsnFeatureSet::SIMD_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::FPIMM0,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDMISC(ASIMDMISC::FCMEQ_Vd_V_4H_Vn_V_4H_FPIMM0(
            FCMEQ_Vd_V_4H_Vn_V_4H_FPIMM0::from(bits),
        ))
    }
}
impl InsnOpcode for FCMEQ_Vd_V_4H_Vn_V_4H_FPIMM0 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCMEQ_Vd_V_2S_Vn_V_2S_Vm_V_2S {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcmeq",
        aliases: &[],
        opcode: 0xe20e400,
        mask: 0xbfa0fc00,
        class: InsnClass::ASIMDSAME,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSAME(ASIMDSAME::FCMEQ_Vd_V_2S_Vn_V_2S_Vm_V_2S(
            FCMEQ_Vd_V_2S_Vn_V_2S_Vm_V_2S::from(bits),
        ))
    }
}
impl InsnOpcode for FCMEQ_Vd_V_2S_Vn_V_2S_Vm_V_2S {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCMEQ_Sd_Sn_FPIMM0 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcmeq",
        aliases: &[],
        opcode: 0x5ea0d800,
        mask: 0xffbffc00,
        class: InsnClass::ASISDMISC,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::FPIMM0,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMD_SCALAR_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDMISC(ASISDMISC::FCMEQ_Sd_Sn_FPIMM0(FCMEQ_Sd_Sn_FPIMM0::from(
            bits,
        )))
    }
}
impl InsnOpcode for FCMEQ_Sd_Sn_FPIMM0 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCMEQ_Sd_S_H_Sn_S_H_FPIMM0 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcmeq",
        aliases: &[],
        opcode: 0x5ef8d800,
        mask: 0xfffffc00,
        class: InsnClass::ASISDMISC,
        feature_set: InsnFeatureSet::SIMD_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::FPIMM0,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMD_SCALAR_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDMISC(ASISDMISC::FCMEQ_Sd_S_H_Sn_S_H_FPIMM0(
            FCMEQ_Sd_S_H_Sn_S_H_FPIMM0::from(bits),
        ))
    }
}
impl InsnOpcode for FCMEQ_Sd_S_H_Sn_S_H_FPIMM0 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCMEQ_Sd_S_S_Sn_S_S_Sm_S_S {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcmeq",
        aliases: &[],
        opcode: 0x5e20e400,
        mask: 0xffa0fc00,
        class: InsnClass::ASISDSAME,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sm,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMD_SCALAR_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDSAME(ASISDSAME::FCMEQ_Sd_S_S_Sn_S_S_Sm_S_S(
            FCMEQ_Sd_S_S_Sn_S_S_Sm_S_S::from(bits),
        ))
    }
}
impl InsnOpcode for FCMEQ_Sd_S_S_Sn_S_S_Sm_S_S {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCMGE_SVE_Pd_SVE_Pg3_SVE_Zn_FPIMM0 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcmge",
        aliases: &[],
        opcode: 0x65102000,
        mask: 0xff3fe010,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Pd,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pd,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_Z,
                    InsnOperandQualifier::P_Z,
                    InsnOperandQualifier::P_Z,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::FPIMM0,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::FCMGE_SVE_Pd_SVE_Pg3_SVE_Zn_FPIMM0(
            FCMGE_SVE_Pd_SVE_Pg3_SVE_Zn_FPIMM0::from(bits),
        ))
    }
}
impl InsnOpcode for FCMGE_SVE_Pd_SVE_Pg3_SVE_Zn_FPIMM0 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCMGE_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcmge",
        aliases: &[],
        opcode: 0x65004000,
        mask: 0xff20e010,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Pd,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pd,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_Z,
                    InsnOperandQualifier::P_Z,
                    InsnOperandQualifier::P_Z,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ALIAS.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::FCMGE_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16(
            FCMGE_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for FCMGE_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCMGE_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcmge",
        aliases: &[],
        opcode: 0x2e402400,
        mask: 0xbfe0fc00,
        class: InsnClass::ASIMDSAME,
        feature_set: InsnFeatureSet::SIMD_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSAME(ASIMDSAME::FCMGE_Vd_Vn_Vm(FCMGE_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for FCMGE_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCMGE_Sd_Sn_Sm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcmge",
        aliases: &[],
        opcode: 0x7e402400,
        mask: 0xffe0fc00,
        class: InsnClass::ASISDSAME,
        feature_set: InsnFeatureSet::SIMD_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sm,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMD_SCALAR_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDSAME(ASISDSAME::FCMGE_Sd_Sn_Sm(FCMGE_Sd_Sn_Sm::from(bits)))
    }
}
impl InsnOpcode for FCMGE_Sd_Sn_Sm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCMGE_Vd_Vn_FPIMM0 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcmge",
        aliases: &[],
        opcode: 0x2ea0c800,
        mask: 0xbfbffc00,
        class: InsnClass::ASIMDMISC,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::FPIMM0,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDMISC(ASIMDMISC::FCMGE_Vd_Vn_FPIMM0(FCMGE_Vd_Vn_FPIMM0::from(
            bits,
        )))
    }
}
impl InsnOpcode for FCMGE_Vd_Vn_FPIMM0 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCMGE_Vd_V_4H_Vn_V_4H_FPIMM0 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcmge",
        aliases: &[],
        opcode: 0x2ef8c800,
        mask: 0xbffffc00,
        class: InsnClass::ASIMDMISC,
        feature_set: InsnFeatureSet::SIMD_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::FPIMM0,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDMISC(ASIMDMISC::FCMGE_Vd_V_4H_Vn_V_4H_FPIMM0(
            FCMGE_Vd_V_4H_Vn_V_4H_FPIMM0::from(bits),
        ))
    }
}
impl InsnOpcode for FCMGE_Vd_V_4H_Vn_V_4H_FPIMM0 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCMGE_Vd_V_2S_Vn_V_2S_Vm_V_2S {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcmge",
        aliases: &[],
        opcode: 0x2e20e400,
        mask: 0xbfa0fc00,
        class: InsnClass::ASIMDSAME,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSAME(ASIMDSAME::FCMGE_Vd_V_2S_Vn_V_2S_Vm_V_2S(
            FCMGE_Vd_V_2S_Vn_V_2S_Vm_V_2S::from(bits),
        ))
    }
}
impl InsnOpcode for FCMGE_Vd_V_2S_Vn_V_2S_Vm_V_2S {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCMGE_Sd_Sn_FPIMM0 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcmge",
        aliases: &[],
        opcode: 0x7ea0c800,
        mask: 0xffbffc00,
        class: InsnClass::ASISDMISC,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::FPIMM0,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMD_SCALAR_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDMISC(ASISDMISC::FCMGE_Sd_Sn_FPIMM0(FCMGE_Sd_Sn_FPIMM0::from(
            bits,
        )))
    }
}
impl InsnOpcode for FCMGE_Sd_Sn_FPIMM0 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCMGE_Sd_S_H_Sn_S_H_FPIMM0 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcmge",
        aliases: &[],
        opcode: 0x7ef8c800,
        mask: 0xfffffc00,
        class: InsnClass::ASISDMISC,
        feature_set: InsnFeatureSet::SIMD_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::FPIMM0,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMD_SCALAR_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDMISC(ASISDMISC::FCMGE_Sd_S_H_Sn_S_H_FPIMM0(
            FCMGE_Sd_S_H_Sn_S_H_FPIMM0::from(bits),
        ))
    }
}
impl InsnOpcode for FCMGE_Sd_S_H_Sn_S_H_FPIMM0 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCMGE_Sd_S_S_Sn_S_S_Sm_S_S {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcmge",
        aliases: &[],
        opcode: 0x7e20e400,
        mask: 0xffa0fc00,
        class: InsnClass::ASISDSAME,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sm,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMD_SCALAR_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDSAME(ASISDSAME::FCMGE_Sd_S_S_Sn_S_S_Sm_S_S(
            FCMGE_Sd_S_S_Sn_S_S_Sm_S_S::from(bits),
        ))
    }
}
impl InsnOpcode for FCMGE_Sd_S_S_Sn_S_S_Sm_S_S {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCMGT_SVE_Pd_SVE_Pg3_SVE_Zn_FPIMM0 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcmgt",
        aliases: &[],
        opcode: 0x65102010,
        mask: 0xff3fe010,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Pd,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pd,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_Z,
                    InsnOperandQualifier::P_Z,
                    InsnOperandQualifier::P_Z,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::FPIMM0,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::FCMGT_SVE_Pd_SVE_Pg3_SVE_Zn_FPIMM0(
            FCMGT_SVE_Pd_SVE_Pg3_SVE_Zn_FPIMM0::from(bits),
        ))
    }
}
impl InsnOpcode for FCMGT_SVE_Pd_SVE_Pg3_SVE_Zn_FPIMM0 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCMGT_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcmgt",
        aliases: &[],
        opcode: 0x65004010,
        mask: 0xff20e010,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Pd,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pd,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_Z,
                    InsnOperandQualifier::P_Z,
                    InsnOperandQualifier::P_Z,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ALIAS.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::FCMGT_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16(
            FCMGT_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for FCMGT_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCMGT_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcmgt",
        aliases: &[],
        opcode: 0x2ec02400,
        mask: 0xbfe0fc00,
        class: InsnClass::ASIMDSAME,
        feature_set: InsnFeatureSet::SIMD_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSAME(ASIMDSAME::FCMGT_Vd_Vn_Vm(FCMGT_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for FCMGT_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCMGT_Sd_Sn_Sm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcmgt",
        aliases: &[],
        opcode: 0x7ec02400,
        mask: 0xffe0fc00,
        class: InsnClass::ASISDSAME,
        feature_set: InsnFeatureSet::SIMD_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sm,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMD_SCALAR_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDSAME(ASISDSAME::FCMGT_Sd_Sn_Sm(FCMGT_Sd_Sn_Sm::from(bits)))
    }
}
impl InsnOpcode for FCMGT_Sd_Sn_Sm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCMGT_Vd_Vn_FPIMM0 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcmgt",
        aliases: &[],
        opcode: 0xea0c800,
        mask: 0xbfbffc00,
        class: InsnClass::ASIMDMISC,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::FPIMM0,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDMISC(ASIMDMISC::FCMGT_Vd_Vn_FPIMM0(FCMGT_Vd_Vn_FPIMM0::from(
            bits,
        )))
    }
}
impl InsnOpcode for FCMGT_Vd_Vn_FPIMM0 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCMGT_Vd_V_4H_Vn_V_4H_FPIMM0 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcmgt",
        aliases: &[],
        opcode: 0xef8c800,
        mask: 0xbffffc00,
        class: InsnClass::ASIMDMISC,
        feature_set: InsnFeatureSet::SIMD_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::FPIMM0,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDMISC(ASIMDMISC::FCMGT_Vd_V_4H_Vn_V_4H_FPIMM0(
            FCMGT_Vd_V_4H_Vn_V_4H_FPIMM0::from(bits),
        ))
    }
}
impl InsnOpcode for FCMGT_Vd_V_4H_Vn_V_4H_FPIMM0 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCMGT_Vd_V_2S_Vn_V_2S_Vm_V_2S {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcmgt",
        aliases: &[],
        opcode: 0x2ea0e400,
        mask: 0xbfa0fc00,
        class: InsnClass::ASIMDSAME,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSAME(ASIMDSAME::FCMGT_Vd_V_2S_Vn_V_2S_Vm_V_2S(
            FCMGT_Vd_V_2S_Vn_V_2S_Vm_V_2S::from(bits),
        ))
    }
}
impl InsnOpcode for FCMGT_Vd_V_2S_Vn_V_2S_Vm_V_2S {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCMGT_Sd_Sn_FPIMM0 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcmgt",
        aliases: &[],
        opcode: 0x5ea0c800,
        mask: 0xffbffc00,
        class: InsnClass::ASISDMISC,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::FPIMM0,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMD_SCALAR_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDMISC(ASISDMISC::FCMGT_Sd_Sn_FPIMM0(FCMGT_Sd_Sn_FPIMM0::from(
            bits,
        )))
    }
}
impl InsnOpcode for FCMGT_Sd_Sn_FPIMM0 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCMGT_Sd_S_H_Sn_S_H_FPIMM0 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcmgt",
        aliases: &[],
        opcode: 0x5ef8c800,
        mask: 0xfffffc00,
        class: InsnClass::ASISDMISC,
        feature_set: InsnFeatureSet::SIMD_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::FPIMM0,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMD_SCALAR_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDMISC(ASISDMISC::FCMGT_Sd_S_H_Sn_S_H_FPIMM0(
            FCMGT_Sd_S_H_Sn_S_H_FPIMM0::from(bits),
        ))
    }
}
impl InsnOpcode for FCMGT_Sd_S_H_Sn_S_H_FPIMM0 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCMGT_Sd_S_S_Sn_S_S_Sm_S_S {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcmgt",
        aliases: &[],
        opcode: 0x7ea0e400,
        mask: 0xffa0fc00,
        class: InsnClass::ASISDSAME,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sm,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMD_SCALAR_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDSAME(ASISDSAME::FCMGT_Sd_S_S_Sn_S_S_Sm_S_S(
            FCMGT_Sd_S_S_Sn_S_S_Sm_S_S::from(bits),
        ))
    }
}
impl InsnOpcode for FCMGT_Sd_S_S_Sn_S_S_Sm_S_S {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCMLA_SVE_Zd_SVE_Pg3_SVE_Zn_SVE_Zm_16_IMM_ROT2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcmla",
        aliases: &[],
        opcode: 0x64000000,
        mask: 0xff208000,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::IMM_ROT2,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::rotate2,
                    lsb: 13,
                    width: 2,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(
            SVE_SIZE_HSD::FCMLA_SVE_Zd_SVE_Pg3_SVE_Zn_SVE_Zm_16_IMM_ROT2(
                FCMLA_SVE_Zd_SVE_Pg3_SVE_Zn_SVE_Zm_16_IMM_ROT2::from(bits),
            ),
        )
    }
}
impl InsnOpcode for FCMLA_SVE_Zd_SVE_Pg3_SVE_Zn_SVE_Zm_16_IMM_ROT2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCMLA_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX_SVE_IMM_ROT2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcmla",
        aliases: &[],
        opcode: 0x64a01000,
        mask: 0xffe0f000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm3_INDEX,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_IMM_ROT2,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_rot2,
                    lsb: 10,
                    width: 2,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::FCMLA_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX_SVE_IMM_ROT2(
            FCMLA_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX_SVE_IMM_ROT2::from(bits),
        ))
    }
}
impl InsnOpcode for FCMLA_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX_SVE_IMM_ROT2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCMLA_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX_SVE_IMM_ROT2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcmla",
        aliases: &[],
        opcode: 0x64e01000,
        mask: 0xffe0f000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm4_INDEX,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_IMM_ROT2,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_rot2,
                    lsb: 10,
                    width: 2,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::FCMLA_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX_SVE_IMM_ROT2(
            FCMLA_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX_SVE_IMM_ROT2::from(bits),
        ))
    }
}
impl InsnOpcode for FCMLA_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX_SVE_IMM_ROT2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCMLA_Vd_Vn_Vm_IMM_ROT1 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcmla",
        aliases: &[],
        opcode: 0x2e00c400,
        mask: 0xbf20e400,
        class: InsnClass::ASIMDSAME,
        feature_set: InsnFeatureSet::COMPNUM,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[
                    InsnOperandQualifier::V_4H,
                    InsnOperandQualifier::V_8H,
                    InsnOperandQualifier::V_2S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[
                    InsnOperandQualifier::V_4H,
                    InsnOperandQualifier::V_8H,
                    InsnOperandQualifier::V_2S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[
                    InsnOperandQualifier::V_4H,
                    InsnOperandQualifier::V_8H,
                    InsnOperandQualifier::V_2S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::IMM_ROT1,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::rotate1,
                    lsb: 11,
                    width: 2,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSAME(ASIMDSAME::FCMLA_Vd_Vn_Vm_IMM_ROT1(
            FCMLA_Vd_Vn_Vm_IMM_ROT1::from(bits),
        ))
    }
}
impl InsnOpcode for FCMLA_Vd_Vn_Vm_IMM_ROT1 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCMLA_Vd_Vn_Em_IMM_ROT2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcmla",
        aliases: &[],
        opcode: 0x2f001000,
        mask: 0xbf009400,
        class: InsnClass::ASIMDELEM,
        feature_set: InsnFeatureSet::COMPNUM,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[
                    InsnOperandQualifier::V_4H,
                    InsnOperandQualifier::V_8H,
                    InsnOperandQualifier::V_4S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[
                    InsnOperandQualifier::V_4H,
                    InsnOperandQualifier::V_8H,
                    InsnOperandQualifier::V_4S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Em,
                class: InsnOperandClass::SIMD_ELEMENT,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::IMM_ROT2,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::rotate2,
                    lsb: 13,
                    width: 2,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDELEM(ASIMDELEM::FCMLA_Vd_Vn_Em_IMM_ROT2(
            FCMLA_Vd_Vn_Em_IMM_ROT2::from(bits),
        ))
    }
}
impl InsnOpcode for FCMLA_Vd_Vn_Em_IMM_ROT2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCMLE_SVE_Pd_SVE_Pg3_SVE_Zn_FPIMM0 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcmle",
        aliases: &[],
        opcode: 0x65112010,
        mask: 0xff3fe010,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Pd,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pd,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_Z,
                    InsnOperandQualifier::P_Z,
                    InsnOperandQualifier::P_Z,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::FPIMM0,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::FCMLE_SVE_Pd_SVE_Pg3_SVE_Zn_FPIMM0(
            FCMLE_SVE_Pd_SVE_Pg3_SVE_Zn_FPIMM0::from(bits),
        ))
    }
}
impl InsnOpcode for FCMLE_SVE_Pd_SVE_Pg3_SVE_Zn_FPIMM0 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCMLE_Vd_Vn_FPIMM0 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcmle",
        aliases: &[],
        opcode: 0x2ea0d800,
        mask: 0xbfbffc00,
        class: InsnClass::ASIMDMISC,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::FPIMM0,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDMISC(ASIMDMISC::FCMLE_Vd_Vn_FPIMM0(FCMLE_Vd_Vn_FPIMM0::from(
            bits,
        )))
    }
}
impl InsnOpcode for FCMLE_Vd_Vn_FPIMM0 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCMLE_Vd_V_4H_Vn_V_4H_FPIMM0 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcmle",
        aliases: &[],
        opcode: 0x2ef8d800,
        mask: 0xbffffc00,
        class: InsnClass::ASIMDMISC,
        feature_set: InsnFeatureSet::SIMD_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::FPIMM0,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDMISC(ASIMDMISC::FCMLE_Vd_V_4H_Vn_V_4H_FPIMM0(
            FCMLE_Vd_V_4H_Vn_V_4H_FPIMM0::from(bits),
        ))
    }
}
impl InsnOpcode for FCMLE_Vd_V_4H_Vn_V_4H_FPIMM0 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCMLE_Sd_Sn_FPIMM0 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcmle",
        aliases: &[],
        opcode: 0x7ea0d800,
        mask: 0xffbffc00,
        class: InsnClass::ASISDMISC,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::FPIMM0,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMD_SCALAR_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDMISC(ASISDMISC::FCMLE_Sd_Sn_FPIMM0(FCMLE_Sd_Sn_FPIMM0::from(
            bits,
        )))
    }
}
impl InsnOpcode for FCMLE_Sd_Sn_FPIMM0 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCMLE_Sd_S_H_Sn_S_H_FPIMM0 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcmle",
        aliases: &[],
        opcode: 0x7ef8d800,
        mask: 0xfffffc00,
        class: InsnClass::ASISDMISC,
        feature_set: InsnFeatureSet::SIMD_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::FPIMM0,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMD_SCALAR_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDMISC(ASISDMISC::FCMLE_Sd_S_H_Sn_S_H_FPIMM0(
            FCMLE_Sd_S_H_Sn_S_H_FPIMM0::from(bits),
        ))
    }
}
impl InsnOpcode for FCMLE_Sd_S_H_Sn_S_H_FPIMM0 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCMLT_SVE_Pd_SVE_Pg3_SVE_Zn_FPIMM0 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcmlt",
        aliases: &[],
        opcode: 0x65112000,
        mask: 0xff3fe010,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Pd,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pd,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_Z,
                    InsnOperandQualifier::P_Z,
                    InsnOperandQualifier::P_Z,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::FPIMM0,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::FCMLT_SVE_Pd_SVE_Pg3_SVE_Zn_FPIMM0(
            FCMLT_SVE_Pd_SVE_Pg3_SVE_Zn_FPIMM0::from(bits),
        ))
    }
}
impl InsnOpcode for FCMLT_SVE_Pd_SVE_Pg3_SVE_Zn_FPIMM0 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCMLT_Vd_Vn_FPIMM0 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcmlt",
        aliases: &[],
        opcode: 0xea0e800,
        mask: 0xbfbffc00,
        class: InsnClass::ASIMDMISC,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::FPIMM0,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDMISC(ASIMDMISC::FCMLT_Vd_Vn_FPIMM0(FCMLT_Vd_Vn_FPIMM0::from(
            bits,
        )))
    }
}
impl InsnOpcode for FCMLT_Vd_Vn_FPIMM0 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCMLT_Vd_V_4H_Vn_V_4H_FPIMM0 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcmlt",
        aliases: &[],
        opcode: 0xef8e800,
        mask: 0xbffffc00,
        class: InsnClass::ASIMDMISC,
        feature_set: InsnFeatureSet::SIMD_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::FPIMM0,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDMISC(ASIMDMISC::FCMLT_Vd_V_4H_Vn_V_4H_FPIMM0(
            FCMLT_Vd_V_4H_Vn_V_4H_FPIMM0::from(bits),
        ))
    }
}
impl InsnOpcode for FCMLT_Vd_V_4H_Vn_V_4H_FPIMM0 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCMLT_Sd_Sn_FPIMM0 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcmlt",
        aliases: &[],
        opcode: 0x5ea0e800,
        mask: 0xffbffc00,
        class: InsnClass::ASISDMISC,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::FPIMM0,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMD_SCALAR_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDMISC(ASISDMISC::FCMLT_Sd_Sn_FPIMM0(FCMLT_Sd_Sn_FPIMM0::from(
            bits,
        )))
    }
}
impl InsnOpcode for FCMLT_Sd_Sn_FPIMM0 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCMLT_Sd_S_H_Sn_S_H_FPIMM0 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcmlt",
        aliases: &[],
        opcode: 0x5ef8e800,
        mask: 0xfffffc00,
        class: InsnClass::ASISDMISC,
        feature_set: InsnFeatureSet::SIMD_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::FPIMM0,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMD_SCALAR_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDMISC(ASISDMISC::FCMLT_Sd_S_H_Sn_S_H_FPIMM0(
            FCMLT_Sd_S_H_Sn_S_H_FPIMM0::from(bits),
        ))
    }
}
impl InsnOpcode for FCMLT_Sd_S_H_Sn_S_H_FPIMM0 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCMNE_SVE_Pd_SVE_Pg3_SVE_Zn_FPIMM0 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcmne",
        aliases: &[],
        opcode: 0x65132000,
        mask: 0xff3fe010,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Pd,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pd,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_Z,
                    InsnOperandQualifier::P_Z,
                    InsnOperandQualifier::P_Z,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::FPIMM0,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::FCMNE_SVE_Pd_SVE_Pg3_SVE_Zn_FPIMM0(
            FCMNE_SVE_Pd_SVE_Pg3_SVE_Zn_FPIMM0::from(bits),
        ))
    }
}
impl InsnOpcode for FCMNE_SVE_Pd_SVE_Pg3_SVE_Zn_FPIMM0 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCMNE_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcmne",
        aliases: &[],
        opcode: 0x65006010,
        mask: 0xff20e010,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Pd,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pd,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_Z,
                    InsnOperandQualifier::P_Z,
                    InsnOperandQualifier::P_Z,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::FCMNE_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16(
            FCMNE_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for FCMNE_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCMP_Fn_Fm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcmp",
        aliases: &[],
        opcode: 0x1ee02000,
        mask: 0xffe0fc1f,
        class: InsnClass::FLOATCMP,
        feature_set: InsnFeatureSet::FP_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Fn,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fm,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_FPTYPE_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::FLOATCMP(FLOATCMP::FCMP_Fn_Fm(FCMP_Fn_Fm::from(bits)))
    }
}
impl InsnOpcode for FCMP_Fn_Fm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCMP_Fn_S_S_Fm_S_S {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcmp",
        aliases: &[],
        opcode: 0x1e202000,
        mask: 0xff20fc1f,
        class: InsnClass::FLOATCMP,
        feature_set: InsnFeatureSet::FP,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Fn,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fm,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_FPTYPE_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::FLOATCMP(FLOATCMP::FCMP_Fn_S_S_Fm_S_S(FCMP_Fn_S_S_Fm_S_S::from(bits)))
    }
}
impl InsnOpcode for FCMP_Fn_S_S_Fm_S_S {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCMP_Fn_FPIMM0 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcmp",
        aliases: &[],
        opcode: 0x1ee02008,
        mask: 0xffe0fc1f,
        class: InsnClass::FLOATCMP,
        feature_set: InsnFeatureSet::FP_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Fn,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::FPIMM0,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_FPTYPE_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::FLOATCMP(FLOATCMP::FCMP_Fn_FPIMM0(FCMP_Fn_FPIMM0::from(bits)))
    }
}
impl InsnOpcode for FCMP_Fn_FPIMM0 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCMP_Fn_S_S_FPIMM0 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcmp",
        aliases: &[],
        opcode: 0x1e202008,
        mask: 0xff20fc1f,
        class: InsnClass::FLOATCMP,
        feature_set: InsnFeatureSet::FP,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Fn,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::FPIMM0,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_FPTYPE_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::FLOATCMP(FLOATCMP::FCMP_Fn_S_S_FPIMM0(FCMP_Fn_S_S_FPIMM0::from(bits)))
    }
}
impl InsnOpcode for FCMP_Fn_S_S_FPIMM0 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCMPE_Fn_Fm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcmpe",
        aliases: &[],
        opcode: 0x1ee02010,
        mask: 0xffe0fc1f,
        class: InsnClass::FLOATCMP,
        feature_set: InsnFeatureSet::FP_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Fn,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fm,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_FPTYPE_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::FLOATCMP(FLOATCMP::FCMPE_Fn_Fm(FCMPE_Fn_Fm::from(bits)))
    }
}
impl InsnOpcode for FCMPE_Fn_Fm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCMPE_Fn_S_S_Fm_S_S {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcmpe",
        aliases: &[],
        opcode: 0x1e202010,
        mask: 0xff20fc1f,
        class: InsnClass::FLOATCMP,
        feature_set: InsnFeatureSet::FP,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Fn,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fm,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_FPTYPE_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::FLOATCMP(FLOATCMP::FCMPE_Fn_S_S_Fm_S_S(FCMPE_Fn_S_S_Fm_S_S::from(
            bits,
        )))
    }
}
impl InsnOpcode for FCMPE_Fn_S_S_Fm_S_S {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCMPE_Fn_FPIMM0 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcmpe",
        aliases: &[],
        opcode: 0x1ee02018,
        mask: 0xffe0fc1f,
        class: InsnClass::FLOATCMP,
        feature_set: InsnFeatureSet::FP_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Fn,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::FPIMM0,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_FPTYPE_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::FLOATCMP(FLOATCMP::FCMPE_Fn_FPIMM0(FCMPE_Fn_FPIMM0::from(bits)))
    }
}
impl InsnOpcode for FCMPE_Fn_FPIMM0 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCMPE_Fn_S_S_FPIMM0 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcmpe",
        aliases: &[],
        opcode: 0x1e202018,
        mask: 0xff20fc1f,
        class: InsnClass::FLOATCMP,
        feature_set: InsnFeatureSet::FP,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Fn,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::FPIMM0,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_FPTYPE_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::FLOATCMP(FLOATCMP::FCMPE_Fn_S_S_FPIMM0(FCMPE_Fn_S_S_FPIMM0::from(
            bits,
        )))
    }
}
impl InsnOpcode for FCMPE_Fn_S_S_FPIMM0 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCMUO_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcmuo",
        aliases: &[],
        opcode: 0x6500c000,
        mask: 0xff20e010,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Pd,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pd,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_Z,
                    InsnOperandQualifier::P_Z,
                    InsnOperandQualifier::P_Z,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::FCMUO_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16(
            FCMUO_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for FCMUO_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCPY_SVE_Zd_SVE_Pg4_16_SVE_FPIMM8 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcpy",
        aliases: &[],
        opcode: 0x510c000,
        mask: 0xff30e000,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg4_16,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M, InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg4_16,
                    lsb: 16,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_FPIMM8,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_imm8,
                    lsb: 5,
                    width: 8,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ALIAS.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::FCPY_SVE_Zd_SVE_Pg4_16_SVE_FPIMM8(
            FCPY_SVE_Zd_SVE_Pg4_16_SVE_FPIMM8::from(bits),
        ))
    }
}
impl InsnOpcode for FCPY_SVE_Zd_SVE_Pg4_16_SVE_FPIMM8 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCSEL_Fd_Fn_Fm_COND {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcsel",
        aliases: &[],
        opcode: 0x1ee00c00,
        mask: 0xffe00c00,
        class: InsnClass::FLOATSEL,
        feature_set: InsnFeatureSet::FP_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Fd,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fn,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fm,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::COND,
                class: InsnOperandClass::COND,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_FPTYPE_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::FLOATSEL(FLOATSEL::FCSEL_Fd_Fn_Fm_COND(FCSEL_Fd_Fn_Fm_COND::from(
            bits,
        )))
    }
}
impl InsnOpcode for FCSEL_Fd_Fn_Fm_COND {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCSEL_Fd_S_S_Fn_S_S_Fm_S_S_COND {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcsel",
        aliases: &[],
        opcode: 0x1e200c00,
        mask: 0xff200c00,
        class: InsnClass::FLOATSEL,
        feature_set: InsnFeatureSet::FP,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Fd,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fn,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fm,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::COND,
                class: InsnOperandClass::COND,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_FPTYPE_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::FLOATSEL(FLOATSEL::FCSEL_Fd_S_S_Fn_S_S_Fm_S_S_COND(
            FCSEL_Fd_S_S_Fn_S_S_Fm_S_S_COND::from(bits),
        ))
    }
}
impl InsnOpcode for FCSEL_Fd_S_S_Fn_S_S_Fm_S_S_COND {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCVT_SVE_Zd_SME_Znx2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcvt",
        aliases: &[],
        opcode: 0xc120e000,
        mask: 0xfffffc20,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn2,
                    lsb: 6,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::FCVT_SVE_Zd_SME_Znx2(FCVT_SVE_Zd_SME_Znx2::from(
            bits,
        )))
    }
}
impl InsnOpcode for FCVT_SVE_Zd_SME_Znx2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCVT_SVE_Zd_SVE_Pg3_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcvt",
        aliases: &[],
        opcode: 0x6588a000,
        mask: 0xffffe000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::FCVT_SVE_Zd_SVE_Pg3_SVE_Zn(
            FCVT_SVE_Zd_SVE_Pg3_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for FCVT_SVE_Zd_SVE_Pg3_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCVT_SVE_Zd_S_H_SVE_Pg3_P_M_SVE_Zn_S_D {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcvt",
        aliases: &[],
        opcode: 0x65c8a000,
        mask: 0xffffe000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::FCVT_SVE_Zd_S_H_SVE_Pg3_P_M_SVE_Zn_S_D(
            FCVT_SVE_Zd_S_H_SVE_Pg3_P_M_SVE_Zn_S_D::from(bits),
        ))
    }
}
impl InsnOpcode for FCVT_SVE_Zd_S_H_SVE_Pg3_P_M_SVE_Zn_S_D {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCVT_SVE_Zd_S_S_SVE_Pg3_P_M_SVE_Zn_S_D {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcvt",
        aliases: &[],
        opcode: 0x65caa000,
        mask: 0xffffe000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::FCVT_SVE_Zd_S_S_SVE_Pg3_P_M_SVE_Zn_S_D(
            FCVT_SVE_Zd_S_S_SVE_Pg3_P_M_SVE_Zn_S_D::from(bits),
        ))
    }
}
impl InsnOpcode for FCVT_SVE_Zd_S_S_SVE_Pg3_P_M_SVE_Zn_S_D {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCVT_SVE_Zd_S_S_SVE_Pg3_P_M_SVE_Zn_S_H {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcvt",
        aliases: &[],
        opcode: 0x6589a000,
        mask: 0xffffe000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::FCVT_SVE_Zd_S_S_SVE_Pg3_P_M_SVE_Zn_S_H(
            FCVT_SVE_Zd_S_S_SVE_Pg3_P_M_SVE_Zn_S_H::from(bits),
        ))
    }
}
impl InsnOpcode for FCVT_SVE_Zd_S_S_SVE_Pg3_P_M_SVE_Zn_S_H {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCVT_SVE_Zd_S_D_SVE_Pg3_P_M_SVE_Zn_S_H {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcvt",
        aliases: &[],
        opcode: 0x65c9a000,
        mask: 0xffffe000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::FCVT_SVE_Zd_S_D_SVE_Pg3_P_M_SVE_Zn_S_H(
            FCVT_SVE_Zd_S_D_SVE_Pg3_P_M_SVE_Zn_S_H::from(bits),
        ))
    }
}
impl InsnOpcode for FCVT_SVE_Zd_S_D_SVE_Pg3_P_M_SVE_Zn_S_H {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCVT_SVE_Zd_S_D_SVE_Pg3_P_M_SVE_Zn_S_S {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcvt",
        aliases: &[],
        opcode: 0x65cba000,
        mask: 0xffffe000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::FCVT_SVE_Zd_S_D_SVE_Pg3_P_M_SVE_Zn_S_S(
            FCVT_SVE_Zd_S_D_SVE_Pg3_P_M_SVE_Zn_S_S::from(bits),
        ))
    }
}
impl InsnOpcode for FCVT_SVE_Zd_S_D_SVE_Pg3_P_M_SVE_Zn_S_S {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCVT_Fd_Fn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcvt",
        aliases: &[],
        opcode: 0x1e224000,
        mask: 0xff3e7c00,
        class: InsnClass::FLOATDP1,
        feature_set: InsnFeatureSet::FP,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Fd,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fn,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_FPTYPE_FIELD.bits() | InsnFlags::HAS_SPEC_DECODE_RULES.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::FLOATDP1(FLOATDP1::FCVT_Fd_Fn(FCVT_Fd_Fn::from(bits)))
    }
}
impl InsnOpcode for FCVT_Fd_Fn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCVTAS_Vd_Vn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcvtas",
        aliases: &[],
        opcode: 0xe21c800,
        mask: 0xbfbffc00,
        class: InsnClass::ASIMDMISC,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDMISC(ASIMDMISC::FCVTAS_Vd_Vn(FCVTAS_Vd_Vn::from(bits)))
    }
}
impl InsnOpcode for FCVTAS_Vd_Vn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCVTAS_Vd_V_4H_Vn_V_4H {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcvtas",
        aliases: &[],
        opcode: 0xe79c800,
        mask: 0xbffffc00,
        class: InsnClass::ASIMDMISC,
        feature_set: InsnFeatureSet::SIMD_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDMISC(ASIMDMISC::FCVTAS_Vd_V_4H_Vn_V_4H(
            FCVTAS_Vd_V_4H_Vn_V_4H::from(bits),
        ))
    }
}
impl InsnOpcode for FCVTAS_Vd_V_4H_Vn_V_4H {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCVTAS_Rd_Fn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcvtas",
        aliases: &[],
        opcode: 0x1ee40000,
        mask: 0x7ffffc00,
        class: InsnClass::FLOAT2INT,
        feature_set: InsnFeatureSet::FP_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fn,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_FPTYPE_FIELD.bits() | InsnFlags::HAS_SF_FIELD.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::FLOAT2INT(FLOAT2INT::FCVTAS_Rd_Fn(FCVTAS_Rd_Fn::from(bits)))
    }
}
impl InsnOpcode for FCVTAS_Rd_Fn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCVTAS_Rd_W_Fn_S_D {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcvtas",
        aliases: &[],
        opcode: 0x1e240000,
        mask: 0x7f3ffc00,
        class: InsnClass::FLOAT2INT,
        feature_set: InsnFeatureSet::FP,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fn,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_FPTYPE_FIELD.bits() | InsnFlags::HAS_SF_FIELD.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::FLOAT2INT(FLOAT2INT::FCVTAS_Rd_W_Fn_S_D(FCVTAS_Rd_W_Fn_S_D::from(
            bits,
        )))
    }
}
impl InsnOpcode for FCVTAS_Rd_W_Fn_S_D {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCVTAS_Sd_Sn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcvtas",
        aliases: &[],
        opcode: 0x5e21c800,
        mask: 0xffbffc00,
        class: InsnClass::ASISDMISC,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMD_SCALAR_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDMISC(ASISDMISC::FCVTAS_Sd_Sn(FCVTAS_Sd_Sn::from(bits)))
    }
}
impl InsnOpcode for FCVTAS_Sd_Sn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCVTAS_Sd_S_H_Sn_S_H {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcvtas",
        aliases: &[],
        opcode: 0x5e79c800,
        mask: 0xfffffc00,
        class: InsnClass::ASISDMISC,
        feature_set: InsnFeatureSet::SIMD_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMD_SCALAR_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDMISC(ASISDMISC::FCVTAS_Sd_S_H_Sn_S_H(FCVTAS_Sd_S_H_Sn_S_H::from(
            bits,
        )))
    }
}
impl InsnOpcode for FCVTAS_Sd_S_H_Sn_S_H {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCVTAU_Vd_Vn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcvtau",
        aliases: &[],
        opcode: 0x2e21c800,
        mask: 0xbfbffc00,
        class: InsnClass::ASIMDMISC,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDMISC(ASIMDMISC::FCVTAU_Vd_Vn(FCVTAU_Vd_Vn::from(bits)))
    }
}
impl InsnOpcode for FCVTAU_Vd_Vn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCVTAU_Vd_V_4H_Vn_V_4H {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcvtau",
        aliases: &[],
        opcode: 0x2e79c800,
        mask: 0xbffffc00,
        class: InsnClass::ASIMDMISC,
        feature_set: InsnFeatureSet::SIMD_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDMISC(ASIMDMISC::FCVTAU_Vd_V_4H_Vn_V_4H(
            FCVTAU_Vd_V_4H_Vn_V_4H::from(bits),
        ))
    }
}
impl InsnOpcode for FCVTAU_Vd_V_4H_Vn_V_4H {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCVTAU_Rd_Fn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcvtau",
        aliases: &[],
        opcode: 0x1ee50000,
        mask: 0x7ffffc00,
        class: InsnClass::FLOAT2INT,
        feature_set: InsnFeatureSet::FP_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fn,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_FPTYPE_FIELD.bits() | InsnFlags::HAS_SF_FIELD.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::FLOAT2INT(FLOAT2INT::FCVTAU_Rd_Fn(FCVTAU_Rd_Fn::from(bits)))
    }
}
impl InsnOpcode for FCVTAU_Rd_Fn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCVTAU_Rd_W_Fn_S_D {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcvtau",
        aliases: &[],
        opcode: 0x1e250000,
        mask: 0x7f3ffc00,
        class: InsnClass::FLOAT2INT,
        feature_set: InsnFeatureSet::FP,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fn,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_FPTYPE_FIELD.bits() | InsnFlags::HAS_SF_FIELD.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::FLOAT2INT(FLOAT2INT::FCVTAU_Rd_W_Fn_S_D(FCVTAU_Rd_W_Fn_S_D::from(
            bits,
        )))
    }
}
impl InsnOpcode for FCVTAU_Rd_W_Fn_S_D {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCVTAU_Sd_Sn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcvtau",
        aliases: &[],
        opcode: 0x7e21c800,
        mask: 0xffbffc00,
        class: InsnClass::ASISDMISC,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMD_SCALAR_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDMISC(ASISDMISC::FCVTAU_Sd_Sn(FCVTAU_Sd_Sn::from(bits)))
    }
}
impl InsnOpcode for FCVTAU_Sd_Sn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCVTAU_Sd_S_H_Sn_S_H {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcvtau",
        aliases: &[],
        opcode: 0x7e79c800,
        mask: 0xfffffc00,
        class: InsnClass::ASISDMISC,
        feature_set: InsnFeatureSet::SIMD_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMD_SCALAR_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDMISC(ASISDMISC::FCVTAU_Sd_S_H_Sn_S_H(FCVTAU_Sd_S_H_Sn_S_H::from(
            bits,
        )))
    }
}
impl InsnOpcode for FCVTAU_Sd_S_H_Sn_S_H {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCVTL_Vd_Vn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcvtl",
        aliases: &[],
        opcode: 0xe217800,
        mask: 0xffbffc00,
        class: InsnClass::ASIMDMISC,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SPEC_DECODE_RULES.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDMISC(ASIMDMISC::FCVTL_Vd_Vn(FCVTL_Vd_Vn::from(bits)))
    }
}
impl InsnOpcode for FCVTL_Vd_Vn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCVTL2_Vd_Vn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcvtl2",
        aliases: &[],
        opcode: 0x4e217800,
        mask: 0xffbffc00,
        class: InsnClass::ASIMDMISC,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SPEC_DECODE_RULES.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDMISC(ASIMDMISC::FCVTL2_Vd_Vn(FCVTL2_Vd_Vn::from(bits)))
    }
}
impl InsnOpcode for FCVTL2_Vd_Vn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCVTLT_SVE_Zd_SVE_Pg3_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcvtlt",
        aliases: &[],
        opcode: 0x6489a000,
        mask: 0xffffe000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::FCVTLT_SVE_Zd_SVE_Pg3_SVE_Zn(
            FCVTLT_SVE_Zd_SVE_Pg3_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for FCVTLT_SVE_Zd_SVE_Pg3_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCVTLT_SVE_Zd_S_D_SVE_Pg3_P_M_SVE_Zn_S_S {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcvtlt",
        aliases: &[],
        opcode: 0x64cba000,
        mask: 0xffffe000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::FCVTLT_SVE_Zd_S_D_SVE_Pg3_P_M_SVE_Zn_S_S(
            FCVTLT_SVE_Zd_S_D_SVE_Pg3_P_M_SVE_Zn_S_S::from(bits),
        ))
    }
}
impl InsnOpcode for FCVTLT_SVE_Zd_S_D_SVE_Pg3_P_M_SVE_Zn_S_S {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCVTMS_Vd_Vn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcvtms",
        aliases: &[],
        opcode: 0xe21b800,
        mask: 0xbfbffc00,
        class: InsnClass::ASIMDMISC,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDMISC(ASIMDMISC::FCVTMS_Vd_Vn(FCVTMS_Vd_Vn::from(bits)))
    }
}
impl InsnOpcode for FCVTMS_Vd_Vn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCVTMS_Vd_V_4H_Vn_V_4H {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcvtms",
        aliases: &[],
        opcode: 0xe79b800,
        mask: 0xbffffc00,
        class: InsnClass::ASIMDMISC,
        feature_set: InsnFeatureSet::SIMD_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDMISC(ASIMDMISC::FCVTMS_Vd_V_4H_Vn_V_4H(
            FCVTMS_Vd_V_4H_Vn_V_4H::from(bits),
        ))
    }
}
impl InsnOpcode for FCVTMS_Vd_V_4H_Vn_V_4H {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCVTMS_Rd_Fn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcvtms",
        aliases: &[],
        opcode: 0x1ef00000,
        mask: 0x7ffffc00,
        class: InsnClass::FLOAT2INT,
        feature_set: InsnFeatureSet::FP_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fn,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_FPTYPE_FIELD.bits() | InsnFlags::HAS_SF_FIELD.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::FLOAT2INT(FLOAT2INT::FCVTMS_Rd_Fn(FCVTMS_Rd_Fn::from(bits)))
    }
}
impl InsnOpcode for FCVTMS_Rd_Fn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCVTMS_Rd_W_Fn_S_D {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcvtms",
        aliases: &[],
        opcode: 0x1e300000,
        mask: 0x7f3ffc00,
        class: InsnClass::FLOAT2INT,
        feature_set: InsnFeatureSet::FP,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fn,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_FPTYPE_FIELD.bits() | InsnFlags::HAS_SF_FIELD.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::FLOAT2INT(FLOAT2INT::FCVTMS_Rd_W_Fn_S_D(FCVTMS_Rd_W_Fn_S_D::from(
            bits,
        )))
    }
}
impl InsnOpcode for FCVTMS_Rd_W_Fn_S_D {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCVTMS_Sd_Sn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcvtms",
        aliases: &[],
        opcode: 0x5e21b800,
        mask: 0xffbffc00,
        class: InsnClass::ASISDMISC,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMD_SCALAR_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDMISC(ASISDMISC::FCVTMS_Sd_Sn(FCVTMS_Sd_Sn::from(bits)))
    }
}
impl InsnOpcode for FCVTMS_Sd_Sn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCVTMS_Sd_S_H_Sn_S_H {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcvtms",
        aliases: &[],
        opcode: 0x5e79b800,
        mask: 0xfffffc00,
        class: InsnClass::ASISDMISC,
        feature_set: InsnFeatureSet::SIMD_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMD_SCALAR_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDMISC(ASISDMISC::FCVTMS_Sd_S_H_Sn_S_H(FCVTMS_Sd_S_H_Sn_S_H::from(
            bits,
        )))
    }
}
impl InsnOpcode for FCVTMS_Sd_S_H_Sn_S_H {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCVTMU_Vd_Vn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcvtmu",
        aliases: &[],
        opcode: 0x2e21b800,
        mask: 0xbfbffc00,
        class: InsnClass::ASIMDMISC,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDMISC(ASIMDMISC::FCVTMU_Vd_Vn(FCVTMU_Vd_Vn::from(bits)))
    }
}
impl InsnOpcode for FCVTMU_Vd_Vn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCVTMU_Vd_V_4H_Vn_V_4H {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcvtmu",
        aliases: &[],
        opcode: 0x2e79b800,
        mask: 0xbffffc00,
        class: InsnClass::ASIMDMISC,
        feature_set: InsnFeatureSet::SIMD_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDMISC(ASIMDMISC::FCVTMU_Vd_V_4H_Vn_V_4H(
            FCVTMU_Vd_V_4H_Vn_V_4H::from(bits),
        ))
    }
}
impl InsnOpcode for FCVTMU_Vd_V_4H_Vn_V_4H {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCVTMU_Rd_Fn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcvtmu",
        aliases: &[],
        opcode: 0x1ef10000,
        mask: 0x7ffffc00,
        class: InsnClass::FLOAT2INT,
        feature_set: InsnFeatureSet::FP_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fn,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_FPTYPE_FIELD.bits() | InsnFlags::HAS_SF_FIELD.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::FLOAT2INT(FLOAT2INT::FCVTMU_Rd_Fn(FCVTMU_Rd_Fn::from(bits)))
    }
}
impl InsnOpcode for FCVTMU_Rd_Fn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCVTMU_Rd_W_Fn_S_D {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcvtmu",
        aliases: &[],
        opcode: 0x1e310000,
        mask: 0x7f3ffc00,
        class: InsnClass::FLOAT2INT,
        feature_set: InsnFeatureSet::FP,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fn,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_FPTYPE_FIELD.bits() | InsnFlags::HAS_SF_FIELD.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::FLOAT2INT(FLOAT2INT::FCVTMU_Rd_W_Fn_S_D(FCVTMU_Rd_W_Fn_S_D::from(
            bits,
        )))
    }
}
impl InsnOpcode for FCVTMU_Rd_W_Fn_S_D {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCVTMU_Sd_Sn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcvtmu",
        aliases: &[],
        opcode: 0x7e21b800,
        mask: 0xffbffc00,
        class: InsnClass::ASISDMISC,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMD_SCALAR_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDMISC(ASISDMISC::FCVTMU_Sd_Sn(FCVTMU_Sd_Sn::from(bits)))
    }
}
impl InsnOpcode for FCVTMU_Sd_Sn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCVTMU_Sd_S_H_Sn_S_H {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcvtmu",
        aliases: &[],
        opcode: 0x7e79b800,
        mask: 0xfffffc00,
        class: InsnClass::ASISDMISC,
        feature_set: InsnFeatureSet::SIMD_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMD_SCALAR_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDMISC(ASISDMISC::FCVTMU_Sd_S_H_Sn_S_H(FCVTMU_Sd_S_H_Sn_S_H::from(
            bits,
        )))
    }
}
impl InsnOpcode for FCVTMU_Sd_S_H_Sn_S_H {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCVTN_SVE_Zd_SME_Znx2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcvtn",
        aliases: &[],
        opcode: 0xc120e020,
        mask: 0xfffffc20,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn2,
                    lsb: 6,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::FCVTN_SVE_Zd_SME_Znx2(
            FCVTN_SVE_Zd_SME_Znx2::from(bits),
        ))
    }
}
impl InsnOpcode for FCVTN_SVE_Zd_SME_Znx2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCVTN_Vd_Vn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcvtn",
        aliases: &[],
        opcode: 0xe216800,
        mask: 0xffbffc00,
        class: InsnClass::ASIMDMISC,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SPEC_DECODE_RULES.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDMISC(ASIMDMISC::FCVTN_Vd_Vn(FCVTN_Vd_Vn::from(bits)))
    }
}
impl InsnOpcode for FCVTN_Vd_Vn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCVTN2_Vd_Vn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcvtn2",
        aliases: &[],
        opcode: 0x4e216800,
        mask: 0xffbffc00,
        class: InsnClass::ASIMDMISC,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SPEC_DECODE_RULES.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDMISC(ASIMDMISC::FCVTN2_Vd_Vn(FCVTN2_Vd_Vn::from(bits)))
    }
}
impl InsnOpcode for FCVTN2_Vd_Vn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCVTNS_Vd_Vn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcvtns",
        aliases: &[],
        opcode: 0xe21a800,
        mask: 0xbfbffc00,
        class: InsnClass::ASIMDMISC,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDMISC(ASIMDMISC::FCVTNS_Vd_Vn(FCVTNS_Vd_Vn::from(bits)))
    }
}
impl InsnOpcode for FCVTNS_Vd_Vn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCVTNS_Vd_V_4H_Vn_V_4H {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcvtns",
        aliases: &[],
        opcode: 0xe79a800,
        mask: 0xbffffc00,
        class: InsnClass::ASIMDMISC,
        feature_set: InsnFeatureSet::SIMD_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDMISC(ASIMDMISC::FCVTNS_Vd_V_4H_Vn_V_4H(
            FCVTNS_Vd_V_4H_Vn_V_4H::from(bits),
        ))
    }
}
impl InsnOpcode for FCVTNS_Vd_V_4H_Vn_V_4H {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCVTNS_Rd_Fn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcvtns",
        aliases: &[],
        opcode: 0x1ee00000,
        mask: 0x7ffffc00,
        class: InsnClass::FLOAT2INT,
        feature_set: InsnFeatureSet::FP_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fn,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_FPTYPE_FIELD.bits() | InsnFlags::HAS_SF_FIELD.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::FLOAT2INT(FLOAT2INT::FCVTNS_Rd_Fn(FCVTNS_Rd_Fn::from(bits)))
    }
}
impl InsnOpcode for FCVTNS_Rd_Fn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCVTNS_Rd_W_Fn_S_D {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcvtns",
        aliases: &[],
        opcode: 0x1e200000,
        mask: 0x7f3ffc00,
        class: InsnClass::FLOAT2INT,
        feature_set: InsnFeatureSet::FP,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fn,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_FPTYPE_FIELD.bits() | InsnFlags::HAS_SF_FIELD.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::FLOAT2INT(FLOAT2INT::FCVTNS_Rd_W_Fn_S_D(FCVTNS_Rd_W_Fn_S_D::from(
            bits,
        )))
    }
}
impl InsnOpcode for FCVTNS_Rd_W_Fn_S_D {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCVTNS_Sd_Sn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcvtns",
        aliases: &[],
        opcode: 0x5e21a800,
        mask: 0xffbffc00,
        class: InsnClass::ASISDMISC,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMD_SCALAR_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDMISC(ASISDMISC::FCVTNS_Sd_Sn(FCVTNS_Sd_Sn::from(bits)))
    }
}
impl InsnOpcode for FCVTNS_Sd_Sn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCVTNS_Sd_S_H_Sn_S_H {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcvtns",
        aliases: &[],
        opcode: 0x5e79a800,
        mask: 0xfffffc00,
        class: InsnClass::ASISDMISC,
        feature_set: InsnFeatureSet::SIMD_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMD_SCALAR_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDMISC(ASISDMISC::FCVTNS_Sd_S_H_Sn_S_H(FCVTNS_Sd_S_H_Sn_S_H::from(
            bits,
        )))
    }
}
impl InsnOpcode for FCVTNS_Sd_S_H_Sn_S_H {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCVTNT_SVE_Zd_SVE_Pg3_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcvtnt",
        aliases: &[],
        opcode: 0x6488a000,
        mask: 0xffffe000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::FCVTNT_SVE_Zd_SVE_Pg3_SVE_Zn(
            FCVTNT_SVE_Zd_SVE_Pg3_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for FCVTNT_SVE_Zd_SVE_Pg3_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCVTNT_SVE_Zd_S_S_SVE_Pg3_P_M_SVE_Zn_S_D {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcvtnt",
        aliases: &[],
        opcode: 0x64caa000,
        mask: 0xffffe000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::FCVTNT_SVE_Zd_S_S_SVE_Pg3_P_M_SVE_Zn_S_D(
            FCVTNT_SVE_Zd_S_S_SVE_Pg3_P_M_SVE_Zn_S_D::from(bits),
        ))
    }
}
impl InsnOpcode for FCVTNT_SVE_Zd_S_S_SVE_Pg3_P_M_SVE_Zn_S_D {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCVTNU_Vd_Vn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcvtnu",
        aliases: &[],
        opcode: 0x2e21a800,
        mask: 0xbfbffc00,
        class: InsnClass::ASIMDMISC,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDMISC(ASIMDMISC::FCVTNU_Vd_Vn(FCVTNU_Vd_Vn::from(bits)))
    }
}
impl InsnOpcode for FCVTNU_Vd_Vn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCVTNU_Vd_V_4H_Vn_V_4H {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcvtnu",
        aliases: &[],
        opcode: 0x2e79a800,
        mask: 0xbffffc00,
        class: InsnClass::ASIMDMISC,
        feature_set: InsnFeatureSet::SIMD_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDMISC(ASIMDMISC::FCVTNU_Vd_V_4H_Vn_V_4H(
            FCVTNU_Vd_V_4H_Vn_V_4H::from(bits),
        ))
    }
}
impl InsnOpcode for FCVTNU_Vd_V_4H_Vn_V_4H {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCVTNU_Rd_Fn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcvtnu",
        aliases: &[],
        opcode: 0x1ee10000,
        mask: 0x7ffffc00,
        class: InsnClass::FLOAT2INT,
        feature_set: InsnFeatureSet::FP_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fn,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_FPTYPE_FIELD.bits() | InsnFlags::HAS_SF_FIELD.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::FLOAT2INT(FLOAT2INT::FCVTNU_Rd_Fn(FCVTNU_Rd_Fn::from(bits)))
    }
}
impl InsnOpcode for FCVTNU_Rd_Fn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCVTNU_Rd_W_Fn_S_D {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcvtnu",
        aliases: &[],
        opcode: 0x1e210000,
        mask: 0x7f3ffc00,
        class: InsnClass::FLOAT2INT,
        feature_set: InsnFeatureSet::FP,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fn,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_FPTYPE_FIELD.bits() | InsnFlags::HAS_SF_FIELD.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::FLOAT2INT(FLOAT2INT::FCVTNU_Rd_W_Fn_S_D(FCVTNU_Rd_W_Fn_S_D::from(
            bits,
        )))
    }
}
impl InsnOpcode for FCVTNU_Rd_W_Fn_S_D {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCVTNU_Sd_Sn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcvtnu",
        aliases: &[],
        opcode: 0x7e21a800,
        mask: 0xffbffc00,
        class: InsnClass::ASISDMISC,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMD_SCALAR_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDMISC(ASISDMISC::FCVTNU_Sd_Sn(FCVTNU_Sd_Sn::from(bits)))
    }
}
impl InsnOpcode for FCVTNU_Sd_Sn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCVTNU_Sd_S_H_Sn_S_H {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcvtnu",
        aliases: &[],
        opcode: 0x7e79a800,
        mask: 0xfffffc00,
        class: InsnClass::ASISDMISC,
        feature_set: InsnFeatureSet::SIMD_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMD_SCALAR_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDMISC(ASISDMISC::FCVTNU_Sd_S_H_Sn_S_H(FCVTNU_Sd_S_H_Sn_S_H::from(
            bits,
        )))
    }
}
impl InsnOpcode for FCVTNU_Sd_S_H_Sn_S_H {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCVTPS_Vd_Vn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcvtps",
        aliases: &[],
        opcode: 0xea1a800,
        mask: 0xbfbffc00,
        class: InsnClass::ASIMDMISC,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDMISC(ASIMDMISC::FCVTPS_Vd_Vn(FCVTPS_Vd_Vn::from(bits)))
    }
}
impl InsnOpcode for FCVTPS_Vd_Vn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCVTPS_Vd_V_4H_Vn_V_4H {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcvtps",
        aliases: &[],
        opcode: 0xef9a800,
        mask: 0xbffffc00,
        class: InsnClass::ASIMDMISC,
        feature_set: InsnFeatureSet::SIMD_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDMISC(ASIMDMISC::FCVTPS_Vd_V_4H_Vn_V_4H(
            FCVTPS_Vd_V_4H_Vn_V_4H::from(bits),
        ))
    }
}
impl InsnOpcode for FCVTPS_Vd_V_4H_Vn_V_4H {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCVTPS_Rd_Fn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcvtps",
        aliases: &[],
        opcode: 0x1ee80000,
        mask: 0x7ffffc00,
        class: InsnClass::FLOAT2INT,
        feature_set: InsnFeatureSet::FP_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fn,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_FPTYPE_FIELD.bits() | InsnFlags::HAS_SF_FIELD.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::FLOAT2INT(FLOAT2INT::FCVTPS_Rd_Fn(FCVTPS_Rd_Fn::from(bits)))
    }
}
impl InsnOpcode for FCVTPS_Rd_Fn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCVTPS_Rd_W_Fn_S_D {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcvtps",
        aliases: &[],
        opcode: 0x1e280000,
        mask: 0x7f3ffc00,
        class: InsnClass::FLOAT2INT,
        feature_set: InsnFeatureSet::FP,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fn,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_FPTYPE_FIELD.bits() | InsnFlags::HAS_SF_FIELD.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::FLOAT2INT(FLOAT2INT::FCVTPS_Rd_W_Fn_S_D(FCVTPS_Rd_W_Fn_S_D::from(
            bits,
        )))
    }
}
impl InsnOpcode for FCVTPS_Rd_W_Fn_S_D {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCVTPS_Sd_Sn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcvtps",
        aliases: &[],
        opcode: 0x5ea1a800,
        mask: 0xffbffc00,
        class: InsnClass::ASISDMISC,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMD_SCALAR_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDMISC(ASISDMISC::FCVTPS_Sd_Sn(FCVTPS_Sd_Sn::from(bits)))
    }
}
impl InsnOpcode for FCVTPS_Sd_Sn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCVTPS_Sd_S_H_Sn_S_H {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcvtps",
        aliases: &[],
        opcode: 0x5ef9a800,
        mask: 0xfffffc00,
        class: InsnClass::ASISDMISC,
        feature_set: InsnFeatureSet::SIMD_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMD_SCALAR_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDMISC(ASISDMISC::FCVTPS_Sd_S_H_Sn_S_H(FCVTPS_Sd_S_H_Sn_S_H::from(
            bits,
        )))
    }
}
impl InsnOpcode for FCVTPS_Sd_S_H_Sn_S_H {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCVTPU_Vd_Vn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcvtpu",
        aliases: &[],
        opcode: 0x2ea1a800,
        mask: 0xbfbffc00,
        class: InsnClass::ASIMDMISC,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDMISC(ASIMDMISC::FCVTPU_Vd_Vn(FCVTPU_Vd_Vn::from(bits)))
    }
}
impl InsnOpcode for FCVTPU_Vd_Vn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCVTPU_Vd_V_4H_Vn_V_4H {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcvtpu",
        aliases: &[],
        opcode: 0x2ef9a800,
        mask: 0xbffffc00,
        class: InsnClass::ASIMDMISC,
        feature_set: InsnFeatureSet::SIMD_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDMISC(ASIMDMISC::FCVTPU_Vd_V_4H_Vn_V_4H(
            FCVTPU_Vd_V_4H_Vn_V_4H::from(bits),
        ))
    }
}
impl InsnOpcode for FCVTPU_Vd_V_4H_Vn_V_4H {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCVTPU_Rd_Fn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcvtpu",
        aliases: &[],
        opcode: 0x1ee90000,
        mask: 0x7ffffc00,
        class: InsnClass::FLOAT2INT,
        feature_set: InsnFeatureSet::FP_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fn,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_FPTYPE_FIELD.bits() | InsnFlags::HAS_SF_FIELD.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::FLOAT2INT(FLOAT2INT::FCVTPU_Rd_Fn(FCVTPU_Rd_Fn::from(bits)))
    }
}
impl InsnOpcode for FCVTPU_Rd_Fn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCVTPU_Rd_W_Fn_S_D {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcvtpu",
        aliases: &[],
        opcode: 0x1e290000,
        mask: 0x7f3ffc00,
        class: InsnClass::FLOAT2INT,
        feature_set: InsnFeatureSet::FP,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fn,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_FPTYPE_FIELD.bits() | InsnFlags::HAS_SF_FIELD.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::FLOAT2INT(FLOAT2INT::FCVTPU_Rd_W_Fn_S_D(FCVTPU_Rd_W_Fn_S_D::from(
            bits,
        )))
    }
}
impl InsnOpcode for FCVTPU_Rd_W_Fn_S_D {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCVTPU_Sd_Sn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcvtpu",
        aliases: &[],
        opcode: 0x7ea1a800,
        mask: 0xffbffc00,
        class: InsnClass::ASISDMISC,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMD_SCALAR_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDMISC(ASISDMISC::FCVTPU_Sd_Sn(FCVTPU_Sd_Sn::from(bits)))
    }
}
impl InsnOpcode for FCVTPU_Sd_Sn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCVTPU_Sd_S_H_Sn_S_H {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcvtpu",
        aliases: &[],
        opcode: 0x7ef9a800,
        mask: 0xfffffc00,
        class: InsnClass::ASISDMISC,
        feature_set: InsnFeatureSet::SIMD_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMD_SCALAR_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDMISC(ASISDMISC::FCVTPU_Sd_S_H_Sn_S_H(FCVTPU_Sd_S_H_Sn_S_H::from(
            bits,
        )))
    }
}
impl InsnOpcode for FCVTPU_Sd_S_H_Sn_S_H {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCVTX_SVE_Zd_SVE_Pg3_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcvtx",
        aliases: &[],
        opcode: 0x650aa000,
        mask: 0xffffe000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::FCVTX_SVE_Zd_SVE_Pg3_SVE_Zn(
            FCVTX_SVE_Zd_SVE_Pg3_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for FCVTX_SVE_Zd_SVE_Pg3_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCVTXN_Vd_Vn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcvtxn",
        aliases: &[],
        opcode: 0x2e616800,
        mask: 0xfffffc00,
        class: InsnClass::ASIMDMISC,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDMISC(ASIMDMISC::FCVTXN_Vd_Vn(FCVTXN_Vd_Vn::from(bits)))
    }
}
impl InsnOpcode for FCVTXN_Vd_Vn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCVTXN_Sd_Sn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcvtxn",
        aliases: &[],
        opcode: 0x7e216800,
        mask: 0xffbffc00,
        class: InsnClass::ASISDMISC,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SPEC_DECODE_RULES.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDMISC(ASISDMISC::FCVTXN_Sd_Sn(FCVTXN_Sd_Sn::from(bits)))
    }
}
impl InsnOpcode for FCVTXN_Sd_Sn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCVTXN2_Vd_Vn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcvtxn2",
        aliases: &[],
        opcode: 0x6e616800,
        mask: 0xfffffc00,
        class: InsnClass::ASIMDMISC,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDMISC(ASIMDMISC::FCVTXN2_Vd_Vn(FCVTXN2_Vd_Vn::from(bits)))
    }
}
impl InsnOpcode for FCVTXN2_Vd_Vn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCVTXNT_SVE_Zd_SVE_Pg3_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcvtxnt",
        aliases: &[],
        opcode: 0x640aa000,
        mask: 0xffffe000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::FCVTXNT_SVE_Zd_SVE_Pg3_SVE_Zn(
            FCVTXNT_SVE_Zd_SVE_Pg3_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for FCVTXNT_SVE_Zd_SVE_Pg3_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCVTZS_SME_Zdnx2_SME_Znx2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcvtzs",
        aliases: &[],
        opcode: 0xc121e000,
        mask: 0xfffffc21,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn2,
                    lsb: 1,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn2,
                    lsb: 6,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::FCVTZS_SME_Zdnx2_SME_Znx2(
            FCVTZS_SME_Zdnx2_SME_Znx2::from(bits),
        ))
    }
}
impl InsnOpcode for FCVTZS_SME_Zdnx2_SME_Znx2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCVTZS_SME_Zdnx4_SME_Znx4 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcvtzs",
        aliases: &[],
        opcode: 0xc131e000,
        mask: 0xfffffc63,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn4,
                    lsb: 2,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn4,
                    lsb: 7,
                    width: 3,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::FCVTZS_SME_Zdnx4_SME_Znx4(
            FCVTZS_SME_Zdnx4_SME_Znx4::from(bits),
        ))
    }
}
impl InsnOpcode for FCVTZS_SME_Zdnx4_SME_Znx4 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCVTZS_SVE_Zd_SVE_Pg3_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcvtzs",
        aliases: &[],
        opcode: 0x659ca000,
        mask: 0xffffe000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::FCVTZS_SVE_Zd_SVE_Pg3_SVE_Zn(
            FCVTZS_SVE_Zd_SVE_Pg3_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for FCVTZS_SVE_Zd_SVE_Pg3_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCVTZS_SVE_Zd_S_S_SVE_Pg3_P_M_SVE_Zn_S_D {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcvtzs",
        aliases: &[],
        opcode: 0x65d8a000,
        mask: 0xffffe000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::FCVTZS_SVE_Zd_S_S_SVE_Pg3_P_M_SVE_Zn_S_D(
            FCVTZS_SVE_Zd_S_S_SVE_Pg3_P_M_SVE_Zn_S_D::from(bits),
        ))
    }
}
impl InsnOpcode for FCVTZS_SVE_Zd_S_S_SVE_Pg3_P_M_SVE_Zn_S_D {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCVTZS_SVE_Zd_S_S_SVE_Pg3_P_M_SVE_Zn_S_H {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcvtzs",
        aliases: &[],
        opcode: 0x655ca000,
        mask: 0xffffe000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::FCVTZS_SVE_Zd_S_S_SVE_Pg3_P_M_SVE_Zn_S_H(
            FCVTZS_SVE_Zd_S_S_SVE_Pg3_P_M_SVE_Zn_S_H::from(bits),
        ))
    }
}
impl InsnOpcode for FCVTZS_SVE_Zd_S_S_SVE_Pg3_P_M_SVE_Zn_S_H {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCVTZS_SVE_Zd_S_D_SVE_Pg3_P_M_SVE_Zn_S_S {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcvtzs",
        aliases: &[],
        opcode: 0x65dca000,
        mask: 0xffffe000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::FCVTZS_SVE_Zd_S_D_SVE_Pg3_P_M_SVE_Zn_S_S(
            FCVTZS_SVE_Zd_S_D_SVE_Pg3_P_M_SVE_Zn_S_S::from(bits),
        ))
    }
}
impl InsnOpcode for FCVTZS_SVE_Zd_S_D_SVE_Pg3_P_M_SVE_Zn_S_S {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCVTZS_SVE_Zd_S_H_SVE_Pg3_P_M_SVE_Zn_S_H {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcvtzs",
        aliases: &[],
        opcode: 0x655aa000,
        mask: 0xffffe000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::FCVTZS_SVE_Zd_S_H_SVE_Pg3_P_M_SVE_Zn_S_H(
            FCVTZS_SVE_Zd_S_H_SVE_Pg3_P_M_SVE_Zn_S_H::from(bits),
        ))
    }
}
impl InsnOpcode for FCVTZS_SVE_Zd_S_H_SVE_Pg3_P_M_SVE_Zn_S_H {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCVTZS_SVE_Zd_S_D_SVE_Pg3_P_M_SVE_Zn_S_H {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcvtzs",
        aliases: &[],
        opcode: 0x655ea000,
        mask: 0xffffe000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::FCVTZS_SVE_Zd_S_D_SVE_Pg3_P_M_SVE_Zn_S_H(
            FCVTZS_SVE_Zd_S_D_SVE_Pg3_P_M_SVE_Zn_S_H::from(bits),
        ))
    }
}
impl InsnOpcode for FCVTZS_SVE_Zd_S_D_SVE_Pg3_P_M_SVE_Zn_S_H {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCVTZS_SVE_Zd_S_D_SVE_Pg3_P_M_SVE_Zn_S_D {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcvtzs",
        aliases: &[],
        opcode: 0x65dea000,
        mask: 0xffffe000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::FCVTZS_SVE_Zd_S_D_SVE_Pg3_P_M_SVE_Zn_S_D(
            FCVTZS_SVE_Zd_S_D_SVE_Pg3_P_M_SVE_Zn_S_D::from(bits),
        ))
    }
}
impl InsnOpcode for FCVTZS_SVE_Zd_S_D_SVE_Pg3_P_M_SVE_Zn_S_D {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCVTZS_Rd_Fn_FBITS {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcvtzs",
        aliases: &[],
        opcode: 0x1ed80000,
        mask: 0x7fff0000,
        class: InsnClass::FLOAT2FIX,
        feature_set: InsnFeatureSet::FP_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fn,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::FBITS,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[
                    InsnOperandQualifier::imm_1_32,
                    InsnOperandQualifier::imm_1_64,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::scale,
                    lsb: 10,
                    width: 6,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_FPTYPE_FIELD.bits() | InsnFlags::HAS_SF_FIELD.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::FLOAT2FIX(FLOAT2FIX::FCVTZS_Rd_Fn_FBITS(FCVTZS_Rd_Fn_FBITS::from(
            bits,
        )))
    }
}
impl InsnOpcode for FCVTZS_Rd_Fn_FBITS {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCVTZS_Rd_W_Fn_S_D_FBITS_imm_1_32 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcvtzs",
        aliases: &[],
        opcode: 0x1e180000,
        mask: 0x7f3f0000,
        class: InsnClass::FLOAT2FIX,
        feature_set: InsnFeatureSet::FP,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fn,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_D, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::FBITS,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[
                    InsnOperandQualifier::imm_1_32,
                    InsnOperandQualifier::imm_1_32,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::scale,
                    lsb: 10,
                    width: 6,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_FPTYPE_FIELD.bits() | InsnFlags::HAS_SF_FIELD.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::FLOAT2FIX(FLOAT2FIX::FCVTZS_Rd_W_Fn_S_D_FBITS_imm_1_32(
            FCVTZS_Rd_W_Fn_S_D_FBITS_imm_1_32::from(bits),
        ))
    }
}
impl InsnOpcode for FCVTZS_Rd_W_Fn_S_D_FBITS_imm_1_32 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCVTZS_Vd_Vn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcvtzs",
        aliases: &[],
        opcode: 0xea1b800,
        mask: 0xbfbffc00,
        class: InsnClass::ASIMDMISC,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDMISC(ASIMDMISC::FCVTZS_Vd_Vn(FCVTZS_Vd_Vn::from(bits)))
    }
}
impl InsnOpcode for FCVTZS_Vd_Vn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCVTZS_Vd_V_4H_Vn_V_4H {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcvtzs",
        aliases: &[],
        opcode: 0xef9b800,
        mask: 0xbffffc00,
        class: InsnClass::ASIMDMISC,
        feature_set: InsnFeatureSet::SIMD_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDMISC(ASIMDMISC::FCVTZS_Vd_V_4H_Vn_V_4H(
            FCVTZS_Vd_V_4H_Vn_V_4H::from(bits),
        ))
    }
}
impl InsnOpcode for FCVTZS_Vd_V_4H_Vn_V_4H {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCVTZS_Rd_Fn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcvtzs",
        aliases: &[],
        opcode: 0x1ef80000,
        mask: 0x7ffffc00,
        class: InsnClass::FLOAT2INT,
        feature_set: InsnFeatureSet::FP_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fn,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_FPTYPE_FIELD.bits() | InsnFlags::HAS_SF_FIELD.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::FLOAT2INT(FLOAT2INT::FCVTZS_Rd_Fn(FCVTZS_Rd_Fn::from(bits)))
    }
}
impl InsnOpcode for FCVTZS_Rd_Fn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCVTZS_Rd_W_Fn_S_D {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcvtzs",
        aliases: &[],
        opcode: 0x1e380000,
        mask: 0x7f3ffc00,
        class: InsnClass::FLOAT2INT,
        feature_set: InsnFeatureSet::FP,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fn,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_FPTYPE_FIELD.bits() | InsnFlags::HAS_SF_FIELD.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::FLOAT2INT(FLOAT2INT::FCVTZS_Rd_W_Fn_S_D(FCVTZS_Rd_W_Fn_S_D::from(
            bits,
        )))
    }
}
impl InsnOpcode for FCVTZS_Rd_W_Fn_S_D {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCVTZS_Sd_Sn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcvtzs",
        aliases: &[],
        opcode: 0x5ea1b800,
        mask: 0xffbffc00,
        class: InsnClass::ASISDMISC,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMD_SCALAR_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDMISC(ASISDMISC::FCVTZS_Sd_Sn(FCVTZS_Sd_Sn::from(bits)))
    }
}
impl InsnOpcode for FCVTZS_Sd_Sn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCVTZS_Sd_S_H_Sn_S_H {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcvtzs",
        aliases: &[],
        opcode: 0x5ef9b800,
        mask: 0xfffffc00,
        class: InsnClass::ASISDMISC,
        feature_set: InsnFeatureSet::SIMD_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMD_SCALAR_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDMISC(ASISDMISC::FCVTZS_Sd_S_H_Sn_S_H(FCVTZS_Sd_S_H_Sn_S_H::from(
            bits,
        )))
    }
}
impl InsnOpcode for FCVTZS_Sd_S_H_Sn_S_H {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCVTZS_Vd_Vn_IMM_VLSR {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcvtzs",
        aliases: &[],
        opcode: 0xf10fc00,
        mask: 0xbf90fc00,
        class: InsnClass::ASIMDSHF,
        feature_set: InsnFeatureSet::SIMD_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::IMM_VLSR,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSHF(ASIMDSHF::FCVTZS_Vd_Vn_IMM_VLSR(
            FCVTZS_Vd_Vn_IMM_VLSR::from(bits),
        ))
    }
}
impl InsnOpcode for FCVTZS_Vd_Vn_IMM_VLSR {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCVTZS_Vd_V_2S_Vn_V_2S_IMM_VLSR_V_2S {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcvtzs",
        aliases: &[],
        opcode: 0xf00fc00,
        mask: 0xbf80fc00,
        class: InsnClass::ASIMDSHF,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::IMM_VLSR,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[InsnOperandQualifier::V_2S, InsnOperandQualifier::V_4S],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSHF(ASIMDSHF::FCVTZS_Vd_V_2S_Vn_V_2S_IMM_VLSR_V_2S(
            FCVTZS_Vd_V_2S_Vn_V_2S_IMM_VLSR_V_2S::from(bits),
        ))
    }
}
impl InsnOpcode for FCVTZS_Vd_V_2S_Vn_V_2S_IMM_VLSR_V_2S {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCVTZS_Sd_Sn_IMM_VLSR {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcvtzs",
        aliases: &[],
        opcode: 0x5f10fc00,
        mask: 0xff90fc00,
        class: InsnClass::ASISDSHF,
        feature_set: InsnFeatureSet::SIMD_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::IMM_VLSR,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDSHF(ASISDSHF::FCVTZS_Sd_Sn_IMM_VLSR(
            FCVTZS_Sd_Sn_IMM_VLSR::from(bits),
        ))
    }
}
impl InsnOpcode for FCVTZS_Sd_Sn_IMM_VLSR {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCVTZS_Sd_S_S_Sn_S_S_IMM_VLSR_S_S {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcvtzs",
        aliases: &[],
        opcode: 0x5f00fc00,
        mask: 0xff80fc00,
        class: InsnClass::ASISDSHF,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::IMM_VLSR,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDSHF(ASISDSHF::FCVTZS_Sd_S_S_Sn_S_S_IMM_VLSR_S_S(
            FCVTZS_Sd_S_S_Sn_S_S_IMM_VLSR_S_S::from(bits),
        ))
    }
}
impl InsnOpcode for FCVTZS_Sd_S_S_Sn_S_S_IMM_VLSR_S_S {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCVTZU_SME_Zdnx2_SME_Znx2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcvtzu",
        aliases: &[],
        opcode: 0xc121e020,
        mask: 0xfffffc21,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn2,
                    lsb: 1,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn2,
                    lsb: 6,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::FCVTZU_SME_Zdnx2_SME_Znx2(
            FCVTZU_SME_Zdnx2_SME_Znx2::from(bits),
        ))
    }
}
impl InsnOpcode for FCVTZU_SME_Zdnx2_SME_Znx2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCVTZU_SME_Zdnx4_SME_Znx4 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcvtzu",
        aliases: &[],
        opcode: 0xc131e020,
        mask: 0xfffffc63,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn4,
                    lsb: 2,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn4,
                    lsb: 7,
                    width: 3,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::FCVTZU_SME_Zdnx4_SME_Znx4(
            FCVTZU_SME_Zdnx4_SME_Znx4::from(bits),
        ))
    }
}
impl InsnOpcode for FCVTZU_SME_Zdnx4_SME_Znx4 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCVTZU_SVE_Zd_SVE_Pg3_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcvtzu",
        aliases: &[],
        opcode: 0x65d9a000,
        mask: 0xffffe000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::FCVTZU_SVE_Zd_SVE_Pg3_SVE_Zn(
            FCVTZU_SVE_Zd_SVE_Pg3_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for FCVTZU_SVE_Zd_SVE_Pg3_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCVTZU_SVE_Zd_S_S_SVE_Pg3_P_M_SVE_Zn_S_S {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcvtzu",
        aliases: &[],
        opcode: 0x659da000,
        mask: 0xffffe000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::FCVTZU_SVE_Zd_S_S_SVE_Pg3_P_M_SVE_Zn_S_S(
            FCVTZU_SVE_Zd_S_S_SVE_Pg3_P_M_SVE_Zn_S_S::from(bits),
        ))
    }
}
impl InsnOpcode for FCVTZU_SVE_Zd_S_S_SVE_Pg3_P_M_SVE_Zn_S_S {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCVTZU_SVE_Zd_S_S_SVE_Pg3_P_M_SVE_Zn_S_H {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcvtzu",
        aliases: &[],
        opcode: 0x655da000,
        mask: 0xffffe000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::FCVTZU_SVE_Zd_S_S_SVE_Pg3_P_M_SVE_Zn_S_H(
            FCVTZU_SVE_Zd_S_S_SVE_Pg3_P_M_SVE_Zn_S_H::from(bits),
        ))
    }
}
impl InsnOpcode for FCVTZU_SVE_Zd_S_S_SVE_Pg3_P_M_SVE_Zn_S_H {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCVTZU_SVE_Zd_S_D_SVE_Pg3_P_M_SVE_Zn_S_S {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcvtzu",
        aliases: &[],
        opcode: 0x65dda000,
        mask: 0xffffe000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::FCVTZU_SVE_Zd_S_D_SVE_Pg3_P_M_SVE_Zn_S_S(
            FCVTZU_SVE_Zd_S_D_SVE_Pg3_P_M_SVE_Zn_S_S::from(bits),
        ))
    }
}
impl InsnOpcode for FCVTZU_SVE_Zd_S_D_SVE_Pg3_P_M_SVE_Zn_S_S {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCVTZU_SVE_Zd_S_H_SVE_Pg3_P_M_SVE_Zn_S_H {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcvtzu",
        aliases: &[],
        opcode: 0x655ba000,
        mask: 0xffffe000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::FCVTZU_SVE_Zd_S_H_SVE_Pg3_P_M_SVE_Zn_S_H(
            FCVTZU_SVE_Zd_S_H_SVE_Pg3_P_M_SVE_Zn_S_H::from(bits),
        ))
    }
}
impl InsnOpcode for FCVTZU_SVE_Zd_S_H_SVE_Pg3_P_M_SVE_Zn_S_H {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCVTZU_SVE_Zd_S_D_SVE_Pg3_P_M_SVE_Zn_S_H {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcvtzu",
        aliases: &[],
        opcode: 0x655fa000,
        mask: 0xffffe000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::FCVTZU_SVE_Zd_S_D_SVE_Pg3_P_M_SVE_Zn_S_H(
            FCVTZU_SVE_Zd_S_D_SVE_Pg3_P_M_SVE_Zn_S_H::from(bits),
        ))
    }
}
impl InsnOpcode for FCVTZU_SVE_Zd_S_D_SVE_Pg3_P_M_SVE_Zn_S_H {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCVTZU_SVE_Zd_S_D_SVE_Pg3_P_M_SVE_Zn_S_D {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcvtzu",
        aliases: &[],
        opcode: 0x65dfa000,
        mask: 0xffffe000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::FCVTZU_SVE_Zd_S_D_SVE_Pg3_P_M_SVE_Zn_S_D(
            FCVTZU_SVE_Zd_S_D_SVE_Pg3_P_M_SVE_Zn_S_D::from(bits),
        ))
    }
}
impl InsnOpcode for FCVTZU_SVE_Zd_S_D_SVE_Pg3_P_M_SVE_Zn_S_D {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCVTZU_Rd_Fn_FBITS {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcvtzu",
        aliases: &[],
        opcode: 0x1ed90000,
        mask: 0x7fff0000,
        class: InsnClass::FLOAT2FIX,
        feature_set: InsnFeatureSet::FP_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fn,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::FBITS,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[
                    InsnOperandQualifier::imm_1_32,
                    InsnOperandQualifier::imm_1_64,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::scale,
                    lsb: 10,
                    width: 6,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_FPTYPE_FIELD.bits() | InsnFlags::HAS_SF_FIELD.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::FLOAT2FIX(FLOAT2FIX::FCVTZU_Rd_Fn_FBITS(FCVTZU_Rd_Fn_FBITS::from(
            bits,
        )))
    }
}
impl InsnOpcode for FCVTZU_Rd_Fn_FBITS {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCVTZU_Rd_W_Fn_S_D_FBITS_imm_1_32 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcvtzu",
        aliases: &[],
        opcode: 0x1e190000,
        mask: 0x7f3f0000,
        class: InsnClass::FLOAT2FIX,
        feature_set: InsnFeatureSet::FP,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fn,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_D, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::FBITS,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[
                    InsnOperandQualifier::imm_1_32,
                    InsnOperandQualifier::imm_1_32,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::scale,
                    lsb: 10,
                    width: 6,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_FPTYPE_FIELD.bits() | InsnFlags::HAS_SF_FIELD.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::FLOAT2FIX(FLOAT2FIX::FCVTZU_Rd_W_Fn_S_D_FBITS_imm_1_32(
            FCVTZU_Rd_W_Fn_S_D_FBITS_imm_1_32::from(bits),
        ))
    }
}
impl InsnOpcode for FCVTZU_Rd_W_Fn_S_D_FBITS_imm_1_32 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCVTZU_Vd_Vn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcvtzu",
        aliases: &[],
        opcode: 0x2ea1b800,
        mask: 0xbfbffc00,
        class: InsnClass::ASIMDMISC,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDMISC(ASIMDMISC::FCVTZU_Vd_Vn(FCVTZU_Vd_Vn::from(bits)))
    }
}
impl InsnOpcode for FCVTZU_Vd_Vn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCVTZU_Vd_V_4H_Vn_V_4H {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcvtzu",
        aliases: &[],
        opcode: 0x2ef9b800,
        mask: 0xbffffc00,
        class: InsnClass::ASIMDMISC,
        feature_set: InsnFeatureSet::SIMD_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDMISC(ASIMDMISC::FCVTZU_Vd_V_4H_Vn_V_4H(
            FCVTZU_Vd_V_4H_Vn_V_4H::from(bits),
        ))
    }
}
impl InsnOpcode for FCVTZU_Vd_V_4H_Vn_V_4H {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCVTZU_Rd_Fn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcvtzu",
        aliases: &[],
        opcode: 0x1ef90000,
        mask: 0x7ffffc00,
        class: InsnClass::FLOAT2INT,
        feature_set: InsnFeatureSet::FP_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fn,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_FPTYPE_FIELD.bits() | InsnFlags::HAS_SF_FIELD.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::FLOAT2INT(FLOAT2INT::FCVTZU_Rd_Fn(FCVTZU_Rd_Fn::from(bits)))
    }
}
impl InsnOpcode for FCVTZU_Rd_Fn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCVTZU_Rd_W_Fn_S_D {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcvtzu",
        aliases: &[],
        opcode: 0x1e390000,
        mask: 0x7f3ffc00,
        class: InsnClass::FLOAT2INT,
        feature_set: InsnFeatureSet::FP,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fn,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_FPTYPE_FIELD.bits() | InsnFlags::HAS_SF_FIELD.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::FLOAT2INT(FLOAT2INT::FCVTZU_Rd_W_Fn_S_D(FCVTZU_Rd_W_Fn_S_D::from(
            bits,
        )))
    }
}
impl InsnOpcode for FCVTZU_Rd_W_Fn_S_D {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCVTZU_Sd_Sn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcvtzu",
        aliases: &[],
        opcode: 0x7ea1b800,
        mask: 0xffbffc00,
        class: InsnClass::ASISDMISC,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMD_SCALAR_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDMISC(ASISDMISC::FCVTZU_Sd_Sn(FCVTZU_Sd_Sn::from(bits)))
    }
}
impl InsnOpcode for FCVTZU_Sd_Sn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCVTZU_Sd_S_H_Sn_S_H {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcvtzu",
        aliases: &[],
        opcode: 0x7ef9b800,
        mask: 0xfffffc00,
        class: InsnClass::ASISDMISC,
        feature_set: InsnFeatureSet::SIMD_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMD_SCALAR_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDMISC(ASISDMISC::FCVTZU_Sd_S_H_Sn_S_H(FCVTZU_Sd_S_H_Sn_S_H::from(
            bits,
        )))
    }
}
impl InsnOpcode for FCVTZU_Sd_S_H_Sn_S_H {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCVTZU_Vd_Vn_IMM_VLSR {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcvtzu",
        aliases: &[],
        opcode: 0x2f10fc00,
        mask: 0xbf90fc00,
        class: InsnClass::ASIMDSHF,
        feature_set: InsnFeatureSet::SIMD_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::IMM_VLSR,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSHF(ASIMDSHF::FCVTZU_Vd_Vn_IMM_VLSR(
            FCVTZU_Vd_Vn_IMM_VLSR::from(bits),
        ))
    }
}
impl InsnOpcode for FCVTZU_Vd_Vn_IMM_VLSR {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCVTZU_Vd_V_2S_Vn_V_2S_IMM_VLSR_V_2S {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcvtzu",
        aliases: &[],
        opcode: 0x2f00fc00,
        mask: 0xbf80fc00,
        class: InsnClass::ASIMDSHF,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::IMM_VLSR,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[InsnOperandQualifier::V_2S, InsnOperandQualifier::V_4S],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSHF(ASIMDSHF::FCVTZU_Vd_V_2S_Vn_V_2S_IMM_VLSR_V_2S(
            FCVTZU_Vd_V_2S_Vn_V_2S_IMM_VLSR_V_2S::from(bits),
        ))
    }
}
impl InsnOpcode for FCVTZU_Vd_V_2S_Vn_V_2S_IMM_VLSR_V_2S {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCVTZU_Sd_Sn_IMM_VLSR {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcvtzu",
        aliases: &[],
        opcode: 0x7f10fc00,
        mask: 0xff90fc00,
        class: InsnClass::ASISDSHF,
        feature_set: InsnFeatureSet::SIMD_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::IMM_VLSR,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDSHF(ASISDSHF::FCVTZU_Sd_Sn_IMM_VLSR(
            FCVTZU_Sd_Sn_IMM_VLSR::from(bits),
        ))
    }
}
impl InsnOpcode for FCVTZU_Sd_Sn_IMM_VLSR {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FCVTZU_Sd_S_S_Sn_S_S_IMM_VLSR_S_S {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fcvtzu",
        aliases: &[],
        opcode: 0x7f00fc00,
        mask: 0xff80fc00,
        class: InsnClass::ASISDSHF,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::IMM_VLSR,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDSHF(ASISDSHF::FCVTZU_Sd_S_S_Sn_S_S_IMM_VLSR_S_S(
            FCVTZU_Sd_S_S_Sn_S_S_IMM_VLSR_S_S::from(bits),
        ))
    }
}
impl InsnOpcode for FCVTZU_Sd_S_S_Sn_S_S_IMM_VLSR_S_S {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FDIV_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fdiv",
        aliases: &[],
        opcode: 0x650d8000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_5,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_5,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::FDIV_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(
            FDIV_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5::from(bits),
        ))
    }
}
impl InsnOpcode for FDIV_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FDIV_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fdiv",
        aliases: &[],
        opcode: 0x2e403c00,
        mask: 0xbfe0fc00,
        class: InsnClass::ASIMDSAME,
        feature_set: InsnFeatureSet::SIMD_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSAME(ASIMDSAME::FDIV_Vd_Vn_Vm(FDIV_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for FDIV_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FDIV_Vd_V_2S_Vn_V_2S_Vm_V_2S {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fdiv",
        aliases: &[],
        opcode: 0x2e20fc00,
        mask: 0xbfa0fc00,
        class: InsnClass::ASIMDSAME,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSAME(ASIMDSAME::FDIV_Vd_V_2S_Vn_V_2S_Vm_V_2S(
            FDIV_Vd_V_2S_Vn_V_2S_Vm_V_2S::from(bits),
        ))
    }
}
impl InsnOpcode for FDIV_Vd_V_2S_Vn_V_2S_Vm_V_2S {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FDIV_Fd_Fn_Fm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fdiv",
        aliases: &[],
        opcode: 0x1ee01800,
        mask: 0xffe0fc00,
        class: InsnClass::FLOATDP2,
        feature_set: InsnFeatureSet::FP_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Fd,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fn,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fm,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_FPTYPE_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::FLOATDP2(FLOATDP2::FDIV_Fd_Fn_Fm(FDIV_Fd_Fn_Fm::from(bits)))
    }
}
impl InsnOpcode for FDIV_Fd_Fn_Fm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FDIV_Fd_S_S_Fn_S_S_Fm_S_S {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fdiv",
        aliases: &[],
        opcode: 0x1e201800,
        mask: 0xff20fc00,
        class: InsnClass::FLOATDP2,
        feature_set: InsnFeatureSet::FP,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Fd,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fn,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fm,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_FPTYPE_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::FLOATDP2(FLOATDP2::FDIV_Fd_S_S_Fn_S_S_Fm_S_S(
            FDIV_Fd_S_S_Fn_S_S_Fm_S_S::from(bits),
        ))
    }
}
impl InsnOpcode for FDIV_Fd_S_S_Fn_S_S_Fm_S_S {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FDIVR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fdivr",
        aliases: &[],
        opcode: 0x650c8000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_5,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_5,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::FDIVR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(
            FDIVR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5::from(bits),
        ))
    }
}
impl InsnOpcode for FDIVR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fdot",
        aliases: &[],
        opcode: 0xc1501008,
        mask: 0xfff09038,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off3_0,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_0,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn2,
                    lsb: 6,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm_INDEX2,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zm,
                        lsb: 16,
                        width: 4,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_10,
                        lsb: 10,
                        width: 2,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::FDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2(
            FDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2::from(bits),
        ))
    }
}
impl InsnOpcode for FDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fdot",
        aliases: &[],
        opcode: 0xc1509008,
        mask: 0xfff09078,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off3_0,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_0,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn4,
                    lsb: 7,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm_INDEX2,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zm,
                        lsb: 16,
                        width: 4,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_10,
                        lsb: 10,
                        width: 2,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_4.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::FDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2(
            FDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2::from(bits),
        ))
    }
}
impl InsnOpcode for FDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FDOT_SME_ZA_array_off3_0_SVE_ZnxN_SME_Zm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fdot",
        aliases: &[],
        opcode: 0xc1201000,
        mask: 0xfff09c18,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off3_0,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_0,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ZnxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm,
                    lsb: 16,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::FDOT_SME_ZA_array_off3_0_SVE_ZnxN_SME_Zm(
            FDOT_SME_ZA_array_off3_0_SVE_ZnxN_SME_Zm::from(bits),
        ))
    }
}
impl InsnOpcode for FDOT_SME_ZA_array_off3_0_SVE_ZnxN_SME_Zm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FDOT_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_H_SME_Zm_S_H {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fdot",
        aliases: &[],
        opcode: 0xc1301000,
        mask: 0xfff09c18,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off3_0,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_0,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ZnxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm,
                    lsb: 16,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_4.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(
            SME_MISC::FDOT_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_H_SME_Zm_S_H(
                FDOT_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_H_SME_Zm_S_H::from(bits),
            ),
        )
    }
}
impl InsnOpcode for FDOT_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_H_SME_Zm_S_H {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zmx2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fdot",
        aliases: &[],
        opcode: 0xc1a01000,
        mask: 0xffe19c38,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off3_0,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_0,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn2,
                    lsb: 6,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zmx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm2,
                    lsb: 17,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::FDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zmx2(
            FDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zmx2::from(bits),
        ))
    }
}
impl InsnOpcode for FDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zmx2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zmx4 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fdot",
        aliases: &[],
        opcode: 0xc1a11000,
        mask: 0xffe39c78,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off3_0,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_0,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn4,
                    lsb: 7,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zmx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm4,
                    lsb: 18,
                    width: 3,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_4.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::FDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zmx4(
            FDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zmx4::from(bits),
        ))
    }
}
impl InsnOpcode for FDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zmx4 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FDOT_SVE_Zd_SVE_Zn_SVE_Zm3_19_INDEX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fdot",
        aliases: &[],
        opcode: 0x64204000,
        mask: 0xffe0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm3_19_INDEX,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_19,
                        lsb: 19,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_imm3,
                        lsb: 16,
                        width: 3,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::FDOT_SVE_Zd_SVE_Zn_SVE_Zm3_19_INDEX(
            FDOT_SVE_Zd_SVE_Zn_SVE_Zm3_19_INDEX::from(bits),
        ))
    }
}
impl InsnOpcode for FDOT_SVE_Zd_SVE_Zn_SVE_Zm3_19_INDEX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FDOT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fdot",
        aliases: &[],
        opcode: 0x64208000,
        mask: 0xffe0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::FDOT_SVE_Zd_SVE_Zn_SVE_Zm_16(
            FDOT_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for FDOT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FDUP_SVE_Zd_SVE_FPIMM8 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fdup",
        aliases: &[],
        opcode: 0x2539c000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_FPIMM8,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_imm8,
                    lsb: 5,
                    width: 8,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ALIAS.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::FDUP_SVE_Zd_SVE_FPIMM8(
            FDUP_SVE_Zd_SVE_FPIMM8::from(bits),
        ))
    }
}
impl InsnOpcode for FDUP_SVE_Zd_SVE_FPIMM8 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FEXPA_SVE_Zd_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fexpa",
        aliases: &[],
        opcode: 0x420b800,
        mask: 0xff3ffc00,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::FEXPA_SVE_Zd_SVE_Zn(
            FEXPA_SVE_Zd_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for FEXPA_SVE_Zd_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FJCVTZS_Rd_Fn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fjcvtzs",
        aliases: &[],
        opcode: 0x1e7e0000,
        mask: 0xfffffc00,
        class: InsnClass::FLOAT2INT,
        feature_set: InsnFeatureSet::JSCVT,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fn,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::FLOAT2INT(FLOAT2INT::FJCVTZS_Rd_Fn(FJCVTZS_Rd_Fn::from(bits)))
    }
}
impl InsnOpcode for FJCVTZS_Rd_Fn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FLOGB_SVE_Zd_SVE_Pg3_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "flogb",
        aliases: &[],
        opcode: 0x6518a000,
        mask: 0xfff9e000,
        class: InsnClass::SVE_SIZE_HSD2,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M, InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD2(SVE_SIZE_HSD2::FLOGB_SVE_Zd_SVE_Pg3_SVE_Zn(
            FLOGB_SVE_Zd_SVE_Pg3_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for FLOGB_SVE_Zd_SVE_Pg3_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMAD_SVE_Zd_SVE_Pg3_SVE_Zm_5_SVE_Za_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmad",
        aliases: &[],
        opcode: 0x65208000,
        mask: 0xff20e000,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_5,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_5,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Za_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Za_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::FMAD_SVE_Zd_SVE_Pg3_SVE_Zm_5_SVE_Za_16(
            FMAD_SVE_Zd_SVE_Pg3_SVE_Zm_5_SVE_Za_16::from(bits),
        ))
    }
}
impl InsnOpcode for FMAD_SVE_Zd_SVE_Pg3_SVE_Zm_5_SVE_Za_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMADD_Fd_Fn_Fm_Fa {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmadd",
        aliases: &[],
        opcode: 0x1fc00000,
        mask: 0xffe08000,
        class: InsnClass::FLOATDP3,
        feature_set: InsnFeatureSet::FP_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Fd,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fn,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fm,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fa,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Ra,
                    lsb: 10,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_FPTYPE_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::FLOATDP3(FLOATDP3::FMADD_Fd_Fn_Fm_Fa(FMADD_Fd_Fn_Fm_Fa::from(bits)))
    }
}
impl InsnOpcode for FMADD_Fd_Fn_Fm_Fa {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMADD_Fd_S_S_Fn_S_S_Fm_S_S_Fa_S_S {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmadd",
        aliases: &[],
        opcode: 0x1f000000,
        mask: 0xff208000,
        class: InsnClass::FLOATDP3,
        feature_set: InsnFeatureSet::FP,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Fd,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fn,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fm,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fa,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Ra,
                    lsb: 10,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_FPTYPE_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::FLOATDP3(FLOATDP3::FMADD_Fd_S_S_Fn_S_S_Fm_S_S_Fa_S_S(
            FMADD_Fd_S_S_Fn_S_S_Fm_S_S_Fa_S_S::from(bits),
        ))
    }
}
impl InsnOpcode for FMADD_Fd_S_S_Fn_S_S_Fm_S_S_Fa_S_S {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMAX_SME_Zdnx2_SME_Zdnx2_SME_Zm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmax",
        aliases: &[],
        opcode: 0xc120a100,
        mask: 0xff30ffe1,
        class: InsnClass::SME_SIZE_22_HSD,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn2,
                    lsb: 1,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn2,
                    lsb: 1,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm,
                    lsb: 16,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_SIZE_22_HSD(SME_SIZE_22_HSD::FMAX_SME_Zdnx2_SME_Zdnx2_SME_Zm(
            FMAX_SME_Zdnx2_SME_Zdnx2_SME_Zm::from(bits),
        ))
    }
}
impl InsnOpcode for FMAX_SME_Zdnx2_SME_Zdnx2_SME_Zm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMAX_SME_Zdnx2_SME_Zdnx2_SME_Zmx2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmax",
        aliases: &[],
        opcode: 0xc120b100,
        mask: 0xff21ffe1,
        class: InsnClass::SME_SIZE_22_HSD,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn2,
                    lsb: 1,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn2,
                    lsb: 1,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zmx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm2,
                    lsb: 17,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_SIZE_22_HSD(SME_SIZE_22_HSD::FMAX_SME_Zdnx2_SME_Zdnx2_SME_Zmx2(
            FMAX_SME_Zdnx2_SME_Zdnx2_SME_Zmx2::from(bits),
        ))
    }
}
impl InsnOpcode for FMAX_SME_Zdnx2_SME_Zdnx2_SME_Zmx2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMAX_SME_Zdnx4_SME_Zdnx4_SME_Zm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmax",
        aliases: &[],
        opcode: 0xc120a900,
        mask: 0xff30ffe3,
        class: InsnClass::SME_SIZE_22_HSD,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn4,
                    lsb: 2,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn4,
                    lsb: 2,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm,
                    lsb: 16,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_SIZE_22_HSD(SME_SIZE_22_HSD::FMAX_SME_Zdnx4_SME_Zdnx4_SME_Zm(
            FMAX_SME_Zdnx4_SME_Zdnx4_SME_Zm::from(bits),
        ))
    }
}
impl InsnOpcode for FMAX_SME_Zdnx4_SME_Zdnx4_SME_Zm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMAX_SME_Zdnx4_SME_Zdnx4_SME_Zmx4 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmax",
        aliases: &[],
        opcode: 0xc120b900,
        mask: 0xff23ffe3,
        class: InsnClass::SME_SIZE_22_HSD,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn4,
                    lsb: 2,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn4,
                    lsb: 2,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zmx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm4,
                    lsb: 18,
                    width: 3,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_SIZE_22_HSD(SME_SIZE_22_HSD::FMAX_SME_Zdnx4_SME_Zdnx4_SME_Zmx4(
            FMAX_SME_Zdnx4_SME_Zdnx4_SME_Zmx4::from(bits),
        ))
    }
}
impl InsnOpcode for FMAX_SME_Zdnx4_SME_Zdnx4_SME_Zmx4 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMAX_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmax",
        aliases: &[],
        opcode: 0x65068000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_5,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_5,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::FMAX_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(
            FMAX_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5::from(bits),
        ))
    }
}
impl InsnOpcode for FMAX_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMAX_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_I1_ZERO_ONE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmax",
        aliases: &[],
        opcode: 0x651e8000,
        mask: 0xff3fe3c0,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_I1_ZERO_ONE,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_i1,
                    lsb: 5,
                    width: 1,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::FMAX_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_I1_ZERO_ONE(
            FMAX_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_I1_ZERO_ONE::from(bits),
        ))
    }
}
impl InsnOpcode for FMAX_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_I1_ZERO_ONE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMAX_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmax",
        aliases: &[],
        opcode: 0xe403400,
        mask: 0xbfe0fc00,
        class: InsnClass::ASIMDSAME,
        feature_set: InsnFeatureSet::SIMD_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSAME(ASIMDSAME::FMAX_Vd_Vn_Vm(FMAX_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for FMAX_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMAX_Vd_V_2S_Vn_V_2S_Vm_V_2S {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmax",
        aliases: &[],
        opcode: 0xe20f400,
        mask: 0xbfa0fc00,
        class: InsnClass::ASIMDSAME,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSAME(ASIMDSAME::FMAX_Vd_V_2S_Vn_V_2S_Vm_V_2S(
            FMAX_Vd_V_2S_Vn_V_2S_Vm_V_2S::from(bits),
        ))
    }
}
impl InsnOpcode for FMAX_Vd_V_2S_Vn_V_2S_Vm_V_2S {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMAX_Fd_Fn_Fm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmax",
        aliases: &[],
        opcode: 0x1ee04800,
        mask: 0xffe0fc00,
        class: InsnClass::FLOATDP2,
        feature_set: InsnFeatureSet::FP_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Fd,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fn,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fm,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_FPTYPE_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::FLOATDP2(FLOATDP2::FMAX_Fd_Fn_Fm(FMAX_Fd_Fn_Fm::from(bits)))
    }
}
impl InsnOpcode for FMAX_Fd_Fn_Fm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMAX_Fd_S_S_Fn_S_S_Fm_S_S {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmax",
        aliases: &[],
        opcode: 0x1e204800,
        mask: 0xff20fc00,
        class: InsnClass::FLOATDP2,
        feature_set: InsnFeatureSet::FP,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Fd,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fn,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fm,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_FPTYPE_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::FLOATDP2(FLOATDP2::FMAX_Fd_S_S_Fn_S_S_Fm_S_S(
            FMAX_Fd_S_S_Fn_S_S_Fm_S_S::from(bits),
        ))
    }
}
impl InsnOpcode for FMAX_Fd_S_S_Fn_S_S_Fm_S_S {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMAXNM_SME_Zdnx2_SME_Zdnx2_SME_Zm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmaxnm",
        aliases: &[],
        opcode: 0xc120a120,
        mask: 0xff30ffe1,
        class: InsnClass::SME_SIZE_22_HSD,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn2,
                    lsb: 1,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn2,
                    lsb: 1,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm,
                    lsb: 16,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_SIZE_22_HSD(SME_SIZE_22_HSD::FMAXNM_SME_Zdnx2_SME_Zdnx2_SME_Zm(
            FMAXNM_SME_Zdnx2_SME_Zdnx2_SME_Zm::from(bits),
        ))
    }
}
impl InsnOpcode for FMAXNM_SME_Zdnx2_SME_Zdnx2_SME_Zm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMAXNM_SME_Zdnx2_SME_Zdnx2_SME_Zmx2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmaxnm",
        aliases: &[],
        opcode: 0xc120b120,
        mask: 0xff21ffe1,
        class: InsnClass::SME_SIZE_22_HSD,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn2,
                    lsb: 1,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn2,
                    lsb: 1,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zmx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm2,
                    lsb: 17,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_SIZE_22_HSD(SME_SIZE_22_HSD::FMAXNM_SME_Zdnx2_SME_Zdnx2_SME_Zmx2(
            FMAXNM_SME_Zdnx2_SME_Zdnx2_SME_Zmx2::from(bits),
        ))
    }
}
impl InsnOpcode for FMAXNM_SME_Zdnx2_SME_Zdnx2_SME_Zmx2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMAXNM_SME_Zdnx4_SME_Zdnx4_SME_Zm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmaxnm",
        aliases: &[],
        opcode: 0xc120a920,
        mask: 0xff30ffe3,
        class: InsnClass::SME_SIZE_22_HSD,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn4,
                    lsb: 2,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn4,
                    lsb: 2,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm,
                    lsb: 16,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_SIZE_22_HSD(SME_SIZE_22_HSD::FMAXNM_SME_Zdnx4_SME_Zdnx4_SME_Zm(
            FMAXNM_SME_Zdnx4_SME_Zdnx4_SME_Zm::from(bits),
        ))
    }
}
impl InsnOpcode for FMAXNM_SME_Zdnx4_SME_Zdnx4_SME_Zm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMAXNM_SME_Zdnx4_SME_Zdnx4_SME_Zmx4 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmaxnm",
        aliases: &[],
        opcode: 0xc120b920,
        mask: 0xff23ffe3,
        class: InsnClass::SME_SIZE_22_HSD,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn4,
                    lsb: 2,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn4,
                    lsb: 2,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zmx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm4,
                    lsb: 18,
                    width: 3,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_SIZE_22_HSD(SME_SIZE_22_HSD::FMAXNM_SME_Zdnx4_SME_Zdnx4_SME_Zmx4(
            FMAXNM_SME_Zdnx4_SME_Zdnx4_SME_Zmx4::from(bits),
        ))
    }
}
impl InsnOpcode for FMAXNM_SME_Zdnx4_SME_Zdnx4_SME_Zmx4 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMAXNM_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmaxnm",
        aliases: &[],
        opcode: 0x65048000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_5,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_5,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::FMAXNM_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(
            FMAXNM_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5::from(bits),
        ))
    }
}
impl InsnOpcode for FMAXNM_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMAXNM_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_I1_ZERO_ONE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmaxnm",
        aliases: &[],
        opcode: 0x651c8000,
        mask: 0xff3fe3c0,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_I1_ZERO_ONE,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_i1,
                    lsb: 5,
                    width: 1,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::FMAXNM_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_I1_ZERO_ONE(
            FMAXNM_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_I1_ZERO_ONE::from(bits),
        ))
    }
}
impl InsnOpcode for FMAXNM_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_I1_ZERO_ONE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMAXNM_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmaxnm",
        aliases: &[],
        opcode: 0xe400400,
        mask: 0xbfe0fc00,
        class: InsnClass::ASIMDSAME,
        feature_set: InsnFeatureSet::SIMD_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSAME(ASIMDSAME::FMAXNM_Vd_Vn_Vm(FMAXNM_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for FMAXNM_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMAXNM_Vd_V_2S_Vn_V_2S_Vm_V_2S {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmaxnm",
        aliases: &[],
        opcode: 0xe20c400,
        mask: 0xbfa0fc00,
        class: InsnClass::ASIMDSAME,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSAME(ASIMDSAME::FMAXNM_Vd_V_2S_Vn_V_2S_Vm_V_2S(
            FMAXNM_Vd_V_2S_Vn_V_2S_Vm_V_2S::from(bits),
        ))
    }
}
impl InsnOpcode for FMAXNM_Vd_V_2S_Vn_V_2S_Vm_V_2S {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMAXNM_Fd_Fn_Fm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmaxnm",
        aliases: &[],
        opcode: 0x1ee06800,
        mask: 0xffe0fc00,
        class: InsnClass::FLOATDP2,
        feature_set: InsnFeatureSet::FP_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Fd,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fn,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fm,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_FPTYPE_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::FLOATDP2(FLOATDP2::FMAXNM_Fd_Fn_Fm(FMAXNM_Fd_Fn_Fm::from(bits)))
    }
}
impl InsnOpcode for FMAXNM_Fd_Fn_Fm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMAXNM_Fd_S_S_Fn_S_S_Fm_S_S {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmaxnm",
        aliases: &[],
        opcode: 0x1e206800,
        mask: 0xff20fc00,
        class: InsnClass::FLOATDP2,
        feature_set: InsnFeatureSet::FP,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Fd,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fn,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fm,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_FPTYPE_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::FLOATDP2(FLOATDP2::FMAXNM_Fd_S_S_Fn_S_S_Fm_S_S(
            FMAXNM_Fd_S_S_Fn_S_S_Fm_S_S::from(bits),
        ))
    }
}
impl InsnOpcode for FMAXNM_Fd_S_S_Fn_S_S_Fm_S_S {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMAXNMP_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmaxnmp",
        aliases: &[],
        opcode: 0x64148000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::FMAXNMP_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(
            FMAXNMP_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for FMAXNMP_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMAXNMP_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmaxnmp",
        aliases: &[],
        opcode: 0x2e400400,
        mask: 0xbfe0fc00,
        class: InsnClass::ASIMDSAME,
        feature_set: InsnFeatureSet::SIMD_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSAME(ASIMDSAME::FMAXNMP_Vd_Vn_Vm(FMAXNMP_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for FMAXNMP_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMAXNMP_Vd_V_2S_Vn_V_2S_Vm_V_2S {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmaxnmp",
        aliases: &[],
        opcode: 0x2e20c400,
        mask: 0xbfa0fc00,
        class: InsnClass::ASIMDSAME,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSAME(ASIMDSAME::FMAXNMP_Vd_V_2S_Vn_V_2S_Vm_V_2S(
            FMAXNMP_Vd_V_2S_Vn_V_2S_Vm_V_2S::from(bits),
        ))
    }
}
impl InsnOpcode for FMAXNMP_Vd_V_2S_Vn_V_2S_Vm_V_2S {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMAXNMP_Sd_Vn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmaxnmp",
        aliases: &[],
        opcode: 0x5e30c800,
        mask: 0xfffffc00,
        class: InsnClass::ASISDPAIR,
        feature_set: InsnFeatureSet::SIMD_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDPAIR(ASISDPAIR::FMAXNMP_Sd_Vn(FMAXNMP_Sd_Vn::from(bits)))
    }
}
impl InsnOpcode for FMAXNMP_Sd_Vn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMAXNMP_Sd_S_S_Vn_V_2S {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmaxnmp",
        aliases: &[],
        opcode: 0x7e30c800,
        mask: 0xffbffc00,
        class: InsnClass::ASISDPAIR,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDPAIR(ASISDPAIR::FMAXNMP_Sd_S_S_Vn_V_2S(
            FMAXNMP_Sd_S_S_Vn_V_2S::from(bits),
        ))
    }
}
impl InsnOpcode for FMAXNMP_Sd_S_S_Vn_V_2S {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMAXNMQV_Vd_SVE_Pg3_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmaxnmqv",
        aliases: &[],
        opcode: 0x6414a000,
        mask: 0xff3fe000,
        class: InsnClass::SVE2_URQVS,
        feature_set: InsnFeatureSet::SVE2P1,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8H, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE2_URQVS(SVE2_URQVS::FMAXNMQV_Vd_SVE_Pg3_SVE_Zn(
            FMAXNMQV_Vd_SVE_Pg3_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for FMAXNMQV_Vd_SVE_Pg3_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMAXNMV_SVE_Vd_SVE_Pg3_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmaxnmv",
        aliases: &[],
        opcode: 0x65042000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Vd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::FMAXNMV_SVE_Vd_SVE_Pg3_SVE_Zn(
            FMAXNMV_SVE_Vd_SVE_Pg3_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for FMAXNMV_SVE_Vd_SVE_Pg3_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMAXNMV_Fd_Vn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmaxnmv",
        aliases: &[],
        opcode: 0xe30c800,
        mask: 0xbffffc00,
        class: InsnClass::ASIMDALL,
        feature_set: InsnFeatureSet::SIMD_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Fd,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDALL(ASIMDALL::FMAXNMV_Fd_Vn(FMAXNMV_Fd_Vn::from(bits)))
    }
}
impl InsnOpcode for FMAXNMV_Fd_Vn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMAXNMV_Fd_S_S_Vn_V_4S {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmaxnmv",
        aliases: &[],
        opcode: 0x2e30c800,
        mask: 0xbfbffc00,
        class: InsnClass::ASIMDALL,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Fd,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDALL(ASIMDALL::FMAXNMV_Fd_S_S_Vn_V_4S(
            FMAXNMV_Fd_S_S_Vn_V_4S::from(bits),
        ))
    }
}
impl InsnOpcode for FMAXNMV_Fd_S_S_Vn_V_4S {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMAXP_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmaxp",
        aliases: &[],
        opcode: 0x64168000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::FMAXP_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(
            FMAXP_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for FMAXP_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMAXP_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmaxp",
        aliases: &[],
        opcode: 0x2e403400,
        mask: 0xbfe0fc00,
        class: InsnClass::ASIMDSAME,
        feature_set: InsnFeatureSet::SIMD_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSAME(ASIMDSAME::FMAXP_Vd_Vn_Vm(FMAXP_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for FMAXP_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMAXP_Vd_V_2S_Vn_V_2S_Vm_V_2S {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmaxp",
        aliases: &[],
        opcode: 0x2e20f400,
        mask: 0xbfa0fc00,
        class: InsnClass::ASIMDSAME,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSAME(ASIMDSAME::FMAXP_Vd_V_2S_Vn_V_2S_Vm_V_2S(
            FMAXP_Vd_V_2S_Vn_V_2S_Vm_V_2S::from(bits),
        ))
    }
}
impl InsnOpcode for FMAXP_Vd_V_2S_Vn_V_2S_Vm_V_2S {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMAXP_Sd_Vn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmaxp",
        aliases: &[],
        opcode: 0x5e30f800,
        mask: 0xfffffc00,
        class: InsnClass::ASISDPAIR,
        feature_set: InsnFeatureSet::SIMD_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDPAIR(ASISDPAIR::FMAXP_Sd_Vn(FMAXP_Sd_Vn::from(bits)))
    }
}
impl InsnOpcode for FMAXP_Sd_Vn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMAXP_Sd_S_S_Vn_V_2S {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmaxp",
        aliases: &[],
        opcode: 0x7e30f800,
        mask: 0xffbffc00,
        class: InsnClass::ASISDPAIR,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDPAIR(ASISDPAIR::FMAXP_Sd_S_S_Vn_V_2S(FMAXP_Sd_S_S_Vn_V_2S::from(
            bits,
        )))
    }
}
impl InsnOpcode for FMAXP_Sd_S_S_Vn_V_2S {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMAXQV_Vd_SVE_Pg3_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmaxqv",
        aliases: &[],
        opcode: 0x6416a000,
        mask: 0xff3fe000,
        class: InsnClass::SVE2_URQVS,
        feature_set: InsnFeatureSet::SVE2P1,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8H, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE2_URQVS(SVE2_URQVS::FMAXQV_Vd_SVE_Pg3_SVE_Zn(
            FMAXQV_Vd_SVE_Pg3_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for FMAXQV_Vd_SVE_Pg3_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMAXV_SVE_Vd_SVE_Pg3_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmaxv",
        aliases: &[],
        opcode: 0x65062000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Vd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::FMAXV_SVE_Vd_SVE_Pg3_SVE_Zn(
            FMAXV_SVE_Vd_SVE_Pg3_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for FMAXV_SVE_Vd_SVE_Pg3_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMAXV_Fd_Vn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmaxv",
        aliases: &[],
        opcode: 0xe30f800,
        mask: 0xbffffc00,
        class: InsnClass::ASIMDALL,
        feature_set: InsnFeatureSet::SIMD_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Fd,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDALL(ASIMDALL::FMAXV_Fd_Vn(FMAXV_Fd_Vn::from(bits)))
    }
}
impl InsnOpcode for FMAXV_Fd_Vn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMAXV_Fd_S_S_Vn_V_4S {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmaxv",
        aliases: &[],
        opcode: 0x2e30f800,
        mask: 0xbfbffc00,
        class: InsnClass::ASIMDALL,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Fd,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDALL(ASIMDALL::FMAXV_Fd_S_S_Vn_V_4S(FMAXV_Fd_S_S_Vn_V_4S::from(
            bits,
        )))
    }
}
impl InsnOpcode for FMAXV_Fd_S_S_Vn_V_4S {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMIN_SME_Zdnx2_SME_Zdnx2_SME_Zm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmin",
        aliases: &[],
        opcode: 0xc120a101,
        mask: 0xff30ffe1,
        class: InsnClass::SME_SIZE_22_HSD,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn2,
                    lsb: 1,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn2,
                    lsb: 1,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm,
                    lsb: 16,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_SIZE_22_HSD(SME_SIZE_22_HSD::FMIN_SME_Zdnx2_SME_Zdnx2_SME_Zm(
            FMIN_SME_Zdnx2_SME_Zdnx2_SME_Zm::from(bits),
        ))
    }
}
impl InsnOpcode for FMIN_SME_Zdnx2_SME_Zdnx2_SME_Zm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMIN_SME_Zdnx2_SME_Zdnx2_SME_Zmx2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmin",
        aliases: &[],
        opcode: 0xc120b101,
        mask: 0xff21ffe1,
        class: InsnClass::SME_SIZE_22_HSD,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn2,
                    lsb: 1,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn2,
                    lsb: 1,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zmx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm2,
                    lsb: 17,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_SIZE_22_HSD(SME_SIZE_22_HSD::FMIN_SME_Zdnx2_SME_Zdnx2_SME_Zmx2(
            FMIN_SME_Zdnx2_SME_Zdnx2_SME_Zmx2::from(bits),
        ))
    }
}
impl InsnOpcode for FMIN_SME_Zdnx2_SME_Zdnx2_SME_Zmx2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMIN_SME_Zdnx4_SME_Zdnx4_SME_Zm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmin",
        aliases: &[],
        opcode: 0xc120a901,
        mask: 0xff30ffe3,
        class: InsnClass::SME_SIZE_22_HSD,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn4,
                    lsb: 2,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn4,
                    lsb: 2,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm,
                    lsb: 16,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_SIZE_22_HSD(SME_SIZE_22_HSD::FMIN_SME_Zdnx4_SME_Zdnx4_SME_Zm(
            FMIN_SME_Zdnx4_SME_Zdnx4_SME_Zm::from(bits),
        ))
    }
}
impl InsnOpcode for FMIN_SME_Zdnx4_SME_Zdnx4_SME_Zm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMIN_SME_Zdnx4_SME_Zdnx4_SME_Zmx4 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmin",
        aliases: &[],
        opcode: 0xc120b901,
        mask: 0xff23ffe3,
        class: InsnClass::SME_SIZE_22_HSD,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn4,
                    lsb: 2,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn4,
                    lsb: 2,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zmx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm4,
                    lsb: 18,
                    width: 3,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_SIZE_22_HSD(SME_SIZE_22_HSD::FMIN_SME_Zdnx4_SME_Zdnx4_SME_Zmx4(
            FMIN_SME_Zdnx4_SME_Zdnx4_SME_Zmx4::from(bits),
        ))
    }
}
impl InsnOpcode for FMIN_SME_Zdnx4_SME_Zdnx4_SME_Zmx4 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMIN_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmin",
        aliases: &[],
        opcode: 0x65078000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_5,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_5,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::FMIN_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(
            FMIN_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5::from(bits),
        ))
    }
}
impl InsnOpcode for FMIN_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMIN_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_I1_ZERO_ONE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmin",
        aliases: &[],
        opcode: 0x651f8000,
        mask: 0xff3fe3c0,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_I1_ZERO_ONE,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_i1,
                    lsb: 5,
                    width: 1,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::FMIN_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_I1_ZERO_ONE(
            FMIN_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_I1_ZERO_ONE::from(bits),
        ))
    }
}
impl InsnOpcode for FMIN_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_I1_ZERO_ONE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMIN_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmin",
        aliases: &[],
        opcode: 0xec03400,
        mask: 0xbfe0fc00,
        class: InsnClass::ASIMDSAME,
        feature_set: InsnFeatureSet::SIMD_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSAME(ASIMDSAME::FMIN_Vd_Vn_Vm(FMIN_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for FMIN_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMIN_Vd_V_2S_Vn_V_2S_Vm_V_2S {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmin",
        aliases: &[],
        opcode: 0xea0f400,
        mask: 0xbfa0fc00,
        class: InsnClass::ASIMDSAME,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSAME(ASIMDSAME::FMIN_Vd_V_2S_Vn_V_2S_Vm_V_2S(
            FMIN_Vd_V_2S_Vn_V_2S_Vm_V_2S::from(bits),
        ))
    }
}
impl InsnOpcode for FMIN_Vd_V_2S_Vn_V_2S_Vm_V_2S {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMIN_Fd_Fn_Fm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmin",
        aliases: &[],
        opcode: 0x1ee05800,
        mask: 0xffe0fc00,
        class: InsnClass::FLOATDP2,
        feature_set: InsnFeatureSet::FP_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Fd,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fn,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fm,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_FPTYPE_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::FLOATDP2(FLOATDP2::FMIN_Fd_Fn_Fm(FMIN_Fd_Fn_Fm::from(bits)))
    }
}
impl InsnOpcode for FMIN_Fd_Fn_Fm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMIN_Fd_S_S_Fn_S_S_Fm_S_S {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmin",
        aliases: &[],
        opcode: 0x1e205800,
        mask: 0xff20fc00,
        class: InsnClass::FLOATDP2,
        feature_set: InsnFeatureSet::FP,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Fd,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fn,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fm,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_FPTYPE_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::FLOATDP2(FLOATDP2::FMIN_Fd_S_S_Fn_S_S_Fm_S_S(
            FMIN_Fd_S_S_Fn_S_S_Fm_S_S::from(bits),
        ))
    }
}
impl InsnOpcode for FMIN_Fd_S_S_Fn_S_S_Fm_S_S {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMINNM_SME_Zdnx2_SME_Zdnx2_SME_Zm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fminnm",
        aliases: &[],
        opcode: 0xc120a121,
        mask: 0xff30ffe1,
        class: InsnClass::SME_SIZE_22_HSD,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn2,
                    lsb: 1,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn2,
                    lsb: 1,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm,
                    lsb: 16,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_SIZE_22_HSD(SME_SIZE_22_HSD::FMINNM_SME_Zdnx2_SME_Zdnx2_SME_Zm(
            FMINNM_SME_Zdnx2_SME_Zdnx2_SME_Zm::from(bits),
        ))
    }
}
impl InsnOpcode for FMINNM_SME_Zdnx2_SME_Zdnx2_SME_Zm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMINNM_SME_Zdnx2_SME_Zdnx2_SME_Zmx2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fminnm",
        aliases: &[],
        opcode: 0xc120b121,
        mask: 0xff21ffe1,
        class: InsnClass::SME_SIZE_22_HSD,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn2,
                    lsb: 1,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn2,
                    lsb: 1,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zmx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm2,
                    lsb: 17,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_SIZE_22_HSD(SME_SIZE_22_HSD::FMINNM_SME_Zdnx2_SME_Zdnx2_SME_Zmx2(
            FMINNM_SME_Zdnx2_SME_Zdnx2_SME_Zmx2::from(bits),
        ))
    }
}
impl InsnOpcode for FMINNM_SME_Zdnx2_SME_Zdnx2_SME_Zmx2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMINNM_SME_Zdnx4_SME_Zdnx4_SME_Zm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fminnm",
        aliases: &[],
        opcode: 0xc120a921,
        mask: 0xff30ffe3,
        class: InsnClass::SME_SIZE_22_HSD,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn4,
                    lsb: 2,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn4,
                    lsb: 2,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm,
                    lsb: 16,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_SIZE_22_HSD(SME_SIZE_22_HSD::FMINNM_SME_Zdnx4_SME_Zdnx4_SME_Zm(
            FMINNM_SME_Zdnx4_SME_Zdnx4_SME_Zm::from(bits),
        ))
    }
}
impl InsnOpcode for FMINNM_SME_Zdnx4_SME_Zdnx4_SME_Zm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMINNM_SME_Zdnx4_SME_Zdnx4_SME_Zmx4 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fminnm",
        aliases: &[],
        opcode: 0xc120b921,
        mask: 0xff23ffe3,
        class: InsnClass::SME_SIZE_22_HSD,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn4,
                    lsb: 2,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn4,
                    lsb: 2,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zmx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm4,
                    lsb: 18,
                    width: 3,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_SIZE_22_HSD(SME_SIZE_22_HSD::FMINNM_SME_Zdnx4_SME_Zdnx4_SME_Zmx4(
            FMINNM_SME_Zdnx4_SME_Zdnx4_SME_Zmx4::from(bits),
        ))
    }
}
impl InsnOpcode for FMINNM_SME_Zdnx4_SME_Zdnx4_SME_Zmx4 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMINNM_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fminnm",
        aliases: &[],
        opcode: 0x65058000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_5,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_5,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::FMINNM_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(
            FMINNM_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5::from(bits),
        ))
    }
}
impl InsnOpcode for FMINNM_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMINNM_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_I1_ZERO_ONE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fminnm",
        aliases: &[],
        opcode: 0x651d8000,
        mask: 0xff3fe3c0,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_I1_ZERO_ONE,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_i1,
                    lsb: 5,
                    width: 1,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::FMINNM_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_I1_ZERO_ONE(
            FMINNM_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_I1_ZERO_ONE::from(bits),
        ))
    }
}
impl InsnOpcode for FMINNM_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_I1_ZERO_ONE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMINNM_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fminnm",
        aliases: &[],
        opcode: 0xec00400,
        mask: 0xbfe0fc00,
        class: InsnClass::ASIMDSAME,
        feature_set: InsnFeatureSet::SIMD_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSAME(ASIMDSAME::FMINNM_Vd_Vn_Vm(FMINNM_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for FMINNM_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMINNM_Vd_V_2S_Vn_V_2S_Vm_V_2S {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fminnm",
        aliases: &[],
        opcode: 0xea0c400,
        mask: 0xbfa0fc00,
        class: InsnClass::ASIMDSAME,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSAME(ASIMDSAME::FMINNM_Vd_V_2S_Vn_V_2S_Vm_V_2S(
            FMINNM_Vd_V_2S_Vn_V_2S_Vm_V_2S::from(bits),
        ))
    }
}
impl InsnOpcode for FMINNM_Vd_V_2S_Vn_V_2S_Vm_V_2S {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMINNM_Fd_Fn_Fm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fminnm",
        aliases: &[],
        opcode: 0x1ee07800,
        mask: 0xffe0fc00,
        class: InsnClass::FLOATDP2,
        feature_set: InsnFeatureSet::FP_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Fd,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fn,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fm,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_FPTYPE_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::FLOATDP2(FLOATDP2::FMINNM_Fd_Fn_Fm(FMINNM_Fd_Fn_Fm::from(bits)))
    }
}
impl InsnOpcode for FMINNM_Fd_Fn_Fm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMINNM_Fd_S_S_Fn_S_S_Fm_S_S {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fminnm",
        aliases: &[],
        opcode: 0x1e207800,
        mask: 0xff20fc00,
        class: InsnClass::FLOATDP2,
        feature_set: InsnFeatureSet::FP,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Fd,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fn,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fm,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_FPTYPE_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::FLOATDP2(FLOATDP2::FMINNM_Fd_S_S_Fn_S_S_Fm_S_S(
            FMINNM_Fd_S_S_Fn_S_S_Fm_S_S::from(bits),
        ))
    }
}
impl InsnOpcode for FMINNM_Fd_S_S_Fn_S_S_Fm_S_S {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMINNMP_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fminnmp",
        aliases: &[],
        opcode: 0x64158000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::FMINNMP_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(
            FMINNMP_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for FMINNMP_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMINNMP_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fminnmp",
        aliases: &[],
        opcode: 0x2ec00400,
        mask: 0xbfe0fc00,
        class: InsnClass::ASIMDSAME,
        feature_set: InsnFeatureSet::SIMD_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSAME(ASIMDSAME::FMINNMP_Vd_Vn_Vm(FMINNMP_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for FMINNMP_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMINNMP_Vd_V_2S_Vn_V_2S_Vm_V_2S {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fminnmp",
        aliases: &[],
        opcode: 0x2ea0c400,
        mask: 0xbfa0fc00,
        class: InsnClass::ASIMDSAME,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSAME(ASIMDSAME::FMINNMP_Vd_V_2S_Vn_V_2S_Vm_V_2S(
            FMINNMP_Vd_V_2S_Vn_V_2S_Vm_V_2S::from(bits),
        ))
    }
}
impl InsnOpcode for FMINNMP_Vd_V_2S_Vn_V_2S_Vm_V_2S {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMINNMP_Sd_Vn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fminnmp",
        aliases: &[],
        opcode: 0x5eb0c800,
        mask: 0xfffffc00,
        class: InsnClass::ASISDPAIR,
        feature_set: InsnFeatureSet::SIMD_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDPAIR(ASISDPAIR::FMINNMP_Sd_Vn(FMINNMP_Sd_Vn::from(bits)))
    }
}
impl InsnOpcode for FMINNMP_Sd_Vn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMINNMP_Sd_S_S_Vn_V_2S {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fminnmp",
        aliases: &[],
        opcode: 0x7eb0c800,
        mask: 0xffbffc00,
        class: InsnClass::ASISDPAIR,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDPAIR(ASISDPAIR::FMINNMP_Sd_S_S_Vn_V_2S(
            FMINNMP_Sd_S_S_Vn_V_2S::from(bits),
        ))
    }
}
impl InsnOpcode for FMINNMP_Sd_S_S_Vn_V_2S {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMINNMQV_Vd_SVE_Pg3_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fminnmqv",
        aliases: &[],
        opcode: 0x6415a000,
        mask: 0xff3fe000,
        class: InsnClass::SVE2_URQVS,
        feature_set: InsnFeatureSet::SVE2P1,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8H, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE2_URQVS(SVE2_URQVS::FMINNMQV_Vd_SVE_Pg3_SVE_Zn(
            FMINNMQV_Vd_SVE_Pg3_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for FMINNMQV_Vd_SVE_Pg3_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMINNMV_SVE_Vd_SVE_Pg3_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fminnmv",
        aliases: &[],
        opcode: 0x65052000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Vd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::FMINNMV_SVE_Vd_SVE_Pg3_SVE_Zn(
            FMINNMV_SVE_Vd_SVE_Pg3_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for FMINNMV_SVE_Vd_SVE_Pg3_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMINNMV_Fd_Vn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fminnmv",
        aliases: &[],
        opcode: 0xeb0c800,
        mask: 0xbffffc00,
        class: InsnClass::ASIMDALL,
        feature_set: InsnFeatureSet::SIMD_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Fd,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDALL(ASIMDALL::FMINNMV_Fd_Vn(FMINNMV_Fd_Vn::from(bits)))
    }
}
impl InsnOpcode for FMINNMV_Fd_Vn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMINNMV_Fd_S_S_Vn_V_4S {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fminnmv",
        aliases: &[],
        opcode: 0x2eb0c800,
        mask: 0xbfbffc00,
        class: InsnClass::ASIMDALL,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Fd,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDALL(ASIMDALL::FMINNMV_Fd_S_S_Vn_V_4S(
            FMINNMV_Fd_S_S_Vn_V_4S::from(bits),
        ))
    }
}
impl InsnOpcode for FMINNMV_Fd_S_S_Vn_V_4S {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMINP_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fminp",
        aliases: &[],
        opcode: 0x64178000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::FMINP_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(
            FMINP_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for FMINP_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMINP_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fminp",
        aliases: &[],
        opcode: 0x2ec03400,
        mask: 0xbfe0fc00,
        class: InsnClass::ASIMDSAME,
        feature_set: InsnFeatureSet::SIMD_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSAME(ASIMDSAME::FMINP_Vd_Vn_Vm(FMINP_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for FMINP_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMINP_Vd_V_2S_Vn_V_2S_Vm_V_2S {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fminp",
        aliases: &[],
        opcode: 0x2ea0f400,
        mask: 0xbfa0fc00,
        class: InsnClass::ASIMDSAME,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSAME(ASIMDSAME::FMINP_Vd_V_2S_Vn_V_2S_Vm_V_2S(
            FMINP_Vd_V_2S_Vn_V_2S_Vm_V_2S::from(bits),
        ))
    }
}
impl InsnOpcode for FMINP_Vd_V_2S_Vn_V_2S_Vm_V_2S {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMINP_Sd_Vn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fminp",
        aliases: &[],
        opcode: 0x5eb0f800,
        mask: 0xfffffc00,
        class: InsnClass::ASISDPAIR,
        feature_set: InsnFeatureSet::SIMD_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDPAIR(ASISDPAIR::FMINP_Sd_Vn(FMINP_Sd_Vn::from(bits)))
    }
}
impl InsnOpcode for FMINP_Sd_Vn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMINP_Sd_S_S_Vn_V_2S {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fminp",
        aliases: &[],
        opcode: 0x7eb0f800,
        mask: 0xffbffc00,
        class: InsnClass::ASISDPAIR,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDPAIR(ASISDPAIR::FMINP_Sd_S_S_Vn_V_2S(FMINP_Sd_S_S_Vn_V_2S::from(
            bits,
        )))
    }
}
impl InsnOpcode for FMINP_Sd_S_S_Vn_V_2S {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMINQV_Vd_SVE_Pg3_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fminqv",
        aliases: &[],
        opcode: 0x6417a000,
        mask: 0xff3fe000,
        class: InsnClass::SVE2_URQVS,
        feature_set: InsnFeatureSet::SVE2P1,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8H, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE2_URQVS(SVE2_URQVS::FMINQV_Vd_SVE_Pg3_SVE_Zn(
            FMINQV_Vd_SVE_Pg3_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for FMINQV_Vd_SVE_Pg3_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMINV_SVE_Vd_SVE_Pg3_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fminv",
        aliases: &[],
        opcode: 0x65072000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Vd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::FMINV_SVE_Vd_SVE_Pg3_SVE_Zn(
            FMINV_SVE_Vd_SVE_Pg3_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for FMINV_SVE_Vd_SVE_Pg3_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMINV_Fd_Vn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fminv",
        aliases: &[],
        opcode: 0xeb0f800,
        mask: 0xbffffc00,
        class: InsnClass::ASIMDALL,
        feature_set: InsnFeatureSet::SIMD_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Fd,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDALL(ASIMDALL::FMINV_Fd_Vn(FMINV_Fd_Vn::from(bits)))
    }
}
impl InsnOpcode for FMINV_Fd_Vn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMINV_Fd_S_S_Vn_V_4S {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fminv",
        aliases: &[],
        opcode: 0x2eb0f800,
        mask: 0xbfbffc00,
        class: InsnClass::ASIMDALL,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Fd,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDALL(ASIMDALL::FMINV_Fd_S_S_Vn_V_4S(FMINV_Fd_S_S_Vn_V_4S::from(
            bits,
        )))
    }
}
impl InsnOpcode for FMINV_Fd_S_S_Vn_V_4S {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMLA_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmla",
        aliases: &[],
        opcode: 0xc1500000,
        mask: 0xfff09038,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off3_0,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_0,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn2,
                    lsb: 6,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm_INDEX2,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zm,
                        lsb: 16,
                        width: 4,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_10,
                        lsb: 10,
                        width: 2,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::FMLA_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2(
            FMLA_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2::from(bits),
        ))
    }
}
impl InsnOpcode for FMLA_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMLA_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmla",
        aliases: &[],
        opcode: 0xc1508000,
        mask: 0xfff09078,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off3_0,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_0,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn4,
                    lsb: 7,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm_INDEX2,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zm,
                        lsb: 16,
                        width: 4,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_10,
                        lsb: 10,
                        width: 2,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_4.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::FMLA_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2(
            FMLA_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2::from(bits),
        ))
    }
}
impl InsnOpcode for FMLA_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMLA_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX1 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmla",
        aliases: &[],
        opcode: 0xc1d00000,
        mask: 0xfff09838,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2_F64F64,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off3_0,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_0,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn2,
                    lsb: 6,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm_INDEX1,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zm,
                        lsb: 16,
                        width: 4,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm1_10,
                        lsb: 10,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::FMLA_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX1(
            FMLA_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX1::from(bits),
        ))
    }
}
impl InsnOpcode for FMLA_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX1 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMLA_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX1 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmla",
        aliases: &[],
        opcode: 0xc1d08000,
        mask: 0xfff09878,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2_F64F64,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off3_0,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_0,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn4,
                    lsb: 7,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm_INDEX1,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zm,
                        lsb: 16,
                        width: 4,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm1_10,
                        lsb: 10,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_4.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::FMLA_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX1(
            FMLA_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX1::from(bits),
        ))
    }
}
impl InsnOpcode for FMLA_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX1 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMLA_SME_ZA_array_off3_0_SVE_ZnxN_SME_Zm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmla",
        aliases: &[],
        opcode: 0xc1201800,
        mask: 0xffb09c18,
        class: InsnClass::SME_FP_SD,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off3_0,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_0,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ZnxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm,
                    lsb: 16,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_FP_SD(SME_FP_SD::FMLA_SME_ZA_array_off3_0_SVE_ZnxN_SME_Zm(
            FMLA_SME_ZA_array_off3_0_SVE_ZnxN_SME_Zm::from(bits),
        ))
    }
}
impl InsnOpcode for FMLA_SME_ZA_array_off3_0_SVE_ZnxN_SME_Zm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMLA_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_S_SME_Zm_S_S {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmla",
        aliases: &[],
        opcode: 0xc1301800,
        mask: 0xffb09c18,
        class: InsnClass::SME_FP_SD,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off3_0,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_0,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ZnxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm,
                    lsb: 16,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_4.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_FP_SD(
            SME_FP_SD::FMLA_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_S_SME_Zm_S_S(
                FMLA_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_S_SME_Zm_S_S::from(bits),
            ),
        )
    }
}
impl InsnOpcode for FMLA_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_S_SME_Zm_S_S {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMLA_SME_ZA_array_off3_0_SME_Znx2_SME_Zmx2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmla",
        aliases: &[],
        opcode: 0xc1a01800,
        mask: 0xffa19c38,
        class: InsnClass::SME_FP_SD,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off3_0,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_0,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn2,
                    lsb: 6,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zmx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm2,
                    lsb: 17,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_FP_SD(SME_FP_SD::FMLA_SME_ZA_array_off3_0_SME_Znx2_SME_Zmx2(
            FMLA_SME_ZA_array_off3_0_SME_Znx2_SME_Zmx2::from(bits),
        ))
    }
}
impl InsnOpcode for FMLA_SME_ZA_array_off3_0_SME_Znx2_SME_Zmx2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMLA_SME_ZA_array_off3_0_SME_Znx4_SME_Zmx4 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmla",
        aliases: &[],
        opcode: 0xc1a11800,
        mask: 0xffa39c78,
        class: InsnClass::SME_FP_SD,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off3_0,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_0,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn4,
                    lsb: 7,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zmx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm4,
                    lsb: 18,
                    width: 3,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_4.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_FP_SD(SME_FP_SD::FMLA_SME_ZA_array_off3_0_SME_Znx4_SME_Zmx4(
            FMLA_SME_ZA_array_off3_0_SME_Znx4_SME_Zmx4::from(bits),
        ))
    }
}
impl InsnOpcode for FMLA_SME_ZA_array_off3_0_SME_Znx4_SME_Zmx4 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMLA_SVE_Zd_SVE_Zn_SVE_Zm3_22_INDEX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmla",
        aliases: &[],
        opcode: 0x64200000,
        mask: 0xffa0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm3_22_INDEX,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_i3h,
                        lsb: 22,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zm_16,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::FMLA_SVE_Zd_SVE_Zn_SVE_Zm3_22_INDEX(
            FMLA_SVE_Zd_SVE_Zn_SVE_Zm3_22_INDEX::from(bits),
        ))
    }
}
impl InsnOpcode for FMLA_SVE_Zd_SVE_Zn_SVE_Zm3_22_INDEX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMLA_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmla",
        aliases: &[],
        opcode: 0x64a00000,
        mask: 0xffe0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm3_INDEX,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::FMLA_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX(
            FMLA_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX::from(bits),
        ))
    }
}
impl InsnOpcode for FMLA_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMLA_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmla",
        aliases: &[],
        opcode: 0x64e00000,
        mask: 0xffe0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm4_INDEX,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::FMLA_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX(
            FMLA_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX::from(bits),
        ))
    }
}
impl InsnOpcode for FMLA_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMLA_SVE_Zd_SVE_Pg3_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmla",
        aliases: &[],
        opcode: 0x65200000,
        mask: 0xff20e000,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::FMLA_SVE_Zd_SVE_Pg3_SVE_Zn_SVE_Zm_16(
            FMLA_SVE_Zd_SVE_Pg3_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for FMLA_SVE_Zd_SVE_Pg3_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMLA_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmla",
        aliases: &[],
        opcode: 0xe400c00,
        mask: 0xbfe0fc00,
        class: InsnClass::ASIMDSAME,
        feature_set: InsnFeatureSet::SIMD_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSAME(ASIMDSAME::FMLA_Vd_Vn_Vm(FMLA_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for FMLA_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMLA_Vd_V_2S_Vn_V_2S_Vm_V_2S {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmla",
        aliases: &[],
        opcode: 0xe20cc00,
        mask: 0xbfa0fc00,
        class: InsnClass::ASIMDSAME,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSAME(ASIMDSAME::FMLA_Vd_V_2S_Vn_V_2S_Vm_V_2S(
            FMLA_Vd_V_2S_Vn_V_2S_Vm_V_2S::from(bits),
        ))
    }
}
impl InsnOpcode for FMLA_Vd_V_2S_Vn_V_2S_Vm_V_2S {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMLA_Vd_Vn_Em16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmla",
        aliases: &[],
        opcode: 0xf001000,
        mask: 0xbfc0f400,
        class: InsnClass::ASIMDELEM,
        feature_set: InsnFeatureSet::SIMD_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Em16,
                class: InsnOperandClass::SIMD_ELEMENT,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDELEM(ASIMDELEM::FMLA_Vd_Vn_Em16(FMLA_Vd_Vn_Em16::from(bits)))
    }
}
impl InsnOpcode for FMLA_Vd_Vn_Em16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMLA_Vd_Vn_Em {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmla",
        aliases: &[],
        opcode: 0xf801000,
        mask: 0xbf80f400,
        class: InsnClass::ASIMDELEM,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Em,
                class: InsnOperandClass::SIMD_ELEMENT,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDELEM(ASIMDELEM::FMLA_Vd_Vn_Em(FMLA_Vd_Vn_Em::from(bits)))
    }
}
impl InsnOpcode for FMLA_Vd_Vn_Em {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMLA_Sd_Sn_Em16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmla",
        aliases: &[],
        opcode: 0x5f001000,
        mask: 0xffc0f400,
        class: InsnClass::ASISDELEM,
        feature_set: InsnFeatureSet::SIMD_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Em16,
                class: InsnOperandClass::SIMD_ELEMENT,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMD_SCALAR_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDELEM(ASISDELEM::FMLA_Sd_Sn_Em16(FMLA_Sd_Sn_Em16::from(bits)))
    }
}
impl InsnOpcode for FMLA_Sd_Sn_Em16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMLA_Sd_Sn_Em {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmla",
        aliases: &[],
        opcode: 0x5f801000,
        mask: 0xff80f400,
        class: InsnClass::ASISDELEM,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Em,
                class: InsnOperandClass::SIMD_ELEMENT,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMD_SCALAR_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDELEM(ASISDELEM::FMLA_Sd_Sn_Em(FMLA_Sd_Sn_Em::from(bits)))
    }
}
impl InsnOpcode for FMLA_Sd_Sn_Em {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMLAL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm_INDEX3_10 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmlal",
        aliases: &[],
        opcode: 0xc1801000,
        mask: 0xfff01018,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off3x2,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_0,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm_INDEX3_10,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zm,
                        lsb: 16,
                        width: 4,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm1_15,
                        lsb: 15,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_10,
                        lsb: 10,
                        width: 2,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::FMLAL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm_INDEX3_10(
            FMLAL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm_INDEX3_10::from(bits),
        ))
    }
}
impl InsnOpcode for FMLAL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm_INDEX3_10 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMLAL_SME_ZA_array_off2x2_SME_Znx2_SME_Zm_INDEX3_2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmlal",
        aliases: &[],
        opcode: 0xc1901000,
        mask: 0xfff09038,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off2x2,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_0,
                        lsb: 0,
                        width: 2,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn2,
                    lsb: 6,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm_INDEX3_2,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zm,
                        lsb: 16,
                        width: 4,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_10,
                        lsb: 10,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm1_2,
                        lsb: 2,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(
            SME_MISC::FMLAL_SME_ZA_array_off2x2_SME_Znx2_SME_Zm_INDEX3_2(
                FMLAL_SME_ZA_array_off2x2_SME_Znx2_SME_Zm_INDEX3_2::from(bits),
            ),
        )
    }
}
impl InsnOpcode for FMLAL_SME_ZA_array_off2x2_SME_Znx2_SME_Zm_INDEX3_2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMLAL_SME_ZA_array_off2x2_SME_Znx4_SME_Zm_INDEX3_2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmlal",
        aliases: &[],
        opcode: 0xc1909000,
        mask: 0xfff09078,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off2x2,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_0,
                        lsb: 0,
                        width: 2,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn4,
                    lsb: 7,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm_INDEX3_2,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zm,
                        lsb: 16,
                        width: 4,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_10,
                        lsb: 10,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm1_2,
                        lsb: 2,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_4.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(
            SME_MISC::FMLAL_SME_ZA_array_off2x2_SME_Znx4_SME_Zm_INDEX3_2(
                FMLAL_SME_ZA_array_off2x2_SME_Znx4_SME_Zm_INDEX3_2::from(bits),
            ),
        )
    }
}
impl InsnOpcode for FMLAL_SME_ZA_array_off2x2_SME_Znx4_SME_Zm_INDEX3_2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMLAL_SME_ZA_array_off2x2_SVE_ZnxN_SME_Zm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmlal",
        aliases: &[],
        opcode: 0xc1200800,
        mask: 0xfff09c1c,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off2x2,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_0,
                        lsb: 0,
                        width: 2,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ZnxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm,
                    lsb: 16,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::FMLAL_SME_ZA_array_off2x2_SVE_ZnxN_SME_Zm(
            FMLAL_SME_ZA_array_off2x2_SVE_ZnxN_SME_Zm::from(bits),
        ))
    }
}
impl InsnOpcode for FMLAL_SME_ZA_array_off2x2_SVE_ZnxN_SME_Zm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMLAL_SME_ZA_array_off2x2_S_S_SVE_ZnxN_S_H_SME_Zm_S_H {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmlal",
        aliases: &[],
        opcode: 0xc1300800,
        mask: 0xfff09c1c,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off2x2,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_0,
                        lsb: 0,
                        width: 2,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ZnxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm,
                    lsb: 16,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_4.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(
            SME_MISC::FMLAL_SME_ZA_array_off2x2_S_S_SVE_ZnxN_S_H_SME_Zm_S_H(
                FMLAL_SME_ZA_array_off2x2_S_S_SVE_ZnxN_S_H_SME_Zm_S_H::from(bits),
            ),
        )
    }
}
impl InsnOpcode for FMLAL_SME_ZA_array_off2x2_S_S_SVE_ZnxN_S_H_SME_Zm_S_H {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMLAL_SME_ZA_array_off2x2_SME_Znx2_SME_Zmx2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmlal",
        aliases: &[],
        opcode: 0xc1a00800,
        mask: 0xffe19c3c,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off2x2,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_0,
                        lsb: 0,
                        width: 2,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn2,
                    lsb: 6,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zmx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm2,
                    lsb: 17,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::FMLAL_SME_ZA_array_off2x2_SME_Znx2_SME_Zmx2(
            FMLAL_SME_ZA_array_off2x2_SME_Znx2_SME_Zmx2::from(bits),
        ))
    }
}
impl InsnOpcode for FMLAL_SME_ZA_array_off2x2_SME_Znx2_SME_Zmx2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMLAL_SME_ZA_array_off2x2_SME_Znx4_SME_Zmx4 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmlal",
        aliases: &[],
        opcode: 0xc1a10800,
        mask: 0xffe39c7c,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off2x2,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_0,
                        lsb: 0,
                        width: 2,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn4,
                    lsb: 7,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zmx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm4,
                    lsb: 18,
                    width: 3,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_4.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::FMLAL_SME_ZA_array_off2x2_SME_Znx4_SME_Zmx4(
            FMLAL_SME_ZA_array_off2x2_SME_Znx4_SME_Zmx4::from(bits),
        ))
    }
}
impl InsnOpcode for FMLAL_SME_ZA_array_off2x2_SME_Znx4_SME_Zmx4 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMLAL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmlal",
        aliases: &[],
        opcode: 0xc1200c00,
        mask: 0xfff09c18,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off3x2,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_0,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm,
                    lsb: 16,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::FMLAL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm(
            FMLAL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm::from(bits),
        ))
    }
}
impl InsnOpcode for FMLAL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMLAL_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmlal",
        aliases: &[],
        opcode: 0xe20ec00,
        mask: 0xffa0fc00,
        class: InsnClass::ASIMDSAME,
        feature_set: InsnFeatureSet::FP_16_V8_2A,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSAME(ASIMDSAME::FMLAL_Vd_Vn_Vm(FMLAL_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for FMLAL_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMLAL_Vd_V_4S_Vn_V_4H_Vm_V_4H {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmlal",
        aliases: &[],
        opcode: 0x4e20ec00,
        mask: 0xffa0fc00,
        class: InsnClass::ASIMDSAME,
        feature_set: InsnFeatureSet::FP_16_V8_2A,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSAME(ASIMDSAME::FMLAL_Vd_V_4S_Vn_V_4H_Vm_V_4H(
            FMLAL_Vd_V_4S_Vn_V_4H_Vm_V_4H::from(bits),
        ))
    }
}
impl InsnOpcode for FMLAL_Vd_V_4S_Vn_V_4H_Vm_V_4H {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMLAL_Vd_Vn_Em16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmlal",
        aliases: &[],
        opcode: 0xf800000,
        mask: 0xffc0f400,
        class: InsnClass::ASIMDELEM,
        feature_set: InsnFeatureSet::FP_16_V8_2A,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Em16,
                class: InsnOperandClass::SIMD_ELEMENT,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDELEM(ASIMDELEM::FMLAL_Vd_Vn_Em16(FMLAL_Vd_Vn_Em16::from(bits)))
    }
}
impl InsnOpcode for FMLAL_Vd_Vn_Em16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMLAL_Vd_V_4S_Vn_V_4H_Em16_S_H {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmlal",
        aliases: &[],
        opcode: 0x4f800000,
        mask: 0xffc0f400,
        class: InsnClass::ASIMDELEM,
        feature_set: InsnFeatureSet::FP_16_V8_2A,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Em16,
                class: InsnOperandClass::SIMD_ELEMENT,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDELEM(ASIMDELEM::FMLAL_Vd_V_4S_Vn_V_4H_Em16_S_H(
            FMLAL_Vd_V_4S_Vn_V_4H_Em16_S_H::from(bits),
        ))
    }
}
impl InsnOpcode for FMLAL_Vd_V_4S_Vn_V_4H_Em16_S_H {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMLAL2_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmlal2",
        aliases: &[],
        opcode: 0x2e20cc00,
        mask: 0xffa0fc00,
        class: InsnClass::ASIMDSAME,
        feature_set: InsnFeatureSet::FP_16_V8_2A,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSAME(ASIMDSAME::FMLAL2_Vd_Vn_Vm(FMLAL2_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for FMLAL2_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMLAL2_Vd_V_4S_Vn_V_4H_Vm_V_4H {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmlal2",
        aliases: &[],
        opcode: 0x6e20cc00,
        mask: 0xffa0fc00,
        class: InsnClass::ASIMDSAME,
        feature_set: InsnFeatureSet::FP_16_V8_2A,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSAME(ASIMDSAME::FMLAL2_Vd_V_4S_Vn_V_4H_Vm_V_4H(
            FMLAL2_Vd_V_4S_Vn_V_4H_Vm_V_4H::from(bits),
        ))
    }
}
impl InsnOpcode for FMLAL2_Vd_V_4S_Vn_V_4H_Vm_V_4H {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMLAL2_Vd_Vn_Em16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmlal2",
        aliases: &[],
        opcode: 0x2f808000,
        mask: 0xffc0f400,
        class: InsnClass::ASIMDELEM,
        feature_set: InsnFeatureSet::FP_16_V8_2A,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Em16,
                class: InsnOperandClass::SIMD_ELEMENT,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDELEM(ASIMDELEM::FMLAL2_Vd_Vn_Em16(FMLAL2_Vd_Vn_Em16::from(bits)))
    }
}
impl InsnOpcode for FMLAL2_Vd_Vn_Em16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMLAL2_Vd_V_4S_Vn_V_4H_Em16_S_H {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmlal2",
        aliases: &[],
        opcode: 0x6f808000,
        mask: 0xffc0f400,
        class: InsnClass::ASIMDELEM,
        feature_set: InsnFeatureSet::FP_16_V8_2A,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Em16,
                class: InsnOperandClass::SIMD_ELEMENT,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDELEM(ASIMDELEM::FMLAL2_Vd_V_4S_Vn_V_4H_Em16_S_H(
            FMLAL2_Vd_V_4S_Vn_V_4H_Em16_S_H::from(bits),
        ))
    }
}
impl InsnOpcode for FMLAL2_Vd_V_4S_Vn_V_4H_Em16_S_H {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMLALB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmlalb",
        aliases: &[],
        opcode: 0x64a04000,
        mask: 0xffe0f400,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm3_11_INDEX,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_i3h2,
                        lsb: 19,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_i3l,
                        lsb: 11,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_imm3,
                        lsb: 16,
                        width: 3,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::FMLALB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX(
            FMLALB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX::from(bits),
        ))
    }
}
impl InsnOpcode for FMLALB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMLALB_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmlalb",
        aliases: &[],
        opcode: 0x64a08000,
        mask: 0xffe0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::FMLALB_SVE_Zd_SVE_Zn_SVE_Zm_16(
            FMLALB_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for FMLALB_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMLALT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmlalt",
        aliases: &[],
        opcode: 0x64a04400,
        mask: 0xffe0f400,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm3_11_INDEX,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_i3h2,
                        lsb: 19,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_i3l,
                        lsb: 11,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_imm3,
                        lsb: 16,
                        width: 3,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::FMLALT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX(
            FMLALT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX::from(bits),
        ))
    }
}
impl InsnOpcode for FMLALT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMLALT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmlalt",
        aliases: &[],
        opcode: 0x64a08400,
        mask: 0xffe0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::FMLALT_SVE_Zd_SVE_Zn_SVE_Zm_16(
            FMLALT_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for FMLALT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMLS_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmls",
        aliases: &[],
        opcode: 0xc1500010,
        mask: 0xfff09038,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off3_0,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_0,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn2,
                    lsb: 6,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm_INDEX2,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zm,
                        lsb: 16,
                        width: 4,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_10,
                        lsb: 10,
                        width: 2,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::FMLS_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2(
            FMLS_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2::from(bits),
        ))
    }
}
impl InsnOpcode for FMLS_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMLS_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmls",
        aliases: &[],
        opcode: 0xc1508010,
        mask: 0xfff09078,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off3_0,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_0,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn4,
                    lsb: 7,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm_INDEX2,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zm,
                        lsb: 16,
                        width: 4,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_10,
                        lsb: 10,
                        width: 2,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_4.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::FMLS_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2(
            FMLS_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2::from(bits),
        ))
    }
}
impl InsnOpcode for FMLS_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMLS_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX1 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmls",
        aliases: &[],
        opcode: 0xc1d00010,
        mask: 0xfff09838,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2_F64F64,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off3_0,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_0,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn2,
                    lsb: 6,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm_INDEX1,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zm,
                        lsb: 16,
                        width: 4,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm1_10,
                        lsb: 10,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::FMLS_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX1(
            FMLS_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX1::from(bits),
        ))
    }
}
impl InsnOpcode for FMLS_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX1 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMLS_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX1 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmls",
        aliases: &[],
        opcode: 0xc1d08010,
        mask: 0xfff09878,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2_F64F64,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off3_0,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_0,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn4,
                    lsb: 7,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm_INDEX1,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zm,
                        lsb: 16,
                        width: 4,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm1_10,
                        lsb: 10,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_4.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::FMLS_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX1(
            FMLS_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX1::from(bits),
        ))
    }
}
impl InsnOpcode for FMLS_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX1 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMLS_SME_ZA_array_off3_0_SVE_ZnxN_SME_Zm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmls",
        aliases: &[],
        opcode: 0xc1201808,
        mask: 0xffb09c18,
        class: InsnClass::SME_FP_SD,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off3_0,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_0,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ZnxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm,
                    lsb: 16,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_FP_SD(SME_FP_SD::FMLS_SME_ZA_array_off3_0_SVE_ZnxN_SME_Zm(
            FMLS_SME_ZA_array_off3_0_SVE_ZnxN_SME_Zm::from(bits),
        ))
    }
}
impl InsnOpcode for FMLS_SME_ZA_array_off3_0_SVE_ZnxN_SME_Zm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMLS_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_S_SME_Zm_S_S {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmls",
        aliases: &[],
        opcode: 0xc1301808,
        mask: 0xffb09c18,
        class: InsnClass::SME_FP_SD,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off3_0,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_0,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ZnxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm,
                    lsb: 16,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_4.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_FP_SD(
            SME_FP_SD::FMLS_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_S_SME_Zm_S_S(
                FMLS_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_S_SME_Zm_S_S::from(bits),
            ),
        )
    }
}
impl InsnOpcode for FMLS_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_S_SME_Zm_S_S {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMLS_SME_ZA_array_off3_0_SME_Znx2_SME_Zmx2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmls",
        aliases: &[],
        opcode: 0xc1a01808,
        mask: 0xffa19c38,
        class: InsnClass::SME_FP_SD,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off3_0,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_0,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn2,
                    lsb: 6,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zmx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm2,
                    lsb: 17,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_FP_SD(SME_FP_SD::FMLS_SME_ZA_array_off3_0_SME_Znx2_SME_Zmx2(
            FMLS_SME_ZA_array_off3_0_SME_Znx2_SME_Zmx2::from(bits),
        ))
    }
}
impl InsnOpcode for FMLS_SME_ZA_array_off3_0_SME_Znx2_SME_Zmx2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMLS_SME_ZA_array_off3_0_SME_Znx4_SME_Zmx4 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmls",
        aliases: &[],
        opcode: 0xc1a11808,
        mask: 0xffa39c78,
        class: InsnClass::SME_FP_SD,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off3_0,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_0,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn4,
                    lsb: 7,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zmx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm4,
                    lsb: 18,
                    width: 3,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_4.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_FP_SD(SME_FP_SD::FMLS_SME_ZA_array_off3_0_SME_Znx4_SME_Zmx4(
            FMLS_SME_ZA_array_off3_0_SME_Znx4_SME_Zmx4::from(bits),
        ))
    }
}
impl InsnOpcode for FMLS_SME_ZA_array_off3_0_SME_Znx4_SME_Zmx4 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMLS_SVE_Zd_SVE_Zn_SVE_Zm3_22_INDEX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmls",
        aliases: &[],
        opcode: 0x64200400,
        mask: 0xffa0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm3_22_INDEX,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_i3h,
                        lsb: 22,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zm_16,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::FMLS_SVE_Zd_SVE_Zn_SVE_Zm3_22_INDEX(
            FMLS_SVE_Zd_SVE_Zn_SVE_Zm3_22_INDEX::from(bits),
        ))
    }
}
impl InsnOpcode for FMLS_SVE_Zd_SVE_Zn_SVE_Zm3_22_INDEX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMLS_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmls",
        aliases: &[],
        opcode: 0x64a00400,
        mask: 0xffe0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm3_INDEX,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::FMLS_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX(
            FMLS_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX::from(bits),
        ))
    }
}
impl InsnOpcode for FMLS_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMLS_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmls",
        aliases: &[],
        opcode: 0x64e00400,
        mask: 0xffe0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm4_INDEX,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::FMLS_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX(
            FMLS_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX::from(bits),
        ))
    }
}
impl InsnOpcode for FMLS_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMLS_SVE_Zd_SVE_Pg3_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmls",
        aliases: &[],
        opcode: 0x65202000,
        mask: 0xff20e000,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::FMLS_SVE_Zd_SVE_Pg3_SVE_Zn_SVE_Zm_16(
            FMLS_SVE_Zd_SVE_Pg3_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for FMLS_SVE_Zd_SVE_Pg3_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMLS_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmls",
        aliases: &[],
        opcode: 0xec00c00,
        mask: 0xbfe0fc00,
        class: InsnClass::ASIMDSAME,
        feature_set: InsnFeatureSet::SIMD_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSAME(ASIMDSAME::FMLS_Vd_Vn_Vm(FMLS_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for FMLS_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMLS_Vd_V_2S_Vn_V_2S_Vm_V_2S {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmls",
        aliases: &[],
        opcode: 0xea0cc00,
        mask: 0xbfa0fc00,
        class: InsnClass::ASIMDSAME,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSAME(ASIMDSAME::FMLS_Vd_V_2S_Vn_V_2S_Vm_V_2S(
            FMLS_Vd_V_2S_Vn_V_2S_Vm_V_2S::from(bits),
        ))
    }
}
impl InsnOpcode for FMLS_Vd_V_2S_Vn_V_2S_Vm_V_2S {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMLS_Vd_Vn_Em16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmls",
        aliases: &[],
        opcode: 0xf005000,
        mask: 0xbfc0f400,
        class: InsnClass::ASIMDELEM,
        feature_set: InsnFeatureSet::SIMD_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Em16,
                class: InsnOperandClass::SIMD_ELEMENT,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDELEM(ASIMDELEM::FMLS_Vd_Vn_Em16(FMLS_Vd_Vn_Em16::from(bits)))
    }
}
impl InsnOpcode for FMLS_Vd_Vn_Em16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMLS_Vd_Vn_Em {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmls",
        aliases: &[],
        opcode: 0xf805000,
        mask: 0xbf80f400,
        class: InsnClass::ASIMDELEM,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Em,
                class: InsnOperandClass::SIMD_ELEMENT,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDELEM(ASIMDELEM::FMLS_Vd_Vn_Em(FMLS_Vd_Vn_Em::from(bits)))
    }
}
impl InsnOpcode for FMLS_Vd_Vn_Em {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMLS_Sd_Sn_Em16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmls",
        aliases: &[],
        opcode: 0x5f005000,
        mask: 0xffc0f400,
        class: InsnClass::ASISDELEM,
        feature_set: InsnFeatureSet::SIMD_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Em16,
                class: InsnOperandClass::SIMD_ELEMENT,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMD_SCALAR_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDELEM(ASISDELEM::FMLS_Sd_Sn_Em16(FMLS_Sd_Sn_Em16::from(bits)))
    }
}
impl InsnOpcode for FMLS_Sd_Sn_Em16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMLS_Sd_Sn_Em {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmls",
        aliases: &[],
        opcode: 0x5f805000,
        mask: 0xff80f400,
        class: InsnClass::ASISDELEM,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Em,
                class: InsnOperandClass::SIMD_ELEMENT,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMD_SCALAR_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDELEM(ASISDELEM::FMLS_Sd_Sn_Em(FMLS_Sd_Sn_Em::from(bits)))
    }
}
impl InsnOpcode for FMLS_Sd_Sn_Em {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMLSL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm_INDEX3_10 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmlsl",
        aliases: &[],
        opcode: 0xc1801008,
        mask: 0xfff01018,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off3x2,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_0,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm_INDEX3_10,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zm,
                        lsb: 16,
                        width: 4,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm1_15,
                        lsb: 15,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_10,
                        lsb: 10,
                        width: 2,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::FMLSL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm_INDEX3_10(
            FMLSL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm_INDEX3_10::from(bits),
        ))
    }
}
impl InsnOpcode for FMLSL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm_INDEX3_10 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMLSL_SME_ZA_array_off2x2_SME_Znx2_SME_Zm_INDEX3_2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmlsl",
        aliases: &[],
        opcode: 0xc1901008,
        mask: 0xfff09038,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off2x2,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_0,
                        lsb: 0,
                        width: 2,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn2,
                    lsb: 6,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm_INDEX3_2,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zm,
                        lsb: 16,
                        width: 4,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_10,
                        lsb: 10,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm1_2,
                        lsb: 2,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(
            SME_MISC::FMLSL_SME_ZA_array_off2x2_SME_Znx2_SME_Zm_INDEX3_2(
                FMLSL_SME_ZA_array_off2x2_SME_Znx2_SME_Zm_INDEX3_2::from(bits),
            ),
        )
    }
}
impl InsnOpcode for FMLSL_SME_ZA_array_off2x2_SME_Znx2_SME_Zm_INDEX3_2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMLSL_SME_ZA_array_off2x2_SME_Znx4_SME_Zm_INDEX3_2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmlsl",
        aliases: &[],
        opcode: 0xc1909008,
        mask: 0xfff09078,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off2x2,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_0,
                        lsb: 0,
                        width: 2,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn4,
                    lsb: 7,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm_INDEX3_2,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zm,
                        lsb: 16,
                        width: 4,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_10,
                        lsb: 10,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm1_2,
                        lsb: 2,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_4.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(
            SME_MISC::FMLSL_SME_ZA_array_off2x2_SME_Znx4_SME_Zm_INDEX3_2(
                FMLSL_SME_ZA_array_off2x2_SME_Znx4_SME_Zm_INDEX3_2::from(bits),
            ),
        )
    }
}
impl InsnOpcode for FMLSL_SME_ZA_array_off2x2_SME_Znx4_SME_Zm_INDEX3_2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMLSL_SME_ZA_array_off2x2_SVE_ZnxN_SME_Zm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmlsl",
        aliases: &[],
        opcode: 0xc1200808,
        mask: 0xfff09c1c,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off2x2,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_0,
                        lsb: 0,
                        width: 2,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ZnxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm,
                    lsb: 16,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::FMLSL_SME_ZA_array_off2x2_SVE_ZnxN_SME_Zm(
            FMLSL_SME_ZA_array_off2x2_SVE_ZnxN_SME_Zm::from(bits),
        ))
    }
}
impl InsnOpcode for FMLSL_SME_ZA_array_off2x2_SVE_ZnxN_SME_Zm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMLSL_SME_ZA_array_off2x2_S_S_SVE_ZnxN_S_H_SME_Zm_S_H {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmlsl",
        aliases: &[],
        opcode: 0xc1300808,
        mask: 0xfff09c1c,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off2x2,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_0,
                        lsb: 0,
                        width: 2,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ZnxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm,
                    lsb: 16,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_4.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(
            SME_MISC::FMLSL_SME_ZA_array_off2x2_S_S_SVE_ZnxN_S_H_SME_Zm_S_H(
                FMLSL_SME_ZA_array_off2x2_S_S_SVE_ZnxN_S_H_SME_Zm_S_H::from(bits),
            ),
        )
    }
}
impl InsnOpcode for FMLSL_SME_ZA_array_off2x2_S_S_SVE_ZnxN_S_H_SME_Zm_S_H {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMLSL_SME_ZA_array_off2x2_SME_Znx2_SME_Zmx2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmlsl",
        aliases: &[],
        opcode: 0xc1a00808,
        mask: 0xffe19c3c,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off2x2,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_0,
                        lsb: 0,
                        width: 2,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn2,
                    lsb: 6,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zmx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm2,
                    lsb: 17,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::FMLSL_SME_ZA_array_off2x2_SME_Znx2_SME_Zmx2(
            FMLSL_SME_ZA_array_off2x2_SME_Znx2_SME_Zmx2::from(bits),
        ))
    }
}
impl InsnOpcode for FMLSL_SME_ZA_array_off2x2_SME_Znx2_SME_Zmx2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMLSL_SME_ZA_array_off2x2_SME_Znx4_SME_Zmx4 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmlsl",
        aliases: &[],
        opcode: 0xc1a10808,
        mask: 0xffe39c7c,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off2x2,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_0,
                        lsb: 0,
                        width: 2,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn4,
                    lsb: 7,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zmx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm4,
                    lsb: 18,
                    width: 3,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_4.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::FMLSL_SME_ZA_array_off2x2_SME_Znx4_SME_Zmx4(
            FMLSL_SME_ZA_array_off2x2_SME_Znx4_SME_Zmx4::from(bits),
        ))
    }
}
impl InsnOpcode for FMLSL_SME_ZA_array_off2x2_SME_Znx4_SME_Zmx4 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMLSL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmlsl",
        aliases: &[],
        opcode: 0xc1200c08,
        mask: 0xfff09c18,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off3x2,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_0,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm,
                    lsb: 16,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::FMLSL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm(
            FMLSL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm::from(bits),
        ))
    }
}
impl InsnOpcode for FMLSL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMLSL_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmlsl",
        aliases: &[],
        opcode: 0xea0ec00,
        mask: 0xffa0fc00,
        class: InsnClass::ASIMDSAME,
        feature_set: InsnFeatureSet::FP_16_V8_2A,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSAME(ASIMDSAME::FMLSL_Vd_Vn_Vm(FMLSL_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for FMLSL_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMLSL_Vd_V_4S_Vn_V_4H_Vm_V_4H {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmlsl",
        aliases: &[],
        opcode: 0x4ea0ec00,
        mask: 0xffa0fc00,
        class: InsnClass::ASIMDSAME,
        feature_set: InsnFeatureSet::FP_16_V8_2A,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSAME(ASIMDSAME::FMLSL_Vd_V_4S_Vn_V_4H_Vm_V_4H(
            FMLSL_Vd_V_4S_Vn_V_4H_Vm_V_4H::from(bits),
        ))
    }
}
impl InsnOpcode for FMLSL_Vd_V_4S_Vn_V_4H_Vm_V_4H {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMLSL_Vd_Vn_Em16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmlsl",
        aliases: &[],
        opcode: 0xf804000,
        mask: 0xffc0f400,
        class: InsnClass::ASIMDELEM,
        feature_set: InsnFeatureSet::FP_16_V8_2A,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Em16,
                class: InsnOperandClass::SIMD_ELEMENT,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDELEM(ASIMDELEM::FMLSL_Vd_Vn_Em16(FMLSL_Vd_Vn_Em16::from(bits)))
    }
}
impl InsnOpcode for FMLSL_Vd_Vn_Em16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMLSL_Vd_V_4S_Vn_V_4H_Em16_S_H {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmlsl",
        aliases: &[],
        opcode: 0x4f804000,
        mask: 0xffc0f400,
        class: InsnClass::ASIMDELEM,
        feature_set: InsnFeatureSet::FP_16_V8_2A,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Em16,
                class: InsnOperandClass::SIMD_ELEMENT,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDELEM(ASIMDELEM::FMLSL_Vd_V_4S_Vn_V_4H_Em16_S_H(
            FMLSL_Vd_V_4S_Vn_V_4H_Em16_S_H::from(bits),
        ))
    }
}
impl InsnOpcode for FMLSL_Vd_V_4S_Vn_V_4H_Em16_S_H {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMLSL2_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmlsl2",
        aliases: &[],
        opcode: 0x2ea0cc00,
        mask: 0xffa0fc00,
        class: InsnClass::ASIMDSAME,
        feature_set: InsnFeatureSet::FP_16_V8_2A,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSAME(ASIMDSAME::FMLSL2_Vd_Vn_Vm(FMLSL2_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for FMLSL2_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMLSL2_Vd_V_4S_Vn_V_4H_Vm_V_4H {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmlsl2",
        aliases: &[],
        opcode: 0x6ea0cc00,
        mask: 0xffa0fc00,
        class: InsnClass::ASIMDSAME,
        feature_set: InsnFeatureSet::FP_16_V8_2A,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSAME(ASIMDSAME::FMLSL2_Vd_V_4S_Vn_V_4H_Vm_V_4H(
            FMLSL2_Vd_V_4S_Vn_V_4H_Vm_V_4H::from(bits),
        ))
    }
}
impl InsnOpcode for FMLSL2_Vd_V_4S_Vn_V_4H_Vm_V_4H {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMLSL2_Vd_Vn_Em16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmlsl2",
        aliases: &[],
        opcode: 0x2f80c000,
        mask: 0xffc0f400,
        class: InsnClass::ASIMDELEM,
        feature_set: InsnFeatureSet::FP_16_V8_2A,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Em16,
                class: InsnOperandClass::SIMD_ELEMENT,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDELEM(ASIMDELEM::FMLSL2_Vd_Vn_Em16(FMLSL2_Vd_Vn_Em16::from(bits)))
    }
}
impl InsnOpcode for FMLSL2_Vd_Vn_Em16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMLSL2_Vd_V_4S_Vn_V_4H_Em16_S_H {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmlsl2",
        aliases: &[],
        opcode: 0x6f80c000,
        mask: 0xffc0f400,
        class: InsnClass::ASIMDELEM,
        feature_set: InsnFeatureSet::FP_16_V8_2A,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Em16,
                class: InsnOperandClass::SIMD_ELEMENT,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDELEM(ASIMDELEM::FMLSL2_Vd_V_4S_Vn_V_4H_Em16_S_H(
            FMLSL2_Vd_V_4S_Vn_V_4H_Em16_S_H::from(bits),
        ))
    }
}
impl InsnOpcode for FMLSL2_Vd_V_4S_Vn_V_4H_Em16_S_H {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMLSLB_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmlslb",
        aliases: &[],
        opcode: 0x64a0a000,
        mask: 0xffe0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::FMLSLB_SVE_Zd_SVE_Zn_SVE_Zm_16(
            FMLSLB_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for FMLSLB_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMLSLB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmlslb",
        aliases: &[],
        opcode: 0x64a06000,
        mask: 0xffe0f400,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm3_11_INDEX,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_i3h2,
                        lsb: 19,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_i3l,
                        lsb: 11,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_imm3,
                        lsb: 16,
                        width: 3,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::FMLSLB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX(
            FMLSLB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX::from(bits),
        ))
    }
}
impl InsnOpcode for FMLSLB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMLSLT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmlslt",
        aliases: &[],
        opcode: 0x64a0a400,
        mask: 0xffe0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::FMLSLT_SVE_Zd_SVE_Zn_SVE_Zm_16(
            FMLSLT_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for FMLSLT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMLSLT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmlslt",
        aliases: &[],
        opcode: 0x64a06400,
        mask: 0xffe0f400,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm3_11_INDEX,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_i3h2,
                        lsb: 19,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_i3l,
                        lsb: 11,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_imm3,
                        lsb: 16,
                        width: 3,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::FMLSLT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX(
            FMLSLT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX::from(bits),
        ))
    }
}
impl InsnOpcode for FMLSLT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMMLA_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmmla",
        aliases: &[],
        opcode: 0x64a0e400,
        mask: 0xffe0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::F32MM_SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::FMMLA_SVE_Zd_SVE_Zn_SVE_Zm_16(
            FMMLA_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for FMMLA_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMMLA_SVE_Zd_S_D_SVE_Zn_S_D_SVE_Zm_16_S_D {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmmla",
        aliases: &[],
        opcode: 0x64e0e400,
        mask: 0xffe0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::F64MM_SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::FMMLA_SVE_Zd_S_D_SVE_Zn_S_D_SVE_Zm_16_S_D(
            FMMLA_SVE_Zd_S_D_SVE_Zn_S_D_SVE_Zm_16_S_D::from(bits),
        ))
    }
}
impl InsnOpcode for FMMLA_SVE_Zd_S_D_SVE_Zn_S_D_SVE_Zm_16_S_D {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMOPA_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmopa",
        aliases: &[],
        opcode: 0x80800000,
        mask: 0xffe0001c,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZAda_2b,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_ZAda_2b,
                    lsb: 0,
                    width: 2,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Pm,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Pm,
                    lsb: 13,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::FMOPA_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16(
            FMOPA_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for FMOPA_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMOPA_SME_ZAda_3b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmopa",
        aliases: &[],
        opcode: 0x80c00000,
        mask: 0xffe00018,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME_F64F64,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZAda_3b,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_ZAda_3b,
                    lsb: 0,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Pm,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Pm,
                    lsb: 13,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::FMOPA_SME_ZAda_3b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16(
            FMOPA_SME_ZAda_3b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for FMOPA_SME_ZAda_3b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMOPA_SME_ZAda_2b_S_S_SVE_Pg3_P_M_SME_Pm_P_M_SVE_Zn_S_H_SVE_Zm_16_S_H {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmopa",
        aliases: &[],
        opcode: 0x81a00000,
        mask: 0xffe0001c,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZAda_2b,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_ZAda_2b,
                    lsb: 0,
                    width: 2,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Pm,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Pm,
                    lsb: 13,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(
            SME_MISC::FMOPA_SME_ZAda_2b_S_S_SVE_Pg3_P_M_SME_Pm_P_M_SVE_Zn_S_H_SVE_Zm_16_S_H(
                FMOPA_SME_ZAda_2b_S_S_SVE_Pg3_P_M_SME_Pm_P_M_SVE_Zn_S_H_SVE_Zm_16_S_H::from(bits),
            ),
        )
    }
}
impl InsnOpcode for FMOPA_SME_ZAda_2b_S_S_SVE_Pg3_P_M_SME_Pm_P_M_SVE_Zn_S_H_SVE_Zm_16_S_H {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMOPS_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmops",
        aliases: &[],
        opcode: 0x80800010,
        mask: 0xffe0001c,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZAda_2b,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_ZAda_2b,
                    lsb: 0,
                    width: 2,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Pm,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Pm,
                    lsb: 13,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::FMOPS_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16(
            FMOPS_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for FMOPS_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMOPS_SME_ZAda_3b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmops",
        aliases: &[],
        opcode: 0x80c00010,
        mask: 0xffe00018,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME_F64F64,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZAda_3b,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_ZAda_3b,
                    lsb: 0,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Pm,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Pm,
                    lsb: 13,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::FMOPS_SME_ZAda_3b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16(
            FMOPS_SME_ZAda_3b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for FMOPS_SME_ZAda_3b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMOPS_SME_ZAda_2b_S_S_SVE_Pg3_P_M_SME_Pm_P_M_SVE_Zn_S_H_SVE_Zm_16_S_H {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmops",
        aliases: &[],
        opcode: 0x81a00010,
        mask: 0xffe0001c,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZAda_2b,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_ZAda_2b,
                    lsb: 0,
                    width: 2,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Pm,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Pm,
                    lsb: 13,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(
            SME_MISC::FMOPS_SME_ZAda_2b_S_S_SVE_Pg3_P_M_SME_Pm_P_M_SVE_Zn_S_H_SVE_Zm_16_S_H(
                FMOPS_SME_ZAda_2b_S_S_SVE_Pg3_P_M_SME_Pm_P_M_SVE_Zn_S_H_SVE_Zm_16_S_H::from(bits),
            ),
        )
    }
}
impl InsnOpcode for FMOPS_SME_ZAda_2b_S_S_SVE_Pg3_P_M_SME_Pm_P_M_SVE_Zn_S_H_SVE_Zm_16_S_H {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMOV_Rd_Fn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmov",
        aliases: &[],
        opcode: 0x1ee60000,
        mask: 0x7ffffc00,
        class: InsnClass::FLOAT2INT,
        feature_set: InsnFeatureSet::FP_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fn,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_FPTYPE_FIELD.bits() | InsnFlags::HAS_SF_FIELD.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::FLOAT2INT(FLOAT2INT::FMOV_Rd_Fn(FMOV_Rd_Fn::from(bits)))
    }
}
impl InsnOpcode for FMOV_Rd_Fn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMOV_Rd_W_Fn_S_S {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmov",
        aliases: &[],
        opcode: 0x1e260000,
        mask: 0x7f3ffc00,
        class: InsnClass::FLOAT2INT,
        feature_set: InsnFeatureSet::FP,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fn,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_FPTYPE_FIELD.bits() | InsnFlags::HAS_SF_FIELD.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::FLOAT2INT(FLOAT2INT::FMOV_Rd_W_Fn_S_S(FMOV_Rd_W_Fn_S_S::from(bits)))
    }
}
impl InsnOpcode for FMOV_Rd_W_Fn_S_S {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMOV_Rd_VnD1 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmov",
        aliases: &[],
        opcode: 0x9eae0000,
        mask: 0xfffffc00,
        class: InsnClass::FLOAT2INT,
        feature_set: InsnFeatureSet::FP,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::VnD1,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::FLOAT2INT(FLOAT2INT::FMOV_Rd_VnD1(FMOV_Rd_VnD1::from(bits)))
    }
}
impl InsnOpcode for FMOV_Rd_VnD1 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMOV_Fd_Rn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmov",
        aliases: &[],
        opcode: 0x1ee70000,
        mask: 0x7ffffc00,
        class: InsnClass::FLOAT2INT,
        feature_set: InsnFeatureSet::FP_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Fd,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_FPTYPE_FIELD.bits() | InsnFlags::HAS_SF_FIELD.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::FLOAT2INT(FLOAT2INT::FMOV_Fd_Rn(FMOV_Fd_Rn::from(bits)))
    }
}
impl InsnOpcode for FMOV_Fd_Rn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMOV_Fd_S_S_Rn_W {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmov",
        aliases: &[],
        opcode: 0x1e270000,
        mask: 0x7f3ffc00,
        class: InsnClass::FLOAT2INT,
        feature_set: InsnFeatureSet::FP,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Fd,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_FPTYPE_FIELD.bits() | InsnFlags::HAS_SF_FIELD.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::FLOAT2INT(FLOAT2INT::FMOV_Fd_S_S_Rn_W(FMOV_Fd_S_S_Rn_W::from(bits)))
    }
}
impl InsnOpcode for FMOV_Fd_S_S_Rn_W {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMOV_VdD1_Rn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmov",
        aliases: &[],
        opcode: 0x9eaf0000,
        mask: 0xfffffc00,
        class: InsnClass::FLOAT2INT,
        feature_set: InsnFeatureSet::FP,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::VdD1,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::FLOAT2INT(FLOAT2INT::FMOV_VdD1_Rn(FMOV_VdD1_Rn::from(bits)))
    }
}
impl InsnOpcode for FMOV_VdD1_Rn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMOV_Fd_Fn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmov",
        aliases: &[],
        opcode: 0x1ee04000,
        mask: 0xfffffc00,
        class: InsnClass::FLOATDP1,
        feature_set: InsnFeatureSet::FP_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Fd,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fn,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_FPTYPE_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::FLOATDP1(FLOATDP1::FMOV_Fd_Fn(FMOV_Fd_Fn::from(bits)))
    }
}
impl InsnOpcode for FMOV_Fd_Fn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMOV_Fd_S_S_Fn_S_S {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmov",
        aliases: &[],
        opcode: 0x1e204000,
        mask: 0xff3ffc00,
        class: InsnClass::FLOATDP1,
        feature_set: InsnFeatureSet::FP,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Fd,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fn,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_FPTYPE_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::FLOATDP1(FLOATDP1::FMOV_Fd_S_S_Fn_S_S(FMOV_Fd_S_S_Fn_S_S::from(bits)))
    }
}
impl InsnOpcode for FMOV_Fd_S_S_Fn_S_S {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMOV_Fd_FPIMM {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmov",
        aliases: &[],
        opcode: 0x1ee01000,
        mask: 0xffe01fe0,
        class: InsnClass::FLOATIMM,
        feature_set: InsnFeatureSet::FP_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Fd,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::FPIMM,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::imm8,
                    lsb: 13,
                    width: 8,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_FPTYPE_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::FLOATIMM(FLOATIMM::FMOV_Fd_FPIMM(FMOV_Fd_FPIMM::from(bits)))
    }
}
impl InsnOpcode for FMOV_Fd_FPIMM {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMOV_Fd_S_S_FPIMM {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmov",
        aliases: &[],
        opcode: 0x1e201000,
        mask: 0xff201fe0,
        class: InsnClass::FLOATIMM,
        feature_set: InsnFeatureSet::FP,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Fd,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::FPIMM,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::imm8,
                    lsb: 13,
                    width: 8,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_FPTYPE_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::FLOATIMM(FLOATIMM::FMOV_Fd_S_S_FPIMM(FMOV_Fd_S_S_FPIMM::from(bits)))
    }
}
impl InsnOpcode for FMOV_Fd_S_S_FPIMM {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMOV_Vd_SIMD_FPIMM {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmov",
        aliases: &[],
        opcode: 0xf00f400,
        mask: 0xbff8fc00,
        class: InsnClass::ASIMDIMM,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SIMD_FPIMM,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDIMM(ASIMDIMM::FMOV_Vd_SIMD_FPIMM(FMOV_Vd_SIMD_FPIMM::from(bits)))
    }
}
impl InsnOpcode for FMOV_Vd_SIMD_FPIMM {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMOV_Vd_V_2D_SIMD_FPIMM {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmov",
        aliases: &[],
        opcode: 0x6f00f400,
        mask: 0xfff8fc00,
        class: InsnClass::ASIMDIMM,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SIMD_FPIMM,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDIMM(ASIMDIMM::FMOV_Vd_V_2D_SIMD_FPIMM(
            FMOV_Vd_V_2D_SIMD_FPIMM::from(bits),
        ))
    }
}
impl InsnOpcode for FMOV_Vd_V_2D_SIMD_FPIMM {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMOV_Vd_V_4H_SIMD_FPIMM {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmov",
        aliases: &[],
        opcode: 0xf00fc00,
        mask: 0xbff8fc00,
        class: InsnClass::ASIMDIMM,
        feature_set: InsnFeatureSet::SIMD_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SIMD_FPIMM,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDIMM(ASIMDIMM::FMOV_Vd_V_4H_SIMD_FPIMM(
            FMOV_Vd_V_4H_SIMD_FPIMM::from(bits),
        ))
    }
}
impl InsnOpcode for FMOV_Vd_V_4H_SIMD_FPIMM {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMSB_SVE_Zd_SVE_Pg3_SVE_Zm_5_SVE_Za_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmsb",
        aliases: &[],
        opcode: 0x6520a000,
        mask: 0xff20e000,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_5,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_5,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Za_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Za_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::FMSB_SVE_Zd_SVE_Pg3_SVE_Zm_5_SVE_Za_16(
            FMSB_SVE_Zd_SVE_Pg3_SVE_Zm_5_SVE_Za_16::from(bits),
        ))
    }
}
impl InsnOpcode for FMSB_SVE_Zd_SVE_Pg3_SVE_Zm_5_SVE_Za_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMSUB_Fd_Fn_Fm_Fa {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmsub",
        aliases: &[],
        opcode: 0x1fc08000,
        mask: 0xffe08000,
        class: InsnClass::FLOATDP3,
        feature_set: InsnFeatureSet::FP_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Fd,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fn,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fm,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fa,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Ra,
                    lsb: 10,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_FPTYPE_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::FLOATDP3(FLOATDP3::FMSUB_Fd_Fn_Fm_Fa(FMSUB_Fd_Fn_Fm_Fa::from(bits)))
    }
}
impl InsnOpcode for FMSUB_Fd_Fn_Fm_Fa {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMSUB_Fd_S_S_Fn_S_S_Fm_S_S_Fa_S_S {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmsub",
        aliases: &[],
        opcode: 0x1f008000,
        mask: 0xff208000,
        class: InsnClass::FLOATDP3,
        feature_set: InsnFeatureSet::FP,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Fd,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fn,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fm,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fa,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Ra,
                    lsb: 10,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_FPTYPE_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::FLOATDP3(FLOATDP3::FMSUB_Fd_S_S_Fn_S_S_Fm_S_S_Fa_S_S(
            FMSUB_Fd_S_S_Fn_S_S_Fm_S_S_Fa_S_S::from(bits),
        ))
    }
}
impl InsnOpcode for FMSUB_Fd_S_S_Fn_S_S_Fm_S_S_Fa_S_S {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMUL_SVE_Zd_SVE_Zn_SVE_Zm3_22_INDEX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmul",
        aliases: &[],
        opcode: 0x64202000,
        mask: 0xffa0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm3_22_INDEX,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_i3h,
                        lsb: 22,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zm_16,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::FMUL_SVE_Zd_SVE_Zn_SVE_Zm3_22_INDEX(
            FMUL_SVE_Zd_SVE_Zn_SVE_Zm3_22_INDEX::from(bits),
        ))
    }
}
impl InsnOpcode for FMUL_SVE_Zd_SVE_Zn_SVE_Zm3_22_INDEX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMUL_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmul",
        aliases: &[],
        opcode: 0x64a02000,
        mask: 0xffe0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm3_INDEX,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::FMUL_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX(
            FMUL_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX::from(bits),
        ))
    }
}
impl InsnOpcode for FMUL_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMUL_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmul",
        aliases: &[],
        opcode: 0x64e02000,
        mask: 0xffe0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm4_INDEX,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::FMUL_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX(
            FMUL_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX::from(bits),
        ))
    }
}
impl InsnOpcode for FMUL_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMUL_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmul",
        aliases: &[],
        opcode: 0x65000800,
        mask: 0xff20fc00,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::FMUL_SVE_Zd_SVE_Zn_SVE_Zm_16(
            FMUL_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for FMUL_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMUL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmul",
        aliases: &[],
        opcode: 0x65028000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_5,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_5,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::FMUL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(
            FMUL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5::from(bits),
        ))
    }
}
impl InsnOpcode for FMUL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMUL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_I1_HALF_TWO {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmul",
        aliases: &[],
        opcode: 0x651a8000,
        mask: 0xff3fe3c0,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_I1_HALF_TWO,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_i1,
                    lsb: 5,
                    width: 1,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::FMUL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_I1_HALF_TWO(
            FMUL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_I1_HALF_TWO::from(bits),
        ))
    }
}
impl InsnOpcode for FMUL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_I1_HALF_TWO {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMUL_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmul",
        aliases: &[],
        opcode: 0x2e401c00,
        mask: 0xbfe0fc00,
        class: InsnClass::ASIMDSAME,
        feature_set: InsnFeatureSet::SIMD_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSAME(ASIMDSAME::FMUL_Vd_Vn_Vm(FMUL_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for FMUL_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMUL_Vd_V_2S_Vn_V_2S_Vm_V_2S {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmul",
        aliases: &[],
        opcode: 0x2e20dc00,
        mask: 0xbfa0fc00,
        class: InsnClass::ASIMDSAME,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSAME(ASIMDSAME::FMUL_Vd_V_2S_Vn_V_2S_Vm_V_2S(
            FMUL_Vd_V_2S_Vn_V_2S_Vm_V_2S::from(bits),
        ))
    }
}
impl InsnOpcode for FMUL_Vd_V_2S_Vn_V_2S_Vm_V_2S {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMUL_Fd_Fn_Fm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmul",
        aliases: &[],
        opcode: 0x1ee00800,
        mask: 0xffe0fc00,
        class: InsnClass::FLOATDP2,
        feature_set: InsnFeatureSet::FP_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Fd,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fn,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fm,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_FPTYPE_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::FLOATDP2(FLOATDP2::FMUL_Fd_Fn_Fm(FMUL_Fd_Fn_Fm::from(bits)))
    }
}
impl InsnOpcode for FMUL_Fd_Fn_Fm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMUL_Fd_S_S_Fn_S_S_Fm_S_S {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmul",
        aliases: &[],
        opcode: 0x1e200800,
        mask: 0xff20fc00,
        class: InsnClass::FLOATDP2,
        feature_set: InsnFeatureSet::FP,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Fd,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fn,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fm,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_FPTYPE_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::FLOATDP2(FLOATDP2::FMUL_Fd_S_S_Fn_S_S_Fm_S_S(
            FMUL_Fd_S_S_Fn_S_S_Fm_S_S::from(bits),
        ))
    }
}
impl InsnOpcode for FMUL_Fd_S_S_Fn_S_S_Fm_S_S {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMUL_Vd_Vn_Em16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmul",
        aliases: &[],
        opcode: 0xf009000,
        mask: 0xbfc0f400,
        class: InsnClass::ASIMDELEM,
        feature_set: InsnFeatureSet::SIMD_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Em16,
                class: InsnOperandClass::SIMD_ELEMENT,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDELEM(ASIMDELEM::FMUL_Vd_Vn_Em16(FMUL_Vd_Vn_Em16::from(bits)))
    }
}
impl InsnOpcode for FMUL_Vd_Vn_Em16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMUL_Vd_Vn_Em {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmul",
        aliases: &[],
        opcode: 0xf809000,
        mask: 0xbf80f400,
        class: InsnClass::ASIMDELEM,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Em,
                class: InsnOperandClass::SIMD_ELEMENT,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDELEM(ASIMDELEM::FMUL_Vd_Vn_Em(FMUL_Vd_Vn_Em::from(bits)))
    }
}
impl InsnOpcode for FMUL_Vd_Vn_Em {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMUL_Sd_Sn_Em16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmul",
        aliases: &[],
        opcode: 0x5f009000,
        mask: 0xffc0f400,
        class: InsnClass::ASISDELEM,
        feature_set: InsnFeatureSet::SIMD_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Em16,
                class: InsnOperandClass::SIMD_ELEMENT,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMD_SCALAR_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDELEM(ASISDELEM::FMUL_Sd_Sn_Em16(FMUL_Sd_Sn_Em16::from(bits)))
    }
}
impl InsnOpcode for FMUL_Sd_Sn_Em16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMUL_Sd_Sn_Em {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmul",
        aliases: &[],
        opcode: 0x5f809000,
        mask: 0xff80f400,
        class: InsnClass::ASISDELEM,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Em,
                class: InsnOperandClass::SIMD_ELEMENT,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMD_SCALAR_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDELEM(ASISDELEM::FMUL_Sd_Sn_Em(FMUL_Sd_Sn_Em::from(bits)))
    }
}
impl InsnOpcode for FMUL_Sd_Sn_Em {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMULX_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmulx",
        aliases: &[],
        opcode: 0x650a8000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_5,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_5,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::FMULX_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(
            FMULX_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5::from(bits),
        ))
    }
}
impl InsnOpcode for FMULX_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMULX_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmulx",
        aliases: &[],
        opcode: 0xe401c00,
        mask: 0xbfe0fc00,
        class: InsnClass::ASIMDSAME,
        feature_set: InsnFeatureSet::SIMD_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSAME(ASIMDSAME::FMULX_Vd_Vn_Vm(FMULX_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for FMULX_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMULX_Sd_Sn_Sm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmulx",
        aliases: &[],
        opcode: 0x5e401c00,
        mask: 0xffe0fc00,
        class: InsnClass::ASISDSAME,
        feature_set: InsnFeatureSet::SIMD_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sm,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMD_SCALAR_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDSAME(ASISDSAME::FMULX_Sd_Sn_Sm(FMULX_Sd_Sn_Sm::from(bits)))
    }
}
impl InsnOpcode for FMULX_Sd_Sn_Sm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMULX_Vd_V_2S_Vn_V_2S_Vm_V_2S {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmulx",
        aliases: &[],
        opcode: 0xe20dc00,
        mask: 0xbfa0fc00,
        class: InsnClass::ASIMDSAME,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSAME(ASIMDSAME::FMULX_Vd_V_2S_Vn_V_2S_Vm_V_2S(
            FMULX_Vd_V_2S_Vn_V_2S_Vm_V_2S::from(bits),
        ))
    }
}
impl InsnOpcode for FMULX_Vd_V_2S_Vn_V_2S_Vm_V_2S {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMULX_Sd_S_S_Sn_S_S_Sm_S_S {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmulx",
        aliases: &[],
        opcode: 0x5e20dc00,
        mask: 0xffa0fc00,
        class: InsnClass::ASISDSAME,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sm,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMD_SCALAR_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDSAME(ASISDSAME::FMULX_Sd_S_S_Sn_S_S_Sm_S_S(
            FMULX_Sd_S_S_Sn_S_S_Sm_S_S::from(bits),
        ))
    }
}
impl InsnOpcode for FMULX_Sd_S_S_Sn_S_S_Sm_S_S {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMULX_Vd_Vn_Em16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmulx",
        aliases: &[],
        opcode: 0x2f009000,
        mask: 0xbfc0f400,
        class: InsnClass::ASIMDELEM,
        feature_set: InsnFeatureSet::SIMD_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Em16,
                class: InsnOperandClass::SIMD_ELEMENT,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDELEM(ASIMDELEM::FMULX_Vd_Vn_Em16(FMULX_Vd_Vn_Em16::from(bits)))
    }
}
impl InsnOpcode for FMULX_Vd_Vn_Em16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMULX_Vd_Vn_Em {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmulx",
        aliases: &[],
        opcode: 0x2f809000,
        mask: 0xbf80f400,
        class: InsnClass::ASIMDELEM,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Em,
                class: InsnOperandClass::SIMD_ELEMENT,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDELEM(ASIMDELEM::FMULX_Vd_Vn_Em(FMULX_Vd_Vn_Em::from(bits)))
    }
}
impl InsnOpcode for FMULX_Vd_Vn_Em {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMULX_Sd_Sn_Em16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmulx",
        aliases: &[],
        opcode: 0x7f009000,
        mask: 0xffc0f400,
        class: InsnClass::ASISDELEM,
        feature_set: InsnFeatureSet::SIMD_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Em16,
                class: InsnOperandClass::SIMD_ELEMENT,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMD_SCALAR_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDELEM(ASISDELEM::FMULX_Sd_Sn_Em16(FMULX_Sd_Sn_Em16::from(bits)))
    }
}
impl InsnOpcode for FMULX_Sd_Sn_Em16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FMULX_Sd_Sn_Em {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fmulx",
        aliases: &[],
        opcode: 0x7f809000,
        mask: 0xff80f400,
        class: InsnClass::ASISDELEM,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Em,
                class: InsnOperandClass::SIMD_ELEMENT,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMD_SCALAR_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDELEM(ASISDELEM::FMULX_Sd_Sn_Em(FMULX_Sd_Sn_Em::from(bits)))
    }
}
impl InsnOpcode for FMULX_Sd_Sn_Em {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FNEG_SVE_Zd_SVE_Pg3_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fneg",
        aliases: &[],
        opcode: 0x41da000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M, InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::FNEG_SVE_Zd_SVE_Pg3_SVE_Zn(
            FNEG_SVE_Zd_SVE_Pg3_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for FNEG_SVE_Zd_SVE_Pg3_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FNEG_Vd_Vn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fneg",
        aliases: &[],
        opcode: 0x2ea0f800,
        mask: 0xbfbffc00,
        class: InsnClass::ASIMDMISC,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDMISC(ASIMDMISC::FNEG_Vd_Vn(FNEG_Vd_Vn::from(bits)))
    }
}
impl InsnOpcode for FNEG_Vd_Vn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FNEG_Vd_V_4H_Vn_V_4H {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fneg",
        aliases: &[],
        opcode: 0x2ef8f800,
        mask: 0xbffffc00,
        class: InsnClass::ASIMDMISC,
        feature_set: InsnFeatureSet::SIMD_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDMISC(ASIMDMISC::FNEG_Vd_V_4H_Vn_V_4H(FNEG_Vd_V_4H_Vn_V_4H::from(
            bits,
        )))
    }
}
impl InsnOpcode for FNEG_Vd_V_4H_Vn_V_4H {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FNEG_Fd_Fn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fneg",
        aliases: &[],
        opcode: 0x1ee14000,
        mask: 0xfffffc00,
        class: InsnClass::FLOATDP1,
        feature_set: InsnFeatureSet::FP_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Fd,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fn,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_FPTYPE_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::FLOATDP1(FLOATDP1::FNEG_Fd_Fn(FNEG_Fd_Fn::from(bits)))
    }
}
impl InsnOpcode for FNEG_Fd_Fn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FNEG_Fd_S_S_Fn_S_S {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fneg",
        aliases: &[],
        opcode: 0x1e214000,
        mask: 0xff3ffc00,
        class: InsnClass::FLOATDP1,
        feature_set: InsnFeatureSet::FP,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Fd,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fn,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_FPTYPE_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::FLOATDP1(FLOATDP1::FNEG_Fd_S_S_Fn_S_S(FNEG_Fd_S_S_Fn_S_S::from(bits)))
    }
}
impl InsnOpcode for FNEG_Fd_S_S_Fn_S_S {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FNMAD_SVE_Zd_SVE_Pg3_SVE_Zm_5_SVE_Za_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fnmad",
        aliases: &[],
        opcode: 0x6520c000,
        mask: 0xff20e000,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_5,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_5,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Za_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Za_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::FNMAD_SVE_Zd_SVE_Pg3_SVE_Zm_5_SVE_Za_16(
            FNMAD_SVE_Zd_SVE_Pg3_SVE_Zm_5_SVE_Za_16::from(bits),
        ))
    }
}
impl InsnOpcode for FNMAD_SVE_Zd_SVE_Pg3_SVE_Zm_5_SVE_Za_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FNMADD_Fd_Fn_Fm_Fa {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fnmadd",
        aliases: &[],
        opcode: 0x1fe00000,
        mask: 0xffe08000,
        class: InsnClass::FLOATDP3,
        feature_set: InsnFeatureSet::FP_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Fd,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fn,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fm,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fa,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Ra,
                    lsb: 10,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_FPTYPE_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::FLOATDP3(FLOATDP3::FNMADD_Fd_Fn_Fm_Fa(FNMADD_Fd_Fn_Fm_Fa::from(bits)))
    }
}
impl InsnOpcode for FNMADD_Fd_Fn_Fm_Fa {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FNMADD_Fd_S_S_Fn_S_S_Fm_S_S_Fa_S_S {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fnmadd",
        aliases: &[],
        opcode: 0x1f200000,
        mask: 0xff208000,
        class: InsnClass::FLOATDP3,
        feature_set: InsnFeatureSet::FP,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Fd,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fn,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fm,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fa,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Ra,
                    lsb: 10,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_FPTYPE_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::FLOATDP3(FLOATDP3::FNMADD_Fd_S_S_Fn_S_S_Fm_S_S_Fa_S_S(
            FNMADD_Fd_S_S_Fn_S_S_Fm_S_S_Fa_S_S::from(bits),
        ))
    }
}
impl InsnOpcode for FNMADD_Fd_S_S_Fn_S_S_Fm_S_S_Fa_S_S {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FNMLA_SVE_Zd_SVE_Pg3_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fnmla",
        aliases: &[],
        opcode: 0x65204000,
        mask: 0xff20e000,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::FNMLA_SVE_Zd_SVE_Pg3_SVE_Zn_SVE_Zm_16(
            FNMLA_SVE_Zd_SVE_Pg3_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for FNMLA_SVE_Zd_SVE_Pg3_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FNMLS_SVE_Zd_SVE_Pg3_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fnmls",
        aliases: &[],
        opcode: 0x65206000,
        mask: 0xff20e000,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::FNMLS_SVE_Zd_SVE_Pg3_SVE_Zn_SVE_Zm_16(
            FNMLS_SVE_Zd_SVE_Pg3_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for FNMLS_SVE_Zd_SVE_Pg3_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FNMSB_SVE_Zd_SVE_Pg3_SVE_Zm_5_SVE_Za_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fnmsb",
        aliases: &[],
        opcode: 0x6520e000,
        mask: 0xff20e000,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_5,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_5,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Za_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Za_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::FNMSB_SVE_Zd_SVE_Pg3_SVE_Zm_5_SVE_Za_16(
            FNMSB_SVE_Zd_SVE_Pg3_SVE_Zm_5_SVE_Za_16::from(bits),
        ))
    }
}
impl InsnOpcode for FNMSB_SVE_Zd_SVE_Pg3_SVE_Zm_5_SVE_Za_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FNMSUB_Fd_Fn_Fm_Fa {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fnmsub",
        aliases: &[],
        opcode: 0x1fe08000,
        mask: 0xffe08000,
        class: InsnClass::FLOATDP3,
        feature_set: InsnFeatureSet::FP_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Fd,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fn,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fm,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fa,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Ra,
                    lsb: 10,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_FPTYPE_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::FLOATDP3(FLOATDP3::FNMSUB_Fd_Fn_Fm_Fa(FNMSUB_Fd_Fn_Fm_Fa::from(bits)))
    }
}
impl InsnOpcode for FNMSUB_Fd_Fn_Fm_Fa {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FNMSUB_Fd_S_S_Fn_S_S_Fm_S_S_Fa_S_S {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fnmsub",
        aliases: &[],
        opcode: 0x1f208000,
        mask: 0xff208000,
        class: InsnClass::FLOATDP3,
        feature_set: InsnFeatureSet::FP,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Fd,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fn,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fm,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fa,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Ra,
                    lsb: 10,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_FPTYPE_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::FLOATDP3(FLOATDP3::FNMSUB_Fd_S_S_Fn_S_S_Fm_S_S_Fa_S_S(
            FNMSUB_Fd_S_S_Fn_S_S_Fm_S_S_Fa_S_S::from(bits),
        ))
    }
}
impl InsnOpcode for FNMSUB_Fd_S_S_Fn_S_S_Fm_S_S_Fa_S_S {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FNMUL_Fd_Fn_Fm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fnmul",
        aliases: &[],
        opcode: 0x1ee08800,
        mask: 0xffe0fc00,
        class: InsnClass::FLOATDP2,
        feature_set: InsnFeatureSet::FP_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Fd,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fn,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fm,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_FPTYPE_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::FLOATDP2(FLOATDP2::FNMUL_Fd_Fn_Fm(FNMUL_Fd_Fn_Fm::from(bits)))
    }
}
impl InsnOpcode for FNMUL_Fd_Fn_Fm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FNMUL_Fd_S_S_Fn_S_S_Fm_S_S {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fnmul",
        aliases: &[],
        opcode: 0x1e208800,
        mask: 0xff20fc00,
        class: InsnClass::FLOATDP2,
        feature_set: InsnFeatureSet::FP,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Fd,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fn,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fm,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_FPTYPE_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::FLOATDP2(FLOATDP2::FNMUL_Fd_S_S_Fn_S_S_Fm_S_S(
            FNMUL_Fd_S_S_Fn_S_S_Fm_S_S::from(bits),
        ))
    }
}
impl InsnOpcode for FNMUL_Fd_S_S_Fn_S_S_Fm_S_S {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FRECPE_SVE_Zd_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "frecpe",
        aliases: &[],
        opcode: 0x650e3000,
        mask: 0xff3ffc00,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::FRECPE_SVE_Zd_SVE_Zn(
            FRECPE_SVE_Zd_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for FRECPE_SVE_Zd_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FRECPE_Vd_Vn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "frecpe",
        aliases: &[],
        opcode: 0xea1d800,
        mask: 0xbfbffc00,
        class: InsnClass::ASIMDMISC,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDMISC(ASIMDMISC::FRECPE_Vd_Vn(FRECPE_Vd_Vn::from(bits)))
    }
}
impl InsnOpcode for FRECPE_Vd_Vn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FRECPE_Vd_V_4H_Vn_V_4H {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "frecpe",
        aliases: &[],
        opcode: 0xef9d800,
        mask: 0xbffffc00,
        class: InsnClass::ASIMDMISC,
        feature_set: InsnFeatureSet::SIMD_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDMISC(ASIMDMISC::FRECPE_Vd_V_4H_Vn_V_4H(
            FRECPE_Vd_V_4H_Vn_V_4H::from(bits),
        ))
    }
}
impl InsnOpcode for FRECPE_Vd_V_4H_Vn_V_4H {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FRECPE_Sd_Sn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "frecpe",
        aliases: &[],
        opcode: 0x5ea1d800,
        mask: 0xffbffc00,
        class: InsnClass::ASISDMISC,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMD_SCALAR_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDMISC(ASISDMISC::FRECPE_Sd_Sn(FRECPE_Sd_Sn::from(bits)))
    }
}
impl InsnOpcode for FRECPE_Sd_Sn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FRECPE_Sd_S_H_Sn_S_H {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "frecpe",
        aliases: &[],
        opcode: 0x5ef9d800,
        mask: 0xfffffc00,
        class: InsnClass::ASISDMISC,
        feature_set: InsnFeatureSet::SIMD_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMD_SCALAR_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDMISC(ASISDMISC::FRECPE_Sd_S_H_Sn_S_H(FRECPE_Sd_S_H_Sn_S_H::from(
            bits,
        )))
    }
}
impl InsnOpcode for FRECPE_Sd_S_H_Sn_S_H {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FRECPS_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "frecps",
        aliases: &[],
        opcode: 0x65001800,
        mask: 0xff20fc00,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::FRECPS_SVE_Zd_SVE_Zn_SVE_Zm_16(
            FRECPS_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for FRECPS_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FRECPS_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "frecps",
        aliases: &[],
        opcode: 0xe403c00,
        mask: 0xbfe0fc00,
        class: InsnClass::ASIMDSAME,
        feature_set: InsnFeatureSet::SIMD_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSAME(ASIMDSAME::FRECPS_Vd_Vn_Vm(FRECPS_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for FRECPS_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FRECPS_Sd_Sn_Sm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "frecps",
        aliases: &[],
        opcode: 0x5e403c00,
        mask: 0xffe0fc00,
        class: InsnClass::ASISDSAME,
        feature_set: InsnFeatureSet::SIMD_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sm,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMD_SCALAR_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDSAME(ASISDSAME::FRECPS_Sd_Sn_Sm(FRECPS_Sd_Sn_Sm::from(bits)))
    }
}
impl InsnOpcode for FRECPS_Sd_Sn_Sm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FRECPS_Vd_V_2S_Vn_V_2S_Vm_V_2S {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "frecps",
        aliases: &[],
        opcode: 0xe20fc00,
        mask: 0xbfa0fc00,
        class: InsnClass::ASIMDSAME,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSAME(ASIMDSAME::FRECPS_Vd_V_2S_Vn_V_2S_Vm_V_2S(
            FRECPS_Vd_V_2S_Vn_V_2S_Vm_V_2S::from(bits),
        ))
    }
}
impl InsnOpcode for FRECPS_Vd_V_2S_Vn_V_2S_Vm_V_2S {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FRECPS_Sd_S_S_Sn_S_S_Sm_S_S {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "frecps",
        aliases: &[],
        opcode: 0x5e20fc00,
        mask: 0xffa0fc00,
        class: InsnClass::ASISDSAME,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sm,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMD_SCALAR_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDSAME(ASISDSAME::FRECPS_Sd_S_S_Sn_S_S_Sm_S_S(
            FRECPS_Sd_S_S_Sn_S_S_Sm_S_S::from(bits),
        ))
    }
}
impl InsnOpcode for FRECPS_Sd_S_S_Sn_S_S_Sm_S_S {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FRECPX_SVE_Zd_SVE_Pg3_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "frecpx",
        aliases: &[],
        opcode: 0x650ca000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M, InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::FRECPX_SVE_Zd_SVE_Pg3_SVE_Zn(
            FRECPX_SVE_Zd_SVE_Pg3_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for FRECPX_SVE_Zd_SVE_Pg3_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FRECPX_Sd_Sn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "frecpx",
        aliases: &[],
        opcode: 0x5ea1f800,
        mask: 0xffbffc00,
        class: InsnClass::ASISDMISC,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMD_SCALAR_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDMISC(ASISDMISC::FRECPX_Sd_Sn(FRECPX_Sd_Sn::from(bits)))
    }
}
impl InsnOpcode for FRECPX_Sd_Sn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FRECPX_Sd_S_H_Sn_S_H {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "frecpx",
        aliases: &[],
        opcode: 0x5ef9f800,
        mask: 0xfffffc00,
        class: InsnClass::ASISDMISC,
        feature_set: InsnFeatureSet::SIMD_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMD_SCALAR_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDMISC(ASISDMISC::FRECPX_Sd_S_H_Sn_S_H(FRECPX_Sd_S_H_Sn_S_H::from(
            bits,
        )))
    }
}
impl InsnOpcode for FRECPX_Sd_S_H_Sn_S_H {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FRINT32X_Vd_Vn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "frint32x",
        aliases: &[],
        opcode: 0x2e21e800,
        mask: 0xbfbffc00,
        class: InsnClass::ASIMDMISC,
        feature_set: InsnFeatureSet::FRINTTS,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDMISC(ASIMDMISC::FRINT32X_Vd_Vn(FRINT32X_Vd_Vn::from(bits)))
    }
}
impl InsnOpcode for FRINT32X_Vd_Vn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FRINT32X_Fd_Fn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "frint32x",
        aliases: &[],
        opcode: 0x1e28c000,
        mask: 0xffbffc00,
        class: InsnClass::FLOATDP1,
        feature_set: InsnFeatureSet::FRINTTS,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Fd,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fn,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_FPTYPE_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::FLOATDP1(FLOATDP1::FRINT32X_Fd_Fn(FRINT32X_Fd_Fn::from(bits)))
    }
}
impl InsnOpcode for FRINT32X_Fd_Fn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FRINT32Z_Vd_Vn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "frint32z",
        aliases: &[],
        opcode: 0xe21e800,
        mask: 0xbfbffc00,
        class: InsnClass::ASIMDMISC,
        feature_set: InsnFeatureSet::FRINTTS,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDMISC(ASIMDMISC::FRINT32Z_Vd_Vn(FRINT32Z_Vd_Vn::from(bits)))
    }
}
impl InsnOpcode for FRINT32Z_Vd_Vn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FRINT32Z_Fd_Fn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "frint32z",
        aliases: &[],
        opcode: 0x1e284000,
        mask: 0xffbffc00,
        class: InsnClass::FLOATDP1,
        feature_set: InsnFeatureSet::FRINTTS,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Fd,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fn,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_FPTYPE_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::FLOATDP1(FLOATDP1::FRINT32Z_Fd_Fn(FRINT32Z_Fd_Fn::from(bits)))
    }
}
impl InsnOpcode for FRINT32Z_Fd_Fn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FRINT64X_Vd_Vn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "frint64x",
        aliases: &[],
        opcode: 0x2e21f800,
        mask: 0xbfbffc00,
        class: InsnClass::ASIMDMISC,
        feature_set: InsnFeatureSet::FRINTTS,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDMISC(ASIMDMISC::FRINT64X_Vd_Vn(FRINT64X_Vd_Vn::from(bits)))
    }
}
impl InsnOpcode for FRINT64X_Vd_Vn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FRINT64X_Fd_Fn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "frint64x",
        aliases: &[],
        opcode: 0x1e29c000,
        mask: 0xffbffc00,
        class: InsnClass::FLOATDP1,
        feature_set: InsnFeatureSet::FRINTTS,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Fd,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fn,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_FPTYPE_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::FLOATDP1(FLOATDP1::FRINT64X_Fd_Fn(FRINT64X_Fd_Fn::from(bits)))
    }
}
impl InsnOpcode for FRINT64X_Fd_Fn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FRINT64Z_Vd_Vn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "frint64z",
        aliases: &[],
        opcode: 0xe21f800,
        mask: 0xbfbffc00,
        class: InsnClass::ASIMDMISC,
        feature_set: InsnFeatureSet::FRINTTS,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDMISC(ASIMDMISC::FRINT64Z_Vd_Vn(FRINT64Z_Vd_Vn::from(bits)))
    }
}
impl InsnOpcode for FRINT64Z_Vd_Vn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FRINT64Z_Fd_Fn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "frint64z",
        aliases: &[],
        opcode: 0x1e294000,
        mask: 0xffbffc00,
        class: InsnClass::FLOATDP1,
        feature_set: InsnFeatureSet::FRINTTS,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Fd,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fn,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_FPTYPE_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::FLOATDP1(FLOATDP1::FRINT64Z_Fd_Fn(FRINT64Z_Fd_Fn::from(bits)))
    }
}
impl InsnOpcode for FRINT64Z_Fd_Fn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FRINTA_SME_Zdnx2_SME_Znx2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "frinta",
        aliases: &[],
        opcode: 0xc1ace000,
        mask: 0xfffffc21,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn2,
                    lsb: 1,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn2,
                    lsb: 6,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::FRINTA_SME_Zdnx2_SME_Znx2(
            FRINTA_SME_Zdnx2_SME_Znx2::from(bits),
        ))
    }
}
impl InsnOpcode for FRINTA_SME_Zdnx2_SME_Znx2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FRINTA_SME_Zdnx4_SME_Znx4 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "frinta",
        aliases: &[],
        opcode: 0xc1bce000,
        mask: 0xfffffc63,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn4,
                    lsb: 2,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn4,
                    lsb: 7,
                    width: 3,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::FRINTA_SME_Zdnx4_SME_Znx4(
            FRINTA_SME_Zdnx4_SME_Znx4::from(bits),
        ))
    }
}
impl InsnOpcode for FRINTA_SME_Zdnx4_SME_Znx4 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FRINTA_SVE_Zd_SVE_Pg3_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "frinta",
        aliases: &[],
        opcode: 0x6504a000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M, InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::FRINTA_SVE_Zd_SVE_Pg3_SVE_Zn(
            FRINTA_SVE_Zd_SVE_Pg3_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for FRINTA_SVE_Zd_SVE_Pg3_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FRINTA_Vd_Vn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "frinta",
        aliases: &[],
        opcode: 0x2e218800,
        mask: 0xbfbffc00,
        class: InsnClass::ASIMDMISC,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDMISC(ASIMDMISC::FRINTA_Vd_Vn(FRINTA_Vd_Vn::from(bits)))
    }
}
impl InsnOpcode for FRINTA_Vd_Vn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FRINTA_Vd_V_4H_Vn_V_4H {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "frinta",
        aliases: &[],
        opcode: 0x2e798800,
        mask: 0xbffffc00,
        class: InsnClass::ASIMDMISC,
        feature_set: InsnFeatureSet::SIMD_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDMISC(ASIMDMISC::FRINTA_Vd_V_4H_Vn_V_4H(
            FRINTA_Vd_V_4H_Vn_V_4H::from(bits),
        ))
    }
}
impl InsnOpcode for FRINTA_Vd_V_4H_Vn_V_4H {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FRINTA_Fd_Fn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "frinta",
        aliases: &[],
        opcode: 0x1ee64000,
        mask: 0xfffffc00,
        class: InsnClass::FLOATDP1,
        feature_set: InsnFeatureSet::FP_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Fd,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fn,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_FPTYPE_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::FLOATDP1(FLOATDP1::FRINTA_Fd_Fn(FRINTA_Fd_Fn::from(bits)))
    }
}
impl InsnOpcode for FRINTA_Fd_Fn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FRINTA_Fd_S_S_Fn_S_S {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "frinta",
        aliases: &[],
        opcode: 0x1e264000,
        mask: 0xff3ffc00,
        class: InsnClass::FLOATDP1,
        feature_set: InsnFeatureSet::FP,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Fd,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fn,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_FPTYPE_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::FLOATDP1(FLOATDP1::FRINTA_Fd_S_S_Fn_S_S(FRINTA_Fd_S_S_Fn_S_S::from(
            bits,
        )))
    }
}
impl InsnOpcode for FRINTA_Fd_S_S_Fn_S_S {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FRINTI_SVE_Zd_SVE_Pg3_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "frinti",
        aliases: &[],
        opcode: 0x6507a000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M, InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::FRINTI_SVE_Zd_SVE_Pg3_SVE_Zn(
            FRINTI_SVE_Zd_SVE_Pg3_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for FRINTI_SVE_Zd_SVE_Pg3_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FRINTI_Vd_Vn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "frinti",
        aliases: &[],
        opcode: 0x2ea19800,
        mask: 0xbfbffc00,
        class: InsnClass::ASIMDMISC,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDMISC(ASIMDMISC::FRINTI_Vd_Vn(FRINTI_Vd_Vn::from(bits)))
    }
}
impl InsnOpcode for FRINTI_Vd_Vn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FRINTI_Vd_V_4H_Vn_V_4H {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "frinti",
        aliases: &[],
        opcode: 0x2ef99800,
        mask: 0xbffffc00,
        class: InsnClass::ASIMDMISC,
        feature_set: InsnFeatureSet::SIMD_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDMISC(ASIMDMISC::FRINTI_Vd_V_4H_Vn_V_4H(
            FRINTI_Vd_V_4H_Vn_V_4H::from(bits),
        ))
    }
}
impl InsnOpcode for FRINTI_Vd_V_4H_Vn_V_4H {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FRINTI_Fd_Fn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "frinti",
        aliases: &[],
        opcode: 0x1ee7c000,
        mask: 0xfffffc00,
        class: InsnClass::FLOATDP1,
        feature_set: InsnFeatureSet::FP_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Fd,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fn,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_FPTYPE_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::FLOATDP1(FLOATDP1::FRINTI_Fd_Fn(FRINTI_Fd_Fn::from(bits)))
    }
}
impl InsnOpcode for FRINTI_Fd_Fn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FRINTI_Fd_S_S_Fn_S_S {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "frinti",
        aliases: &[],
        opcode: 0x1e27c000,
        mask: 0xff3ffc00,
        class: InsnClass::FLOATDP1,
        feature_set: InsnFeatureSet::FP,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Fd,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fn,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_FPTYPE_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::FLOATDP1(FLOATDP1::FRINTI_Fd_S_S_Fn_S_S(FRINTI_Fd_S_S_Fn_S_S::from(
            bits,
        )))
    }
}
impl InsnOpcode for FRINTI_Fd_S_S_Fn_S_S {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FRINTM_SME_Zdnx2_SME_Znx2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "frintm",
        aliases: &[],
        opcode: 0xc1aae000,
        mask: 0xfffffc21,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn2,
                    lsb: 1,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn2,
                    lsb: 6,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::FRINTM_SME_Zdnx2_SME_Znx2(
            FRINTM_SME_Zdnx2_SME_Znx2::from(bits),
        ))
    }
}
impl InsnOpcode for FRINTM_SME_Zdnx2_SME_Znx2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FRINTM_SME_Zdnx4_SME_Znx4 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "frintm",
        aliases: &[],
        opcode: 0xc1bae000,
        mask: 0xfffffc63,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn4,
                    lsb: 2,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn4,
                    lsb: 7,
                    width: 3,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::FRINTM_SME_Zdnx4_SME_Znx4(
            FRINTM_SME_Zdnx4_SME_Znx4::from(bits),
        ))
    }
}
impl InsnOpcode for FRINTM_SME_Zdnx4_SME_Znx4 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FRINTM_SVE_Zd_SVE_Pg3_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "frintm",
        aliases: &[],
        opcode: 0x6502a000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M, InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::FRINTM_SVE_Zd_SVE_Pg3_SVE_Zn(
            FRINTM_SVE_Zd_SVE_Pg3_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for FRINTM_SVE_Zd_SVE_Pg3_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FRINTM_Vd_Vn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "frintm",
        aliases: &[],
        opcode: 0xe219800,
        mask: 0xbfbffc00,
        class: InsnClass::ASIMDMISC,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDMISC(ASIMDMISC::FRINTM_Vd_Vn(FRINTM_Vd_Vn::from(bits)))
    }
}
impl InsnOpcode for FRINTM_Vd_Vn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FRINTM_Vd_V_4H_Vn_V_4H {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "frintm",
        aliases: &[],
        opcode: 0xe799800,
        mask: 0xbffffc00,
        class: InsnClass::ASIMDMISC,
        feature_set: InsnFeatureSet::SIMD_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDMISC(ASIMDMISC::FRINTM_Vd_V_4H_Vn_V_4H(
            FRINTM_Vd_V_4H_Vn_V_4H::from(bits),
        ))
    }
}
impl InsnOpcode for FRINTM_Vd_V_4H_Vn_V_4H {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FRINTM_Fd_Fn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "frintm",
        aliases: &[],
        opcode: 0x1ee54000,
        mask: 0xfffffc00,
        class: InsnClass::FLOATDP1,
        feature_set: InsnFeatureSet::FP_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Fd,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fn,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_FPTYPE_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::FLOATDP1(FLOATDP1::FRINTM_Fd_Fn(FRINTM_Fd_Fn::from(bits)))
    }
}
impl InsnOpcode for FRINTM_Fd_Fn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FRINTM_Fd_S_S_Fn_S_S {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "frintm",
        aliases: &[],
        opcode: 0x1e254000,
        mask: 0xff3ffc00,
        class: InsnClass::FLOATDP1,
        feature_set: InsnFeatureSet::FP,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Fd,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fn,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_FPTYPE_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::FLOATDP1(FLOATDP1::FRINTM_Fd_S_S_Fn_S_S(FRINTM_Fd_S_S_Fn_S_S::from(
            bits,
        )))
    }
}
impl InsnOpcode for FRINTM_Fd_S_S_Fn_S_S {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FRINTN_SME_Zdnx2_SME_Znx2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "frintn",
        aliases: &[],
        opcode: 0xc1a8e000,
        mask: 0xfffffc21,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn2,
                    lsb: 1,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn2,
                    lsb: 6,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::FRINTN_SME_Zdnx2_SME_Znx2(
            FRINTN_SME_Zdnx2_SME_Znx2::from(bits),
        ))
    }
}
impl InsnOpcode for FRINTN_SME_Zdnx2_SME_Znx2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FRINTN_SME_Zdnx4_SME_Znx4 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "frintn",
        aliases: &[],
        opcode: 0xc1b8e000,
        mask: 0xfffffc63,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn4,
                    lsb: 2,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn4,
                    lsb: 7,
                    width: 3,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::FRINTN_SME_Zdnx4_SME_Znx4(
            FRINTN_SME_Zdnx4_SME_Znx4::from(bits),
        ))
    }
}
impl InsnOpcode for FRINTN_SME_Zdnx4_SME_Znx4 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FRINTN_SVE_Zd_SVE_Pg3_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "frintn",
        aliases: &[],
        opcode: 0x6500a000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M, InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::FRINTN_SVE_Zd_SVE_Pg3_SVE_Zn(
            FRINTN_SVE_Zd_SVE_Pg3_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for FRINTN_SVE_Zd_SVE_Pg3_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FRINTN_Vd_Vn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "frintn",
        aliases: &[],
        opcode: 0xe218800,
        mask: 0xbfbffc00,
        class: InsnClass::ASIMDMISC,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDMISC(ASIMDMISC::FRINTN_Vd_Vn(FRINTN_Vd_Vn::from(bits)))
    }
}
impl InsnOpcode for FRINTN_Vd_Vn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FRINTN_Vd_V_4H_Vn_V_4H {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "frintn",
        aliases: &[],
        opcode: 0xe798800,
        mask: 0xbffffc00,
        class: InsnClass::ASIMDMISC,
        feature_set: InsnFeatureSet::SIMD_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDMISC(ASIMDMISC::FRINTN_Vd_V_4H_Vn_V_4H(
            FRINTN_Vd_V_4H_Vn_V_4H::from(bits),
        ))
    }
}
impl InsnOpcode for FRINTN_Vd_V_4H_Vn_V_4H {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FRINTN_Fd_Fn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "frintn",
        aliases: &[],
        opcode: 0x1ee44000,
        mask: 0xfffffc00,
        class: InsnClass::FLOATDP1,
        feature_set: InsnFeatureSet::FP_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Fd,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fn,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_FPTYPE_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::FLOATDP1(FLOATDP1::FRINTN_Fd_Fn(FRINTN_Fd_Fn::from(bits)))
    }
}
impl InsnOpcode for FRINTN_Fd_Fn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FRINTN_Fd_S_S_Fn_S_S {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "frintn",
        aliases: &[],
        opcode: 0x1e244000,
        mask: 0xff3ffc00,
        class: InsnClass::FLOATDP1,
        feature_set: InsnFeatureSet::FP,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Fd,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fn,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_FPTYPE_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::FLOATDP1(FLOATDP1::FRINTN_Fd_S_S_Fn_S_S(FRINTN_Fd_S_S_Fn_S_S::from(
            bits,
        )))
    }
}
impl InsnOpcode for FRINTN_Fd_S_S_Fn_S_S {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FRINTP_SME_Zdnx2_SME_Znx2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "frintp",
        aliases: &[],
        opcode: 0xc1a9e000,
        mask: 0xfffffc21,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn2,
                    lsb: 1,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn2,
                    lsb: 6,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::FRINTP_SME_Zdnx2_SME_Znx2(
            FRINTP_SME_Zdnx2_SME_Znx2::from(bits),
        ))
    }
}
impl InsnOpcode for FRINTP_SME_Zdnx2_SME_Znx2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FRINTP_SME_Zdnx4_SME_Znx4 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "frintp",
        aliases: &[],
        opcode: 0xc1b9e000,
        mask: 0xfffffc63,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn4,
                    lsb: 2,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn4,
                    lsb: 7,
                    width: 3,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::FRINTP_SME_Zdnx4_SME_Znx4(
            FRINTP_SME_Zdnx4_SME_Znx4::from(bits),
        ))
    }
}
impl InsnOpcode for FRINTP_SME_Zdnx4_SME_Znx4 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FRINTP_SVE_Zd_SVE_Pg3_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "frintp",
        aliases: &[],
        opcode: 0x6501a000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M, InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::FRINTP_SVE_Zd_SVE_Pg3_SVE_Zn(
            FRINTP_SVE_Zd_SVE_Pg3_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for FRINTP_SVE_Zd_SVE_Pg3_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FRINTP_Vd_Vn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "frintp",
        aliases: &[],
        opcode: 0xea18800,
        mask: 0xbfbffc00,
        class: InsnClass::ASIMDMISC,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDMISC(ASIMDMISC::FRINTP_Vd_Vn(FRINTP_Vd_Vn::from(bits)))
    }
}
impl InsnOpcode for FRINTP_Vd_Vn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FRINTP_Vd_V_4H_Vn_V_4H {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "frintp",
        aliases: &[],
        opcode: 0xef98800,
        mask: 0xbffffc00,
        class: InsnClass::ASIMDMISC,
        feature_set: InsnFeatureSet::SIMD_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDMISC(ASIMDMISC::FRINTP_Vd_V_4H_Vn_V_4H(
            FRINTP_Vd_V_4H_Vn_V_4H::from(bits),
        ))
    }
}
impl InsnOpcode for FRINTP_Vd_V_4H_Vn_V_4H {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FRINTP_Fd_Fn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "frintp",
        aliases: &[],
        opcode: 0x1ee4c000,
        mask: 0xfffffc00,
        class: InsnClass::FLOATDP1,
        feature_set: InsnFeatureSet::FP_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Fd,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fn,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_FPTYPE_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::FLOATDP1(FLOATDP1::FRINTP_Fd_Fn(FRINTP_Fd_Fn::from(bits)))
    }
}
impl InsnOpcode for FRINTP_Fd_Fn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FRINTP_Fd_S_S_Fn_S_S {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "frintp",
        aliases: &[],
        opcode: 0x1e24c000,
        mask: 0xff3ffc00,
        class: InsnClass::FLOATDP1,
        feature_set: InsnFeatureSet::FP,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Fd,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fn,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_FPTYPE_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::FLOATDP1(FLOATDP1::FRINTP_Fd_S_S_Fn_S_S(FRINTP_Fd_S_S_Fn_S_S::from(
            bits,
        )))
    }
}
impl InsnOpcode for FRINTP_Fd_S_S_Fn_S_S {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FRINTX_SVE_Zd_SVE_Pg3_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "frintx",
        aliases: &[],
        opcode: 0x6506a000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M, InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::FRINTX_SVE_Zd_SVE_Pg3_SVE_Zn(
            FRINTX_SVE_Zd_SVE_Pg3_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for FRINTX_SVE_Zd_SVE_Pg3_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FRINTX_Vd_Vn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "frintx",
        aliases: &[],
        opcode: 0x2e219800,
        mask: 0xbfbffc00,
        class: InsnClass::ASIMDMISC,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDMISC(ASIMDMISC::FRINTX_Vd_Vn(FRINTX_Vd_Vn::from(bits)))
    }
}
impl InsnOpcode for FRINTX_Vd_Vn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FRINTX_Vd_V_4H_Vn_V_4H {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "frintx",
        aliases: &[],
        opcode: 0x2e799800,
        mask: 0xbffffc00,
        class: InsnClass::ASIMDMISC,
        feature_set: InsnFeatureSet::SIMD_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDMISC(ASIMDMISC::FRINTX_Vd_V_4H_Vn_V_4H(
            FRINTX_Vd_V_4H_Vn_V_4H::from(bits),
        ))
    }
}
impl InsnOpcode for FRINTX_Vd_V_4H_Vn_V_4H {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FRINTX_Fd_Fn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "frintx",
        aliases: &[],
        opcode: 0x1ee74000,
        mask: 0xfffffc00,
        class: InsnClass::FLOATDP1,
        feature_set: InsnFeatureSet::FP_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Fd,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fn,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_FPTYPE_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::FLOATDP1(FLOATDP1::FRINTX_Fd_Fn(FRINTX_Fd_Fn::from(bits)))
    }
}
impl InsnOpcode for FRINTX_Fd_Fn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FRINTX_Fd_S_S_Fn_S_S {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "frintx",
        aliases: &[],
        opcode: 0x1e274000,
        mask: 0xff3ffc00,
        class: InsnClass::FLOATDP1,
        feature_set: InsnFeatureSet::FP,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Fd,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fn,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_FPTYPE_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::FLOATDP1(FLOATDP1::FRINTX_Fd_S_S_Fn_S_S(FRINTX_Fd_S_S_Fn_S_S::from(
            bits,
        )))
    }
}
impl InsnOpcode for FRINTX_Fd_S_S_Fn_S_S {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FRINTZ_SVE_Zd_SVE_Pg3_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "frintz",
        aliases: &[],
        opcode: 0x6503a000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M, InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::FRINTZ_SVE_Zd_SVE_Pg3_SVE_Zn(
            FRINTZ_SVE_Zd_SVE_Pg3_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for FRINTZ_SVE_Zd_SVE_Pg3_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FRINTZ_Vd_Vn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "frintz",
        aliases: &[],
        opcode: 0xea19800,
        mask: 0xbfbffc00,
        class: InsnClass::ASIMDMISC,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDMISC(ASIMDMISC::FRINTZ_Vd_Vn(FRINTZ_Vd_Vn::from(bits)))
    }
}
impl InsnOpcode for FRINTZ_Vd_Vn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FRINTZ_Vd_V_4H_Vn_V_4H {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "frintz",
        aliases: &[],
        opcode: 0xef99800,
        mask: 0xbffffc00,
        class: InsnClass::ASIMDMISC,
        feature_set: InsnFeatureSet::SIMD_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDMISC(ASIMDMISC::FRINTZ_Vd_V_4H_Vn_V_4H(
            FRINTZ_Vd_V_4H_Vn_V_4H::from(bits),
        ))
    }
}
impl InsnOpcode for FRINTZ_Vd_V_4H_Vn_V_4H {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FRINTZ_Fd_Fn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "frintz",
        aliases: &[],
        opcode: 0x1ee5c000,
        mask: 0xfffffc00,
        class: InsnClass::FLOATDP1,
        feature_set: InsnFeatureSet::FP_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Fd,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fn,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_FPTYPE_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::FLOATDP1(FLOATDP1::FRINTZ_Fd_Fn(FRINTZ_Fd_Fn::from(bits)))
    }
}
impl InsnOpcode for FRINTZ_Fd_Fn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FRINTZ_Fd_S_S_Fn_S_S {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "frintz",
        aliases: &[],
        opcode: 0x1e25c000,
        mask: 0xff3ffc00,
        class: InsnClass::FLOATDP1,
        feature_set: InsnFeatureSet::FP,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Fd,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fn,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_FPTYPE_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::FLOATDP1(FLOATDP1::FRINTZ_Fd_S_S_Fn_S_S(FRINTZ_Fd_S_S_Fn_S_S::from(
            bits,
        )))
    }
}
impl InsnOpcode for FRINTZ_Fd_S_S_Fn_S_S {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FRSQRTE_SVE_Zd_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "frsqrte",
        aliases: &[],
        opcode: 0x650f3000,
        mask: 0xff3ffc00,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::FRSQRTE_SVE_Zd_SVE_Zn(
            FRSQRTE_SVE_Zd_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for FRSQRTE_SVE_Zd_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FRSQRTE_Vd_Vn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "frsqrte",
        aliases: &[],
        opcode: 0x2ea1d800,
        mask: 0xbfbffc00,
        class: InsnClass::ASIMDMISC,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDMISC(ASIMDMISC::FRSQRTE_Vd_Vn(FRSQRTE_Vd_Vn::from(bits)))
    }
}
impl InsnOpcode for FRSQRTE_Vd_Vn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FRSQRTE_Vd_V_4H_Vn_V_4H {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "frsqrte",
        aliases: &[],
        opcode: 0x2ef9d800,
        mask: 0xbffffc00,
        class: InsnClass::ASIMDMISC,
        feature_set: InsnFeatureSet::SIMD_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDMISC(ASIMDMISC::FRSQRTE_Vd_V_4H_Vn_V_4H(
            FRSQRTE_Vd_V_4H_Vn_V_4H::from(bits),
        ))
    }
}
impl InsnOpcode for FRSQRTE_Vd_V_4H_Vn_V_4H {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FRSQRTE_Sd_Sn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "frsqrte",
        aliases: &[],
        opcode: 0x7ea1d800,
        mask: 0xffbffc00,
        class: InsnClass::ASISDMISC,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMD_SCALAR_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDMISC(ASISDMISC::FRSQRTE_Sd_Sn(FRSQRTE_Sd_Sn::from(bits)))
    }
}
impl InsnOpcode for FRSQRTE_Sd_Sn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FRSQRTE_Sd_S_H_Sn_S_H {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "frsqrte",
        aliases: &[],
        opcode: 0x7ef9d800,
        mask: 0xfffffc00,
        class: InsnClass::ASISDMISC,
        feature_set: InsnFeatureSet::SIMD_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMD_SCALAR_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDMISC(ASISDMISC::FRSQRTE_Sd_S_H_Sn_S_H(
            FRSQRTE_Sd_S_H_Sn_S_H::from(bits),
        ))
    }
}
impl InsnOpcode for FRSQRTE_Sd_S_H_Sn_S_H {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FRSQRTS_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "frsqrts",
        aliases: &[],
        opcode: 0x65001c00,
        mask: 0xff20fc00,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::FRSQRTS_SVE_Zd_SVE_Zn_SVE_Zm_16(
            FRSQRTS_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for FRSQRTS_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FRSQRTS_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "frsqrts",
        aliases: &[],
        opcode: 0xec03c00,
        mask: 0xbfe0fc00,
        class: InsnClass::ASIMDSAME,
        feature_set: InsnFeatureSet::SIMD_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSAME(ASIMDSAME::FRSQRTS_Vd_Vn_Vm(FRSQRTS_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for FRSQRTS_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FRSQRTS_Sd_Sn_Sm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "frsqrts",
        aliases: &[],
        opcode: 0x5ec03c00,
        mask: 0xffe0fc00,
        class: InsnClass::ASISDSAME,
        feature_set: InsnFeatureSet::SIMD_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sm,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMD_SCALAR_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDSAME(ASISDSAME::FRSQRTS_Sd_Sn_Sm(FRSQRTS_Sd_Sn_Sm::from(bits)))
    }
}
impl InsnOpcode for FRSQRTS_Sd_Sn_Sm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FRSQRTS_Vd_V_2S_Vn_V_2S_Vm_V_2S {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "frsqrts",
        aliases: &[],
        opcode: 0xea0fc00,
        mask: 0xbfa0fc00,
        class: InsnClass::ASIMDSAME,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSAME(ASIMDSAME::FRSQRTS_Vd_V_2S_Vn_V_2S_Vm_V_2S(
            FRSQRTS_Vd_V_2S_Vn_V_2S_Vm_V_2S::from(bits),
        ))
    }
}
impl InsnOpcode for FRSQRTS_Vd_V_2S_Vn_V_2S_Vm_V_2S {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FRSQRTS_Sd_S_S_Sn_S_S_Sm_S_S {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "frsqrts",
        aliases: &[],
        opcode: 0x5ea0fc00,
        mask: 0xffa0fc00,
        class: InsnClass::ASISDSAME,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sm,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMD_SCALAR_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDSAME(ASISDSAME::FRSQRTS_Sd_S_S_Sn_S_S_Sm_S_S(
            FRSQRTS_Sd_S_S_Sn_S_S_Sm_S_S::from(bits),
        ))
    }
}
impl InsnOpcode for FRSQRTS_Sd_S_S_Sn_S_S_Sm_S_S {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FSCALE_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fscale",
        aliases: &[],
        opcode: 0x65098000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_5,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_5,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::FSCALE_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(
            FSCALE_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5::from(bits),
        ))
    }
}
impl InsnOpcode for FSCALE_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FSQRT_SVE_Zd_SVE_Pg3_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fsqrt",
        aliases: &[],
        opcode: 0x650da000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M, InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::FSQRT_SVE_Zd_SVE_Pg3_SVE_Zn(
            FSQRT_SVE_Zd_SVE_Pg3_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for FSQRT_SVE_Zd_SVE_Pg3_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FSQRT_Vd_Vn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fsqrt",
        aliases: &[],
        opcode: 0x2ea1f800,
        mask: 0xbfbffc00,
        class: InsnClass::ASIMDMISC,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDMISC(ASIMDMISC::FSQRT_Vd_Vn(FSQRT_Vd_Vn::from(bits)))
    }
}
impl InsnOpcode for FSQRT_Vd_Vn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FSQRT_Vd_V_4H_Vn_V_4H {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fsqrt",
        aliases: &[],
        opcode: 0x2ef9f800,
        mask: 0xbffffc00,
        class: InsnClass::ASIMDMISC,
        feature_set: InsnFeatureSet::SIMD_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDMISC(ASIMDMISC::FSQRT_Vd_V_4H_Vn_V_4H(
            FSQRT_Vd_V_4H_Vn_V_4H::from(bits),
        ))
    }
}
impl InsnOpcode for FSQRT_Vd_V_4H_Vn_V_4H {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FSQRT_Fd_Fn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fsqrt",
        aliases: &[],
        opcode: 0x1ee1c000,
        mask: 0xfffffc00,
        class: InsnClass::FLOATDP1,
        feature_set: InsnFeatureSet::FP_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Fd,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fn,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_FPTYPE_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::FLOATDP1(FLOATDP1::FSQRT_Fd_Fn(FSQRT_Fd_Fn::from(bits)))
    }
}
impl InsnOpcode for FSQRT_Fd_Fn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FSQRT_Fd_S_S_Fn_S_S {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fsqrt",
        aliases: &[],
        opcode: 0x1e21c000,
        mask: 0xff3ffc00,
        class: InsnClass::FLOATDP1,
        feature_set: InsnFeatureSet::FP,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Fd,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fn,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_FPTYPE_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::FLOATDP1(FLOATDP1::FSQRT_Fd_S_S_Fn_S_S(FSQRT_Fd_S_S_Fn_S_S::from(
            bits,
        )))
    }
}
impl InsnOpcode for FSQRT_Fd_S_S_Fn_S_S {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FSUB_SME_ZA_array_off3_0_SME_Znx2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fsub",
        aliases: &[],
        opcode: 0xc1a01c08,
        mask: 0xffbf9c38,
        class: InsnClass::SME_FP_SD,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off3_0,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_0,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn2,
                    lsb: 6,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_FP_SD(SME_FP_SD::FSUB_SME_ZA_array_off3_0_SME_Znx2(
            FSUB_SME_ZA_array_off3_0_SME_Znx2::from(bits),
        ))
    }
}
impl InsnOpcode for FSUB_SME_ZA_array_off3_0_SME_Znx2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FSUB_SME_ZA_array_off3_0_SME_Znx4 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fsub",
        aliases: &[],
        opcode: 0xc1a11c08,
        mask: 0xffbf9c78,
        class: InsnClass::SME_FP_SD,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off3_0,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_0,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn4,
                    lsb: 7,
                    width: 3,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_4.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_FP_SD(SME_FP_SD::FSUB_SME_ZA_array_off3_0_SME_Znx4(
            FSUB_SME_ZA_array_off3_0_SME_Znx4::from(bits),
        ))
    }
}
impl InsnOpcode for FSUB_SME_ZA_array_off3_0_SME_Znx4 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FSUB_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fsub",
        aliases: &[],
        opcode: 0x65000400,
        mask: 0xff20fc00,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::FSUB_SVE_Zd_SVE_Zn_SVE_Zm_16(
            FSUB_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for FSUB_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FSUB_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fsub",
        aliases: &[],
        opcode: 0x65018000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_5,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_5,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::FSUB_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(
            FSUB_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5::from(bits),
        ))
    }
}
impl InsnOpcode for FSUB_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FSUB_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_I1_HALF_ONE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fsub",
        aliases: &[],
        opcode: 0x65198000,
        mask: 0xff3fe3c0,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_I1_HALF_ONE,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_i1,
                    lsb: 5,
                    width: 1,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::FSUB_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_I1_HALF_ONE(
            FSUB_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_I1_HALF_ONE::from(bits),
        ))
    }
}
impl InsnOpcode for FSUB_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_I1_HALF_ONE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FSUB_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fsub",
        aliases: &[],
        opcode: 0xec01400,
        mask: 0xbfe0fc00,
        class: InsnClass::ASIMDSAME,
        feature_set: InsnFeatureSet::SIMD_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSAME(ASIMDSAME::FSUB_Vd_Vn_Vm(FSUB_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for FSUB_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FSUB_Vd_V_2S_Vn_V_2S_Vm_V_2S {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fsub",
        aliases: &[],
        opcode: 0xea0d400,
        mask: 0xbfa0fc00,
        class: InsnClass::ASIMDSAME,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSAME(ASIMDSAME::FSUB_Vd_V_2S_Vn_V_2S_Vm_V_2S(
            FSUB_Vd_V_2S_Vn_V_2S_Vm_V_2S::from(bits),
        ))
    }
}
impl InsnOpcode for FSUB_Vd_V_2S_Vn_V_2S_Vm_V_2S {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FSUB_Fd_Fn_Fm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fsub",
        aliases: &[],
        opcode: 0x1ee03800,
        mask: 0xffe0fc00,
        class: InsnClass::FLOATDP2,
        feature_set: InsnFeatureSet::FP_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Fd,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fn,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fm,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_FPTYPE_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::FLOATDP2(FLOATDP2::FSUB_Fd_Fn_Fm(FSUB_Fd_Fn_Fm::from(bits)))
    }
}
impl InsnOpcode for FSUB_Fd_Fn_Fm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FSUB_Fd_S_S_Fn_S_S_Fm_S_S {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fsub",
        aliases: &[],
        opcode: 0x1e203800,
        mask: 0xff20fc00,
        class: InsnClass::FLOATDP2,
        feature_set: InsnFeatureSet::FP,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Fd,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fn,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fm,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_FPTYPE_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::FLOATDP2(FLOATDP2::FSUB_Fd_S_S_Fn_S_S_Fm_S_S(
            FSUB_Fd_S_S_Fn_S_S_Fm_S_S::from(bits),
        ))
    }
}
impl InsnOpcode for FSUB_Fd_S_S_Fn_S_S_Fm_S_S {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FSUBR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fsubr",
        aliases: &[],
        opcode: 0x65038000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_5,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_5,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::FSUBR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(
            FSUBR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5::from(bits),
        ))
    }
}
impl InsnOpcode for FSUBR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FSUBR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_I1_HALF_ONE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fsubr",
        aliases: &[],
        opcode: 0x651b8000,
        mask: 0xff3fe3c0,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_I1_HALF_ONE,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_i1,
                    lsb: 5,
                    width: 1,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::FSUBR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_I1_HALF_ONE(
            FSUBR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_I1_HALF_ONE::from(bits),
        ))
    }
}
impl InsnOpcode for FSUBR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_I1_HALF_ONE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FTMAD_SVE_Zd_SVE_Zd_SVE_Zm_5_SVE_UIMM3 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ftmad",
        aliases: &[],
        opcode: 0x65108000,
        mask: 0xff38fc00,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_5,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_5,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_UIMM3,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_imm3,
                    lsb: 16,
                    width: 3,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::FTMAD_SVE_Zd_SVE_Zd_SVE_Zm_5_SVE_UIMM3(
            FTMAD_SVE_Zd_SVE_Zd_SVE_Zm_5_SVE_UIMM3::from(bits),
        ))
    }
}
impl InsnOpcode for FTMAD_SVE_Zd_SVE_Zd_SVE_Zm_5_SVE_UIMM3 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FTSMUL_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ftsmul",
        aliases: &[],
        opcode: 0x65000c00,
        mask: 0xff20fc00,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::FTSMUL_SVE_Zd_SVE_Zn_SVE_Zm_16(
            FTSMUL_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for FTSMUL_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FTSSEL_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ftssel",
        aliases: &[],
        opcode: 0x420b000,
        mask: 0xff20fc00,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::FTSSEL_SVE_Zd_SVE_Zn_SVE_Zm_16(
            FTSSEL_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for FTSSEL_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl FVDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "fvdot",
        aliases: &[],
        opcode: 0xc1500008,
        mask: 0xfff09038,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off3_0,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_0,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn2,
                    lsb: 6,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm_INDEX2,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zm,
                        lsb: 16,
                        width: 4,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_10,
                        lsb: 10,
                        width: 2,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::FVDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2(
            FVDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2::from(bits),
        ))
    }
}
impl InsnOpcode for FVDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl GCSPOPCX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "gcspopcx",
        aliases: &[],
        opcode: 0xd50877bf,
        mask: 0xffffffff,
        class: InsnClass::GCS,
        feature_set: InsnFeatureSet::GCS,
        operands: &[],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::GCS(GCS::GCSPOPCX(GCSPOPCX::from(bits)))
    }
}
impl InsnOpcode for GCSPOPCX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl GCSPOPM {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "gcspopm",
        aliases: &[],
        opcode: 0xd52b773f,
        mask: 0xffffffff,
        class: InsnClass::GCS,
        feature_set: InsnFeatureSet::GCS,
        operands: &[],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::GCS(GCS::GCSPOPM(GCSPOPM::from(bits)))
    }
}
impl InsnOpcode for GCSPOPM {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl GCSPOPM_Rt {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "gcspopm",
        aliases: &[],
        opcode: 0xd52b7720,
        mask: 0xffffffe0,
        class: InsnClass::GCS,
        feature_set: InsnFeatureSet::GCS,
        operands: &[InsnOperand {
            kind: InsnOperandKind::Rt,
            class: InsnOperandClass::INT_REG,
            qualifiers: &[],
            bit_fields: &[BitfieldSpec {
                bitfield: InsnBitField::Rt,
                lsb: 0,
                width: 5,
            }],
        }],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::GCS(GCS::GCSPOPM_Rt(GCSPOPM_Rt::from(bits)))
    }
}
impl InsnOpcode for GCSPOPM_Rt {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl GCSPOPX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "gcspopx",
        aliases: &[],
        opcode: 0xd50877df,
        mask: 0xffffffff,
        class: InsnClass::GCS,
        feature_set: InsnFeatureSet::GCS,
        operands: &[],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::GCS(GCS::GCSPOPX(GCSPOPX::from(bits)))
    }
}
impl InsnOpcode for GCSPOPX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl GCSPUSHM_Rt {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "gcspushm",
        aliases: &[],
        opcode: 0xd50b7700,
        mask: 0xffffffe0,
        class: InsnClass::GCS,
        feature_set: InsnFeatureSet::GCS,
        operands: &[InsnOperand {
            kind: InsnOperandKind::Rt,
            class: InsnOperandClass::INT_REG,
            qualifiers: &[],
            bit_fields: &[BitfieldSpec {
                bitfield: InsnBitField::Rt,
                lsb: 0,
                width: 5,
            }],
        }],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::GCS(GCS::GCSPUSHM_Rt(GCSPUSHM_Rt::from(bits)))
    }
}
impl InsnOpcode for GCSPUSHM_Rt {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl GCSPUSHX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "gcspushx",
        aliases: &[],
        opcode: 0xd508779f,
        mask: 0xffffffff,
        class: InsnClass::GCS,
        feature_set: InsnFeatureSet::GCS,
        operands: &[],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::GCS(GCS::GCSPUSHX(GCSPUSHX::from(bits)))
    }
}
impl InsnOpcode for GCSPUSHX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl GCSSS1_Rt {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "gcsss1",
        aliases: &[],
        opcode: 0xd50b7740,
        mask: 0xffffffe0,
        class: InsnClass::GCS,
        feature_set: InsnFeatureSet::GCS,
        operands: &[InsnOperand {
            kind: InsnOperandKind::Rt,
            class: InsnOperandClass::INT_REG,
            qualifiers: &[],
            bit_fields: &[BitfieldSpec {
                bitfield: InsnBitField::Rt,
                lsb: 0,
                width: 5,
            }],
        }],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::GCS(GCS::GCSSS1_Rt(GCSSS1_Rt::from(bits)))
    }
}
impl InsnOpcode for GCSSS1_Rt {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl GCSSS2_Rt {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "gcsss2",
        aliases: &[],
        opcode: 0xd52b7760,
        mask: 0xffffffe0,
        class: InsnClass::GCS,
        feature_set: InsnFeatureSet::GCS,
        operands: &[InsnOperand {
            kind: InsnOperandKind::Rt,
            class: InsnOperandClass::INT_REG,
            qualifiers: &[],
            bit_fields: &[BitfieldSpec {
                bitfield: InsnBitField::Rt,
                lsb: 0,
                width: 5,
            }],
        }],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::GCS(GCS::GCSSS2_Rt(GCSSS2_Rt::from(bits)))
    }
}
impl InsnOpcode for GCSSS2_Rt {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl GCSSTR_Rt_Rn_SP {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "gcsstr",
        aliases: &[],
        opcode: 0xd91f0c00,
        mask: 0xfffffc00,
        class: InsnClass::GCS,
        feature_set: InsnFeatureSet::GCS,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn_SP,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::GCS(GCS::GCSSTR_Rt_Rn_SP(GCSSTR_Rt_Rn_SP::from(bits)))
    }
}
impl InsnOpcode for GCSSTR_Rt_Rn_SP {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl GCSSTTR_Rt_Rn_SP {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "gcssttr",
        aliases: &[],
        opcode: 0xd91f1c00,
        mask: 0xfffffc00,
        class: InsnClass::GCS,
        feature_set: InsnFeatureSet::GCS,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn_SP,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::GCS(GCS::GCSSTTR_Rt_Rn_SP(GCSSTTR_Rt_Rn_SP::from(bits)))
    }
}
impl InsnOpcode for GCSSTTR_Rt_Rn_SP {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl GMI_Rd_Rn_SP_Rm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "gmi",
        aliases: &[],
        opcode: 0x9ac01400,
        mask: 0xffe0fc00,
        class: InsnClass::DP_2SRC,
        feature_set: InsnFeatureSet::MEMTAG,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn_SP,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rm,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::DP_2SRC(DP_2SRC::GMI_Rd_Rn_SP_Rm(GMI_Rd_Rn_SP_Rm::from(bits)))
    }
}
impl InsnOpcode for GMI_Rd_Rn_SP_Rm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl HINT_UIMM7 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "hint",
        aliases: &[],
        opcode: 0xd503201f,
        mask: 0xfffff01f,
        class: InsnClass::IC_SYSTEM,
        feature_set: InsnFeatureSet::V8,
        operands: &[InsnOperand {
            kind: InsnOperandKind::UIMM7,
            class: InsnOperandClass::IMMEDIATE,
            qualifiers: &[],
            bit_fields: &[
                BitfieldSpec {
                    bitfield: InsnBitField::CRm,
                    lsb: 8,
                    width: 4,
                },
                BitfieldSpec {
                    bitfield: InsnBitField::op2,
                    lsb: 5,
                    width: 3,
                },
            ],
        }],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ALIAS.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::IC_SYSTEM(IC_SYSTEM::HINT_UIMM7(HINT_UIMM7::from(bits)))
    }
}
impl InsnOpcode for HINT_UIMM7 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl HISTCNT_SVE_Zd_SVE_Pg3_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "histcnt",
        aliases: &[],
        opcode: 0x45a0c000,
        mask: 0xffa0e000,
        class: InsnClass::SVE_SIZE_SD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z, InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_SD(SVE_SIZE_SD::HISTCNT_SVE_Zd_SVE_Pg3_SVE_Zn_SVE_Zm_16(
            HISTCNT_SVE_Zd_SVE_Pg3_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for HISTCNT_SVE_Zd_SVE_Pg3_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl HISTSEG_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "histseg",
        aliases: &[],
        opcode: 0x4520a000,
        mask: 0xffe0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::HISTSEG_SVE_Zd_SVE_Zn_SVE_Zm_16(
            HISTSEG_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for HISTSEG_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl HLT_EXCEPTION {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "hlt",
        aliases: &[],
        opcode: 0xd4400000,
        mask: 0xffe0001f,
        class: InsnClass::EXCEPTION,
        feature_set: InsnFeatureSet::V8,
        operands: &[InsnOperand {
            kind: InsnOperandKind::EXCEPTION,
            class: InsnOperandClass::IMMEDIATE,
            qualifiers: &[],
            bit_fields: &[BitfieldSpec {
                bitfield: InsnBitField::imm16_5,
                lsb: 5,
                width: 16,
            }],
        }],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::EXCEPTION(EXCEPTION::HLT_EXCEPTION(HLT_EXCEPTION::from(bits)))
    }
}
impl InsnOpcode for HLT_EXCEPTION {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl HVC_EXCEPTION {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "hvc",
        aliases: &[],
        opcode: 0xd4000002,
        mask: 0xffe0001f,
        class: InsnClass::EXCEPTION,
        feature_set: InsnFeatureSet::V8,
        operands: &[InsnOperand {
            kind: InsnOperandKind::EXCEPTION,
            class: InsnOperandClass::IMMEDIATE,
            qualifiers: &[],
            bit_fields: &[BitfieldSpec {
                bitfield: InsnBitField::imm16_5,
                lsb: 5,
                width: 16,
            }],
        }],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::EXCEPTION(EXCEPTION::HVC_EXCEPTION(HVC_EXCEPTION::from(bits)))
    }
}
impl InsnOpcode for HVC_EXCEPTION {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl INCB_Rd_SVE_PATTERN_SCALED {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "incb",
        aliases: &[],
        opcode: 0x430e000,
        mask: 0xfff0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_PATTERN_SCALED,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_pattern,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::INCB_Rd_SVE_PATTERN_SCALED(
            INCB_Rd_SVE_PATTERN_SCALED::from(bits),
        ))
    }
}
impl InsnOpcode for INCB_Rd_SVE_PATTERN_SCALED {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl INCD_SVE_Zd_SVE_PATTERN_SCALED {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "incd",
        aliases: &[],
        opcode: 0x4f0c000,
        mask: 0xfff0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_PATTERN_SCALED,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_pattern,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::INCD_SVE_Zd_SVE_PATTERN_SCALED(
            INCD_SVE_Zd_SVE_PATTERN_SCALED::from(bits),
        ))
    }
}
impl InsnOpcode for INCD_SVE_Zd_SVE_PATTERN_SCALED {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl INCD_Rd_SVE_PATTERN_SCALED {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "incd",
        aliases: &[],
        opcode: 0x4f0e000,
        mask: 0xfff0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_PATTERN_SCALED,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_pattern,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::INCD_Rd_SVE_PATTERN_SCALED(
            INCD_Rd_SVE_PATTERN_SCALED::from(bits),
        ))
    }
}
impl InsnOpcode for INCD_Rd_SVE_PATTERN_SCALED {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl INCH_SVE_Zd_SVE_PATTERN_SCALED {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "inch",
        aliases: &[],
        opcode: 0x470c000,
        mask: 0xfff0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_PATTERN_SCALED,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_pattern,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::INCH_SVE_Zd_SVE_PATTERN_SCALED(
            INCH_SVE_Zd_SVE_PATTERN_SCALED::from(bits),
        ))
    }
}
impl InsnOpcode for INCH_SVE_Zd_SVE_PATTERN_SCALED {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl INCH_Rd_SVE_PATTERN_SCALED {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "inch",
        aliases: &[],
        opcode: 0x470e000,
        mask: 0xfff0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_PATTERN_SCALED,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_pattern,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::INCH_Rd_SVE_PATTERN_SCALED(
            INCH_Rd_SVE_PATTERN_SCALED::from(bits),
        ))
    }
}
impl InsnOpcode for INCH_Rd_SVE_PATTERN_SCALED {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl INCP_SVE_Zd_SVE_Pg4_5 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "incp",
        aliases: &[],
        opcode: 0x252c8000,
        mask: 0xff3ffe00,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg4_5,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg4_5,
                    lsb: 5,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::INCP_SVE_Zd_SVE_Pg4_5(
            INCP_SVE_Zd_SVE_Pg4_5::from(bits),
        ))
    }
}
impl InsnOpcode for INCP_SVE_Zd_SVE_Pg4_5 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl INCP_Rd_SVE_Pg4_5 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "incp",
        aliases: &[],
        opcode: 0x252c8800,
        mask: 0xff3ffe00,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg4_5,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg4_5,
                    lsb: 5,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::INCP_Rd_SVE_Pg4_5(INCP_Rd_SVE_Pg4_5::from(
            bits,
        )))
    }
}
impl InsnOpcode for INCP_Rd_SVE_Pg4_5 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl INCW_SVE_Zd_SVE_PATTERN_SCALED {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "incw",
        aliases: &[],
        opcode: 0x4b0c000,
        mask: 0xfff0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_PATTERN_SCALED,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_pattern,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::INCW_SVE_Zd_SVE_PATTERN_SCALED(
            INCW_SVE_Zd_SVE_PATTERN_SCALED::from(bits),
        ))
    }
}
impl InsnOpcode for INCW_SVE_Zd_SVE_PATTERN_SCALED {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl INCW_Rd_SVE_PATTERN_SCALED {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "incw",
        aliases: &[],
        opcode: 0x4b0e000,
        mask: 0xfff0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_PATTERN_SCALED,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_pattern,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::INCW_Rd_SVE_PATTERN_SCALED(
            INCW_Rd_SVE_PATTERN_SCALED::from(bits),
        ))
    }
}
impl InsnOpcode for INCW_Rd_SVE_PATTERN_SCALED {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl INDEX_SVE_Zd_SVE_SIMM5_SVE_SIMM5B {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "index",
        aliases: &[],
        opcode: 0x4204000,
        mask: 0xff20fc00,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_SIMM5,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_imm5,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_SIMM5B,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_imm5b,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::INDEX_SVE_Zd_SVE_SIMM5_SVE_SIMM5B(
            INDEX_SVE_Zd_SVE_SIMM5_SVE_SIMM5B::from(bits),
        ))
    }
}
impl InsnOpcode for INDEX_SVE_Zd_SVE_SIMM5_SVE_SIMM5B {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl INDEX_SVE_Zd_Rn_SIMM5 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "index",
        aliases: &[],
        opcode: 0x4204400,
        mask: 0xff20fc00,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SIMM5,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::imm5,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::INDEX_SVE_Zd_Rn_SIMM5(
            INDEX_SVE_Zd_Rn_SIMM5::from(bits),
        ))
    }
}
impl InsnOpcode for INDEX_SVE_Zd_Rn_SIMM5 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl INDEX_SVE_Zd_SVE_SIMM5_Rm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "index",
        aliases: &[],
        opcode: 0x4204800,
        mask: 0xff20fc00,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_SIMM5,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_imm5,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rm,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::INDEX_SVE_Zd_SVE_SIMM5_Rm(
            INDEX_SVE_Zd_SVE_SIMM5_Rm::from(bits),
        ))
    }
}
impl InsnOpcode for INDEX_SVE_Zd_SVE_SIMM5_Rm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl INDEX_SVE_Zd_Rn_Rm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "index",
        aliases: &[],
        opcode: 0x4204c00,
        mask: 0xff20fc00,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rm,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::INDEX_SVE_Zd_Rn_Rm(INDEX_SVE_Zd_Rn_Rm::from(
            bits,
        )))
    }
}
impl InsnOpcode for INDEX_SVE_Zd_Rn_Rm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl INS_Ed_Rn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ins",
        aliases: &[],
        opcode: 0x4e001c00,
        mask: 0xffe0fc00,
        class: InsnClass::ASIMDINS,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Ed,
                class: InsnOperandClass::SIMD_ELEMENT,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ALIAS.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDINS(ASIMDINS::INS_Ed_Rn(INS_Ed_Rn::from(bits)))
    }
}
impl InsnOpcode for INS_Ed_Rn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl INS_Ed_En {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ins",
        aliases: &[],
        opcode: 0x6e000400,
        mask: 0xffe08400,
        class: InsnClass::ASIMDINS,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Ed,
                class: InsnOperandClass::SIMD_ELEMENT,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::En,
                class: InsnOperandClass::SIMD_ELEMENT,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ALIAS.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDINS(ASIMDINS::INS_Ed_En(INS_Ed_En::from(bits)))
    }
}
impl InsnOpcode for INS_Ed_En {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl INSR_SVE_Zd_SVE_Rm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "insr",
        aliases: &[],
        opcode: 0x5243800,
        mask: 0xff3ffc00,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Rm,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Rm,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::INSR_SVE_Zd_SVE_Rm(INSR_SVE_Zd_SVE_Rm::from(
            bits,
        )))
    }
}
impl InsnOpcode for INSR_SVE_Zd_SVE_Rm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl INSR_SVE_Zd_SVE_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "insr",
        aliases: &[],
        opcode: 0x5343800,
        mask: 0xff3ffc00,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Vm,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::INSR_SVE_Zd_SVE_Vm(INSR_SVE_Zd_SVE_Vm::from(
            bits,
        )))
    }
}
impl InsnOpcode for INSR_SVE_Zd_SVE_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl IRG_Rd_SP_Rn_SP_Rm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "irg",
        aliases: &[],
        opcode: 0x9ac01000,
        mask: 0xffe0fc00,
        class: InsnClass::DP_2SRC,
        feature_set: InsnFeatureSet::MEMTAG,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd_SP,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn_SP,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rm,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::DP_2SRC(DP_2SRC::IRG_Rd_SP_Rn_SP_Rm(IRG_Rd_SP_Rn_SP_Rm::from(bits)))
    }
}
impl InsnOpcode for IRG_Rd_SP_Rn_SP_Rm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ISB_BARRIER_ISB {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "isb",
        aliases: &[],
        opcode: 0xd50330df,
        mask: 0xfffff0ff,
        class: InsnClass::IC_SYSTEM,
        feature_set: InsnFeatureSet::V8,
        operands: &[InsnOperand {
            kind: InsnOperandKind::BARRIER_ISB,
            class: InsnOperandClass::SYSTEM,
            qualifiers: &[],
            bit_fields: &[],
        }],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::IC_SYSTEM(IC_SYSTEM::ISB_BARRIER_ISB(ISB_BARRIER_ISB::from(bits)))
    }
}
impl InsnOpcode for ISB_BARRIER_ISB {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LASTA_SVE_Vd_SVE_Pg3_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "lasta",
        aliases: &[],
        opcode: 0x5228000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Vd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::LASTA_SVE_Vd_SVE_Pg3_SVE_Zn(
            LASTA_SVE_Vd_SVE_Pg3_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for LASTA_SVE_Vd_SVE_Pg3_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LASTA_Rd_SVE_Pg3_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "lasta",
        aliases: &[],
        opcode: 0x520a000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::LASTA_Rd_SVE_Pg3_SVE_Zn(
            LASTA_Rd_SVE_Pg3_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for LASTA_Rd_SVE_Pg3_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LASTB_SVE_Vd_SVE_Pg3_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "lastb",
        aliases: &[],
        opcode: 0x5238000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Vd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::LASTB_SVE_Vd_SVE_Pg3_SVE_Zn(
            LASTB_SVE_Vd_SVE_Pg3_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for LASTB_SVE_Vd_SVE_Pg3_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LASTB_Rd_SVE_Pg3_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "lastb",
        aliases: &[],
        opcode: 0x521a000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::LASTB_Rd_SVE_Pg3_SVE_Zn(
            LASTB_Rd_SVE_Pg3_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for LASTB_Rd_SVE_Pg3_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1_LVt_SIMD_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1",
        aliases: &[],
        opcode: 0xc400000,
        mask: 0xbfff0000,
        class: InsnClass::ASISDLSE,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::LVt,
                class: InsnOperandClass::SIMD_REGLIST,
                qualifiers: &[InsnOperandQualifier::V_8B],
                bit_fields: &[],
            },
            InsnOperand {
                kind: InsnOperandKind::SIMD_ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits()
                | InsnFlags::HAS_SIZEQ_FIELD.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDLSE(ASISDLSE::LD1_LVt_SIMD_ADDR_SIMPLE(
            LD1_LVt_SIMD_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for LD1_LVt_SIMD_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1_LEt_SIMD_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1",
        aliases: &[],
        opcode: 0xd400000,
        mask: 0xbfff2000,
        class: InsnClass::ASISDLSO,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::LEt,
                class: InsnOperandClass::SIMD_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[],
            },
            InsnOperand {
                kind: InsnOperandKind::SIMD_ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDLSO(ASISDLSO::LD1_LEt_SIMD_ADDR_SIMPLE(
            LD1_LEt_SIMD_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for LD1_LEt_SIMD_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1_LVt_SIMD_ADDR_POST {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1",
        aliases: &[],
        opcode: 0xcc00000,
        mask: 0xbfe00000,
        class: InsnClass::ASISDLSEP,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::LVt,
                class: InsnOperandClass::SIMD_REGLIST,
                qualifiers: &[InsnOperandQualifier::V_8B],
                bit_fields: &[],
            },
            InsnOperand {
                kind: InsnOperandKind::SIMD_ADDR_POST,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits()
                | InsnFlags::HAS_SIZEQ_FIELD.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDLSEP(ASISDLSEP::LD1_LVt_SIMD_ADDR_POST(
            LD1_LVt_SIMD_ADDR_POST::from(bits),
        ))
    }
}
impl InsnOpcode for LD1_LVt_SIMD_ADDR_POST {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1_LEt_SIMD_ADDR_POST {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1",
        aliases: &[],
        opcode: 0xdc00000,
        mask: 0xbfe02000,
        class: InsnClass::ASISDLSOP,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::LEt,
                class: InsnOperandClass::SIMD_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[],
            },
            InsnOperand {
                kind: InsnOperandKind::SIMD_ADDR_POST,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDLSOP(ASISDLSOP::LD1_LEt_SIMD_ADDR_POST(
            LD1_LEt_SIMD_ADDR_POST::from(bits),
        ))
    }
}
impl InsnOpcode for LD1_LEt_SIMD_ADDR_POST {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1B_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1b",
        aliases: &[],
        opcode: 0xa0000000,
        mask: 0xffe0e001,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn2,
                    lsb: 1,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RR,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1B_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR(
            LD1B_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR::from(bits),
        ))
    }
}
impl InsnOpcode for LD1B_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1B_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1b",
        aliases: &[],
        opcode: 0xa0008000,
        mask: 0xffe0e003,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn4,
                    lsb: 2,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RR,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1B_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR(
            LD1B_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR::from(bits),
        ))
    }
}
impl InsnOpcode for LD1B_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1B_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_RR {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1b",
        aliases: &[],
        opcode: 0xe0000000,
        mask: 0xffe00010,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_HV_idx_ldstr,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_size_22,
                        lsb: 22,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::index2,
                        lsb: 24,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_V,
                        lsb: 15,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm4_0,
                        lsb: 0,
                        width: 4,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RR,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1B_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_RR(
            LD1B_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_RR::from(bits),
        ))
    }
}
impl InsnOpcode for LD1B_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_RR {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1B_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_R {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1b",
        aliases: &[],
        opcode: 0xe0000000,
        mask: 0xffe00010,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_HV_idx_ldstr,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_size_22,
                        lsb: 22,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::index2,
                        lsb: 24,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_V,
                        lsb: 15,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm4_0,
                        lsb: 0,
                        width: 4,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_R,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1B_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_R(
            LD1B_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_R::from(bits),
        ))
    }
}
impl InsnOpcode for LD1B_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_R {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1B_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1b",
        aliases: &[],
        opcode: 0xa0400000,
        mask: 0xfff0e001,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn2,
                    lsb: 1,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4x2xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1B_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL(
            LD1B_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL::from(bits),
        ))
    }
}
impl InsnOpcode for LD1B_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1B_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1b",
        aliases: &[],
        opcode: 0xa0408000,
        mask: 0xfff0e003,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn4,
                    lsb: 2,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4x4xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1B_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL(
            LD1B_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL::from(bits),
        ))
    }
}
impl InsnOpcode for LD1B_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1B_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1b",
        aliases: &[],
        opcode: 0xa1000000,
        mask: 0xffe0e008,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Ztx2_STRIDED,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_ZtT,
                        lsb: 4,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zt3,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RR,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1B_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR(
            LD1B_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR::from(bits),
        ))
    }
}
impl InsnOpcode for LD1B_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1B_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1b",
        aliases: &[],
        opcode: 0xa1008000,
        mask: 0xffe0e00c,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Ztx4_STRIDED,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_ZtT,
                        lsb: 4,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zt2,
                        lsb: 0,
                        width: 2,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RR,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1B_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR(
            LD1B_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR::from(bits),
        ))
    }
}
impl InsnOpcode for LD1B_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1B_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1b",
        aliases: &[],
        opcode: 0xa1400000,
        mask: 0xfff0e008,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Ztx2_STRIDED,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_ZtT,
                        lsb: 4,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zt3,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4x2xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(
            SVE_MISC::LD1B_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL(
                LD1B_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL::from(bits),
            ),
        )
    }
}
impl InsnOpcode for LD1B_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1B_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1b",
        aliases: &[],
        opcode: 0xa1408000,
        mask: 0xfff0e00c,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Ztx4_STRIDED,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_ZtT,
                        lsb: 4,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zt2,
                        lsb: 0,
                        width: 2,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4x4xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(
            SVE_MISC::LD1B_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL(
                LD1B_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL::from(bits),
            ),
        )
    }
}
impl InsnOpcode for LD1B_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1b",
        aliases: &[],
        opcode: 0x84004000,
        mask: 0xffa0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RZ_XTW_22,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zm_16,
                        lsb: 16,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_xs_22,
                        lsb: 22,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22(
            LD1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22::from(bits),
        ))
    }
}
impl InsnOpcode for LD1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1B_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW_22_S_D {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1b",
        aliases: &[],
        opcode: 0xc4004000,
        mask: 0xffa0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RZ_XTW_22,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zm_16,
                        lsb: 16,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_xs_22,
                        lsb: 22,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(
            SVE_MISC::LD1B_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW_22_S_D(
                LD1B_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW_22_S_D::from(bits),
            ),
        )
    }
}
impl InsnOpcode for LD1B_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW_22_S_D {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1b",
        aliases: &[],
        opcode: 0x8420c000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_ZI_U5,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5(
            LD1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5::from(bits),
        ))
    }
}
impl InsnOpcode for LD1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1b",
        aliases: &[],
        opcode: 0xc440c000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RZ,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zm_16,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ(
            LD1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ::from(bits),
        ))
    }
}
impl InsnOpcode for LD1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1B_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_ZI_U5_S_D {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1b",
        aliases: &[],
        opcode: 0xc420c000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_ZI_U5,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1B_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_ZI_U5_S_D(
            LD1B_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_ZI_U5_S_D::from(bits),
        ))
    }
}
impl InsnOpcode for LD1B_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_ZI_U5_S_D {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1b",
        aliases: &[],
        opcode: 0xa4004000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RX,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX(
            LD1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX::from(bits),
        ))
    }
}
impl InsnOpcode for LD1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1B_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1b",
        aliases: &[],
        opcode: 0xa4404000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RX,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1B_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RX(
            LD1B_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RX::from(bits),
        ))
    }
}
impl InsnOpcode for LD1B_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1b",
        aliases: &[],
        opcode: 0xa400a000,
        mask: 0xfff0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL(
            LD1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL::from(bits),
        ))
    }
}
impl InsnOpcode for LD1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1B_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1b",
        aliases: &[],
        opcode: 0xa440a000,
        mask: 0xfff0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1B_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL(
            LD1B_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL::from(bits),
        ))
    }
}
impl InsnOpcode for LD1B_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1B_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1b",
        aliases: &[],
        opcode: 0xa4204000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RX,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1B_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RX(
            LD1B_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RX::from(bits),
        ))
    }
}
impl InsnOpcode for LD1B_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1B_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1b",
        aliases: &[],
        opcode: 0xa4604000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RX,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1B_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RX(
            LD1B_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RX::from(bits),
        ))
    }
}
impl InsnOpcode for LD1B_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1B_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1b",
        aliases: &[],
        opcode: 0xa420a000,
        mask: 0xfff0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1B_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL(
            LD1B_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL::from(bits),
        ))
    }
}
impl InsnOpcode for LD1B_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1B_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1b",
        aliases: &[],
        opcode: 0xa460a000,
        mask: 0xfff0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1B_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL(
            LD1B_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL::from(bits),
        ))
    }
}
impl InsnOpcode for LD1B_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1D_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR_LSL3 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1d",
        aliases: &[],
        opcode: 0xa0006000,
        mask: 0xffe0e001,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn2,
                    lsb: 1,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RR_LSL3,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1D_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR_LSL3(
            LD1D_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR_LSL3::from(bits),
        ))
    }
}
impl InsnOpcode for LD1D_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR_LSL3 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1D_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR_LSL3 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1d",
        aliases: &[],
        opcode: 0xa000e000,
        mask: 0xffe0e003,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn4,
                    lsb: 2,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RR_LSL3,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1D_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR_LSL3(
            LD1D_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR_LSL3::from(bits),
        ))
    }
}
impl InsnOpcode for LD1D_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR_LSL3 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1D_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1d",
        aliases: &[],
        opcode: 0xa0406000,
        mask: 0xfff0e001,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn2,
                    lsb: 1,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4x2xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1D_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL(
            LD1D_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL::from(bits),
        ))
    }
}
impl InsnOpcode for LD1D_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1D_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1d",
        aliases: &[],
        opcode: 0xa040e000,
        mask: 0xfff0e003,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn4,
                    lsb: 2,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4x4xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1D_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL(
            LD1D_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL::from(bits),
        ))
    }
}
impl InsnOpcode for LD1D_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1D_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_RR_LSL3 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1d",
        aliases: &[],
        opcode: 0xe0c00000,
        mask: 0xffe00010,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_HV_idx_ldstr,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_size_22,
                        lsb: 22,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::index2,
                        lsb: 24,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_V,
                        lsb: 15,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm4_0,
                        lsb: 0,
                        width: 4,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RR_LSL3,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1D_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_RR_LSL3(
            LD1D_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_RR_LSL3::from(bits),
        ))
    }
}
impl InsnOpcode for LD1D_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_RR_LSL3 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1D_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_R {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1d",
        aliases: &[],
        opcode: 0xe0c00000,
        mask: 0xffe00010,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_HV_idx_ldstr,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_size_22,
                        lsb: 22,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::index2,
                        lsb: 24,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_V,
                        lsb: 15,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm4_0,
                        lsb: 0,
                        width: 4,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_R,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1D_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_R(
            LD1D_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_R::from(bits),
        ))
    }
}
impl InsnOpcode for LD1D_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_R {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1D_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL3 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1d",
        aliases: &[],
        opcode: 0xa1006000,
        mask: 0xffe0e008,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Ztx2_STRIDED,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_ZtT,
                        lsb: 4,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zt3,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RR_LSL3,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1D_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL3(
            LD1D_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL3::from(bits),
        ))
    }
}
impl InsnOpcode for LD1D_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL3 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1D_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL3 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1d",
        aliases: &[],
        opcode: 0xa100e000,
        mask: 0xffe0e00c,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Ztx4_STRIDED,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_ZtT,
                        lsb: 4,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zt2,
                        lsb: 0,
                        width: 2,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RR_LSL3,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1D_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL3(
            LD1D_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL3::from(bits),
        ))
    }
}
impl InsnOpcode for LD1D_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL3 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1D_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1d",
        aliases: &[],
        opcode: 0xa1406000,
        mask: 0xfff0e008,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Ztx2_STRIDED,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_ZtT,
                        lsb: 4,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zt3,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4x2xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(
            SVE_MISC::LD1D_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL(
                LD1D_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL::from(bits),
            ),
        )
    }
}
impl InsnOpcode for LD1D_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1D_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1d",
        aliases: &[],
        opcode: 0xa140e000,
        mask: 0xfff0e00c,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Ztx4_STRIDED,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_ZtT,
                        lsb: 4,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zt2,
                        lsb: 0,
                        width: 2,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4x4xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(
            SVE_MISC::LD1D_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL(
                LD1D_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL::from(bits),
            ),
        )
    }
}
impl InsnOpcode for LD1D_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1d",
        aliases: &[],
        opcode: 0xc5804000,
        mask: 0xffa0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RZ_XTW_22,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zm_16,
                        lsb: 16,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_xs_22,
                        lsb: 22,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22(
            LD1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22::from(bits),
        ))
    }
}
impl InsnOpcode for LD1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW3_22 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1d",
        aliases: &[],
        opcode: 0xc5a04000,
        mask: 0xffa0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RZ_XTW3_22,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zm_16,
                        lsb: 16,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_xs_22,
                        lsb: 22,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW3_22(
            LD1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW3_22::from(bits),
        ))
    }
}
impl InsnOpcode for LD1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW3_22 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1d",
        aliases: &[],
        opcode: 0xc5c0c000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RZ,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zm_16,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ(
            LD1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ::from(bits),
        ))
    }
}
impl InsnOpcode for LD1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x8 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1d",
        aliases: &[],
        opcode: 0xc5a0c000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_ZI_U5x8,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x8(
            LD1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x8::from(bits),
        ))
    }
}
impl InsnOpcode for LD1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x8 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL3 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1d",
        aliases: &[],
        opcode: 0xc5e0c000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RZ_LSL3,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zm_16,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL3(
            LD1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL3::from(bits),
        ))
    }
}
impl InsnOpcode for LD1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL3 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL3 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1d",
        aliases: &[],
        opcode: 0xa5e04000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RX_LSL3,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL3(
            LD1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL3::from(bits),
        ))
    }
}
impl InsnOpcode for LD1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL3 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1d",
        aliases: &[],
        opcode: 0xa5e0a000,
        mask: 0xfff0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL(
            LD1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL::from(bits),
        ))
    }
}
impl InsnOpcode for LD1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1H_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR_LSL1 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1h",
        aliases: &[],
        opcode: 0xa0002000,
        mask: 0xffe0e001,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn2,
                    lsb: 1,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RR_LSL1,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1H_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR_LSL1(
            LD1H_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR_LSL1::from(bits),
        ))
    }
}
impl InsnOpcode for LD1H_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR_LSL1 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1H_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR_LSL1 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1h",
        aliases: &[],
        opcode: 0xa000a000,
        mask: 0xffe0e003,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn4,
                    lsb: 2,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RR_LSL1,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1H_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR_LSL1(
            LD1H_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR_LSL1::from(bits),
        ))
    }
}
impl InsnOpcode for LD1H_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR_LSL1 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1H_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1h",
        aliases: &[],
        opcode: 0xa0402000,
        mask: 0xfff0e001,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn2,
                    lsb: 1,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4x2xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1H_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL(
            LD1H_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL::from(bits),
        ))
    }
}
impl InsnOpcode for LD1H_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1H_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1h",
        aliases: &[],
        opcode: 0xa040a000,
        mask: 0xfff0e003,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn4,
                    lsb: 2,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4x4xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1H_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL(
            LD1H_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL::from(bits),
        ))
    }
}
impl InsnOpcode for LD1H_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1H_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_RR_LSL1 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1h",
        aliases: &[],
        opcode: 0xe0400000,
        mask: 0xffe00010,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_HV_idx_ldstr,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_size_22,
                        lsb: 22,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::index2,
                        lsb: 24,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_V,
                        lsb: 15,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm4_0,
                        lsb: 0,
                        width: 4,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RR_LSL1,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1H_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_RR_LSL1(
            LD1H_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_RR_LSL1::from(bits),
        ))
    }
}
impl InsnOpcode for LD1H_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_RR_LSL1 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1H_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_R {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1h",
        aliases: &[],
        opcode: 0xe0400000,
        mask: 0xffe00010,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_HV_idx_ldstr,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_size_22,
                        lsb: 22,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::index2,
                        lsb: 24,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_V,
                        lsb: 15,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm4_0,
                        lsb: 0,
                        width: 4,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_R,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1H_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_R(
            LD1H_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_R::from(bits),
        ))
    }
}
impl InsnOpcode for LD1H_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_R {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1H_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL1 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1h",
        aliases: &[],
        opcode: 0xa1002000,
        mask: 0xffe0e008,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Ztx2_STRIDED,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_ZtT,
                        lsb: 4,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zt3,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RR_LSL1,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1H_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL1(
            LD1H_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL1::from(bits),
        ))
    }
}
impl InsnOpcode for LD1H_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL1 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1H_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL1 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1h",
        aliases: &[],
        opcode: 0xa100a000,
        mask: 0xffe0e00c,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Ztx4_STRIDED,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_ZtT,
                        lsb: 4,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zt2,
                        lsb: 0,
                        width: 2,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RR_LSL1,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1H_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL1(
            LD1H_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL1::from(bits),
        ))
    }
}
impl InsnOpcode for LD1H_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL1 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1H_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1h",
        aliases: &[],
        opcode: 0xa1402000,
        mask: 0xfff0e008,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Ztx2_STRIDED,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_ZtT,
                        lsb: 4,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zt3,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4x2xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(
            SVE_MISC::LD1H_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL(
                LD1H_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL::from(bits),
            ),
        )
    }
}
impl InsnOpcode for LD1H_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1H_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1h",
        aliases: &[],
        opcode: 0xa140a000,
        mask: 0xfff0e00c,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Ztx4_STRIDED,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_ZtT,
                        lsb: 4,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zt2,
                        lsb: 0,
                        width: 2,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4x4xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(
            SVE_MISC::LD1H_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL(
                LD1H_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL::from(bits),
            ),
        )
    }
}
impl InsnOpcode for LD1H_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1h",
        aliases: &[],
        opcode: 0x84804000,
        mask: 0xffa0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RZ_XTW_22,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zm_16,
                        lsb: 16,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_xs_22,
                        lsb: 22,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22(
            LD1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22::from(bits),
        ))
    }
}
impl InsnOpcode for LD1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1H_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW_22_S_D {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1h",
        aliases: &[],
        opcode: 0xc4804000,
        mask: 0xffa0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RZ_XTW_22,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zm_16,
                        lsb: 16,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_xs_22,
                        lsb: 22,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(
            SVE_MISC::LD1H_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW_22_S_D(
                LD1H_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW_22_S_D::from(bits),
            ),
        )
    }
}
impl InsnOpcode for LD1H_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW_22_S_D {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW1_22 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1h",
        aliases: &[],
        opcode: 0x84a04000,
        mask: 0xffa0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RZ_XTW1_22,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zm_16,
                        lsb: 16,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_xs_22,
                        lsb: 22,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW1_22(
            LD1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW1_22::from(bits),
        ))
    }
}
impl InsnOpcode for LD1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW1_22 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1H_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW1_22_S_D {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1h",
        aliases: &[],
        opcode: 0xc4a04000,
        mask: 0xffa0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RZ_XTW1_22,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zm_16,
                        lsb: 16,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_xs_22,
                        lsb: 22,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(
            SVE_MISC::LD1H_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW1_22_S_D(
                LD1H_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW1_22_S_D::from(bits),
            ),
        )
    }
}
impl InsnOpcode for LD1H_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW1_22_S_D {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1h",
        aliases: &[],
        opcode: 0x84a0c000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_ZI_U5x2,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x2(
            LD1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x2::from(bits),
        ))
    }
}
impl InsnOpcode for LD1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1h",
        aliases: &[],
        opcode: 0xc4c0c000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RZ,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zm_16,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ(
            LD1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ::from(bits),
        ))
    }
}
impl InsnOpcode for LD1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1H_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_ZI_U5x2_S_D {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1h",
        aliases: &[],
        opcode: 0xc4a0c000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_ZI_U5x2,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(
            SVE_MISC::LD1H_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_ZI_U5x2_S_D(
                LD1H_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_ZI_U5x2_S_D::from(bits),
            ),
        )
    }
}
impl InsnOpcode for LD1H_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_ZI_U5x2_S_D {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL1 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1h",
        aliases: &[],
        opcode: 0xc4e0c000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RZ_LSL1,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zm_16,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL1(
            LD1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL1::from(bits),
        ))
    }
}
impl InsnOpcode for LD1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL1 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1h",
        aliases: &[],
        opcode: 0xa4c04000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RX_LSL1,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1(
            LD1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1::from(bits),
        ))
    }
}
impl InsnOpcode for LD1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1h",
        aliases: &[],
        opcode: 0xa4c0a000,
        mask: 0xfff0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL(
            LD1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL::from(bits),
        ))
    }
}
impl InsnOpcode for LD1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1H_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RX_LSL1 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1h",
        aliases: &[],
        opcode: 0xa4a04000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RX_LSL1,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1H_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RX_LSL1(
            LD1H_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RX_LSL1::from(bits),
        ))
    }
}
impl InsnOpcode for LD1H_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RX_LSL1 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1H_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RX_LSL1 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1h",
        aliases: &[],
        opcode: 0xa4e04000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RX_LSL1,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1H_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RX_LSL1(
            LD1H_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RX_LSL1::from(bits),
        ))
    }
}
impl InsnOpcode for LD1H_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RX_LSL1 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1H_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1h",
        aliases: &[],
        opcode: 0xa4a0a000,
        mask: 0xfff0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1H_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL(
            LD1H_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL::from(bits),
        ))
    }
}
impl InsnOpcode for LD1H_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1H_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1h",
        aliases: &[],
        opcode: 0xa4e0a000,
        mask: 0xfff0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1H_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL(
            LD1H_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL::from(bits),
        ))
    }
}
impl InsnOpcode for LD1H_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1Q_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_RR_LSL4 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1q",
        aliases: &[],
        opcode: 0xe1c00000,
        mask: 0xffe00010,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_HV_idx_ldstr,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_Q],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_size_22,
                        lsb: 22,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::index2,
                        lsb: 24,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_V,
                        lsb: 15,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm4_0,
                        lsb: 0,
                        width: 4,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RR_LSL4,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1Q_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_RR_LSL4(
            LD1Q_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_RR_LSL4::from(bits),
        ))
    }
}
impl InsnOpcode for LD1Q_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_RR_LSL4 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1Q_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_R {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1q",
        aliases: &[],
        opcode: 0xe1c00000,
        mask: 0xffe00010,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_HV_idx_ldstr,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_Q],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_size_22,
                        lsb: 22,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::index2,
                        lsb: 24,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_V,
                        lsb: 15,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm4_0,
                        lsb: 0,
                        width: 4,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_R,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1Q_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_R(
            LD1Q_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_R::from(bits),
        ))
    }
}
impl InsnOpcode for LD1Q_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_R {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1Q_SVE_Zt_SVE_Pg3_SVE_ADDR_ZX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1q",
        aliases: &[],
        opcode: 0xc400a000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE2P1,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zt,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_Q],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_ZX,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1Q_SVE_Zt_SVE_Pg3_SVE_ADDR_ZX(
            LD1Q_SVE_Zt_SVE_Pg3_SVE_ADDR_ZX::from(bits),
        ))
    }
}
impl InsnOpcode for LD1Q_SVE_Zt_SVE_Pg3_SVE_ADDR_ZX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1R_LVt_AL_SIMD_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1r",
        aliases: &[],
        opcode: 0xd40c000,
        mask: 0xbffff000,
        class: InsnClass::ASISDLSO,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::LVt_AL,
                class: InsnOperandClass::SIMD_REGLIST,
                qualifiers: &[InsnOperandQualifier::V_8B],
                bit_fields: &[],
            },
            InsnOperand {
                kind: InsnOperandKind::SIMD_ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits()
                | InsnFlags::HAS_SIZEQ_FIELD.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDLSO(ASISDLSO::LD1R_LVt_AL_SIMD_ADDR_SIMPLE(
            LD1R_LVt_AL_SIMD_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for LD1R_LVt_AL_SIMD_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1R_LVt_AL_SIMD_ADDR_POST {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1r",
        aliases: &[],
        opcode: 0xdc0c000,
        mask: 0xbfe0f000,
        class: InsnClass::ASISDLSOP,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::LVt_AL,
                class: InsnOperandClass::SIMD_REGLIST,
                qualifiers: &[InsnOperandQualifier::V_8B],
                bit_fields: &[],
            },
            InsnOperand {
                kind: InsnOperandKind::SIMD_ADDR_POST,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits()
                | InsnFlags::HAS_SIZEQ_FIELD.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDLSOP(ASISDLSOP::LD1R_LVt_AL_SIMD_ADDR_POST(
            LD1R_LVt_AL_SIMD_ADDR_POST::from(bits),
        ))
    }
}
impl InsnOpcode for LD1R_LVt_AL_SIMD_ADDR_POST {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1RB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_U6 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1rb",
        aliases: &[],
        opcode: 0x84408000,
        mask: 0xffc0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_U6,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1RB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_U6(
            LD1RB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_U6::from(bits),
        ))
    }
}
impl InsnOpcode for LD1RB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_U6 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1RB_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RI_U6 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1rb",
        aliases: &[],
        opcode: 0x8440c000,
        mask: 0xffc0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_U6,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1RB_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RI_U6(
            LD1RB_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RI_U6::from(bits),
        ))
    }
}
impl InsnOpcode for LD1RB_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RI_U6 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1RB_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RI_U6 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1rb",
        aliases: &[],
        opcode: 0x8440a000,
        mask: 0xffc0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_U6,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1RB_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RI_U6(
            LD1RB_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RI_U6::from(bits),
        ))
    }
}
impl InsnOpcode for LD1RB_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RI_U6 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1RB_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RI_U6 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1rb",
        aliases: &[],
        opcode: 0x8440e000,
        mask: 0xffc0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_U6,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1RB_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RI_U6(
            LD1RB_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RI_U6::from(bits),
        ))
    }
}
impl InsnOpcode for LD1RB_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RI_U6 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1RD_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_U6x8 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1rd",
        aliases: &[],
        opcode: 0x85c0e000,
        mask: 0xffc0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_U6x8,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1RD_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_U6x8(
            LD1RD_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_U6x8::from(bits),
        ))
    }
}
impl InsnOpcode for LD1RD_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_U6x8 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1RH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_U6x2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1rh",
        aliases: &[],
        opcode: 0x84c0c000,
        mask: 0xffc0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_U6x2,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1RH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_U6x2(
            LD1RH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_U6x2::from(bits),
        ))
    }
}
impl InsnOpcode for LD1RH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_U6x2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1RH_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RI_U6x2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1rh",
        aliases: &[],
        opcode: 0x84c0a000,
        mask: 0xffc0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_U6x2,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1RH_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RI_U6x2(
            LD1RH_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RI_U6x2::from(bits),
        ))
    }
}
impl InsnOpcode for LD1RH_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RI_U6x2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1RH_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RI_U6x2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1rh",
        aliases: &[],
        opcode: 0x84c0e000,
        mask: 0xffc0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_U6x2,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1RH_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RI_U6x2(
            LD1RH_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RI_U6x2::from(bits),
        ))
    }
}
impl InsnOpcode for LD1RH_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RI_U6x2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1ROB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1rob",
        aliases: &[],
        opcode: 0xa4200000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::F64MM_SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RX,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1ROB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX(
            LD1ROB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX::from(bits),
        ))
    }
}
impl InsnOpcode for LD1ROB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1ROB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x32 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1rob",
        aliases: &[],
        opcode: 0xa4202000,
        mask: 0xfff0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::F64MM_SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4x32,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1ROB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x32(
            LD1ROB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x32::from(bits),
        ))
    }
}
impl InsnOpcode for LD1ROB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x32 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1ROD_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL3 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1rod",
        aliases: &[],
        opcode: 0xa5a00000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::F64MM_SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RX_LSL3,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1ROD_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL3(
            LD1ROD_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL3::from(bits),
        ))
    }
}
impl InsnOpcode for LD1ROD_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL3 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1ROD_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x32 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1rod",
        aliases: &[],
        opcode: 0xa5a02000,
        mask: 0xfff0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::F64MM_SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4x32,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1ROD_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x32(
            LD1ROD_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x32::from(bits),
        ))
    }
}
impl InsnOpcode for LD1ROD_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x32 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1ROH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1roh",
        aliases: &[],
        opcode: 0xa4a00000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::F64MM_SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RX_LSL1,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1ROH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1(
            LD1ROH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1::from(bits),
        ))
    }
}
impl InsnOpcode for LD1ROH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1ROH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x32 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1roh",
        aliases: &[],
        opcode: 0xa4a02000,
        mask: 0xfff0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::F64MM_SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4x32,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1ROH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x32(
            LD1ROH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x32::from(bits),
        ))
    }
}
impl InsnOpcode for LD1ROH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x32 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1ROW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1row",
        aliases: &[],
        opcode: 0xa5200000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::F64MM_SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RX_LSL2,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1ROW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2(
            LD1ROW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2::from(bits),
        ))
    }
}
impl InsnOpcode for LD1ROW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1ROW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x32 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1row",
        aliases: &[],
        opcode: 0xa5202000,
        mask: 0xfff0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::F64MM_SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4x32,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1ROW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x32(
            LD1ROW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x32::from(bits),
        ))
    }
}
impl InsnOpcode for LD1ROW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x32 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1RQB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1rqb",
        aliases: &[],
        opcode: 0xa4000000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RX,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1RQB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX(
            LD1RQB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX::from(bits),
        ))
    }
}
impl InsnOpcode for LD1RQB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1RQB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1rqb",
        aliases: &[],
        opcode: 0xa4002000,
        mask: 0xfff0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4x16,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1RQB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x16(
            LD1RQB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x16::from(bits),
        ))
    }
}
impl InsnOpcode for LD1RQB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1RQD_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL3 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1rqd",
        aliases: &[],
        opcode: 0xa5800000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RX_LSL3,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1RQD_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL3(
            LD1RQD_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL3::from(bits),
        ))
    }
}
impl InsnOpcode for LD1RQD_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL3 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1RQD_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1rqd",
        aliases: &[],
        opcode: 0xa5802000,
        mask: 0xfff0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4x16,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1RQD_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x16(
            LD1RQD_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x16::from(bits),
        ))
    }
}
impl InsnOpcode for LD1RQD_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1RQH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1rqh",
        aliases: &[],
        opcode: 0xa4800000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RX_LSL1,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1RQH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1(
            LD1RQH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1::from(bits),
        ))
    }
}
impl InsnOpcode for LD1RQH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1RQH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1rqh",
        aliases: &[],
        opcode: 0xa4802000,
        mask: 0xfff0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4x16,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1RQH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x16(
            LD1RQH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x16::from(bits),
        ))
    }
}
impl InsnOpcode for LD1RQH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1RQW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1rqw",
        aliases: &[],
        opcode: 0xa5000000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RX_LSL2,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1RQW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2(
            LD1RQW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2::from(bits),
        ))
    }
}
impl InsnOpcode for LD1RQW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1RQW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1rqw",
        aliases: &[],
        opcode: 0xa5002000,
        mask: 0xfff0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4x16,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1RQW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x16(
            LD1RQW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x16::from(bits),
        ))
    }
}
impl InsnOpcode for LD1RQW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1RSB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_U6 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1rsb",
        aliases: &[],
        opcode: 0x85c08000,
        mask: 0xffc0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_U6,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1RSB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_U6(
            LD1RSB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_U6::from(bits),
        ))
    }
}
impl InsnOpcode for LD1RSB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_U6 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1RSB_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RI_U6 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1rsb",
        aliases: &[],
        opcode: 0x85c0c000,
        mask: 0xffc0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_U6,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1RSB_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RI_U6(
            LD1RSB_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RI_U6::from(bits),
        ))
    }
}
impl InsnOpcode for LD1RSB_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RI_U6 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1RSB_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RI_U6 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1rsb",
        aliases: &[],
        opcode: 0x85c0a000,
        mask: 0xffc0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_U6,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1RSB_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RI_U6(
            LD1RSB_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RI_U6::from(bits),
        ))
    }
}
impl InsnOpcode for LD1RSB_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RI_U6 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1RSH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_U6x2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1rsh",
        aliases: &[],
        opcode: 0x85408000,
        mask: 0xffc0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_U6x2,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1RSH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_U6x2(
            LD1RSH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_U6x2::from(bits),
        ))
    }
}
impl InsnOpcode for LD1RSH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_U6x2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1RSH_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RI_U6x2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1rsh",
        aliases: &[],
        opcode: 0x8540a000,
        mask: 0xffc0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_U6x2,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1RSH_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RI_U6x2(
            LD1RSH_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RI_U6x2::from(bits),
        ))
    }
}
impl InsnOpcode for LD1RSH_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RI_U6x2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1RSW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_U6x4 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1rsw",
        aliases: &[],
        opcode: 0x84c08000,
        mask: 0xffc0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_U6x4,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1RSW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_U6x4(
            LD1RSW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_U6x4::from(bits),
        ))
    }
}
impl InsnOpcode for LD1RSW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_U6x4 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1RW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_U6x4 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1rw",
        aliases: &[],
        opcode: 0x8540c000,
        mask: 0xffc0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_U6x4,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1RW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_U6x4(
            LD1RW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_U6x4::from(bits),
        ))
    }
}
impl InsnOpcode for LD1RW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_U6x4 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1RW_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RI_U6x4 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1rw",
        aliases: &[],
        opcode: 0x8540e000,
        mask: 0xffc0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_U6x4,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1RW_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RI_U6x4(
            LD1RW_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RI_U6x4::from(bits),
        ))
    }
}
impl InsnOpcode for LD1RW_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RI_U6x4 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1SB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1sb",
        aliases: &[],
        opcode: 0x84000000,
        mask: 0xffa0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RZ_XTW_22,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zm_16,
                        lsb: 16,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_xs_22,
                        lsb: 22,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1SB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22(
            LD1SB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22::from(bits),
        ))
    }
}
impl InsnOpcode for LD1SB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1SB_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW_22_S_D {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1sb",
        aliases: &[],
        opcode: 0xc4000000,
        mask: 0xffa0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RZ_XTW_22,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zm_16,
                        lsb: 16,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_xs_22,
                        lsb: 22,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(
            SVE_MISC::LD1SB_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW_22_S_D(
                LD1SB_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW_22_S_D::from(bits),
            ),
        )
    }
}
impl InsnOpcode for LD1SB_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW_22_S_D {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1SB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1sb",
        aliases: &[],
        opcode: 0x84208000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_ZI_U5,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1SB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5(
            LD1SB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5::from(bits),
        ))
    }
}
impl InsnOpcode for LD1SB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1SB_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_ZI_U5_S_D {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1sb",
        aliases: &[],
        opcode: 0xc4208000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_ZI_U5,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1SB_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_ZI_U5_S_D(
            LD1SB_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_ZI_U5_S_D::from(bits),
        ))
    }
}
impl InsnOpcode for LD1SB_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_ZI_U5_S_D {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1SB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1sb",
        aliases: &[],
        opcode: 0xc4408000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RZ,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zm_16,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1SB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ(
            LD1SB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ::from(bits),
        ))
    }
}
impl InsnOpcode for LD1SB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1SB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1sb",
        aliases: &[],
        opcode: 0xa5804000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RX,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1SB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX(
            LD1SB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX::from(bits),
        ))
    }
}
impl InsnOpcode for LD1SB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1SB_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1sb",
        aliases: &[],
        opcode: 0xa5c04000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RX,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1SB_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RX(
            LD1SB_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RX::from(bits),
        ))
    }
}
impl InsnOpcode for LD1SB_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1SB_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1sb",
        aliases: &[],
        opcode: 0xa5a04000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RX,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1SB_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RX(
            LD1SB_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RX::from(bits),
        ))
    }
}
impl InsnOpcode for LD1SB_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1SB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1sb",
        aliases: &[],
        opcode: 0xa580a000,
        mask: 0xfff0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1SB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL(
            LD1SB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL::from(bits),
        ))
    }
}
impl InsnOpcode for LD1SB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1SB_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1sb",
        aliases: &[],
        opcode: 0xa5c0a000,
        mask: 0xfff0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1SB_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL(
            LD1SB_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL::from(bits),
        ))
    }
}
impl InsnOpcode for LD1SB_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1SB_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1sb",
        aliases: &[],
        opcode: 0xa5a0a000,
        mask: 0xfff0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1SB_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL(
            LD1SB_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL::from(bits),
        ))
    }
}
impl InsnOpcode for LD1SB_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1sh",
        aliases: &[],
        opcode: 0x84800000,
        mask: 0xffa0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RZ_XTW_22,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zm_16,
                        lsb: 16,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_xs_22,
                        lsb: 22,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22(
            LD1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22::from(bits),
        ))
    }
}
impl InsnOpcode for LD1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1SH_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW_22_S_D {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1sh",
        aliases: &[],
        opcode: 0xc4800000,
        mask: 0xffa0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RZ_XTW_22,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zm_16,
                        lsb: 16,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_xs_22,
                        lsb: 22,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(
            SVE_MISC::LD1SH_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW_22_S_D(
                LD1SH_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW_22_S_D::from(bits),
            ),
        )
    }
}
impl InsnOpcode for LD1SH_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW_22_S_D {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW1_22 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1sh",
        aliases: &[],
        opcode: 0x84a00000,
        mask: 0xffa0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RZ_XTW1_22,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zm_16,
                        lsb: 16,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_xs_22,
                        lsb: 22,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW1_22(
            LD1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW1_22::from(bits),
        ))
    }
}
impl InsnOpcode for LD1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW1_22 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1SH_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW1_22_S_D {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1sh",
        aliases: &[],
        opcode: 0xc4a00000,
        mask: 0xffa0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RZ_XTW1_22,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zm_16,
                        lsb: 16,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_xs_22,
                        lsb: 22,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(
            SVE_MISC::LD1SH_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW1_22_S_D(
                LD1SH_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW1_22_S_D::from(bits),
            ),
        )
    }
}
impl InsnOpcode for LD1SH_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW1_22_S_D {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1sh",
        aliases: &[],
        opcode: 0x84a08000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_ZI_U5x2,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x2(
            LD1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x2::from(bits),
        ))
    }
}
impl InsnOpcode for LD1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1SH_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_ZI_U5x2_S_D {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1sh",
        aliases: &[],
        opcode: 0xc4a08000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_ZI_U5x2,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(
            SVE_MISC::LD1SH_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_ZI_U5x2_S_D(
                LD1SH_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_ZI_U5x2_S_D::from(bits),
            ),
        )
    }
}
impl InsnOpcode for LD1SH_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_ZI_U5x2_S_D {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1sh",
        aliases: &[],
        opcode: 0xc4c08000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RZ,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zm_16,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ(
            LD1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ::from(bits),
        ))
    }
}
impl InsnOpcode for LD1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL1 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1sh",
        aliases: &[],
        opcode: 0xc4e08000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RZ_LSL1,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zm_16,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL1(
            LD1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL1::from(bits),
        ))
    }
}
impl InsnOpcode for LD1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL1 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1sh",
        aliases: &[],
        opcode: 0xa5004000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RX_LSL1,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1(
            LD1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1::from(bits),
        ))
    }
}
impl InsnOpcode for LD1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1SH_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RX_LSL1 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1sh",
        aliases: &[],
        opcode: 0xa5204000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RX_LSL1,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1SH_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RX_LSL1(
            LD1SH_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RX_LSL1::from(bits),
        ))
    }
}
impl InsnOpcode for LD1SH_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RX_LSL1 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1sh",
        aliases: &[],
        opcode: 0xa500a000,
        mask: 0xfff0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL(
            LD1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL::from(bits),
        ))
    }
}
impl InsnOpcode for LD1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1SH_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1sh",
        aliases: &[],
        opcode: 0xa520a000,
        mask: 0xfff0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1SH_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL(
            LD1SH_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL::from(bits),
        ))
    }
}
impl InsnOpcode for LD1SH_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1sw",
        aliases: &[],
        opcode: 0xa4804000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RX_LSL2,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2(
            LD1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2::from(bits),
        ))
    }
}
impl InsnOpcode for LD1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1sw",
        aliases: &[],
        opcode: 0xa480a000,
        mask: 0xfff0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL(
            LD1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL::from(bits),
        ))
    }
}
impl InsnOpcode for LD1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1sw",
        aliases: &[],
        opcode: 0xc5000000,
        mask: 0xffa0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RZ_XTW_22,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zm_16,
                        lsb: 16,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_xs_22,
                        lsb: 22,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22(
            LD1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22::from(bits),
        ))
    }
}
impl InsnOpcode for LD1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW2_22 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1sw",
        aliases: &[],
        opcode: 0xc5200000,
        mask: 0xffa0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RZ_XTW2_22,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zm_16,
                        lsb: 16,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_xs_22,
                        lsb: 22,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW2_22(
            LD1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW2_22::from(bits),
        ))
    }
}
impl InsnOpcode for LD1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW2_22 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1sw",
        aliases: &[],
        opcode: 0xc5408000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RZ,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zm_16,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ(
            LD1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ::from(bits),
        ))
    }
}
impl InsnOpcode for LD1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x4 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1sw",
        aliases: &[],
        opcode: 0xc5208000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_ZI_U5x4,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x4(
            LD1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x4::from(bits),
        ))
    }
}
impl InsnOpcode for LD1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x4 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1sw",
        aliases: &[],
        opcode: 0xc5608000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RZ_LSL2,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zm_16,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL2(
            LD1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL2::from(bits),
        ))
    }
}
impl InsnOpcode for LD1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1W_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR_LSL2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1w",
        aliases: &[],
        opcode: 0xa0004000,
        mask: 0xffe0e001,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn2,
                    lsb: 1,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RR_LSL2,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1W_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR_LSL2(
            LD1W_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR_LSL2::from(bits),
        ))
    }
}
impl InsnOpcode for LD1W_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR_LSL2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1W_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR_LSL2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1w",
        aliases: &[],
        opcode: 0xa000c000,
        mask: 0xffe0e003,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn4,
                    lsb: 2,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RR_LSL2,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1W_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR_LSL2(
            LD1W_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR_LSL2::from(bits),
        ))
    }
}
impl InsnOpcode for LD1W_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR_LSL2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1W_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_RR_LSL2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1w",
        aliases: &[],
        opcode: 0xe0800000,
        mask: 0xffe00010,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_HV_idx_ldstr,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_size_22,
                        lsb: 22,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::index2,
                        lsb: 24,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_V,
                        lsb: 15,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm4_0,
                        lsb: 0,
                        width: 4,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RR_LSL2,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1W_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_RR_LSL2(
            LD1W_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_RR_LSL2::from(bits),
        ))
    }
}
impl InsnOpcode for LD1W_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_RR_LSL2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1W_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_R {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1w",
        aliases: &[],
        opcode: 0xe0800000,
        mask: 0xffe00010,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_HV_idx_ldstr,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_size_22,
                        lsb: 22,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::index2,
                        lsb: 24,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_V,
                        lsb: 15,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm4_0,
                        lsb: 0,
                        width: 4,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_R,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1W_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_R(
            LD1W_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_R::from(bits),
        ))
    }
}
impl InsnOpcode for LD1W_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_R {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1W_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1w",
        aliases: &[],
        opcode: 0xa0404000,
        mask: 0xfff0e001,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn2,
                    lsb: 1,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4x2xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1W_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL(
            LD1W_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL::from(bits),
        ))
    }
}
impl InsnOpcode for LD1W_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1W_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1w",
        aliases: &[],
        opcode: 0xa040c000,
        mask: 0xfff0e003,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn4,
                    lsb: 2,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4x4xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1W_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL(
            LD1W_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL::from(bits),
        ))
    }
}
impl InsnOpcode for LD1W_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1W_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1w",
        aliases: &[],
        opcode: 0xa1004000,
        mask: 0xffe0e008,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Ztx2_STRIDED,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_ZtT,
                        lsb: 4,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zt3,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RR_LSL2,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1W_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL2(
            LD1W_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL2::from(bits),
        ))
    }
}
impl InsnOpcode for LD1W_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1W_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1w",
        aliases: &[],
        opcode: 0xa100c000,
        mask: 0xffe0e00c,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Ztx4_STRIDED,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_ZtT,
                        lsb: 4,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zt2,
                        lsb: 0,
                        width: 2,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RR_LSL2,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1W_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL2(
            LD1W_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL2::from(bits),
        ))
    }
}
impl InsnOpcode for LD1W_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1W_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1w",
        aliases: &[],
        opcode: 0xa1404000,
        mask: 0xfff0e008,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Ztx2_STRIDED,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_ZtT,
                        lsb: 4,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zt3,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4x2xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(
            SVE_MISC::LD1W_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL(
                LD1W_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL::from(bits),
            ),
        )
    }
}
impl InsnOpcode for LD1W_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1W_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1w",
        aliases: &[],
        opcode: 0xa140c000,
        mask: 0xfff0e00c,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Ztx4_STRIDED,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_ZtT,
                        lsb: 4,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zt2,
                        lsb: 0,
                        width: 2,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4x4xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(
            SVE_MISC::LD1W_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL(
                LD1W_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL::from(bits),
            ),
        )
    }
}
impl InsnOpcode for LD1W_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1w",
        aliases: &[],
        opcode: 0x85004000,
        mask: 0xffa0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RZ_XTW_22,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zm_16,
                        lsb: 16,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_xs_22,
                        lsb: 22,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22(
            LD1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22::from(bits),
        ))
    }
}
impl InsnOpcode for LD1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW2_22 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1w",
        aliases: &[],
        opcode: 0x85204000,
        mask: 0xffa0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RZ_XTW2_22,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zm_16,
                        lsb: 16,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_xs_22,
                        lsb: 22,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW2_22(
            LD1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW2_22::from(bits),
        ))
    }
}
impl InsnOpcode for LD1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW2_22 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x4 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1w",
        aliases: &[],
        opcode: 0x8520c000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_ZI_U5x4,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x4(
            LD1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x4::from(bits),
        ))
    }
}
impl InsnOpcode for LD1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x4 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1W_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW_22_S_D {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1w",
        aliases: &[],
        opcode: 0xc5004000,
        mask: 0xffa0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RZ_XTW_22,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zm_16,
                        lsb: 16,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_xs_22,
                        lsb: 22,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(
            SVE_MISC::LD1W_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW_22_S_D(
                LD1W_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW_22_S_D::from(bits),
            ),
        )
    }
}
impl InsnOpcode for LD1W_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW_22_S_D {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1W_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW2_22_S_D {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1w",
        aliases: &[],
        opcode: 0xc5204000,
        mask: 0xffa0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RZ_XTW2_22,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zm_16,
                        lsb: 16,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_xs_22,
                        lsb: 22,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(
            SVE_MISC::LD1W_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW2_22_S_D(
                LD1W_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW2_22_S_D::from(bits),
            ),
        )
    }
}
impl InsnOpcode for LD1W_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW2_22_S_D {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1w",
        aliases: &[],
        opcode: 0xc540c000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RZ,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zm_16,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ(
            LD1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ::from(bits),
        ))
    }
}
impl InsnOpcode for LD1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1W_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_ZI_U5x4_S_D {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1w",
        aliases: &[],
        opcode: 0xc520c000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_ZI_U5x4,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(
            SVE_MISC::LD1W_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_ZI_U5x4_S_D(
                LD1W_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_ZI_U5x4_S_D::from(bits),
            ),
        )
    }
}
impl InsnOpcode for LD1W_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_ZI_U5x4_S_D {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1w",
        aliases: &[],
        opcode: 0xc560c000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RZ_LSL2,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zm_16,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL2(
            LD1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL2::from(bits),
        ))
    }
}
impl InsnOpcode for LD1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1w",
        aliases: &[],
        opcode: 0xa5404000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RX_LSL2,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2(
            LD1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2::from(bits),
        ))
    }
}
impl InsnOpcode for LD1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1W_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RX_LSL2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1w",
        aliases: &[],
        opcode: 0xa5604000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RX_LSL2,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1W_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RX_LSL2(
            LD1W_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RX_LSL2::from(bits),
        ))
    }
}
impl InsnOpcode for LD1W_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RX_LSL2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1w",
        aliases: &[],
        opcode: 0xa540a000,
        mask: 0xfff0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL(
            LD1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL::from(bits),
        ))
    }
}
impl InsnOpcode for LD1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD1W_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld1w",
        aliases: &[],
        opcode: 0xa560a000,
        mask: 0xfff0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD1W_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL(
            LD1W_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL::from(bits),
        ))
    }
}
impl InsnOpcode for LD1W_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD2_LVt_SIMD_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld2",
        aliases: &[],
        opcode: 0xc400000,
        mask: 0xbfff0000,
        class: InsnClass::ASISDLSE,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::LVt,
                class: InsnOperandClass::SIMD_REGLIST,
                qualifiers: &[InsnOperandQualifier::V_8B],
                bit_fields: &[],
            },
            InsnOperand {
                kind: InsnOperandKind::SIMD_ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits()
                | InsnFlags::HAS_SIZEQ_FIELD.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDLSE(ASISDLSE::LD2_LVt_SIMD_ADDR_SIMPLE(
            LD2_LVt_SIMD_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for LD2_LVt_SIMD_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD2_LEt_SIMD_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld2",
        aliases: &[],
        opcode: 0xd600000,
        mask: 0xbfff2000,
        class: InsnClass::ASISDLSO,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::LEt,
                class: InsnOperandClass::SIMD_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[],
            },
            InsnOperand {
                kind: InsnOperandKind::SIMD_ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDLSO(ASISDLSO::LD2_LEt_SIMD_ADDR_SIMPLE(
            LD2_LEt_SIMD_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for LD2_LEt_SIMD_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD2_LVt_SIMD_ADDR_POST {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld2",
        aliases: &[],
        opcode: 0xcc00000,
        mask: 0xbfe00000,
        class: InsnClass::ASISDLSEP,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::LVt,
                class: InsnOperandClass::SIMD_REGLIST,
                qualifiers: &[InsnOperandQualifier::V_8B],
                bit_fields: &[],
            },
            InsnOperand {
                kind: InsnOperandKind::SIMD_ADDR_POST,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits()
                | InsnFlags::HAS_SIZEQ_FIELD.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDLSEP(ASISDLSEP::LD2_LVt_SIMD_ADDR_POST(
            LD2_LVt_SIMD_ADDR_POST::from(bits),
        ))
    }
}
impl InsnOpcode for LD2_LVt_SIMD_ADDR_POST {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD2_LEt_SIMD_ADDR_POST {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld2",
        aliases: &[],
        opcode: 0xde00000,
        mask: 0xbfe02000,
        class: InsnClass::ASISDLSOP,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::LEt,
                class: InsnOperandClass::SIMD_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[],
            },
            InsnOperand {
                kind: InsnOperandKind::SIMD_ADDR_POST,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDLSOP(ASISDLSOP::LD2_LEt_SIMD_ADDR_POST(
            LD2_LEt_SIMD_ADDR_POST::from(bits),
        ))
    }
}
impl InsnOpcode for LD2_LEt_SIMD_ADDR_POST {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD2B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld2b",
        aliases: &[],
        opcode: 0xa420c000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RX,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD2B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX(
            LD2B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX::from(bits),
        ))
    }
}
impl InsnOpcode for LD2B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD2B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x2xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld2b",
        aliases: &[],
        opcode: 0xa420e000,
        mask: 0xfff0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4x2xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD2B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x2xVL(
            LD2B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x2xVL::from(bits),
        ))
    }
}
impl InsnOpcode for LD2B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x2xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD2D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL3 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld2d",
        aliases: &[],
        opcode: 0xa5a0c000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RX_LSL3,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD2D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL3(
            LD2D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL3::from(bits),
        ))
    }
}
impl InsnOpcode for LD2D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL3 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD2D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x2xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld2d",
        aliases: &[],
        opcode: 0xa5a0e000,
        mask: 0xfff0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4x2xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD2D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x2xVL(
            LD2D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x2xVL::from(bits),
        ))
    }
}
impl InsnOpcode for LD2D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x2xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD2H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld2h",
        aliases: &[],
        opcode: 0xa4a0c000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RX_LSL1,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD2H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1(
            LD2H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1::from(bits),
        ))
    }
}
impl InsnOpcode for LD2H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD2H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x2xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld2h",
        aliases: &[],
        opcode: 0xa4a0e000,
        mask: 0xfff0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4x2xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD2H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x2xVL(
            LD2H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x2xVL::from(bits),
        ))
    }
}
impl InsnOpcode for LD2H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x2xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD2Q_SME_Zt2_SVE_Pg3_SVE_ADDR_RI_S4x2xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld2q",
        aliases: &[],
        opcode: 0xa490e000,
        mask: 0xfff0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE2P1,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zt2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_Q],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4x2xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD2Q_SME_Zt2_SVE_Pg3_SVE_ADDR_RI_S4x2xVL(
            LD2Q_SME_Zt2_SVE_Pg3_SVE_ADDR_RI_S4x2xVL::from(bits),
        ))
    }
}
impl InsnOpcode for LD2Q_SME_Zt2_SVE_Pg3_SVE_ADDR_RI_S4x2xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD2Q_SME_Zt2_SVE_Pg3_SVE_ADDR_RR_LSL4 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld2q",
        aliases: &[],
        opcode: 0xa4a0e000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE2P1,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zt2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_Q],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RR_LSL4,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD2Q_SME_Zt2_SVE_Pg3_SVE_ADDR_RR_LSL4(
            LD2Q_SME_Zt2_SVE_Pg3_SVE_ADDR_RR_LSL4::from(bits),
        ))
    }
}
impl InsnOpcode for LD2Q_SME_Zt2_SVE_Pg3_SVE_ADDR_RR_LSL4 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD2R_LVt_AL_SIMD_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld2r",
        aliases: &[],
        opcode: 0xd60c000,
        mask: 0xbffff000,
        class: InsnClass::ASISDLSO,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::LVt_AL,
                class: InsnOperandClass::SIMD_REGLIST,
                qualifiers: &[InsnOperandQualifier::V_8B],
                bit_fields: &[],
            },
            InsnOperand {
                kind: InsnOperandKind::SIMD_ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits()
                | InsnFlags::HAS_SIZEQ_FIELD.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDLSO(ASISDLSO::LD2R_LVt_AL_SIMD_ADDR_SIMPLE(
            LD2R_LVt_AL_SIMD_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for LD2R_LVt_AL_SIMD_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD2R_LVt_AL_SIMD_ADDR_POST {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld2r",
        aliases: &[],
        opcode: 0xde0c000,
        mask: 0xbfe0f000,
        class: InsnClass::ASISDLSOP,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::LVt_AL,
                class: InsnOperandClass::SIMD_REGLIST,
                qualifiers: &[InsnOperandQualifier::V_8B],
                bit_fields: &[],
            },
            InsnOperand {
                kind: InsnOperandKind::SIMD_ADDR_POST,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits()
                | InsnFlags::HAS_SIZEQ_FIELD.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDLSOP(ASISDLSOP::LD2R_LVt_AL_SIMD_ADDR_POST(
            LD2R_LVt_AL_SIMD_ADDR_POST::from(bits),
        ))
    }
}
impl InsnOpcode for LD2R_LVt_AL_SIMD_ADDR_POST {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD2W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld2w",
        aliases: &[],
        opcode: 0xa520c000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RX_LSL2,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD2W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2(
            LD2W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2::from(bits),
        ))
    }
}
impl InsnOpcode for LD2W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD2W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x2xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld2w",
        aliases: &[],
        opcode: 0xa520e000,
        mask: 0xfff0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4x2xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD2W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x2xVL(
            LD2W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x2xVL::from(bits),
        ))
    }
}
impl InsnOpcode for LD2W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x2xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD3_LVt_SIMD_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld3",
        aliases: &[],
        opcode: 0xc400000,
        mask: 0xbfff0000,
        class: InsnClass::ASISDLSE,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::LVt,
                class: InsnOperandClass::SIMD_REGLIST,
                qualifiers: &[InsnOperandQualifier::V_8B],
                bit_fields: &[],
            },
            InsnOperand {
                kind: InsnOperandKind::SIMD_ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits()
                | InsnFlags::HAS_SIZEQ_FIELD.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDLSE(ASISDLSE::LD3_LVt_SIMD_ADDR_SIMPLE(
            LD3_LVt_SIMD_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for LD3_LVt_SIMD_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD3_LEt_SIMD_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld3",
        aliases: &[],
        opcode: 0xd402000,
        mask: 0xbfff2000,
        class: InsnClass::ASISDLSO,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::LEt,
                class: InsnOperandClass::SIMD_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[],
            },
            InsnOperand {
                kind: InsnOperandKind::SIMD_ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDLSO(ASISDLSO::LD3_LEt_SIMD_ADDR_SIMPLE(
            LD3_LEt_SIMD_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for LD3_LEt_SIMD_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD3_LVt_SIMD_ADDR_POST {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld3",
        aliases: &[],
        opcode: 0xcc00000,
        mask: 0xbfe00000,
        class: InsnClass::ASISDLSEP,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::LVt,
                class: InsnOperandClass::SIMD_REGLIST,
                qualifiers: &[InsnOperandQualifier::V_8B],
                bit_fields: &[],
            },
            InsnOperand {
                kind: InsnOperandKind::SIMD_ADDR_POST,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits()
                | InsnFlags::HAS_SIZEQ_FIELD.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDLSEP(ASISDLSEP::LD3_LVt_SIMD_ADDR_POST(
            LD3_LVt_SIMD_ADDR_POST::from(bits),
        ))
    }
}
impl InsnOpcode for LD3_LVt_SIMD_ADDR_POST {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD3_LEt_SIMD_ADDR_POST {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld3",
        aliases: &[],
        opcode: 0xdc02000,
        mask: 0xbfe02000,
        class: InsnClass::ASISDLSOP,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::LEt,
                class: InsnOperandClass::SIMD_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[],
            },
            InsnOperand {
                kind: InsnOperandKind::SIMD_ADDR_POST,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDLSOP(ASISDLSOP::LD3_LEt_SIMD_ADDR_POST(
            LD3_LEt_SIMD_ADDR_POST::from(bits),
        ))
    }
}
impl InsnOpcode for LD3_LEt_SIMD_ADDR_POST {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD3B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld3b",
        aliases: &[],
        opcode: 0xa440c000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RX,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD3B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX(
            LD3B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX::from(bits),
        ))
    }
}
impl InsnOpcode for LD3B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD3B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x3xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld3b",
        aliases: &[],
        opcode: 0xa440e000,
        mask: 0xfff0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4x3xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD3B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x3xVL(
            LD3B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x3xVL::from(bits),
        ))
    }
}
impl InsnOpcode for LD3B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x3xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD3D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL3 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld3d",
        aliases: &[],
        opcode: 0xa5c0c000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RX_LSL3,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD3D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL3(
            LD3D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL3::from(bits),
        ))
    }
}
impl InsnOpcode for LD3D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL3 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD3D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x3xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld3d",
        aliases: &[],
        opcode: 0xa5c0e000,
        mask: 0xfff0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4x3xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD3D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x3xVL(
            LD3D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x3xVL::from(bits),
        ))
    }
}
impl InsnOpcode for LD3D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x3xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD3H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld3h",
        aliases: &[],
        opcode: 0xa4c0c000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RX_LSL1,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD3H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1(
            LD3H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1::from(bits),
        ))
    }
}
impl InsnOpcode for LD3H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD3H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x3xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld3h",
        aliases: &[],
        opcode: 0xa4c0e000,
        mask: 0xfff0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4x3xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD3H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x3xVL(
            LD3H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x3xVL::from(bits),
        ))
    }
}
impl InsnOpcode for LD3H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x3xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD3Q_SME_Zt3_SVE_Pg3_SVE_ADDR_RI_S4x2xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld3q",
        aliases: &[],
        opcode: 0xa510e000,
        mask: 0xfff0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE2P1,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zt3,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_Q],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4x2xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD3Q_SME_Zt3_SVE_Pg3_SVE_ADDR_RI_S4x2xVL(
            LD3Q_SME_Zt3_SVE_Pg3_SVE_ADDR_RI_S4x2xVL::from(bits),
        ))
    }
}
impl InsnOpcode for LD3Q_SME_Zt3_SVE_Pg3_SVE_ADDR_RI_S4x2xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD3Q_SME_Zt3_SVE_Pg3_SVE_ADDR_RR_LSL4 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld3q",
        aliases: &[],
        opcode: 0xa5208000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE2P1,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zt3,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_Q],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RR_LSL4,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD3Q_SME_Zt3_SVE_Pg3_SVE_ADDR_RR_LSL4(
            LD3Q_SME_Zt3_SVE_Pg3_SVE_ADDR_RR_LSL4::from(bits),
        ))
    }
}
impl InsnOpcode for LD3Q_SME_Zt3_SVE_Pg3_SVE_ADDR_RR_LSL4 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD3R_LVt_AL_SIMD_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld3r",
        aliases: &[],
        opcode: 0xd40e000,
        mask: 0xbffff000,
        class: InsnClass::ASISDLSO,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::LVt_AL,
                class: InsnOperandClass::SIMD_REGLIST,
                qualifiers: &[InsnOperandQualifier::V_8B],
                bit_fields: &[],
            },
            InsnOperand {
                kind: InsnOperandKind::SIMD_ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits()
                | InsnFlags::HAS_SIZEQ_FIELD.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDLSO(ASISDLSO::LD3R_LVt_AL_SIMD_ADDR_SIMPLE(
            LD3R_LVt_AL_SIMD_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for LD3R_LVt_AL_SIMD_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD3R_LVt_AL_SIMD_ADDR_POST {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld3r",
        aliases: &[],
        opcode: 0xdc0e000,
        mask: 0xbfe0f000,
        class: InsnClass::ASISDLSOP,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::LVt_AL,
                class: InsnOperandClass::SIMD_REGLIST,
                qualifiers: &[InsnOperandQualifier::V_8B],
                bit_fields: &[],
            },
            InsnOperand {
                kind: InsnOperandKind::SIMD_ADDR_POST,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits()
                | InsnFlags::HAS_SIZEQ_FIELD.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDLSOP(ASISDLSOP::LD3R_LVt_AL_SIMD_ADDR_POST(
            LD3R_LVt_AL_SIMD_ADDR_POST::from(bits),
        ))
    }
}
impl InsnOpcode for LD3R_LVt_AL_SIMD_ADDR_POST {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD3W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld3w",
        aliases: &[],
        opcode: 0xa540c000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RX_LSL2,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD3W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2(
            LD3W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2::from(bits),
        ))
    }
}
impl InsnOpcode for LD3W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD3W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x3xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld3w",
        aliases: &[],
        opcode: 0xa540e000,
        mask: 0xfff0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4x3xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD3W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x3xVL(
            LD3W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x3xVL::from(bits),
        ))
    }
}
impl InsnOpcode for LD3W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x3xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD4_LVt_SIMD_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld4",
        aliases: &[],
        opcode: 0xc400000,
        mask: 0xbfff0000,
        class: InsnClass::ASISDLSE,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::LVt,
                class: InsnOperandClass::SIMD_REGLIST,
                qualifiers: &[InsnOperandQualifier::V_8B],
                bit_fields: &[],
            },
            InsnOperand {
                kind: InsnOperandKind::SIMD_ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_4.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits()
                | InsnFlags::HAS_SIZEQ_FIELD.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDLSE(ASISDLSE::LD4_LVt_SIMD_ADDR_SIMPLE(
            LD4_LVt_SIMD_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for LD4_LVt_SIMD_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD4_LEt_SIMD_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld4",
        aliases: &[],
        opcode: 0xd602000,
        mask: 0xbfff2000,
        class: InsnClass::ASISDLSO,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::LEt,
                class: InsnOperandClass::SIMD_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[],
            },
            InsnOperand {
                kind: InsnOperandKind::SIMD_ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_4.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDLSO(ASISDLSO::LD4_LEt_SIMD_ADDR_SIMPLE(
            LD4_LEt_SIMD_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for LD4_LEt_SIMD_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD4_LVt_SIMD_ADDR_POST {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld4",
        aliases: &[],
        opcode: 0xcc00000,
        mask: 0xbfe00000,
        class: InsnClass::ASISDLSEP,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::LVt,
                class: InsnOperandClass::SIMD_REGLIST,
                qualifiers: &[InsnOperandQualifier::V_8B],
                bit_fields: &[],
            },
            InsnOperand {
                kind: InsnOperandKind::SIMD_ADDR_POST,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_4.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits()
                | InsnFlags::HAS_SIZEQ_FIELD.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDLSEP(ASISDLSEP::LD4_LVt_SIMD_ADDR_POST(
            LD4_LVt_SIMD_ADDR_POST::from(bits),
        ))
    }
}
impl InsnOpcode for LD4_LVt_SIMD_ADDR_POST {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD4_LEt_SIMD_ADDR_POST {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld4",
        aliases: &[],
        opcode: 0xde02000,
        mask: 0xbfe02000,
        class: InsnClass::ASISDLSOP,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::LEt,
                class: InsnOperandClass::SIMD_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[],
            },
            InsnOperand {
                kind: InsnOperandKind::SIMD_ADDR_POST,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_4.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDLSOP(ASISDLSOP::LD4_LEt_SIMD_ADDR_POST(
            LD4_LEt_SIMD_ADDR_POST::from(bits),
        ))
    }
}
impl InsnOpcode for LD4_LEt_SIMD_ADDR_POST {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD4B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld4b",
        aliases: &[],
        opcode: 0xa460c000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RX,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_4.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD4B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX(
            LD4B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX::from(bits),
        ))
    }
}
impl InsnOpcode for LD4B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD4B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x4xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld4b",
        aliases: &[],
        opcode: 0xa460e000,
        mask: 0xfff0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4x4xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_4.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD4B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x4xVL(
            LD4B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x4xVL::from(bits),
        ))
    }
}
impl InsnOpcode for LD4B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x4xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD4D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL3 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld4d",
        aliases: &[],
        opcode: 0xa5e0c000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RX_LSL3,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_4.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD4D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL3(
            LD4D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL3::from(bits),
        ))
    }
}
impl InsnOpcode for LD4D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL3 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD4D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x4xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld4d",
        aliases: &[],
        opcode: 0xa5e0e000,
        mask: 0xfff0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4x4xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_4.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD4D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x4xVL(
            LD4D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x4xVL::from(bits),
        ))
    }
}
impl InsnOpcode for LD4D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x4xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD4H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld4h",
        aliases: &[],
        opcode: 0xa4e0c000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RX_LSL1,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_4.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD4H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1(
            LD4H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1::from(bits),
        ))
    }
}
impl InsnOpcode for LD4H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD4H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x4xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld4h",
        aliases: &[],
        opcode: 0xa4e0e000,
        mask: 0xfff0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4x4xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_4.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD4H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x4xVL(
            LD4H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x4xVL::from(bits),
        ))
    }
}
impl InsnOpcode for LD4H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x4xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD4Q_SME_Zt4_SVE_Pg3_SVE_ADDR_RI_S4x2xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld4q",
        aliases: &[],
        opcode: 0xa590e000,
        mask: 0xfff0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE2P1,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zt4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_Q],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4x2xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD4Q_SME_Zt4_SVE_Pg3_SVE_ADDR_RI_S4x2xVL(
            LD4Q_SME_Zt4_SVE_Pg3_SVE_ADDR_RI_S4x2xVL::from(bits),
        ))
    }
}
impl InsnOpcode for LD4Q_SME_Zt4_SVE_Pg3_SVE_ADDR_RI_S4x2xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD4Q_SME_Zt4_SVE_Pg3_SVE_ADDR_RR_LSL4 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld4q",
        aliases: &[],
        opcode: 0xa5a08000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE2P1,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zt4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_Q],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RR_LSL4,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD4Q_SME_Zt4_SVE_Pg3_SVE_ADDR_RR_LSL4(
            LD4Q_SME_Zt4_SVE_Pg3_SVE_ADDR_RR_LSL4::from(bits),
        ))
    }
}
impl InsnOpcode for LD4Q_SME_Zt4_SVE_Pg3_SVE_ADDR_RR_LSL4 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD4R_LVt_AL_SIMD_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld4r",
        aliases: &[],
        opcode: 0xd60e000,
        mask: 0xbffff000,
        class: InsnClass::ASISDLSO,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::LVt_AL,
                class: InsnOperandClass::SIMD_REGLIST,
                qualifiers: &[InsnOperandQualifier::V_8B],
                bit_fields: &[],
            },
            InsnOperand {
                kind: InsnOperandKind::SIMD_ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_4.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits()
                | InsnFlags::HAS_SIZEQ_FIELD.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDLSO(ASISDLSO::LD4R_LVt_AL_SIMD_ADDR_SIMPLE(
            LD4R_LVt_AL_SIMD_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for LD4R_LVt_AL_SIMD_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD4R_LVt_AL_SIMD_ADDR_POST {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld4r",
        aliases: &[],
        opcode: 0xde0e000,
        mask: 0xbfe0f000,
        class: InsnClass::ASISDLSOP,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::LVt_AL,
                class: InsnOperandClass::SIMD_REGLIST,
                qualifiers: &[InsnOperandQualifier::V_8B],
                bit_fields: &[],
            },
            InsnOperand {
                kind: InsnOperandKind::SIMD_ADDR_POST,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_4.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits()
                | InsnFlags::HAS_SIZEQ_FIELD.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDLSOP(ASISDLSOP::LD4R_LVt_AL_SIMD_ADDR_POST(
            LD4R_LVt_AL_SIMD_ADDR_POST::from(bits),
        ))
    }
}
impl InsnOpcode for LD4R_LVt_AL_SIMD_ADDR_POST {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD4W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld4w",
        aliases: &[],
        opcode: 0xa560c000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RX_LSL2,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_4.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD4W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2(
            LD4W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2::from(bits),
        ))
    }
}
impl InsnOpcode for LD4W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD4W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x4xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld4w",
        aliases: &[],
        opcode: 0xa560e000,
        mask: 0xfff0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4x4xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_4.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LD4W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x4xVL(
            LD4W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x4xVL::from(bits),
        ))
    }
}
impl InsnOpcode for LD4W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x4xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LD64B_Rt_LS64_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ld64b",
        aliases: &[],
        opcode: 0xf83fd000,
        mask: 0xfffffc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LS64,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt_LS64,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::LD64B_Rt_LS64_ADDR_SIMPLE(
            LD64B_Rt_LS64_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for LD64B_Rt_LS64_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDADD_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldadd",
        aliases: &[],
        opcode: 0xb8200000,
        mask: 0xbfe0fc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LSE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_ALIAS.bits() | InsnFlags::HAS_LSE_SZ_FIELD.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::LDADD_Rs_Rt_ADDR_SIMPLE(
            LDADD_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for LDADD_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDADDA_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldadda",
        aliases: &[],
        opcode: 0xb8a00000,
        mask: 0xbfe0fc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LSE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_LSE_SZ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::LDADDA_Rs_Rt_ADDR_SIMPLE(
            LDADDA_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for LDADDA_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDADDAB_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldaddab",
        aliases: &[],
        opcode: 0x38a00000,
        mask: 0xffe0fc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LSE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::LDADDAB_Rs_Rt_ADDR_SIMPLE(
            LDADDAB_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for LDADDAB_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDADDAH_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldaddah",
        aliases: &[],
        opcode: 0x78a00000,
        mask: 0xffe0fc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LSE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::LDADDAH_Rs_Rt_ADDR_SIMPLE(
            LDADDAH_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for LDADDAH_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDADDAL_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldaddal",
        aliases: &[],
        opcode: 0xb8e00000,
        mask: 0xbfe0fc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LSE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_LSE_SZ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::LDADDAL_Rs_Rt_ADDR_SIMPLE(
            LDADDAL_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for LDADDAL_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDADDALB_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldaddalb",
        aliases: &[],
        opcode: 0x38e00000,
        mask: 0xffe0fc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LSE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::LDADDALB_Rs_Rt_ADDR_SIMPLE(
            LDADDALB_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for LDADDALB_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDADDALH_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldaddalh",
        aliases: &[],
        opcode: 0x78e00000,
        mask: 0xffe0fc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LSE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::LDADDALH_Rs_Rt_ADDR_SIMPLE(
            LDADDALH_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for LDADDALH_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDADDB_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldaddb",
        aliases: &[],
        opcode: 0x38200000,
        mask: 0xffe0fc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LSE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ALIAS.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::LDADDB_Rs_Rt_ADDR_SIMPLE(
            LDADDB_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for LDADDB_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDADDH_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldaddh",
        aliases: &[],
        opcode: 0x78200000,
        mask: 0xffe0fc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LSE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ALIAS.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::LDADDH_Rs_Rt_ADDR_SIMPLE(
            LDADDH_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for LDADDH_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDADDL_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldaddl",
        aliases: &[],
        opcode: 0xb8600000,
        mask: 0xbfe0fc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LSE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_ALIAS.bits() | InsnFlags::HAS_LSE_SZ_FIELD.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::LDADDL_Rs_Rt_ADDR_SIMPLE(
            LDADDL_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for LDADDL_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDADDLB_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldaddlb",
        aliases: &[],
        opcode: 0x38600000,
        mask: 0xffe0fc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LSE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ALIAS.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::LDADDLB_Rs_Rt_ADDR_SIMPLE(
            LDADDLB_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for LDADDLB_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDADDLH_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldaddlh",
        aliases: &[],
        opcode: 0x78600000,
        mask: 0xffe0fc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LSE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ALIAS.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::LDADDLH_Rs_Rt_ADDR_SIMPLE(
            LDADDLH_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for LDADDLH_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDAP1_LEt_SIMD_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldap1",
        aliases: &[],
        opcode: 0xd418400,
        mask: 0xbffffc00,
        class: InsnClass::RCPC3,
        feature_set: InsnFeatureSet::RCPC3,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::LEt,
                class: InsnOperandClass::SIMD_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[],
            },
            InsnOperand {
                kind: InsnOperandKind::SIMD_ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::RCPC3(RCPC3::LDAP1_LEt_SIMD_ADDR_SIMPLE(
            LDAP1_LEt_SIMD_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for LDAP1_LEt_SIMD_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDAPR_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldapr",
        aliases: &[],
        opcode: 0xb8bfc000,
        mask: 0xbffffc00,
        class: InsnClass::LDSTEXCL,
        feature_set: InsnFeatureSet::RCPC,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMV_GPRSIZE_IN_Q.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDSTEXCL(LDSTEXCL::LDAPR_Rt_ADDR_SIMPLE(LDAPR_Rt_ADDR_SIMPLE::from(
            bits,
        )))
    }
}
impl InsnOpcode for LDAPR_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDAPR_Rt_RCPC3_ADDR_POSTIND {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldapr",
        aliases: &[],
        opcode: 0x19c00800,
        mask: 0x3ffffc00,
        class: InsnClass::RCPC3,
        feature_set: InsnFeatureSet::RCPC3,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::RCPC3_ADDR_POSTIND,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_RCPC3_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::RCPC3(RCPC3::LDAPR_Rt_RCPC3_ADDR_POSTIND(
            LDAPR_Rt_RCPC3_ADDR_POSTIND::from(bits),
        ))
    }
}
impl InsnOpcode for LDAPR_Rt_RCPC3_ADDR_POSTIND {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDAPRB_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldaprb",
        aliases: &[],
        opcode: 0x38bfc000,
        mask: 0xfffffc00,
        class: InsnClass::LDSTEXCL,
        feature_set: InsnFeatureSet::RCPC,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDSTEXCL(LDSTEXCL::LDAPRB_Rt_ADDR_SIMPLE(
            LDAPRB_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for LDAPRB_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDAPRH_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldaprh",
        aliases: &[],
        opcode: 0x78bfc000,
        mask: 0xfffffc00,
        class: InsnClass::LDSTEXCL,
        feature_set: InsnFeatureSet::RCPC,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDSTEXCL(LDSTEXCL::LDAPRH_Rt_ADDR_SIMPLE(
            LDAPRH_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for LDAPRH_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDAPUR_Rt_ADDR_OFFSET {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldapur",
        aliases: &[],
        opcode: 0x99400000,
        mask: 0xffe00c00,
        class: InsnClass::LDST_UNSCALED,
        feature_set: InsnFeatureSet::RCPC2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_OFFSET,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm9,
                        lsb: 12,
                        width: 9,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::index,
                        lsb: 11,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDST_UNSCALED(LDST_UNSCALED::LDAPUR_Rt_ADDR_OFFSET(
            LDAPUR_Rt_ADDR_OFFSET::from(bits),
        ))
    }
}
impl InsnOpcode for LDAPUR_Rt_ADDR_OFFSET {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDAPUR_Rt_X_ADDR_OFFSET {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldapur",
        aliases: &[],
        opcode: 0xd9400000,
        mask: 0xffe00c00,
        class: InsnClass::LDST_UNSCALED,
        feature_set: InsnFeatureSet::RCPC2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_OFFSET,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm9,
                        lsb: 12,
                        width: 9,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::index,
                        lsb: 11,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDST_UNSCALED(LDST_UNSCALED::LDAPUR_Rt_X_ADDR_OFFSET(
            LDAPUR_Rt_X_ADDR_OFFSET::from(bits),
        ))
    }
}
impl InsnOpcode for LDAPUR_Rt_X_ADDR_OFFSET {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDAPUR_Ft_RCPC3_ADDR_OFFSET {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldapur",
        aliases: &[],
        opcode: 0x1d400800,
        mask: 0x3f600c00,
        class: InsnClass::RCPC3,
        feature_set: InsnFeatureSet::RCPC3,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Ft,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::RCPC3_ADDR_OFFSET,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm9,
                        lsb: 12,
                        width: 9,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_RCPC3_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::RCPC3(RCPC3::LDAPUR_Ft_RCPC3_ADDR_OFFSET(
            LDAPUR_Ft_RCPC3_ADDR_OFFSET::from(bits),
        ))
    }
}
impl InsnOpcode for LDAPUR_Ft_RCPC3_ADDR_OFFSET {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDAPURB_Rt_ADDR_OFFSET {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldapurb",
        aliases: &[],
        opcode: 0x19400000,
        mask: 0xffe00c00,
        class: InsnClass::LDST_UNSCALED,
        feature_set: InsnFeatureSet::RCPC2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_OFFSET,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm9,
                        lsb: 12,
                        width: 9,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::index,
                        lsb: 11,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDST_UNSCALED(LDST_UNSCALED::LDAPURB_Rt_ADDR_OFFSET(
            LDAPURB_Rt_ADDR_OFFSET::from(bits),
        ))
    }
}
impl InsnOpcode for LDAPURB_Rt_ADDR_OFFSET {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDAPURH_Rt_ADDR_OFFSET {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldapurh",
        aliases: &[],
        opcode: 0x59400000,
        mask: 0xffe00c00,
        class: InsnClass::LDST_UNSCALED,
        feature_set: InsnFeatureSet::RCPC2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_OFFSET,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm9,
                        lsb: 12,
                        width: 9,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::index,
                        lsb: 11,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDST_UNSCALED(LDST_UNSCALED::LDAPURH_Rt_ADDR_OFFSET(
            LDAPURH_Rt_ADDR_OFFSET::from(bits),
        ))
    }
}
impl InsnOpcode for LDAPURH_Rt_ADDR_OFFSET {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDAPURSB_Rt_ADDR_OFFSET {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldapursb",
        aliases: &[],
        opcode: 0x19800000,
        mask: 0xffe00c00,
        class: InsnClass::LDST_UNSCALED,
        feature_set: InsnFeatureSet::RCPC2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_OFFSET,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm9,
                        lsb: 12,
                        width: 9,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::index,
                        lsb: 11,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDST_UNSCALED(LDST_UNSCALED::LDAPURSB_Rt_ADDR_OFFSET(
            LDAPURSB_Rt_ADDR_OFFSET::from(bits),
        ))
    }
}
impl InsnOpcode for LDAPURSB_Rt_ADDR_OFFSET {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDAPURSB_Rt_W_ADDR_OFFSET {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldapursb",
        aliases: &[],
        opcode: 0x19c00000,
        mask: 0xffe00c00,
        class: InsnClass::LDST_UNSCALED,
        feature_set: InsnFeatureSet::RCPC2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_OFFSET,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm9,
                        lsb: 12,
                        width: 9,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::index,
                        lsb: 11,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDST_UNSCALED(LDST_UNSCALED::LDAPURSB_Rt_W_ADDR_OFFSET(
            LDAPURSB_Rt_W_ADDR_OFFSET::from(bits),
        ))
    }
}
impl InsnOpcode for LDAPURSB_Rt_W_ADDR_OFFSET {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDAPURSH_Rt_ADDR_OFFSET {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldapursh",
        aliases: &[],
        opcode: 0x59800000,
        mask: 0xffe00c00,
        class: InsnClass::LDST_UNSCALED,
        feature_set: InsnFeatureSet::RCPC2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_OFFSET,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm9,
                        lsb: 12,
                        width: 9,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::index,
                        lsb: 11,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDST_UNSCALED(LDST_UNSCALED::LDAPURSH_Rt_ADDR_OFFSET(
            LDAPURSH_Rt_ADDR_OFFSET::from(bits),
        ))
    }
}
impl InsnOpcode for LDAPURSH_Rt_ADDR_OFFSET {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDAPURSH_Rt_W_ADDR_OFFSET {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldapursh",
        aliases: &[],
        opcode: 0x59c00000,
        mask: 0xffe00c00,
        class: InsnClass::LDST_UNSCALED,
        feature_set: InsnFeatureSet::RCPC2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_OFFSET,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm9,
                        lsb: 12,
                        width: 9,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::index,
                        lsb: 11,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDST_UNSCALED(LDST_UNSCALED::LDAPURSH_Rt_W_ADDR_OFFSET(
            LDAPURSH_Rt_W_ADDR_OFFSET::from(bits),
        ))
    }
}
impl InsnOpcode for LDAPURSH_Rt_W_ADDR_OFFSET {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDAPURSW_Rt_ADDR_OFFSET {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldapursw",
        aliases: &[],
        opcode: 0x99800000,
        mask: 0xffe00c00,
        class: InsnClass::LDST_UNSCALED,
        feature_set: InsnFeatureSet::RCPC2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_OFFSET,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm9,
                        lsb: 12,
                        width: 9,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::index,
                        lsb: 11,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDST_UNSCALED(LDST_UNSCALED::LDAPURSW_Rt_ADDR_OFFSET(
            LDAPURSW_Rt_ADDR_OFFSET::from(bits),
        ))
    }
}
impl InsnOpcode for LDAPURSW_Rt_ADDR_OFFSET {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDAR_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldar",
        aliases: &[],
        opcode: 0x88dffc00,
        mask: 0xbffffc00,
        class: InsnClass::LDSTEXCL,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMV_GPRSIZE_IN_Q.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDSTEXCL(LDSTEXCL::LDAR_Rt_ADDR_SIMPLE(LDAR_Rt_ADDR_SIMPLE::from(
            bits,
        )))
    }
}
impl InsnOpcode for LDAR_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDARB_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldarb",
        aliases: &[],
        opcode: 0x8dffc00,
        mask: 0xfffffc00,
        class: InsnClass::LDSTEXCL,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDSTEXCL(LDSTEXCL::LDARB_Rt_ADDR_SIMPLE(LDARB_Rt_ADDR_SIMPLE::from(
            bits,
        )))
    }
}
impl InsnOpcode for LDARB_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDARH_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldarh",
        aliases: &[],
        opcode: 0x48dffc00,
        mask: 0xfffffc00,
        class: InsnClass::LDSTEXCL,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDSTEXCL(LDSTEXCL::LDARH_Rt_ADDR_SIMPLE(LDARH_Rt_ADDR_SIMPLE::from(
            bits,
        )))
    }
}
impl InsnOpcode for LDARH_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDAXP_Rt_Rt2_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldaxp",
        aliases: &[],
        opcode: 0x887f8000,
        mask: 0xbfff8000,
        class: InsnClass::LDSTEXCL,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt2,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt2,
                    lsb: 10,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMV_GPRSIZE_IN_Q.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDSTEXCL(LDSTEXCL::LDAXP_Rt_Rt2_ADDR_SIMPLE(
            LDAXP_Rt_Rt2_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for LDAXP_Rt_Rt2_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDAXR_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldaxr",
        aliases: &[],
        opcode: 0x885ffc00,
        mask: 0xbffffc00,
        class: InsnClass::LDSTEXCL,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMV_GPRSIZE_IN_Q.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDSTEXCL(LDSTEXCL::LDAXR_Rt_ADDR_SIMPLE(LDAXR_Rt_ADDR_SIMPLE::from(
            bits,
        )))
    }
}
impl InsnOpcode for LDAXR_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDAXRB_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldaxrb",
        aliases: &[],
        opcode: 0x85ffc00,
        mask: 0xfffffc00,
        class: InsnClass::LDSTEXCL,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDSTEXCL(LDSTEXCL::LDAXRB_Rt_ADDR_SIMPLE(
            LDAXRB_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for LDAXRB_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDAXRH_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldaxrh",
        aliases: &[],
        opcode: 0x485ffc00,
        mask: 0xfffffc00,
        class: InsnClass::LDSTEXCL,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDSTEXCL(LDSTEXCL::LDAXRH_Rt_ADDR_SIMPLE(
            LDAXRH_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for LDAXRH_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDCLR_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldclr",
        aliases: &[],
        opcode: 0xb8201000,
        mask: 0xbfe0fc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LSE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_ALIAS.bits() | InsnFlags::HAS_LSE_SZ_FIELD.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::LDCLR_Rs_Rt_ADDR_SIMPLE(
            LDCLR_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for LDCLR_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDCLRA_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldclra",
        aliases: &[],
        opcode: 0xb8a01000,
        mask: 0xbfe0fc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LSE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_LSE_SZ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::LDCLRA_Rs_Rt_ADDR_SIMPLE(
            LDCLRA_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for LDCLRA_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDCLRAB_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldclrab",
        aliases: &[],
        opcode: 0x38a01000,
        mask: 0xffe0fc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LSE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::LDCLRAB_Rs_Rt_ADDR_SIMPLE(
            LDCLRAB_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for LDCLRAB_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDCLRAH_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldclrah",
        aliases: &[],
        opcode: 0x78a01000,
        mask: 0xffe0fc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LSE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::LDCLRAH_Rs_Rt_ADDR_SIMPLE(
            LDCLRAH_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for LDCLRAH_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDCLRAL_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldclral",
        aliases: &[],
        opcode: 0xb8e01000,
        mask: 0xbfe0fc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LSE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_LSE_SZ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::LDCLRAL_Rs_Rt_ADDR_SIMPLE(
            LDCLRAL_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for LDCLRAL_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDCLRALB_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldclralb",
        aliases: &[],
        opcode: 0x38e01000,
        mask: 0xffe0fc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LSE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::LDCLRALB_Rs_Rt_ADDR_SIMPLE(
            LDCLRALB_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for LDCLRALB_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDCLRALH_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldclralh",
        aliases: &[],
        opcode: 0x78e01000,
        mask: 0xffe0fc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LSE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::LDCLRALH_Rs_Rt_ADDR_SIMPLE(
            LDCLRALH_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for LDCLRALH_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDCLRB_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldclrb",
        aliases: &[],
        opcode: 0x38201000,
        mask: 0xffe0fc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LSE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ALIAS.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::LDCLRB_Rs_Rt_ADDR_SIMPLE(
            LDCLRB_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for LDCLRB_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDCLRH_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldclrh",
        aliases: &[],
        opcode: 0x78201000,
        mask: 0xffe0fc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LSE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ALIAS.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::LDCLRH_Rs_Rt_ADDR_SIMPLE(
            LDCLRH_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for LDCLRH_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDCLRL_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldclrl",
        aliases: &[],
        opcode: 0xb8601000,
        mask: 0xbfe0fc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LSE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_ALIAS.bits() | InsnFlags::HAS_LSE_SZ_FIELD.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::LDCLRL_Rs_Rt_ADDR_SIMPLE(
            LDCLRL_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for LDCLRL_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDCLRLB_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldclrlb",
        aliases: &[],
        opcode: 0x38601000,
        mask: 0xffe0fc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LSE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ALIAS.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::LDCLRLB_Rs_Rt_ADDR_SIMPLE(
            LDCLRLB_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for LDCLRLB_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDCLRLH_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldclrlh",
        aliases: &[],
        opcode: 0x78601000,
        mask: 0xffe0fc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LSE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ALIAS.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::LDCLRLH_Rs_Rt_ADDR_SIMPLE(
            LDCLRLH_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for LDCLRLH_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDCLRP_LSE128_Rt_LSE128_Rt2_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldclrp",
        aliases: &[],
        opcode: 0x19201000,
        mask: 0xffe0fc00,
        class: InsnClass::LSE128_ATOMIC,
        feature_set: InsnFeatureSet::LSE128,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::LSE128_Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::LSE128_Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::LSE128_Rt2,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::LSE128_Rt2,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE128_ATOMIC(LSE128_ATOMIC::LDCLRP_LSE128_Rt_LSE128_Rt2_ADDR_SIMPLE(
            LDCLRP_LSE128_Rt_LSE128_Rt2_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for LDCLRP_LSE128_Rt_LSE128_Rt2_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDCLRPA_LSE128_Rt_LSE128_Rt2_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldclrpa",
        aliases: &[],
        opcode: 0x19a01000,
        mask: 0xffe0fc00,
        class: InsnClass::LSE128_ATOMIC,
        feature_set: InsnFeatureSet::LSE128,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::LSE128_Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::LSE128_Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::LSE128_Rt2,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::LSE128_Rt2,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE128_ATOMIC(LSE128_ATOMIC::LDCLRPA_LSE128_Rt_LSE128_Rt2_ADDR_SIMPLE(
            LDCLRPA_LSE128_Rt_LSE128_Rt2_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for LDCLRPA_LSE128_Rt_LSE128_Rt2_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDCLRPAL_LSE128_Rt_LSE128_Rt2_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldclrpal",
        aliases: &[],
        opcode: 0x19e01000,
        mask: 0xffe0fc00,
        class: InsnClass::LSE128_ATOMIC,
        feature_set: InsnFeatureSet::LSE128,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::LSE128_Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::LSE128_Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::LSE128_Rt2,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::LSE128_Rt2,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE128_ATOMIC(LSE128_ATOMIC::LDCLRPAL_LSE128_Rt_LSE128_Rt2_ADDR_SIMPLE(
            LDCLRPAL_LSE128_Rt_LSE128_Rt2_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for LDCLRPAL_LSE128_Rt_LSE128_Rt2_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDCLRPL_LSE128_Rt_LSE128_Rt2_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldclrpl",
        aliases: &[],
        opcode: 0x19601000,
        mask: 0xffe0fc00,
        class: InsnClass::LSE128_ATOMIC,
        feature_set: InsnFeatureSet::LSE128,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::LSE128_Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::LSE128_Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::LSE128_Rt2,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::LSE128_Rt2,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE128_ATOMIC(LSE128_ATOMIC::LDCLRPL_LSE128_Rt_LSE128_Rt2_ADDR_SIMPLE(
            LDCLRPL_LSE128_Rt_LSE128_Rt2_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for LDCLRPL_LSE128_Rt_LSE128_Rt2_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDEOR_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldeor",
        aliases: &[],
        opcode: 0xb8202000,
        mask: 0xbfe0fc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LSE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_ALIAS.bits() | InsnFlags::HAS_LSE_SZ_FIELD.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::LDEOR_Rs_Rt_ADDR_SIMPLE(
            LDEOR_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for LDEOR_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDEORA_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldeora",
        aliases: &[],
        opcode: 0xb8a02000,
        mask: 0xbfe0fc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LSE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_LSE_SZ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::LDEORA_Rs_Rt_ADDR_SIMPLE(
            LDEORA_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for LDEORA_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDEORAB_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldeorab",
        aliases: &[],
        opcode: 0x38a02000,
        mask: 0xffe0fc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LSE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::LDEORAB_Rs_Rt_ADDR_SIMPLE(
            LDEORAB_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for LDEORAB_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDEORAH_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldeorah",
        aliases: &[],
        opcode: 0x78a02000,
        mask: 0xffe0fc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LSE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::LDEORAH_Rs_Rt_ADDR_SIMPLE(
            LDEORAH_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for LDEORAH_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDEORAL_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldeoral",
        aliases: &[],
        opcode: 0xb8e02000,
        mask: 0xbfe0fc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LSE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_LSE_SZ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::LDEORAL_Rs_Rt_ADDR_SIMPLE(
            LDEORAL_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for LDEORAL_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDEORALB_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldeoralb",
        aliases: &[],
        opcode: 0x38e02000,
        mask: 0xffe0fc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LSE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::LDEORALB_Rs_Rt_ADDR_SIMPLE(
            LDEORALB_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for LDEORALB_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDEORALH_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldeoralh",
        aliases: &[],
        opcode: 0x78e02000,
        mask: 0xffe0fc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LSE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::LDEORALH_Rs_Rt_ADDR_SIMPLE(
            LDEORALH_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for LDEORALH_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDEORB_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldeorb",
        aliases: &[],
        opcode: 0x38202000,
        mask: 0xffe0fc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LSE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ALIAS.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::LDEORB_Rs_Rt_ADDR_SIMPLE(
            LDEORB_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for LDEORB_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDEORH_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldeorh",
        aliases: &[],
        opcode: 0x78202000,
        mask: 0xffe0fc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LSE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ALIAS.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::LDEORH_Rs_Rt_ADDR_SIMPLE(
            LDEORH_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for LDEORH_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDEORL_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldeorl",
        aliases: &[],
        opcode: 0xb8602000,
        mask: 0xbfe0fc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LSE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_ALIAS.bits() | InsnFlags::HAS_LSE_SZ_FIELD.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::LDEORL_Rs_Rt_ADDR_SIMPLE(
            LDEORL_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for LDEORL_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDEORLB_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldeorlb",
        aliases: &[],
        opcode: 0x38602000,
        mask: 0xffe0fc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LSE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ALIAS.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::LDEORLB_Rs_Rt_ADDR_SIMPLE(
            LDEORLB_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for LDEORLB_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDEORLH_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldeorlh",
        aliases: &[],
        opcode: 0x78602000,
        mask: 0xffe0fc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LSE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ALIAS.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::LDEORLH_Rs_Rt_ADDR_SIMPLE(
            LDEORLH_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for LDEORLH_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDFF1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldff1b",
        aliases: &[],
        opcode: 0x84006000,
        mask: 0xffa0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RZ_XTW_22,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zm_16,
                        lsb: 16,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_xs_22,
                        lsb: 22,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LDFF1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22(
            LDFF1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22::from(bits),
        ))
    }
}
impl InsnOpcode for LDFF1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDFF1B_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW_22_S_D {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldff1b",
        aliases: &[],
        opcode: 0xc4006000,
        mask: 0xffa0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RZ_XTW_22,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zm_16,
                        lsb: 16,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_xs_22,
                        lsb: 22,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(
            SVE_MISC::LDFF1B_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW_22_S_D(
                LDFF1B_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW_22_S_D::from(bits),
            ),
        )
    }
}
impl InsnOpcode for LDFF1B_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW_22_S_D {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDFF1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldff1b",
        aliases: &[],
        opcode: 0x8420e000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_ZI_U5,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LDFF1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5(
            LDFF1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5::from(bits),
        ))
    }
}
impl InsnOpcode for LDFF1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDFF1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldff1b",
        aliases: &[],
        opcode: 0xc440e000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RZ,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zm_16,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LDFF1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ(
            LDFF1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ::from(bits),
        ))
    }
}
impl InsnOpcode for LDFF1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDFF1B_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_ZI_U5_S_D {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldff1b",
        aliases: &[],
        opcode: 0xc420e000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_ZI_U5,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(
            SVE_MISC::LDFF1B_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_ZI_U5_S_D(
                LDFF1B_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_ZI_U5_S_D::from(bits),
            ),
        )
    }
}
impl InsnOpcode for LDFF1B_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_ZI_U5_S_D {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDFF1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RR {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldff1b",
        aliases: &[],
        opcode: 0xa4006000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RR,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LDFF1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RR(
            LDFF1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RR::from(bits),
        ))
    }
}
impl InsnOpcode for LDFF1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RR {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDFF1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_R {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldff1b",
        aliases: &[],
        opcode: 0xa4006000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_R,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LDFF1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_R(
            LDFF1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_R::from(bits),
        ))
    }
}
impl InsnOpcode for LDFF1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_R {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDFF1B_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RR {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldff1b",
        aliases: &[],
        opcode: 0xa4406000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RR,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LDFF1B_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RR(
            LDFF1B_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RR::from(bits),
        ))
    }
}
impl InsnOpcode for LDFF1B_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RR {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDFF1B_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_R {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldff1b",
        aliases: &[],
        opcode: 0xa4406000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_R,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LDFF1B_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_R(
            LDFF1B_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_R::from(bits),
        ))
    }
}
impl InsnOpcode for LDFF1B_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_R {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDFF1B_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RR {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldff1b",
        aliases: &[],
        opcode: 0xa4206000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RR,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LDFF1B_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RR(
            LDFF1B_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RR::from(bits),
        ))
    }
}
impl InsnOpcode for LDFF1B_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RR {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDFF1B_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_R {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldff1b",
        aliases: &[],
        opcode: 0xa4206000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_R,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LDFF1B_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_R(
            LDFF1B_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_R::from(bits),
        ))
    }
}
impl InsnOpcode for LDFF1B_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_R {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDFF1B_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RR {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldff1b",
        aliases: &[],
        opcode: 0xa4606000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RR,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LDFF1B_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RR(
            LDFF1B_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RR::from(bits),
        ))
    }
}
impl InsnOpcode for LDFF1B_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RR {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDFF1B_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_R {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldff1b",
        aliases: &[],
        opcode: 0xa4606000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_R,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LDFF1B_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_R(
            LDFF1B_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_R::from(bits),
        ))
    }
}
impl InsnOpcode for LDFF1B_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_R {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDFF1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldff1d",
        aliases: &[],
        opcode: 0xc5806000,
        mask: 0xffa0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RZ_XTW_22,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zm_16,
                        lsb: 16,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_xs_22,
                        lsb: 22,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LDFF1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22(
            LDFF1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22::from(bits),
        ))
    }
}
impl InsnOpcode for LDFF1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDFF1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW3_22 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldff1d",
        aliases: &[],
        opcode: 0xc5a06000,
        mask: 0xffa0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RZ_XTW3_22,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zm_16,
                        lsb: 16,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_xs_22,
                        lsb: 22,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LDFF1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW3_22(
            LDFF1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW3_22::from(bits),
        ))
    }
}
impl InsnOpcode for LDFF1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW3_22 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDFF1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldff1d",
        aliases: &[],
        opcode: 0xc5c0e000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RZ,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zm_16,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LDFF1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ(
            LDFF1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ::from(bits),
        ))
    }
}
impl InsnOpcode for LDFF1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDFF1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x8 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldff1d",
        aliases: &[],
        opcode: 0xc5a0e000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_ZI_U5x8,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LDFF1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x8(
            LDFF1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x8::from(bits),
        ))
    }
}
impl InsnOpcode for LDFF1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x8 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDFF1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL3 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldff1d",
        aliases: &[],
        opcode: 0xc5e0e000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RZ_LSL3,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zm_16,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LDFF1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL3(
            LDFF1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL3::from(bits),
        ))
    }
}
impl InsnOpcode for LDFF1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL3 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDFF1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RR_LSL3 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldff1d",
        aliases: &[],
        opcode: 0xa5e06000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RR_LSL3,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LDFF1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RR_LSL3(
            LDFF1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RR_LSL3::from(bits),
        ))
    }
}
impl InsnOpcode for LDFF1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RR_LSL3 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDFF1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_R {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldff1d",
        aliases: &[],
        opcode: 0xa5e06000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_R,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LDFF1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_R(
            LDFF1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_R::from(bits),
        ))
    }
}
impl InsnOpcode for LDFF1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_R {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDFF1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldff1h",
        aliases: &[],
        opcode: 0x84806000,
        mask: 0xffa0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RZ_XTW_22,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zm_16,
                        lsb: 16,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_xs_22,
                        lsb: 22,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LDFF1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22(
            LDFF1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22::from(bits),
        ))
    }
}
impl InsnOpcode for LDFF1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDFF1H_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW_22_S_D {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldff1h",
        aliases: &[],
        opcode: 0xc4806000,
        mask: 0xffa0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RZ_XTW_22,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zm_16,
                        lsb: 16,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_xs_22,
                        lsb: 22,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(
            SVE_MISC::LDFF1H_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW_22_S_D(
                LDFF1H_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW_22_S_D::from(bits),
            ),
        )
    }
}
impl InsnOpcode for LDFF1H_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW_22_S_D {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDFF1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW1_22 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldff1h",
        aliases: &[],
        opcode: 0x84a06000,
        mask: 0xffa0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RZ_XTW1_22,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zm_16,
                        lsb: 16,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_xs_22,
                        lsb: 22,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LDFF1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW1_22(
            LDFF1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW1_22::from(bits),
        ))
    }
}
impl InsnOpcode for LDFF1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW1_22 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDFF1H_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW1_22_S_D {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldff1h",
        aliases: &[],
        opcode: 0xc4a06000,
        mask: 0xffa0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RZ_XTW1_22,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zm_16,
                        lsb: 16,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_xs_22,
                        lsb: 22,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(
            SVE_MISC::LDFF1H_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW1_22_S_D(
                LDFF1H_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW1_22_S_D::from(bits),
            ),
        )
    }
}
impl InsnOpcode for LDFF1H_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW1_22_S_D {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDFF1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldff1h",
        aliases: &[],
        opcode: 0x84a0e000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_ZI_U5x2,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LDFF1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x2(
            LDFF1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x2::from(bits),
        ))
    }
}
impl InsnOpcode for LDFF1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDFF1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldff1h",
        aliases: &[],
        opcode: 0xc4c0e000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RZ,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zm_16,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LDFF1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ(
            LDFF1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ::from(bits),
        ))
    }
}
impl InsnOpcode for LDFF1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDFF1H_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_ZI_U5x2_S_D {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldff1h",
        aliases: &[],
        opcode: 0xc4a0e000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_ZI_U5x2,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(
            SVE_MISC::LDFF1H_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_ZI_U5x2_S_D(
                LDFF1H_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_ZI_U5x2_S_D::from(bits),
            ),
        )
    }
}
impl InsnOpcode for LDFF1H_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_ZI_U5x2_S_D {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDFF1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL1 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldff1h",
        aliases: &[],
        opcode: 0xc4e0e000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RZ_LSL1,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zm_16,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LDFF1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL1(
            LDFF1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL1::from(bits),
        ))
    }
}
impl InsnOpcode for LDFF1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL1 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDFF1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RR_LSL1 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldff1h",
        aliases: &[],
        opcode: 0xa4c06000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RR_LSL1,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LDFF1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RR_LSL1(
            LDFF1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RR_LSL1::from(bits),
        ))
    }
}
impl InsnOpcode for LDFF1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RR_LSL1 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDFF1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_R {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldff1h",
        aliases: &[],
        opcode: 0xa4c06000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_R,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LDFF1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_R(
            LDFF1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_R::from(bits),
        ))
    }
}
impl InsnOpcode for LDFF1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_R {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDFF1H_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RR_LSL1 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldff1h",
        aliases: &[],
        opcode: 0xa4a06000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RR_LSL1,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LDFF1H_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RR_LSL1(
            LDFF1H_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RR_LSL1::from(bits),
        ))
    }
}
impl InsnOpcode for LDFF1H_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RR_LSL1 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDFF1H_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_R {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldff1h",
        aliases: &[],
        opcode: 0xa4a06000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_R,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LDFF1H_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_R(
            LDFF1H_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_R::from(bits),
        ))
    }
}
impl InsnOpcode for LDFF1H_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_R {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDFF1H_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RR_LSL1 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldff1h",
        aliases: &[],
        opcode: 0xa4e06000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RR_LSL1,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LDFF1H_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RR_LSL1(
            LDFF1H_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RR_LSL1::from(bits),
        ))
    }
}
impl InsnOpcode for LDFF1H_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RR_LSL1 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDFF1H_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_R {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldff1h",
        aliases: &[],
        opcode: 0xa4e06000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_R,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LDFF1H_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_R(
            LDFF1H_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_R::from(bits),
        ))
    }
}
impl InsnOpcode for LDFF1H_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_R {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDFF1SB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldff1sb",
        aliases: &[],
        opcode: 0x84002000,
        mask: 0xffa0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RZ_XTW_22,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zm_16,
                        lsb: 16,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_xs_22,
                        lsb: 22,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LDFF1SB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22(
            LDFF1SB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22::from(bits),
        ))
    }
}
impl InsnOpcode for LDFF1SB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDFF1SB_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW_22_S_D {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldff1sb",
        aliases: &[],
        opcode: 0xc4002000,
        mask: 0xffa0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RZ_XTW_22,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zm_16,
                        lsb: 16,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_xs_22,
                        lsb: 22,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(
            SVE_MISC::LDFF1SB_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW_22_S_D(
                LDFF1SB_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW_22_S_D::from(bits),
            ),
        )
    }
}
impl InsnOpcode for LDFF1SB_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW_22_S_D {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDFF1SB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldff1sb",
        aliases: &[],
        opcode: 0x8420a000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_ZI_U5,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LDFF1SB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5(
            LDFF1SB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5::from(bits),
        ))
    }
}
impl InsnOpcode for LDFF1SB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDFF1SB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldff1sb",
        aliases: &[],
        opcode: 0xc440a000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RZ,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zm_16,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LDFF1SB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ(
            LDFF1SB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ::from(bits),
        ))
    }
}
impl InsnOpcode for LDFF1SB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDFF1SB_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_ZI_U5_S_D {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldff1sb",
        aliases: &[],
        opcode: 0xc420a000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_ZI_U5,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(
            SVE_MISC::LDFF1SB_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_ZI_U5_S_D(
                LDFF1SB_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_ZI_U5_S_D::from(bits),
            ),
        )
    }
}
impl InsnOpcode for LDFF1SB_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_ZI_U5_S_D {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDFF1SB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RR {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldff1sb",
        aliases: &[],
        opcode: 0xa5806000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RR,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LDFF1SB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RR(
            LDFF1SB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RR::from(bits),
        ))
    }
}
impl InsnOpcode for LDFF1SB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RR {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDFF1SB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_R {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldff1sb",
        aliases: &[],
        opcode: 0xa5806000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_R,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LDFF1SB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_R(
            LDFF1SB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_R::from(bits),
        ))
    }
}
impl InsnOpcode for LDFF1SB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_R {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDFF1SB_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RR {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldff1sb",
        aliases: &[],
        opcode: 0xa5c06000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RR,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LDFF1SB_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RR(
            LDFF1SB_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RR::from(bits),
        ))
    }
}
impl InsnOpcode for LDFF1SB_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RR {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDFF1SB_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_R {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldff1sb",
        aliases: &[],
        opcode: 0xa5c06000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_R,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LDFF1SB_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_R(
            LDFF1SB_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_R::from(bits),
        ))
    }
}
impl InsnOpcode for LDFF1SB_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_R {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDFF1SB_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RR {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldff1sb",
        aliases: &[],
        opcode: 0xa5a06000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RR,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LDFF1SB_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RR(
            LDFF1SB_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RR::from(bits),
        ))
    }
}
impl InsnOpcode for LDFF1SB_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RR {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDFF1SB_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_R {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldff1sb",
        aliases: &[],
        opcode: 0xa5a06000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_R,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LDFF1SB_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_R(
            LDFF1SB_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_R::from(bits),
        ))
    }
}
impl InsnOpcode for LDFF1SB_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_R {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDFF1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldff1sh",
        aliases: &[],
        opcode: 0x84802000,
        mask: 0xffa0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RZ_XTW_22,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zm_16,
                        lsb: 16,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_xs_22,
                        lsb: 22,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LDFF1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22(
            LDFF1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22::from(bits),
        ))
    }
}
impl InsnOpcode for LDFF1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDFF1SH_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW_22_S_D {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldff1sh",
        aliases: &[],
        opcode: 0xc4802000,
        mask: 0xffa0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RZ_XTW_22,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zm_16,
                        lsb: 16,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_xs_22,
                        lsb: 22,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(
            SVE_MISC::LDFF1SH_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW_22_S_D(
                LDFF1SH_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW_22_S_D::from(bits),
            ),
        )
    }
}
impl InsnOpcode for LDFF1SH_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW_22_S_D {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDFF1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW1_22 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldff1sh",
        aliases: &[],
        opcode: 0x84a02000,
        mask: 0xffa0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RZ_XTW1_22,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zm_16,
                        lsb: 16,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_xs_22,
                        lsb: 22,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LDFF1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW1_22(
            LDFF1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW1_22::from(bits),
        ))
    }
}
impl InsnOpcode for LDFF1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW1_22 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDFF1SH_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW1_22_S_D {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldff1sh",
        aliases: &[],
        opcode: 0xc4a02000,
        mask: 0xffa0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RZ_XTW1_22,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zm_16,
                        lsb: 16,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_xs_22,
                        lsb: 22,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(
            SVE_MISC::LDFF1SH_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW1_22_S_D(
                LDFF1SH_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW1_22_S_D::from(bits),
            ),
        )
    }
}
impl InsnOpcode for LDFF1SH_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW1_22_S_D {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDFF1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldff1sh",
        aliases: &[],
        opcode: 0x84a0a000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_ZI_U5x2,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LDFF1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x2(
            LDFF1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x2::from(bits),
        ))
    }
}
impl InsnOpcode for LDFF1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDFF1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldff1sh",
        aliases: &[],
        opcode: 0xc4c0a000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RZ,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zm_16,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LDFF1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ(
            LDFF1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ::from(bits),
        ))
    }
}
impl InsnOpcode for LDFF1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDFF1SH_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_ZI_U5x2_S_D {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldff1sh",
        aliases: &[],
        opcode: 0xc4a0a000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_ZI_U5x2,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(
            SVE_MISC::LDFF1SH_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_ZI_U5x2_S_D(
                LDFF1SH_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_ZI_U5x2_S_D::from(bits),
            ),
        )
    }
}
impl InsnOpcode for LDFF1SH_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_ZI_U5x2_S_D {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDFF1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL1 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldff1sh",
        aliases: &[],
        opcode: 0xc4e0a000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RZ_LSL1,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zm_16,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LDFF1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL1(
            LDFF1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL1::from(bits),
        ))
    }
}
impl InsnOpcode for LDFF1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL1 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDFF1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RR_LSL1 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldff1sh",
        aliases: &[],
        opcode: 0xa5006000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RR_LSL1,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LDFF1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RR_LSL1(
            LDFF1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RR_LSL1::from(bits),
        ))
    }
}
impl InsnOpcode for LDFF1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RR_LSL1 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDFF1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_R {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldff1sh",
        aliases: &[],
        opcode: 0xa5006000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_R,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LDFF1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_R(
            LDFF1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_R::from(bits),
        ))
    }
}
impl InsnOpcode for LDFF1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_R {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDFF1SH_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RR_LSL1 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldff1sh",
        aliases: &[],
        opcode: 0xa5206000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RR_LSL1,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LDFF1SH_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RR_LSL1(
            LDFF1SH_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RR_LSL1::from(bits),
        ))
    }
}
impl InsnOpcode for LDFF1SH_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RR_LSL1 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDFF1SH_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_R {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldff1sh",
        aliases: &[],
        opcode: 0xa5206000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_R,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LDFF1SH_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_R(
            LDFF1SH_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_R::from(bits),
        ))
    }
}
impl InsnOpcode for LDFF1SH_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_R {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDFF1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RR_LSL2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldff1sw",
        aliases: &[],
        opcode: 0xa4806000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RR_LSL2,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LDFF1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RR_LSL2(
            LDFF1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RR_LSL2::from(bits),
        ))
    }
}
impl InsnOpcode for LDFF1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RR_LSL2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDFF1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_R {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldff1sw",
        aliases: &[],
        opcode: 0xa4806000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_R,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LDFF1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_R(
            LDFF1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_R::from(bits),
        ))
    }
}
impl InsnOpcode for LDFF1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_R {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDFF1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldff1sw",
        aliases: &[],
        opcode: 0xc5002000,
        mask: 0xffa0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RZ_XTW_22,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zm_16,
                        lsb: 16,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_xs_22,
                        lsb: 22,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LDFF1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22(
            LDFF1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22::from(bits),
        ))
    }
}
impl InsnOpcode for LDFF1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDFF1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW2_22 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldff1sw",
        aliases: &[],
        opcode: 0xc5202000,
        mask: 0xffa0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RZ_XTW2_22,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zm_16,
                        lsb: 16,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_xs_22,
                        lsb: 22,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LDFF1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW2_22(
            LDFF1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW2_22::from(bits),
        ))
    }
}
impl InsnOpcode for LDFF1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW2_22 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDFF1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldff1sw",
        aliases: &[],
        opcode: 0xc540a000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RZ,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zm_16,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LDFF1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ(
            LDFF1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ::from(bits),
        ))
    }
}
impl InsnOpcode for LDFF1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDFF1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x4 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldff1sw",
        aliases: &[],
        opcode: 0xc520a000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_ZI_U5x4,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LDFF1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x4(
            LDFF1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x4::from(bits),
        ))
    }
}
impl InsnOpcode for LDFF1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x4 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDFF1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldff1sw",
        aliases: &[],
        opcode: 0xc560a000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RZ_LSL2,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zm_16,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LDFF1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL2(
            LDFF1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL2::from(bits),
        ))
    }
}
impl InsnOpcode for LDFF1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDFF1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldff1w",
        aliases: &[],
        opcode: 0x85006000,
        mask: 0xffa0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RZ_XTW_22,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zm_16,
                        lsb: 16,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_xs_22,
                        lsb: 22,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LDFF1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22(
            LDFF1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22::from(bits),
        ))
    }
}
impl InsnOpcode for LDFF1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDFF1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW2_22 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldff1w",
        aliases: &[],
        opcode: 0x85206000,
        mask: 0xffa0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RZ_XTW2_22,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zm_16,
                        lsb: 16,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_xs_22,
                        lsb: 22,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LDFF1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW2_22(
            LDFF1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW2_22::from(bits),
        ))
    }
}
impl InsnOpcode for LDFF1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW2_22 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDFF1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x4 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldff1w",
        aliases: &[],
        opcode: 0x8520e000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_ZI_U5x4,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LDFF1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x4(
            LDFF1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x4::from(bits),
        ))
    }
}
impl InsnOpcode for LDFF1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x4 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDFF1W_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW_22_S_D {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldff1w",
        aliases: &[],
        opcode: 0xc5006000,
        mask: 0xffa0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RZ_XTW_22,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zm_16,
                        lsb: 16,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_xs_22,
                        lsb: 22,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(
            SVE_MISC::LDFF1W_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW_22_S_D(
                LDFF1W_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW_22_S_D::from(bits),
            ),
        )
    }
}
impl InsnOpcode for LDFF1W_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW_22_S_D {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDFF1W_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW2_22_S_D {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldff1w",
        aliases: &[],
        opcode: 0xc5206000,
        mask: 0xffa0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RZ_XTW2_22,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zm_16,
                        lsb: 16,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_xs_22,
                        lsb: 22,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(
            SVE_MISC::LDFF1W_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW2_22_S_D(
                LDFF1W_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW2_22_S_D::from(bits),
            ),
        )
    }
}
impl InsnOpcode for LDFF1W_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW2_22_S_D {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDFF1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldff1w",
        aliases: &[],
        opcode: 0xc540e000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RZ,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zm_16,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LDFF1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ(
            LDFF1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ::from(bits),
        ))
    }
}
impl InsnOpcode for LDFF1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDFF1W_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_ZI_U5x4_S_D {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldff1w",
        aliases: &[],
        opcode: 0xc520e000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_ZI_U5x4,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(
            SVE_MISC::LDFF1W_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_ZI_U5x4_S_D(
                LDFF1W_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_ZI_U5x4_S_D::from(bits),
            ),
        )
    }
}
impl InsnOpcode for LDFF1W_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_ZI_U5x4_S_D {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDFF1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldff1w",
        aliases: &[],
        opcode: 0xc560e000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RZ_LSL2,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zm_16,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LDFF1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL2(
            LDFF1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL2::from(bits),
        ))
    }
}
impl InsnOpcode for LDFF1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDFF1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RR_LSL2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldff1w",
        aliases: &[],
        opcode: 0xa5406000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RR_LSL2,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LDFF1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RR_LSL2(
            LDFF1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RR_LSL2::from(bits),
        ))
    }
}
impl InsnOpcode for LDFF1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RR_LSL2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDFF1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_R {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldff1w",
        aliases: &[],
        opcode: 0xa5406000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_R,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LDFF1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_R(
            LDFF1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_R::from(bits),
        ))
    }
}
impl InsnOpcode for LDFF1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_R {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDFF1W_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RR_LSL2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldff1w",
        aliases: &[],
        opcode: 0xa5606000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RR_LSL2,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LDFF1W_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RR_LSL2(
            LDFF1W_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RR_LSL2::from(bits),
        ))
    }
}
impl InsnOpcode for LDFF1W_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RR_LSL2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDFF1W_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_R {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldff1w",
        aliases: &[],
        opcode: 0xa5606000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_R,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LDFF1W_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_R(
            LDFF1W_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_R::from(bits),
        ))
    }
}
impl InsnOpcode for LDFF1W_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_R {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDG_Rt_ADDR_SIMM13 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldg",
        aliases: &[],
        opcode: 0xd9600000,
        mask: 0xffe00c00,
        class: InsnClass::LDST_UNSCALED,
        feature_set: InsnFeatureSet::MEMTAG,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMM13,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::imm_tag],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::imm9,
                        lsb: 12,
                        width: 9,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::index,
                        lsb: 11,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDST_UNSCALED(LDST_UNSCALED::LDG_Rt_ADDR_SIMM13(LDG_Rt_ADDR_SIMM13::from(
            bits,
        )))
    }
}
impl InsnOpcode for LDG_Rt_ADDR_SIMM13 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDGM_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldgm",
        aliases: &[],
        opcode: 0xd9e00000,
        mask: 0xfffffc00,
        class: InsnClass::LDSTEXCL,
        feature_set: InsnFeatureSet::MEMTAG,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDSTEXCL(LDSTEXCL::LDGM_Rt_ADDR_SIMPLE(LDGM_Rt_ADDR_SIMPLE::from(
            bits,
        )))
    }
}
impl InsnOpcode for LDGM_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDIAPP_Rt_Rs_RCPC3_ADDR_OPT_POSTIND {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldiapp",
        aliases: &[],
        opcode: 0x19400800,
        mask: 0x3fe0ec00,
        class: InsnClass::RCPC3,
        feature_set: InsnFeatureSet::RCPC3,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::RCPC3_ADDR_OPT_POSTIND,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::opc2,
                    lsb: 12,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_RCPC3_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::RCPC3(RCPC3::LDIAPP_Rt_Rs_RCPC3_ADDR_OPT_POSTIND(
            LDIAPP_Rt_Rs_RCPC3_ADDR_OPT_POSTIND::from(bits),
        ))
    }
}
impl InsnOpcode for LDIAPP_Rt_Rs_RCPC3_ADDR_OPT_POSTIND {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDLAR_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldlar",
        aliases: &[],
        opcode: 0x88df7c00,
        mask: 0xbffffc00,
        class: InsnClass::LDSTEXCL,
        feature_set: InsnFeatureSet::LOR,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMV_GPRSIZE_IN_Q.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDSTEXCL(LDSTEXCL::LDLAR_Rt_ADDR_SIMPLE(LDLAR_Rt_ADDR_SIMPLE::from(
            bits,
        )))
    }
}
impl InsnOpcode for LDLAR_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDLARB_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldlarb",
        aliases: &[],
        opcode: 0x8df7c00,
        mask: 0xfffffc00,
        class: InsnClass::LDSTEXCL,
        feature_set: InsnFeatureSet::LOR,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDSTEXCL(LDSTEXCL::LDLARB_Rt_ADDR_SIMPLE(
            LDLARB_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for LDLARB_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDLARH_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldlarh",
        aliases: &[],
        opcode: 0x48df7c00,
        mask: 0xfffffc00,
        class: InsnClass::LDSTEXCL,
        feature_set: InsnFeatureSet::LOR,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDSTEXCL(LDSTEXCL::LDLARH_Rt_ADDR_SIMPLE(
            LDLARH_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for LDLARH_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDNF1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldnf1b",
        aliases: &[],
        opcode: 0xa410a000,
        mask: 0xfff0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LDNF1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL(
            LDNF1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL::from(bits),
        ))
    }
}
impl InsnOpcode for LDNF1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDNF1B_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldnf1b",
        aliases: &[],
        opcode: 0xa450a000,
        mask: 0xfff0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LDNF1B_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL(
            LDNF1B_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL::from(bits),
        ))
    }
}
impl InsnOpcode for LDNF1B_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDNF1B_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldnf1b",
        aliases: &[],
        opcode: 0xa430a000,
        mask: 0xfff0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LDNF1B_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL(
            LDNF1B_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL::from(bits),
        ))
    }
}
impl InsnOpcode for LDNF1B_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDNF1B_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldnf1b",
        aliases: &[],
        opcode: 0xa470a000,
        mask: 0xfff0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LDNF1B_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL(
            LDNF1B_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL::from(bits),
        ))
    }
}
impl InsnOpcode for LDNF1B_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDNF1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldnf1d",
        aliases: &[],
        opcode: 0xa5f0a000,
        mask: 0xfff0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LDNF1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL(
            LDNF1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL::from(bits),
        ))
    }
}
impl InsnOpcode for LDNF1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDNF1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldnf1h",
        aliases: &[],
        opcode: 0xa4d0a000,
        mask: 0xfff0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LDNF1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL(
            LDNF1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL::from(bits),
        ))
    }
}
impl InsnOpcode for LDNF1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDNF1H_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldnf1h",
        aliases: &[],
        opcode: 0xa4b0a000,
        mask: 0xfff0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LDNF1H_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL(
            LDNF1H_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL::from(bits),
        ))
    }
}
impl InsnOpcode for LDNF1H_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDNF1H_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldnf1h",
        aliases: &[],
        opcode: 0xa4f0a000,
        mask: 0xfff0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LDNF1H_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL(
            LDNF1H_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL::from(bits),
        ))
    }
}
impl InsnOpcode for LDNF1H_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDNF1SB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldnf1sb",
        aliases: &[],
        opcode: 0xa590a000,
        mask: 0xfff0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LDNF1SB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL(
            LDNF1SB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL::from(bits),
        ))
    }
}
impl InsnOpcode for LDNF1SB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDNF1SB_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldnf1sb",
        aliases: &[],
        opcode: 0xa5d0a000,
        mask: 0xfff0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(
            SVE_MISC::LDNF1SB_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL(
                LDNF1SB_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL::from(bits),
            ),
        )
    }
}
impl InsnOpcode for LDNF1SB_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDNF1SB_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldnf1sb",
        aliases: &[],
        opcode: 0xa5b0a000,
        mask: 0xfff0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(
            SVE_MISC::LDNF1SB_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL(
                LDNF1SB_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL::from(bits),
            ),
        )
    }
}
impl InsnOpcode for LDNF1SB_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDNF1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldnf1sh",
        aliases: &[],
        opcode: 0xa510a000,
        mask: 0xfff0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LDNF1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL(
            LDNF1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL::from(bits),
        ))
    }
}
impl InsnOpcode for LDNF1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDNF1SH_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldnf1sh",
        aliases: &[],
        opcode: 0xa530a000,
        mask: 0xfff0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(
            SVE_MISC::LDNF1SH_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL(
                LDNF1SH_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL::from(bits),
            ),
        )
    }
}
impl InsnOpcode for LDNF1SH_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDNF1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldnf1sw",
        aliases: &[],
        opcode: 0xa490a000,
        mask: 0xfff0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LDNF1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL(
            LDNF1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL::from(bits),
        ))
    }
}
impl InsnOpcode for LDNF1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDNF1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldnf1w",
        aliases: &[],
        opcode: 0xa550a000,
        mask: 0xfff0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LDNF1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL(
            LDNF1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL::from(bits),
        ))
    }
}
impl InsnOpcode for LDNF1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDNF1W_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldnf1w",
        aliases: &[],
        opcode: 0xa570a000,
        mask: 0xfff0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LDNF1W_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL(
            LDNF1W_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL::from(bits),
        ))
    }
}
impl InsnOpcode for LDNF1W_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDNP_Rt_Rt2_ADDR_SIMM7 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldnp",
        aliases: &[],
        opcode: 0x28400000,
        mask: 0x7fc00000,
        class: InsnClass::LDSTNAPAIR_OFFS,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt2,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt2,
                    lsb: 10,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMM7,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::imm7,
                        lsb: 15,
                        width: 7,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::index2,
                        lsb: 24,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SF_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDSTNAPAIR_OFFS(LDSTNAPAIR_OFFS::LDNP_Rt_Rt2_ADDR_SIMM7(
            LDNP_Rt_Rt2_ADDR_SIMM7::from(bits),
        ))
    }
}
impl InsnOpcode for LDNP_Rt_Rt2_ADDR_SIMM7 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDNP_Ft_Ft2_ADDR_SIMM7 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldnp",
        aliases: &[],
        opcode: 0x2c400000,
        mask: 0x3fc00000,
        class: InsnClass::LDSTNAPAIR_OFFS,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Ft,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Ft2,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt2,
                    lsb: 10,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMM7,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::imm7,
                        lsb: 15,
                        width: 7,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::index2,
                        lsb: 24,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDSTNAPAIR_OFFS(LDSTNAPAIR_OFFS::LDNP_Ft_Ft2_ADDR_SIMM7(
            LDNP_Ft_Ft2_ADDR_SIMM7::from(bits),
        ))
    }
}
impl InsnOpcode for LDNP_Ft_Ft2_ADDR_SIMM7 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDNT1B_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldnt1b",
        aliases: &[],
        opcode: 0xa0000001,
        mask: 0xffe0e001,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn2,
                    lsb: 1,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RR,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LDNT1B_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR(
            LDNT1B_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR::from(bits),
        ))
    }
}
impl InsnOpcode for LDNT1B_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDNT1B_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldnt1b",
        aliases: &[],
        opcode: 0xa0008001,
        mask: 0xffe0e003,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn4,
                    lsb: 2,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RR,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LDNT1B_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR(
            LDNT1B_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR::from(bits),
        ))
    }
}
impl InsnOpcode for LDNT1B_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDNT1B_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldnt1b",
        aliases: &[],
        opcode: 0xa0400001,
        mask: 0xfff0e001,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn2,
                    lsb: 1,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4x2xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LDNT1B_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL(
            LDNT1B_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL::from(bits),
        ))
    }
}
impl InsnOpcode for LDNT1B_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDNT1B_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldnt1b",
        aliases: &[],
        opcode: 0xa0408001,
        mask: 0xfff0e003,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn4,
                    lsb: 2,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4x4xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LDNT1B_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL(
            LDNT1B_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL::from(bits),
        ))
    }
}
impl InsnOpcode for LDNT1B_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDNT1B_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldnt1b",
        aliases: &[],
        opcode: 0xa1000008,
        mask: 0xffe0e008,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Ztx2_STRIDED,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_ZtT,
                        lsb: 4,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zt3,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RR,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LDNT1B_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR(
            LDNT1B_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR::from(bits),
        ))
    }
}
impl InsnOpcode for LDNT1B_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDNT1B_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldnt1b",
        aliases: &[],
        opcode: 0xa1008008,
        mask: 0xffe0e00c,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Ztx4_STRIDED,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_ZtT,
                        lsb: 4,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zt2,
                        lsb: 0,
                        width: 2,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RR,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LDNT1B_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR(
            LDNT1B_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR::from(bits),
        ))
    }
}
impl InsnOpcode for LDNT1B_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDNT1B_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldnt1b",
        aliases: &[],
        opcode: 0xa1400008,
        mask: 0xfff0e008,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Ztx2_STRIDED,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_ZtT,
                        lsb: 4,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zt3,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4x2xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(
            SVE_MISC::LDNT1B_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL(
                LDNT1B_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL::from(bits),
            ),
        )
    }
}
impl InsnOpcode for LDNT1B_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDNT1B_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldnt1b",
        aliases: &[],
        opcode: 0xa1408008,
        mask: 0xfff0e00c,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Ztx4_STRIDED,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_ZtT,
                        lsb: 4,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zt2,
                        lsb: 0,
                        width: 2,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4x4xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(
            SVE_MISC::LDNT1B_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL(
                LDNT1B_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL::from(bits),
            ),
        )
    }
}
impl InsnOpcode for LDNT1B_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDNT1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldnt1b",
        aliases: &[],
        opcode: 0xc400c000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_ZX,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LDNT1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZX(
            LDNT1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZX::from(bits),
        ))
    }
}
impl InsnOpcode for LDNT1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDNT1B_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_ZX_S_S {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldnt1b",
        aliases: &[],
        opcode: 0x8400a000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_ZX,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LDNT1B_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_ZX_S_S(
            LDNT1B_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_ZX_S_S::from(bits),
        ))
    }
}
impl InsnOpcode for LDNT1B_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_ZX_S_S {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDNT1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldnt1b",
        aliases: &[],
        opcode: 0xa400c000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RX,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LDNT1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX(
            LDNT1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX::from(bits),
        ))
    }
}
impl InsnOpcode for LDNT1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDNT1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldnt1b",
        aliases: &[],
        opcode: 0xa400e000,
        mask: 0xfff0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LDNT1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL(
            LDNT1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL::from(bits),
        ))
    }
}
impl InsnOpcode for LDNT1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDNT1D_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR_LSL3 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldnt1d",
        aliases: &[],
        opcode: 0xa0006001,
        mask: 0xffe0e001,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn2,
                    lsb: 1,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RR_LSL3,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LDNT1D_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR_LSL3(
            LDNT1D_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR_LSL3::from(bits),
        ))
    }
}
impl InsnOpcode for LDNT1D_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR_LSL3 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDNT1D_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR_LSL3 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldnt1d",
        aliases: &[],
        opcode: 0xa000e001,
        mask: 0xffe0e003,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn4,
                    lsb: 2,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RR_LSL3,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LDNT1D_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR_LSL3(
            LDNT1D_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR_LSL3::from(bits),
        ))
    }
}
impl InsnOpcode for LDNT1D_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR_LSL3 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDNT1D_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldnt1d",
        aliases: &[],
        opcode: 0xa0406001,
        mask: 0xfff0e001,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn2,
                    lsb: 1,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4x2xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LDNT1D_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL(
            LDNT1D_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL::from(bits),
        ))
    }
}
impl InsnOpcode for LDNT1D_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDNT1D_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldnt1d",
        aliases: &[],
        opcode: 0xa040e001,
        mask: 0xfff0e003,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn4,
                    lsb: 2,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4x4xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LDNT1D_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL(
            LDNT1D_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL::from(bits),
        ))
    }
}
impl InsnOpcode for LDNT1D_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDNT1D_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL3 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldnt1d",
        aliases: &[],
        opcode: 0xa1006008,
        mask: 0xffe0e008,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Ztx2_STRIDED,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_ZtT,
                        lsb: 4,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zt3,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RR_LSL3,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LDNT1D_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL3(
            LDNT1D_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL3::from(bits),
        ))
    }
}
impl InsnOpcode for LDNT1D_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL3 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDNT1D_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL3 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldnt1d",
        aliases: &[],
        opcode: 0xa100e008,
        mask: 0xffe0e00c,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Ztx4_STRIDED,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_ZtT,
                        lsb: 4,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zt2,
                        lsb: 0,
                        width: 2,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RR_LSL3,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LDNT1D_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL3(
            LDNT1D_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL3::from(bits),
        ))
    }
}
impl InsnOpcode for LDNT1D_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL3 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDNT1D_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldnt1d",
        aliases: &[],
        opcode: 0xa1406008,
        mask: 0xfff0e008,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Ztx2_STRIDED,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_ZtT,
                        lsb: 4,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zt3,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4x2xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(
            SVE_MISC::LDNT1D_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL(
                LDNT1D_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL::from(bits),
            ),
        )
    }
}
impl InsnOpcode for LDNT1D_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDNT1D_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldnt1d",
        aliases: &[],
        opcode: 0xa140e008,
        mask: 0xfff0e00c,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Ztx4_STRIDED,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_ZtT,
                        lsb: 4,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zt2,
                        lsb: 0,
                        width: 2,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4x4xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(
            SVE_MISC::LDNT1D_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL(
                LDNT1D_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL::from(bits),
            ),
        )
    }
}
impl InsnOpcode for LDNT1D_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDNT1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldnt1d",
        aliases: &[],
        opcode: 0xc580c000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_ZX,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LDNT1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZX(
            LDNT1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZX::from(bits),
        ))
    }
}
impl InsnOpcode for LDNT1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDNT1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL3 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldnt1d",
        aliases: &[],
        opcode: 0xa580c000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RX_LSL3,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LDNT1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL3(
            LDNT1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL3::from(bits),
        ))
    }
}
impl InsnOpcode for LDNT1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL3 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDNT1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldnt1d",
        aliases: &[],
        opcode: 0xa580e000,
        mask: 0xfff0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LDNT1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL(
            LDNT1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL::from(bits),
        ))
    }
}
impl InsnOpcode for LDNT1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDNT1H_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR_LSL1 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldnt1h",
        aliases: &[],
        opcode: 0xa0002001,
        mask: 0xffe0e001,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn2,
                    lsb: 1,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RR_LSL1,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LDNT1H_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR_LSL1(
            LDNT1H_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR_LSL1::from(bits),
        ))
    }
}
impl InsnOpcode for LDNT1H_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR_LSL1 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDNT1H_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR_LSL1 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldnt1h",
        aliases: &[],
        opcode: 0xa000a001,
        mask: 0xffe0e003,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn4,
                    lsb: 2,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RR_LSL1,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LDNT1H_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR_LSL1(
            LDNT1H_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR_LSL1::from(bits),
        ))
    }
}
impl InsnOpcode for LDNT1H_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR_LSL1 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDNT1H_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldnt1h",
        aliases: &[],
        opcode: 0xa0402001,
        mask: 0xfff0e001,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn2,
                    lsb: 1,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4x2xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LDNT1H_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL(
            LDNT1H_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL::from(bits),
        ))
    }
}
impl InsnOpcode for LDNT1H_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDNT1H_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldnt1h",
        aliases: &[],
        opcode: 0xa040a001,
        mask: 0xfff0e003,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn4,
                    lsb: 2,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4x4xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LDNT1H_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL(
            LDNT1H_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL::from(bits),
        ))
    }
}
impl InsnOpcode for LDNT1H_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDNT1H_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL1 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldnt1h",
        aliases: &[],
        opcode: 0xa1002008,
        mask: 0xffe0e008,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Ztx2_STRIDED,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_ZtT,
                        lsb: 4,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zt3,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RR_LSL1,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LDNT1H_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL1(
            LDNT1H_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL1::from(bits),
        ))
    }
}
impl InsnOpcode for LDNT1H_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL1 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDNT1H_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL1 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldnt1h",
        aliases: &[],
        opcode: 0xa100a008,
        mask: 0xffe0e00c,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Ztx4_STRIDED,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_ZtT,
                        lsb: 4,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zt2,
                        lsb: 0,
                        width: 2,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RR_LSL1,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LDNT1H_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL1(
            LDNT1H_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL1::from(bits),
        ))
    }
}
impl InsnOpcode for LDNT1H_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL1 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDNT1H_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldnt1h",
        aliases: &[],
        opcode: 0xa1402008,
        mask: 0xfff0e008,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Ztx2_STRIDED,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_ZtT,
                        lsb: 4,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zt3,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4x2xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(
            SVE_MISC::LDNT1H_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL(
                LDNT1H_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL::from(bits),
            ),
        )
    }
}
impl InsnOpcode for LDNT1H_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDNT1H_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldnt1h",
        aliases: &[],
        opcode: 0xa140a008,
        mask: 0xfff0e00c,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Ztx4_STRIDED,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_ZtT,
                        lsb: 4,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zt2,
                        lsb: 0,
                        width: 2,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4x4xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(
            SVE_MISC::LDNT1H_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL(
                LDNT1H_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL::from(bits),
            ),
        )
    }
}
impl InsnOpcode for LDNT1H_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDNT1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldnt1h",
        aliases: &[],
        opcode: 0xc480c000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_ZX,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LDNT1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZX(
            LDNT1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZX::from(bits),
        ))
    }
}
impl InsnOpcode for LDNT1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDNT1H_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_ZX_S_S {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldnt1h",
        aliases: &[],
        opcode: 0x8480a000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_ZX,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LDNT1H_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_ZX_S_S(
            LDNT1H_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_ZX_S_S::from(bits),
        ))
    }
}
impl InsnOpcode for LDNT1H_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_ZX_S_S {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDNT1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldnt1h",
        aliases: &[],
        opcode: 0xa480c000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RX_LSL1,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LDNT1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1(
            LDNT1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1::from(bits),
        ))
    }
}
impl InsnOpcode for LDNT1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDNT1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldnt1h",
        aliases: &[],
        opcode: 0xa480e000,
        mask: 0xfff0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LDNT1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL(
            LDNT1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL::from(bits),
        ))
    }
}
impl InsnOpcode for LDNT1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDNT1SB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldnt1sb",
        aliases: &[],
        opcode: 0x84008000,
        mask: 0xbfe0e000,
        class: InsnClass::SVE_SIZE_SD2,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z, InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_ZX,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_SD2(SVE_SIZE_SD2::LDNT1SB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZX(
            LDNT1SB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZX::from(bits),
        ))
    }
}
impl InsnOpcode for LDNT1SB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDNT1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldnt1sh",
        aliases: &[],
        opcode: 0x84808000,
        mask: 0xbfe0e000,
        class: InsnClass::SVE_SIZE_SD2,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z, InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_ZX,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_SD2(SVE_SIZE_SD2::LDNT1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZX(
            LDNT1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZX::from(bits),
        ))
    }
}
impl InsnOpcode for LDNT1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDNT1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldnt1sw",
        aliases: &[],
        opcode: 0xc5008000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_ZX,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LDNT1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZX(
            LDNT1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZX::from(bits),
        ))
    }
}
impl InsnOpcode for LDNT1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDNT1W_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR_LSL2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldnt1w",
        aliases: &[],
        opcode: 0xa0004001,
        mask: 0xffe0e001,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn2,
                    lsb: 1,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RR_LSL2,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LDNT1W_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR_LSL2(
            LDNT1W_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR_LSL2::from(bits),
        ))
    }
}
impl InsnOpcode for LDNT1W_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR_LSL2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDNT1W_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR_LSL2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldnt1w",
        aliases: &[],
        opcode: 0xa000c001,
        mask: 0xffe0e003,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn4,
                    lsb: 2,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RR_LSL2,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LDNT1W_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR_LSL2(
            LDNT1W_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR_LSL2::from(bits),
        ))
    }
}
impl InsnOpcode for LDNT1W_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR_LSL2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDNT1W_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldnt1w",
        aliases: &[],
        opcode: 0xa0404001,
        mask: 0xfff0e001,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn2,
                    lsb: 1,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4x2xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LDNT1W_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL(
            LDNT1W_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL::from(bits),
        ))
    }
}
impl InsnOpcode for LDNT1W_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDNT1W_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldnt1w",
        aliases: &[],
        opcode: 0xa040c001,
        mask: 0xfff0e003,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn4,
                    lsb: 2,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4x4xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LDNT1W_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL(
            LDNT1W_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL::from(bits),
        ))
    }
}
impl InsnOpcode for LDNT1W_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDNT1W_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldnt1w",
        aliases: &[],
        opcode: 0xa1004008,
        mask: 0xffe0e008,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Ztx2_STRIDED,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_ZtT,
                        lsb: 4,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zt3,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RR_LSL2,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LDNT1W_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL2(
            LDNT1W_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL2::from(bits),
        ))
    }
}
impl InsnOpcode for LDNT1W_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDNT1W_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldnt1w",
        aliases: &[],
        opcode: 0xa100c008,
        mask: 0xffe0e00c,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Ztx4_STRIDED,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_ZtT,
                        lsb: 4,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zt2,
                        lsb: 0,
                        width: 2,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RR_LSL2,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LDNT1W_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL2(
            LDNT1W_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL2::from(bits),
        ))
    }
}
impl InsnOpcode for LDNT1W_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDNT1W_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldnt1w",
        aliases: &[],
        opcode: 0xa1404008,
        mask: 0xfff0e008,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Ztx2_STRIDED,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_ZtT,
                        lsb: 4,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zt3,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4x2xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(
            SVE_MISC::LDNT1W_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL(
                LDNT1W_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL::from(bits),
            ),
        )
    }
}
impl InsnOpcode for LDNT1W_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDNT1W_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldnt1w",
        aliases: &[],
        opcode: 0xa140c008,
        mask: 0xfff0e00c,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Ztx4_STRIDED,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_ZtT,
                        lsb: 4,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zt2,
                        lsb: 0,
                        width: 2,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4x4xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(
            SVE_MISC::LDNT1W_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL(
                LDNT1W_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL::from(bits),
            ),
        )
    }
}
impl InsnOpcode for LDNT1W_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDNT1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldnt1w",
        aliases: &[],
        opcode: 0x8500a000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_ZX,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LDNT1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZX(
            LDNT1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZX::from(bits),
        ))
    }
}
impl InsnOpcode for LDNT1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDNT1W_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_ZX_S_D {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldnt1w",
        aliases: &[],
        opcode: 0xc500c000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_ZX,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LDNT1W_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_ZX_S_D(
            LDNT1W_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_ZX_S_D::from(bits),
        ))
    }
}
impl InsnOpcode for LDNT1W_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_ZX_S_D {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDNT1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldnt1w",
        aliases: &[],
        opcode: 0xa500c000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RX_LSL2,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LDNT1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2(
            LDNT1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2::from(bits),
        ))
    }
}
impl InsnOpcode for LDNT1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDNT1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldnt1w",
        aliases: &[],
        opcode: 0xa500e000,
        mask: 0xfff0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LDNT1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL(
            LDNT1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL::from(bits),
        ))
    }
}
impl InsnOpcode for LDNT1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDP_Rt_Rt2_ADDR_SIMM7 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldp",
        aliases: &[],
        opcode: 0x29400000,
        mask: 0x7fc00000,
        class: InsnClass::LDSTPAIR_OFF,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt2,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt2,
                    lsb: 10,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMM7,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::imm7,
                        lsb: 15,
                        width: 7,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::index2,
                        lsb: 24,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SF_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDSTPAIR_OFF(LDSTPAIR_OFF::LDP_Rt_Rt2_ADDR_SIMM7(
            LDP_Rt_Rt2_ADDR_SIMM7::from(bits),
        ))
    }
}
impl InsnOpcode for LDP_Rt_Rt2_ADDR_SIMM7 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDP_Rt_W_Rt2_W_ADDR_SIMM7_S_S {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldp",
        aliases: &[],
        opcode: 0x28c00000,
        mask: 0x7ec00000,
        class: InsnClass::LDSTPAIR_INDEXED,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt2,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt2,
                    lsb: 10,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMM7,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::imm7,
                        lsb: 15,
                        width: 7,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::index2,
                        lsb: 24,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SF_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDSTPAIR_INDEXED(LDSTPAIR_INDEXED::LDP_Rt_W_Rt2_W_ADDR_SIMM7_S_S(
            LDP_Rt_W_Rt2_W_ADDR_SIMM7_S_S::from(bits),
        ))
    }
}
impl InsnOpcode for LDP_Rt_W_Rt2_W_ADDR_SIMM7_S_S {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDP_Ft_Ft2_ADDR_SIMM7 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldp",
        aliases: &[],
        opcode: 0x2d400000,
        mask: 0x3fc00000,
        class: InsnClass::LDSTPAIR_OFF,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Ft,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Ft2,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt2,
                    lsb: 10,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMM7,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::imm7,
                        lsb: 15,
                        width: 7,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::index2,
                        lsb: 24,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDSTPAIR_OFF(LDSTPAIR_OFF::LDP_Ft_Ft2_ADDR_SIMM7(
            LDP_Ft_Ft2_ADDR_SIMM7::from(bits),
        ))
    }
}
impl InsnOpcode for LDP_Ft_Ft2_ADDR_SIMM7 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDP_Ft_S_S_Ft2_S_S_ADDR_SIMM7_S_S {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldp",
        aliases: &[],
        opcode: 0x2cc00000,
        mask: 0x3ec00000,
        class: InsnClass::LDSTPAIR_INDEXED,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Ft,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Ft2,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt2,
                    lsb: 10,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMM7,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::imm7,
                        lsb: 15,
                        width: 7,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::index2,
                        lsb: 24,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDSTPAIR_INDEXED(LDSTPAIR_INDEXED::LDP_Ft_S_S_Ft2_S_S_ADDR_SIMM7_S_S(
            LDP_Ft_S_S_Ft2_S_S_ADDR_SIMM7_S_S::from(bits),
        ))
    }
}
impl InsnOpcode for LDP_Ft_S_S_Ft2_S_S_ADDR_SIMM7_S_S {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDPSW_Rt_Rt2_ADDR_SIMM7 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldpsw",
        aliases: &[],
        opcode: 0x69400000,
        mask: 0xffc00000,
        class: InsnClass::LDSTPAIR_OFF,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt2,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt2,
                    lsb: 10,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMM7,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::imm7,
                        lsb: 15,
                        width: 7,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::index2,
                        lsb: 24,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDSTPAIR_OFF(LDSTPAIR_OFF::LDPSW_Rt_Rt2_ADDR_SIMM7(
            LDPSW_Rt_Rt2_ADDR_SIMM7::from(bits),
        ))
    }
}
impl InsnOpcode for LDPSW_Rt_Rt2_ADDR_SIMM7 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDPSW_Rt_X_Rt2_X_ADDR_SIMM7_S_S {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldpsw",
        aliases: &[],
        opcode: 0x68c00000,
        mask: 0xfec00000,
        class: InsnClass::LDSTPAIR_INDEXED,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt2,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt2,
                    lsb: 10,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMM7,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::imm7,
                        lsb: 15,
                        width: 7,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::index2,
                        lsb: 24,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDSTPAIR_INDEXED(LDSTPAIR_INDEXED::LDPSW_Rt_X_Rt2_X_ADDR_SIMM7_S_S(
            LDPSW_Rt_X_Rt2_X_ADDR_SIMM7_S_S::from(bits),
        ))
    }
}
impl InsnOpcode for LDPSW_Rt_X_Rt2_X_ADDR_SIMM7_S_S {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDR_SME_ZA_array_off4_SME_ADDR_RI_U4xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldr",
        aliases: &[],
        opcode: 0xe1000000,
        mask: 0xffff9c10,
        class: InsnClass::SME_LDR,
        feature_set: InsnFeatureSet::SME,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off4,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm4_0,
                        lsb: 0,
                        width: 4,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_ADDR_RI_U4xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm4_0,
                        lsb: 0,
                        width: 4,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_LDR(SME_LDR::LDR_SME_ZA_array_off4_SME_ADDR_RI_U4xVL(
            LDR_SME_ZA_array_off4_SME_ADDR_RI_U4xVL::from(bits),
        ))
    }
}
impl InsnOpcode for LDR_SME_ZA_array_off4_SME_ADDR_RI_U4xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDR_SME_ZT0_SIMD_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldr",
        aliases: &[],
        opcode: 0xe11f8000,
        mask: 0xfffffc1f,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZT0,
                class: InsnOperandClass::SYSTEM,
                qualifiers: &[],
                bit_fields: &[],
            },
            InsnOperand {
                kind: InsnOperandKind::SIMD_ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::LDR_SME_ZT0_SIMD_ADDR_SIMPLE(
            LDR_SME_ZT0_SIMD_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for LDR_SME_ZT0_SIMD_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDR_Rt_ADDR_PCREL19 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldr",
        aliases: &[],
        opcode: 0x18000000,
        mask: 0xbf000000,
        class: InsnClass::LOADLIT,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_PCREL19,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::imm19,
                    lsb: 5,
                    width: 19,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMV_GPRSIZE_IN_Q.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LOADLIT(LOADLIT::LDR_Rt_ADDR_PCREL19(LDR_Rt_ADDR_PCREL19::from(
            bits,
        )))
    }
}
impl InsnOpcode for LDR_Rt_ADDR_PCREL19 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDR_Rt_ADDR_REGOFF {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldr",
        aliases: &[],
        opcode: 0xb8600800,
        mask: 0xbfe00c00,
        class: InsnClass::LDST_REGOFF,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_REGOFF,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMV_GPRSIZE_IN_Q.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDST_REGOFF(LDST_REGOFF::LDR_Rt_ADDR_REGOFF(LDR_Rt_ADDR_REGOFF::from(
            bits,
        )))
    }
}
impl InsnOpcode for LDR_Rt_ADDR_REGOFF {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDR_Rt_ADDR_SIMM9 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldr",
        aliases: &[],
        opcode: 0xb8400400,
        mask: 0xbfe00400,
        class: InsnClass::LDST_IMM9,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMM9,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::imm9,
                        lsb: 12,
                        width: 9,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::index,
                        lsb: 11,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMV_GPRSIZE_IN_Q.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDST_IMM9(LDST_IMM9::LDR_Rt_ADDR_SIMM9(LDR_Rt_ADDR_SIMM9::from(bits)))
    }
}
impl InsnOpcode for LDR_Rt_ADDR_SIMM9 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDR_Rt_ADDR_UIMM12 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldr",
        aliases: &[],
        opcode: 0xb9400000,
        mask: 0xbfc00000,
        class: InsnClass::LDST_POS,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_UIMM12,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm12,
                        lsb: 10,
                        width: 12,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMV_GPRSIZE_IN_Q.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDST_POS(LDST_POS::LDR_Rt_ADDR_UIMM12(LDR_Rt_ADDR_UIMM12::from(bits)))
    }
}
impl InsnOpcode for LDR_Rt_ADDR_UIMM12 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDR_SVE_Pt_SVE_ADDR_RI_S9xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldr",
        aliases: &[],
        opcode: 0x85800000,
        mask: 0xffc0e010,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Pt,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pt,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S9xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LDR_SVE_Pt_SVE_ADDR_RI_S9xVL(
            LDR_SVE_Pt_SVE_ADDR_RI_S9xVL::from(bits),
        ))
    }
}
impl InsnOpcode for LDR_SVE_Pt_SVE_ADDR_RI_S9xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDR_SVE_PNt_SVE_ADDR_RI_S9xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldr",
        aliases: &[],
        opcode: 0x85800000,
        mask: 0xffc0e010,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_PNt,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pt,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S9xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LDR_SVE_PNt_SVE_ADDR_RI_S9xVL(
            LDR_SVE_PNt_SVE_ADDR_RI_S9xVL::from(bits),
        ))
    }
}
impl InsnOpcode for LDR_SVE_PNt_SVE_ADDR_RI_S9xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDR_SVE_Zt_SVE_ADDR_RI_S9xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldr",
        aliases: &[],
        opcode: 0x85804000,
        mask: 0xffc0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zt,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S9xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::LDR_SVE_Zt_SVE_ADDR_RI_S9xVL(
            LDR_SVE_Zt_SVE_ADDR_RI_S9xVL::from(bits),
        ))
    }
}
impl InsnOpcode for LDR_SVE_Zt_SVE_ADDR_RI_S9xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDR_Ft_ADDR_PCREL19 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldr",
        aliases: &[],
        opcode: 0x1c000000,
        mask: 0x3f000000,
        class: InsnClass::LOADLIT,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Ft,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_PCREL19,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::imm19,
                    lsb: 5,
                    width: 19,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LOADLIT(LOADLIT::LDR_Ft_ADDR_PCREL19(LDR_Ft_ADDR_PCREL19::from(
            bits,
        )))
    }
}
impl InsnOpcode for LDR_Ft_ADDR_PCREL19 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDR_Ft_ADDR_REGOFF {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldr",
        aliases: &[],
        opcode: 0x3c600800,
        mask: 0x3f600c00,
        class: InsnClass::LDST_REGOFF,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Ft,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_REGOFF,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDST_REGOFF(LDST_REGOFF::LDR_Ft_ADDR_REGOFF(LDR_Ft_ADDR_REGOFF::from(
            bits,
        )))
    }
}
impl InsnOpcode for LDR_Ft_ADDR_REGOFF {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDR_Ft_ADDR_SIMM9 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldr",
        aliases: &[],
        opcode: 0x3c400400,
        mask: 0x3f600400,
        class: InsnClass::LDST_IMM9,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Ft,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMM9,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::imm9,
                        lsb: 12,
                        width: 9,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::index,
                        lsb: 11,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDST_IMM9(LDST_IMM9::LDR_Ft_ADDR_SIMM9(LDR_Ft_ADDR_SIMM9::from(bits)))
    }
}
impl InsnOpcode for LDR_Ft_ADDR_SIMM9 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDR_Ft_ADDR_UIMM12 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldr",
        aliases: &[],
        opcode: 0x3d400000,
        mask: 0x3f400000,
        class: InsnClass::LDST_POS,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Ft,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_UIMM12,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm12,
                        lsb: 10,
                        width: 12,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDST_POS(LDST_POS::LDR_Ft_ADDR_UIMM12(LDR_Ft_ADDR_UIMM12::from(bits)))
    }
}
impl InsnOpcode for LDR_Ft_ADDR_UIMM12 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDRAA_Rt_ADDR_SIMM10 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldraa",
        aliases: &[],
        opcode: 0xf8200400,
        mask: 0xffa00400,
        class: InsnClass::LDST_IMM10,
        feature_set: InsnFeatureSet::PAC,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMM10,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::S_imm10,
                        lsb: 22,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm9,
                        lsb: 12,
                        width: 9,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::index,
                        lsb: 11,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDST_IMM10(LDST_IMM10::LDRAA_Rt_ADDR_SIMM10(
            LDRAA_Rt_ADDR_SIMM10::from(bits),
        ))
    }
}
impl InsnOpcode for LDRAA_Rt_ADDR_SIMM10 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDRAB_Rt_ADDR_SIMM10 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldrab",
        aliases: &[],
        opcode: 0xf8a00400,
        mask: 0xffa00400,
        class: InsnClass::LDST_IMM10,
        feature_set: InsnFeatureSet::PAC,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMM10,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::S_imm10,
                        lsb: 22,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm9,
                        lsb: 12,
                        width: 9,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::index,
                        lsb: 11,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDST_IMM10(LDST_IMM10::LDRAB_Rt_ADDR_SIMM10(
            LDRAB_Rt_ADDR_SIMM10::from(bits),
        ))
    }
}
impl InsnOpcode for LDRAB_Rt_ADDR_SIMM10 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDRB_Rt_ADDR_REGOFF {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldrb",
        aliases: &[],
        opcode: 0x38600800,
        mask: 0xffe00c00,
        class: InsnClass::LDST_REGOFF,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_REGOFF,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDST_REGOFF(LDST_REGOFF::LDRB_Rt_ADDR_REGOFF(LDRB_Rt_ADDR_REGOFF::from(
            bits,
        )))
    }
}
impl InsnOpcode for LDRB_Rt_ADDR_REGOFF {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDRB_Rt_ADDR_SIMM9 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldrb",
        aliases: &[],
        opcode: 0x38400400,
        mask: 0xffe00400,
        class: InsnClass::LDST_IMM9,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMM9,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::imm9,
                        lsb: 12,
                        width: 9,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::index,
                        lsb: 11,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDST_IMM9(LDST_IMM9::LDRB_Rt_ADDR_SIMM9(LDRB_Rt_ADDR_SIMM9::from(
            bits,
        )))
    }
}
impl InsnOpcode for LDRB_Rt_ADDR_SIMM9 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDRB_Rt_ADDR_UIMM12 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldrb",
        aliases: &[],
        opcode: 0x39400000,
        mask: 0xffc00000,
        class: InsnClass::LDST_POS,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_UIMM12,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm12,
                        lsb: 10,
                        width: 12,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDST_POS(LDST_POS::LDRB_Rt_ADDR_UIMM12(LDRB_Rt_ADDR_UIMM12::from(
            bits,
        )))
    }
}
impl InsnOpcode for LDRB_Rt_ADDR_UIMM12 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDRH_Rt_ADDR_REGOFF {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldrh",
        aliases: &[],
        opcode: 0x78600800,
        mask: 0xffe00c00,
        class: InsnClass::LDST_REGOFF,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_REGOFF,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDST_REGOFF(LDST_REGOFF::LDRH_Rt_ADDR_REGOFF(LDRH_Rt_ADDR_REGOFF::from(
            bits,
        )))
    }
}
impl InsnOpcode for LDRH_Rt_ADDR_REGOFF {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDRH_Rt_ADDR_SIMM9 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldrh",
        aliases: &[],
        opcode: 0x78400400,
        mask: 0xffe00400,
        class: InsnClass::LDST_IMM9,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMM9,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::imm9,
                        lsb: 12,
                        width: 9,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::index,
                        lsb: 11,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDST_IMM9(LDST_IMM9::LDRH_Rt_ADDR_SIMM9(LDRH_Rt_ADDR_SIMM9::from(
            bits,
        )))
    }
}
impl InsnOpcode for LDRH_Rt_ADDR_SIMM9 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDRH_Rt_ADDR_UIMM12 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldrh",
        aliases: &[],
        opcode: 0x79400000,
        mask: 0xffc00000,
        class: InsnClass::LDST_POS,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_UIMM12,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm12,
                        lsb: 10,
                        width: 12,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDST_POS(LDST_POS::LDRH_Rt_ADDR_UIMM12(LDRH_Rt_ADDR_UIMM12::from(
            bits,
        )))
    }
}
impl InsnOpcode for LDRH_Rt_ADDR_UIMM12 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDRSB_Rt_ADDR_REGOFF {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldrsb",
        aliases: &[],
        opcode: 0x38a00800,
        mask: 0xffa00c00,
        class: InsnClass::LDST_REGOFF,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_REGOFF,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_LDS_SIZE_IN_BIT_22.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDST_REGOFF(LDST_REGOFF::LDRSB_Rt_ADDR_REGOFF(
            LDRSB_Rt_ADDR_REGOFF::from(bits),
        ))
    }
}
impl InsnOpcode for LDRSB_Rt_ADDR_REGOFF {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDRSB_Rt_ADDR_SIMM9 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldrsb",
        aliases: &[],
        opcode: 0x38800400,
        mask: 0xffa00400,
        class: InsnClass::LDST_IMM9,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMM9,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::imm9,
                        lsb: 12,
                        width: 9,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::index,
                        lsb: 11,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_LDS_SIZE_IN_BIT_22.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDST_IMM9(LDST_IMM9::LDRSB_Rt_ADDR_SIMM9(LDRSB_Rt_ADDR_SIMM9::from(
            bits,
        )))
    }
}
impl InsnOpcode for LDRSB_Rt_ADDR_SIMM9 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDRSB_Rt_ADDR_UIMM12 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldrsb",
        aliases: &[],
        opcode: 0x39800000,
        mask: 0xff800000,
        class: InsnClass::LDST_POS,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_UIMM12,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm12,
                        lsb: 10,
                        width: 12,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_LDS_SIZE_IN_BIT_22.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDST_POS(LDST_POS::LDRSB_Rt_ADDR_UIMM12(LDRSB_Rt_ADDR_UIMM12::from(
            bits,
        )))
    }
}
impl InsnOpcode for LDRSB_Rt_ADDR_UIMM12 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDRSH_Rt_ADDR_REGOFF {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldrsh",
        aliases: &[],
        opcode: 0x78a00800,
        mask: 0xffa00c00,
        class: InsnClass::LDST_REGOFF,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_REGOFF,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_LDS_SIZE_IN_BIT_22.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDST_REGOFF(LDST_REGOFF::LDRSH_Rt_ADDR_REGOFF(
            LDRSH_Rt_ADDR_REGOFF::from(bits),
        ))
    }
}
impl InsnOpcode for LDRSH_Rt_ADDR_REGOFF {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDRSH_Rt_ADDR_SIMM9 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldrsh",
        aliases: &[],
        opcode: 0x78800400,
        mask: 0xffa00400,
        class: InsnClass::LDST_IMM9,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMM9,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::imm9,
                        lsb: 12,
                        width: 9,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::index,
                        lsb: 11,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_LDS_SIZE_IN_BIT_22.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDST_IMM9(LDST_IMM9::LDRSH_Rt_ADDR_SIMM9(LDRSH_Rt_ADDR_SIMM9::from(
            bits,
        )))
    }
}
impl InsnOpcode for LDRSH_Rt_ADDR_SIMM9 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDRSH_Rt_ADDR_UIMM12 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldrsh",
        aliases: &[],
        opcode: 0x79800000,
        mask: 0xff800000,
        class: InsnClass::LDST_POS,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_UIMM12,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm12,
                        lsb: 10,
                        width: 12,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_LDS_SIZE_IN_BIT_22.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDST_POS(LDST_POS::LDRSH_Rt_ADDR_UIMM12(LDRSH_Rt_ADDR_UIMM12::from(
            bits,
        )))
    }
}
impl InsnOpcode for LDRSH_Rt_ADDR_UIMM12 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDRSW_Rt_ADDR_PCREL19 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldrsw",
        aliases: &[],
        opcode: 0x98000000,
        mask: 0xff000000,
        class: InsnClass::LOADLIT,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_PCREL19,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::imm19,
                    lsb: 5,
                    width: 19,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LOADLIT(LOADLIT::LDRSW_Rt_ADDR_PCREL19(LDRSW_Rt_ADDR_PCREL19::from(
            bits,
        )))
    }
}
impl InsnOpcode for LDRSW_Rt_ADDR_PCREL19 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDRSW_Rt_ADDR_REGOFF {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldrsw",
        aliases: &[],
        opcode: 0xb8a00800,
        mask: 0xffe00c00,
        class: InsnClass::LDST_REGOFF,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_REGOFF,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDST_REGOFF(LDST_REGOFF::LDRSW_Rt_ADDR_REGOFF(
            LDRSW_Rt_ADDR_REGOFF::from(bits),
        ))
    }
}
impl InsnOpcode for LDRSW_Rt_ADDR_REGOFF {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDRSW_Rt_ADDR_SIMM9 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldrsw",
        aliases: &[],
        opcode: 0xb8800400,
        mask: 0xffe00400,
        class: InsnClass::LDST_IMM9,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMM9,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::imm9,
                        lsb: 12,
                        width: 9,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::index,
                        lsb: 11,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDST_IMM9(LDST_IMM9::LDRSW_Rt_ADDR_SIMM9(LDRSW_Rt_ADDR_SIMM9::from(
            bits,
        )))
    }
}
impl InsnOpcode for LDRSW_Rt_ADDR_SIMM9 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDRSW_Rt_ADDR_UIMM12 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldrsw",
        aliases: &[],
        opcode: 0xb9800000,
        mask: 0xffc00000,
        class: InsnClass::LDST_POS,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_UIMM12,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm12,
                        lsb: 10,
                        width: 12,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDST_POS(LDST_POS::LDRSW_Rt_ADDR_UIMM12(LDRSW_Rt_ADDR_UIMM12::from(
            bits,
        )))
    }
}
impl InsnOpcode for LDRSW_Rt_ADDR_UIMM12 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDSET_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldset",
        aliases: &[],
        opcode: 0xb8203000,
        mask: 0xbfe0fc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LSE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_ALIAS.bits() | InsnFlags::HAS_LSE_SZ_FIELD.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::LDSET_Rs_Rt_ADDR_SIMPLE(
            LDSET_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for LDSET_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDSETA_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldseta",
        aliases: &[],
        opcode: 0xb8a03000,
        mask: 0xbfe0fc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LSE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_LSE_SZ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::LDSETA_Rs_Rt_ADDR_SIMPLE(
            LDSETA_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for LDSETA_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDSETAB_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldsetab",
        aliases: &[],
        opcode: 0x38a03000,
        mask: 0xffe0fc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LSE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::LDSETAB_Rs_Rt_ADDR_SIMPLE(
            LDSETAB_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for LDSETAB_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDSETAH_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldsetah",
        aliases: &[],
        opcode: 0x78a03000,
        mask: 0xffe0fc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LSE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::LDSETAH_Rs_Rt_ADDR_SIMPLE(
            LDSETAH_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for LDSETAH_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDSETAL_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldsetal",
        aliases: &[],
        opcode: 0xb8e03000,
        mask: 0xbfe0fc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LSE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_LSE_SZ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::LDSETAL_Rs_Rt_ADDR_SIMPLE(
            LDSETAL_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for LDSETAL_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDSETALB_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldsetalb",
        aliases: &[],
        opcode: 0x38e03000,
        mask: 0xffe0fc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LSE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::LDSETALB_Rs_Rt_ADDR_SIMPLE(
            LDSETALB_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for LDSETALB_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDSETALH_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldsetalh",
        aliases: &[],
        opcode: 0x78e03000,
        mask: 0xffe0fc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LSE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::LDSETALH_Rs_Rt_ADDR_SIMPLE(
            LDSETALH_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for LDSETALH_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDSETB_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldsetb",
        aliases: &[],
        opcode: 0x38203000,
        mask: 0xffe0fc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LSE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ALIAS.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::LDSETB_Rs_Rt_ADDR_SIMPLE(
            LDSETB_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for LDSETB_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDSETH_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldseth",
        aliases: &[],
        opcode: 0x78203000,
        mask: 0xffe0fc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LSE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ALIAS.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::LDSETH_Rs_Rt_ADDR_SIMPLE(
            LDSETH_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for LDSETH_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDSETL_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldsetl",
        aliases: &[],
        opcode: 0xb8603000,
        mask: 0xbfe0fc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LSE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_ALIAS.bits() | InsnFlags::HAS_LSE_SZ_FIELD.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::LDSETL_Rs_Rt_ADDR_SIMPLE(
            LDSETL_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for LDSETL_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDSETLB_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldsetlb",
        aliases: &[],
        opcode: 0x38603000,
        mask: 0xffe0fc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LSE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ALIAS.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::LDSETLB_Rs_Rt_ADDR_SIMPLE(
            LDSETLB_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for LDSETLB_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDSETLH_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldsetlh",
        aliases: &[],
        opcode: 0x78603000,
        mask: 0xffe0fc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LSE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ALIAS.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::LDSETLH_Rs_Rt_ADDR_SIMPLE(
            LDSETLH_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for LDSETLH_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDSETP_LSE128_Rt_LSE128_Rt2_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldsetp",
        aliases: &[],
        opcode: 0x19203000,
        mask: 0xffe0fc00,
        class: InsnClass::LSE128_ATOMIC,
        feature_set: InsnFeatureSet::LSE128,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::LSE128_Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::LSE128_Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::LSE128_Rt2,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::LSE128_Rt2,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE128_ATOMIC(LSE128_ATOMIC::LDSETP_LSE128_Rt_LSE128_Rt2_ADDR_SIMPLE(
            LDSETP_LSE128_Rt_LSE128_Rt2_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for LDSETP_LSE128_Rt_LSE128_Rt2_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDSETPA_LSE128_Rt_LSE128_Rt2_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldsetpa",
        aliases: &[],
        opcode: 0x19a03000,
        mask: 0xffe0fc00,
        class: InsnClass::LSE128_ATOMIC,
        feature_set: InsnFeatureSet::LSE128,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::LSE128_Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::LSE128_Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::LSE128_Rt2,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::LSE128_Rt2,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE128_ATOMIC(LSE128_ATOMIC::LDSETPA_LSE128_Rt_LSE128_Rt2_ADDR_SIMPLE(
            LDSETPA_LSE128_Rt_LSE128_Rt2_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for LDSETPA_LSE128_Rt_LSE128_Rt2_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDSETPAL_LSE128_Rt_LSE128_Rt2_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldsetpal",
        aliases: &[],
        opcode: 0x19e03000,
        mask: 0xffe0fc00,
        class: InsnClass::LSE128_ATOMIC,
        feature_set: InsnFeatureSet::LSE128,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::LSE128_Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::LSE128_Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::LSE128_Rt2,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::LSE128_Rt2,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE128_ATOMIC(LSE128_ATOMIC::LDSETPAL_LSE128_Rt_LSE128_Rt2_ADDR_SIMPLE(
            LDSETPAL_LSE128_Rt_LSE128_Rt2_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for LDSETPAL_LSE128_Rt_LSE128_Rt2_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDSETPL_LSE128_Rt_LSE128_Rt2_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldsetpl",
        aliases: &[],
        opcode: 0x19603000,
        mask: 0xffe0fc00,
        class: InsnClass::LSE128_ATOMIC,
        feature_set: InsnFeatureSet::LSE128,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::LSE128_Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::LSE128_Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::LSE128_Rt2,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::LSE128_Rt2,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE128_ATOMIC(LSE128_ATOMIC::LDSETPL_LSE128_Rt_LSE128_Rt2_ADDR_SIMPLE(
            LDSETPL_LSE128_Rt_LSE128_Rt2_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for LDSETPL_LSE128_Rt_LSE128_Rt2_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDSMAX_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldsmax",
        aliases: &[],
        opcode: 0xb8204000,
        mask: 0xbfe0fc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LSE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_ALIAS.bits() | InsnFlags::HAS_LSE_SZ_FIELD.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::LDSMAX_Rs_Rt_ADDR_SIMPLE(
            LDSMAX_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for LDSMAX_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDSMAXA_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldsmaxa",
        aliases: &[],
        opcode: 0xb8a04000,
        mask: 0xbfe0fc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LSE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_LSE_SZ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::LDSMAXA_Rs_Rt_ADDR_SIMPLE(
            LDSMAXA_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for LDSMAXA_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDSMAXAB_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldsmaxab",
        aliases: &[],
        opcode: 0x38a04000,
        mask: 0xffe0fc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LSE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::LDSMAXAB_Rs_Rt_ADDR_SIMPLE(
            LDSMAXAB_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for LDSMAXAB_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDSMAXAH_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldsmaxah",
        aliases: &[],
        opcode: 0x78a04000,
        mask: 0xffe0fc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LSE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::LDSMAXAH_Rs_Rt_ADDR_SIMPLE(
            LDSMAXAH_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for LDSMAXAH_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDSMAXAL_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldsmaxal",
        aliases: &[],
        opcode: 0xb8e04000,
        mask: 0xbfe0fc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LSE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_LSE_SZ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::LDSMAXAL_Rs_Rt_ADDR_SIMPLE(
            LDSMAXAL_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for LDSMAXAL_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDSMAXALB_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldsmaxalb",
        aliases: &[],
        opcode: 0x38e04000,
        mask: 0xffe0fc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LSE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::LDSMAXALB_Rs_Rt_ADDR_SIMPLE(
            LDSMAXALB_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for LDSMAXALB_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDSMAXALH_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldsmaxalh",
        aliases: &[],
        opcode: 0x78e04000,
        mask: 0xffe0fc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LSE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::LDSMAXALH_Rs_Rt_ADDR_SIMPLE(
            LDSMAXALH_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for LDSMAXALH_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDSMAXB_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldsmaxb",
        aliases: &[],
        opcode: 0x38204000,
        mask: 0xffe0fc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LSE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ALIAS.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::LDSMAXB_Rs_Rt_ADDR_SIMPLE(
            LDSMAXB_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for LDSMAXB_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDSMAXH_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldsmaxh",
        aliases: &[],
        opcode: 0x78204000,
        mask: 0xffe0fc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LSE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ALIAS.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::LDSMAXH_Rs_Rt_ADDR_SIMPLE(
            LDSMAXH_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for LDSMAXH_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDSMAXL_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldsmaxl",
        aliases: &[],
        opcode: 0xb8604000,
        mask: 0xbfe0fc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LSE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_ALIAS.bits() | InsnFlags::HAS_LSE_SZ_FIELD.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::LDSMAXL_Rs_Rt_ADDR_SIMPLE(
            LDSMAXL_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for LDSMAXL_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDSMAXLB_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldsmaxlb",
        aliases: &[],
        opcode: 0x38604000,
        mask: 0xffe0fc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LSE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ALIAS.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::LDSMAXLB_Rs_Rt_ADDR_SIMPLE(
            LDSMAXLB_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for LDSMAXLB_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDSMAXLH_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldsmaxlh",
        aliases: &[],
        opcode: 0x78604000,
        mask: 0xffe0fc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LSE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ALIAS.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::LDSMAXLH_Rs_Rt_ADDR_SIMPLE(
            LDSMAXLH_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for LDSMAXLH_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDSMIN_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldsmin",
        aliases: &[],
        opcode: 0xb8205000,
        mask: 0xbfe0fc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LSE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_ALIAS.bits() | InsnFlags::HAS_LSE_SZ_FIELD.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::LDSMIN_Rs_Rt_ADDR_SIMPLE(
            LDSMIN_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for LDSMIN_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDSMINA_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldsmina",
        aliases: &[],
        opcode: 0xb8a05000,
        mask: 0xbfe0fc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LSE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_LSE_SZ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::LDSMINA_Rs_Rt_ADDR_SIMPLE(
            LDSMINA_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for LDSMINA_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDSMINAB_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldsminab",
        aliases: &[],
        opcode: 0x38a05000,
        mask: 0xffe0fc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LSE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::LDSMINAB_Rs_Rt_ADDR_SIMPLE(
            LDSMINAB_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for LDSMINAB_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDSMINAH_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldsminah",
        aliases: &[],
        opcode: 0x78a05000,
        mask: 0xffe0fc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LSE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::LDSMINAH_Rs_Rt_ADDR_SIMPLE(
            LDSMINAH_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for LDSMINAH_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDSMINAL_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldsminal",
        aliases: &[],
        opcode: 0xb8e05000,
        mask: 0xbfe0fc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LSE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_LSE_SZ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::LDSMINAL_Rs_Rt_ADDR_SIMPLE(
            LDSMINAL_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for LDSMINAL_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDSMINALB_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldsminalb",
        aliases: &[],
        opcode: 0x38e05000,
        mask: 0xffe0fc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LSE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::LDSMINALB_Rs_Rt_ADDR_SIMPLE(
            LDSMINALB_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for LDSMINALB_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDSMINALH_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldsminalh",
        aliases: &[],
        opcode: 0x78e05000,
        mask: 0xffe0fc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LSE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::LDSMINALH_Rs_Rt_ADDR_SIMPLE(
            LDSMINALH_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for LDSMINALH_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDSMINB_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldsminb",
        aliases: &[],
        opcode: 0x38205000,
        mask: 0xffe0fc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LSE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ALIAS.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::LDSMINB_Rs_Rt_ADDR_SIMPLE(
            LDSMINB_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for LDSMINB_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDSMINH_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldsminh",
        aliases: &[],
        opcode: 0x78205000,
        mask: 0xffe0fc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LSE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ALIAS.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::LDSMINH_Rs_Rt_ADDR_SIMPLE(
            LDSMINH_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for LDSMINH_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDSMINL_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldsminl",
        aliases: &[],
        opcode: 0xb8605000,
        mask: 0xbfe0fc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LSE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_ALIAS.bits() | InsnFlags::HAS_LSE_SZ_FIELD.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::LDSMINL_Rs_Rt_ADDR_SIMPLE(
            LDSMINL_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for LDSMINL_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDSMINLB_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldsminlb",
        aliases: &[],
        opcode: 0x38605000,
        mask: 0xffe0fc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LSE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ALIAS.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::LDSMINLB_Rs_Rt_ADDR_SIMPLE(
            LDSMINLB_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for LDSMINLB_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDSMINLH_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldsminlh",
        aliases: &[],
        opcode: 0x78605000,
        mask: 0xffe0fc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LSE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ALIAS.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::LDSMINLH_Rs_Rt_ADDR_SIMPLE(
            LDSMINLH_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for LDSMINLH_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDTR_Rt_ADDR_SIMM9 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldtr",
        aliases: &[],
        opcode: 0xb8400800,
        mask: 0xbfe00c00,
        class: InsnClass::LDST_UNPRIV,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMM9,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::imm9,
                        lsb: 12,
                        width: 9,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::index,
                        lsb: 11,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMV_GPRSIZE_IN_Q.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDST_UNPRIV(LDST_UNPRIV::LDTR_Rt_ADDR_SIMM9(LDTR_Rt_ADDR_SIMM9::from(
            bits,
        )))
    }
}
impl InsnOpcode for LDTR_Rt_ADDR_SIMM9 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDTRB_Rt_ADDR_SIMM9 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldtrb",
        aliases: &[],
        opcode: 0x38400800,
        mask: 0xffe00c00,
        class: InsnClass::LDST_UNPRIV,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMM9,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::imm9,
                        lsb: 12,
                        width: 9,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::index,
                        lsb: 11,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDST_UNPRIV(LDST_UNPRIV::LDTRB_Rt_ADDR_SIMM9(LDTRB_Rt_ADDR_SIMM9::from(
            bits,
        )))
    }
}
impl InsnOpcode for LDTRB_Rt_ADDR_SIMM9 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDTRH_Rt_ADDR_SIMM9 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldtrh",
        aliases: &[],
        opcode: 0x78400800,
        mask: 0xffe00c00,
        class: InsnClass::LDST_UNPRIV,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMM9,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::imm9,
                        lsb: 12,
                        width: 9,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::index,
                        lsb: 11,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDST_UNPRIV(LDST_UNPRIV::LDTRH_Rt_ADDR_SIMM9(LDTRH_Rt_ADDR_SIMM9::from(
            bits,
        )))
    }
}
impl InsnOpcode for LDTRH_Rt_ADDR_SIMM9 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDTRSB_Rt_ADDR_SIMM9 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldtrsb",
        aliases: &[],
        opcode: 0x38800800,
        mask: 0xffa00c00,
        class: InsnClass::LDST_UNPRIV,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMM9,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::imm9,
                        lsb: 12,
                        width: 9,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::index,
                        lsb: 11,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_LDS_SIZE_IN_BIT_22.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDST_UNPRIV(LDST_UNPRIV::LDTRSB_Rt_ADDR_SIMM9(
            LDTRSB_Rt_ADDR_SIMM9::from(bits),
        ))
    }
}
impl InsnOpcode for LDTRSB_Rt_ADDR_SIMM9 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDTRSH_Rt_ADDR_SIMM9 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldtrsh",
        aliases: &[],
        opcode: 0x78800800,
        mask: 0xffa00c00,
        class: InsnClass::LDST_UNPRIV,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMM9,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::imm9,
                        lsb: 12,
                        width: 9,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::index,
                        lsb: 11,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_LDS_SIZE_IN_BIT_22.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDST_UNPRIV(LDST_UNPRIV::LDTRSH_Rt_ADDR_SIMM9(
            LDTRSH_Rt_ADDR_SIMM9::from(bits),
        ))
    }
}
impl InsnOpcode for LDTRSH_Rt_ADDR_SIMM9 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDTRSW_Rt_ADDR_SIMM9 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldtrsw",
        aliases: &[],
        opcode: 0xb8800800,
        mask: 0xffe00c00,
        class: InsnClass::LDST_UNPRIV,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMM9,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::imm9,
                        lsb: 12,
                        width: 9,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::index,
                        lsb: 11,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDST_UNPRIV(LDST_UNPRIV::LDTRSW_Rt_ADDR_SIMM9(
            LDTRSW_Rt_ADDR_SIMM9::from(bits),
        ))
    }
}
impl InsnOpcode for LDTRSW_Rt_ADDR_SIMM9 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDUMAX_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldumax",
        aliases: &[],
        opcode: 0xb8206000,
        mask: 0xbfe0fc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LSE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_ALIAS.bits() | InsnFlags::HAS_LSE_SZ_FIELD.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::LDUMAX_Rs_Rt_ADDR_SIMPLE(
            LDUMAX_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for LDUMAX_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDUMAXA_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldumaxa",
        aliases: &[],
        opcode: 0xb8a06000,
        mask: 0xbfe0fc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LSE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_LSE_SZ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::LDUMAXA_Rs_Rt_ADDR_SIMPLE(
            LDUMAXA_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for LDUMAXA_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDUMAXAB_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldumaxab",
        aliases: &[],
        opcode: 0x38a06000,
        mask: 0xffe0fc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LSE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::LDUMAXAB_Rs_Rt_ADDR_SIMPLE(
            LDUMAXAB_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for LDUMAXAB_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDUMAXAH_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldumaxah",
        aliases: &[],
        opcode: 0x78a06000,
        mask: 0xffe0fc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LSE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::LDUMAXAH_Rs_Rt_ADDR_SIMPLE(
            LDUMAXAH_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for LDUMAXAH_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDUMAXAL_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldumaxal",
        aliases: &[],
        opcode: 0xb8e06000,
        mask: 0xbfe0fc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LSE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_LSE_SZ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::LDUMAXAL_Rs_Rt_ADDR_SIMPLE(
            LDUMAXAL_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for LDUMAXAL_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDUMAXALB_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldumaxalb",
        aliases: &[],
        opcode: 0x38e06000,
        mask: 0xffe0fc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LSE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::LDUMAXALB_Rs_Rt_ADDR_SIMPLE(
            LDUMAXALB_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for LDUMAXALB_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDUMAXALH_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldumaxalh",
        aliases: &[],
        opcode: 0x78e06000,
        mask: 0xffe0fc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LSE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::LDUMAXALH_Rs_Rt_ADDR_SIMPLE(
            LDUMAXALH_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for LDUMAXALH_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDUMAXB_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldumaxb",
        aliases: &[],
        opcode: 0x38206000,
        mask: 0xffe0fc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LSE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ALIAS.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::LDUMAXB_Rs_Rt_ADDR_SIMPLE(
            LDUMAXB_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for LDUMAXB_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDUMAXH_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldumaxh",
        aliases: &[],
        opcode: 0x78206000,
        mask: 0xffe0fc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LSE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ALIAS.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::LDUMAXH_Rs_Rt_ADDR_SIMPLE(
            LDUMAXH_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for LDUMAXH_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDUMAXL_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldumaxl",
        aliases: &[],
        opcode: 0xb8606000,
        mask: 0xbfe0fc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LSE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_ALIAS.bits() | InsnFlags::HAS_LSE_SZ_FIELD.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::LDUMAXL_Rs_Rt_ADDR_SIMPLE(
            LDUMAXL_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for LDUMAXL_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDUMAXLB_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldumaxlb",
        aliases: &[],
        opcode: 0x38606000,
        mask: 0xffe0fc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LSE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ALIAS.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::LDUMAXLB_Rs_Rt_ADDR_SIMPLE(
            LDUMAXLB_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for LDUMAXLB_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDUMAXLH_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldumaxlh",
        aliases: &[],
        opcode: 0x78606000,
        mask: 0xffe0fc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LSE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ALIAS.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::LDUMAXLH_Rs_Rt_ADDR_SIMPLE(
            LDUMAXLH_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for LDUMAXLH_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDUMIN_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldumin",
        aliases: &[],
        opcode: 0xb8207000,
        mask: 0xbfe0fc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LSE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_ALIAS.bits() | InsnFlags::HAS_LSE_SZ_FIELD.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::LDUMIN_Rs_Rt_ADDR_SIMPLE(
            LDUMIN_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for LDUMIN_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDUMINA_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldumina",
        aliases: &[],
        opcode: 0xb8a07000,
        mask: 0xbfe0fc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LSE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_LSE_SZ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::LDUMINA_Rs_Rt_ADDR_SIMPLE(
            LDUMINA_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for LDUMINA_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDUMINAB_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "lduminab",
        aliases: &[],
        opcode: 0x38a07000,
        mask: 0xffe0fc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LSE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::LDUMINAB_Rs_Rt_ADDR_SIMPLE(
            LDUMINAB_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for LDUMINAB_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDUMINAH_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "lduminah",
        aliases: &[],
        opcode: 0x78a07000,
        mask: 0xffe0fc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LSE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::LDUMINAH_Rs_Rt_ADDR_SIMPLE(
            LDUMINAH_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for LDUMINAH_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDUMINAL_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "lduminal",
        aliases: &[],
        opcode: 0xb8e07000,
        mask: 0xbfe0fc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LSE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_LSE_SZ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::LDUMINAL_Rs_Rt_ADDR_SIMPLE(
            LDUMINAL_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for LDUMINAL_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDUMINALB_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "lduminalb",
        aliases: &[],
        opcode: 0x38e07000,
        mask: 0xffe0fc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LSE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::LDUMINALB_Rs_Rt_ADDR_SIMPLE(
            LDUMINALB_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for LDUMINALB_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDUMINALH_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "lduminalh",
        aliases: &[],
        opcode: 0x78e07000,
        mask: 0xffe0fc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LSE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::LDUMINALH_Rs_Rt_ADDR_SIMPLE(
            LDUMINALH_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for LDUMINALH_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDUMINB_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "lduminb",
        aliases: &[],
        opcode: 0x38207000,
        mask: 0xffe0fc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LSE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ALIAS.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::LDUMINB_Rs_Rt_ADDR_SIMPLE(
            LDUMINB_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for LDUMINB_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDUMINH_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "lduminh",
        aliases: &[],
        opcode: 0x78207000,
        mask: 0xffe0fc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LSE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ALIAS.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::LDUMINH_Rs_Rt_ADDR_SIMPLE(
            LDUMINH_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for LDUMINH_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDUMINL_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "lduminl",
        aliases: &[],
        opcode: 0xb8607000,
        mask: 0xbfe0fc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LSE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_ALIAS.bits() | InsnFlags::HAS_LSE_SZ_FIELD.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::LDUMINL_Rs_Rt_ADDR_SIMPLE(
            LDUMINL_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for LDUMINL_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDUMINLB_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "lduminlb",
        aliases: &[],
        opcode: 0x38607000,
        mask: 0xffe0fc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LSE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ALIAS.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::LDUMINLB_Rs_Rt_ADDR_SIMPLE(
            LDUMINLB_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for LDUMINLB_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDUMINLH_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "lduminlh",
        aliases: &[],
        opcode: 0x78607000,
        mask: 0xffe0fc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LSE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ALIAS.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::LDUMINLH_Rs_Rt_ADDR_SIMPLE(
            LDUMINLH_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for LDUMINLH_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDUR_Rt_ADDR_SIMM9 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldur",
        aliases: &[],
        opcode: 0xb8400000,
        mask: 0xbfe00c00,
        class: InsnClass::LDST_UNSCALED,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMM9,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::imm9,
                        lsb: 12,
                        width: 9,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::index,
                        lsb: 11,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMV_GPRSIZE_IN_Q.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDST_UNSCALED(LDST_UNSCALED::LDUR_Rt_ADDR_SIMM9(LDUR_Rt_ADDR_SIMM9::from(
            bits,
        )))
    }
}
impl InsnOpcode for LDUR_Rt_ADDR_SIMM9 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDUR_Ft_ADDR_SIMM9 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldur",
        aliases: &[],
        opcode: 0x3c400000,
        mask: 0x3f600c00,
        class: InsnClass::LDST_UNSCALED,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Ft,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMM9,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::imm9,
                        lsb: 12,
                        width: 9,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::index,
                        lsb: 11,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDST_UNSCALED(LDST_UNSCALED::LDUR_Ft_ADDR_SIMM9(LDUR_Ft_ADDR_SIMM9::from(
            bits,
        )))
    }
}
impl InsnOpcode for LDUR_Ft_ADDR_SIMM9 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDURB_Rt_ADDR_SIMM9 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldurb",
        aliases: &[],
        opcode: 0x38400000,
        mask: 0xffe00c00,
        class: InsnClass::LDST_UNSCALED,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMM9,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::imm9,
                        lsb: 12,
                        width: 9,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::index,
                        lsb: 11,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDST_UNSCALED(LDST_UNSCALED::LDURB_Rt_ADDR_SIMM9(
            LDURB_Rt_ADDR_SIMM9::from(bits),
        ))
    }
}
impl InsnOpcode for LDURB_Rt_ADDR_SIMM9 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDURH_Rt_ADDR_SIMM9 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldurh",
        aliases: &[],
        opcode: 0x78400000,
        mask: 0xffe00c00,
        class: InsnClass::LDST_UNSCALED,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMM9,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::imm9,
                        lsb: 12,
                        width: 9,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::index,
                        lsb: 11,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDST_UNSCALED(LDST_UNSCALED::LDURH_Rt_ADDR_SIMM9(
            LDURH_Rt_ADDR_SIMM9::from(bits),
        ))
    }
}
impl InsnOpcode for LDURH_Rt_ADDR_SIMM9 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDURSB_Rt_ADDR_SIMM9 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldursb",
        aliases: &[],
        opcode: 0x38800000,
        mask: 0xffa00c00,
        class: InsnClass::LDST_UNSCALED,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMM9,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::imm9,
                        lsb: 12,
                        width: 9,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::index,
                        lsb: 11,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_LDS_SIZE_IN_BIT_22.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDST_UNSCALED(LDST_UNSCALED::LDURSB_Rt_ADDR_SIMM9(
            LDURSB_Rt_ADDR_SIMM9::from(bits),
        ))
    }
}
impl InsnOpcode for LDURSB_Rt_ADDR_SIMM9 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDURSH_Rt_ADDR_SIMM9 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldursh",
        aliases: &[],
        opcode: 0x78800000,
        mask: 0xffa00c00,
        class: InsnClass::LDST_UNSCALED,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMM9,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::imm9,
                        lsb: 12,
                        width: 9,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::index,
                        lsb: 11,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_LDS_SIZE_IN_BIT_22.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDST_UNSCALED(LDST_UNSCALED::LDURSH_Rt_ADDR_SIMM9(
            LDURSH_Rt_ADDR_SIMM9::from(bits),
        ))
    }
}
impl InsnOpcode for LDURSH_Rt_ADDR_SIMM9 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDURSW_Rt_ADDR_SIMM9 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldursw",
        aliases: &[],
        opcode: 0xb8800000,
        mask: 0xffe00c00,
        class: InsnClass::LDST_UNSCALED,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMM9,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::imm9,
                        lsb: 12,
                        width: 9,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::index,
                        lsb: 11,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDST_UNSCALED(LDST_UNSCALED::LDURSW_Rt_ADDR_SIMM9(
            LDURSW_Rt_ADDR_SIMM9::from(bits),
        ))
    }
}
impl InsnOpcode for LDURSW_Rt_ADDR_SIMM9 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDXP_Rt_Rt2_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldxp",
        aliases: &[],
        opcode: 0x887f0000,
        mask: 0xbfff8000,
        class: InsnClass::LDSTEXCL,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt2,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt2,
                    lsb: 10,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMV_GPRSIZE_IN_Q.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDSTEXCL(LDSTEXCL::LDXP_Rt_Rt2_ADDR_SIMPLE(
            LDXP_Rt_Rt2_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for LDXP_Rt_Rt2_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDXR_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldxr",
        aliases: &[],
        opcode: 0x885f7c00,
        mask: 0xbffffc00,
        class: InsnClass::LDSTEXCL,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMV_GPRSIZE_IN_Q.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDSTEXCL(LDSTEXCL::LDXR_Rt_ADDR_SIMPLE(LDXR_Rt_ADDR_SIMPLE::from(
            bits,
        )))
    }
}
impl InsnOpcode for LDXR_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDXRB_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldxrb",
        aliases: &[],
        opcode: 0x85f7c00,
        mask: 0xfffffc00,
        class: InsnClass::LDSTEXCL,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDSTEXCL(LDSTEXCL::LDXRB_Rt_ADDR_SIMPLE(LDXRB_Rt_ADDR_SIMPLE::from(
            bits,
        )))
    }
}
impl InsnOpcode for LDXRB_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LDXRH_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ldxrh",
        aliases: &[],
        opcode: 0x485f7c00,
        mask: 0xfffffc00,
        class: InsnClass::LDSTEXCL,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDSTEXCL(LDSTEXCL::LDXRH_Rt_ADDR_SIMPLE(LDXRH_Rt_ADDR_SIMPLE::from(
            bits,
        )))
    }
}
impl InsnOpcode for LDXRH_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LSL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_SHLIMM_PRED {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "lsl",
        aliases: &[],
        opcode: 0x4038000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SHIFT_PRED,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_SHLIMM_PRED,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_tszh,
                        lsb: 22,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_imm5,
                        lsb: 5,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SHIFT_PRED(SVE_SHIFT_PRED::LSL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_SHLIMM_PRED(
            LSL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_SHLIMM_PRED::from(bits),
        ))
    }
}
impl InsnOpcode for LSL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_SHLIMM_PRED {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LSL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "lsl",
        aliases: &[],
        opcode: 0x4138000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_5,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_5,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::LSL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(
            LSL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5::from(bits),
        ))
    }
}
impl InsnOpcode for LSL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LSL_SVE_Zd_S_B_SVE_Pg3_P_M_SVE_Zd_S_B_SVE_Zm_5_S_D {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "lsl",
        aliases: &[],
        opcode: 0x41b8000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_BHS,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_5,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_D,
                    InsnOperandQualifier::S_D,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_5,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHS(
            SVE_SIZE_BHS::LSL_SVE_Zd_S_B_SVE_Pg3_P_M_SVE_Zd_S_B_SVE_Zm_5_S_D(
                LSL_SVE_Zd_S_B_SVE_Pg3_P_M_SVE_Zd_S_B_SVE_Zm_5_S_D::from(bits),
            ),
        )
    }
}
impl InsnOpcode for LSL_SVE_Zd_S_B_SVE_Pg3_P_M_SVE_Zd_S_B_SVE_Zm_5_S_D {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LSL_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "lsl",
        aliases: &[],
        opcode: 0x4208c00,
        mask: 0xff20fc00,
        class: InsnClass::SVE_SIZE_BHS,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHS(SVE_SIZE_BHS::LSL_SVE_Zd_SVE_Zn_SVE_Zm_16(
            LSL_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for LSL_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LSL_SVE_Zd_SVE_Zn_SVE_SHLIMM_UNPRED {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "lsl",
        aliases: &[],
        opcode: 0x4209c00,
        mask: 0xff20fc00,
        class: InsnClass::SVE_SHIFT_UNPRED,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_SHLIMM_UNPRED,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_tszh,
                        lsb: 22,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm5,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SHIFT_UNPRED(SVE_SHIFT_UNPRED::LSL_SVE_Zd_SVE_Zn_SVE_SHLIMM_UNPRED(
            LSL_SVE_Zd_SVE_Zn_SVE_SHLIMM_UNPRED::from(bits),
        ))
    }
}
impl InsnOpcode for LSL_SVE_Zd_SVE_Zn_SVE_SHLIMM_UNPRED {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LSLR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "lslr",
        aliases: &[],
        opcode: 0x4178000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_5,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_5,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::LSLR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(
            LSLR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5::from(bits),
        ))
    }
}
impl InsnOpcode for LSLR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LSLV_Rd_Rn_Rm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "lslv",
        aliases: &[],
        opcode: 0x1ac02000,
        mask: 0x7fe0fc00,
        class: InsnClass::DP_2SRC,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rm,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_ALIAS.bits() | InsnFlags::HAS_SF_FIELD.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::DP_2SRC(DP_2SRC::LSLV_Rd_Rn_Rm(LSLV_Rd_Rn_Rm::from(bits)))
    }
}
impl InsnOpcode for LSLV_Rd_Rn_Rm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LSR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_SHRIMM_PRED {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "lsr",
        aliases: &[],
        opcode: 0x4018000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SHIFT_PRED,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_SHRIMM_PRED,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_tszh,
                        lsb: 22,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_imm5,
                        lsb: 5,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SHIFT_PRED(SVE_SHIFT_PRED::LSR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_SHRIMM_PRED(
            LSR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_SHRIMM_PRED::from(bits),
        ))
    }
}
impl InsnOpcode for LSR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_SHRIMM_PRED {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LSR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "lsr",
        aliases: &[],
        opcode: 0x4118000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_5,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_5,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::LSR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(
            LSR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5::from(bits),
        ))
    }
}
impl InsnOpcode for LSR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LSR_SVE_Zd_S_B_SVE_Pg3_P_M_SVE_Zd_S_B_SVE_Zm_5_S_D {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "lsr",
        aliases: &[],
        opcode: 0x4198000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_BHS,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_5,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_D,
                    InsnOperandQualifier::S_D,
                    InsnOperandQualifier::S_D,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_5,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHS(
            SVE_SIZE_BHS::LSR_SVE_Zd_S_B_SVE_Pg3_P_M_SVE_Zd_S_B_SVE_Zm_5_S_D(
                LSR_SVE_Zd_S_B_SVE_Pg3_P_M_SVE_Zd_S_B_SVE_Zm_5_S_D::from(bits),
            ),
        )
    }
}
impl InsnOpcode for LSR_SVE_Zd_S_B_SVE_Pg3_P_M_SVE_Zd_S_B_SVE_Zm_5_S_D {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LSR_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "lsr",
        aliases: &[],
        opcode: 0x4208400,
        mask: 0xff20fc00,
        class: InsnClass::SVE_SIZE_BHS,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHS(SVE_SIZE_BHS::LSR_SVE_Zd_SVE_Zn_SVE_Zm_16(
            LSR_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for LSR_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LSR_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "lsr",
        aliases: &[],
        opcode: 0x4209400,
        mask: 0xff20fc00,
        class: InsnClass::SVE_SHIFT_UNPRED,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_SHRIMM_UNPRED,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_tszh,
                        lsb: 22,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm5,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SHIFT_UNPRED(SVE_SHIFT_UNPRED::LSR_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED(
            LSR_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED::from(bits),
        ))
    }
}
impl InsnOpcode for LSR_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LSRR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "lsrr",
        aliases: &[],
        opcode: 0x4158000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_5,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_5,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::LSRR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(
            LSRR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5::from(bits),
        ))
    }
}
impl InsnOpcode for LSRR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LSRV_Rd_Rn_Rm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "lsrv",
        aliases: &[],
        opcode: 0x1ac02400,
        mask: 0x7fe0fc00,
        class: InsnClass::DP_2SRC,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rm,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_ALIAS.bits() | InsnFlags::HAS_SF_FIELD.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::DP_2SRC(DP_2SRC::LSRV_Rd_Rn_Rm(LSRV_Rd_Rn_Rm::from(bits)))
    }
}
impl InsnOpcode for LSRV_Rd_Rn_Rm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LUTI2_SME_Zdnx4_SME_ZT0_SME_Zn_INDEX2_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "luti2",
        aliases: &[],
        opcode: 0xc08c8000,
        mask: 0xfffccc03,
        class: InsnClass::SME_SIZE_12_BHS,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn4,
                    lsb: 2,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_ZT0,
                class: InsnOperandClass::SYSTEM,
                qualifiers: &[],
                bit_fields: &[],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zn_INDEX2_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_16,
                        lsb: 16,
                        width: 2,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_SIZE_12_BHS(SME_SIZE_12_BHS::LUTI2_SME_Zdnx4_SME_ZT0_SME_Zn_INDEX2_16(
            LUTI2_SME_Zdnx4_SME_ZT0_SME_Zn_INDEX2_16::from(bits),
        ))
    }
}
impl InsnOpcode for LUTI2_SME_Zdnx4_SME_ZT0_SME_Zn_INDEX2_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LUTI2_SME_Zdnx2_SME_ZT0_SME_Zn_INDEX3_15 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "luti2",
        aliases: &[],
        opcode: 0xc08c4000,
        mask: 0xfffc4c01,
        class: InsnClass::SME_SIZE_12_BHS,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn2,
                    lsb: 1,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_ZT0,
                class: InsnOperandClass::SYSTEM,
                qualifiers: &[],
                bit_fields: &[],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zn_INDEX3_15,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_15,
                        lsb: 15,
                        width: 3,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_SIZE_12_BHS(SME_SIZE_12_BHS::LUTI2_SME_Zdnx2_SME_ZT0_SME_Zn_INDEX3_15(
            LUTI2_SME_Zdnx2_SME_ZT0_SME_Zn_INDEX3_15::from(bits),
        ))
    }
}
impl InsnOpcode for LUTI2_SME_Zdnx2_SME_ZT0_SME_Zn_INDEX3_15 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LUTI2_SVE_Zd_SME_ZT0_SME_Zn_INDEX4_14 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "luti2",
        aliases: &[],
        opcode: 0xc0cc0000,
        mask: 0xfffc0c00,
        class: InsnClass::SME_SIZE_12_BHS,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_ZT0,
                class: InsnOperandClass::SYSTEM,
                qualifiers: &[],
                bit_fields: &[],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zn_INDEX4_14,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm4_14,
                        lsb: 14,
                        width: 4,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_SIZE_12_BHS(SME_SIZE_12_BHS::LUTI2_SVE_Zd_SME_ZT0_SME_Zn_INDEX4_14(
            LUTI2_SVE_Zd_SME_ZT0_SME_Zn_INDEX4_14::from(bits),
        ))
    }
}
impl InsnOpcode for LUTI2_SVE_Zd_SME_ZT0_SME_Zn_INDEX4_14 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LUTI4_SME_Zdnx4_SME_ZT0_SME_Zn_INDEX1_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "luti4",
        aliases: &[],
        opcode: 0xc08a8000,
        mask: 0xfffecc03,
        class: InsnClass::SME_SIZE_12_HS,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn4,
                    lsb: 2,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_ZT0,
                class: InsnOperandClass::SYSTEM,
                qualifiers: &[],
                bit_fields: &[],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zn_INDEX1_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm1_16,
                        lsb: 16,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_SIZE_12_HS(SME_SIZE_12_HS::LUTI4_SME_Zdnx4_SME_ZT0_SME_Zn_INDEX1_16(
            LUTI4_SME_Zdnx4_SME_ZT0_SME_Zn_INDEX1_16::from(bits),
        ))
    }
}
impl InsnOpcode for LUTI4_SME_Zdnx4_SME_ZT0_SME_Zn_INDEX1_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LUTI4_SME_Zdnx2_SME_ZT0_SME_Zn_INDEX2_15 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "luti4",
        aliases: &[],
        opcode: 0xc08a4000,
        mask: 0xfffe4c01,
        class: InsnClass::SME_SIZE_12_BHS,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn2,
                    lsb: 1,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_ZT0,
                class: InsnOperandClass::SYSTEM,
                qualifiers: &[],
                bit_fields: &[],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zn_INDEX2_15,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_15,
                        lsb: 15,
                        width: 2,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_SIZE_12_BHS(SME_SIZE_12_BHS::LUTI4_SME_Zdnx2_SME_ZT0_SME_Zn_INDEX2_15(
            LUTI4_SME_Zdnx2_SME_ZT0_SME_Zn_INDEX2_15::from(bits),
        ))
    }
}
impl InsnOpcode for LUTI4_SME_Zdnx2_SME_ZT0_SME_Zn_INDEX2_15 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl LUTI4_SVE_Zd_SME_ZT0_SME_Zn_INDEX3_14 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "luti4",
        aliases: &[],
        opcode: 0xc0ca0000,
        mask: 0xfffe0c00,
        class: InsnClass::SME_SIZE_12_BHS,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_ZT0,
                class: InsnOperandClass::SYSTEM,
                qualifiers: &[],
                bit_fields: &[],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zn_INDEX3_14,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_14,
                        lsb: 14,
                        width: 3,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_SIZE_12_BHS(SME_SIZE_12_BHS::LUTI4_SVE_Zd_SME_ZT0_SME_Zn_INDEX3_14(
            LUTI4_SVE_Zd_SME_ZT0_SME_Zn_INDEX3_14::from(bits),
        ))
    }
}
impl InsnOpcode for LUTI4_SVE_Zd_SME_ZT0_SME_Zn_INDEX3_14 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl MAD_SVE_Zd_SVE_Pg3_SVE_Zm_16_SVE_Za_5 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "mad",
        aliases: &[],
        opcode: 0x400c000,
        mask: 0xff20e000,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Za_5,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Za_5,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::MAD_SVE_Zd_SVE_Pg3_SVE_Zm_16_SVE_Za_5(
            MAD_SVE_Zd_SVE_Pg3_SVE_Zm_16_SVE_Za_5::from(bits),
        ))
    }
}
impl InsnOpcode for MAD_SVE_Zd_SVE_Pg3_SVE_Zm_16_SVE_Za_5 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl MADD_Rd_Rn_Rm_Ra {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "madd",
        aliases: &[],
        opcode: 0x1b000000,
        mask: 0x7fe08000,
        class: InsnClass::DP_3SRC,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rm,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Ra,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Ra,
                    lsb: 10,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_ALIAS.bits() | InsnFlags::HAS_SF_FIELD.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::DP_3SRC(DP_3SRC::MADD_Rd_Rn_Rm_Ra(MADD_Rd_Rn_Rm_Ra::from(bits)))
    }
}
impl InsnOpcode for MADD_Rd_Rn_Rm_Ra {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl MATCH_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "match",
        aliases: &[],
        opcode: 0x45208000,
        mask: 0xffa0e010,
        class: InsnClass::SVE_SIZE_BH,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Pd,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pd,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z, InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BH(SVE_SIZE_BH::MATCH_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16(
            MATCH_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for MATCH_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl MLA_SVE_Zd_SVE_Zn_SVE_Zm3_22_INDEX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "mla",
        aliases: &[],
        opcode: 0x44200800,
        mask: 0xffa0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm3_22_INDEX,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_i3h,
                        lsb: 22,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zm_16,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::MLA_SVE_Zd_SVE_Zn_SVE_Zm3_22_INDEX(
            MLA_SVE_Zd_SVE_Zn_SVE_Zm3_22_INDEX::from(bits),
        ))
    }
}
impl InsnOpcode for MLA_SVE_Zd_SVE_Zn_SVE_Zm3_22_INDEX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl MLA_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "mla",
        aliases: &[],
        opcode: 0x44a00800,
        mask: 0xffe0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm3_INDEX,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::MLA_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX(
            MLA_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX::from(bits),
        ))
    }
}
impl InsnOpcode for MLA_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl MLA_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "mla",
        aliases: &[],
        opcode: 0x44e00800,
        mask: 0xffe0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm4_INDEX,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::MLA_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX(
            MLA_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX::from(bits),
        ))
    }
}
impl InsnOpcode for MLA_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl MLA_SVE_Zd_SVE_Pg3_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "mla",
        aliases: &[],
        opcode: 0x4004000,
        mask: 0xff20e000,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::MLA_SVE_Zd_SVE_Pg3_SVE_Zn_SVE_Zm_16(
            MLA_SVE_Zd_SVE_Pg3_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for MLA_SVE_Zd_SVE_Pg3_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl MLA_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "mla",
        aliases: &[],
        opcode: 0xe209400,
        mask: 0xbf20fc00,
        class: InsnClass::ASIMDSAME,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSAME(ASIMDSAME::MLA_Vd_Vn_Vm(MLA_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for MLA_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl MLA_Vd_Vn_Em16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "mla",
        aliases: &[],
        opcode: 0x2f000000,
        mask: 0xbf00f400,
        class: InsnClass::ASIMDELEM,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Em16,
                class: InsnOperandClass::SIMD_ELEMENT,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDELEM(ASIMDELEM::MLA_Vd_Vn_Em16(MLA_Vd_Vn_Em16::from(bits)))
    }
}
impl InsnOpcode for MLA_Vd_Vn_Em16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl MLS_SVE_Zd_SVE_Zn_SVE_Zm3_22_INDEX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "mls",
        aliases: &[],
        opcode: 0x44200c00,
        mask: 0xffa0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm3_22_INDEX,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_i3h,
                        lsb: 22,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zm_16,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::MLS_SVE_Zd_SVE_Zn_SVE_Zm3_22_INDEX(
            MLS_SVE_Zd_SVE_Zn_SVE_Zm3_22_INDEX::from(bits),
        ))
    }
}
impl InsnOpcode for MLS_SVE_Zd_SVE_Zn_SVE_Zm3_22_INDEX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl MLS_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "mls",
        aliases: &[],
        opcode: 0x44a00c00,
        mask: 0xffe0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm3_INDEX,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::MLS_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX(
            MLS_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX::from(bits),
        ))
    }
}
impl InsnOpcode for MLS_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl MLS_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "mls",
        aliases: &[],
        opcode: 0x44e00c00,
        mask: 0xffe0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm4_INDEX,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::MLS_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX(
            MLS_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX::from(bits),
        ))
    }
}
impl InsnOpcode for MLS_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl MLS_SVE_Zd_SVE_Pg3_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "mls",
        aliases: &[],
        opcode: 0x4006000,
        mask: 0xff20e000,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::MLS_SVE_Zd_SVE_Pg3_SVE_Zn_SVE_Zm_16(
            MLS_SVE_Zd_SVE_Pg3_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for MLS_SVE_Zd_SVE_Pg3_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl MLS_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "mls",
        aliases: &[],
        opcode: 0x2e209400,
        mask: 0xbf20fc00,
        class: InsnClass::ASIMDSAME,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSAME(ASIMDSAME::MLS_Vd_Vn_Vm(MLS_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for MLS_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl MLS_Vd_Vn_Em16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "mls",
        aliases: &[],
        opcode: 0x2f004000,
        mask: 0xbf00f400,
        class: InsnClass::ASIMDELEM,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Em16,
                class: InsnOperandClass::SIMD_ELEMENT,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDELEM(ASIMDELEM::MLS_Vd_Vn_Em16(MLS_Vd_Vn_Em16::from(bits)))
    }
}
impl InsnOpcode for MLS_Vd_Vn_Em16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl MOV_SME_ZA_HV_idx_dest_SVE_Pg3_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "mov",
        aliases: &[],
        opcode: 0xc0000000,
        mask: 0xff3e0010,
        class: InsnClass::SME_MOV,
        feature_set: InsnFeatureSet::SME,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_HV_idx_dest,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_size_22,
                        lsb: 22,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Q,
                        lsb: 16,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_V,
                        lsb: 15,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm4_0,
                        lsb: 0,
                        width: 4,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M, InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MOV(SME_MOV::MOV_SME_ZA_HV_idx_dest_SVE_Pg3_SVE_Zn(
            MOV_SME_ZA_HV_idx_dest_SVE_Pg3_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for MOV_SME_ZA_HV_idx_dest_SVE_Pg3_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl MOV_SVE_Zd_SVE_Pg3_SME_ZA_HV_idx_src {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "mov",
        aliases: &[],
        opcode: 0xc0020000,
        mask: 0xff3e0200,
        class: InsnClass::SME_MOV,
        feature_set: InsnFeatureSet::SME,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M, InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_HV_idx_src,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_size_22,
                        lsb: 22,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Q,
                        lsb: 16,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_V,
                        lsb: 15,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm4_5,
                        lsb: 5,
                        width: 4,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MOV(SME_MOV::MOV_SVE_Zd_SVE_Pg3_SME_ZA_HV_idx_src(
            MOV_SVE_Zd_SVE_Pg3_SME_ZA_HV_idx_src::from(bits),
        ))
    }
}
impl InsnOpcode for MOV_SVE_Zd_SVE_Pg3_SME_ZA_HV_idx_src {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl MOV_SME_ZA_HV_idx_destxN_SME_Znx2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "mov",
        aliases: &[],
        opcode: 0xc0040000,
        mask: 0xff3f1c38,
        class: InsnClass::SME_SIZE_22,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_HV_idx_destxN,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_V,
                        lsb: 15,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_0,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn2,
                    lsb: 6,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_SIZE_22(SME_SIZE_22::MOV_SME_ZA_HV_idx_destxN_SME_Znx2(
            MOV_SME_ZA_HV_idx_destxN_SME_Znx2::from(bits),
        ))
    }
}
impl InsnOpcode for MOV_SME_ZA_HV_idx_destxN_SME_Znx2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl MOV_SME_Zdnx2_SME_ZA_HV_idx_srcxN {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "mov",
        aliases: &[],
        opcode: 0xc0060000,
        mask: 0xff3f1f01,
        class: InsnClass::SME_SIZE_22,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn2,
                    lsb: 1,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_HV_idx_srcxN,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_V,
                        lsb: 15,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_5,
                        lsb: 5,
                        width: 3,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_SIZE_22(SME_SIZE_22::MOV_SME_Zdnx2_SME_ZA_HV_idx_srcxN(
            MOV_SME_Zdnx2_SME_ZA_HV_idx_srcxN::from(bits),
        ))
    }
}
impl InsnOpcode for MOV_SME_Zdnx2_SME_ZA_HV_idx_srcxN {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl MOV_SME_ZA_array_off3_0_SME_Znx2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "mov",
        aliases: &[],
        opcode: 0xc0040800,
        mask: 0xffff9c38,
        class: InsnClass::SME2_MOV,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off3_0,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_0,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn2,
                    lsb: 6,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME2_MOV(SME2_MOV::MOV_SME_ZA_array_off3_0_SME_Znx2(
            MOV_SME_ZA_array_off3_0_SME_Znx2::from(bits),
        ))
    }
}
impl InsnOpcode for MOV_SME_ZA_array_off3_0_SME_Znx2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl MOV_SME_Zdnx2_SME_ZA_array_off3_5 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "mov",
        aliases: &[],
        opcode: 0xc0060800,
        mask: 0xffff9f01,
        class: InsnClass::SME2_MOV,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn2,
                    lsb: 1,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off3_5,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_5,
                        lsb: 5,
                        width: 3,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME2_MOV(SME2_MOV::MOV_SME_Zdnx2_SME_ZA_array_off3_5(
            MOV_SME_Zdnx2_SME_ZA_array_off3_5::from(bits),
        ))
    }
}
impl InsnOpcode for MOV_SME_Zdnx2_SME_ZA_array_off3_5 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl MOV_SME_ZA_HV_idx_destxN_SME_Znx4 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "mov",
        aliases: &[],
        opcode: 0xc0040400,
        mask: 0xff3f1c78,
        class: InsnClass::SME_SIZE_22,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_HV_idx_destxN,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_V,
                        lsb: 15,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_0,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn4,
                    lsb: 7,
                    width: 3,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_4.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_SIZE_22(SME_SIZE_22::MOV_SME_ZA_HV_idx_destxN_SME_Znx4(
            MOV_SME_ZA_HV_idx_destxN_SME_Znx4::from(bits),
        ))
    }
}
impl InsnOpcode for MOV_SME_ZA_HV_idx_destxN_SME_Znx4 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl MOV_SME_Zdnx4_SME_ZA_HV_idx_srcxN {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "mov",
        aliases: &[],
        opcode: 0xc0060400,
        mask: 0xff3f1f03,
        class: InsnClass::SME_SIZE_22,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn4,
                    lsb: 2,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_HV_idx_srcxN,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_V,
                        lsb: 15,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_5,
                        lsb: 5,
                        width: 3,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_4.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_SIZE_22(SME_SIZE_22::MOV_SME_Zdnx4_SME_ZA_HV_idx_srcxN(
            MOV_SME_Zdnx4_SME_ZA_HV_idx_srcxN::from(bits),
        ))
    }
}
impl InsnOpcode for MOV_SME_Zdnx4_SME_ZA_HV_idx_srcxN {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl MOV_SME_ZA_array_off3_0_SME_Znx4 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "mov",
        aliases: &[],
        opcode: 0xc0040c00,
        mask: 0xffff9c78,
        class: InsnClass::SME2_MOV,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off3_0,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_0,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn4,
                    lsb: 7,
                    width: 3,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_4.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME2_MOV(SME2_MOV::MOV_SME_ZA_array_off3_0_SME_Znx4(
            MOV_SME_ZA_array_off3_0_SME_Znx4::from(bits),
        ))
    }
}
impl InsnOpcode for MOV_SME_ZA_array_off3_0_SME_Znx4 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl MOV_SME_Zdnx4_SME_ZA_array_off3_5 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "mov",
        aliases: &[],
        opcode: 0xc0060c00,
        mask: 0xffff9f03,
        class: InsnClass::SME2_MOV,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn4,
                    lsb: 2,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off3_5,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_5,
                        lsb: 5,
                        width: 3,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_4.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME2_MOV(SME2_MOV::MOV_SME_Zdnx4_SME_ZA_array_off3_5(
            MOV_SME_Zdnx4_SME_ZA_array_off3_5::from(bits),
        ))
    }
}
impl InsnOpcode for MOV_SME_Zdnx4_SME_ZA_array_off3_5 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl MOVA_SME_ZA_HV_idx_dest_SVE_Pg3_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "mova",
        aliases: &[],
        opcode: 0xc0000000,
        mask: 0xff3e0010,
        class: InsnClass::SME_MOV,
        feature_set: InsnFeatureSet::SME,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_HV_idx_dest,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_size_22,
                        lsb: 22,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Q,
                        lsb: 16,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_V,
                        lsb: 15,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm4_0,
                        lsb: 0,
                        width: 4,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M, InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MOV(SME_MOV::MOVA_SME_ZA_HV_idx_dest_SVE_Pg3_SVE_Zn(
            MOVA_SME_ZA_HV_idx_dest_SVE_Pg3_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for MOVA_SME_ZA_HV_idx_dest_SVE_Pg3_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl MOVA_SVE_Zd_SVE_Pg3_SME_ZA_HV_idx_src {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "mova",
        aliases: &[],
        opcode: 0xc0020000,
        mask: 0xff3e0200,
        class: InsnClass::SME_MOV,
        feature_set: InsnFeatureSet::SME,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M, InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_HV_idx_src,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_size_22,
                        lsb: 22,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Q,
                        lsb: 16,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_V,
                        lsb: 15,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm4_5,
                        lsb: 5,
                        width: 4,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MOV(SME_MOV::MOVA_SVE_Zd_SVE_Pg3_SME_ZA_HV_idx_src(
            MOVA_SVE_Zd_SVE_Pg3_SME_ZA_HV_idx_src::from(bits),
        ))
    }
}
impl InsnOpcode for MOVA_SVE_Zd_SVE_Pg3_SME_ZA_HV_idx_src {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl MOVA_SME_ZA_HV_idx_destxN_SME_Znx2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "mova",
        aliases: &[],
        opcode: 0xc0040000,
        mask: 0xff3f1c38,
        class: InsnClass::SME_SIZE_22,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_HV_idx_destxN,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_V,
                        lsb: 15,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_0,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn2,
                    lsb: 6,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_SIZE_22(SME_SIZE_22::MOVA_SME_ZA_HV_idx_destxN_SME_Znx2(
            MOVA_SME_ZA_HV_idx_destxN_SME_Znx2::from(bits),
        ))
    }
}
impl InsnOpcode for MOVA_SME_ZA_HV_idx_destxN_SME_Znx2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl MOVA_SME_Zdnx2_SME_ZA_HV_idx_srcxN {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "mova",
        aliases: &[],
        opcode: 0xc0060000,
        mask: 0xff3f1f01,
        class: InsnClass::SME_SIZE_22,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn2,
                    lsb: 1,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_HV_idx_srcxN,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_V,
                        lsb: 15,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_5,
                        lsb: 5,
                        width: 3,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_SIZE_22(SME_SIZE_22::MOVA_SME_Zdnx2_SME_ZA_HV_idx_srcxN(
            MOVA_SME_Zdnx2_SME_ZA_HV_idx_srcxN::from(bits),
        ))
    }
}
impl InsnOpcode for MOVA_SME_Zdnx2_SME_ZA_HV_idx_srcxN {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl MOVA_SME_ZA_array_off3_0_SME_Znx2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "mova",
        aliases: &[],
        opcode: 0xc0040800,
        mask: 0xffff9c38,
        class: InsnClass::SME2_MOV,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off3_0,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_0,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn2,
                    lsb: 6,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME2_MOV(SME2_MOV::MOVA_SME_ZA_array_off3_0_SME_Znx2(
            MOVA_SME_ZA_array_off3_0_SME_Znx2::from(bits),
        ))
    }
}
impl InsnOpcode for MOVA_SME_ZA_array_off3_0_SME_Znx2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl MOVA_SME_Zdnx2_SME_ZA_array_off3_5 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "mova",
        aliases: &[],
        opcode: 0xc0060800,
        mask: 0xffff9f01,
        class: InsnClass::SME2_MOV,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn2,
                    lsb: 1,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off3_5,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_5,
                        lsb: 5,
                        width: 3,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME2_MOV(SME2_MOV::MOVA_SME_Zdnx2_SME_ZA_array_off3_5(
            MOVA_SME_Zdnx2_SME_ZA_array_off3_5::from(bits),
        ))
    }
}
impl InsnOpcode for MOVA_SME_Zdnx2_SME_ZA_array_off3_5 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl MOVA_SME_ZA_HV_idx_destxN_SME_Znx4 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "mova",
        aliases: &[],
        opcode: 0xc0040400,
        mask: 0xff3f1c78,
        class: InsnClass::SME_SIZE_22,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_HV_idx_destxN,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_V,
                        lsb: 15,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_0,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn4,
                    lsb: 7,
                    width: 3,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_4.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_SIZE_22(SME_SIZE_22::MOVA_SME_ZA_HV_idx_destxN_SME_Znx4(
            MOVA_SME_ZA_HV_idx_destxN_SME_Znx4::from(bits),
        ))
    }
}
impl InsnOpcode for MOVA_SME_ZA_HV_idx_destxN_SME_Znx4 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl MOVA_SME_Zdnx4_SME_ZA_HV_idx_srcxN {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "mova",
        aliases: &[],
        opcode: 0xc0060400,
        mask: 0xff3f1f03,
        class: InsnClass::SME_SIZE_22,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn4,
                    lsb: 2,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_HV_idx_srcxN,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_V,
                        lsb: 15,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_5,
                        lsb: 5,
                        width: 3,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_4.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_SIZE_22(SME_SIZE_22::MOVA_SME_Zdnx4_SME_ZA_HV_idx_srcxN(
            MOVA_SME_Zdnx4_SME_ZA_HV_idx_srcxN::from(bits),
        ))
    }
}
impl InsnOpcode for MOVA_SME_Zdnx4_SME_ZA_HV_idx_srcxN {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl MOVA_SME_ZA_array_off3_0_SME_Znx4 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "mova",
        aliases: &[],
        opcode: 0xc0040c00,
        mask: 0xffff9c78,
        class: InsnClass::SME2_MOV,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off3_0,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_0,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn4,
                    lsb: 7,
                    width: 3,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_4.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME2_MOV(SME2_MOV::MOVA_SME_ZA_array_off3_0_SME_Znx4(
            MOVA_SME_ZA_array_off3_0_SME_Znx4::from(bits),
        ))
    }
}
impl InsnOpcode for MOVA_SME_ZA_array_off3_0_SME_Znx4 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl MOVA_SME_Zdnx4_SME_ZA_array_off3_5 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "mova",
        aliases: &[],
        opcode: 0xc0060c00,
        mask: 0xffff9f03,
        class: InsnClass::SME2_MOV,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn4,
                    lsb: 2,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off3_5,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_5,
                        lsb: 5,
                        width: 3,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_4.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME2_MOV(SME2_MOV::MOVA_SME_Zdnx4_SME_ZA_array_off3_5(
            MOVA_SME_Zdnx4_SME_ZA_array_off3_5::from(bits),
        ))
    }
}
impl InsnOpcode for MOVA_SME_Zdnx4_SME_ZA_array_off3_5 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl MOVAZ_SME_Zdnx2_SME_ZA_array_vrsb_1 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "movaz",
        aliases: &[],
        opcode: 0xc0060200,
        mask: 0xffff1f01,
        class: InsnClass::SME2_MOVAZ,
        feature_set: InsnFeatureSet::SME2P1,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn2,
                    lsb: 1,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_vrsb_1,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_V,
                        lsb: 15,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::off3,
                        lsb: 5,
                        width: 3,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME2_MOVAZ(SME2_MOVAZ::MOVAZ_SME_Zdnx2_SME_ZA_array_vrsb_1(
            MOVAZ_SME_Zdnx2_SME_ZA_array_vrsb_1::from(bits),
        ))
    }
}
impl InsnOpcode for MOVAZ_SME_Zdnx2_SME_ZA_array_vrsb_1 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl MOVAZ_SME_Zdnx2_SME_ZA_array_vrss_1 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "movaz",
        aliases: &[],
        opcode: 0xc0860200,
        mask: 0xffff1f01,
        class: InsnClass::SME2_MOVAZ,
        feature_set: InsnFeatureSet::SME2P1,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn2,
                    lsb: 1,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_vrss_1,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_V,
                        lsb: 15,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::ZAn_2,
                        lsb: 6,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::ol,
                        lsb: 5,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME2_MOVAZ(SME2_MOVAZ::MOVAZ_SME_Zdnx2_SME_ZA_array_vrss_1(
            MOVAZ_SME_Zdnx2_SME_ZA_array_vrss_1::from(bits),
        ))
    }
}
impl InsnOpcode for MOVAZ_SME_Zdnx2_SME_ZA_array_vrss_1 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl MOVAZ_SME_Zdnx2_SME_ZA_array_vrsh_1 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "movaz",
        aliases: &[],
        opcode: 0xc0460200,
        mask: 0xffff1f01,
        class: InsnClass::SME2_MOVAZ,
        feature_set: InsnFeatureSet::SME2P1,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn2,
                    lsb: 1,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_vrsh_1,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_V,
                        lsb: 15,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::ZAn_1,
                        lsb: 7,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::off2,
                        lsb: 5,
                        width: 2,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME2_MOVAZ(SME2_MOVAZ::MOVAZ_SME_Zdnx2_SME_ZA_array_vrsh_1(
            MOVAZ_SME_Zdnx2_SME_ZA_array_vrsh_1::from(bits),
        ))
    }
}
impl InsnOpcode for MOVAZ_SME_Zdnx2_SME_ZA_array_vrsh_1 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl MOVAZ_SME_Zdnx2_SME_ZA_array_vrsd_1 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "movaz",
        aliases: &[],
        opcode: 0xc0c60200,
        mask: 0xffff1f01,
        class: InsnClass::SME2_MOVAZ,
        feature_set: InsnFeatureSet::SME2P1,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn2,
                    lsb: 1,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_vrsd_1,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_V,
                        lsb: 15,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::ZAn_3,
                        lsb: 5,
                        width: 3,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME2_MOVAZ(SME2_MOVAZ::MOVAZ_SME_Zdnx2_SME_ZA_array_vrsd_1(
            MOVAZ_SME_Zdnx2_SME_ZA_array_vrsd_1::from(bits),
        ))
    }
}
impl InsnOpcode for MOVAZ_SME_Zdnx2_SME_ZA_array_vrsd_1 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl MOVAZ_SME_Zdnx4_SME_ZA_array_vrsb_2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "movaz",
        aliases: &[],
        opcode: 0xc0060600,
        mask: 0xffff1f83,
        class: InsnClass::SME2_MOVAZ,
        feature_set: InsnFeatureSet::SME2P1,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn4,
                    lsb: 2,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_vrsb_2,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_V,
                        lsb: 15,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::off2,
                        lsb: 5,
                        width: 2,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME2_MOVAZ(SME2_MOVAZ::MOVAZ_SME_Zdnx4_SME_ZA_array_vrsb_2(
            MOVAZ_SME_Zdnx4_SME_ZA_array_vrsb_2::from(bits),
        ))
    }
}
impl InsnOpcode for MOVAZ_SME_Zdnx4_SME_ZA_array_vrsb_2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl MOVAZ_SME_Zdnx4_SME_ZA_array_vrss_2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "movaz",
        aliases: &[],
        opcode: 0xc0860600,
        mask: 0xffff1f83,
        class: InsnClass::SME2_MOVAZ,
        feature_set: InsnFeatureSet::SME2P1,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn4,
                    lsb: 2,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_vrss_2,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_V,
                        lsb: 15,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::off2,
                        lsb: 5,
                        width: 2,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME2_MOVAZ(SME2_MOVAZ::MOVAZ_SME_Zdnx4_SME_ZA_array_vrss_2(
            MOVAZ_SME_Zdnx4_SME_ZA_array_vrss_2::from(bits),
        ))
    }
}
impl InsnOpcode for MOVAZ_SME_Zdnx4_SME_ZA_array_vrss_2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl MOVAZ_SME_Zdnx4_SME_ZA_array_vrsh_2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "movaz",
        aliases: &[],
        opcode: 0xc0460600,
        mask: 0xffff1f83,
        class: InsnClass::SME2_MOVAZ,
        feature_set: InsnFeatureSet::SME2P1,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn4,
                    lsb: 2,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_vrsh_2,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_V,
                        lsb: 15,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::ZAn,
                        lsb: 6,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::ol,
                        lsb: 5,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME2_MOVAZ(SME2_MOVAZ::MOVAZ_SME_Zdnx4_SME_ZA_array_vrsh_2(
            MOVAZ_SME_Zdnx4_SME_ZA_array_vrsh_2::from(bits),
        ))
    }
}
impl InsnOpcode for MOVAZ_SME_Zdnx4_SME_ZA_array_vrsh_2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl MOVAZ_SME_Zdnx4_SME_ZA_array_vrsd_2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "movaz",
        aliases: &[],
        opcode: 0xc0c60600,
        mask: 0xffff1f03,
        class: InsnClass::SME2_MOVAZ,
        feature_set: InsnFeatureSet::SME2P1,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn4,
                    lsb: 2,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_vrsd_2,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_V,
                        lsb: 15,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::ZAn_3,
                        lsb: 5,
                        width: 3,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME2_MOVAZ(SME2_MOVAZ::MOVAZ_SME_Zdnx4_SME_ZA_array_vrsd_2(
            MOVAZ_SME_Zdnx4_SME_ZA_array_vrsd_2::from(bits),
        ))
    }
}
impl InsnOpcode for MOVAZ_SME_Zdnx4_SME_ZA_array_vrsd_2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl MOVI_Vd_SIMD_IMM_SFT {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "movi",
        aliases: &[],
        opcode: 0xf000400,
        mask: 0xbff89c00,
        class: InsnClass::ASIMDIMM,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SIMD_IMM_SFT,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[InsnOperandQualifier::LSL],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDIMM(ASIMDIMM::MOVI_Vd_SIMD_IMM_SFT(MOVI_Vd_SIMD_IMM_SFT::from(
            bits,
        )))
    }
}
impl InsnOpcode for MOVI_Vd_SIMD_IMM_SFT {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl MOVI_Vd_V_4H_SIMD_IMM_SFT_LSL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "movi",
        aliases: &[],
        opcode: 0xf008400,
        mask: 0xbff8dc00,
        class: InsnClass::ASIMDIMM,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SIMD_IMM_SFT,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[InsnOperandQualifier::LSL],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDIMM(ASIMDIMM::MOVI_Vd_V_4H_SIMD_IMM_SFT_LSL(
            MOVI_Vd_V_4H_SIMD_IMM_SFT_LSL::from(bits),
        ))
    }
}
impl InsnOpcode for MOVI_Vd_V_4H_SIMD_IMM_SFT_LSL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl MOVI_Vd_V_2S_SIMD_IMM_SFT_MSL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "movi",
        aliases: &[],
        opcode: 0xf00c400,
        mask: 0xbff8ec00,
        class: InsnClass::ASIMDIMM,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SIMD_IMM_SFT,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[InsnOperandQualifier::MSL],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDIMM(ASIMDIMM::MOVI_Vd_V_2S_SIMD_IMM_SFT_MSL(
            MOVI_Vd_V_2S_SIMD_IMM_SFT_MSL::from(bits),
        ))
    }
}
impl InsnOpcode for MOVI_Vd_V_2S_SIMD_IMM_SFT_MSL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl MOVI_Vd_V_8B_SIMD_IMM_SFT_LSL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "movi",
        aliases: &[],
        opcode: 0xf00e400,
        mask: 0xbff8fc00,
        class: InsnClass::ASIMDIMM,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SIMD_IMM_SFT,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[InsnOperandQualifier::LSL],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDIMM(ASIMDIMM::MOVI_Vd_V_8B_SIMD_IMM_SFT_LSL(
            MOVI_Vd_V_8B_SIMD_IMM_SFT_LSL::from(bits),
        ))
    }
}
impl InsnOpcode for MOVI_Vd_V_8B_SIMD_IMM_SFT_LSL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl MOVI_Sd_SIMD_IMM {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "movi",
        aliases: &[],
        opcode: 0x2f00e400,
        mask: 0xfff8fc00,
        class: InsnClass::ASIMDIMM,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SIMD_IMM,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDIMM(ASIMDIMM::MOVI_Sd_SIMD_IMM(MOVI_Sd_SIMD_IMM::from(bits)))
    }
}
impl InsnOpcode for MOVI_Sd_SIMD_IMM {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl MOVI_Vd_SIMD_IMM {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "movi",
        aliases: &[],
        opcode: 0x6f00e400,
        mask: 0xfff8fc00,
        class: InsnClass::ASIMDIMM,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SIMD_IMM,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDIMM(ASIMDIMM::MOVI_Vd_SIMD_IMM(MOVI_Vd_SIMD_IMM::from(bits)))
    }
}
impl InsnOpcode for MOVI_Vd_SIMD_IMM {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl MOVK_Rd_HALF {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "movk",
        aliases: &[],
        opcode: 0x72800000,
        mask: 0x7f800000,
        class: InsnClass::MOVEWIDE,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::HALF,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::imm16_5,
                    lsb: 5,
                    width: 16,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SF_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::MOVEWIDE(MOVEWIDE::MOVK_Rd_HALF(MOVK_Rd_HALF::from(bits)))
    }
}
impl InsnOpcode for MOVK_Rd_HALF {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl MOVN_Rd_HALF {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "movn",
        aliases: &[],
        opcode: 0x12800000,
        mask: 0x7f800000,
        class: InsnClass::MOVEWIDE,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::HALF,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::imm16_5,
                    lsb: 5,
                    width: 16,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_ALIAS.bits() | InsnFlags::HAS_SF_FIELD.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::MOVEWIDE(MOVEWIDE::MOVN_Rd_HALF(MOVN_Rd_HALF::from(bits)))
    }
}
impl InsnOpcode for MOVN_Rd_HALF {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl MOVPRFX_SVE_Zd_SVE_Pg3_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "movprfx",
        aliases: &[],
        opcode: 0x4102000,
        mask: 0xff3ee000,
        class: InsnClass::SVE_MOVPRFX,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z, InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::RESTRICTED_NEXT_INSN_SET.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MOVPRFX(SVE_MOVPRFX::MOVPRFX_SVE_Zd_SVE_Pg3_SVE_Zn(
            MOVPRFX_SVE_Zd_SVE_Pg3_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for MOVPRFX_SVE_Zd_SVE_Pg3_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl MOVPRFX_SVE_Zd_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "movprfx",
        aliases: &[],
        opcode: 0x420bc00,
        mask: 0xfffffc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::RESTRICTED_NEXT_INSN_SET.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::MOVPRFX_SVE_Zd_SVE_Zn(
            MOVPRFX_SVE_Zd_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for MOVPRFX_SVE_Zd_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl MOVT_Rt_SME_ZT0_INDEX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "movt",
        aliases: &[],
        opcode: 0xc04c03e0,
        mask: 0xffff8fe0,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_ZT0_INDEX,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::imm3_12,
                    lsb: 12,
                    width: 3,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::MOVT_Rt_SME_ZT0_INDEX(
            MOVT_Rt_SME_ZT0_INDEX::from(bits),
        ))
    }
}
impl InsnOpcode for MOVT_Rt_SME_ZT0_INDEX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl MOVT_SME_ZT0_INDEX_Rt {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "movt",
        aliases: &[],
        opcode: 0xc04e03e0,
        mask: 0xffff8fe0,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZT0_INDEX,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::imm3_12,
                    lsb: 12,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::MOVT_SME_ZT0_INDEX_Rt(
            MOVT_SME_ZT0_INDEX_Rt::from(bits),
        ))
    }
}
impl InsnOpcode for MOVT_SME_ZT0_INDEX_Rt {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl MOVZ_Rd_HALF {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "movz",
        aliases: &[],
        opcode: 0x52800000,
        mask: 0x7f800000,
        class: InsnClass::MOVEWIDE,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::HALF,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::imm16_5,
                    lsb: 5,
                    width: 16,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_ALIAS.bits() | InsnFlags::HAS_SF_FIELD.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::MOVEWIDE(MOVEWIDE::MOVZ_Rd_HALF(MOVZ_Rd_HALF::from(bits)))
    }
}
impl InsnOpcode for MOVZ_Rd_HALF {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl MRRS_Rt_PAIRREG_SYSREG128 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "mrrs",
        aliases: &[],
        opcode: 0xd5700000,
        mask: 0xfff00000,
        class: InsnClass::IC_SYSTEM,
        feature_set: InsnFeatureSet::D128,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::PAIRREG,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[],
            },
            InsnOperand {
                kind: InsnOperandKind::SYSREG128,
                class: InsnOperandClass::SYSTEM,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::IS_SYS_READ.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::IC_SYSTEM(IC_SYSTEM::MRRS_Rt_PAIRREG_SYSREG128(
            MRRS_Rt_PAIRREG_SYSREG128::from(bits),
        ))
    }
}
impl InsnOpcode for MRRS_Rt_PAIRREG_SYSREG128 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl MRS_Rt_SYSREG {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "mrs",
        aliases: &[],
        opcode: 0xd5200000,
        mask: 0xffe00000,
        class: InsnClass::IC_SYSTEM,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SYSREG,
                class: InsnOperandClass::SYSTEM,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::IS_SYS_READ.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::IC_SYSTEM(IC_SYSTEM::MRS_Rt_SYSREG(MRS_Rt_SYSREG::from(bits)))
    }
}
impl InsnOpcode for MRS_Rt_SYSREG {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl MSB_SVE_Zd_SVE_Pg3_SVE_Zm_16_SVE_Za_5 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "msb",
        aliases: &[],
        opcode: 0x400e000,
        mask: 0xff20e000,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Za_5,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Za_5,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::MSB_SVE_Zd_SVE_Pg3_SVE_Zm_16_SVE_Za_5(
            MSB_SVE_Zd_SVE_Pg3_SVE_Zm_16_SVE_Za_5::from(bits),
        ))
    }
}
impl InsnOpcode for MSB_SVE_Zd_SVE_Pg3_SVE_Zm_16_SVE_Za_5 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl MSR_PSTATEFIELD_UIMM4 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "msr",
        aliases: &[],
        opcode: 0xd500401f,
        mask: 0xfff8f01f,
        class: InsnClass::IC_SYSTEM,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::PSTATEFIELD,
                class: InsnOperandClass::SYSTEM,
                qualifiers: &[],
                bit_fields: &[],
            },
            InsnOperand {
                kind: InsnOperandKind::UIMM4,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::CRm,
                    lsb: 8,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::IS_SYS_WRITE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::IC_SYSTEM(IC_SYSTEM::MSR_PSTATEFIELD_UIMM4(
            MSR_PSTATEFIELD_UIMM4::from(bits),
        ))
    }
}
impl InsnOpcode for MSR_PSTATEFIELD_UIMM4 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl MSR_SYSREG_Rt {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "msr",
        aliases: &[],
        opcode: 0xd5000000,
        mask: 0xffe00000,
        class: InsnClass::IC_SYSTEM,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SYSREG,
                class: InsnOperandClass::SYSTEM,
                qualifiers: &[],
                bit_fields: &[],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::IS_SYS_WRITE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::IC_SYSTEM(IC_SYSTEM::MSR_SYSREG_Rt(MSR_SYSREG_Rt::from(bits)))
    }
}
impl InsnOpcode for MSR_SYSREG_Rt {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl MSRR_SYSREG128_Rt_PAIRREG {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "msrr",
        aliases: &[],
        opcode: 0xd5500000,
        mask: 0xfff00000,
        class: InsnClass::IC_SYSTEM,
        feature_set: InsnFeatureSet::D128,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SYSREG128,
                class: InsnOperandClass::SYSTEM,
                qualifiers: &[],
                bit_fields: &[],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::PAIRREG,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::IS_SYS_WRITE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::IC_SYSTEM(IC_SYSTEM::MSRR_SYSREG128_Rt_PAIRREG(
            MSRR_SYSREG128_Rt_PAIRREG::from(bits),
        ))
    }
}
impl InsnOpcode for MSRR_SYSREG128_Rt_PAIRREG {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl MSUB_Rd_Rn_Rm_Ra {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "msub",
        aliases: &[],
        opcode: 0x1b008000,
        mask: 0x7fe08000,
        class: InsnClass::DP_3SRC,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rm,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Ra,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Ra,
                    lsb: 10,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_ALIAS.bits() | InsnFlags::HAS_SF_FIELD.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::DP_3SRC(DP_3SRC::MSUB_Rd_Rn_Rm_Ra(MSUB_Rd_Rn_Rm_Ra::from(bits)))
    }
}
impl InsnOpcode for MSUB_Rd_Rn_Rm_Ra {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl MUL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "mul",
        aliases: &[],
        opcode: 0x4100000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_5,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_5,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::MUL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(
            MUL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5::from(bits),
        ))
    }
}
impl InsnOpcode for MUL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl MUL_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "mul",
        aliases: &[],
        opcode: 0x4206000,
        mask: 0xff20fc00,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::MUL_SVE_Zd_SVE_Zn_SVE_Zm_16(
            MUL_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for MUL_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl MUL_SVE_Zd_SVE_Zn_SVE_Zm3_22_INDEX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "mul",
        aliases: &[],
        opcode: 0x4420f800,
        mask: 0xffa0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm3_22_INDEX,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_i3h,
                        lsb: 22,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zm_16,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::MUL_SVE_Zd_SVE_Zn_SVE_Zm3_22_INDEX(
            MUL_SVE_Zd_SVE_Zn_SVE_Zm3_22_INDEX::from(bits),
        ))
    }
}
impl InsnOpcode for MUL_SVE_Zd_SVE_Zn_SVE_Zm3_22_INDEX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl MUL_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "mul",
        aliases: &[],
        opcode: 0x44a0f800,
        mask: 0xffe0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm3_INDEX,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::MUL_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX(
            MUL_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX::from(bits),
        ))
    }
}
impl InsnOpcode for MUL_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl MUL_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "mul",
        aliases: &[],
        opcode: 0x44e0f800,
        mask: 0xffe0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm4_INDEX,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::MUL_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX(
            MUL_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX::from(bits),
        ))
    }
}
impl InsnOpcode for MUL_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl MUL_SVE_Zd_SVE_Zd_SVE_SIMM8 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "mul",
        aliases: &[],
        opcode: 0x2530c000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_SIMM8,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_imm8,
                    lsb: 5,
                    width: 8,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::MUL_SVE_Zd_SVE_Zd_SVE_SIMM8(
            MUL_SVE_Zd_SVE_Zd_SVE_SIMM8::from(bits),
        ))
    }
}
impl InsnOpcode for MUL_SVE_Zd_SVE_Zd_SVE_SIMM8 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl MUL_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "mul",
        aliases: &[],
        opcode: 0xe209c00,
        mask: 0xbf20fc00,
        class: InsnClass::ASIMDSAME,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSAME(ASIMDSAME::MUL_Vd_Vn_Vm(MUL_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for MUL_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl MUL_Vd_Vn_Em16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "mul",
        aliases: &[],
        opcode: 0xf008000,
        mask: 0xbf00f400,
        class: InsnClass::ASIMDELEM,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Em16,
                class: InsnOperandClass::SIMD_ELEMENT,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDELEM(ASIMDELEM::MUL_Vd_Vn_Em16(MUL_Vd_Vn_Em16::from(bits)))
    }
}
impl InsnOpcode for MUL_Vd_Vn_Em16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl MVNI_Vd_SIMD_IMM_SFT {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "mvni",
        aliases: &[],
        opcode: 0x2f000400,
        mask: 0xbff89c00,
        class: InsnClass::ASIMDIMM,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SIMD_IMM_SFT,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[InsnOperandQualifier::LSL],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDIMM(ASIMDIMM::MVNI_Vd_SIMD_IMM_SFT(MVNI_Vd_SIMD_IMM_SFT::from(
            bits,
        )))
    }
}
impl InsnOpcode for MVNI_Vd_SIMD_IMM_SFT {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl MVNI_Vd_V_4H_SIMD_IMM_SFT_LSL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "mvni",
        aliases: &[],
        opcode: 0x2f008400,
        mask: 0xbff8dc00,
        class: InsnClass::ASIMDIMM,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SIMD_IMM_SFT,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[InsnOperandQualifier::LSL],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDIMM(ASIMDIMM::MVNI_Vd_V_4H_SIMD_IMM_SFT_LSL(
            MVNI_Vd_V_4H_SIMD_IMM_SFT_LSL::from(bits),
        ))
    }
}
impl InsnOpcode for MVNI_Vd_V_4H_SIMD_IMM_SFT_LSL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl MVNI_Vd_V_2S_SIMD_IMM_SFT_MSL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "mvni",
        aliases: &[],
        opcode: 0x2f00c400,
        mask: 0xbff8ec00,
        class: InsnClass::ASIMDIMM,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SIMD_IMM_SFT,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[InsnOperandQualifier::MSL],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDIMM(ASIMDIMM::MVNI_Vd_V_2S_SIMD_IMM_SFT_MSL(
            MVNI_Vd_V_2S_SIMD_IMM_SFT_MSL::from(bits),
        ))
    }
}
impl InsnOpcode for MVNI_Vd_V_2S_SIMD_IMM_SFT_MSL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl NAND_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "nand",
        aliases: &[],
        opcode: 0x25804210,
        mask: 0xfff0c210,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Pd,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pd,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg4_10,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg4_10,
                    lsb: 10,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pn,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pn,
                    lsb: 5,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pm,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pm,
                    lsb: 16,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::NAND_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm(
            NAND_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm::from(bits),
        ))
    }
}
impl InsnOpcode for NAND_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl NANDS_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "nands",
        aliases: &[],
        opcode: 0x25c04210,
        mask: 0xfff0c210,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Pd,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pd,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg4_10,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg4_10,
                    lsb: 10,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pn,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pn,
                    lsb: 5,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pm,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pm,
                    lsb: 16,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::NANDS_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm(
            NANDS_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm::from(bits),
        ))
    }
}
impl InsnOpcode for NANDS_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl NBSL_SVE_Zd_SVE_Zd_SVE_Zm_16_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "nbsl",
        aliases: &[],
        opcode: 0x4e03c00,
        mask: 0xffe0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::NBSL_SVE_Zd_SVE_Zd_SVE_Zm_16_SVE_Zn(
            NBSL_SVE_Zd_SVE_Zd_SVE_Zm_16_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for NBSL_SVE_Zd_SVE_Zd_SVE_Zm_16_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl NEG_SVE_Zd_SVE_Pg3_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "neg",
        aliases: &[],
        opcode: 0x417a000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M, InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::NEG_SVE_Zd_SVE_Pg3_SVE_Zn(
            NEG_SVE_Zd_SVE_Pg3_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for NEG_SVE_Zd_SVE_Pg3_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl NEG_Vd_Vn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "neg",
        aliases: &[],
        opcode: 0x2e20b800,
        mask: 0xbf3ffc00,
        class: InsnClass::ASIMDMISC,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDMISC(ASIMDMISC::NEG_Vd_Vn(NEG_Vd_Vn::from(bits)))
    }
}
impl InsnOpcode for NEG_Vd_Vn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl NEG_Sd_Sn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "neg",
        aliases: &[],
        opcode: 0x7e20b800,
        mask: 0xff3ffc00,
        class: InsnClass::ASISDMISC,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMD_SCALAR_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDMISC(ASISDMISC::NEG_Sd_Sn(NEG_Sd_Sn::from(bits)))
    }
}
impl InsnOpcode for NEG_Sd_Sn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl NMATCH_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "nmatch",
        aliases: &[],
        opcode: 0x45208010,
        mask: 0xffa0e010,
        class: InsnClass::SVE_SIZE_BH,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Pd,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pd,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z, InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BH(SVE_SIZE_BH::NMATCH_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16(
            NMATCH_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for NMATCH_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl NOR_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "nor",
        aliases: &[],
        opcode: 0x25804200,
        mask: 0xfff0c210,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Pd,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pd,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg4_10,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg4_10,
                    lsb: 10,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pn,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pn,
                    lsb: 5,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pm,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pm,
                    lsb: 16,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::NOR_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm(
            NOR_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm::from(bits),
        ))
    }
}
impl InsnOpcode for NOR_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl NORS_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "nors",
        aliases: &[],
        opcode: 0x25c04200,
        mask: 0xfff0c210,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Pd,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pd,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg4_10,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg4_10,
                    lsb: 10,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pn,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pn,
                    lsb: 5,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pm,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pm,
                    lsb: 16,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::NORS_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm(
            NORS_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm::from(bits),
        ))
    }
}
impl InsnOpcode for NORS_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl NOT_SVE_Zd_SVE_Pg3_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "not",
        aliases: &[],
        opcode: 0x41ea000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M, InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::NOT_SVE_Zd_SVE_Pg3_SVE_Zn(
            NOT_SVE_Zd_SVE_Pg3_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for NOT_SVE_Zd_SVE_Pg3_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl NOT_Vd_Vn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "not",
        aliases: &[],
        opcode: 0x2e205800,
        mask: 0xbffffc00,
        class: InsnClass::ASIMDMISC,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_ALIAS.bits() | InsnFlags::HAS_SIZEQ_FIELD.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDMISC(ASIMDMISC::NOT_Vd_Vn(NOT_Vd_Vn::from(bits)))
    }
}
impl InsnOpcode for NOT_Vd_Vn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ORN_Rd_Rn_Rm_SFT {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "orn",
        aliases: &[],
        opcode: 0x2a200000,
        mask: 0x7f200000,
        class: InsnClass::LOG_SHIFT,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rm_SFT,
                class: InsnOperandClass::MODIFIED_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_ALIAS.bits() | InsnFlags::HAS_SF_FIELD.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LOG_SHIFT(LOG_SHIFT::ORN_Rd_Rn_Rm_SFT(ORN_Rd_Rn_Rm_SFT::from(bits)))
    }
}
impl InsnOpcode for ORN_Rd_Rn_Rm_SFT {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ORN_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "orn",
        aliases: &[],
        opcode: 0x25804010,
        mask: 0xfff0c210,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Pd,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pd,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg4_10,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg4_10,
                    lsb: 10,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pn,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pn,
                    lsb: 5,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pm,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pm,
                    lsb: 16,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::ORN_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm(
            ORN_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm::from(bits),
        ))
    }
}
impl InsnOpcode for ORN_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ORN_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "orn",
        aliases: &[],
        opcode: 0xee01c00,
        mask: 0xbfe0fc00,
        class: InsnClass::ASIMDSAME,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSAME(ASIMDSAME::ORN_Vd_Vn_Vm(ORN_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for ORN_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ORNS_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "orns",
        aliases: &[],
        opcode: 0x25c04010,
        mask: 0xfff0c210,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Pd,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pd,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg4_10,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg4_10,
                    lsb: 10,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pn,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pn,
                    lsb: 5,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pm,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pm,
                    lsb: 16,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::ORNS_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm(
            ORNS_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm::from(bits),
        ))
    }
}
impl InsnOpcode for ORNS_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ORR_Rd_SP_Rn_LIMM {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "orr",
        aliases: &[],
        opcode: 0x32000000,
        mask: 0x7f800000,
        class: InsnClass::LOG_IMM,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd_SP,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::LIMM,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::N,
                        lsb: 22,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::immr,
                        lsb: 16,
                        width: 6,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imms,
                        lsb: 10,
                        width: 6,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_ALIAS.bits() | InsnFlags::HAS_SF_FIELD.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LOG_IMM(LOG_IMM::ORR_Rd_SP_Rn_LIMM(ORR_Rd_SP_Rn_LIMM::from(bits)))
    }
}
impl InsnOpcode for ORR_Rd_SP_Rn_LIMM {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ORR_Rd_Rn_Rm_SFT {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "orr",
        aliases: &[],
        opcode: 0x2a000000,
        mask: 0x7f200000,
        class: InsnClass::LOG_SHIFT,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rm_SFT,
                class: InsnOperandClass::MODIFIED_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_ALIAS.bits() | InsnFlags::HAS_SF_FIELD.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LOG_SHIFT(LOG_SHIFT::ORR_Rd_Rn_Rm_SFT(ORR_Rd_Rn_Rm_SFT::from(bits)))
    }
}
impl InsnOpcode for ORR_Rd_Rn_Rm_SFT {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ORR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "orr",
        aliases: &[],
        opcode: 0x4180000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_5,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_5,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::ORR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(
            ORR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5::from(bits),
        ))
    }
}
impl InsnOpcode for ORR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ORR_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "orr",
        aliases: &[],
        opcode: 0x4603000,
        mask: 0xffe0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ALIAS.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::ORR_SVE_Zd_SVE_Zn_SVE_Zm_16(
            ORR_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for ORR_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ORR_SVE_Zd_SVE_Zd_SVE_LIMM {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "orr",
        aliases: &[],
        opcode: 0x5000000,
        mask: 0xfffc0000,
        class: InsnClass::SVE_LIMM,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_LIMM,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_N,
                        lsb: 17,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_immr,
                        lsb: 11,
                        width: 6,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_imms,
                        lsb: 5,
                        width: 6,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ALIAS.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_LIMM(SVE_LIMM::ORR_SVE_Zd_SVE_Zd_SVE_LIMM(
            ORR_SVE_Zd_SVE_Zd_SVE_LIMM::from(bits),
        ))
    }
}
impl InsnOpcode for ORR_SVE_Zd_SVE_Zd_SVE_LIMM {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ORR_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "orr",
        aliases: &[],
        opcode: 0x25804000,
        mask: 0xfff0c210,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Pd,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pd,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg4_10,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg4_10,
                    lsb: 10,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pn,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pn,
                    lsb: 5,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pm,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pm,
                    lsb: 16,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ALIAS.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::ORR_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm(
            ORR_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm::from(bits),
        ))
    }
}
impl InsnOpcode for ORR_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ORR_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "orr",
        aliases: &[],
        opcode: 0xea01c00,
        mask: 0xbfe0fc00,
        class: InsnClass::ASIMDSAME,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_ALIAS.bits() | InsnFlags::HAS_SIZEQ_FIELD.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSAME(ASIMDSAME::ORR_Vd_Vn_Vm(ORR_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for ORR_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ORR_Vd_SIMD_IMM_SFT {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "orr",
        aliases: &[],
        opcode: 0xf001400,
        mask: 0xbff89c00,
        class: InsnClass::ASIMDIMM,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SIMD_IMM_SFT,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[InsnOperandQualifier::LSL],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDIMM(ASIMDIMM::ORR_Vd_SIMD_IMM_SFT(ORR_Vd_SIMD_IMM_SFT::from(
            bits,
        )))
    }
}
impl InsnOpcode for ORR_Vd_SIMD_IMM_SFT {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ORR_Vd_V_4H_SIMD_IMM_SFT_LSL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "orr",
        aliases: &[],
        opcode: 0xf009400,
        mask: 0xbff8dc00,
        class: InsnClass::ASIMDIMM,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SIMD_IMM_SFT,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[InsnOperandQualifier::LSL],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDIMM(ASIMDIMM::ORR_Vd_V_4H_SIMD_IMM_SFT_LSL(
            ORR_Vd_V_4H_SIMD_IMM_SFT_LSL::from(bits),
        ))
    }
}
impl InsnOpcode for ORR_Vd_V_4H_SIMD_IMM_SFT_LSL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ORRS_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "orrs",
        aliases: &[],
        opcode: 0x25c04000,
        mask: 0xfff0c210,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Pd,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pd,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg4_10,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg4_10,
                    lsb: 10,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pn,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pn,
                    lsb: 5,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pm,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pm,
                    lsb: 16,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ALIAS.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::ORRS_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm(
            ORRS_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm::from(bits),
        ))
    }
}
impl InsnOpcode for ORRS_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ORV_SVE_Vd_SVE_Pg3_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "orv",
        aliases: &[],
        opcode: 0x4182000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Vd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::ORV_SVE_Vd_SVE_Pg3_SVE_Zn(
            ORV_SVE_Vd_SVE_Pg3_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for ORV_SVE_Vd_SVE_Pg3_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl PACDA_Rd_Rn_SP {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "pacda",
        aliases: &[],
        opcode: 0xdac10800,
        mask: 0xfffffc00,
        class: InsnClass::DP_1SRC,
        feature_set: InsnFeatureSet::PAC,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn_SP,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::DP_1SRC(DP_1SRC::PACDA_Rd_Rn_SP(PACDA_Rd_Rn_SP::from(bits)))
    }
}
impl InsnOpcode for PACDA_Rd_Rn_SP {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl PACDB_Rd_Rn_SP {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "pacdb",
        aliases: &[],
        opcode: 0xdac10c00,
        mask: 0xfffffc00,
        class: InsnClass::DP_1SRC,
        feature_set: InsnFeatureSet::PAC,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn_SP,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::DP_1SRC(DP_1SRC::PACDB_Rd_Rn_SP(PACDB_Rd_Rn_SP::from(bits)))
    }
}
impl InsnOpcode for PACDB_Rd_Rn_SP {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl PACDZA_Rd {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "pacdza",
        aliases: &[],
        opcode: 0xdac12be0,
        mask: 0xffffffe0,
        class: InsnClass::DP_1SRC,
        feature_set: InsnFeatureSet::PAC,
        operands: &[InsnOperand {
            kind: InsnOperandKind::Rd,
            class: InsnOperandClass::INT_REG,
            qualifiers: &[],
            bit_fields: &[BitfieldSpec {
                bitfield: InsnBitField::Rd,
                lsb: 0,
                width: 5,
            }],
        }],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::DP_1SRC(DP_1SRC::PACDZA_Rd(PACDZA_Rd::from(bits)))
    }
}
impl InsnOpcode for PACDZA_Rd {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl PACDZB_Rd {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "pacdzb",
        aliases: &[],
        opcode: 0xdac12fe0,
        mask: 0xffffffe0,
        class: InsnClass::DP_1SRC,
        feature_set: InsnFeatureSet::PAC,
        operands: &[InsnOperand {
            kind: InsnOperandKind::Rd,
            class: InsnOperandClass::INT_REG,
            qualifiers: &[],
            bit_fields: &[BitfieldSpec {
                bitfield: InsnBitField::Rd,
                lsb: 0,
                width: 5,
            }],
        }],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::DP_1SRC(DP_1SRC::PACDZB_Rd(PACDZB_Rd::from(bits)))
    }
}
impl InsnOpcode for PACDZB_Rd {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl PACGA_Rd_Rn_Rm_SP {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "pacga",
        aliases: &[],
        opcode: 0x9ac03000,
        mask: 0xffe0fc00,
        class: InsnClass::DP_2SRC,
        feature_set: InsnFeatureSet::PAC,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rm_SP,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::DP_2SRC(DP_2SRC::PACGA_Rd_Rn_Rm_SP(PACGA_Rd_Rn_Rm_SP::from(bits)))
    }
}
impl InsnOpcode for PACGA_Rd_Rn_Rm_SP {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl PACIA_Rd_Rn_SP {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "pacia",
        aliases: &[],
        opcode: 0xdac10000,
        mask: 0xfffffc00,
        class: InsnClass::DP_1SRC,
        feature_set: InsnFeatureSet::PAC,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn_SP,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::DP_1SRC(DP_1SRC::PACIA_Rd_Rn_SP(PACIA_Rd_Rn_SP::from(bits)))
    }
}
impl InsnOpcode for PACIA_Rd_Rn_SP {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl PACIB_Rd_Rn_SP {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "pacib",
        aliases: &[],
        opcode: 0xdac10400,
        mask: 0xfffffc00,
        class: InsnClass::DP_1SRC,
        feature_set: InsnFeatureSet::PAC,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn_SP,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::DP_1SRC(DP_1SRC::PACIB_Rd_Rn_SP(PACIB_Rd_Rn_SP::from(bits)))
    }
}
impl InsnOpcode for PACIB_Rd_Rn_SP {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl PACIZA_Rd {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "paciza",
        aliases: &[],
        opcode: 0xdac123e0,
        mask: 0xffffffe0,
        class: InsnClass::DP_1SRC,
        feature_set: InsnFeatureSet::PAC,
        operands: &[InsnOperand {
            kind: InsnOperandKind::Rd,
            class: InsnOperandClass::INT_REG,
            qualifiers: &[],
            bit_fields: &[BitfieldSpec {
                bitfield: InsnBitField::Rd,
                lsb: 0,
                width: 5,
            }],
        }],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::DP_1SRC(DP_1SRC::PACIZA_Rd(PACIZA_Rd::from(bits)))
    }
}
impl InsnOpcode for PACIZA_Rd {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl PACIZB_Rd {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "pacizb",
        aliases: &[],
        opcode: 0xdac127e0,
        mask: 0xffffffe0,
        class: InsnClass::DP_1SRC,
        feature_set: InsnFeatureSet::PAC,
        operands: &[InsnOperand {
            kind: InsnOperandKind::Rd,
            class: InsnOperandClass::INT_REG,
            qualifiers: &[],
            bit_fields: &[BitfieldSpec {
                bitfield: InsnBitField::Rd,
                lsb: 0,
                width: 5,
            }],
        }],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::DP_1SRC(DP_1SRC::PACIZB_Rd(PACIZB_Rd::from(bits)))
    }
}
impl InsnOpcode for PACIZB_Rd {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl PEXT_SVE_Pd_SME_PNn3_INDEX2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "pext",
        aliases: &[],
        opcode: 0x25207010,
        mask: 0xff3ffc10,
        class: InsnClass::SME_SIZE_22,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Pd,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pd,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNn3_INDEX2,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_PNn3,
                        lsb: 5,
                        width: 3,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_8,
                        lsb: 8,
                        width: 2,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_SIZE_22(SME_SIZE_22::PEXT_SVE_Pd_SME_PNn3_INDEX2(
            PEXT_SVE_Pd_SME_PNn3_INDEX2::from(bits),
        ))
    }
}
impl InsnOpcode for PEXT_SVE_Pd_SME_PNn3_INDEX2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl PEXT_SME_PdxN_SME_PNn3_INDEX1 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "pext",
        aliases: &[],
        opcode: 0x25207410,
        mask: 0xff3ffe10,
        class: InsnClass::SME_SIZE_22,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_PdxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pd,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNn3_INDEX1,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_PNn3,
                        lsb: 5,
                        width: 3,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm1_8,
                        lsb: 8,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_SIZE_22(SME_SIZE_22::PEXT_SME_PdxN_SME_PNn3_INDEX1(
            PEXT_SME_PdxN_SME_PNn3_INDEX1::from(bits),
        ))
    }
}
impl InsnOpcode for PEXT_SME_PdxN_SME_PNn3_INDEX1 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl PFALSE_SVE_Pd {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "pfalse",
        aliases: &[],
        opcode: 0x2518e400,
        mask: 0xfffffff0,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[InsnOperand {
            kind: InsnOperandKind::SVE_Pd,
            class: InsnOperandClass::PRED_REG,
            qualifiers: &[],
            bit_fields: &[BitfieldSpec {
                bitfield: InsnBitField::SVE_Pd,
                lsb: 0,
                width: 4,
            }],
        }],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::PFALSE_SVE_Pd(PFALSE_SVE_Pd::from(bits)))
    }
}
impl InsnOpcode for PFALSE_SVE_Pd {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl PFALSE_SVE_PNd {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "pfalse",
        aliases: &[],
        opcode: 0x2518e400,
        mask: 0xfffffff0,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[InsnOperand {
            kind: InsnOperandKind::SVE_PNd,
            class: InsnOperandClass::PRED_REG,
            qualifiers: &[],
            bit_fields: &[BitfieldSpec {
                bitfield: InsnBitField::SVE_Pd,
                lsb: 0,
                width: 4,
            }],
        }],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::PFALSE_SVE_PNd(PFALSE_SVE_PNd::from(bits)))
    }
}
impl InsnOpcode for PFALSE_SVE_PNd {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl PFIRST_SVE_Pd_SVE_Pg4_5_SVE_Pd {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "pfirst",
        aliases: &[],
        opcode: 0x2558c000,
        mask: 0xfffffe10,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Pd,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pd,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg4_5,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg4_5,
                    lsb: 5,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pd,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pd,
                    lsb: 0,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::PFIRST_SVE_Pd_SVE_Pg4_5_SVE_Pd(
            PFIRST_SVE_Pd_SVE_Pg4_5_SVE_Pd::from(bits),
        ))
    }
}
impl InsnOpcode for PFIRST_SVE_Pd_SVE_Pg4_5_SVE_Pd {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl PMUL_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "pmul",
        aliases: &[],
        opcode: 0x4206400,
        mask: 0xffe0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::PMUL_SVE_Zd_SVE_Zn_SVE_Zm_16(
            PMUL_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for PMUL_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl PMUL_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "pmul",
        aliases: &[],
        opcode: 0x2e209c00,
        mask: 0xbf20fc00,
        class: InsnClass::ASIMDSAME,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSAME(ASIMDSAME::PMUL_Vd_Vn_Vm(PMUL_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for PMUL_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl PMULL_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "pmull",
        aliases: &[],
        opcode: 0xe20e000,
        mask: 0xffe0fc00,
        class: InsnClass::ASIMDDIFF,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDDIFF(ASIMDDIFF::PMULL_Vd_Vn_Vm(PMULL_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for PMULL_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl PMULL_Vd_V_1Q_Vn_V_1D_Vm_V_1D {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "pmull",
        aliases: &[],
        opcode: 0xee0e000,
        mask: 0xffe0fc00,
        class: InsnClass::ASIMDDIFF,
        feature_set: InsnFeatureSet::AES,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_1Q],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_1D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_1D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDDIFF(ASIMDDIFF::PMULL_Vd_V_1Q_Vn_V_1D_Vm_V_1D(
            PMULL_Vd_V_1Q_Vn_V_1D_Vm_V_1D::from(bits),
        ))
    }
}
impl InsnOpcode for PMULL_Vd_V_1Q_Vn_V_1D_Vm_V_1D {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl PMULL2_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "pmull2",
        aliases: &[],
        opcode: 0x4e20e000,
        mask: 0xffe0fc00,
        class: InsnClass::ASIMDDIFF,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDDIFF(ASIMDDIFF::PMULL2_Vd_Vn_Vm(PMULL2_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for PMULL2_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl PMULL2_Vd_V_1Q_Vn_V_2D_Vm_V_2D {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "pmull2",
        aliases: &[],
        opcode: 0x4ee0e000,
        mask: 0xffe0fc00,
        class: InsnClass::ASIMDDIFF,
        feature_set: InsnFeatureSet::AES,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_1Q],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDDIFF(ASIMDDIFF::PMULL2_Vd_V_1Q_Vn_V_2D_Vm_V_2D(
            PMULL2_Vd_V_1Q_Vn_V_2D_Vm_V_2D::from(bits),
        ))
    }
}
impl InsnOpcode for PMULL2_Vd_V_1Q_Vn_V_2D_Vm_V_2D {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl PMULLB_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "pmullb",
        aliases: &[],
        opcode: 0x45006800,
        mask: 0xffe0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE2AES,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_Q],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::PMULLB_SVE_Zd_SVE_Zn_SVE_Zm_16(
            PMULLB_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for PMULLB_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl PMULLB_SVE_Zd_S_H_SVE_Zn_S_B_SVE_Zm_16_S_B {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "pmullb",
        aliases: &[],
        opcode: 0x45406800,
        mask: 0xff60fc00,
        class: InsnClass::SVE_SIZE_13,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_13(SVE_SIZE_13::PMULLB_SVE_Zd_S_H_SVE_Zn_S_B_SVE_Zm_16_S_B(
            PMULLB_SVE_Zd_S_H_SVE_Zn_S_B_SVE_Zm_16_S_B::from(bits),
        ))
    }
}
impl InsnOpcode for PMULLB_SVE_Zd_S_H_SVE_Zn_S_B_SVE_Zm_16_S_B {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl PMULLT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "pmullt",
        aliases: &[],
        opcode: 0x45006c00,
        mask: 0xffe0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE2AES,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_Q],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::PMULLT_SVE_Zd_SVE_Zn_SVE_Zm_16(
            PMULLT_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for PMULLT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl PMULLT_SVE_Zd_S_H_SVE_Zn_S_B_SVE_Zm_16_S_B {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "pmullt",
        aliases: &[],
        opcode: 0x45406c00,
        mask: 0xff60fc00,
        class: InsnClass::SVE_SIZE_13,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_13(SVE_SIZE_13::PMULLT_SVE_Zd_S_H_SVE_Zn_S_B_SVE_Zm_16_S_B(
            PMULLT_SVE_Zd_S_H_SVE_Zn_S_B_SVE_Zm_16_S_B::from(bits),
        ))
    }
}
impl InsnOpcode for PMULLT_SVE_Zd_S_H_SVE_Zn_S_B_SVE_Zm_16_S_B {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl PNEXT_SVE_Pd_SVE_Pg4_5_SVE_Pd {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "pnext",
        aliases: &[],
        opcode: 0x2519c400,
        mask: 0xff3ffe10,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Pd,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pd,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg4_5,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg4_5,
                    lsb: 5,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pd,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pd,
                    lsb: 0,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::PNEXT_SVE_Pd_SVE_Pg4_5_SVE_Pd(
            PNEXT_SVE_Pd_SVE_Pg4_5_SVE_Pd::from(bits),
        ))
    }
}
impl InsnOpcode for PNEXT_SVE_Pd_SVE_Pg4_5_SVE_Pd {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl PRFB_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RZ_XTW_22 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "prfb",
        aliases: &[],
        opcode: 0x84200000,
        mask: 0xffa0e010,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_PRFOP,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_prfop,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RZ_XTW_22,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zm_16,
                        lsb: 16,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_xs_22,
                        lsb: 22,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::PRFB_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RZ_XTW_22(
            PRFB_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RZ_XTW_22::from(bits),
        ))
    }
}
impl InsnOpcode for PRFB_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RZ_XTW_22 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl PRFB_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RZ_XTW_22_c4200000 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "prfb",
        aliases: &[],
        opcode: 0xc4200000,
        mask: 0xffa0e010,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_PRFOP,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_prfop,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RZ_XTW_22,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zm_16,
                        lsb: 16,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_xs_22,
                        lsb: 22,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(
            SVE_MISC::PRFB_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RZ_XTW_22_c4200000(
                PRFB_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RZ_XTW_22_c4200000::from(bits),
            ),
        )
    }
}
impl InsnOpcode for PRFB_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RZ_XTW_22_c4200000 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl PRFB_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RZ {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "prfb",
        aliases: &[],
        opcode: 0xc4608000,
        mask: 0xffe0e010,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_PRFOP,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_prfop,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RZ,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zm_16,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::PRFB_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RZ(
            PRFB_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RZ::from(bits),
        ))
    }
}
impl InsnOpcode for PRFB_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RZ {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl PRFB_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "prfb",
        aliases: &[],
        opcode: 0x8400c000,
        mask: 0xffe0e010,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_PRFOP,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_prfop,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RX,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::PRFB_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RX(
            PRFB_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RX::from(bits),
        ))
    }
}
impl InsnOpcode for PRFB_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl PRFB_SVE_PRFOP_SVE_Pg3_SVE_ADDR_ZI_U5 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "prfb",
        aliases: &[],
        opcode: 0x8400e000,
        mask: 0xffe0e010,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_PRFOP,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_prfop,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_ZI_U5,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::PRFB_SVE_PRFOP_SVE_Pg3_SVE_ADDR_ZI_U5(
            PRFB_SVE_PRFOP_SVE_Pg3_SVE_ADDR_ZI_U5::from(bits),
        ))
    }
}
impl InsnOpcode for PRFB_SVE_PRFOP_SVE_Pg3_SVE_ADDR_ZI_U5 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl PRFB_SVE_PRFOP_SVE_Pg3_SVE_ADDR_ZI_U5_c400e000 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "prfb",
        aliases: &[],
        opcode: 0xc400e000,
        mask: 0xffe0e010,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_PRFOP,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_prfop,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_ZI_U5,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::PRFB_SVE_PRFOP_SVE_Pg3_SVE_ADDR_ZI_U5_c400e000(
            PRFB_SVE_PRFOP_SVE_Pg3_SVE_ADDR_ZI_U5_c400e000::from(bits),
        ))
    }
}
impl InsnOpcode for PRFB_SVE_PRFOP_SVE_Pg3_SVE_ADDR_ZI_U5_c400e000 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl PRFB_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RI_S6xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "prfb",
        aliases: &[],
        opcode: 0x85c00000,
        mask: 0xffc0e010,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_PRFOP,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_prfop,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S6xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::PRFB_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RI_S6xVL(
            PRFB_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RI_S6xVL::from(bits),
        ))
    }
}
impl InsnOpcode for PRFB_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RI_S6xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl PRFD_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RZ_XTW3_22 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "prfd",
        aliases: &[],
        opcode: 0x84206000,
        mask: 0xffa0e010,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_PRFOP,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_prfop,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RZ_XTW3_22,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zm_16,
                        lsb: 16,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_xs_22,
                        lsb: 22,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::PRFD_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RZ_XTW3_22(
            PRFD_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RZ_XTW3_22::from(bits),
        ))
    }
}
impl InsnOpcode for PRFD_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RZ_XTW3_22 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl PRFD_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RZ_XTW3_22_c4206000 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "prfd",
        aliases: &[],
        opcode: 0xc4206000,
        mask: 0xffa0e010,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_PRFOP,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_prfop,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RZ_XTW3_22,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zm_16,
                        lsb: 16,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_xs_22,
                        lsb: 22,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(
            SVE_MISC::PRFD_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RZ_XTW3_22_c4206000(
                PRFD_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RZ_XTW3_22_c4206000::from(bits),
            ),
        )
    }
}
impl InsnOpcode for PRFD_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RZ_XTW3_22_c4206000 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl PRFD_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RZ_LSL3 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "prfd",
        aliases: &[],
        opcode: 0xc460e000,
        mask: 0xffe0e010,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_PRFOP,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_prfop,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RZ_LSL3,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zm_16,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::PRFD_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RZ_LSL3(
            PRFD_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RZ_LSL3::from(bits),
        ))
    }
}
impl InsnOpcode for PRFD_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RZ_LSL3 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl PRFD_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RX_LSL3 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "prfd",
        aliases: &[],
        opcode: 0x8580c000,
        mask: 0xffe0e010,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_PRFOP,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_prfop,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RX_LSL3,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::PRFD_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RX_LSL3(
            PRFD_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RX_LSL3::from(bits),
        ))
    }
}
impl InsnOpcode for PRFD_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RX_LSL3 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl PRFD_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RI_S6xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "prfd",
        aliases: &[],
        opcode: 0x85c06000,
        mask: 0xffc0e010,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_PRFOP,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_prfop,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S6xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::PRFD_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RI_S6xVL(
            PRFD_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RI_S6xVL::from(bits),
        ))
    }
}
impl InsnOpcode for PRFD_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RI_S6xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl PRFD_SVE_PRFOP_SVE_Pg3_SVE_ADDR_ZI_U5x8 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "prfd",
        aliases: &[],
        opcode: 0x8580e000,
        mask: 0xffe0e010,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_PRFOP,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_prfop,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_ZI_U5x8,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::PRFD_SVE_PRFOP_SVE_Pg3_SVE_ADDR_ZI_U5x8(
            PRFD_SVE_PRFOP_SVE_Pg3_SVE_ADDR_ZI_U5x8::from(bits),
        ))
    }
}
impl InsnOpcode for PRFD_SVE_PRFOP_SVE_Pg3_SVE_ADDR_ZI_U5x8 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl PRFD_SVE_PRFOP_SVE_Pg3_SVE_ADDR_ZI_U5x8_c580e000 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "prfd",
        aliases: &[],
        opcode: 0xc580e000,
        mask: 0xffe0e010,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_PRFOP,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_prfop,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_ZI_U5x8,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::PRFD_SVE_PRFOP_SVE_Pg3_SVE_ADDR_ZI_U5x8_c580e000(
            PRFD_SVE_PRFOP_SVE_Pg3_SVE_ADDR_ZI_U5x8_c580e000::from(bits),
        ))
    }
}
impl InsnOpcode for PRFD_SVE_PRFOP_SVE_Pg3_SVE_ADDR_ZI_U5x8_c580e000 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl PRFH_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RX_LSL1 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "prfh",
        aliases: &[],
        opcode: 0x8480c000,
        mask: 0xffe0e010,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_PRFOP,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_prfop,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RX_LSL1,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::PRFH_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RX_LSL1(
            PRFH_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RX_LSL1::from(bits),
        ))
    }
}
impl InsnOpcode for PRFH_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RX_LSL1 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl PRFH_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RZ_XTW1_22 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "prfh",
        aliases: &[],
        opcode: 0x84202000,
        mask: 0xffa0e010,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_PRFOP,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_prfop,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RZ_XTW1_22,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zm_16,
                        lsb: 16,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_xs_22,
                        lsb: 22,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::PRFH_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RZ_XTW1_22(
            PRFH_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RZ_XTW1_22::from(bits),
        ))
    }
}
impl InsnOpcode for PRFH_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RZ_XTW1_22 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl PRFH_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RZ_XTW1_22_c4202000 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "prfh",
        aliases: &[],
        opcode: 0xc4202000,
        mask: 0xffa0e010,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_PRFOP,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_prfop,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RZ_XTW1_22,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zm_16,
                        lsb: 16,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_xs_22,
                        lsb: 22,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(
            SVE_MISC::PRFH_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RZ_XTW1_22_c4202000(
                PRFH_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RZ_XTW1_22_c4202000::from(bits),
            ),
        )
    }
}
impl InsnOpcode for PRFH_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RZ_XTW1_22_c4202000 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl PRFH_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RZ_LSL1 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "prfh",
        aliases: &[],
        opcode: 0xc460a000,
        mask: 0xffe0e010,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_PRFOP,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_prfop,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RZ_LSL1,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zm_16,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::PRFH_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RZ_LSL1(
            PRFH_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RZ_LSL1::from(bits),
        ))
    }
}
impl InsnOpcode for PRFH_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RZ_LSL1 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl PRFH_SVE_PRFOP_SVE_Pg3_SVE_ADDR_ZI_U5x2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "prfh",
        aliases: &[],
        opcode: 0x8480e000,
        mask: 0xffe0e010,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_PRFOP,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_prfop,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_ZI_U5x2,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::PRFH_SVE_PRFOP_SVE_Pg3_SVE_ADDR_ZI_U5x2(
            PRFH_SVE_PRFOP_SVE_Pg3_SVE_ADDR_ZI_U5x2::from(bits),
        ))
    }
}
impl InsnOpcode for PRFH_SVE_PRFOP_SVE_Pg3_SVE_ADDR_ZI_U5x2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl PRFH_SVE_PRFOP_SVE_Pg3_SVE_ADDR_ZI_U5x2_c480e000 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "prfh",
        aliases: &[],
        opcode: 0xc480e000,
        mask: 0xffe0e010,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_PRFOP,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_prfop,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_ZI_U5x2,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::PRFH_SVE_PRFOP_SVE_Pg3_SVE_ADDR_ZI_U5x2_c480e000(
            PRFH_SVE_PRFOP_SVE_Pg3_SVE_ADDR_ZI_U5x2_c480e000::from(bits),
        ))
    }
}
impl InsnOpcode for PRFH_SVE_PRFOP_SVE_Pg3_SVE_ADDR_ZI_U5x2_c480e000 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl PRFH_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RI_S6xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "prfh",
        aliases: &[],
        opcode: 0x85c02000,
        mask: 0xffc0e010,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_PRFOP,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_prfop,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S6xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::PRFH_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RI_S6xVL(
            PRFH_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RI_S6xVL::from(bits),
        ))
    }
}
impl InsnOpcode for PRFH_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RI_S6xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl PRFM_PRFOP_ADDR_PCREL19 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "prfm",
        aliases: &[],
        opcode: 0xd8000000,
        mask: 0xff000000,
        class: InsnClass::LOADLIT,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::PRFOP,
                class: InsnOperandClass::SYSTEM,
                qualifiers: &[],
                bit_fields: &[],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_PCREL19,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::imm19,
                    lsb: 5,
                    width: 19,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LOADLIT(LOADLIT::PRFM_PRFOP_ADDR_PCREL19(
            PRFM_PRFOP_ADDR_PCREL19::from(bits),
        ))
    }
}
impl InsnOpcode for PRFM_PRFOP_ADDR_PCREL19 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl PRFM_PRFOP_ADDR_REGOFF {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "prfm",
        aliases: &[],
        opcode: 0xf8a00800,
        mask: 0xffe00c00,
        class: InsnClass::LDST_REGOFF,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::PRFOP,
                class: InsnOperandClass::SYSTEM,
                qualifiers: &[],
                bit_fields: &[],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_REGOFF,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDST_REGOFF(LDST_REGOFF::PRFM_PRFOP_ADDR_REGOFF(
            PRFM_PRFOP_ADDR_REGOFF::from(bits),
        ))
    }
}
impl InsnOpcode for PRFM_PRFOP_ADDR_REGOFF {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl PRFM_PRFOP_ADDR_UIMM12 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "prfm",
        aliases: &[],
        opcode: 0xf9800000,
        mask: 0xffc00000,
        class: InsnClass::LDST_POS,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::PRFOP,
                class: InsnOperandClass::SYSTEM,
                qualifiers: &[],
                bit_fields: &[],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_UIMM12,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm12,
                        lsb: 10,
                        width: 12,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDST_POS(LDST_POS::PRFM_PRFOP_ADDR_UIMM12(
            PRFM_PRFOP_ADDR_UIMM12::from(bits),
        ))
    }
}
impl InsnOpcode for PRFM_PRFOP_ADDR_UIMM12 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl PRFUM_PRFOP_ADDR_SIMM9 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "prfum",
        aliases: &[],
        opcode: 0xf8800000,
        mask: 0xffe00c00,
        class: InsnClass::LDST_UNSCALED,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::PRFOP,
                class: InsnOperandClass::SYSTEM,
                qualifiers: &[],
                bit_fields: &[],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMM9,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::imm9,
                        lsb: 12,
                        width: 9,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::index,
                        lsb: 11,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDST_UNSCALED(LDST_UNSCALED::PRFUM_PRFOP_ADDR_SIMM9(
            PRFUM_PRFOP_ADDR_SIMM9::from(bits),
        ))
    }
}
impl InsnOpcode for PRFUM_PRFOP_ADDR_SIMM9 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl PRFW_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RZ_XTW2_22 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "prfw",
        aliases: &[],
        opcode: 0x84204000,
        mask: 0xffa0e010,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_PRFOP,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_prfop,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RZ_XTW2_22,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zm_16,
                        lsb: 16,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_xs_22,
                        lsb: 22,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::PRFW_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RZ_XTW2_22(
            PRFW_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RZ_XTW2_22::from(bits),
        ))
    }
}
impl InsnOpcode for PRFW_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RZ_XTW2_22 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl PRFW_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RZ_XTW2_22_c4204000 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "prfw",
        aliases: &[],
        opcode: 0xc4204000,
        mask: 0xffa0e010,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_PRFOP,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_prfop,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RZ_XTW2_22,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zm_16,
                        lsb: 16,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_xs_22,
                        lsb: 22,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(
            SVE_MISC::PRFW_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RZ_XTW2_22_c4204000(
                PRFW_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RZ_XTW2_22_c4204000::from(bits),
            ),
        )
    }
}
impl InsnOpcode for PRFW_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RZ_XTW2_22_c4204000 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl PRFW_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RZ_LSL2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "prfw",
        aliases: &[],
        opcode: 0xc460c000,
        mask: 0xffe0e010,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_PRFOP,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_prfop,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RZ_LSL2,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zm_16,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::PRFW_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RZ_LSL2(
            PRFW_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RZ_LSL2::from(bits),
        ))
    }
}
impl InsnOpcode for PRFW_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RZ_LSL2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl PRFW_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RI_S6xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "prfw",
        aliases: &[],
        opcode: 0x85c04000,
        mask: 0xffc0e010,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_PRFOP,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_prfop,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S6xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::PRFW_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RI_S6xVL(
            PRFW_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RI_S6xVL::from(bits),
        ))
    }
}
impl InsnOpcode for PRFW_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RI_S6xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl PRFW_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RX_LSL2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "prfw",
        aliases: &[],
        opcode: 0x8500c000,
        mask: 0xffe0e010,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_PRFOP,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_prfop,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RX_LSL2,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::PRFW_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RX_LSL2(
            PRFW_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RX_LSL2::from(bits),
        ))
    }
}
impl InsnOpcode for PRFW_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RX_LSL2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl PRFW_SVE_PRFOP_SVE_Pg3_SVE_ADDR_ZI_U5x4 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "prfw",
        aliases: &[],
        opcode: 0x8500e000,
        mask: 0xffe0e010,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_PRFOP,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_prfop,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_ZI_U5x4,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::PRFW_SVE_PRFOP_SVE_Pg3_SVE_ADDR_ZI_U5x4(
            PRFW_SVE_PRFOP_SVE_Pg3_SVE_ADDR_ZI_U5x4::from(bits),
        ))
    }
}
impl InsnOpcode for PRFW_SVE_PRFOP_SVE_Pg3_SVE_ADDR_ZI_U5x4 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl PRFW_SVE_PRFOP_SVE_Pg3_SVE_ADDR_ZI_U5x4_c500e000 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "prfw",
        aliases: &[],
        opcode: 0xc500e000,
        mask: 0xffe0e010,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_PRFOP,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_prfop,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_ZI_U5x4,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::PRFW_SVE_PRFOP_SVE_Pg3_SVE_ADDR_ZI_U5x4_c500e000(
            PRFW_SVE_PRFOP_SVE_Pg3_SVE_ADDR_ZI_U5x4_c500e000::from(bits),
        ))
    }
}
impl InsnOpcode for PRFW_SVE_PRFOP_SVE_Pg3_SVE_ADDR_ZI_U5x4_c500e000 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl PSEL_SVE_Pd_SVE_Pg4_10_SME_PnT_Wm_imm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "psel",
        aliases: &[],
        opcode: 0x25204000,
        mask: 0xff20c210,
        class: InsnClass::SME_PSEL,
        feature_set: InsnFeatureSet::SME,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Pd,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pd,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg4_10,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg4_10,
                    lsb: 10,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PnT_Wm_imm,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rm,
                        lsb: 16,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Pn,
                        lsb: 5,
                        width: 4,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_i1,
                        lsb: 23,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_tszh,
                        lsb: 22,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_tszl,
                        lsb: 18,
                        width: 3,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_PSEL(SME_PSEL::PSEL_SVE_Pd_SVE_Pg4_10_SME_PnT_Wm_imm(
            PSEL_SVE_Pd_SVE_Pg4_10_SME_PnT_Wm_imm::from(bits),
        ))
    }
}
impl InsnOpcode for PSEL_SVE_Pd_SVE_Pg4_10_SME_PnT_Wm_imm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl PSEL_SVE_PNd_SVE_PNg4_10_SME_PnT_Wm_imm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "psel",
        aliases: &[],
        opcode: 0x25204000,
        mask: 0xff20c210,
        class: InsnClass::SME_PSEL,
        feature_set: InsnFeatureSet::SME,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_PNd,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pd,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_PNg4_10,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg4_10,
                    lsb: 10,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PnT_Wm_imm,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rm,
                        lsb: 16,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Pn,
                        lsb: 5,
                        width: 4,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_i1,
                        lsb: 23,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_tszh,
                        lsb: 22,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_tszl,
                        lsb: 18,
                        width: 3,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_PSEL(SME_PSEL::PSEL_SVE_PNd_SVE_PNg4_10_SME_PnT_Wm_imm(
            PSEL_SVE_PNd_SVE_PNg4_10_SME_PnT_Wm_imm::from(bits),
        ))
    }
}
impl InsnOpcode for PSEL_SVE_PNd_SVE_PNg4_10_SME_PnT_Wm_imm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl PTEST_SVE_Pg4_10_SVE_Pn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ptest",
        aliases: &[],
        opcode: 0x2550c000,
        mask: 0xffffc21f,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg4_10,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg4_10,
                    lsb: 10,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pn,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pn,
                    lsb: 5,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::PTEST_SVE_Pg4_10_SVE_Pn(
            PTEST_SVE_Pg4_10_SVE_Pn::from(bits),
        ))
    }
}
impl InsnOpcode for PTEST_SVE_Pg4_10_SVE_Pn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl PTRUE_SME_PNd3 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ptrue",
        aliases: &[],
        opcode: 0x25207810,
        mask: 0xff3ffff8,
        class: InsnClass::SME_SIZE_22,
        feature_set: InsnFeatureSet::SME2,
        operands: &[InsnOperand {
            kind: InsnOperandKind::SME_PNd3,
            class: InsnOperandClass::PRED_REG,
            qualifiers: &[],
            bit_fields: &[BitfieldSpec {
                bitfield: InsnBitField::SME_PNd3,
                lsb: 0,
                width: 3,
            }],
        }],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_SIZE_22(SME_SIZE_22::PTRUE_SME_PNd3(PTRUE_SME_PNd3::from(bits)))
    }
}
impl InsnOpcode for PTRUE_SME_PNd3 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl PTRUE_SVE_Pd_SVE_PATTERN {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ptrue",
        aliases: &[],
        opcode: 0x2518e000,
        mask: 0xff3ffc10,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Pd,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pd,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_PATTERN,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_pattern,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::PTRUE_SVE_Pd_SVE_PATTERN(
            PTRUE_SVE_Pd_SVE_PATTERN::from(bits),
        ))
    }
}
impl InsnOpcode for PTRUE_SVE_Pd_SVE_PATTERN {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl PTRUES_SVE_Pd_SVE_PATTERN {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ptrues",
        aliases: &[],
        opcode: 0x2519e000,
        mask: 0xff3ffc10,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Pd,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pd,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_PATTERN,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_pattern,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::PTRUES_SVE_Pd_SVE_PATTERN(
            PTRUES_SVE_Pd_SVE_PATTERN::from(bits),
        ))
    }
}
impl InsnOpcode for PTRUES_SVE_Pd_SVE_PATTERN {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl PUNPKHI_SVE_Pd_SVE_Pn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "punpkhi",
        aliases: &[],
        opcode: 0x5314000,
        mask: 0xfffffe10,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Pd,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pd,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pn,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pn,
                    lsb: 5,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::PUNPKHI_SVE_Pd_SVE_Pn(
            PUNPKHI_SVE_Pd_SVE_Pn::from(bits),
        ))
    }
}
impl InsnOpcode for PUNPKHI_SVE_Pd_SVE_Pn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl PUNPKLO_SVE_Pd_SVE_Pn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "punpklo",
        aliases: &[],
        opcode: 0x5304000,
        mask: 0xfffffe10,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Pd,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pd,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pn,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pn,
                    lsb: 5,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::PUNPKLO_SVE_Pd_SVE_Pn(
            PUNPKLO_SVE_Pd_SVE_Pn::from(bits),
        ))
    }
}
impl InsnOpcode for PUNPKLO_SVE_Pd_SVE_Pn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl RADDHN_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "raddhn",
        aliases: &[],
        opcode: 0x2e204000,
        mask: 0xff20fc00,
        class: InsnClass::ASIMDDIFF,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_4H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8H, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8H, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDDIFF(ASIMDDIFF::RADDHN_Vd_Vn_Vm(RADDHN_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for RADDHN_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl RADDHN2_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "raddhn2",
        aliases: &[],
        opcode: 0x6e204000,
        mask: 0xff20fc00,
        class: InsnClass::ASIMDDIFF,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_16B, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8H, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8H, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDDIFF(ASIMDDIFF::RADDHN2_Vd_Vn_Vm(RADDHN2_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for RADDHN2_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl RADDHNB_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "raddhnb",
        aliases: &[],
        opcode: 0x45206800,
        mask: 0xff20fc00,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::RADDHNB_SVE_Zd_SVE_Zn_SVE_Zm_16(
            RADDHNB_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for RADDHNB_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl RADDHNT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "raddhnt",
        aliases: &[],
        opcode: 0x45206c00,
        mask: 0xff20fc00,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::RADDHNT_SVE_Zd_SVE_Zn_SVE_Zm_16(
            RADDHNT_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for RADDHNT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl RAX1_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "rax1",
        aliases: &[],
        opcode: 0x4520f400,
        mask: 0xffe0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE2SHA3,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::RAX1_SVE_Zd_SVE_Zn_SVE_Zm_16(
            RAX1_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for RAX1_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl RAX1_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "rax1",
        aliases: &[],
        opcode: 0xce608c00,
        mask: 0xffe0fc00,
        class: InsnClass::CRYPTOSHA3,
        feature_set: InsnFeatureSet::SHA3,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::CRYPTOSHA3(CRYPTOSHA3::RAX1_Vd_Vn_Vm(RAX1_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for RAX1_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl RBIT_Rd_Rn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "rbit",
        aliases: &[],
        opcode: 0x5ac00000,
        mask: 0x7ffffc00,
        class: InsnClass::DP_1SRC,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SF_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::DP_1SRC(DP_1SRC::RBIT_Rd_Rn(RBIT_Rd_Rn::from(bits)))
    }
}
impl InsnOpcode for RBIT_Rd_Rn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl RBIT_SVE_Zd_SVE_Pg3_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "rbit",
        aliases: &[],
        opcode: 0x5278000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M, InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::RBIT_SVE_Zd_SVE_Pg3_SVE_Zn(
            RBIT_SVE_Zd_SVE_Pg3_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for RBIT_SVE_Zd_SVE_Pg3_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl RBIT_Vd_Vn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "rbit",
        aliases: &[],
        opcode: 0x2e605800,
        mask: 0xbffffc00,
        class: InsnClass::ASIMDMISC,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDMISC(ASIMDMISC::RBIT_Vd_Vn(RBIT_Vd_Vn::from(bits)))
    }
}
impl InsnOpcode for RBIT_Vd_Vn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl RCWCAS_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "rcwcas",
        aliases: &[],
        opcode: 0x19200800,
        mask: 0xffe0fc00,
        class: InsnClass::THE,
        feature_set: InsnFeatureSet::THE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::THE(THE::RCWCAS_Rs_Rt_ADDR_SIMPLE(
            RCWCAS_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for RCWCAS_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl RCWCASA_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "rcwcasa",
        aliases: &[],
        opcode: 0x19a00800,
        mask: 0xffe0fc00,
        class: InsnClass::THE,
        feature_set: InsnFeatureSet::THE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::THE(THE::RCWCASA_Rs_Rt_ADDR_SIMPLE(
            RCWCASA_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for RCWCASA_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl RCWCASAL_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "rcwcasal",
        aliases: &[],
        opcode: 0x19e00800,
        mask: 0xffe0fc00,
        class: InsnClass::THE,
        feature_set: InsnFeatureSet::THE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::THE(THE::RCWCASAL_Rs_Rt_ADDR_SIMPLE(
            RCWCASAL_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for RCWCASAL_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl RCWCASL_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "rcwcasl",
        aliases: &[],
        opcode: 0x19600800,
        mask: 0xffe0fc00,
        class: InsnClass::THE,
        feature_set: InsnFeatureSet::THE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::THE(THE::RCWCASL_Rs_Rt_ADDR_SIMPLE(
            RCWCASL_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for RCWCASL_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl RCWCASP_Rs_PAIRREG_Rt_PAIRREG_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "rcwcasp",
        aliases: &[],
        opcode: 0x19200c00,
        mask: 0xffe0fc00,
        class: InsnClass::THE,
        feature_set: InsnFeatureSet::D128_THE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::PAIRREG,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::PAIRREG,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::THE(THE::RCWCASP_Rs_PAIRREG_Rt_PAIRREG_ADDR_SIMPLE(
            RCWCASP_Rs_PAIRREG_Rt_PAIRREG_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for RCWCASP_Rs_PAIRREG_Rt_PAIRREG_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl RCWCASPA_Rs_PAIRREG_Rt_PAIRREG_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "rcwcaspa",
        aliases: &[],
        opcode: 0x19a00c00,
        mask: 0xffe0fc00,
        class: InsnClass::THE,
        feature_set: InsnFeatureSet::D128_THE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::PAIRREG,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::PAIRREG,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::THE(THE::RCWCASPA_Rs_PAIRREG_Rt_PAIRREG_ADDR_SIMPLE(
            RCWCASPA_Rs_PAIRREG_Rt_PAIRREG_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for RCWCASPA_Rs_PAIRREG_Rt_PAIRREG_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl RCWCASPAL_Rs_PAIRREG_Rt_PAIRREG_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "rcwcaspal",
        aliases: &[],
        opcode: 0x19e00c00,
        mask: 0xffe0fc00,
        class: InsnClass::THE,
        feature_set: InsnFeatureSet::D128_THE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::PAIRREG,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::PAIRREG,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::THE(THE::RCWCASPAL_Rs_PAIRREG_Rt_PAIRREG_ADDR_SIMPLE(
            RCWCASPAL_Rs_PAIRREG_Rt_PAIRREG_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for RCWCASPAL_Rs_PAIRREG_Rt_PAIRREG_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl RCWCASPL_Rs_PAIRREG_Rt_PAIRREG_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "rcwcaspl",
        aliases: &[],
        opcode: 0x19600c00,
        mask: 0xffe0fc00,
        class: InsnClass::THE,
        feature_set: InsnFeatureSet::D128_THE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::PAIRREG,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::PAIRREG,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::THE(THE::RCWCASPL_Rs_PAIRREG_Rt_PAIRREG_ADDR_SIMPLE(
            RCWCASPL_Rs_PAIRREG_Rt_PAIRREG_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for RCWCASPL_Rs_PAIRREG_Rt_PAIRREG_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl RCWCLR_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "rcwclr",
        aliases: &[],
        opcode: 0x38209000,
        mask: 0xffe0fc00,
        class: InsnClass::THE,
        feature_set: InsnFeatureSet::THE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::THE(THE::RCWCLR_Rs_Rt_ADDR_SIMPLE(
            RCWCLR_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for RCWCLR_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl RCWCLRA_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "rcwclra",
        aliases: &[],
        opcode: 0x38a09000,
        mask: 0xffe0fc00,
        class: InsnClass::THE,
        feature_set: InsnFeatureSet::THE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::THE(THE::RCWCLRA_Rs_Rt_ADDR_SIMPLE(
            RCWCLRA_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for RCWCLRA_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl RCWCLRAL_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "rcwclral",
        aliases: &[],
        opcode: 0x38e09000,
        mask: 0xffe0fc00,
        class: InsnClass::THE,
        feature_set: InsnFeatureSet::THE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::THE(THE::RCWCLRAL_Rs_Rt_ADDR_SIMPLE(
            RCWCLRAL_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for RCWCLRAL_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl RCWCLRL_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "rcwclrl",
        aliases: &[],
        opcode: 0x38609000,
        mask: 0xffe0fc00,
        class: InsnClass::THE,
        feature_set: InsnFeatureSet::THE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::THE(THE::RCWCLRL_Rs_Rt_ADDR_SIMPLE(
            RCWCLRL_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for RCWCLRL_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl RCWCLRP_Rt_Rs_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "rcwclrp",
        aliases: &[],
        opcode: 0x19209000,
        mask: 0xffe0fc00,
        class: InsnClass::THE,
        feature_set: InsnFeatureSet::D128_THE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::THE(THE::RCWCLRP_Rt_Rs_ADDR_SIMPLE(
            RCWCLRP_Rt_Rs_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for RCWCLRP_Rt_Rs_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl RCWCLRPA_Rt_Rs_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "rcwclrpa",
        aliases: &[],
        opcode: 0x19a09000,
        mask: 0xffe0fc00,
        class: InsnClass::THE,
        feature_set: InsnFeatureSet::D128_THE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::THE(THE::RCWCLRPA_Rt_Rs_ADDR_SIMPLE(
            RCWCLRPA_Rt_Rs_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for RCWCLRPA_Rt_Rs_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl RCWCLRPAL_Rt_Rs_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "rcwclrpal",
        aliases: &[],
        opcode: 0x19e09000,
        mask: 0xffe0fc00,
        class: InsnClass::THE,
        feature_set: InsnFeatureSet::D128_THE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::THE(THE::RCWCLRPAL_Rt_Rs_ADDR_SIMPLE(
            RCWCLRPAL_Rt_Rs_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for RCWCLRPAL_Rt_Rs_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl RCWCLRPL_Rt_Rs_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "rcwclrpl",
        aliases: &[],
        opcode: 0x19609000,
        mask: 0xffe0fc00,
        class: InsnClass::THE,
        feature_set: InsnFeatureSet::D128_THE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::THE(THE::RCWCLRPL_Rt_Rs_ADDR_SIMPLE(
            RCWCLRPL_Rt_Rs_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for RCWCLRPL_Rt_Rs_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl RCWSCAS_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "rcwscas",
        aliases: &[],
        opcode: 0x59200800,
        mask: 0xffe0fc00,
        class: InsnClass::THE,
        feature_set: InsnFeatureSet::THE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::THE(THE::RCWSCAS_Rs_Rt_ADDR_SIMPLE(
            RCWSCAS_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for RCWSCAS_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl RCWSCASA_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "rcwscasa",
        aliases: &[],
        opcode: 0x59a00800,
        mask: 0xffe0fc00,
        class: InsnClass::THE,
        feature_set: InsnFeatureSet::THE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::THE(THE::RCWSCASA_Rs_Rt_ADDR_SIMPLE(
            RCWSCASA_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for RCWSCASA_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl RCWSCASAL_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "rcwscasal",
        aliases: &[],
        opcode: 0x59e00800,
        mask: 0xffe0fc00,
        class: InsnClass::THE,
        feature_set: InsnFeatureSet::THE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::THE(THE::RCWSCASAL_Rs_Rt_ADDR_SIMPLE(
            RCWSCASAL_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for RCWSCASAL_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl RCWSCASL_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "rcwscasl",
        aliases: &[],
        opcode: 0x59600800,
        mask: 0xffe0fc00,
        class: InsnClass::THE,
        feature_set: InsnFeatureSet::THE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::THE(THE::RCWSCASL_Rs_Rt_ADDR_SIMPLE(
            RCWSCASL_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for RCWSCASL_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl RCWSCASP_Rs_PAIRREG_Rt_PAIRREG_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "rcwscasp",
        aliases: &[],
        opcode: 0x59200c00,
        mask: 0xffe0fc00,
        class: InsnClass::THE,
        feature_set: InsnFeatureSet::D128_THE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::PAIRREG,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::PAIRREG,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::THE(THE::RCWSCASP_Rs_PAIRREG_Rt_PAIRREG_ADDR_SIMPLE(
            RCWSCASP_Rs_PAIRREG_Rt_PAIRREG_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for RCWSCASP_Rs_PAIRREG_Rt_PAIRREG_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl RCWSCASPA_Rs_PAIRREG_Rt_PAIRREG_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "rcwscaspa",
        aliases: &[],
        opcode: 0x59a00c00,
        mask: 0xffe0fc00,
        class: InsnClass::THE,
        feature_set: InsnFeatureSet::D128_THE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::PAIRREG,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::PAIRREG,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::THE(THE::RCWSCASPA_Rs_PAIRREG_Rt_PAIRREG_ADDR_SIMPLE(
            RCWSCASPA_Rs_PAIRREG_Rt_PAIRREG_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for RCWSCASPA_Rs_PAIRREG_Rt_PAIRREG_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl RCWSCASPAL_Rs_PAIRREG_Rt_PAIRREG_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "rcwscaspal",
        aliases: &[],
        opcode: 0x59e00c00,
        mask: 0xffe0fc00,
        class: InsnClass::THE,
        feature_set: InsnFeatureSet::D128_THE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::PAIRREG,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::PAIRREG,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::THE(THE::RCWSCASPAL_Rs_PAIRREG_Rt_PAIRREG_ADDR_SIMPLE(
            RCWSCASPAL_Rs_PAIRREG_Rt_PAIRREG_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for RCWSCASPAL_Rs_PAIRREG_Rt_PAIRREG_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl RCWSCASPL_Rs_PAIRREG_Rt_PAIRREG_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "rcwscaspl",
        aliases: &[],
        opcode: 0x59600c00,
        mask: 0xffe0fc00,
        class: InsnClass::THE,
        feature_set: InsnFeatureSet::D128_THE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::PAIRREG,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::PAIRREG,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::THE(THE::RCWSCASPL_Rs_PAIRREG_Rt_PAIRREG_ADDR_SIMPLE(
            RCWSCASPL_Rs_PAIRREG_Rt_PAIRREG_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for RCWSCASPL_Rs_PAIRREG_Rt_PAIRREG_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl RCWSCLR_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "rcwsclr",
        aliases: &[],
        opcode: 0x78209000,
        mask: 0xffe0fc00,
        class: InsnClass::THE,
        feature_set: InsnFeatureSet::THE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::THE(THE::RCWSCLR_Rs_Rt_ADDR_SIMPLE(
            RCWSCLR_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for RCWSCLR_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl RCWSCLRA_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "rcwsclra",
        aliases: &[],
        opcode: 0x78a09000,
        mask: 0xffe0fc00,
        class: InsnClass::THE,
        feature_set: InsnFeatureSet::THE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::THE(THE::RCWSCLRA_Rs_Rt_ADDR_SIMPLE(
            RCWSCLRA_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for RCWSCLRA_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl RCWSCLRAL_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "rcwsclral",
        aliases: &[],
        opcode: 0x78e09000,
        mask: 0xffe0fc00,
        class: InsnClass::THE,
        feature_set: InsnFeatureSet::THE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::THE(THE::RCWSCLRAL_Rs_Rt_ADDR_SIMPLE(
            RCWSCLRAL_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for RCWSCLRAL_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl RCWSCLRL_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "rcwsclrl",
        aliases: &[],
        opcode: 0x78609000,
        mask: 0xffe0fc00,
        class: InsnClass::THE,
        feature_set: InsnFeatureSet::THE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::THE(THE::RCWSCLRL_Rs_Rt_ADDR_SIMPLE(
            RCWSCLRL_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for RCWSCLRL_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl RCWSCLRP_Rt_Rs_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "rcwsclrp",
        aliases: &[],
        opcode: 0x59209000,
        mask: 0xffe0fc00,
        class: InsnClass::THE,
        feature_set: InsnFeatureSet::D128_THE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::THE(THE::RCWSCLRP_Rt_Rs_ADDR_SIMPLE(
            RCWSCLRP_Rt_Rs_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for RCWSCLRP_Rt_Rs_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl RCWSCLRPA_Rt_Rs_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "rcwsclrpa",
        aliases: &[],
        opcode: 0x59a09000,
        mask: 0xffe0fc00,
        class: InsnClass::THE,
        feature_set: InsnFeatureSet::D128_THE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::THE(THE::RCWSCLRPA_Rt_Rs_ADDR_SIMPLE(
            RCWSCLRPA_Rt_Rs_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for RCWSCLRPA_Rt_Rs_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl RCWSCLRPAL_Rt_Rs_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "rcwsclrpal",
        aliases: &[],
        opcode: 0x59e09000,
        mask: 0xffe0fc00,
        class: InsnClass::THE,
        feature_set: InsnFeatureSet::D128_THE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::THE(THE::RCWSCLRPAL_Rt_Rs_ADDR_SIMPLE(
            RCWSCLRPAL_Rt_Rs_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for RCWSCLRPAL_Rt_Rs_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl RCWSCLRPL_Rt_Rs_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "rcwsclrpl",
        aliases: &[],
        opcode: 0x59609000,
        mask: 0xffe0fc00,
        class: InsnClass::THE,
        feature_set: InsnFeatureSet::D128_THE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::THE(THE::RCWSCLRPL_Rt_Rs_ADDR_SIMPLE(
            RCWSCLRPL_Rt_Rs_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for RCWSCLRPL_Rt_Rs_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl RCWSET_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "rcwset",
        aliases: &[],
        opcode: 0x3820b000,
        mask: 0xffe0fc00,
        class: InsnClass::THE,
        feature_set: InsnFeatureSet::THE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::THE(THE::RCWSET_Rs_Rt_ADDR_SIMPLE(
            RCWSET_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for RCWSET_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl RCWSETA_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "rcwseta",
        aliases: &[],
        opcode: 0x38a0b000,
        mask: 0xffe0fc00,
        class: InsnClass::THE,
        feature_set: InsnFeatureSet::THE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::THE(THE::RCWSETA_Rs_Rt_ADDR_SIMPLE(
            RCWSETA_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for RCWSETA_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl RCWSETAL_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "rcwsetal",
        aliases: &[],
        opcode: 0x38e0b000,
        mask: 0xffe0fc00,
        class: InsnClass::THE,
        feature_set: InsnFeatureSet::THE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::THE(THE::RCWSETAL_Rs_Rt_ADDR_SIMPLE(
            RCWSETAL_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for RCWSETAL_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl RCWSETL_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "rcwsetl",
        aliases: &[],
        opcode: 0x3860b000,
        mask: 0xffe0fc00,
        class: InsnClass::THE,
        feature_set: InsnFeatureSet::THE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::THE(THE::RCWSETL_Rs_Rt_ADDR_SIMPLE(
            RCWSETL_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for RCWSETL_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl RCWSETP_Rt_Rs_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "rcwsetp",
        aliases: &[],
        opcode: 0x1920b000,
        mask: 0xffe0fc00,
        class: InsnClass::THE,
        feature_set: InsnFeatureSet::D128_THE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::THE(THE::RCWSETP_Rt_Rs_ADDR_SIMPLE(
            RCWSETP_Rt_Rs_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for RCWSETP_Rt_Rs_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl RCWSETPA_Rt_Rs_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "rcwsetpa",
        aliases: &[],
        opcode: 0x19a0b000,
        mask: 0xffe0fc00,
        class: InsnClass::THE,
        feature_set: InsnFeatureSet::D128_THE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::THE(THE::RCWSETPA_Rt_Rs_ADDR_SIMPLE(
            RCWSETPA_Rt_Rs_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for RCWSETPA_Rt_Rs_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl RCWSETPAL_Rt_Rs_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "rcwsetpal",
        aliases: &[],
        opcode: 0x19e0b000,
        mask: 0xffe0fc00,
        class: InsnClass::THE,
        feature_set: InsnFeatureSet::D128_THE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::THE(THE::RCWSETPAL_Rt_Rs_ADDR_SIMPLE(
            RCWSETPAL_Rt_Rs_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for RCWSETPAL_Rt_Rs_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl RCWSETPL_Rt_Rs_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "rcwsetpl",
        aliases: &[],
        opcode: 0x1960b000,
        mask: 0xffe0fc00,
        class: InsnClass::THE,
        feature_set: InsnFeatureSet::D128_THE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::THE(THE::RCWSETPL_Rt_Rs_ADDR_SIMPLE(
            RCWSETPL_Rt_Rs_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for RCWSETPL_Rt_Rs_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl RCWSSET_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "rcwsset",
        aliases: &[],
        opcode: 0x7820b000,
        mask: 0xffe0fc00,
        class: InsnClass::THE,
        feature_set: InsnFeatureSet::THE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::THE(THE::RCWSSET_Rs_Rt_ADDR_SIMPLE(
            RCWSSET_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for RCWSSET_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl RCWSSETA_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "rcwsseta",
        aliases: &[],
        opcode: 0x78a0b000,
        mask: 0xffe0fc00,
        class: InsnClass::THE,
        feature_set: InsnFeatureSet::THE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::THE(THE::RCWSSETA_Rs_Rt_ADDR_SIMPLE(
            RCWSSETA_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for RCWSSETA_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl RCWSSETAL_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "rcwssetal",
        aliases: &[],
        opcode: 0x78e0b000,
        mask: 0xffe0fc00,
        class: InsnClass::THE,
        feature_set: InsnFeatureSet::THE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::THE(THE::RCWSSETAL_Rs_Rt_ADDR_SIMPLE(
            RCWSSETAL_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for RCWSSETAL_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl RCWSSETL_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "rcwssetl",
        aliases: &[],
        opcode: 0x7860b000,
        mask: 0xffe0fc00,
        class: InsnClass::THE,
        feature_set: InsnFeatureSet::THE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::THE(THE::RCWSSETL_Rs_Rt_ADDR_SIMPLE(
            RCWSSETL_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for RCWSSETL_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl RCWSSETP_Rt_Rs_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "rcwssetp",
        aliases: &[],
        opcode: 0x5920b000,
        mask: 0xffe0fc00,
        class: InsnClass::THE,
        feature_set: InsnFeatureSet::D128_THE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::THE(THE::RCWSSETP_Rt_Rs_ADDR_SIMPLE(
            RCWSSETP_Rt_Rs_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for RCWSSETP_Rt_Rs_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl RCWSSETPA_Rt_Rs_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "rcwssetpa",
        aliases: &[],
        opcode: 0x59a0b000,
        mask: 0xffe0fc00,
        class: InsnClass::THE,
        feature_set: InsnFeatureSet::D128_THE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::THE(THE::RCWSSETPA_Rt_Rs_ADDR_SIMPLE(
            RCWSSETPA_Rt_Rs_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for RCWSSETPA_Rt_Rs_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl RCWSSETPAL_Rt_Rs_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "rcwssetpal",
        aliases: &[],
        opcode: 0x59e0b000,
        mask: 0xffe0fc00,
        class: InsnClass::THE,
        feature_set: InsnFeatureSet::D128_THE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::THE(THE::RCWSSETPAL_Rt_Rs_ADDR_SIMPLE(
            RCWSSETPAL_Rt_Rs_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for RCWSSETPAL_Rt_Rs_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl RCWSSETPL_Rt_Rs_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "rcwssetpl",
        aliases: &[],
        opcode: 0x5960b000,
        mask: 0xffe0fc00,
        class: InsnClass::THE,
        feature_set: InsnFeatureSet::D128_THE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::THE(THE::RCWSSETPL_Rt_Rs_ADDR_SIMPLE(
            RCWSSETPL_Rt_Rs_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for RCWSSETPL_Rt_Rs_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl RCWSSWP_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "rcwsswp",
        aliases: &[],
        opcode: 0x7820a000,
        mask: 0xffe0fc00,
        class: InsnClass::THE,
        feature_set: InsnFeatureSet::THE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::THE(THE::RCWSSWP_Rs_Rt_ADDR_SIMPLE(
            RCWSSWP_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for RCWSSWP_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl RCWSSWPA_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "rcwsswpa",
        aliases: &[],
        opcode: 0x78a0a000,
        mask: 0xffe0fc00,
        class: InsnClass::THE,
        feature_set: InsnFeatureSet::THE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::THE(THE::RCWSSWPA_Rs_Rt_ADDR_SIMPLE(
            RCWSSWPA_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for RCWSSWPA_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl RCWSSWPAL_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "rcwsswpal",
        aliases: &[],
        opcode: 0x78e0a000,
        mask: 0xffe0fc00,
        class: InsnClass::THE,
        feature_set: InsnFeatureSet::THE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::THE(THE::RCWSSWPAL_Rs_Rt_ADDR_SIMPLE(
            RCWSSWPAL_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for RCWSSWPAL_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl RCWSSWPL_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "rcwsswpl",
        aliases: &[],
        opcode: 0x7860a000,
        mask: 0xffe0fc00,
        class: InsnClass::THE,
        feature_set: InsnFeatureSet::THE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::THE(THE::RCWSSWPL_Rs_Rt_ADDR_SIMPLE(
            RCWSSWPL_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for RCWSSWPL_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl RCWSSWPP_Rt_Rs_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "rcwsswpp",
        aliases: &[],
        opcode: 0x5920a000,
        mask: 0xffe0fc00,
        class: InsnClass::THE,
        feature_set: InsnFeatureSet::D128_THE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::THE(THE::RCWSSWPP_Rt_Rs_ADDR_SIMPLE(
            RCWSSWPP_Rt_Rs_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for RCWSSWPP_Rt_Rs_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl RCWSSWPPA_Rt_Rs_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "rcwsswppa",
        aliases: &[],
        opcode: 0x59a0a000,
        mask: 0xffe0fc00,
        class: InsnClass::THE,
        feature_set: InsnFeatureSet::D128_THE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::THE(THE::RCWSSWPPA_Rt_Rs_ADDR_SIMPLE(
            RCWSSWPPA_Rt_Rs_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for RCWSSWPPA_Rt_Rs_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl RCWSSWPPAL_Rt_Rs_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "rcwsswppal",
        aliases: &[],
        opcode: 0x59e0a000,
        mask: 0xffe0fc00,
        class: InsnClass::THE,
        feature_set: InsnFeatureSet::D128_THE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::THE(THE::RCWSSWPPAL_Rt_Rs_ADDR_SIMPLE(
            RCWSSWPPAL_Rt_Rs_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for RCWSSWPPAL_Rt_Rs_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl RCWSSWPPL_Rt_Rs_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "rcwsswppl",
        aliases: &[],
        opcode: 0x5960a000,
        mask: 0xffe0fc00,
        class: InsnClass::THE,
        feature_set: InsnFeatureSet::D128_THE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::THE(THE::RCWSSWPPL_Rt_Rs_ADDR_SIMPLE(
            RCWSSWPPL_Rt_Rs_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for RCWSSWPPL_Rt_Rs_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl RCWSWP_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "rcwswp",
        aliases: &[],
        opcode: 0x3820a000,
        mask: 0xffe0fc00,
        class: InsnClass::THE,
        feature_set: InsnFeatureSet::THE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::THE(THE::RCWSWP_Rs_Rt_ADDR_SIMPLE(
            RCWSWP_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for RCWSWP_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl RCWSWPA_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "rcwswpa",
        aliases: &[],
        opcode: 0x38a0a000,
        mask: 0xffe0fc00,
        class: InsnClass::THE,
        feature_set: InsnFeatureSet::THE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::THE(THE::RCWSWPA_Rs_Rt_ADDR_SIMPLE(
            RCWSWPA_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for RCWSWPA_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl RCWSWPAL_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "rcwswpal",
        aliases: &[],
        opcode: 0x38e0a000,
        mask: 0xffe0fc00,
        class: InsnClass::THE,
        feature_set: InsnFeatureSet::THE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::THE(THE::RCWSWPAL_Rs_Rt_ADDR_SIMPLE(
            RCWSWPAL_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for RCWSWPAL_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl RCWSWPL_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "rcwswpl",
        aliases: &[],
        opcode: 0x3860a000,
        mask: 0xffe0fc00,
        class: InsnClass::THE,
        feature_set: InsnFeatureSet::THE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::THE(THE::RCWSWPL_Rs_Rt_ADDR_SIMPLE(
            RCWSWPL_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for RCWSWPL_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl RCWSWPP_Rt_Rs_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "rcwswpp",
        aliases: &[],
        opcode: 0x1920a000,
        mask: 0xffe0fc00,
        class: InsnClass::THE,
        feature_set: InsnFeatureSet::D128_THE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::THE(THE::RCWSWPP_Rt_Rs_ADDR_SIMPLE(
            RCWSWPP_Rt_Rs_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for RCWSWPP_Rt_Rs_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl RCWSWPPA_Rt_Rs_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "rcwswppa",
        aliases: &[],
        opcode: 0x19a0a000,
        mask: 0xffe0fc00,
        class: InsnClass::THE,
        feature_set: InsnFeatureSet::D128_THE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::THE(THE::RCWSWPPA_Rt_Rs_ADDR_SIMPLE(
            RCWSWPPA_Rt_Rs_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for RCWSWPPA_Rt_Rs_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl RCWSWPPAL_Rt_Rs_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "rcwswppal",
        aliases: &[],
        opcode: 0x19e0a000,
        mask: 0xffe0fc00,
        class: InsnClass::THE,
        feature_set: InsnFeatureSet::D128_THE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::THE(THE::RCWSWPPAL_Rt_Rs_ADDR_SIMPLE(
            RCWSWPPAL_Rt_Rs_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for RCWSWPPAL_Rt_Rs_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl RCWSWPPL_Rt_Rs_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "rcwswppl",
        aliases: &[],
        opcode: 0x1960a000,
        mask: 0xffe0fc00,
        class: InsnClass::THE,
        feature_set: InsnFeatureSet::D128_THE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::THE(THE::RCWSWPPL_Rt_Rs_ADDR_SIMPLE(
            RCWSWPPL_Rt_Rs_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for RCWSWPPL_Rt_Rs_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl RDFFR_SVE_Pd_SVE_Pg4_5 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "rdffr",
        aliases: &[],
        opcode: 0x2518f000,
        mask: 0xfffffe10,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Pd,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pd,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg4_5,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg4_5,
                    lsb: 5,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::RDFFR_SVE_Pd_SVE_Pg4_5(
            RDFFR_SVE_Pd_SVE_Pg4_5::from(bits),
        ))
    }
}
impl InsnOpcode for RDFFR_SVE_Pd_SVE_Pg4_5 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl RDFFR_SVE_Pd {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "rdffr",
        aliases: &[],
        opcode: 0x2519f000,
        mask: 0xfffffff0,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[InsnOperand {
            kind: InsnOperandKind::SVE_Pd,
            class: InsnOperandClass::PRED_REG,
            qualifiers: &[],
            bit_fields: &[BitfieldSpec {
                bitfield: InsnBitField::SVE_Pd,
                lsb: 0,
                width: 4,
            }],
        }],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::RDFFR_SVE_Pd(RDFFR_SVE_Pd::from(bits)))
    }
}
impl InsnOpcode for RDFFR_SVE_Pd {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl RDFFRS_SVE_Pd_SVE_Pg4_5 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "rdffrs",
        aliases: &[],
        opcode: 0x2558f000,
        mask: 0xfffffe10,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Pd,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pd,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg4_5,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_Z],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg4_5,
                    lsb: 5,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::RDFFRS_SVE_Pd_SVE_Pg4_5(
            RDFFRS_SVE_Pd_SVE_Pg4_5::from(bits),
        ))
    }
}
impl InsnOpcode for RDFFRS_SVE_Pd_SVE_Pg4_5 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl RDSVL_Rd_SVE_SIMM6 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "rdsvl",
        aliases: &[],
        opcode: 0x4bf5800,
        mask: 0xfffff800,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_SIMM6,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_imms,
                    lsb: 5,
                    width: 6,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::RDSVL_Rd_SVE_SIMM6(RDSVL_Rd_SVE_SIMM6::from(bits)))
    }
}
impl InsnOpcode for RDSVL_Rd_SVE_SIMM6 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl RDVL_Rd_SVE_SIMM6 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "rdvl",
        aliases: &[],
        opcode: 0x4bf5000,
        mask: 0xfffff800,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_SIMM6,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_imms,
                    lsb: 5,
                    width: 6,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::RDVL_Rd_SVE_SIMM6(RDVL_Rd_SVE_SIMM6::from(bits)))
    }
}
impl InsnOpcode for RDVL_Rd_SVE_SIMM6 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl RET_Rn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ret",
        aliases: &[],
        opcode: 0xd65f0000,
        mask: 0xfffffc1f,
        class: InsnClass::BRANCH_REG,
        feature_set: InsnFeatureSet::V8,
        operands: &[InsnOperand {
            kind: InsnOperandKind::Rn,
            class: InsnOperandClass::INT_REG,
            qualifiers: &[],
            bit_fields: &[BitfieldSpec {
                bitfield: InsnBitField::Rn,
                lsb: 5,
                width: 5,
            }],
        }],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::BRANCH_REG(BRANCH_REG::RET_Rn(RET_Rn::from(bits)))
    }
}
impl InsnOpcode for RET_Rn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl RETAA {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "retaa",
        aliases: &[],
        opcode: 0xd65f0bff,
        mask: 0xffffffff,
        class: InsnClass::BRANCH_REG,
        feature_set: InsnFeatureSet::PAC,
        operands: &[],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::BRANCH_REG(BRANCH_REG::RETAA(RETAA::from(bits)))
    }
}
impl InsnOpcode for RETAA {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl RETAB {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "retab",
        aliases: &[],
        opcode: 0xd65f0fff,
        mask: 0xffffffff,
        class: InsnClass::BRANCH_REG,
        feature_set: InsnFeatureSet::PAC,
        operands: &[],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::BRANCH_REG(BRANCH_REG::RETAB(RETAB::from(bits)))
    }
}
impl InsnOpcode for RETAB {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl REV_Rd_Rn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "rev",
        aliases: &[],
        opcode: 0x5ac00800,
        mask: 0xfffffc00,
        class: InsnClass::DP_1SRC,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::DP_1SRC(DP_1SRC::REV_Rd_Rn(REV_Rd_Rn::from(bits)))
    }
}
impl InsnOpcode for REV_Rd_Rn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl REV_Rd_X_Rn_X {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "rev",
        aliases: &[],
        opcode: 0xdac00c00,
        mask: 0xfffffc00,
        class: InsnClass::DP_1SRC,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_ALIAS.bits() | InsnFlags::HAS_SF_FIELD.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::DP_1SRC(DP_1SRC::REV_Rd_X_Rn_X(REV_Rd_X_Rn_X::from(bits)))
    }
}
impl InsnOpcode for REV_Rd_X_Rn_X {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl REV_SVE_Zd_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "rev",
        aliases: &[],
        opcode: 0x5383800,
        mask: 0xff3ffc00,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::REV_SVE_Zd_SVE_Zn(REV_SVE_Zd_SVE_Zn::from(
            bits,
        )))
    }
}
impl InsnOpcode for REV_SVE_Zd_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl REV_SVE_Pd_SVE_Pn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "rev",
        aliases: &[],
        opcode: 0x5344000,
        mask: 0xff3ffe10,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Pd,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pd,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pn,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pn,
                    lsb: 5,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::REV_SVE_Pd_SVE_Pn(REV_SVE_Pd_SVE_Pn::from(
            bits,
        )))
    }
}
impl InsnOpcode for REV_SVE_Pd_SVE_Pn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl REV16_Rd_Rn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "rev16",
        aliases: &[],
        opcode: 0x5ac00400,
        mask: 0x7ffffc00,
        class: InsnClass::DP_1SRC,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SF_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::DP_1SRC(DP_1SRC::REV16_Rd_Rn(REV16_Rd_Rn::from(bits)))
    }
}
impl InsnOpcode for REV16_Rd_Rn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl REV16_Vd_Vn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "rev16",
        aliases: &[],
        opcode: 0xe201800,
        mask: 0xbf3ffc00,
        class: InsnClass::ASIMDMISC,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDMISC(ASIMDMISC::REV16_Vd_Vn(REV16_Vd_Vn::from(bits)))
    }
}
impl InsnOpcode for REV16_Vd_Vn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl REV32_Rd_Rn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "rev32",
        aliases: &[],
        opcode: 0xdac00800,
        mask: 0xfffffc00,
        class: InsnClass::DP_1SRC,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::DP_1SRC(DP_1SRC::REV32_Rd_Rn(REV32_Rd_Rn::from(bits)))
    }
}
impl InsnOpcode for REV32_Rd_Rn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl REV32_Vd_Vn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "rev32",
        aliases: &[],
        opcode: 0x2e200800,
        mask: 0xbf3ffc00,
        class: InsnClass::ASIMDMISC,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDMISC(ASIMDMISC::REV32_Vd_Vn(REV32_Vd_Vn::from(bits)))
    }
}
impl InsnOpcode for REV32_Vd_Vn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl REV64_Vd_Vn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "rev64",
        aliases: &[],
        opcode: 0xe200800,
        mask: 0xbf3ffc00,
        class: InsnClass::ASIMDMISC,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDMISC(ASIMDMISC::REV64_Vd_Vn(REV64_Vd_Vn::from(bits)))
    }
}
impl InsnOpcode for REV64_Vd_Vn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl REVB_SVE_Zd_SVE_Pg3_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "revb",
        aliases: &[],
        opcode: 0x5248000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M, InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::REVB_SVE_Zd_SVE_Pg3_SVE_Zn(
            REVB_SVE_Zd_SVE_Pg3_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for REVB_SVE_Zd_SVE_Pg3_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl REVD_SVE_Zd_SVE_Pg3_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "revd",
        aliases: &[],
        opcode: 0x52e8000,
        mask: 0xffffe000,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_Q],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_Q],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::REVD_SVE_Zd_SVE_Pg3_SVE_Zn(
            REVD_SVE_Zd_SVE_Pg3_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for REVD_SVE_Zd_SVE_Pg3_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl REVH_SVE_Zd_SVE_Pg3_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "revh",
        aliases: &[],
        opcode: 0x5a58000,
        mask: 0xffbfe000,
        class: InsnClass::SVE_SIZE_SD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M, InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_SD(SVE_SIZE_SD::REVH_SVE_Zd_SVE_Pg3_SVE_Zn(
            REVH_SVE_Zd_SVE_Pg3_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for REVH_SVE_Zd_SVE_Pg3_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl REVW_SVE_Zd_SVE_Pg3_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "revw",
        aliases: &[],
        opcode: 0x5e68000,
        mask: 0xffffe000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::REVW_SVE_Zd_SVE_Pg3_SVE_Zn(
            REVW_SVE_Zd_SVE_Pg3_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for REVW_SVE_Zd_SVE_Pg3_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl RMIF_Rn_IMM_2_MASK {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "rmif",
        aliases: &[],
        opcode: 0xba000400,
        mask: 0xffe07c10,
        class: InsnClass::IC_SYSTEM,
        feature_set: InsnFeatureSet::FLAGM,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::IMM_2,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[InsnOperandQualifier::imm_0_63],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::imm6_15,
                    lsb: 15,
                    width: 6,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MASK,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[InsnOperandQualifier::imm_0_15],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::imm4_0,
                    lsb: 0,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::IC_SYSTEM(IC_SYSTEM::RMIF_Rn_IMM_2_MASK(RMIF_Rn_IMM_2_MASK::from(
            bits,
        )))
    }
}
impl InsnOpcode for RMIF_Rn_IMM_2_MASK {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl RORV_Rd_Rn_Rm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "rorv",
        aliases: &[],
        opcode: 0x1ac02c00,
        mask: 0x7fe0fc00,
        class: InsnClass::DP_2SRC,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rm,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_ALIAS.bits() | InsnFlags::HAS_SF_FIELD.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::DP_2SRC(DP_2SRC::RORV_Rd_Rn_Rm(RORV_Rd_Rn_Rm::from(bits)))
    }
}
impl InsnOpcode for RORV_Rd_Rn_Rm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl RPRFM_RPRFMOP_Rm_SIMD_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "rprfm",
        aliases: &[],
        opcode: 0xf8a04818,
        mask: 0xffe04c18,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::RPRFMOP,
                class: InsnOperandClass::SYSTEM,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::imm1_15,
                        lsb: 15,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_12,
                        lsb: 12,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_0,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::Rm,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SIMD_ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::RPRFM_RPRFMOP_Rm_SIMD_ADDR_SIMPLE(
            RPRFM_RPRFMOP_Rm_SIMD_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for RPRFM_RPRFMOP_Rm_SIMD_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl RSHRN_Vd_Vn_IMM_VLSR {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "rshrn",
        aliases: &[],
        opcode: 0xf008c00,
        mask: 0xff80fc00,
        class: InsnClass::ASIMDSHF,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_4H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8H, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::IMM_VLSR,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_4H],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSHF(ASIMDSHF::RSHRN_Vd_Vn_IMM_VLSR(RSHRN_Vd_Vn_IMM_VLSR::from(
            bits,
        )))
    }
}
impl InsnOpcode for RSHRN_Vd_Vn_IMM_VLSR {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl RSHRN2_Vd_Vn_IMM_VLSR {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "rshrn2",
        aliases: &[],
        opcode: 0x4f008c00,
        mask: 0xff80fc00,
        class: InsnClass::ASIMDSHF,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_16B, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8H, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::IMM_VLSR,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[InsnOperandQualifier::V_16B, InsnOperandQualifier::V_8H],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSHF(ASIMDSHF::RSHRN2_Vd_Vn_IMM_VLSR(
            RSHRN2_Vd_Vn_IMM_VLSR::from(bits),
        ))
    }
}
impl InsnOpcode for RSHRN2_Vd_Vn_IMM_VLSR {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl RSHRNB_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "rshrnb",
        aliases: &[],
        opcode: 0x45201800,
        mask: 0xffa0fc00,
        class: InsnClass::SVE_SHIFT_TSZ_HSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_SHRIMM_UNPRED_22,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_sz,
                        lsb: 22,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_tszl_19,
                        lsb: 19,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_imm3,
                        lsb: 16,
                        width: 3,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SHIFT_TSZ_HSD(
            SVE_SHIFT_TSZ_HSD::RSHRNB_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22(
                RSHRNB_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22::from(bits),
            ),
        )
    }
}
impl InsnOpcode for RSHRNB_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl RSHRNT_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "rshrnt",
        aliases: &[],
        opcode: 0x45201c00,
        mask: 0xffa0fc00,
        class: InsnClass::SVE_SHIFT_TSZ_HSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_SHRIMM_UNPRED_22,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_sz,
                        lsb: 22,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_tszl_19,
                        lsb: 19,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_imm3,
                        lsb: 16,
                        width: 3,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SHIFT_TSZ_HSD(
            SVE_SHIFT_TSZ_HSD::RSHRNT_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22(
                RSHRNT_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22::from(bits),
            ),
        )
    }
}
impl InsnOpcode for RSHRNT_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl RSUBHN_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "rsubhn",
        aliases: &[],
        opcode: 0x2e206000,
        mask: 0xff20fc00,
        class: InsnClass::ASIMDDIFF,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_4H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8H, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8H, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDDIFF(ASIMDDIFF::RSUBHN_Vd_Vn_Vm(RSUBHN_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for RSUBHN_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl RSUBHN2_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "rsubhn2",
        aliases: &[],
        opcode: 0x6e206000,
        mask: 0xff20fc00,
        class: InsnClass::ASIMDDIFF,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_16B, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8H, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8H, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDDIFF(ASIMDDIFF::RSUBHN2_Vd_Vn_Vm(RSUBHN2_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for RSUBHN2_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl RSUBHNB_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "rsubhnb",
        aliases: &[],
        opcode: 0x45207800,
        mask: 0xff20fc00,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::RSUBHNB_SVE_Zd_SVE_Zn_SVE_Zm_16(
            RSUBHNB_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for RSUBHNB_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl RSUBHNT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "rsubhnt",
        aliases: &[],
        opcode: 0x45207c00,
        mask: 0xff20fc00,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::RSUBHNT_SVE_Zd_SVE_Zn_SVE_Zm_16(
            RSUBHNT_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for RSUBHNT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SABA_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "saba",
        aliases: &[],
        opcode: 0x4500f800,
        mask: 0xff20fc00,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::SABA_SVE_Zd_SVE_Zn_SVE_Zm_16(
            SABA_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for SABA_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SABA_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "saba",
        aliases: &[],
        opcode: 0xe207c00,
        mask: 0xbf20fc00,
        class: InsnClass::ASIMDSAME,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSAME(ASIMDSAME::SABA_Vd_Vn_Vm(SABA_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for SABA_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SABAL_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sabal",
        aliases: &[],
        opcode: 0xe205000,
        mask: 0xff20fc00,
        class: InsnClass::ASIMDDIFF,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8H, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_4H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_4H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDDIFF(ASIMDDIFF::SABAL_Vd_Vn_Vm(SABAL_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for SABAL_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SABAL2_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sabal2",
        aliases: &[],
        opcode: 0x4e205000,
        mask: 0xff20fc00,
        class: InsnClass::ASIMDDIFF,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8H, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_16B, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_16B, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDDIFF(ASIMDDIFF::SABAL2_Vd_Vn_Vm(SABAL2_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for SABAL2_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SABALB_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sabalb",
        aliases: &[],
        opcode: 0x4500c000,
        mask: 0xff20fc00,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::SABALB_SVE_Zd_SVE_Zn_SVE_Zm_16(
            SABALB_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for SABALB_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SABALT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sabalt",
        aliases: &[],
        opcode: 0x4500c400,
        mask: 0xff20fc00,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::SABALT_SVE_Zd_SVE_Zn_SVE_Zm_16(
            SABALT_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for SABALT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SABD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sabd",
        aliases: &[],
        opcode: 0x40c0000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_5,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_5,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::SABD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(
            SABD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5::from(bits),
        ))
    }
}
impl InsnOpcode for SABD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SABD_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sabd",
        aliases: &[],
        opcode: 0xe207400,
        mask: 0xbf20fc00,
        class: InsnClass::ASIMDSAME,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSAME(ASIMDSAME::SABD_Vd_Vn_Vm(SABD_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for SABD_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SABDL_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sabdl",
        aliases: &[],
        opcode: 0xe207000,
        mask: 0xff20fc00,
        class: InsnClass::ASIMDDIFF,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8H, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_4H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_4H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDDIFF(ASIMDDIFF::SABDL_Vd_Vn_Vm(SABDL_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for SABDL_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SABDL2_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sabdl2",
        aliases: &[],
        opcode: 0x4e207000,
        mask: 0xff20fc00,
        class: InsnClass::ASIMDDIFF,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8H, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_16B, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_16B, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDDIFF(ASIMDDIFF::SABDL2_Vd_Vn_Vm(SABDL2_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for SABDL2_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SABDLB_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sabdlb",
        aliases: &[],
        opcode: 0x45003000,
        mask: 0xff20fc00,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::SABDLB_SVE_Zd_SVE_Zn_SVE_Zm_16(
            SABDLB_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for SABDLB_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SABDLT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sabdlt",
        aliases: &[],
        opcode: 0x45003400,
        mask: 0xff20fc00,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::SABDLT_SVE_Zd_SVE_Zn_SVE_Zm_16(
            SABDLT_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for SABDLT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SADALP_SVE_Zd_SVE_Pg3_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sadalp",
        aliases: &[],
        opcode: 0x4404a000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M, InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::SADALP_SVE_Zd_SVE_Pg3_SVE_Zn(
            SADALP_SVE_Zd_SVE_Pg3_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for SADALP_SVE_Zd_SVE_Pg3_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SADALP_Vd_Vn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sadalp",
        aliases: &[],
        opcode: 0xe206800,
        mask: 0xbf3ffc00,
        class: InsnClass::ASIMDMISC,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDMISC(ASIMDMISC::SADALP_Vd_Vn(SADALP_Vd_Vn::from(bits)))
    }
}
impl InsnOpcode for SADALP_Vd_Vn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SADDL_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "saddl",
        aliases: &[],
        opcode: 0xe200000,
        mask: 0xff20fc00,
        class: InsnClass::ASIMDDIFF,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8H, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_4H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_4H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDDIFF(ASIMDDIFF::SADDL_Vd_Vn_Vm(SADDL_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for SADDL_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SADDL2_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "saddl2",
        aliases: &[],
        opcode: 0x4e200000,
        mask: 0xff20fc00,
        class: InsnClass::ASIMDDIFF,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8H, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_16B, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_16B, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDDIFF(ASIMDDIFF::SADDL2_Vd_Vn_Vm(SADDL2_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for SADDL2_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SADDLB_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "saddlb",
        aliases: &[],
        opcode: 0x45000000,
        mask: 0xff20fc00,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::SADDLB_SVE_Zd_SVE_Zn_SVE_Zm_16(
            SADDLB_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for SADDLB_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SADDLBT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "saddlbt",
        aliases: &[],
        opcode: 0x45008000,
        mask: 0xff20fc00,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::SADDLBT_SVE_Zd_SVE_Zn_SVE_Zm_16(
            SADDLBT_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for SADDLBT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SADDLP_Vd_Vn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "saddlp",
        aliases: &[],
        opcode: 0xe202800,
        mask: 0xbf3ffc00,
        class: InsnClass::ASIMDMISC,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDMISC(ASIMDMISC::SADDLP_Vd_Vn(SADDLP_Vd_Vn::from(bits)))
    }
}
impl InsnOpcode for SADDLP_Vd_Vn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SADDLT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "saddlt",
        aliases: &[],
        opcode: 0x45000400,
        mask: 0xff20fc00,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::SADDLT_SVE_Zd_SVE_Zn_SVE_Zm_16(
            SADDLT_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for SADDLT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SADDLV_Fd_Vn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "saddlv",
        aliases: &[],
        opcode: 0xe303800,
        mask: 0xbf3ffc00,
        class: InsnClass::ASIMDALL,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Fd,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDALL(ASIMDALL::SADDLV_Fd_Vn(SADDLV_Fd_Vn::from(bits)))
    }
}
impl InsnOpcode for SADDLV_Fd_Vn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SADDV_SVE_Vd_SVE_Pg3_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "saddv",
        aliases: &[],
        opcode: 0x4002000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_BHS,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::S_D, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Vd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHS(SVE_SIZE_BHS::SADDV_SVE_Vd_SVE_Pg3_SVE_Zn(
            SADDV_SVE_Vd_SVE_Pg3_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for SADDV_SVE_Vd_SVE_Pg3_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SADDW_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "saddw",
        aliases: &[],
        opcode: 0xe201000,
        mask: 0xff20fc00,
        class: InsnClass::ASIMDDIFF,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8H, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8H, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_4H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDDIFF(ASIMDDIFF::SADDW_Vd_Vn_Vm(SADDW_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for SADDW_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SADDW2_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "saddw2",
        aliases: &[],
        opcode: 0x4e201000,
        mask: 0xff20fc00,
        class: InsnClass::ASIMDDIFF,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8H, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8H, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_16B, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDDIFF(ASIMDDIFF::SADDW2_Vd_Vn_Vm(SADDW2_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for SADDW2_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SADDWB_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "saddwb",
        aliases: &[],
        opcode: 0x45004000,
        mask: 0xff20fc00,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::SADDWB_SVE_Zd_SVE_Zn_SVE_Zm_16(
            SADDWB_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for SADDWB_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SADDWT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "saddwt",
        aliases: &[],
        opcode: 0x45004400,
        mask: 0xff20fc00,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::SADDWT_SVE_Zd_SVE_Zn_SVE_Zm_16(
            SADDWT_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for SADDWT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SB {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sb",
        aliases: &[],
        opcode: 0xd50330ff,
        mask: 0xffffffff,
        class: InsnClass::IC_SYSTEM,
        feature_set: InsnFeatureSet::SB,
        operands: &[],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::IC_SYSTEM(IC_SYSTEM::SB(SB::from(bits)))
    }
}
impl InsnOpcode for SB {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SBC_Rd_Rn_Rm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sbc",
        aliases: &[],
        opcode: 0x5a000000,
        mask: 0x7fe0fc00,
        class: InsnClass::ADDSUB_CARRY,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rm,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_ALIAS.bits() | InsnFlags::HAS_SF_FIELD.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ADDSUB_CARRY(ADDSUB_CARRY::SBC_Rd_Rn_Rm(SBC_Rd_Rn_Rm::from(bits)))
    }
}
impl InsnOpcode for SBC_Rd_Rn_Rm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SBCLB_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sbclb",
        aliases: &[],
        opcode: 0x4580d000,
        mask: 0xffa0fc00,
        class: InsnClass::SVE_SIZE_SD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_SD(SVE_SIZE_SD::SBCLB_SVE_Zd_SVE_Zn_SVE_Zm_16(
            SBCLB_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for SBCLB_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SBCLT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sbclt",
        aliases: &[],
        opcode: 0x4580d400,
        mask: 0xffa0fc00,
        class: InsnClass::SVE_SIZE_SD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_SD(SVE_SIZE_SD::SBCLT_SVE_Zd_SVE_Zn_SVE_Zm_16(
            SBCLT_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for SBCLT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SBCS_Rd_Rn_Rm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sbcs",
        aliases: &[],
        opcode: 0x7a000000,
        mask: 0x7fe0fc00,
        class: InsnClass::ADDSUB_CARRY,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rm,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_ALIAS.bits() | InsnFlags::HAS_SF_FIELD.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ADDSUB_CARRY(ADDSUB_CARRY::SBCS_Rd_Rn_Rm(SBCS_Rd_Rn_Rm::from(bits)))
    }
}
impl InsnOpcode for SBCS_Rd_Rn_Rm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SBFM_Rd_Rn_IMMR_IMMS {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sbfm",
        aliases: &[],
        opcode: 0x13000000,
        mask: 0x7f800000,
        class: InsnClass::BITFIELD,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::IMMR,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[
                    InsnOperandQualifier::imm_0_31,
                    InsnOperandQualifier::imm_0_63,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::immr,
                    lsb: 16,
                    width: 6,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::IMMS,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[
                    InsnOperandQualifier::imm_0_31,
                    InsnOperandQualifier::imm_0_63,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::imm6_10,
                    lsb: 10,
                    width: 6,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_ALIAS.bits()
                | InsnFlags::HAS_N_FIELD.bits()
                | InsnFlags::HAS_SF_FIELD.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::BITFIELD(BITFIELD::SBFM_Rd_Rn_IMMR_IMMS(SBFM_Rd_Rn_IMMR_IMMS::from(
            bits,
        )))
    }
}
impl InsnOpcode for SBFM_Rd_Rn_IMMR_IMMS {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SCLAMP_SME_Zdnx2_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sclamp",
        aliases: &[],
        opcode: 0xc120c400,
        mask: 0xff20fc01,
        class: InsnClass::SME_SIZE_22,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn2,
                    lsb: 1,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_SIZE_22(SME_SIZE_22::SCLAMP_SME_Zdnx2_SVE_Zn_SVE_Zm_16(
            SCLAMP_SME_Zdnx2_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for SCLAMP_SME_Zdnx2_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SCLAMP_SME_Zdnx4_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sclamp",
        aliases: &[],
        opcode: 0xc120cc00,
        mask: 0xff20fc03,
        class: InsnClass::SME_SIZE_22,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn4,
                    lsb: 2,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_SIZE_22(SME_SIZE_22::SCLAMP_SME_Zdnx4_SVE_Zn_SVE_Zm_16(
            SCLAMP_SME_Zdnx4_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for SCLAMP_SME_Zdnx4_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SCLAMP_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sclamp",
        aliases: &[],
        opcode: 0x4400c000,
        mask: 0xff20fc00,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SME,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::SCLAMP_SVE_Zd_SVE_Zn_SVE_Zm_16(
            SCLAMP_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for SCLAMP_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SCVTF_SME_Zdnx2_SME_Znx2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "scvtf",
        aliases: &[],
        opcode: 0xc122e000,
        mask: 0xfffffc21,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn2,
                    lsb: 1,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn2,
                    lsb: 6,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::SCVTF_SME_Zdnx2_SME_Znx2(
            SCVTF_SME_Zdnx2_SME_Znx2::from(bits),
        ))
    }
}
impl InsnOpcode for SCVTF_SME_Zdnx2_SME_Znx2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SCVTF_SME_Zdnx4_SME_Znx4 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "scvtf",
        aliases: &[],
        opcode: 0xc132e000,
        mask: 0xfffffc63,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn4,
                    lsb: 2,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn4,
                    lsb: 7,
                    width: 3,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::SCVTF_SME_Zdnx4_SME_Znx4(
            SCVTF_SME_Zdnx4_SME_Znx4::from(bits),
        ))
    }
}
impl InsnOpcode for SCVTF_SME_Zdnx4_SME_Znx4 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SCVTF_SVE_Zd_SVE_Pg3_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "scvtf",
        aliases: &[],
        opcode: 0x65d0a000,
        mask: 0xffffe000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::SCVTF_SVE_Zd_SVE_Pg3_SVE_Zn(
            SCVTF_SVE_Zd_SVE_Pg3_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for SCVTF_SVE_Zd_SVE_Pg3_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SCVTF_SVE_Zd_S_S_SVE_Pg3_P_M_SVE_Zn_S_S {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "scvtf",
        aliases: &[],
        opcode: 0x6594a000,
        mask: 0xffffe000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::SCVTF_SVE_Zd_S_S_SVE_Pg3_P_M_SVE_Zn_S_S(
            SCVTF_SVE_Zd_S_S_SVE_Pg3_P_M_SVE_Zn_S_S::from(bits),
        ))
    }
}
impl InsnOpcode for SCVTF_SVE_Zd_S_S_SVE_Pg3_P_M_SVE_Zn_S_S {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SCVTF_SVE_Zd_S_H_SVE_Pg3_P_M_SVE_Zn_S_S {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "scvtf",
        aliases: &[],
        opcode: 0x6554a000,
        mask: 0xffffe000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::SCVTF_SVE_Zd_S_H_SVE_Pg3_P_M_SVE_Zn_S_S(
            SCVTF_SVE_Zd_S_H_SVE_Pg3_P_M_SVE_Zn_S_S::from(bits),
        ))
    }
}
impl InsnOpcode for SCVTF_SVE_Zd_S_H_SVE_Pg3_P_M_SVE_Zn_S_S {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SCVTF_SVE_Zd_S_S_SVE_Pg3_P_M_SVE_Zn_S_D {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "scvtf",
        aliases: &[],
        opcode: 0x65d4a000,
        mask: 0xffffe000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::SCVTF_SVE_Zd_S_S_SVE_Pg3_P_M_SVE_Zn_S_D(
            SCVTF_SVE_Zd_S_S_SVE_Pg3_P_M_SVE_Zn_S_D::from(bits),
        ))
    }
}
impl InsnOpcode for SCVTF_SVE_Zd_S_S_SVE_Pg3_P_M_SVE_Zn_S_D {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SCVTF_SVE_Zd_S_H_SVE_Pg3_P_M_SVE_Zn_S_H {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "scvtf",
        aliases: &[],
        opcode: 0x6552a000,
        mask: 0xffffe000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::SCVTF_SVE_Zd_S_H_SVE_Pg3_P_M_SVE_Zn_S_H(
            SCVTF_SVE_Zd_S_H_SVE_Pg3_P_M_SVE_Zn_S_H::from(bits),
        ))
    }
}
impl InsnOpcode for SCVTF_SVE_Zd_S_H_SVE_Pg3_P_M_SVE_Zn_S_H {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SCVTF_SVE_Zd_S_H_SVE_Pg3_P_M_SVE_Zn_S_D {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "scvtf",
        aliases: &[],
        opcode: 0x6556a000,
        mask: 0xffffe000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::SCVTF_SVE_Zd_S_H_SVE_Pg3_P_M_SVE_Zn_S_D(
            SCVTF_SVE_Zd_S_H_SVE_Pg3_P_M_SVE_Zn_S_D::from(bits),
        ))
    }
}
impl InsnOpcode for SCVTF_SVE_Zd_S_H_SVE_Pg3_P_M_SVE_Zn_S_D {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SCVTF_SVE_Zd_S_D_SVE_Pg3_P_M_SVE_Zn_S_D {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "scvtf",
        aliases: &[],
        opcode: 0x65d6a000,
        mask: 0xffffe000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::SCVTF_SVE_Zd_S_D_SVE_Pg3_P_M_SVE_Zn_S_D(
            SCVTF_SVE_Zd_S_D_SVE_Pg3_P_M_SVE_Zn_S_D::from(bits),
        ))
    }
}
impl InsnOpcode for SCVTF_SVE_Zd_S_D_SVE_Pg3_P_M_SVE_Zn_S_D {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SCVTF_Fd_Rn_FBITS {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "scvtf",
        aliases: &[],
        opcode: 0x1ec20000,
        mask: 0x7fff0000,
        class: InsnClass::FLOAT2FIX,
        feature_set: InsnFeatureSet::FP_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Fd,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::FBITS,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[
                    InsnOperandQualifier::imm_1_32,
                    InsnOperandQualifier::imm_1_64,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::scale,
                    lsb: 10,
                    width: 6,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_FPTYPE_FIELD.bits() | InsnFlags::HAS_SF_FIELD.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::FLOAT2FIX(FLOAT2FIX::SCVTF_Fd_Rn_FBITS(SCVTF_Fd_Rn_FBITS::from(bits)))
    }
}
impl InsnOpcode for SCVTF_Fd_Rn_FBITS {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SCVTF_Fd_S_D_Rn_W_FBITS_imm_1_32 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "scvtf",
        aliases: &[],
        opcode: 0x1e020000,
        mask: 0x7f3f0000,
        class: InsnClass::FLOAT2FIX,
        feature_set: InsnFeatureSet::FP,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Fd,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_D, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::FBITS,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[
                    InsnOperandQualifier::imm_1_32,
                    InsnOperandQualifier::imm_1_32,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::scale,
                    lsb: 10,
                    width: 6,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_FPTYPE_FIELD.bits() | InsnFlags::HAS_SF_FIELD.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::FLOAT2FIX(FLOAT2FIX::SCVTF_Fd_S_D_Rn_W_FBITS_imm_1_32(
            SCVTF_Fd_S_D_Rn_W_FBITS_imm_1_32::from(bits),
        ))
    }
}
impl InsnOpcode for SCVTF_Fd_S_D_Rn_W_FBITS_imm_1_32 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SCVTF_Vd_Vn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "scvtf",
        aliases: &[],
        opcode: 0xe21d800,
        mask: 0xbfbffc00,
        class: InsnClass::ASIMDMISC,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDMISC(ASIMDMISC::SCVTF_Vd_Vn(SCVTF_Vd_Vn::from(bits)))
    }
}
impl InsnOpcode for SCVTF_Vd_Vn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SCVTF_Vd_V_4H_Vn_V_4H {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "scvtf",
        aliases: &[],
        opcode: 0xe79d800,
        mask: 0xbffffc00,
        class: InsnClass::ASIMDMISC,
        feature_set: InsnFeatureSet::SIMD_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDMISC(ASIMDMISC::SCVTF_Vd_V_4H_Vn_V_4H(
            SCVTF_Vd_V_4H_Vn_V_4H::from(bits),
        ))
    }
}
impl InsnOpcode for SCVTF_Vd_V_4H_Vn_V_4H {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SCVTF_Fd_Rn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "scvtf",
        aliases: &[],
        opcode: 0x1ee20000,
        mask: 0x7ffffc00,
        class: InsnClass::FLOAT2INT,
        feature_set: InsnFeatureSet::FP_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Fd,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_FPTYPE_FIELD.bits() | InsnFlags::HAS_SF_FIELD.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::FLOAT2INT(FLOAT2INT::SCVTF_Fd_Rn(SCVTF_Fd_Rn::from(bits)))
    }
}
impl InsnOpcode for SCVTF_Fd_Rn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SCVTF_Fd_S_D_Rn_W {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "scvtf",
        aliases: &[],
        opcode: 0x1e220000,
        mask: 0x7f3ffc00,
        class: InsnClass::FLOAT2INT,
        feature_set: InsnFeatureSet::FP,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Fd,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_FPTYPE_FIELD.bits() | InsnFlags::HAS_SF_FIELD.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::FLOAT2INT(FLOAT2INT::SCVTF_Fd_S_D_Rn_W(SCVTF_Fd_S_D_Rn_W::from(bits)))
    }
}
impl InsnOpcode for SCVTF_Fd_S_D_Rn_W {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SCVTF_Sd_Sn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "scvtf",
        aliases: &[],
        opcode: 0x5e21d800,
        mask: 0xffbffc00,
        class: InsnClass::ASISDMISC,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMD_SCALAR_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDMISC(ASISDMISC::SCVTF_Sd_Sn(SCVTF_Sd_Sn::from(bits)))
    }
}
impl InsnOpcode for SCVTF_Sd_Sn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SCVTF_Sd_S_H_Sn_S_H {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "scvtf",
        aliases: &[],
        opcode: 0x5e79d800,
        mask: 0xfffffc00,
        class: InsnClass::ASISDMISC,
        feature_set: InsnFeatureSet::SIMD_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMD_SCALAR_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDMISC(ASISDMISC::SCVTF_Sd_S_H_Sn_S_H(SCVTF_Sd_S_H_Sn_S_H::from(
            bits,
        )))
    }
}
impl InsnOpcode for SCVTF_Sd_S_H_Sn_S_H {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SCVTF_Vd_Vn_IMM_VLSR {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "scvtf",
        aliases: &[],
        opcode: 0xf10e400,
        mask: 0xbf90fc00,
        class: InsnClass::ASIMDSHF,
        feature_set: InsnFeatureSet::SIMD_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::IMM_VLSR,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSHF(ASIMDSHF::SCVTF_Vd_Vn_IMM_VLSR(SCVTF_Vd_Vn_IMM_VLSR::from(
            bits,
        )))
    }
}
impl InsnOpcode for SCVTF_Vd_Vn_IMM_VLSR {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SCVTF_Vd_V_2S_Vn_V_2S_IMM_VLSR_V_2S {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "scvtf",
        aliases: &[],
        opcode: 0xf00e400,
        mask: 0xbf80fc00,
        class: InsnClass::ASIMDSHF,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::IMM_VLSR,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[InsnOperandQualifier::V_2S, InsnOperandQualifier::V_4S],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSHF(ASIMDSHF::SCVTF_Vd_V_2S_Vn_V_2S_IMM_VLSR_V_2S(
            SCVTF_Vd_V_2S_Vn_V_2S_IMM_VLSR_V_2S::from(bits),
        ))
    }
}
impl InsnOpcode for SCVTF_Vd_V_2S_Vn_V_2S_IMM_VLSR_V_2S {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SCVTF_Sd_Sn_IMM_VLSR {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "scvtf",
        aliases: &[],
        opcode: 0x5f10e400,
        mask: 0xff90fc00,
        class: InsnClass::ASISDSHF,
        feature_set: InsnFeatureSet::SIMD_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::IMM_VLSR,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDSHF(ASISDSHF::SCVTF_Sd_Sn_IMM_VLSR(SCVTF_Sd_Sn_IMM_VLSR::from(
            bits,
        )))
    }
}
impl InsnOpcode for SCVTF_Sd_Sn_IMM_VLSR {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SCVTF_Sd_S_S_Sn_S_S_IMM_VLSR_S_S {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "scvtf",
        aliases: &[],
        opcode: 0x5f00e400,
        mask: 0xff80fc00,
        class: InsnClass::ASISDSHF,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::IMM_VLSR,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDSHF(ASISDSHF::SCVTF_Sd_S_S_Sn_S_S_IMM_VLSR_S_S(
            SCVTF_Sd_S_S_Sn_S_S_IMM_VLSR_S_S::from(bits),
        ))
    }
}
impl InsnOpcode for SCVTF_Sd_S_S_Sn_S_S_IMM_VLSR_S_S {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SDIV_Rd_Rn_Rm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sdiv",
        aliases: &[],
        opcode: 0x1ac00c00,
        mask: 0x7fe0fc00,
        class: InsnClass::DP_2SRC,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rm,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SF_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::DP_2SRC(DP_2SRC::SDIV_Rd_Rn_Rm(SDIV_Rd_Rn_Rm::from(bits)))
    }
}
impl InsnOpcode for SDIV_Rd_Rn_Rm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SDIV_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sdiv",
        aliases: &[],
        opcode: 0x4940000,
        mask: 0xffbfe000,
        class: InsnClass::SVE_SIZE_SD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M, InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_5,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_5,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_SD(SVE_SIZE_SD::SDIV_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(
            SDIV_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5::from(bits),
        ))
    }
}
impl InsnOpcode for SDIV_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SDIVR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sdivr",
        aliases: &[],
        opcode: 0x4960000,
        mask: 0xffbfe000,
        class: InsnClass::SVE_SIZE_SD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M, InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_5,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_5,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_SD(SVE_SIZE_SD::SDIVR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(
            SDIVR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5::from(bits),
        ))
    }
}
impl InsnOpcode for SDIVR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sdot",
        aliases: &[],
        opcode: 0xc1501000,
        mask: 0xfff09038,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off3_0,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_0,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn2,
                    lsb: 6,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm_INDEX2,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zm,
                        lsb: 16,
                        width: 4,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_10,
                        lsb: 10,
                        width: 2,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::SDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2(
            SDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2::from(bits),
        ))
    }
}
impl InsnOpcode for SDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SDOT_SME_ZA_array_off3_0_S_S_SME_Znx2_S_B_SME_Zm_INDEX2_S_B {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sdot",
        aliases: &[],
        opcode: 0xc1501020,
        mask: 0xfff09038,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off3_0,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_0,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn2,
                    lsb: 6,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm_INDEX2,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zm,
                        lsb: 16,
                        width: 4,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_10,
                        lsb: 10,
                        width: 2,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(
            SME_MISC::SDOT_SME_ZA_array_off3_0_S_S_SME_Znx2_S_B_SME_Zm_INDEX2_S_B(
                SDOT_SME_ZA_array_off3_0_S_S_SME_Znx2_S_B_SME_Zm_INDEX2_S_B::from(bits),
            ),
        )
    }
}
impl InsnOpcode for SDOT_SME_ZA_array_off3_0_S_S_SME_Znx2_S_B_SME_Zm_INDEX2_S_B {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sdot",
        aliases: &[],
        opcode: 0xc1509000,
        mask: 0xfff09078,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off3_0,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_0,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn4,
                    lsb: 7,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm_INDEX2,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zm,
                        lsb: 16,
                        width: 4,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_10,
                        lsb: 10,
                        width: 2,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_4.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::SDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2(
            SDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2::from(bits),
        ))
    }
}
impl InsnOpcode for SDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SDOT_SME_ZA_array_off3_0_S_S_SME_Znx4_S_B_SME_Zm_INDEX2_S_B {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sdot",
        aliases: &[],
        opcode: 0xc1509020,
        mask: 0xfff09078,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off3_0,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_0,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn4,
                    lsb: 7,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm_INDEX2,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zm,
                        lsb: 16,
                        width: 4,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_10,
                        lsb: 10,
                        width: 2,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_4.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(
            SME_MISC::SDOT_SME_ZA_array_off3_0_S_S_SME_Znx4_S_B_SME_Zm_INDEX2_S_B(
                SDOT_SME_ZA_array_off3_0_S_S_SME_Znx4_S_B_SME_Zm_INDEX2_S_B::from(bits),
            ),
        )
    }
}
impl InsnOpcode for SDOT_SME_ZA_array_off3_0_S_S_SME_Znx4_S_B_SME_Zm_INDEX2_S_B {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX1 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sdot",
        aliases: &[],
        opcode: 0xc1d00008,
        mask: 0xfff09838,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2_I16I64,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off3_0,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_0,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn2,
                    lsb: 6,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm_INDEX1,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zm,
                        lsb: 16,
                        width: 4,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm1_10,
                        lsb: 10,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::SDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX1(
            SDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX1::from(bits),
        ))
    }
}
impl InsnOpcode for SDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX1 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX1 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sdot",
        aliases: &[],
        opcode: 0xc1d08008,
        mask: 0xfff09878,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2_I16I64,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off3_0,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_0,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn4,
                    lsb: 7,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm_INDEX1,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zm,
                        lsb: 16,
                        width: 4,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm1_10,
                        lsb: 10,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_4.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::SDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX1(
            SDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX1::from(bits),
        ))
    }
}
impl InsnOpcode for SDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX1 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SDOT_SME_ZA_array_off3_0_SVE_ZnxN_SME_Zm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sdot",
        aliases: &[],
        opcode: 0xc1201400,
        mask: 0xffb09c18,
        class: InsnClass::SME_INT_SD,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off3_0,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_0,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ZnxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm,
                    lsb: 16,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_INT_SD(SME_INT_SD::SDOT_SME_ZA_array_off3_0_SVE_ZnxN_SME_Zm(
            SDOT_SME_ZA_array_off3_0_SVE_ZnxN_SME_Zm::from(bits),
        ))
    }
}
impl InsnOpcode for SDOT_SME_ZA_array_off3_0_SVE_ZnxN_SME_Zm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SDOT_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_B_SME_Zm_S_B {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sdot",
        aliases: &[],
        opcode: 0xc1301400,
        mask: 0xffb09c18,
        class: InsnClass::SME_INT_SD,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off3_0,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_0,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ZnxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm,
                    lsb: 16,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_4.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_INT_SD(
            SME_INT_SD::SDOT_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_B_SME_Zm_S_B(
                SDOT_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_B_SME_Zm_S_B::from(bits),
            ),
        )
    }
}
impl InsnOpcode for SDOT_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_B_SME_Zm_S_B {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zmx2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sdot",
        aliases: &[],
        opcode: 0xc1a01400,
        mask: 0xffa19c38,
        class: InsnClass::SME_INT_SD,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off3_0,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_0,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn2,
                    lsb: 6,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zmx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm2,
                    lsb: 17,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_INT_SD(SME_INT_SD::SDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zmx2(
            SDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zmx2::from(bits),
        ))
    }
}
impl InsnOpcode for SDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zmx2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zmx4 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sdot",
        aliases: &[],
        opcode: 0xc1a11400,
        mask: 0xffa39c78,
        class: InsnClass::SME_INT_SD,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off3_0,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_0,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn4,
                    lsb: 7,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zmx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm4,
                    lsb: 18,
                    width: 3,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_4.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_INT_SD(SME_INT_SD::SDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zmx4(
            SDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zmx4::from(bits),
        ))
    }
}
impl InsnOpcode for SDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zmx4 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SDOT_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_H_SME_Zm_S_H {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sdot",
        aliases: &[],
        opcode: 0xc1601408,
        mask: 0xfff09c18,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off3_0,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_0,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ZnxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm,
                    lsb: 16,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(
            SME_MISC::SDOT_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_H_SME_Zm_S_H(
                SDOT_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_H_SME_Zm_S_H::from(bits),
            ),
        )
    }
}
impl InsnOpcode for SDOT_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_H_SME_Zm_S_H {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SDOT_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_H_SME_Zm_S_H_c1701408 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sdot",
        aliases: &[],
        opcode: 0xc1701408,
        mask: 0xfff09c18,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off3_0,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_0,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ZnxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm,
                    lsb: 16,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_4.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(
            SME_MISC::SDOT_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_H_SME_Zm_S_H_c1701408(
                SDOT_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_H_SME_Zm_S_H_c1701408::from(bits),
            ),
        )
    }
}
impl InsnOpcode for SDOT_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_H_SME_Zm_S_H_c1701408 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SDOT_SME_ZA_array_off3_0_S_S_SME_Znx2_S_H_SME_Zmx2_S_H {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sdot",
        aliases: &[],
        opcode: 0xc1e01408,
        mask: 0xffe19c38,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off3_0,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_0,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn2,
                    lsb: 6,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zmx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm2,
                    lsb: 17,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(
            SME_MISC::SDOT_SME_ZA_array_off3_0_S_S_SME_Znx2_S_H_SME_Zmx2_S_H(
                SDOT_SME_ZA_array_off3_0_S_S_SME_Znx2_S_H_SME_Zmx2_S_H::from(bits),
            ),
        )
    }
}
impl InsnOpcode for SDOT_SME_ZA_array_off3_0_S_S_SME_Znx2_S_H_SME_Zmx2_S_H {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SDOT_SME_ZA_array_off3_0_S_S_SME_Znx4_S_H_SME_Zmx4_S_H {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sdot",
        aliases: &[],
        opcode: 0xc1e11408,
        mask: 0xffe39c78,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off3_0,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_0,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn4,
                    lsb: 7,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zmx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm4,
                    lsb: 18,
                    width: 3,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_4.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(
            SME_MISC::SDOT_SME_ZA_array_off3_0_S_S_SME_Znx4_S_H_SME_Zmx4_S_H(
                SDOT_SME_ZA_array_off3_0_S_S_SME_Znx4_S_H_SME_Zmx4_S_H::from(bits),
            ),
        )
    }
}
impl InsnOpcode for SDOT_SME_ZA_array_off3_0_S_S_SME_Znx4_S_H_SME_Zmx4_S_H {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SDOT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sdot",
        aliases: &[],
        opcode: 0x44800000,
        mask: 0xffa0fc00,
        class: InsnClass::SVE_SIZE_SD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_SD(SVE_SIZE_SD::SDOT_SVE_Zd_SVE_Zn_SVE_Zm_16(
            SDOT_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for SDOT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SDOT_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sdot",
        aliases: &[],
        opcode: 0x44a00000,
        mask: 0xffe0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm3_INDEX,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::SDOT_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX(
            SDOT_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX::from(bits),
        ))
    }
}
impl InsnOpcode for SDOT_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SDOT_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sdot",
        aliases: &[],
        opcode: 0x44e00000,
        mask: 0xffe0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm4_INDEX,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::SDOT_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX(
            SDOT_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX::from(bits),
        ))
    }
}
impl InsnOpcode for SDOT_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SDOT_SVE_Zd_S_S_SVE_Zn_S_H_SVE_Zm_16_S_H {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sdot",
        aliases: &[],
        opcode: 0x4400c800,
        mask: 0xffe0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::SDOT_SVE_Zd_S_S_SVE_Zn_S_H_SVE_Zm_16_S_H(
            SDOT_SVE_Zd_S_S_SVE_Zn_S_H_SVE_Zm_16_S_H::from(bits),
        ))
    }
}
impl InsnOpcode for SDOT_SVE_Zd_S_S_SVE_Zn_S_H_SVE_Zm_16_S_H {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SDOT_SVE_Zd_SVE_Zn_SVE_Zm3_19_INDEX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sdot",
        aliases: &[],
        opcode: 0x4480c800,
        mask: 0xffe0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm3_19_INDEX,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_19,
                        lsb: 19,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_imm3,
                        lsb: 16,
                        width: 3,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::SDOT_SVE_Zd_SVE_Zn_SVE_Zm3_19_INDEX(
            SDOT_SVE_Zd_SVE_Zn_SVE_Zm3_19_INDEX::from(bits),
        ))
    }
}
impl InsnOpcode for SDOT_SVE_Zd_SVE_Zn_SVE_Zm3_19_INDEX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SDOT_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sdot",
        aliases: &[],
        opcode: 0xe009400,
        mask: 0xbf20fc00,
        class: InsnClass::DOTPRODUCT,
        feature_set: InsnFeatureSet::DOTPROD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::DOTPRODUCT(DOTPRODUCT::SDOT_Vd_Vn_Vm(SDOT_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for SDOT_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SDOT_Vd_Vn_Em {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sdot",
        aliases: &[],
        opcode: 0xf00e000,
        mask: 0xbf00f400,
        class: InsnClass::DOTPRODUCT,
        feature_set: InsnFeatureSet::DOTPROD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Em,
                class: InsnOperandClass::SIMD_ELEMENT,
                qualifiers: &[InsnOperandQualifier::S_4B, InsnOperandQualifier::S_4B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::DOTPRODUCT(DOTPRODUCT::SDOT_Vd_Vn_Em(SDOT_Vd_Vn_Em::from(bits)))
    }
}
impl InsnOpcode for SDOT_Vd_Vn_Em {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SEL_SME_Zdnx2_SME_PNg3_SME_Znx2_SME_Zmx2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sel",
        aliases: &[],
        opcode: 0xc1208000,
        mask: 0xff21e021,
        class: InsnClass::SME_SIZE_22,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn2,
                    lsb: 1,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn2,
                    lsb: 6,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zmx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm2,
                    lsb: 17,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_SIZE_22(SME_SIZE_22::SEL_SME_Zdnx2_SME_PNg3_SME_Znx2_SME_Zmx2(
            SEL_SME_Zdnx2_SME_PNg3_SME_Znx2_SME_Zmx2::from(bits),
        ))
    }
}
impl InsnOpcode for SEL_SME_Zdnx2_SME_PNg3_SME_Znx2_SME_Zmx2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SEL_SME_Zdnx4_SME_PNg3_SME_Znx4_SME_Zmx4 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sel",
        aliases: &[],
        opcode: 0xc1218000,
        mask: 0xff23e063,
        class: InsnClass::SME_SIZE_22,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn4,
                    lsb: 2,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn4,
                    lsb: 7,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zmx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm4,
                    lsb: 18,
                    width: 3,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_SIZE_22(SME_SIZE_22::SEL_SME_Zdnx4_SME_PNg3_SME_Znx4_SME_Zmx4(
            SEL_SME_Zdnx4_SME_PNg3_SME_Znx4_SME_Zmx4::from(bits),
        ))
    }
}
impl InsnOpcode for SEL_SME_Zdnx4_SME_PNg3_SME_Znx4_SME_Zmx4 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SEL_SVE_Zd_SVE_Pg4_10_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sel",
        aliases: &[],
        opcode: 0x520c000,
        mask: 0xff20c000,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg4_10,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg4_10,
                    lsb: 10,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ALIAS.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::SEL_SVE_Zd_SVE_Pg4_10_SVE_Zn_SVE_Zm_16(
            SEL_SVE_Zd_SVE_Pg4_10_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for SEL_SVE_Zd_SVE_Pg4_10_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SEL_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sel",
        aliases: &[],
        opcode: 0x25004210,
        mask: 0xfff0c210,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Pd,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pd,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg4_10,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg4_10,
                    lsb: 10,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pn,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pn,
                    lsb: 5,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pm,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pm,
                    lsb: 16,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ALIAS.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::SEL_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm(
            SEL_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm::from(bits),
        ))
    }
}
impl InsnOpcode for SEL_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SETE_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sete",
        aliases: &[],
        opcode: 0x19c08400,
        mask: 0xffe0fc00,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::MOPS,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_WB_Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rm,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(AARCH64_MISC::SETE_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm(
            SETE_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm::from(bits),
        ))
    }
}
impl InsnOpcode for SETE_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SETEN_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "seten",
        aliases: &[],
        opcode: 0x19c0a400,
        mask: 0xffe0fc00,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::MOPS,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_WB_Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rm,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(AARCH64_MISC::SETEN_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm(
            SETEN_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm::from(bits),
        ))
    }
}
impl InsnOpcode for SETEN_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SETET_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "setet",
        aliases: &[],
        opcode: 0x19c09400,
        mask: 0xffe0fc00,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::MOPS,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_WB_Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rm,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(AARCH64_MISC::SETET_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm(
            SETET_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm::from(bits),
        ))
    }
}
impl InsnOpcode for SETET_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SETETN_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "setetn",
        aliases: &[],
        opcode: 0x19c0b400,
        mask: 0xffe0fc00,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::MOPS,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_WB_Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rm,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(AARCH64_MISC::SETETN_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm(
            SETETN_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm::from(bits),
        ))
    }
}
impl InsnOpcode for SETETN_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SETF16_Rn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "setf16",
        aliases: &[],
        opcode: 0x3a00480d,
        mask: 0xfffffc1f,
        class: InsnClass::IC_SYSTEM,
        feature_set: InsnFeatureSet::FLAGM,
        operands: &[InsnOperand {
            kind: InsnOperandKind::Rn,
            class: InsnOperandClass::INT_REG,
            qualifiers: &[],
            bit_fields: &[BitfieldSpec {
                bitfield: InsnBitField::Rn,
                lsb: 5,
                width: 5,
            }],
        }],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::IC_SYSTEM(IC_SYSTEM::SETF16_Rn(SETF16_Rn::from(bits)))
    }
}
impl InsnOpcode for SETF16_Rn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SETF8_Rn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "setf8",
        aliases: &[],
        opcode: 0x3a00080d,
        mask: 0xfffffc1f,
        class: InsnClass::IC_SYSTEM,
        feature_set: InsnFeatureSet::FLAGM,
        operands: &[InsnOperand {
            kind: InsnOperandKind::Rn,
            class: InsnOperandClass::INT_REG,
            qualifiers: &[],
            bit_fields: &[BitfieldSpec {
                bitfield: InsnBitField::Rn,
                lsb: 5,
                width: 5,
            }],
        }],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::IC_SYSTEM(IC_SYSTEM::SETF8_Rn(SETF8_Rn::from(bits)))
    }
}
impl InsnOpcode for SETF8_Rn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SETFFR {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "setffr",
        aliases: &[],
        opcode: 0x252c9000,
        mask: 0xffffffff,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::SETFFR(SETFFR::from(bits)))
    }
}
impl InsnOpcode for SETFFR {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SETGE_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "setge",
        aliases: &[],
        opcode: 0x1dc08400,
        mask: 0xffe0fc00,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::MOPS_MEMTAG,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_WB_Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rm,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(AARCH64_MISC::SETGE_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm(
            SETGE_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm::from(bits),
        ))
    }
}
impl InsnOpcode for SETGE_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SETGEN_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "setgen",
        aliases: &[],
        opcode: 0x1dc0a400,
        mask: 0xffe0fc00,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::MOPS_MEMTAG,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_WB_Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rm,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(AARCH64_MISC::SETGEN_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm(
            SETGEN_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm::from(bits),
        ))
    }
}
impl InsnOpcode for SETGEN_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SETGET_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "setget",
        aliases: &[],
        opcode: 0x1dc09400,
        mask: 0xffe0fc00,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::MOPS_MEMTAG,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_WB_Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rm,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(AARCH64_MISC::SETGET_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm(
            SETGET_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm::from(bits),
        ))
    }
}
impl InsnOpcode for SETGET_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SETGETN_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "setgetn",
        aliases: &[],
        opcode: 0x1dc0b400,
        mask: 0xffe0fc00,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::MOPS_MEMTAG,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_WB_Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rm,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(AARCH64_MISC::SETGETN_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm(
            SETGETN_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm::from(bits),
        ))
    }
}
impl InsnOpcode for SETGETN_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SETGM_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "setgm",
        aliases: &[],
        opcode: 0x1dc04400,
        mask: 0xffe0fc00,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::MOPS_MEMTAG,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_WB_Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rm,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(AARCH64_MISC::SETGM_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm(
            SETGM_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm::from(bits),
        ))
    }
}
impl InsnOpcode for SETGM_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SETGMN_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "setgmn",
        aliases: &[],
        opcode: 0x1dc06400,
        mask: 0xffe0fc00,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::MOPS_MEMTAG,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_WB_Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rm,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(AARCH64_MISC::SETGMN_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm(
            SETGMN_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm::from(bits),
        ))
    }
}
impl InsnOpcode for SETGMN_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SETGMT_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "setgmt",
        aliases: &[],
        opcode: 0x1dc05400,
        mask: 0xffe0fc00,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::MOPS_MEMTAG,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_WB_Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rm,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(AARCH64_MISC::SETGMT_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm(
            SETGMT_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm::from(bits),
        ))
    }
}
impl InsnOpcode for SETGMT_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SETGMTN_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "setgmtn",
        aliases: &[],
        opcode: 0x1dc07400,
        mask: 0xffe0fc00,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::MOPS_MEMTAG,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_WB_Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rm,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(AARCH64_MISC::SETGMTN_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm(
            SETGMTN_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm::from(bits),
        ))
    }
}
impl InsnOpcode for SETGMTN_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SETGP_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "setgp",
        aliases: &[],
        opcode: 0x1dc00400,
        mask: 0xffe0fc00,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::MOPS_MEMTAG,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_WB_Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rm,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::RESTRICTED_NEXT_INSN_SET.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(AARCH64_MISC::SETGP_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm(
            SETGP_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm::from(bits),
        ))
    }
}
impl InsnOpcode for SETGP_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SETGPN_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "setgpn",
        aliases: &[],
        opcode: 0x1dc02400,
        mask: 0xffe0fc00,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::MOPS_MEMTAG,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_WB_Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rm,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::RESTRICTED_NEXT_INSN_SET.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(AARCH64_MISC::SETGPN_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm(
            SETGPN_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm::from(bits),
        ))
    }
}
impl InsnOpcode for SETGPN_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SETGPT_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "setgpt",
        aliases: &[],
        opcode: 0x1dc01400,
        mask: 0xffe0fc00,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::MOPS_MEMTAG,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_WB_Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rm,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::RESTRICTED_NEXT_INSN_SET.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(AARCH64_MISC::SETGPT_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm(
            SETGPT_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm::from(bits),
        ))
    }
}
impl InsnOpcode for SETGPT_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SETGPTN_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "setgptn",
        aliases: &[],
        opcode: 0x1dc03400,
        mask: 0xffe0fc00,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::MOPS_MEMTAG,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_WB_Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rm,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::RESTRICTED_NEXT_INSN_SET.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(AARCH64_MISC::SETGPTN_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm(
            SETGPTN_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm::from(bits),
        ))
    }
}
impl InsnOpcode for SETGPTN_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SETM_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "setm",
        aliases: &[],
        opcode: 0x19c04400,
        mask: 0xffe0fc00,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::MOPS,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_WB_Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rm,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(AARCH64_MISC::SETM_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm(
            SETM_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm::from(bits),
        ))
    }
}
impl InsnOpcode for SETM_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SETMN_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "setmn",
        aliases: &[],
        opcode: 0x19c06400,
        mask: 0xffe0fc00,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::MOPS,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_WB_Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rm,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(AARCH64_MISC::SETMN_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm(
            SETMN_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm::from(bits),
        ))
    }
}
impl InsnOpcode for SETMN_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SETMT_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "setmt",
        aliases: &[],
        opcode: 0x19c05400,
        mask: 0xffe0fc00,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::MOPS,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_WB_Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rm,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(AARCH64_MISC::SETMT_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm(
            SETMT_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm::from(bits),
        ))
    }
}
impl InsnOpcode for SETMT_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SETMTN_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "setmtn",
        aliases: &[],
        opcode: 0x19c07400,
        mask: 0xffe0fc00,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::MOPS,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_WB_Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rm,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(AARCH64_MISC::SETMTN_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm(
            SETMTN_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm::from(bits),
        ))
    }
}
impl InsnOpcode for SETMTN_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SETP_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "setp",
        aliases: &[],
        opcode: 0x19c00400,
        mask: 0xffe0fc00,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::MOPS,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_WB_Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rm,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::RESTRICTED_NEXT_INSN_SET.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(AARCH64_MISC::SETP_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm(
            SETP_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm::from(bits),
        ))
    }
}
impl InsnOpcode for SETP_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SETPN_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "setpn",
        aliases: &[],
        opcode: 0x19c02400,
        mask: 0xffe0fc00,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::MOPS,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_WB_Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rm,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::RESTRICTED_NEXT_INSN_SET.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(AARCH64_MISC::SETPN_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm(
            SETPN_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm::from(bits),
        ))
    }
}
impl InsnOpcode for SETPN_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SETPT_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "setpt",
        aliases: &[],
        opcode: 0x19c01400,
        mask: 0xffe0fc00,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::MOPS,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_WB_Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rm,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::RESTRICTED_NEXT_INSN_SET.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(AARCH64_MISC::SETPT_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm(
            SETPT_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm::from(bits),
        ))
    }
}
impl InsnOpcode for SETPT_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SETPTN_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "setptn",
        aliases: &[],
        opcode: 0x19c03400,
        mask: 0xffe0fc00,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::MOPS,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::MOPS_ADDR_Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::MOPS_WB_Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rm,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::RESTRICTED_NEXT_INSN_SET.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(AARCH64_MISC::SETPTN_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm(
            SETPTN_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm::from(bits),
        ))
    }
}
impl InsnOpcode for SETPTN_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SHA1C_Fd_Fn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sha1c",
        aliases: &[],
        opcode: 0x5e000000,
        mask: 0xffe0fc00,
        class: InsnClass::CRYPTOSHA3,
        feature_set: InsnFeatureSet::SHA2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Fd,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_Q],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fn,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::CRYPTOSHA3(CRYPTOSHA3::SHA1C_Fd_Fn_Vm(SHA1C_Fd_Fn_Vm::from(bits)))
    }
}
impl InsnOpcode for SHA1C_Fd_Fn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SHA1H_Fd_Fn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sha1h",
        aliases: &[],
        opcode: 0x5e280800,
        mask: 0xfffffc00,
        class: InsnClass::CRYPTOSHA2,
        feature_set: InsnFeatureSet::SHA2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Fd,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fn,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::CRYPTOSHA2(CRYPTOSHA2::SHA1H_Fd_Fn(SHA1H_Fd_Fn::from(bits)))
    }
}
impl InsnOpcode for SHA1H_Fd_Fn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SHA1M_Fd_Fn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sha1m",
        aliases: &[],
        opcode: 0x5e002000,
        mask: 0xffe0fc00,
        class: InsnClass::CRYPTOSHA3,
        feature_set: InsnFeatureSet::SHA2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Fd,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_Q],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fn,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::CRYPTOSHA3(CRYPTOSHA3::SHA1M_Fd_Fn_Vm(SHA1M_Fd_Fn_Vm::from(bits)))
    }
}
impl InsnOpcode for SHA1M_Fd_Fn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SHA1P_Fd_Fn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sha1p",
        aliases: &[],
        opcode: 0x5e001000,
        mask: 0xffe0fc00,
        class: InsnClass::CRYPTOSHA3,
        feature_set: InsnFeatureSet::SHA2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Fd,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_Q],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fn,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::CRYPTOSHA3(CRYPTOSHA3::SHA1P_Fd_Fn_Vm(SHA1P_Fd_Fn_Vm::from(bits)))
    }
}
impl InsnOpcode for SHA1P_Fd_Fn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SHA1SU0_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sha1su0",
        aliases: &[],
        opcode: 0x5e003000,
        mask: 0xffe0fc00,
        class: InsnClass::CRYPTOSHA3,
        feature_set: InsnFeatureSet::SHA2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::CRYPTOSHA3(CRYPTOSHA3::SHA1SU0_Vd_Vn_Vm(SHA1SU0_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for SHA1SU0_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SHA1SU1_Vd_Vn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sha1su1",
        aliases: &[],
        opcode: 0x5e281800,
        mask: 0xfffffc00,
        class: InsnClass::CRYPTOSHA2,
        feature_set: InsnFeatureSet::SHA2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::CRYPTOSHA2(CRYPTOSHA2::SHA1SU1_Vd_Vn(SHA1SU1_Vd_Vn::from(bits)))
    }
}
impl InsnOpcode for SHA1SU1_Vd_Vn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SHA256H_Fd_Fn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sha256h",
        aliases: &[],
        opcode: 0x5e004000,
        mask: 0xffe0fc00,
        class: InsnClass::CRYPTOSHA3,
        feature_set: InsnFeatureSet::SHA2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Fd,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_Q],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fn,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_Q],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::CRYPTOSHA3(CRYPTOSHA3::SHA256H_Fd_Fn_Vm(SHA256H_Fd_Fn_Vm::from(bits)))
    }
}
impl InsnOpcode for SHA256H_Fd_Fn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SHA256H2_Fd_Fn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sha256h2",
        aliases: &[],
        opcode: 0x5e005000,
        mask: 0xffe0fc00,
        class: InsnClass::CRYPTOSHA3,
        feature_set: InsnFeatureSet::SHA2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Fd,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_Q],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fn,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_Q],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::CRYPTOSHA3(CRYPTOSHA3::SHA256H2_Fd_Fn_Vm(SHA256H2_Fd_Fn_Vm::from(bits)))
    }
}
impl InsnOpcode for SHA256H2_Fd_Fn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SHA256SU0_Vd_Vn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sha256su0",
        aliases: &[],
        opcode: 0x5e282800,
        mask: 0xfffffc00,
        class: InsnClass::CRYPTOSHA2,
        feature_set: InsnFeatureSet::SHA2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::CRYPTOSHA2(CRYPTOSHA2::SHA256SU0_Vd_Vn(SHA256SU0_Vd_Vn::from(bits)))
    }
}
impl InsnOpcode for SHA256SU0_Vd_Vn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SHA256SU1_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sha256su1",
        aliases: &[],
        opcode: 0x5e006000,
        mask: 0xffe0fc00,
        class: InsnClass::CRYPTOSHA3,
        feature_set: InsnFeatureSet::SHA2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::CRYPTOSHA3(CRYPTOSHA3::SHA256SU1_Vd_Vn_Vm(SHA256SU1_Vd_Vn_Vm::from(
            bits,
        )))
    }
}
impl InsnOpcode for SHA256SU1_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SHA512H_Fd_Fn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sha512h",
        aliases: &[],
        opcode: 0xce608000,
        mask: 0xffe0fc00,
        class: InsnClass::CRYPTOSHA2,
        feature_set: InsnFeatureSet::SHA2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Fd,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_Q],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fn,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_Q],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::CRYPTOSHA2(CRYPTOSHA2::SHA512H_Fd_Fn_Vm(SHA512H_Fd_Fn_Vm::from(bits)))
    }
}
impl InsnOpcode for SHA512H_Fd_Fn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SHA512H2_Fd_Fn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sha512h2",
        aliases: &[],
        opcode: 0xce608400,
        mask: 0xffe0fc00,
        class: InsnClass::CRYPTOSHA2,
        feature_set: InsnFeatureSet::SHA2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Fd,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_Q],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Fn,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_Q],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::CRYPTOSHA2(CRYPTOSHA2::SHA512H2_Fd_Fn_Vm(SHA512H2_Fd_Fn_Vm::from(bits)))
    }
}
impl InsnOpcode for SHA512H2_Fd_Fn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SHA512SU0_Vd_Vn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sha512su0",
        aliases: &[],
        opcode: 0xcec08000,
        mask: 0xfffffc00,
        class: InsnClass::CRYPTOSHA2,
        feature_set: InsnFeatureSet::SHA2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::CRYPTOSHA2(CRYPTOSHA2::SHA512SU0_Vd_Vn(SHA512SU0_Vd_Vn::from(bits)))
    }
}
impl InsnOpcode for SHA512SU0_Vd_Vn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SHA512SU1_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sha512su1",
        aliases: &[],
        opcode: 0xce608800,
        mask: 0xffe0fc00,
        class: InsnClass::CRYPTOSHA2,
        feature_set: InsnFeatureSet::SHA2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::CRYPTOSHA2(CRYPTOSHA2::SHA512SU1_Vd_Vn_Vm(SHA512SU1_Vd_Vn_Vm::from(
            bits,
        )))
    }
}
impl InsnOpcode for SHA512SU1_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SHADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "shadd",
        aliases: &[],
        opcode: 0x44108000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::SHADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(
            SHADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for SHADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SHADD_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "shadd",
        aliases: &[],
        opcode: 0xe200400,
        mask: 0xbf20fc00,
        class: InsnClass::ASIMDSAME,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSAME(ASIMDSAME::SHADD_Vd_Vn_Vm(SHADD_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for SHADD_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SHL_Vd_Vn_IMM_VLSL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "shl",
        aliases: &[],
        opcode: 0xf005400,
        mask: 0xbf80fc00,
        class: InsnClass::ASIMDSHF,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::IMM_VLSL,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSHF(ASIMDSHF::SHL_Vd_Vn_IMM_VLSL(SHL_Vd_Vn_IMM_VLSL::from(bits)))
    }
}
impl InsnOpcode for SHL_Vd_Vn_IMM_VLSL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SHL_Sd_Sn_IMM_VLSL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "shl",
        aliases: &[],
        opcode: 0x5f005400,
        mask: 0xff80fc00,
        class: InsnClass::ASISDSHF,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::IMM_VLSL,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDSHF(ASISDSHF::SHL_Sd_Sn_IMM_VLSL(SHL_Sd_Sn_IMM_VLSL::from(bits)))
    }
}
impl InsnOpcode for SHL_Sd_Sn_IMM_VLSL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SHLL_Vd_Vn_SHLL_IMM {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "shll",
        aliases: &[],
        opcode: 0x2e213800,
        mask: 0xff3ffc00,
        class: InsnClass::ASIMDMISC,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8H, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_4H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SHLL_IMM,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDMISC(ASIMDMISC::SHLL_Vd_Vn_SHLL_IMM(SHLL_Vd_Vn_SHLL_IMM::from(
            bits,
        )))
    }
}
impl InsnOpcode for SHLL_Vd_Vn_SHLL_IMM {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SHLL2_Vd_Vn_SHLL_IMM {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "shll2",
        aliases: &[],
        opcode: 0x6e213800,
        mask: 0xff3ffc00,
        class: InsnClass::ASIMDMISC,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8H, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_16B, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SHLL_IMM,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDMISC(ASIMDMISC::SHLL2_Vd_Vn_SHLL_IMM(SHLL2_Vd_Vn_SHLL_IMM::from(
            bits,
        )))
    }
}
impl InsnOpcode for SHLL2_Vd_Vn_SHLL_IMM {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SHRN_Vd_Vn_IMM_VLSR {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "shrn",
        aliases: &[],
        opcode: 0xf008400,
        mask: 0xff80fc00,
        class: InsnClass::ASIMDSHF,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_4H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8H, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::IMM_VLSR,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_4H],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSHF(ASIMDSHF::SHRN_Vd_Vn_IMM_VLSR(SHRN_Vd_Vn_IMM_VLSR::from(
            bits,
        )))
    }
}
impl InsnOpcode for SHRN_Vd_Vn_IMM_VLSR {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SHRN2_Vd_Vn_IMM_VLSR {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "shrn2",
        aliases: &[],
        opcode: 0x4f008400,
        mask: 0xff80fc00,
        class: InsnClass::ASIMDSHF,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_16B, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8H, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::IMM_VLSR,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[InsnOperandQualifier::V_16B, InsnOperandQualifier::V_8H],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSHF(ASIMDSHF::SHRN2_Vd_Vn_IMM_VLSR(SHRN2_Vd_Vn_IMM_VLSR::from(
            bits,
        )))
    }
}
impl InsnOpcode for SHRN2_Vd_Vn_IMM_VLSR {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SHRNB_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "shrnb",
        aliases: &[],
        opcode: 0x45201000,
        mask: 0xffa0fc00,
        class: InsnClass::SVE_SHIFT_TSZ_HSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_SHRIMM_UNPRED_22,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_sz,
                        lsb: 22,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_tszl_19,
                        lsb: 19,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_imm3,
                        lsb: 16,
                        width: 3,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SHIFT_TSZ_HSD(SVE_SHIFT_TSZ_HSD::SHRNB_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22(
            SHRNB_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22::from(bits),
        ))
    }
}
impl InsnOpcode for SHRNB_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SHRNT_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "shrnt",
        aliases: &[],
        opcode: 0x45201400,
        mask: 0xffa0fc00,
        class: InsnClass::SVE_SHIFT_TSZ_HSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_SHRIMM_UNPRED_22,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_sz,
                        lsb: 22,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_tszl_19,
                        lsb: 19,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_imm3,
                        lsb: 16,
                        width: 3,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SHIFT_TSZ_HSD(SVE_SHIFT_TSZ_HSD::SHRNT_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22(
            SHRNT_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22::from(bits),
        ))
    }
}
impl InsnOpcode for SHRNT_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SHSUB_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "shsub",
        aliases: &[],
        opcode: 0x44128000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::SHSUB_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(
            SHSUB_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for SHSUB_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SHSUB_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "shsub",
        aliases: &[],
        opcode: 0xe202400,
        mask: 0xbf20fc00,
        class: InsnClass::ASIMDSAME,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSAME(ASIMDSAME::SHSUB_Vd_Vn_Vm(SHSUB_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for SHSUB_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SHSUBR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "shsubr",
        aliases: &[],
        opcode: 0x44168000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::SHSUBR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(
            SHSUBR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for SHSUBR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SLI_SVE_Zd_SVE_Zn_SVE_SHLIMM_UNPRED {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sli",
        aliases: &[],
        opcode: 0x4500f400,
        mask: 0xff20fc00,
        class: InsnClass::SVE_SHIFT_TSZ_BHSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_SHLIMM_UNPRED,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_tszh,
                        lsb: 22,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm5,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SHIFT_TSZ_BHSD(SVE_SHIFT_TSZ_BHSD::SLI_SVE_Zd_SVE_Zn_SVE_SHLIMM_UNPRED(
            SLI_SVE_Zd_SVE_Zn_SVE_SHLIMM_UNPRED::from(bits),
        ))
    }
}
impl InsnOpcode for SLI_SVE_Zd_SVE_Zn_SVE_SHLIMM_UNPRED {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SLI_Vd_Vn_IMM_VLSL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sli",
        aliases: &[],
        opcode: 0x2f005400,
        mask: 0xbf80fc00,
        class: InsnClass::ASIMDSHF,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::IMM_VLSL,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSHF(ASIMDSHF::SLI_Vd_Vn_IMM_VLSL(SLI_Vd_Vn_IMM_VLSL::from(bits)))
    }
}
impl InsnOpcode for SLI_Vd_Vn_IMM_VLSL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SLI_Sd_Sn_IMM_VLSL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sli",
        aliases: &[],
        opcode: 0x7f005400,
        mask: 0xff80fc00,
        class: InsnClass::ASISDSHF,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::IMM_VLSL,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDSHF(ASISDSHF::SLI_Sd_Sn_IMM_VLSL(SLI_Sd_Sn_IMM_VLSL::from(bits)))
    }
}
impl InsnOpcode for SLI_Sd_Sn_IMM_VLSL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SM3PARTW1_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sm3partw1",
        aliases: &[],
        opcode: 0xce60c000,
        mask: 0xffe0fc00,
        class: InsnClass::CRYPTOSM3,
        feature_set: InsnFeatureSet::SM4,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::CRYPTOSM3(CRYPTOSM3::SM3PARTW1_Vd_Vn_Vm(SM3PARTW1_Vd_Vn_Vm::from(
            bits,
        )))
    }
}
impl InsnOpcode for SM3PARTW1_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SM3PARTW2_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sm3partw2",
        aliases: &[],
        opcode: 0xce60c400,
        mask: 0xffe0fc00,
        class: InsnClass::CRYPTOSM3,
        feature_set: InsnFeatureSet::SM4,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::CRYPTOSM3(CRYPTOSM3::SM3PARTW2_Vd_Vn_Vm(SM3PARTW2_Vd_Vn_Vm::from(
            bits,
        )))
    }
}
impl InsnOpcode for SM3PARTW2_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SM3SS1_Vd_Vn_Vm_Va {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sm3ss1",
        aliases: &[],
        opcode: 0xce400000,
        mask: 0xffe08000,
        class: InsnClass::CRYPTOSM3,
        feature_set: InsnFeatureSet::SM4,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Va,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Ra,
                    lsb: 10,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::CRYPTOSM3(CRYPTOSM3::SM3SS1_Vd_Vn_Vm_Va(SM3SS1_Vd_Vn_Vm_Va::from(
            bits,
        )))
    }
}
impl InsnOpcode for SM3SS1_Vd_Vn_Vm_Va {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SM3TT1A_Vd_Vn_Em {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sm3tt1a",
        aliases: &[],
        opcode: 0xce408000,
        mask: 0xffe0cc00,
        class: InsnClass::CRYPTOSM3,
        feature_set: InsnFeatureSet::SM4,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Em,
                class: InsnOperandClass::SIMD_ELEMENT,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::CRYPTOSM3(CRYPTOSM3::SM3TT1A_Vd_Vn_Em(SM3TT1A_Vd_Vn_Em::from(bits)))
    }
}
impl InsnOpcode for SM3TT1A_Vd_Vn_Em {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SM3TT1B_Vd_Vn_Em {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sm3tt1b",
        aliases: &[],
        opcode: 0xce408400,
        mask: 0xffe0cc00,
        class: InsnClass::CRYPTOSM3,
        feature_set: InsnFeatureSet::SM4,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Em,
                class: InsnOperandClass::SIMD_ELEMENT,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::CRYPTOSM3(CRYPTOSM3::SM3TT1B_Vd_Vn_Em(SM3TT1B_Vd_Vn_Em::from(bits)))
    }
}
impl InsnOpcode for SM3TT1B_Vd_Vn_Em {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SM3TT2A_Vd_Vn_Em {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sm3tt2a",
        aliases: &[],
        opcode: 0xce408800,
        mask: 0xffe0cc00,
        class: InsnClass::CRYPTOSM3,
        feature_set: InsnFeatureSet::SM4,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Em,
                class: InsnOperandClass::SIMD_ELEMENT,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::CRYPTOSM3(CRYPTOSM3::SM3TT2A_Vd_Vn_Em(SM3TT2A_Vd_Vn_Em::from(bits)))
    }
}
impl InsnOpcode for SM3TT2A_Vd_Vn_Em {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SM3TT2B_Vd_Vn_Em {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sm3tt2b",
        aliases: &[],
        opcode: 0xce408c00,
        mask: 0xffe0cc00,
        class: InsnClass::CRYPTOSM3,
        feature_set: InsnFeatureSet::SM4,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Em,
                class: InsnOperandClass::SIMD_ELEMENT,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::CRYPTOSM3(CRYPTOSM3::SM3TT2B_Vd_Vn_Em(SM3TT2B_Vd_Vn_Em::from(bits)))
    }
}
impl InsnOpcode for SM3TT2B_Vd_Vn_Em {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SM4E_SVE_Zd_SVE_Zd_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sm4e",
        aliases: &[],
        opcode: 0x4523e000,
        mask: 0xfffffc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE2SM4,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::SM4E_SVE_Zd_SVE_Zd_SVE_Zn(
            SM4E_SVE_Zd_SVE_Zd_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for SM4E_SVE_Zd_SVE_Zd_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SM4E_Vd_Vn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sm4e",
        aliases: &[],
        opcode: 0xcec08400,
        mask: 0xfffffc00,
        class: InsnClass::CRYPTOSM4,
        feature_set: InsnFeatureSet::SM4,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::CRYPTOSM4(CRYPTOSM4::SM4E_Vd_Vn(SM4E_Vd_Vn::from(bits)))
    }
}
impl InsnOpcode for SM4E_Vd_Vn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SM4EKEY_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sm4ekey",
        aliases: &[],
        opcode: 0x4520f000,
        mask: 0xffe0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE2SM4,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::SM4EKEY_SVE_Zd_SVE_Zn_SVE_Zm_16(
            SM4EKEY_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for SM4EKEY_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SM4EKEY_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sm4ekey",
        aliases: &[],
        opcode: 0xce60c800,
        mask: 0xffe0fc00,
        class: InsnClass::CRYPTOSM4,
        feature_set: InsnFeatureSet::SM4,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::CRYPTOSM4(CRYPTOSM4::SM4EKEY_Vd_Vn_Vm(SM4EKEY_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for SM4EKEY_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SMADDL_Rd_Rn_Rm_Ra {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "smaddl",
        aliases: &[],
        opcode: 0x9b200000,
        mask: 0xffe08000,
        class: InsnClass::DP_3SRC,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rm,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Ra,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Ra,
                    lsb: 10,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ALIAS.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::DP_3SRC(DP_3SRC::SMADDL_Rd_Rn_Rm_Ra(SMADDL_Rd_Rn_Rm_Ra::from(bits)))
    }
}
impl InsnOpcode for SMADDL_Rd_Rn_Rm_Ra {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SMAX_SME_Zdnx2_SME_Zdnx2_SME_Zm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "smax",
        aliases: &[],
        opcode: 0xc120a000,
        mask: 0xff30ffe1,
        class: InsnClass::SME_SIZE_22,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn2,
                    lsb: 1,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn2,
                    lsb: 1,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm,
                    lsb: 16,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_SIZE_22(SME_SIZE_22::SMAX_SME_Zdnx2_SME_Zdnx2_SME_Zm(
            SMAX_SME_Zdnx2_SME_Zdnx2_SME_Zm::from(bits),
        ))
    }
}
impl InsnOpcode for SMAX_SME_Zdnx2_SME_Zdnx2_SME_Zm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SMAX_SME_Zdnx2_SME_Zdnx2_SME_Zmx2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "smax",
        aliases: &[],
        opcode: 0xc120b000,
        mask: 0xff21ffe1,
        class: InsnClass::SME_SIZE_22,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn2,
                    lsb: 1,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn2,
                    lsb: 1,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zmx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm2,
                    lsb: 17,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_SIZE_22(SME_SIZE_22::SMAX_SME_Zdnx2_SME_Zdnx2_SME_Zmx2(
            SMAX_SME_Zdnx2_SME_Zdnx2_SME_Zmx2::from(bits),
        ))
    }
}
impl InsnOpcode for SMAX_SME_Zdnx2_SME_Zdnx2_SME_Zmx2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SMAX_SME_Zdnx4_SME_Zdnx4_SME_Zm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "smax",
        aliases: &[],
        opcode: 0xc120a800,
        mask: 0xff30ffe3,
        class: InsnClass::SME_SIZE_22,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn4,
                    lsb: 2,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn4,
                    lsb: 2,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm,
                    lsb: 16,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_SIZE_22(SME_SIZE_22::SMAX_SME_Zdnx4_SME_Zdnx4_SME_Zm(
            SMAX_SME_Zdnx4_SME_Zdnx4_SME_Zm::from(bits),
        ))
    }
}
impl InsnOpcode for SMAX_SME_Zdnx4_SME_Zdnx4_SME_Zm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SMAX_SME_Zdnx4_SME_Zdnx4_SME_Zmx4 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "smax",
        aliases: &[],
        opcode: 0xc120b800,
        mask: 0xff23ffe3,
        class: InsnClass::SME_SIZE_22,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn4,
                    lsb: 2,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn4,
                    lsb: 2,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zmx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm4,
                    lsb: 18,
                    width: 3,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_SIZE_22(SME_SIZE_22::SMAX_SME_Zdnx4_SME_Zdnx4_SME_Zmx4(
            SMAX_SME_Zdnx4_SME_Zdnx4_SME_Zmx4::from(bits),
        ))
    }
}
impl InsnOpcode for SMAX_SME_Zdnx4_SME_Zdnx4_SME_Zmx4 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SMAX_Rd_Rn_CSSC_SIMM8 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "smax",
        aliases: &[],
        opcode: 0x11c00000,
        mask: 0x7ffc0000,
        class: InsnClass::CSSC,
        feature_set: InsnFeatureSet::CSSC,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::CSSC_SIMM8,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::CSSC_imm8,
                    lsb: 10,
                    width: 8,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SF_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::CSSC(CSSC::SMAX_Rd_Rn_CSSC_SIMM8(SMAX_Rd_Rn_CSSC_SIMM8::from(
            bits,
        )))
    }
}
impl InsnOpcode for SMAX_Rd_Rn_CSSC_SIMM8 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SMAX_Rd_Rn_Rm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "smax",
        aliases: &[],
        opcode: 0x1ac06000,
        mask: 0x7fe0fc00,
        class: InsnClass::CSSC,
        feature_set: InsnFeatureSet::CSSC,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rm,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SF_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::CSSC(CSSC::SMAX_Rd_Rn_Rm(SMAX_Rd_Rn_Rm::from(bits)))
    }
}
impl InsnOpcode for SMAX_Rd_Rn_Rm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SMAX_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "smax",
        aliases: &[],
        opcode: 0x4080000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_5,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_5,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::SMAX_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(
            SMAX_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5::from(bits),
        ))
    }
}
impl InsnOpcode for SMAX_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SMAX_SVE_Zd_SVE_Zd_SVE_SIMM8 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "smax",
        aliases: &[],
        opcode: 0x2528c000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_SIMM8,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_imm8,
                    lsb: 5,
                    width: 8,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::SMAX_SVE_Zd_SVE_Zd_SVE_SIMM8(
            SMAX_SVE_Zd_SVE_Zd_SVE_SIMM8::from(bits),
        ))
    }
}
impl InsnOpcode for SMAX_SVE_Zd_SVE_Zd_SVE_SIMM8 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SMAX_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "smax",
        aliases: &[],
        opcode: 0xe206400,
        mask: 0xbf20fc00,
        class: InsnClass::ASIMDSAME,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSAME(ASIMDSAME::SMAX_Vd_Vn_Vm(SMAX_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for SMAX_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SMAXP_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "smaxp",
        aliases: &[],
        opcode: 0x4414a000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::SMAXP_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(
            SMAXP_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for SMAXP_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SMAXP_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "smaxp",
        aliases: &[],
        opcode: 0xe20a400,
        mask: 0xbf20fc00,
        class: InsnClass::ASIMDSAME,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSAME(ASIMDSAME::SMAXP_Vd_Vn_Vm(SMAXP_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for SMAXP_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SMAXQV_Vd_SVE_Pg3_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "smaxqv",
        aliases: &[],
        opcode: 0x40c2000,
        mask: 0xff3fe000,
        class: InsnClass::SVE2_URQVS,
        feature_set: InsnFeatureSet::SVE2P1,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_16B, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE2_URQVS(SVE2_URQVS::SMAXQV_Vd_SVE_Pg3_SVE_Zn(
            SMAXQV_Vd_SVE_Pg3_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for SMAXQV_Vd_SVE_Pg3_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SMAXV_SVE_Vd_SVE_Pg3_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "smaxv",
        aliases: &[],
        opcode: 0x4082000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Vd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::SMAXV_SVE_Vd_SVE_Pg3_SVE_Zn(
            SMAXV_SVE_Vd_SVE_Pg3_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for SMAXV_SVE_Vd_SVE_Pg3_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SMAXV_Fd_Vn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "smaxv",
        aliases: &[],
        opcode: 0xe30a800,
        mask: 0xbf3ffc00,
        class: InsnClass::ASIMDALL,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Fd,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDALL(ASIMDALL::SMAXV_Fd_Vn(SMAXV_Fd_Vn::from(bits)))
    }
}
impl InsnOpcode for SMAXV_Fd_Vn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SMC_EXCEPTION {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "smc",
        aliases: &[],
        opcode: 0xd4000003,
        mask: 0xffe0001f,
        class: InsnClass::EXCEPTION,
        feature_set: InsnFeatureSet::V8,
        operands: &[InsnOperand {
            kind: InsnOperandKind::EXCEPTION,
            class: InsnOperandClass::IMMEDIATE,
            qualifiers: &[],
            bit_fields: &[BitfieldSpec {
                bitfield: InsnBitField::imm16_5,
                lsb: 5,
                width: 16,
            }],
        }],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::EXCEPTION(EXCEPTION::SMC_EXCEPTION(SMC_EXCEPTION::from(bits)))
    }
}
impl InsnOpcode for SMC_EXCEPTION {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SMIN_SME_Zdnx2_SME_Zdnx2_SME_Zm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "smin",
        aliases: &[],
        opcode: 0xc120a020,
        mask: 0xff30ffe1,
        class: InsnClass::SME_SIZE_22,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn2,
                    lsb: 1,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn2,
                    lsb: 1,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm,
                    lsb: 16,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_SIZE_22(SME_SIZE_22::SMIN_SME_Zdnx2_SME_Zdnx2_SME_Zm(
            SMIN_SME_Zdnx2_SME_Zdnx2_SME_Zm::from(bits),
        ))
    }
}
impl InsnOpcode for SMIN_SME_Zdnx2_SME_Zdnx2_SME_Zm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SMIN_SME_Zdnx2_SME_Zdnx2_SME_Zmx2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "smin",
        aliases: &[],
        opcode: 0xc120b020,
        mask: 0xff21ffe1,
        class: InsnClass::SME_SIZE_22,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn2,
                    lsb: 1,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn2,
                    lsb: 1,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zmx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm2,
                    lsb: 17,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_SIZE_22(SME_SIZE_22::SMIN_SME_Zdnx2_SME_Zdnx2_SME_Zmx2(
            SMIN_SME_Zdnx2_SME_Zdnx2_SME_Zmx2::from(bits),
        ))
    }
}
impl InsnOpcode for SMIN_SME_Zdnx2_SME_Zdnx2_SME_Zmx2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SMIN_SME_Zdnx4_SME_Zdnx4_SME_Zm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "smin",
        aliases: &[],
        opcode: 0xc120a820,
        mask: 0xff30ffe3,
        class: InsnClass::SME_SIZE_22,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn4,
                    lsb: 2,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn4,
                    lsb: 2,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm,
                    lsb: 16,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_SIZE_22(SME_SIZE_22::SMIN_SME_Zdnx4_SME_Zdnx4_SME_Zm(
            SMIN_SME_Zdnx4_SME_Zdnx4_SME_Zm::from(bits),
        ))
    }
}
impl InsnOpcode for SMIN_SME_Zdnx4_SME_Zdnx4_SME_Zm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SMIN_SME_Zdnx4_SME_Zdnx4_SME_Zmx4 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "smin",
        aliases: &[],
        opcode: 0xc120b820,
        mask: 0xff23ffe3,
        class: InsnClass::SME_SIZE_22,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn4,
                    lsb: 2,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn4,
                    lsb: 2,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zmx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm4,
                    lsb: 18,
                    width: 3,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_SIZE_22(SME_SIZE_22::SMIN_SME_Zdnx4_SME_Zdnx4_SME_Zmx4(
            SMIN_SME_Zdnx4_SME_Zdnx4_SME_Zmx4::from(bits),
        ))
    }
}
impl InsnOpcode for SMIN_SME_Zdnx4_SME_Zdnx4_SME_Zmx4 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SMIN_Rd_Rn_CSSC_SIMM8 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "smin",
        aliases: &[],
        opcode: 0x11c80000,
        mask: 0x7ffc0000,
        class: InsnClass::CSSC,
        feature_set: InsnFeatureSet::CSSC,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::CSSC_SIMM8,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::CSSC_imm8,
                    lsb: 10,
                    width: 8,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SF_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::CSSC(CSSC::SMIN_Rd_Rn_CSSC_SIMM8(SMIN_Rd_Rn_CSSC_SIMM8::from(
            bits,
        )))
    }
}
impl InsnOpcode for SMIN_Rd_Rn_CSSC_SIMM8 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SMIN_Rd_Rn_Rm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "smin",
        aliases: &[],
        opcode: 0x1ac06800,
        mask: 0x7fe0fc00,
        class: InsnClass::CSSC,
        feature_set: InsnFeatureSet::CSSC,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rm,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SF_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::CSSC(CSSC::SMIN_Rd_Rn_Rm(SMIN_Rd_Rn_Rm::from(bits)))
    }
}
impl InsnOpcode for SMIN_Rd_Rn_Rm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SMIN_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "smin",
        aliases: &[],
        opcode: 0x40a0000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_5,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_5,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::SMIN_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(
            SMIN_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5::from(bits),
        ))
    }
}
impl InsnOpcode for SMIN_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SMIN_SVE_Zd_SVE_Zd_SVE_SIMM8 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "smin",
        aliases: &[],
        opcode: 0x252ac000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_SIMM8,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_imm8,
                    lsb: 5,
                    width: 8,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::SMIN_SVE_Zd_SVE_Zd_SVE_SIMM8(
            SMIN_SVE_Zd_SVE_Zd_SVE_SIMM8::from(bits),
        ))
    }
}
impl InsnOpcode for SMIN_SVE_Zd_SVE_Zd_SVE_SIMM8 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SMIN_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "smin",
        aliases: &[],
        opcode: 0xe206c00,
        mask: 0xbf20fc00,
        class: InsnClass::ASIMDSAME,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSAME(ASIMDSAME::SMIN_Vd_Vn_Vm(SMIN_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for SMIN_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SMINP_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sminp",
        aliases: &[],
        opcode: 0x4416a000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::SMINP_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(
            SMINP_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for SMINP_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SMINP_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sminp",
        aliases: &[],
        opcode: 0xe20ac00,
        mask: 0xbf20fc00,
        class: InsnClass::ASIMDSAME,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSAME(ASIMDSAME::SMINP_Vd_Vn_Vm(SMINP_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for SMINP_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SMINQV_Vd_SVE_Pg3_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sminqv",
        aliases: &[],
        opcode: 0x40e2000,
        mask: 0xff3fe000,
        class: InsnClass::SVE2_URQVS,
        feature_set: InsnFeatureSet::SVE2P1,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_16B, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE2_URQVS(SVE2_URQVS::SMINQV_Vd_SVE_Pg3_SVE_Zn(
            SMINQV_Vd_SVE_Pg3_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for SMINQV_Vd_SVE_Pg3_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SMINV_SVE_Vd_SVE_Pg3_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sminv",
        aliases: &[],
        opcode: 0x40a2000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Vd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::SMINV_SVE_Vd_SVE_Pg3_SVE_Zn(
            SMINV_SVE_Vd_SVE_Pg3_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for SMINV_SVE_Vd_SVE_Pg3_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SMINV_Fd_Vn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sminv",
        aliases: &[],
        opcode: 0xe31a800,
        mask: 0xbf3ffc00,
        class: InsnClass::ASIMDALL,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Fd,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDALL(ASIMDALL::SMINV_Fd_Vn(SMINV_Fd_Vn::from(bits)))
    }
}
impl InsnOpcode for SMINV_Fd_Vn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SMLAL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm_INDEX3_10 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "smlal",
        aliases: &[],
        opcode: 0xc1c01000,
        mask: 0xfff01018,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off3x2,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_0,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm_INDEX3_10,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zm,
                        lsb: 16,
                        width: 4,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm1_15,
                        lsb: 15,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_10,
                        lsb: 10,
                        width: 2,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::SMLAL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm_INDEX3_10(
            SMLAL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm_INDEX3_10::from(bits),
        ))
    }
}
impl InsnOpcode for SMLAL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm_INDEX3_10 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SMLAL_SME_ZA_array_off2x2_SME_Znx2_SME_Zm_INDEX3_2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "smlal",
        aliases: &[],
        opcode: 0xc1d01000,
        mask: 0xfff09038,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off2x2,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_0,
                        lsb: 0,
                        width: 2,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn2,
                    lsb: 6,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm_INDEX3_2,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zm,
                        lsb: 16,
                        width: 4,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_10,
                        lsb: 10,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm1_2,
                        lsb: 2,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(
            SME_MISC::SMLAL_SME_ZA_array_off2x2_SME_Znx2_SME_Zm_INDEX3_2(
                SMLAL_SME_ZA_array_off2x2_SME_Znx2_SME_Zm_INDEX3_2::from(bits),
            ),
        )
    }
}
impl InsnOpcode for SMLAL_SME_ZA_array_off2x2_SME_Znx2_SME_Zm_INDEX3_2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SMLAL_SME_ZA_array_off2x2_SME_Znx4_SME_Zm_INDEX3_2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "smlal",
        aliases: &[],
        opcode: 0xc1d09000,
        mask: 0xfff09078,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off2x2,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_0,
                        lsb: 0,
                        width: 2,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn4,
                    lsb: 7,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm_INDEX3_2,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zm,
                        lsb: 16,
                        width: 4,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_10,
                        lsb: 10,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm1_2,
                        lsb: 2,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_4.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(
            SME_MISC::SMLAL_SME_ZA_array_off2x2_SME_Znx4_SME_Zm_INDEX3_2(
                SMLAL_SME_ZA_array_off2x2_SME_Znx4_SME_Zm_INDEX3_2::from(bits),
            ),
        )
    }
}
impl InsnOpcode for SMLAL_SME_ZA_array_off2x2_SME_Znx4_SME_Zm_INDEX3_2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SMLAL_SME_ZA_array_off2x2_SVE_ZnxN_SME_Zm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "smlal",
        aliases: &[],
        opcode: 0xc1600800,
        mask: 0xfff09c1c,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off2x2,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_0,
                        lsb: 0,
                        width: 2,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ZnxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm,
                    lsb: 16,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::SMLAL_SME_ZA_array_off2x2_SVE_ZnxN_SME_Zm(
            SMLAL_SME_ZA_array_off2x2_SVE_ZnxN_SME_Zm::from(bits),
        ))
    }
}
impl InsnOpcode for SMLAL_SME_ZA_array_off2x2_SVE_ZnxN_SME_Zm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SMLAL_SME_ZA_array_off2x2_S_S_SVE_ZnxN_S_H_SME_Zm_S_H {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "smlal",
        aliases: &[],
        opcode: 0xc1700800,
        mask: 0xfff09c1c,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off2x2,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_0,
                        lsb: 0,
                        width: 2,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ZnxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm,
                    lsb: 16,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_4.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(
            SME_MISC::SMLAL_SME_ZA_array_off2x2_S_S_SVE_ZnxN_S_H_SME_Zm_S_H(
                SMLAL_SME_ZA_array_off2x2_S_S_SVE_ZnxN_S_H_SME_Zm_S_H::from(bits),
            ),
        )
    }
}
impl InsnOpcode for SMLAL_SME_ZA_array_off2x2_S_S_SVE_ZnxN_S_H_SME_Zm_S_H {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SMLAL_SME_ZA_array_off2x2_SME_Znx2_SME_Zmx2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "smlal",
        aliases: &[],
        opcode: 0xc1e00800,
        mask: 0xffe19c3c,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off2x2,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_0,
                        lsb: 0,
                        width: 2,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn2,
                    lsb: 6,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zmx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm2,
                    lsb: 17,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::SMLAL_SME_ZA_array_off2x2_SME_Znx2_SME_Zmx2(
            SMLAL_SME_ZA_array_off2x2_SME_Znx2_SME_Zmx2::from(bits),
        ))
    }
}
impl InsnOpcode for SMLAL_SME_ZA_array_off2x2_SME_Znx2_SME_Zmx2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SMLAL_SME_ZA_array_off2x2_SME_Znx4_SME_Zmx4 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "smlal",
        aliases: &[],
        opcode: 0xc1e10800,
        mask: 0xffe39c7c,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off2x2,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_0,
                        lsb: 0,
                        width: 2,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn4,
                    lsb: 7,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zmx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm4,
                    lsb: 18,
                    width: 3,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_4.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::SMLAL_SME_ZA_array_off2x2_SME_Znx4_SME_Zmx4(
            SMLAL_SME_ZA_array_off2x2_SME_Znx4_SME_Zmx4::from(bits),
        ))
    }
}
impl InsnOpcode for SMLAL_SME_ZA_array_off2x2_SME_Znx4_SME_Zmx4 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SMLAL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "smlal",
        aliases: &[],
        opcode: 0xc1600c00,
        mask: 0xfff09c18,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off3x2,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_0,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm,
                    lsb: 16,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::SMLAL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm(
            SMLAL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm::from(bits),
        ))
    }
}
impl InsnOpcode for SMLAL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SMLAL_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "smlal",
        aliases: &[],
        opcode: 0xe208000,
        mask: 0xff20fc00,
        class: InsnClass::ASIMDDIFF,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8H, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_4H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_4H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDDIFF(ASIMDDIFF::SMLAL_Vd_Vn_Vm(SMLAL_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for SMLAL_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SMLAL_Vd_Vn_Em16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "smlal",
        aliases: &[],
        opcode: 0xf002000,
        mask: 0xff00f400,
        class: InsnClass::ASIMDELEM,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4S, InsnOperandQualifier::V_2D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_2S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Em16,
                class: InsnOperandClass::SIMD_ELEMENT,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDELEM(ASIMDELEM::SMLAL_Vd_Vn_Em16(SMLAL_Vd_Vn_Em16::from(bits)))
    }
}
impl InsnOpcode for SMLAL_Vd_Vn_Em16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SMLAL2_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "smlal2",
        aliases: &[],
        opcode: 0x4e208000,
        mask: 0xff20fc00,
        class: InsnClass::ASIMDDIFF,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8H, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_16B, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_16B, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDDIFF(ASIMDDIFF::SMLAL2_Vd_Vn_Vm(SMLAL2_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for SMLAL2_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SMLAL2_Vd_Vn_Em16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "smlal2",
        aliases: &[],
        opcode: 0x4f002000,
        mask: 0xff00f400,
        class: InsnClass::ASIMDELEM,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4S, InsnOperandQualifier::V_2D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8H, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Em16,
                class: InsnOperandClass::SIMD_ELEMENT,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDELEM(ASIMDELEM::SMLAL2_Vd_Vn_Em16(SMLAL2_Vd_Vn_Em16::from(bits)))
    }
}
impl InsnOpcode for SMLAL2_Vd_Vn_Em16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SMLALB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "smlalb",
        aliases: &[],
        opcode: 0x44a08000,
        mask: 0xffe0f400,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm3_11_INDEX,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_i3h2,
                        lsb: 19,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_i3l,
                        lsb: 11,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_imm3,
                        lsb: 16,
                        width: 3,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::SMLALB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX(
            SMLALB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX::from(bits),
        ))
    }
}
impl InsnOpcode for SMLALB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SMLALB_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "smlalb",
        aliases: &[],
        opcode: 0x44e08000,
        mask: 0xffe0f400,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm4_11_INDEX,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_i2h,
                        lsb: 20,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_i3l,
                        lsb: 11,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_imm4,
                        lsb: 16,
                        width: 4,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::SMLALB_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX(
            SMLALB_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX::from(bits),
        ))
    }
}
impl InsnOpcode for SMLALB_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SMLALB_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "smlalb",
        aliases: &[],
        opcode: 0x44004000,
        mask: 0xff20fc00,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::SMLALB_SVE_Zd_SVE_Zn_SVE_Zm_16(
            SMLALB_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for SMLALB_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SMLALL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm_INDEX4_10 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "smlall",
        aliases: &[],
        opcode: 0xc1000000,
        mask: 0xfff0001c,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off2x4,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_0,
                        lsb: 0,
                        width: 2,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm_INDEX4_10,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zm,
                        lsb: 16,
                        width: 4,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm1_15,
                        lsb: 15,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_10,
                        lsb: 10,
                        width: 3,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(
            SME_MISC::SMLALL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm_INDEX4_10(
                SMLALL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm_INDEX4_10::from(bits),
            ),
        )
    }
}
impl InsnOpcode for SMLALL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm_INDEX4_10 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SMLALL_SME_ZA_array_off1x4_SME_Znx2_SME_Zm_INDEX4_1 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "smlall",
        aliases: &[],
        opcode: 0xc1100000,
        mask: 0xfff09038,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off1x4,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm1_0,
                        lsb: 0,
                        width: 1,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn2,
                    lsb: 6,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm_INDEX4_1,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zm,
                        lsb: 16,
                        width: 4,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_10,
                        lsb: 10,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_1,
                        lsb: 1,
                        width: 2,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(
            SME_MISC::SMLALL_SME_ZA_array_off1x4_SME_Znx2_SME_Zm_INDEX4_1(
                SMLALL_SME_ZA_array_off1x4_SME_Znx2_SME_Zm_INDEX4_1::from(bits),
            ),
        )
    }
}
impl InsnOpcode for SMLALL_SME_ZA_array_off1x4_SME_Znx2_SME_Zm_INDEX4_1 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SMLALL_SME_ZA_array_off1x4_SME_Znx4_SME_Zm_INDEX4_1 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "smlall",
        aliases: &[],
        opcode: 0xc1108000,
        mask: 0xfff09078,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off1x4,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm1_0,
                        lsb: 0,
                        width: 1,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn4,
                    lsb: 7,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm_INDEX4_1,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zm,
                        lsb: 16,
                        width: 4,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_10,
                        lsb: 10,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_1,
                        lsb: 1,
                        width: 2,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_4.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(
            SME_MISC::SMLALL_SME_ZA_array_off1x4_SME_Znx4_SME_Zm_INDEX4_1(
                SMLALL_SME_ZA_array_off1x4_SME_Znx4_SME_Zm_INDEX4_1::from(bits),
            ),
        )
    }
}
impl InsnOpcode for SMLALL_SME_ZA_array_off1x4_SME_Znx4_SME_Zm_INDEX4_1 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SMLALL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm_INDEX3_10 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "smlall",
        aliases: &[],
        opcode: 0xc1800000,
        mask: 0xfff0101c,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2_I16I64,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off2x4,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_0,
                        lsb: 0,
                        width: 2,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm_INDEX3_10,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zm,
                        lsb: 16,
                        width: 4,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm1_15,
                        lsb: 15,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_10,
                        lsb: 10,
                        width: 2,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(
            SME_MISC::SMLALL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm_INDEX3_10(
                SMLALL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm_INDEX3_10::from(bits),
            ),
        )
    }
}
impl InsnOpcode for SMLALL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm_INDEX3_10 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SMLALL_SME_ZA_array_off1x4_SME_Znx2_SME_Zm_INDEX3_1 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "smlall",
        aliases: &[],
        opcode: 0xc1900000,
        mask: 0xfff09838,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2_I16I64,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off1x4,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm1_0,
                        lsb: 0,
                        width: 1,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn2,
                    lsb: 6,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm_INDEX3_1,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zm,
                        lsb: 16,
                        width: 4,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm1_10,
                        lsb: 10,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_1,
                        lsb: 1,
                        width: 2,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(
            SME_MISC::SMLALL_SME_ZA_array_off1x4_SME_Znx2_SME_Zm_INDEX3_1(
                SMLALL_SME_ZA_array_off1x4_SME_Znx2_SME_Zm_INDEX3_1::from(bits),
            ),
        )
    }
}
impl InsnOpcode for SMLALL_SME_ZA_array_off1x4_SME_Znx2_SME_Zm_INDEX3_1 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SMLALL_SME_ZA_array_off1x4_SME_Znx4_SME_Zm_INDEX3_1 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "smlall",
        aliases: &[],
        opcode: 0xc1908000,
        mask: 0xfff09878,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2_I16I64,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off1x4,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm1_0,
                        lsb: 0,
                        width: 1,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn4,
                    lsb: 7,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm_INDEX3_1,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zm,
                        lsb: 16,
                        width: 4,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm1_10,
                        lsb: 10,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_1,
                        lsb: 1,
                        width: 2,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_4.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(
            SME_MISC::SMLALL_SME_ZA_array_off1x4_SME_Znx4_SME_Zm_INDEX3_1(
                SMLALL_SME_ZA_array_off1x4_SME_Znx4_SME_Zm_INDEX3_1::from(bits),
            ),
        )
    }
}
impl InsnOpcode for SMLALL_SME_ZA_array_off1x4_SME_Znx4_SME_Zm_INDEX3_1 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SMLALL_SME_ZA_array_off1x4_SVE_ZnxN_SME_Zm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "smlall",
        aliases: &[],
        opcode: 0xc1200000,
        mask: 0xffb09c1e,
        class: InsnClass::SME_INT_SD,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off1x4,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm1_0,
                        lsb: 0,
                        width: 1,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ZnxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm,
                    lsb: 16,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_INT_SD(SME_INT_SD::SMLALL_SME_ZA_array_off1x4_SVE_ZnxN_SME_Zm(
            SMLALL_SME_ZA_array_off1x4_SVE_ZnxN_SME_Zm::from(bits),
        ))
    }
}
impl InsnOpcode for SMLALL_SME_ZA_array_off1x4_SVE_ZnxN_SME_Zm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SMLALL_SME_ZA_array_off1x4_S_S_SVE_ZnxN_S_B_SME_Zm_S_B {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "smlall",
        aliases: &[],
        opcode: 0xc1300000,
        mask: 0xffb09c1e,
        class: InsnClass::SME_INT_SD,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off1x4,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm1_0,
                        lsb: 0,
                        width: 1,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ZnxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm,
                    lsb: 16,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_4.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_INT_SD(
            SME_INT_SD::SMLALL_SME_ZA_array_off1x4_S_S_SVE_ZnxN_S_B_SME_Zm_S_B(
                SMLALL_SME_ZA_array_off1x4_S_S_SVE_ZnxN_S_B_SME_Zm_S_B::from(bits),
            ),
        )
    }
}
impl InsnOpcode for SMLALL_SME_ZA_array_off1x4_S_S_SVE_ZnxN_S_B_SME_Zm_S_B {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SMLALL_SME_ZA_array_off1x4_SME_Znx2_SME_Zmx2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "smlall",
        aliases: &[],
        opcode: 0xc1a00000,
        mask: 0xffa19c3e,
        class: InsnClass::SME_INT_SD,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off1x4,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm1_0,
                        lsb: 0,
                        width: 1,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn2,
                    lsb: 6,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zmx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm2,
                    lsb: 17,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_INT_SD(SME_INT_SD::SMLALL_SME_ZA_array_off1x4_SME_Znx2_SME_Zmx2(
            SMLALL_SME_ZA_array_off1x4_SME_Znx2_SME_Zmx2::from(bits),
        ))
    }
}
impl InsnOpcode for SMLALL_SME_ZA_array_off1x4_SME_Znx2_SME_Zmx2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SMLALL_SME_ZA_array_off1x4_SME_Znx4_SME_Zmx4 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "smlall",
        aliases: &[],
        opcode: 0xc1a10000,
        mask: 0xffa39c7e,
        class: InsnClass::SME_INT_SD,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off1x4,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm1_0,
                        lsb: 0,
                        width: 1,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn4,
                    lsb: 7,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zmx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm4,
                    lsb: 18,
                    width: 3,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_4.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_INT_SD(SME_INT_SD::SMLALL_SME_ZA_array_off1x4_SME_Znx4_SME_Zmx4(
            SMLALL_SME_ZA_array_off1x4_SME_Znx4_SME_Zmx4::from(bits),
        ))
    }
}
impl InsnOpcode for SMLALL_SME_ZA_array_off1x4_SME_Znx4_SME_Zmx4 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SMLALL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "smlall",
        aliases: &[],
        opcode: 0xc1200400,
        mask: 0xffb09c1c,
        class: InsnClass::SME_INT_SD,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off2x4,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_0,
                        lsb: 0,
                        width: 2,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm,
                    lsb: 16,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_INT_SD(SME_INT_SD::SMLALL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm(
            SMLALL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm::from(bits),
        ))
    }
}
impl InsnOpcode for SMLALL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SMLALT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "smlalt",
        aliases: &[],
        opcode: 0x44a08400,
        mask: 0xffe0f400,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm3_11_INDEX,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_i3h2,
                        lsb: 19,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_i3l,
                        lsb: 11,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_imm3,
                        lsb: 16,
                        width: 3,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::SMLALT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX(
            SMLALT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX::from(bits),
        ))
    }
}
impl InsnOpcode for SMLALT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SMLALT_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "smlalt",
        aliases: &[],
        opcode: 0x44e08400,
        mask: 0xffe0f400,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm4_11_INDEX,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_i2h,
                        lsb: 20,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_i3l,
                        lsb: 11,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_imm4,
                        lsb: 16,
                        width: 4,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::SMLALT_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX(
            SMLALT_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX::from(bits),
        ))
    }
}
impl InsnOpcode for SMLALT_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SMLALT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "smlalt",
        aliases: &[],
        opcode: 0x44004400,
        mask: 0xff20fc00,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::SMLALT_SVE_Zd_SVE_Zn_SVE_Zm_16(
            SMLALT_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for SMLALT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SMLSL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm_INDEX3_10 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "smlsl",
        aliases: &[],
        opcode: 0xc1c01008,
        mask: 0xfff01018,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off3x2,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_0,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm_INDEX3_10,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zm,
                        lsb: 16,
                        width: 4,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm1_15,
                        lsb: 15,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_10,
                        lsb: 10,
                        width: 2,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::SMLSL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm_INDEX3_10(
            SMLSL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm_INDEX3_10::from(bits),
        ))
    }
}
impl InsnOpcode for SMLSL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm_INDEX3_10 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SMLSL_SME_ZA_array_off2x2_SME_Znx2_SME_Zm_INDEX3_2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "smlsl",
        aliases: &[],
        opcode: 0xc1d01008,
        mask: 0xfff09038,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off2x2,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_0,
                        lsb: 0,
                        width: 2,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn2,
                    lsb: 6,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm_INDEX3_2,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zm,
                        lsb: 16,
                        width: 4,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_10,
                        lsb: 10,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm1_2,
                        lsb: 2,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(
            SME_MISC::SMLSL_SME_ZA_array_off2x2_SME_Znx2_SME_Zm_INDEX3_2(
                SMLSL_SME_ZA_array_off2x2_SME_Znx2_SME_Zm_INDEX3_2::from(bits),
            ),
        )
    }
}
impl InsnOpcode for SMLSL_SME_ZA_array_off2x2_SME_Znx2_SME_Zm_INDEX3_2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SMLSL_SME_ZA_array_off2x2_SME_Znx4_SME_Zm_INDEX3_2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "smlsl",
        aliases: &[],
        opcode: 0xc1d09008,
        mask: 0xfff09078,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off2x2,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_0,
                        lsb: 0,
                        width: 2,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn4,
                    lsb: 7,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm_INDEX3_2,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zm,
                        lsb: 16,
                        width: 4,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_10,
                        lsb: 10,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm1_2,
                        lsb: 2,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_4.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(
            SME_MISC::SMLSL_SME_ZA_array_off2x2_SME_Znx4_SME_Zm_INDEX3_2(
                SMLSL_SME_ZA_array_off2x2_SME_Znx4_SME_Zm_INDEX3_2::from(bits),
            ),
        )
    }
}
impl InsnOpcode for SMLSL_SME_ZA_array_off2x2_SME_Znx4_SME_Zm_INDEX3_2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SMLSL_SME_ZA_array_off2x2_SVE_ZnxN_SME_Zm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "smlsl",
        aliases: &[],
        opcode: 0xc1600808,
        mask: 0xfff09c1c,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off2x2,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_0,
                        lsb: 0,
                        width: 2,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ZnxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm,
                    lsb: 16,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::SMLSL_SME_ZA_array_off2x2_SVE_ZnxN_SME_Zm(
            SMLSL_SME_ZA_array_off2x2_SVE_ZnxN_SME_Zm::from(bits),
        ))
    }
}
impl InsnOpcode for SMLSL_SME_ZA_array_off2x2_SVE_ZnxN_SME_Zm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SMLSL_SME_ZA_array_off2x2_S_S_SVE_ZnxN_S_H_SME_Zm_S_H {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "smlsl",
        aliases: &[],
        opcode: 0xc1700808,
        mask: 0xfff09c1c,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off2x2,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_0,
                        lsb: 0,
                        width: 2,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ZnxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm,
                    lsb: 16,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_4.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(
            SME_MISC::SMLSL_SME_ZA_array_off2x2_S_S_SVE_ZnxN_S_H_SME_Zm_S_H(
                SMLSL_SME_ZA_array_off2x2_S_S_SVE_ZnxN_S_H_SME_Zm_S_H::from(bits),
            ),
        )
    }
}
impl InsnOpcode for SMLSL_SME_ZA_array_off2x2_S_S_SVE_ZnxN_S_H_SME_Zm_S_H {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SMLSL_SME_ZA_array_off2x2_SME_Znx2_SME_Zmx2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "smlsl",
        aliases: &[],
        opcode: 0xc1e00808,
        mask: 0xffe19c3c,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off2x2,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_0,
                        lsb: 0,
                        width: 2,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn2,
                    lsb: 6,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zmx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm2,
                    lsb: 17,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::SMLSL_SME_ZA_array_off2x2_SME_Znx2_SME_Zmx2(
            SMLSL_SME_ZA_array_off2x2_SME_Znx2_SME_Zmx2::from(bits),
        ))
    }
}
impl InsnOpcode for SMLSL_SME_ZA_array_off2x2_SME_Znx2_SME_Zmx2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SMLSL_SME_ZA_array_off2x2_SME_Znx4_SME_Zmx4 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "smlsl",
        aliases: &[],
        opcode: 0xc1e10808,
        mask: 0xffe39c7c,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off2x2,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_0,
                        lsb: 0,
                        width: 2,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn4,
                    lsb: 7,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zmx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm4,
                    lsb: 18,
                    width: 3,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_4.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::SMLSL_SME_ZA_array_off2x2_SME_Znx4_SME_Zmx4(
            SMLSL_SME_ZA_array_off2x2_SME_Znx4_SME_Zmx4::from(bits),
        ))
    }
}
impl InsnOpcode for SMLSL_SME_ZA_array_off2x2_SME_Znx4_SME_Zmx4 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SMLSL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "smlsl",
        aliases: &[],
        opcode: 0xc1600c08,
        mask: 0xfff09c18,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off3x2,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_0,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm,
                    lsb: 16,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::SMLSL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm(
            SMLSL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm::from(bits),
        ))
    }
}
impl InsnOpcode for SMLSL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SMLSL_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "smlsl",
        aliases: &[],
        opcode: 0xe20a000,
        mask: 0xff20fc00,
        class: InsnClass::ASIMDDIFF,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8H, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_4H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_4H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDDIFF(ASIMDDIFF::SMLSL_Vd_Vn_Vm(SMLSL_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for SMLSL_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SMLSL_Vd_Vn_Em16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "smlsl",
        aliases: &[],
        opcode: 0xf006000,
        mask: 0xff00f400,
        class: InsnClass::ASIMDELEM,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4S, InsnOperandQualifier::V_2D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_2S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Em16,
                class: InsnOperandClass::SIMD_ELEMENT,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDELEM(ASIMDELEM::SMLSL_Vd_Vn_Em16(SMLSL_Vd_Vn_Em16::from(bits)))
    }
}
impl InsnOpcode for SMLSL_Vd_Vn_Em16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SMLSL2_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "smlsl2",
        aliases: &[],
        opcode: 0x4e20a000,
        mask: 0xff20fc00,
        class: InsnClass::ASIMDDIFF,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8H, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_16B, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_16B, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDDIFF(ASIMDDIFF::SMLSL2_Vd_Vn_Vm(SMLSL2_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for SMLSL2_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SMLSL2_Vd_Vn_Em16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "smlsl2",
        aliases: &[],
        opcode: 0x4f006000,
        mask: 0xff00f400,
        class: InsnClass::ASIMDELEM,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4S, InsnOperandQualifier::V_2D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8H, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Em16,
                class: InsnOperandClass::SIMD_ELEMENT,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDELEM(ASIMDELEM::SMLSL2_Vd_Vn_Em16(SMLSL2_Vd_Vn_Em16::from(bits)))
    }
}
impl InsnOpcode for SMLSL2_Vd_Vn_Em16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SMLSLB_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "smlslb",
        aliases: &[],
        opcode: 0x44005000,
        mask: 0xff20fc00,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::SMLSLB_SVE_Zd_SVE_Zn_SVE_Zm_16(
            SMLSLB_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for SMLSLB_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SMLSLB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "smlslb",
        aliases: &[],
        opcode: 0x44a0a000,
        mask: 0xffe0f400,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm3_11_INDEX,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_i3h2,
                        lsb: 19,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_i3l,
                        lsb: 11,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_imm3,
                        lsb: 16,
                        width: 3,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::SMLSLB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX(
            SMLSLB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX::from(bits),
        ))
    }
}
impl InsnOpcode for SMLSLB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SMLSLB_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "smlslb",
        aliases: &[],
        opcode: 0x44e0a000,
        mask: 0xffe0f400,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm4_11_INDEX,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_i2h,
                        lsb: 20,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_i3l,
                        lsb: 11,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_imm4,
                        lsb: 16,
                        width: 4,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::SMLSLB_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX(
            SMLSLB_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX::from(bits),
        ))
    }
}
impl InsnOpcode for SMLSLB_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SMLSLL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm_INDEX4_10 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "smlsll",
        aliases: &[],
        opcode: 0xc1000008,
        mask: 0xfff0001c,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off2x4,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_0,
                        lsb: 0,
                        width: 2,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm_INDEX4_10,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zm,
                        lsb: 16,
                        width: 4,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm1_15,
                        lsb: 15,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_10,
                        lsb: 10,
                        width: 3,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(
            SME_MISC::SMLSLL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm_INDEX4_10(
                SMLSLL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm_INDEX4_10::from(bits),
            ),
        )
    }
}
impl InsnOpcode for SMLSLL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm_INDEX4_10 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SMLSLL_SME_ZA_array_off1x4_SME_Znx2_SME_Zm_INDEX4_1 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "smlsll",
        aliases: &[],
        opcode: 0xc1100008,
        mask: 0xfff09038,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off1x4,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm1_0,
                        lsb: 0,
                        width: 1,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn2,
                    lsb: 6,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm_INDEX4_1,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zm,
                        lsb: 16,
                        width: 4,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_10,
                        lsb: 10,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_1,
                        lsb: 1,
                        width: 2,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(
            SME_MISC::SMLSLL_SME_ZA_array_off1x4_SME_Znx2_SME_Zm_INDEX4_1(
                SMLSLL_SME_ZA_array_off1x4_SME_Znx2_SME_Zm_INDEX4_1::from(bits),
            ),
        )
    }
}
impl InsnOpcode for SMLSLL_SME_ZA_array_off1x4_SME_Znx2_SME_Zm_INDEX4_1 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SMLSLL_SME_ZA_array_off1x4_SME_Znx4_SME_Zm_INDEX4_1 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "smlsll",
        aliases: &[],
        opcode: 0xc1108008,
        mask: 0xfff09078,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off1x4,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm1_0,
                        lsb: 0,
                        width: 1,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn4,
                    lsb: 7,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm_INDEX4_1,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zm,
                        lsb: 16,
                        width: 4,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_10,
                        lsb: 10,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_1,
                        lsb: 1,
                        width: 2,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_4.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(
            SME_MISC::SMLSLL_SME_ZA_array_off1x4_SME_Znx4_SME_Zm_INDEX4_1(
                SMLSLL_SME_ZA_array_off1x4_SME_Znx4_SME_Zm_INDEX4_1::from(bits),
            ),
        )
    }
}
impl InsnOpcode for SMLSLL_SME_ZA_array_off1x4_SME_Znx4_SME_Zm_INDEX4_1 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SMLSLL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm_INDEX3_10 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "smlsll",
        aliases: &[],
        opcode: 0xc1800008,
        mask: 0xfff0101c,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2_I16I64,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off2x4,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_0,
                        lsb: 0,
                        width: 2,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm_INDEX3_10,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zm,
                        lsb: 16,
                        width: 4,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm1_15,
                        lsb: 15,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_10,
                        lsb: 10,
                        width: 2,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(
            SME_MISC::SMLSLL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm_INDEX3_10(
                SMLSLL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm_INDEX3_10::from(bits),
            ),
        )
    }
}
impl InsnOpcode for SMLSLL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm_INDEX3_10 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SMLSLL_SME_ZA_array_off1x4_SME_Znx2_SME_Zm_INDEX3_1 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "smlsll",
        aliases: &[],
        opcode: 0xc1900008,
        mask: 0xfff09838,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2_I16I64,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off1x4,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm1_0,
                        lsb: 0,
                        width: 1,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn2,
                    lsb: 6,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm_INDEX3_1,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zm,
                        lsb: 16,
                        width: 4,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm1_10,
                        lsb: 10,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_1,
                        lsb: 1,
                        width: 2,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(
            SME_MISC::SMLSLL_SME_ZA_array_off1x4_SME_Znx2_SME_Zm_INDEX3_1(
                SMLSLL_SME_ZA_array_off1x4_SME_Znx2_SME_Zm_INDEX3_1::from(bits),
            ),
        )
    }
}
impl InsnOpcode for SMLSLL_SME_ZA_array_off1x4_SME_Znx2_SME_Zm_INDEX3_1 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SMLSLL_SME_ZA_array_off1x4_SME_Znx4_SME_Zm_INDEX3_1 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "smlsll",
        aliases: &[],
        opcode: 0xc1908008,
        mask: 0xfff09878,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2_I16I64,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off1x4,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm1_0,
                        lsb: 0,
                        width: 1,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn4,
                    lsb: 7,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm_INDEX3_1,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zm,
                        lsb: 16,
                        width: 4,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm1_10,
                        lsb: 10,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_1,
                        lsb: 1,
                        width: 2,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_4.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(
            SME_MISC::SMLSLL_SME_ZA_array_off1x4_SME_Znx4_SME_Zm_INDEX3_1(
                SMLSLL_SME_ZA_array_off1x4_SME_Znx4_SME_Zm_INDEX3_1::from(bits),
            ),
        )
    }
}
impl InsnOpcode for SMLSLL_SME_ZA_array_off1x4_SME_Znx4_SME_Zm_INDEX3_1 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SMLSLL_SME_ZA_array_off1x4_SVE_ZnxN_SME_Zm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "smlsll",
        aliases: &[],
        opcode: 0xc1200008,
        mask: 0xffb09c1e,
        class: InsnClass::SME_INT_SD,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off1x4,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm1_0,
                        lsb: 0,
                        width: 1,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ZnxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm,
                    lsb: 16,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_INT_SD(SME_INT_SD::SMLSLL_SME_ZA_array_off1x4_SVE_ZnxN_SME_Zm(
            SMLSLL_SME_ZA_array_off1x4_SVE_ZnxN_SME_Zm::from(bits),
        ))
    }
}
impl InsnOpcode for SMLSLL_SME_ZA_array_off1x4_SVE_ZnxN_SME_Zm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SMLSLL_SME_ZA_array_off1x4_S_S_SVE_ZnxN_S_B_SME_Zm_S_B {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "smlsll",
        aliases: &[],
        opcode: 0xc1300008,
        mask: 0xffb09c1e,
        class: InsnClass::SME_INT_SD,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off1x4,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm1_0,
                        lsb: 0,
                        width: 1,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ZnxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm,
                    lsb: 16,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_4.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_INT_SD(
            SME_INT_SD::SMLSLL_SME_ZA_array_off1x4_S_S_SVE_ZnxN_S_B_SME_Zm_S_B(
                SMLSLL_SME_ZA_array_off1x4_S_S_SVE_ZnxN_S_B_SME_Zm_S_B::from(bits),
            ),
        )
    }
}
impl InsnOpcode for SMLSLL_SME_ZA_array_off1x4_S_S_SVE_ZnxN_S_B_SME_Zm_S_B {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SMLSLL_SME_ZA_array_off1x4_SME_Znx2_SME_Zmx2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "smlsll",
        aliases: &[],
        opcode: 0xc1a00008,
        mask: 0xffa19c3e,
        class: InsnClass::SME_INT_SD,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off1x4,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm1_0,
                        lsb: 0,
                        width: 1,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn2,
                    lsb: 6,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zmx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm2,
                    lsb: 17,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_INT_SD(SME_INT_SD::SMLSLL_SME_ZA_array_off1x4_SME_Znx2_SME_Zmx2(
            SMLSLL_SME_ZA_array_off1x4_SME_Znx2_SME_Zmx2::from(bits),
        ))
    }
}
impl InsnOpcode for SMLSLL_SME_ZA_array_off1x4_SME_Znx2_SME_Zmx2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SMLSLL_SME_ZA_array_off1x4_SME_Znx4_SME_Zmx4 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "smlsll",
        aliases: &[],
        opcode: 0xc1a10008,
        mask: 0xffa39c7e,
        class: InsnClass::SME_INT_SD,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off1x4,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm1_0,
                        lsb: 0,
                        width: 1,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn4,
                    lsb: 7,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zmx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm4,
                    lsb: 18,
                    width: 3,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_4.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_INT_SD(SME_INT_SD::SMLSLL_SME_ZA_array_off1x4_SME_Znx4_SME_Zmx4(
            SMLSLL_SME_ZA_array_off1x4_SME_Znx4_SME_Zmx4::from(bits),
        ))
    }
}
impl InsnOpcode for SMLSLL_SME_ZA_array_off1x4_SME_Znx4_SME_Zmx4 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SMLSLL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "smlsll",
        aliases: &[],
        opcode: 0xc1200408,
        mask: 0xffb09c1c,
        class: InsnClass::SME_INT_SD,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off2x4,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_0,
                        lsb: 0,
                        width: 2,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm,
                    lsb: 16,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_INT_SD(SME_INT_SD::SMLSLL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm(
            SMLSLL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm::from(bits),
        ))
    }
}
impl InsnOpcode for SMLSLL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SMLSLT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "smlslt",
        aliases: &[],
        opcode: 0x44005400,
        mask: 0xff20fc00,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::SMLSLT_SVE_Zd_SVE_Zn_SVE_Zm_16(
            SMLSLT_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for SMLSLT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SMLSLT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "smlslt",
        aliases: &[],
        opcode: 0x44a0a400,
        mask: 0xffe0f400,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm3_11_INDEX,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_i3h2,
                        lsb: 19,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_i3l,
                        lsb: 11,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_imm3,
                        lsb: 16,
                        width: 3,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::SMLSLT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX(
            SMLSLT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX::from(bits),
        ))
    }
}
impl InsnOpcode for SMLSLT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SMLSLT_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "smlslt",
        aliases: &[],
        opcode: 0x44e0a400,
        mask: 0xffe0f400,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm4_11_INDEX,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_i2h,
                        lsb: 20,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_i3l,
                        lsb: 11,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_imm4,
                        lsb: 16,
                        width: 4,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::SMLSLT_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX(
            SMLSLT_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX::from(bits),
        ))
    }
}
impl InsnOpcode for SMLSLT_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SMMLA_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "smmla",
        aliases: &[],
        opcode: 0x45009800,
        mask: 0xffe0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::I8MM_SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::SMMLA_SVE_Zd_SVE_Zn_SVE_Zm_16(
            SMMLA_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for SMMLA_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SMMLA_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "smmla",
        aliases: &[],
        opcode: 0x4e80a400,
        mask: 0xffe0fc00,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::I8MM,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(AARCH64_MISC::SMMLA_Vd_Vn_Vm(SMMLA_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for SMMLA_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SMOPA_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "smopa",
        aliases: &[],
        opcode: 0xa0800000,
        mask: 0xffe0001c,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZAda_2b,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_ZAda_2b,
                    lsb: 0,
                    width: 2,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Pm,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Pm,
                    lsb: 13,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::SMOPA_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16(
            SMOPA_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for SMOPA_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SMOPA_SME_ZAda_2b_S_S_SVE_Pg3_P_M_SME_Pm_P_M_SVE_Zn_S_H_SVE_Zm_16_S_H {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "smopa",
        aliases: &[],
        opcode: 0xa0800008,
        mask: 0xffe0001c,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZAda_2b,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_ZAda_2b,
                    lsb: 0,
                    width: 2,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Pm,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Pm,
                    lsb: 13,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(
            SME_MISC::SMOPA_SME_ZAda_2b_S_S_SVE_Pg3_P_M_SME_Pm_P_M_SVE_Zn_S_H_SVE_Zm_16_S_H(
                SMOPA_SME_ZAda_2b_S_S_SVE_Pg3_P_M_SME_Pm_P_M_SVE_Zn_S_H_SVE_Zm_16_S_H::from(bits),
            ),
        )
    }
}
impl InsnOpcode for SMOPA_SME_ZAda_2b_S_S_SVE_Pg3_P_M_SME_Pm_P_M_SVE_Zn_S_H_SVE_Zm_16_S_H {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SMOPA_SME_ZAda_3b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "smopa",
        aliases: &[],
        opcode: 0xa0c00000,
        mask: 0xffe00018,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME_I16I64,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZAda_3b,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_ZAda_3b,
                    lsb: 0,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Pm,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Pm,
                    lsb: 13,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::SMOPA_SME_ZAda_3b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16(
            SMOPA_SME_ZAda_3b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for SMOPA_SME_ZAda_3b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SMOPS_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "smops",
        aliases: &[],
        opcode: 0xa0800010,
        mask: 0xffe0001c,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZAda_2b,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_ZAda_2b,
                    lsb: 0,
                    width: 2,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Pm,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Pm,
                    lsb: 13,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::SMOPS_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16(
            SMOPS_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for SMOPS_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SMOPS_SME_ZAda_2b_S_S_SVE_Pg3_P_M_SME_Pm_P_M_SVE_Zn_S_H_SVE_Zm_16_S_H {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "smops",
        aliases: &[],
        opcode: 0xa0800018,
        mask: 0xffe0001c,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZAda_2b,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_ZAda_2b,
                    lsb: 0,
                    width: 2,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Pm,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Pm,
                    lsb: 13,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(
            SME_MISC::SMOPS_SME_ZAda_2b_S_S_SVE_Pg3_P_M_SME_Pm_P_M_SVE_Zn_S_H_SVE_Zm_16_S_H(
                SMOPS_SME_ZAda_2b_S_S_SVE_Pg3_P_M_SME_Pm_P_M_SVE_Zn_S_H_SVE_Zm_16_S_H::from(bits),
            ),
        )
    }
}
impl InsnOpcode for SMOPS_SME_ZAda_2b_S_S_SVE_Pg3_P_M_SME_Pm_P_M_SVE_Zn_S_H_SVE_Zm_16_S_H {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SMOPS_SME_ZAda_3b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "smops",
        aliases: &[],
        opcode: 0xa0c00010,
        mask: 0xffe00018,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME_I16I64,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZAda_3b,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_ZAda_3b,
                    lsb: 0,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Pm,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Pm,
                    lsb: 13,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::SMOPS_SME_ZAda_3b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16(
            SMOPS_SME_ZAda_3b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for SMOPS_SME_ZAda_3b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SMOV_Rd_En {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "smov",
        aliases: &[],
        opcode: 0xe002c00,
        mask: 0xbfe0fc00,
        class: InsnClass::ASIMDINS,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::En,
                class: InsnOperandClass::SIMD_ELEMENT,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMV_GPRSIZE_IN_Q.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDINS(ASIMDINS::SMOV_Rd_En(SMOV_Rd_En::from(bits)))
    }
}
impl InsnOpcode for SMOV_Rd_En {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SMSTART {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "smstart",
        aliases: &[],
        opcode: 0xd503477f,
        mask: 0xffffffff,
        class: InsnClass::SME_START,
        feature_set: InsnFeatureSet::SME,
        operands: &[],
        flags: InsnFlags::const_from_bits(InsnFlags::IS_SYS_WRITE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_START(SME_START::SMSTART(SMSTART::from(bits)))
    }
}
impl InsnOpcode for SMSTART {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SMSTART_SME_SM_ZA {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "smstart",
        aliases: &[],
        opcode: 0xd503417f,
        mask: 0xfffff1ff,
        class: InsnClass::SME_START,
        feature_set: InsnFeatureSet::SME,
        operands: &[InsnOperand {
            kind: InsnOperandKind::SME_SM_ZA,
            class: InsnOperandClass::ADDRESS,
            qualifiers: &[],
            bit_fields: &[BitfieldSpec {
                bitfield: InsnBitField::CRm,
                lsb: 8,
                width: 4,
            }],
        }],
        flags: InsnFlags::const_from_bits(InsnFlags::IS_SYS_WRITE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_START(SME_START::SMSTART_SME_SM_ZA(SMSTART_SME_SM_ZA::from(bits)))
    }
}
impl InsnOpcode for SMSTART_SME_SM_ZA {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SMSTOP {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "smstop",
        aliases: &[],
        opcode: 0xd503467f,
        mask: 0xffffffff,
        class: InsnClass::SME_STOP,
        feature_set: InsnFeatureSet::SME,
        operands: &[],
        flags: InsnFlags::const_from_bits(InsnFlags::IS_SYS_WRITE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_STOP(SME_STOP::SMSTOP(SMSTOP::from(bits)))
    }
}
impl InsnOpcode for SMSTOP {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SMSTOP_SME_SM_ZA {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "smstop",
        aliases: &[],
        opcode: 0xd503407f,
        mask: 0xfffff1ff,
        class: InsnClass::SME_STOP,
        feature_set: InsnFeatureSet::SME,
        operands: &[InsnOperand {
            kind: InsnOperandKind::SME_SM_ZA,
            class: InsnOperandClass::ADDRESS,
            qualifiers: &[],
            bit_fields: &[BitfieldSpec {
                bitfield: InsnBitField::CRm,
                lsb: 8,
                width: 4,
            }],
        }],
        flags: InsnFlags::const_from_bits(InsnFlags::IS_SYS_WRITE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_STOP(SME_STOP::SMSTOP_SME_SM_ZA(SMSTOP_SME_SM_ZA::from(bits)))
    }
}
impl InsnOpcode for SMSTOP_SME_SM_ZA {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SMSUBL_Rd_Rn_Rm_Ra {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "smsubl",
        aliases: &[],
        opcode: 0x9b208000,
        mask: 0xffe08000,
        class: InsnClass::DP_3SRC,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rm,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Ra,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Ra,
                    lsb: 10,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ALIAS.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::DP_3SRC(DP_3SRC::SMSUBL_Rd_Rn_Rm_Ra(SMSUBL_Rd_Rn_Rm_Ra::from(bits)))
    }
}
impl InsnOpcode for SMSUBL_Rd_Rn_Rm_Ra {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SMULH_Rd_Rn_Rm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "smulh",
        aliases: &[],
        opcode: 0x9b407c00,
        mask: 0xffe0fc00,
        class: InsnClass::DP_3SRC,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rm,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::DP_3SRC(DP_3SRC::SMULH_Rd_Rn_Rm(SMULH_Rd_Rn_Rm::from(bits)))
    }
}
impl InsnOpcode for SMULH_Rd_Rn_Rm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SMULH_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "smulh",
        aliases: &[],
        opcode: 0x4120000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_5,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_5,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::SMULH_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(
            SMULH_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5::from(bits),
        ))
    }
}
impl InsnOpcode for SMULH_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SMULH_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "smulh",
        aliases: &[],
        opcode: 0x4206800,
        mask: 0xff20fc00,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::SMULH_SVE_Zd_SVE_Zn_SVE_Zm_16(
            SMULH_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for SMULH_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SMULL_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "smull",
        aliases: &[],
        opcode: 0xe20c000,
        mask: 0xff20fc00,
        class: InsnClass::ASIMDDIFF,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8H, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_4H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_4H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDDIFF(ASIMDDIFF::SMULL_Vd_Vn_Vm(SMULL_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for SMULL_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SMULL_Vd_Vn_Em16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "smull",
        aliases: &[],
        opcode: 0xf00a000,
        mask: 0xff00f400,
        class: InsnClass::ASIMDELEM,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4S, InsnOperandQualifier::V_2D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_2S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Em16,
                class: InsnOperandClass::SIMD_ELEMENT,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDELEM(ASIMDELEM::SMULL_Vd_Vn_Em16(SMULL_Vd_Vn_Em16::from(bits)))
    }
}
impl InsnOpcode for SMULL_Vd_Vn_Em16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SMULL2_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "smull2",
        aliases: &[],
        opcode: 0x4e20c000,
        mask: 0xff20fc00,
        class: InsnClass::ASIMDDIFF,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8H, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_16B, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_16B, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDDIFF(ASIMDDIFF::SMULL2_Vd_Vn_Vm(SMULL2_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for SMULL2_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SMULL2_Vd_Vn_Em16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "smull2",
        aliases: &[],
        opcode: 0x4f00a000,
        mask: 0xff00f400,
        class: InsnClass::ASIMDELEM,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4S, InsnOperandQualifier::V_2D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8H, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Em16,
                class: InsnOperandClass::SIMD_ELEMENT,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDELEM(ASIMDELEM::SMULL2_Vd_Vn_Em16(SMULL2_Vd_Vn_Em16::from(bits)))
    }
}
impl InsnOpcode for SMULL2_Vd_Vn_Em16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SMULLB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "smullb",
        aliases: &[],
        opcode: 0x44a0c000,
        mask: 0xffe0f400,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm3_11_INDEX,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_i3h2,
                        lsb: 19,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_i3l,
                        lsb: 11,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_imm3,
                        lsb: 16,
                        width: 3,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::SMULLB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX(
            SMULLB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX::from(bits),
        ))
    }
}
impl InsnOpcode for SMULLB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SMULLB_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "smullb",
        aliases: &[],
        opcode: 0x44e0c000,
        mask: 0xffe0f400,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm4_11_INDEX,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_i2h,
                        lsb: 20,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_i3l,
                        lsb: 11,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_imm4,
                        lsb: 16,
                        width: 4,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::SMULLB_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX(
            SMULLB_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX::from(bits),
        ))
    }
}
impl InsnOpcode for SMULLB_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SMULLB_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "smullb",
        aliases: &[],
        opcode: 0x45007000,
        mask: 0xff20fc00,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::SMULLB_SVE_Zd_SVE_Zn_SVE_Zm_16(
            SMULLB_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for SMULLB_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SMULLT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "smullt",
        aliases: &[],
        opcode: 0x44a0c400,
        mask: 0xffe0f400,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm3_11_INDEX,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_i3h2,
                        lsb: 19,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_i3l,
                        lsb: 11,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_imm3,
                        lsb: 16,
                        width: 3,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::SMULLT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX(
            SMULLT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX::from(bits),
        ))
    }
}
impl InsnOpcode for SMULLT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SMULLT_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "smullt",
        aliases: &[],
        opcode: 0x44e0c400,
        mask: 0xffe0f400,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm4_11_INDEX,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_i2h,
                        lsb: 20,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_i3l,
                        lsb: 11,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_imm4,
                        lsb: 16,
                        width: 4,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::SMULLT_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX(
            SMULLT_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX::from(bits),
        ))
    }
}
impl InsnOpcode for SMULLT_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SMULLT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "smullt",
        aliases: &[],
        opcode: 0x45007400,
        mask: 0xff20fc00,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::SMULLT_SVE_Zd_SVE_Zn_SVE_Zm_16(
            SMULLT_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for SMULLT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SPLICE_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "splice",
        aliases: &[],
        opcode: 0x52c8000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_5,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_5,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::SPLICE_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(
            SPLICE_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5::from(bits),
        ))
    }
}
impl InsnOpcode for SPLICE_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SPLICE_SVE_Zd_SVE_Pg3_SVE_ZnxN {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "splice",
        aliases: &[],
        opcode: 0x52d8000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ZnxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::SPLICE_SVE_Zd_SVE_Pg3_SVE_ZnxN(
            SPLICE_SVE_Zd_SVE_Pg3_SVE_ZnxN::from(bits),
        ))
    }
}
impl InsnOpcode for SPLICE_SVE_Zd_SVE_Pg3_SVE_ZnxN {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQABS_SVE_Zd_SVE_Pg3_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqabs",
        aliases: &[],
        opcode: 0x4408a000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M, InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::SQABS_SVE_Zd_SVE_Pg3_SVE_Zn(
            SQABS_SVE_Zd_SVE_Pg3_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for SQABS_SVE_Zd_SVE_Pg3_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQABS_Vd_Vn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqabs",
        aliases: &[],
        opcode: 0xe207800,
        mask: 0xbf3ffc00,
        class: InsnClass::ASIMDMISC,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDMISC(ASIMDMISC::SQABS_Vd_Vn(SQABS_Vd_Vn::from(bits)))
    }
}
impl InsnOpcode for SQABS_Vd_Vn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQABS_Sd_Sn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqabs",
        aliases: &[],
        opcode: 0x5e207800,
        mask: 0xff3ffc00,
        class: InsnClass::ASISDMISC,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMD_SCALAR_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDMISC(ASISDMISC::SQABS_Sd_Sn(SQABS_Sd_Sn::from(bits)))
    }
}
impl InsnOpcode for SQABS_Sd_Sn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQADD_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqadd",
        aliases: &[],
        opcode: 0x4201000,
        mask: 0xff20fc00,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::SQADD_SVE_Zd_SVE_Zn_SVE_Zm_16(
            SQADD_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for SQADD_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqadd",
        aliases: &[],
        opcode: 0x44188000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::SQADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(
            SQADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for SQADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQADD_SVE_Zd_SVE_Zd_SVE_AIMM {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqadd",
        aliases: &[],
        opcode: 0x2524c000,
        mask: 0xff3fc000,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_AIMM,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_imm9,
                    lsb: 5,
                    width: 9,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::SQADD_SVE_Zd_SVE_Zd_SVE_AIMM(
            SQADD_SVE_Zd_SVE_Zd_SVE_AIMM::from(bits),
        ))
    }
}
impl InsnOpcode for SQADD_SVE_Zd_SVE_Zd_SVE_AIMM {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQADD_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqadd",
        aliases: &[],
        opcode: 0xe200c00,
        mask: 0xbf20fc00,
        class: InsnClass::ASIMDSAME,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSAME(ASIMDSAME::SQADD_Vd_Vn_Vm(SQADD_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for SQADD_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQADD_Sd_Sn_Sm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqadd",
        aliases: &[],
        opcode: 0x5e200c00,
        mask: 0xff20fc00,
        class: InsnClass::ASISDSAME,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sm,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMD_SCALAR_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDSAME(ASISDSAME::SQADD_Sd_Sn_Sm(SQADD_Sd_Sn_Sm::from(bits)))
    }
}
impl InsnOpcode for SQADD_Sd_Sn_Sm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQCADD_SVE_Zd_SVE_Zd_SVE_Zn_SVE_IMM_ROT3 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqcadd",
        aliases: &[],
        opcode: 0x4501d800,
        mask: 0xff3ff800,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_IMM_ROT3,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_rot3,
                    lsb: 10,
                    width: 1,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::SQCADD_SVE_Zd_SVE_Zd_SVE_Zn_SVE_IMM_ROT3(
            SQCADD_SVE_Zd_SVE_Zd_SVE_Zn_SVE_IMM_ROT3::from(bits),
        ))
    }
}
impl InsnOpcode for SQCADD_SVE_Zd_SVE_Zd_SVE_Zn_SVE_IMM_ROT3 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQCVT_SVE_Zd_SME_Znx2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqcvt",
        aliases: &[],
        opcode: 0xc123e000,
        mask: 0xfffffc20,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn2,
                    lsb: 6,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::SQCVT_SVE_Zd_SME_Znx2(
            SQCVT_SVE_Zd_SME_Znx2::from(bits),
        ))
    }
}
impl InsnOpcode for SQCVT_SVE_Zd_SME_Znx2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQCVT_SVE_Zd_SME_Znx4 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqcvt",
        aliases: &[],
        opcode: 0xc133e000,
        mask: 0xff7ffc60,
        class: InsnClass::SME_SZ_23,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn4,
                    lsb: 7,
                    width: 3,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_SZ_23(SME_SZ_23::SQCVT_SVE_Zd_SME_Znx4(
            SQCVT_SVE_Zd_SME_Znx4::from(bits),
        ))
    }
}
impl InsnOpcode for SQCVT_SVE_Zd_SME_Znx4 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQCVTN_SVE_Zd_SME_Znx4 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqcvtn",
        aliases: &[],
        opcode: 0xc133e040,
        mask: 0xff7ffc60,
        class: InsnClass::SME_SZ_23,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn4,
                    lsb: 7,
                    width: 3,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_SZ_23(SME_SZ_23::SQCVTN_SVE_Zd_SME_Znx4(
            SQCVTN_SVE_Zd_SME_Znx4::from(bits),
        ))
    }
}
impl InsnOpcode for SQCVTN_SVE_Zd_SME_Znx4 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQCVTN_SVE_Zd_SME_Znx2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqcvtn",
        aliases: &[],
        opcode: 0x45314000,
        mask: 0xfffffc20,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn2,
                    lsb: 6,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::SQCVTN_SVE_Zd_SME_Znx2(
            SQCVTN_SVE_Zd_SME_Znx2::from(bits),
        ))
    }
}
impl InsnOpcode for SQCVTN_SVE_Zd_SME_Znx2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQCVTU_SVE_Zd_SME_Znx2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqcvtu",
        aliases: &[],
        opcode: 0xc163e000,
        mask: 0xfffffc20,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn2,
                    lsb: 6,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::SQCVTU_SVE_Zd_SME_Znx2(
            SQCVTU_SVE_Zd_SME_Znx2::from(bits),
        ))
    }
}
impl InsnOpcode for SQCVTU_SVE_Zd_SME_Znx2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQCVTU_SVE_Zd_SME_Znx4 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqcvtu",
        aliases: &[],
        opcode: 0xc173e000,
        mask: 0xff7ffc60,
        class: InsnClass::SME_SZ_23,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn4,
                    lsb: 7,
                    width: 3,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_SZ_23(SME_SZ_23::SQCVTU_SVE_Zd_SME_Znx4(
            SQCVTU_SVE_Zd_SME_Znx4::from(bits),
        ))
    }
}
impl InsnOpcode for SQCVTU_SVE_Zd_SME_Znx4 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQCVTUN_SVE_Zd_SME_Znx4 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqcvtun",
        aliases: &[],
        opcode: 0xc173e040,
        mask: 0xff7ffc60,
        class: InsnClass::SME_SZ_23,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn4,
                    lsb: 7,
                    width: 3,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_SZ_23(SME_SZ_23::SQCVTUN_SVE_Zd_SME_Znx4(
            SQCVTUN_SVE_Zd_SME_Znx4::from(bits),
        ))
    }
}
impl InsnOpcode for SQCVTUN_SVE_Zd_SME_Znx4 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQCVTUN_SVE_Zd_SME_Znx2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqcvtun",
        aliases: &[],
        opcode: 0x45315000,
        mask: 0xfffffc20,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn2,
                    lsb: 6,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::SQCVTUN_SVE_Zd_SME_Znx2(
            SQCVTUN_SVE_Zd_SME_Znx2::from(bits),
        ))
    }
}
impl InsnOpcode for SQCVTUN_SVE_Zd_SME_Znx2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQDECB_Rd_Rd_SVE_PATTERN_SCALED {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqdecb",
        aliases: &[],
        opcode: 0x420f800,
        mask: 0xfff0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_PATTERN_SCALED,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_pattern,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::SQDECB_Rd_Rd_SVE_PATTERN_SCALED(
            SQDECB_Rd_Rd_SVE_PATTERN_SCALED::from(bits),
        ))
    }
}
impl InsnOpcode for SQDECB_Rd_Rd_SVE_PATTERN_SCALED {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQDECB_Rd_SVE_PATTERN_SCALED {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqdecb",
        aliases: &[],
        opcode: 0x430f800,
        mask: 0xfff0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_PATTERN_SCALED,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_pattern,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::SQDECB_Rd_SVE_PATTERN_SCALED(
            SQDECB_Rd_SVE_PATTERN_SCALED::from(bits),
        ))
    }
}
impl InsnOpcode for SQDECB_Rd_SVE_PATTERN_SCALED {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQDECD_SVE_Zd_SVE_PATTERN_SCALED {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqdecd",
        aliases: &[],
        opcode: 0x4e0c800,
        mask: 0xfff0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_PATTERN_SCALED,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_pattern,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::SQDECD_SVE_Zd_SVE_PATTERN_SCALED(
            SQDECD_SVE_Zd_SVE_PATTERN_SCALED::from(bits),
        ))
    }
}
impl InsnOpcode for SQDECD_SVE_Zd_SVE_PATTERN_SCALED {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQDECD_Rd_Rd_SVE_PATTERN_SCALED {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqdecd",
        aliases: &[],
        opcode: 0x4e0f800,
        mask: 0xfff0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_PATTERN_SCALED,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_pattern,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::SQDECD_Rd_Rd_SVE_PATTERN_SCALED(
            SQDECD_Rd_Rd_SVE_PATTERN_SCALED::from(bits),
        ))
    }
}
impl InsnOpcode for SQDECD_Rd_Rd_SVE_PATTERN_SCALED {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQDECD_Rd_SVE_PATTERN_SCALED {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqdecd",
        aliases: &[],
        opcode: 0x4f0f800,
        mask: 0xfff0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_PATTERN_SCALED,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_pattern,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::SQDECD_Rd_SVE_PATTERN_SCALED(
            SQDECD_Rd_SVE_PATTERN_SCALED::from(bits),
        ))
    }
}
impl InsnOpcode for SQDECD_Rd_SVE_PATTERN_SCALED {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQDECH_SVE_Zd_SVE_PATTERN_SCALED {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqdech",
        aliases: &[],
        opcode: 0x460c800,
        mask: 0xfff0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_PATTERN_SCALED,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_pattern,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::SQDECH_SVE_Zd_SVE_PATTERN_SCALED(
            SQDECH_SVE_Zd_SVE_PATTERN_SCALED::from(bits),
        ))
    }
}
impl InsnOpcode for SQDECH_SVE_Zd_SVE_PATTERN_SCALED {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQDECH_Rd_Rd_SVE_PATTERN_SCALED {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqdech",
        aliases: &[],
        opcode: 0x460f800,
        mask: 0xfff0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_PATTERN_SCALED,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_pattern,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::SQDECH_Rd_Rd_SVE_PATTERN_SCALED(
            SQDECH_Rd_Rd_SVE_PATTERN_SCALED::from(bits),
        ))
    }
}
impl InsnOpcode for SQDECH_Rd_Rd_SVE_PATTERN_SCALED {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQDECH_Rd_SVE_PATTERN_SCALED {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqdech",
        aliases: &[],
        opcode: 0x470f800,
        mask: 0xfff0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_PATTERN_SCALED,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_pattern,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::SQDECH_Rd_SVE_PATTERN_SCALED(
            SQDECH_Rd_SVE_PATTERN_SCALED::from(bits),
        ))
    }
}
impl InsnOpcode for SQDECH_Rd_SVE_PATTERN_SCALED {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQDECP_SVE_Zd_SVE_Pg4_5 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqdecp",
        aliases: &[],
        opcode: 0x252a8000,
        mask: 0xff3ffe00,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg4_5,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg4_5,
                    lsb: 5,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::SQDECP_SVE_Zd_SVE_Pg4_5(
            SQDECP_SVE_Zd_SVE_Pg4_5::from(bits),
        ))
    }
}
impl InsnOpcode for SQDECP_SVE_Zd_SVE_Pg4_5 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQDECP_Rd_SVE_Pg4_5_Rd {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqdecp",
        aliases: &[],
        opcode: 0x252a8800,
        mask: 0xff3ffe00,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg4_5,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg4_5,
                    lsb: 5,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::SQDECP_Rd_SVE_Pg4_5_Rd(
            SQDECP_Rd_SVE_Pg4_5_Rd::from(bits),
        ))
    }
}
impl InsnOpcode for SQDECP_Rd_SVE_Pg4_5_Rd {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQDECP_Rd_SVE_Pg4_5 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqdecp",
        aliases: &[],
        opcode: 0x252a8c00,
        mask: 0xff3ffe00,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg4_5,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg4_5,
                    lsb: 5,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::SQDECP_Rd_SVE_Pg4_5(
            SQDECP_Rd_SVE_Pg4_5::from(bits),
        ))
    }
}
impl InsnOpcode for SQDECP_Rd_SVE_Pg4_5 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQDECW_SVE_Zd_SVE_PATTERN_SCALED {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqdecw",
        aliases: &[],
        opcode: 0x4a0c800,
        mask: 0xfff0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_PATTERN_SCALED,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_pattern,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::SQDECW_SVE_Zd_SVE_PATTERN_SCALED(
            SQDECW_SVE_Zd_SVE_PATTERN_SCALED::from(bits),
        ))
    }
}
impl InsnOpcode for SQDECW_SVE_Zd_SVE_PATTERN_SCALED {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQDECW_Rd_Rd_SVE_PATTERN_SCALED {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqdecw",
        aliases: &[],
        opcode: 0x4a0f800,
        mask: 0xfff0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_PATTERN_SCALED,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_pattern,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::SQDECW_Rd_Rd_SVE_PATTERN_SCALED(
            SQDECW_Rd_Rd_SVE_PATTERN_SCALED::from(bits),
        ))
    }
}
impl InsnOpcode for SQDECW_Rd_Rd_SVE_PATTERN_SCALED {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQDECW_Rd_SVE_PATTERN_SCALED {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqdecw",
        aliases: &[],
        opcode: 0x4b0f800,
        mask: 0xfff0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_PATTERN_SCALED,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_pattern,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::SQDECW_Rd_SVE_PATTERN_SCALED(
            SQDECW_Rd_SVE_PATTERN_SCALED::from(bits),
        ))
    }
}
impl InsnOpcode for SQDECW_Rd_SVE_PATTERN_SCALED {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQDMLAL_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqdmlal",
        aliases: &[],
        opcode: 0xe209000,
        mask: 0xff20fc00,
        class: InsnClass::ASIMDDIFF,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4S, InsnOperandQualifier::V_2D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_2S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_2S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDDIFF(ASIMDDIFF::SQDMLAL_Vd_Vn_Vm(SQDMLAL_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for SQDMLAL_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQDMLAL_Sd_Sn_Sm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqdmlal",
        aliases: &[],
        opcode: 0x5e209000,
        mask: 0xff20fc00,
        class: InsnClass::ASISDDIFF,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sm,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMD_SCALAR_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDDIFF(ASISDDIFF::SQDMLAL_Sd_Sn_Sm(SQDMLAL_Sd_Sn_Sm::from(bits)))
    }
}
impl InsnOpcode for SQDMLAL_Sd_Sn_Sm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQDMLAL_Vd_Vn_Em16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqdmlal",
        aliases: &[],
        opcode: 0xf003000,
        mask: 0xff00f400,
        class: InsnClass::ASIMDELEM,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4S, InsnOperandQualifier::V_2D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_2S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Em16,
                class: InsnOperandClass::SIMD_ELEMENT,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDELEM(ASIMDELEM::SQDMLAL_Vd_Vn_Em16(SQDMLAL_Vd_Vn_Em16::from(
            bits,
        )))
    }
}
impl InsnOpcode for SQDMLAL_Vd_Vn_Em16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQDMLAL_Sd_Sn_Em16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqdmlal",
        aliases: &[],
        opcode: 0x5f003000,
        mask: 0xff00f400,
        class: InsnClass::ASISDELEM,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Em16,
                class: InsnOperandClass::SIMD_ELEMENT,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMD_SCALAR_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDELEM(ASISDELEM::SQDMLAL_Sd_Sn_Em16(SQDMLAL_Sd_Sn_Em16::from(
            bits,
        )))
    }
}
impl InsnOpcode for SQDMLAL_Sd_Sn_Em16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQDMLAL2_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqdmlal2",
        aliases: &[],
        opcode: 0x4e209000,
        mask: 0xff20fc00,
        class: InsnClass::ASIMDDIFF,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4S, InsnOperandQualifier::V_2D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8H, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8H, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDDIFF(ASIMDDIFF::SQDMLAL2_Vd_Vn_Vm(SQDMLAL2_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for SQDMLAL2_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQDMLAL2_Vd_Vn_Em16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqdmlal2",
        aliases: &[],
        opcode: 0x4f003000,
        mask: 0xff00f400,
        class: InsnClass::ASIMDELEM,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4S, InsnOperandQualifier::V_2D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8H, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Em16,
                class: InsnOperandClass::SIMD_ELEMENT,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDELEM(ASIMDELEM::SQDMLAL2_Vd_Vn_Em16(SQDMLAL2_Vd_Vn_Em16::from(
            bits,
        )))
    }
}
impl InsnOpcode for SQDMLAL2_Vd_Vn_Em16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQDMLALB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqdmlalb",
        aliases: &[],
        opcode: 0x44a02000,
        mask: 0xffe0f400,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm3_11_INDEX,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_i3h2,
                        lsb: 19,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_i3l,
                        lsb: 11,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_imm3,
                        lsb: 16,
                        width: 3,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::SQDMLALB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX(
            SQDMLALB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX::from(bits),
        ))
    }
}
impl InsnOpcode for SQDMLALB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQDMLALB_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqdmlalb",
        aliases: &[],
        opcode: 0x44e02000,
        mask: 0xffe0f400,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm4_11_INDEX,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_i2h,
                        lsb: 20,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_i3l,
                        lsb: 11,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_imm4,
                        lsb: 16,
                        width: 4,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::SQDMLALB_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX(
            SQDMLALB_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX::from(bits),
        ))
    }
}
impl InsnOpcode for SQDMLALB_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQDMLALB_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqdmlalb",
        aliases: &[],
        opcode: 0x44006000,
        mask: 0xff20fc00,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::SQDMLALB_SVE_Zd_SVE_Zn_SVE_Zm_16(
            SQDMLALB_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for SQDMLALB_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQDMLALBT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqdmlalbt",
        aliases: &[],
        opcode: 0x44000800,
        mask: 0xff20fc00,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::SQDMLALBT_SVE_Zd_SVE_Zn_SVE_Zm_16(
            SQDMLALBT_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for SQDMLALBT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQDMLALT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqdmlalt",
        aliases: &[],
        opcode: 0x44a02400,
        mask: 0xffe0f400,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm3_11_INDEX,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_i3h2,
                        lsb: 19,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_i3l,
                        lsb: 11,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_imm3,
                        lsb: 16,
                        width: 3,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::SQDMLALT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX(
            SQDMLALT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX::from(bits),
        ))
    }
}
impl InsnOpcode for SQDMLALT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQDMLALT_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqdmlalt",
        aliases: &[],
        opcode: 0x44e02400,
        mask: 0xffe0f400,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm4_11_INDEX,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_i2h,
                        lsb: 20,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_i3l,
                        lsb: 11,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_imm4,
                        lsb: 16,
                        width: 4,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::SQDMLALT_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX(
            SQDMLALT_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX::from(bits),
        ))
    }
}
impl InsnOpcode for SQDMLALT_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQDMLALT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqdmlalt",
        aliases: &[],
        opcode: 0x44006400,
        mask: 0xff20fc00,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::SQDMLALT_SVE_Zd_SVE_Zn_SVE_Zm_16(
            SQDMLALT_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for SQDMLALT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQDMLSL_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqdmlsl",
        aliases: &[],
        opcode: 0xe20b000,
        mask: 0xff20fc00,
        class: InsnClass::ASIMDDIFF,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4S, InsnOperandQualifier::V_2D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_2S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_2S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDDIFF(ASIMDDIFF::SQDMLSL_Vd_Vn_Vm(SQDMLSL_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for SQDMLSL_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQDMLSL_Sd_Sn_Sm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqdmlsl",
        aliases: &[],
        opcode: 0x5e20b000,
        mask: 0xff20fc00,
        class: InsnClass::ASISDDIFF,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sm,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMD_SCALAR_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDDIFF(ASISDDIFF::SQDMLSL_Sd_Sn_Sm(SQDMLSL_Sd_Sn_Sm::from(bits)))
    }
}
impl InsnOpcode for SQDMLSL_Sd_Sn_Sm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQDMLSL_Vd_Vn_Em16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqdmlsl",
        aliases: &[],
        opcode: 0xf007000,
        mask: 0xff00f400,
        class: InsnClass::ASIMDELEM,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4S, InsnOperandQualifier::V_2D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_2S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Em16,
                class: InsnOperandClass::SIMD_ELEMENT,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDELEM(ASIMDELEM::SQDMLSL_Vd_Vn_Em16(SQDMLSL_Vd_Vn_Em16::from(
            bits,
        )))
    }
}
impl InsnOpcode for SQDMLSL_Vd_Vn_Em16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQDMLSL_Sd_Sn_Em16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqdmlsl",
        aliases: &[],
        opcode: 0x5f007000,
        mask: 0xff00f400,
        class: InsnClass::ASISDELEM,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Em16,
                class: InsnOperandClass::SIMD_ELEMENT,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMD_SCALAR_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDELEM(ASISDELEM::SQDMLSL_Sd_Sn_Em16(SQDMLSL_Sd_Sn_Em16::from(
            bits,
        )))
    }
}
impl InsnOpcode for SQDMLSL_Sd_Sn_Em16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQDMLSL2_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqdmlsl2",
        aliases: &[],
        opcode: 0x4e20b000,
        mask: 0xff20fc00,
        class: InsnClass::ASIMDDIFF,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4S, InsnOperandQualifier::V_2D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8H, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8H, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDDIFF(ASIMDDIFF::SQDMLSL2_Vd_Vn_Vm(SQDMLSL2_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for SQDMLSL2_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQDMLSL2_Vd_Vn_Em16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqdmlsl2",
        aliases: &[],
        opcode: 0x4f007000,
        mask: 0xff00f400,
        class: InsnClass::ASIMDELEM,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4S, InsnOperandQualifier::V_2D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8H, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Em16,
                class: InsnOperandClass::SIMD_ELEMENT,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDELEM(ASIMDELEM::SQDMLSL2_Vd_Vn_Em16(SQDMLSL2_Vd_Vn_Em16::from(
            bits,
        )))
    }
}
impl InsnOpcode for SQDMLSL2_Vd_Vn_Em16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQDMLSLB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqdmlslb",
        aliases: &[],
        opcode: 0x44a03000,
        mask: 0xffe0f400,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm3_11_INDEX,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_i3h2,
                        lsb: 19,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_i3l,
                        lsb: 11,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_imm3,
                        lsb: 16,
                        width: 3,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::SQDMLSLB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX(
            SQDMLSLB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX::from(bits),
        ))
    }
}
impl InsnOpcode for SQDMLSLB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQDMLSLB_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqdmlslb",
        aliases: &[],
        opcode: 0x44e03000,
        mask: 0xffe0f400,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm4_11_INDEX,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_i2h,
                        lsb: 20,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_i3l,
                        lsb: 11,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_imm4,
                        lsb: 16,
                        width: 4,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::SQDMLSLB_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX(
            SQDMLSLB_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX::from(bits),
        ))
    }
}
impl InsnOpcode for SQDMLSLB_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQDMLSLB_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqdmlslb",
        aliases: &[],
        opcode: 0x44006800,
        mask: 0xff20fc00,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::SQDMLSLB_SVE_Zd_SVE_Zn_SVE_Zm_16(
            SQDMLSLB_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for SQDMLSLB_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQDMLSLBT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqdmlslbt",
        aliases: &[],
        opcode: 0x44000c00,
        mask: 0xff20fc00,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::SQDMLSLBT_SVE_Zd_SVE_Zn_SVE_Zm_16(
            SQDMLSLBT_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for SQDMLSLBT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQDMLSLT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqdmlslt",
        aliases: &[],
        opcode: 0x44a03400,
        mask: 0xffe0f400,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm3_11_INDEX,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_i3h2,
                        lsb: 19,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_i3l,
                        lsb: 11,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_imm3,
                        lsb: 16,
                        width: 3,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::SQDMLSLT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX(
            SQDMLSLT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX::from(bits),
        ))
    }
}
impl InsnOpcode for SQDMLSLT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQDMLSLT_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqdmlslt",
        aliases: &[],
        opcode: 0x44e03400,
        mask: 0xffe0f400,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm4_11_INDEX,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_i2h,
                        lsb: 20,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_i3l,
                        lsb: 11,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_imm4,
                        lsb: 16,
                        width: 4,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::SQDMLSLT_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX(
            SQDMLSLT_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX::from(bits),
        ))
    }
}
impl InsnOpcode for SQDMLSLT_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQDMLSLT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqdmlslt",
        aliases: &[],
        opcode: 0x44006c00,
        mask: 0xff20fc00,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::SQDMLSLT_SVE_Zd_SVE_Zn_SVE_Zm_16(
            SQDMLSLT_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for SQDMLSLT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQDMULH_SME_Zdnx2_SME_Zdnx2_SME_Zm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqdmulh",
        aliases: &[],
        opcode: 0xc120a400,
        mask: 0xff30ffe1,
        class: InsnClass::SME_SIZE_22,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn2,
                    lsb: 1,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn2,
                    lsb: 1,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm,
                    lsb: 16,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_SIZE_22(SME_SIZE_22::SQDMULH_SME_Zdnx2_SME_Zdnx2_SME_Zm(
            SQDMULH_SME_Zdnx2_SME_Zdnx2_SME_Zm::from(bits),
        ))
    }
}
impl InsnOpcode for SQDMULH_SME_Zdnx2_SME_Zdnx2_SME_Zm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQDMULH_SME_Zdnx2_SME_Zdnx2_SME_Zmx2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqdmulh",
        aliases: &[],
        opcode: 0xc120b400,
        mask: 0xff21ffe1,
        class: InsnClass::SME_SIZE_22,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn2,
                    lsb: 1,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn2,
                    lsb: 1,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zmx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm2,
                    lsb: 17,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_SIZE_22(SME_SIZE_22::SQDMULH_SME_Zdnx2_SME_Zdnx2_SME_Zmx2(
            SQDMULH_SME_Zdnx2_SME_Zdnx2_SME_Zmx2::from(bits),
        ))
    }
}
impl InsnOpcode for SQDMULH_SME_Zdnx2_SME_Zdnx2_SME_Zmx2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQDMULH_SME_Zdnx4_SME_Zdnx4_SME_Zm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqdmulh",
        aliases: &[],
        opcode: 0xc120ac00,
        mask: 0xff30ffe3,
        class: InsnClass::SME_SIZE_22,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn4,
                    lsb: 2,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn4,
                    lsb: 2,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm,
                    lsb: 16,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_SIZE_22(SME_SIZE_22::SQDMULH_SME_Zdnx4_SME_Zdnx4_SME_Zm(
            SQDMULH_SME_Zdnx4_SME_Zdnx4_SME_Zm::from(bits),
        ))
    }
}
impl InsnOpcode for SQDMULH_SME_Zdnx4_SME_Zdnx4_SME_Zm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQDMULH_SME_Zdnx4_SME_Zdnx4_SME_Zmx4 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqdmulh",
        aliases: &[],
        opcode: 0xc120bc00,
        mask: 0xff23ffe3,
        class: InsnClass::SME_SIZE_22,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn4,
                    lsb: 2,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn4,
                    lsb: 2,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zmx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm4,
                    lsb: 18,
                    width: 3,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_SIZE_22(SME_SIZE_22::SQDMULH_SME_Zdnx4_SME_Zdnx4_SME_Zmx4(
            SQDMULH_SME_Zdnx4_SME_Zdnx4_SME_Zmx4::from(bits),
        ))
    }
}
impl InsnOpcode for SQDMULH_SME_Zdnx4_SME_Zdnx4_SME_Zmx4 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQDMULH_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqdmulh",
        aliases: &[],
        opcode: 0x4207000,
        mask: 0xff20fc00,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::SQDMULH_SVE_Zd_SVE_Zn_SVE_Zm_16(
            SQDMULH_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for SQDMULH_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQDMULH_SVE_Zd_SVE_Zn_SVE_Zm3_22_INDEX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqdmulh",
        aliases: &[],
        opcode: 0x4420f000,
        mask: 0xffa0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm3_22_INDEX,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_i3h,
                        lsb: 22,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zm_16,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::SQDMULH_SVE_Zd_SVE_Zn_SVE_Zm3_22_INDEX(
            SQDMULH_SVE_Zd_SVE_Zn_SVE_Zm3_22_INDEX::from(bits),
        ))
    }
}
impl InsnOpcode for SQDMULH_SVE_Zd_SVE_Zn_SVE_Zm3_22_INDEX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQDMULH_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqdmulh",
        aliases: &[],
        opcode: 0x44a0f000,
        mask: 0xffe0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm3_INDEX,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::SQDMULH_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX(
            SQDMULH_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX::from(bits),
        ))
    }
}
impl InsnOpcode for SQDMULH_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQDMULH_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqdmulh",
        aliases: &[],
        opcode: 0x44e0f000,
        mask: 0xffe0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm4_INDEX,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::SQDMULH_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX(
            SQDMULH_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX::from(bits),
        ))
    }
}
impl InsnOpcode for SQDMULH_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQDMULH_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqdmulh",
        aliases: &[],
        opcode: 0xe20b400,
        mask: 0xbf20fc00,
        class: InsnClass::ASIMDSAME,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSAME(ASIMDSAME::SQDMULH_Vd_Vn_Vm(SQDMULH_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for SQDMULH_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQDMULH_Sd_Sn_Sm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqdmulh",
        aliases: &[],
        opcode: 0x5e20b400,
        mask: 0xff20fc00,
        class: InsnClass::ASISDSAME,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sm,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMD_SCALAR_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDSAME(ASISDSAME::SQDMULH_Sd_Sn_Sm(SQDMULH_Sd_Sn_Sm::from(bits)))
    }
}
impl InsnOpcode for SQDMULH_Sd_Sn_Sm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQDMULH_Vd_Vn_Em16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqdmulh",
        aliases: &[],
        opcode: 0xf00c000,
        mask: 0xbf00f400,
        class: InsnClass::ASIMDELEM,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Em16,
                class: InsnOperandClass::SIMD_ELEMENT,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDELEM(ASIMDELEM::SQDMULH_Vd_Vn_Em16(SQDMULH_Vd_Vn_Em16::from(
            bits,
        )))
    }
}
impl InsnOpcode for SQDMULH_Vd_Vn_Em16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQDMULH_Sd_Sn_Em16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqdmulh",
        aliases: &[],
        opcode: 0x5f00c000,
        mask: 0xff00f400,
        class: InsnClass::ASISDELEM,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Em16,
                class: InsnOperandClass::SIMD_ELEMENT,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMD_SCALAR_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDELEM(ASISDELEM::SQDMULH_Sd_Sn_Em16(SQDMULH_Sd_Sn_Em16::from(
            bits,
        )))
    }
}
impl InsnOpcode for SQDMULH_Sd_Sn_Em16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQDMULL_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqdmull",
        aliases: &[],
        opcode: 0xe20d000,
        mask: 0xff20fc00,
        class: InsnClass::ASIMDDIFF,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4S, InsnOperandQualifier::V_2D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_2S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_2S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDDIFF(ASIMDDIFF::SQDMULL_Vd_Vn_Vm(SQDMULL_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for SQDMULL_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQDMULL_Sd_Sn_Sm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqdmull",
        aliases: &[],
        opcode: 0x5e20d000,
        mask: 0xff20fc00,
        class: InsnClass::ASISDDIFF,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sm,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMD_SCALAR_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDDIFF(ASISDDIFF::SQDMULL_Sd_Sn_Sm(SQDMULL_Sd_Sn_Sm::from(bits)))
    }
}
impl InsnOpcode for SQDMULL_Sd_Sn_Sm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQDMULL_Vd_Vn_Em16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqdmull",
        aliases: &[],
        opcode: 0xf00b000,
        mask: 0xff00f400,
        class: InsnClass::ASIMDELEM,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4S, InsnOperandQualifier::V_2D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_2S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Em16,
                class: InsnOperandClass::SIMD_ELEMENT,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDELEM(ASIMDELEM::SQDMULL_Vd_Vn_Em16(SQDMULL_Vd_Vn_Em16::from(
            bits,
        )))
    }
}
impl InsnOpcode for SQDMULL_Vd_Vn_Em16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQDMULL_Sd_Sn_Em16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqdmull",
        aliases: &[],
        opcode: 0x5f00b000,
        mask: 0xff00f400,
        class: InsnClass::ASISDELEM,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Em16,
                class: InsnOperandClass::SIMD_ELEMENT,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMD_SCALAR_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDELEM(ASISDELEM::SQDMULL_Sd_Sn_Em16(SQDMULL_Sd_Sn_Em16::from(
            bits,
        )))
    }
}
impl InsnOpcode for SQDMULL_Sd_Sn_Em16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQDMULL2_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqdmull2",
        aliases: &[],
        opcode: 0x4e20d000,
        mask: 0xff20fc00,
        class: InsnClass::ASIMDDIFF,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4S, InsnOperandQualifier::V_2D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8H, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8H, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDDIFF(ASIMDDIFF::SQDMULL2_Vd_Vn_Vm(SQDMULL2_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for SQDMULL2_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQDMULL2_Vd_Vn_Em16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqdmull2",
        aliases: &[],
        opcode: 0x4f00b000,
        mask: 0xff00f400,
        class: InsnClass::ASIMDELEM,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4S, InsnOperandQualifier::V_2D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8H, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Em16,
                class: InsnOperandClass::SIMD_ELEMENT,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDELEM(ASIMDELEM::SQDMULL2_Vd_Vn_Em16(SQDMULL2_Vd_Vn_Em16::from(
            bits,
        )))
    }
}
impl InsnOpcode for SQDMULL2_Vd_Vn_Em16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQDMULLB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqdmullb",
        aliases: &[],
        opcode: 0x44a0e000,
        mask: 0xffe0f400,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm3_11_INDEX,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_i3h2,
                        lsb: 19,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_i3l,
                        lsb: 11,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_imm3,
                        lsb: 16,
                        width: 3,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::SQDMULLB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX(
            SQDMULLB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX::from(bits),
        ))
    }
}
impl InsnOpcode for SQDMULLB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQDMULLB_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqdmullb",
        aliases: &[],
        opcode: 0x44e0e000,
        mask: 0xffe0f400,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm4_11_INDEX,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_i2h,
                        lsb: 20,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_i3l,
                        lsb: 11,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_imm4,
                        lsb: 16,
                        width: 4,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::SQDMULLB_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX(
            SQDMULLB_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX::from(bits),
        ))
    }
}
impl InsnOpcode for SQDMULLB_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQDMULLB_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqdmullb",
        aliases: &[],
        opcode: 0x45006000,
        mask: 0xff20fc00,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::SQDMULLB_SVE_Zd_SVE_Zn_SVE_Zm_16(
            SQDMULLB_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for SQDMULLB_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQDMULLT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqdmullt",
        aliases: &[],
        opcode: 0x44a0e400,
        mask: 0xffe0f400,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm3_11_INDEX,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_i3h2,
                        lsb: 19,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_i3l,
                        lsb: 11,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_imm3,
                        lsb: 16,
                        width: 3,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::SQDMULLT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX(
            SQDMULLT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX::from(bits),
        ))
    }
}
impl InsnOpcode for SQDMULLT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQDMULLT_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqdmullt",
        aliases: &[],
        opcode: 0x44e0e400,
        mask: 0xffe0f400,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm4_11_INDEX,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_i2h,
                        lsb: 20,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_i3l,
                        lsb: 11,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_imm4,
                        lsb: 16,
                        width: 4,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::SQDMULLT_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX(
            SQDMULLT_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX::from(bits),
        ))
    }
}
impl InsnOpcode for SQDMULLT_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQDMULLT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqdmullt",
        aliases: &[],
        opcode: 0x45006400,
        mask: 0xff20fc00,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::SQDMULLT_SVE_Zd_SVE_Zn_SVE_Zm_16(
            SQDMULLT_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for SQDMULLT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQINCB_Rd_Rd_SVE_PATTERN_SCALED {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqincb",
        aliases: &[],
        opcode: 0x420f000,
        mask: 0xfff0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_PATTERN_SCALED,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_pattern,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::SQINCB_Rd_Rd_SVE_PATTERN_SCALED(
            SQINCB_Rd_Rd_SVE_PATTERN_SCALED::from(bits),
        ))
    }
}
impl InsnOpcode for SQINCB_Rd_Rd_SVE_PATTERN_SCALED {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQINCB_Rd_SVE_PATTERN_SCALED {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqincb",
        aliases: &[],
        opcode: 0x430f000,
        mask: 0xfff0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_PATTERN_SCALED,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_pattern,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::SQINCB_Rd_SVE_PATTERN_SCALED(
            SQINCB_Rd_SVE_PATTERN_SCALED::from(bits),
        ))
    }
}
impl InsnOpcode for SQINCB_Rd_SVE_PATTERN_SCALED {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQINCD_SVE_Zd_SVE_PATTERN_SCALED {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqincd",
        aliases: &[],
        opcode: 0x4e0c000,
        mask: 0xfff0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_PATTERN_SCALED,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_pattern,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::SQINCD_SVE_Zd_SVE_PATTERN_SCALED(
            SQINCD_SVE_Zd_SVE_PATTERN_SCALED::from(bits),
        ))
    }
}
impl InsnOpcode for SQINCD_SVE_Zd_SVE_PATTERN_SCALED {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQINCD_Rd_Rd_SVE_PATTERN_SCALED {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqincd",
        aliases: &[],
        opcode: 0x4e0f000,
        mask: 0xfff0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_PATTERN_SCALED,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_pattern,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::SQINCD_Rd_Rd_SVE_PATTERN_SCALED(
            SQINCD_Rd_Rd_SVE_PATTERN_SCALED::from(bits),
        ))
    }
}
impl InsnOpcode for SQINCD_Rd_Rd_SVE_PATTERN_SCALED {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQINCD_Rd_SVE_PATTERN_SCALED {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqincd",
        aliases: &[],
        opcode: 0x4f0f000,
        mask: 0xfff0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_PATTERN_SCALED,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_pattern,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::SQINCD_Rd_SVE_PATTERN_SCALED(
            SQINCD_Rd_SVE_PATTERN_SCALED::from(bits),
        ))
    }
}
impl InsnOpcode for SQINCD_Rd_SVE_PATTERN_SCALED {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQINCH_SVE_Zd_SVE_PATTERN_SCALED {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqinch",
        aliases: &[],
        opcode: 0x460c000,
        mask: 0xfff0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_PATTERN_SCALED,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_pattern,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::SQINCH_SVE_Zd_SVE_PATTERN_SCALED(
            SQINCH_SVE_Zd_SVE_PATTERN_SCALED::from(bits),
        ))
    }
}
impl InsnOpcode for SQINCH_SVE_Zd_SVE_PATTERN_SCALED {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQINCH_Rd_Rd_SVE_PATTERN_SCALED {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqinch",
        aliases: &[],
        opcode: 0x460f000,
        mask: 0xfff0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_PATTERN_SCALED,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_pattern,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::SQINCH_Rd_Rd_SVE_PATTERN_SCALED(
            SQINCH_Rd_Rd_SVE_PATTERN_SCALED::from(bits),
        ))
    }
}
impl InsnOpcode for SQINCH_Rd_Rd_SVE_PATTERN_SCALED {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQINCH_Rd_SVE_PATTERN_SCALED {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqinch",
        aliases: &[],
        opcode: 0x470f000,
        mask: 0xfff0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_PATTERN_SCALED,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_pattern,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::SQINCH_Rd_SVE_PATTERN_SCALED(
            SQINCH_Rd_SVE_PATTERN_SCALED::from(bits),
        ))
    }
}
impl InsnOpcode for SQINCH_Rd_SVE_PATTERN_SCALED {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQINCP_SVE_Zd_SVE_Pg4_5 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqincp",
        aliases: &[],
        opcode: 0x25288000,
        mask: 0xff3ffe00,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg4_5,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg4_5,
                    lsb: 5,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::SQINCP_SVE_Zd_SVE_Pg4_5(
            SQINCP_SVE_Zd_SVE_Pg4_5::from(bits),
        ))
    }
}
impl InsnOpcode for SQINCP_SVE_Zd_SVE_Pg4_5 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQINCP_Rd_SVE_Pg4_5_Rd {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqincp",
        aliases: &[],
        opcode: 0x25288800,
        mask: 0xff3ffe00,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg4_5,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg4_5,
                    lsb: 5,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::SQINCP_Rd_SVE_Pg4_5_Rd(
            SQINCP_Rd_SVE_Pg4_5_Rd::from(bits),
        ))
    }
}
impl InsnOpcode for SQINCP_Rd_SVE_Pg4_5_Rd {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQINCP_Rd_SVE_Pg4_5 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqincp",
        aliases: &[],
        opcode: 0x25288c00,
        mask: 0xff3ffe00,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg4_5,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg4_5,
                    lsb: 5,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::SQINCP_Rd_SVE_Pg4_5(
            SQINCP_Rd_SVE_Pg4_5::from(bits),
        ))
    }
}
impl InsnOpcode for SQINCP_Rd_SVE_Pg4_5 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQINCW_SVE_Zd_SVE_PATTERN_SCALED {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqincw",
        aliases: &[],
        opcode: 0x4a0c000,
        mask: 0xfff0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_PATTERN_SCALED,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_pattern,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::SQINCW_SVE_Zd_SVE_PATTERN_SCALED(
            SQINCW_SVE_Zd_SVE_PATTERN_SCALED::from(bits),
        ))
    }
}
impl InsnOpcode for SQINCW_SVE_Zd_SVE_PATTERN_SCALED {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQINCW_Rd_Rd_SVE_PATTERN_SCALED {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqincw",
        aliases: &[],
        opcode: 0x4a0f000,
        mask: 0xfff0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_PATTERN_SCALED,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_pattern,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::SQINCW_Rd_Rd_SVE_PATTERN_SCALED(
            SQINCW_Rd_Rd_SVE_PATTERN_SCALED::from(bits),
        ))
    }
}
impl InsnOpcode for SQINCW_Rd_Rd_SVE_PATTERN_SCALED {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQINCW_Rd_SVE_PATTERN_SCALED {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqincw",
        aliases: &[],
        opcode: 0x4b0f000,
        mask: 0xfff0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_PATTERN_SCALED,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_pattern,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::SQINCW_Rd_SVE_PATTERN_SCALED(
            SQINCW_Rd_SVE_PATTERN_SCALED::from(bits),
        ))
    }
}
impl InsnOpcode for SQINCW_Rd_SVE_PATTERN_SCALED {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQNEG_SVE_Zd_SVE_Pg3_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqneg",
        aliases: &[],
        opcode: 0x4409a000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M, InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::SQNEG_SVE_Zd_SVE_Pg3_SVE_Zn(
            SQNEG_SVE_Zd_SVE_Pg3_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for SQNEG_SVE_Zd_SVE_Pg3_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQNEG_Vd_Vn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqneg",
        aliases: &[],
        opcode: 0x2e207800,
        mask: 0xbf3ffc00,
        class: InsnClass::ASIMDMISC,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDMISC(ASIMDMISC::SQNEG_Vd_Vn(SQNEG_Vd_Vn::from(bits)))
    }
}
impl InsnOpcode for SQNEG_Vd_Vn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQNEG_Sd_Sn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqneg",
        aliases: &[],
        opcode: 0x7e207800,
        mask: 0xff3ffc00,
        class: InsnClass::ASISDMISC,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMD_SCALAR_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDMISC(ASISDMISC::SQNEG_Sd_Sn(SQNEG_Sd_Sn::from(bits)))
    }
}
impl InsnOpcode for SQNEG_Sd_Sn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQRDCMLAH_SVE_Zd_SVE_Zn_SVE_Zm_16_SVE_IMM_ROT2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqrdcmlah",
        aliases: &[],
        opcode: 0x44003000,
        mask: 0xff20f000,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_IMM_ROT2,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_rot2,
                    lsb: 10,
                    width: 2,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(
            SVE_SIZE_BHSD::SQRDCMLAH_SVE_Zd_SVE_Zn_SVE_Zm_16_SVE_IMM_ROT2(
                SQRDCMLAH_SVE_Zd_SVE_Zn_SVE_Zm_16_SVE_IMM_ROT2::from(bits),
            ),
        )
    }
}
impl InsnOpcode for SQRDCMLAH_SVE_Zd_SVE_Zn_SVE_Zm_16_SVE_IMM_ROT2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQRDCMLAH_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX_SVE_IMM_ROT2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqrdcmlah",
        aliases: &[],
        opcode: 0x44a07000,
        mask: 0xffe0f000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm3_INDEX,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_IMM_ROT2,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_rot2,
                    lsb: 10,
                    width: 2,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(
            SVE_MISC::SQRDCMLAH_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX_SVE_IMM_ROT2(
                SQRDCMLAH_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX_SVE_IMM_ROT2::from(bits),
            ),
        )
    }
}
impl InsnOpcode for SQRDCMLAH_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX_SVE_IMM_ROT2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQRDCMLAH_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX_SVE_IMM_ROT2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqrdcmlah",
        aliases: &[],
        opcode: 0x44e07000,
        mask: 0xffe0f000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm4_INDEX,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_IMM_ROT2,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_rot2,
                    lsb: 10,
                    width: 2,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(
            SVE_MISC::SQRDCMLAH_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX_SVE_IMM_ROT2(
                SQRDCMLAH_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX_SVE_IMM_ROT2::from(bits),
            ),
        )
    }
}
impl InsnOpcode for SQRDCMLAH_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX_SVE_IMM_ROT2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQRDMLAH_SVE_Zd_SVE_Zn_SVE_Zm3_22_INDEX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqrdmlah",
        aliases: &[],
        opcode: 0x44201000,
        mask: 0xffa0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm3_22_INDEX,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_i3h,
                        lsb: 22,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zm_16,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::SQRDMLAH_SVE_Zd_SVE_Zn_SVE_Zm3_22_INDEX(
            SQRDMLAH_SVE_Zd_SVE_Zn_SVE_Zm3_22_INDEX::from(bits),
        ))
    }
}
impl InsnOpcode for SQRDMLAH_SVE_Zd_SVE_Zn_SVE_Zm3_22_INDEX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQRDMLAH_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqrdmlah",
        aliases: &[],
        opcode: 0x44a01000,
        mask: 0xffe0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm3_INDEX,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::SQRDMLAH_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX(
            SQRDMLAH_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX::from(bits),
        ))
    }
}
impl InsnOpcode for SQRDMLAH_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQRDMLAH_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqrdmlah",
        aliases: &[],
        opcode: 0x44e01000,
        mask: 0xffe0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm4_INDEX,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::SQRDMLAH_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX(
            SQRDMLAH_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX::from(bits),
        ))
    }
}
impl InsnOpcode for SQRDMLAH_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQRDMLAH_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqrdmlah",
        aliases: &[],
        opcode: 0x44007000,
        mask: 0xff20fc00,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::SQRDMLAH_SVE_Zd_SVE_Zn_SVE_Zm_16(
            SQRDMLAH_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for SQRDMLAH_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQRDMLAH_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqrdmlah",
        aliases: &[],
        opcode: 0x2e008400,
        mask: 0xbf20fc00,
        class: InsnClass::ASIMDSAME,
        feature_set: InsnFeatureSet::RDMA,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSAME(ASIMDSAME::SQRDMLAH_Vd_Vn_Vm(SQRDMLAH_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for SQRDMLAH_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQRDMLAH_Sd_Sn_Sm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqrdmlah",
        aliases: &[],
        opcode: 0x7e008400,
        mask: 0xff20fc00,
        class: InsnClass::ASIMDSAME,
        feature_set: InsnFeatureSet::RDMA,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sm,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMD_SCALAR_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSAME(ASIMDSAME::SQRDMLAH_Sd_Sn_Sm(SQRDMLAH_Sd_Sn_Sm::from(bits)))
    }
}
impl InsnOpcode for SQRDMLAH_Sd_Sn_Sm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQRDMLAH_Vd_Vn_Em16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqrdmlah",
        aliases: &[],
        opcode: 0x2f00d000,
        mask: 0xbf00f400,
        class: InsnClass::ASIMDELEM,
        feature_set: InsnFeatureSet::RDMA,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Em16,
                class: InsnOperandClass::SIMD_ELEMENT,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDELEM(ASIMDELEM::SQRDMLAH_Vd_Vn_Em16(SQRDMLAH_Vd_Vn_Em16::from(
            bits,
        )))
    }
}
impl InsnOpcode for SQRDMLAH_Vd_Vn_Em16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQRDMLAH_Sd_Sn_Em16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqrdmlah",
        aliases: &[],
        opcode: 0x7f00d000,
        mask: 0xff00f400,
        class: InsnClass::ASISDELEM,
        feature_set: InsnFeatureSet::RDMA,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Em16,
                class: InsnOperandClass::SIMD_ELEMENT,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMD_SCALAR_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDELEM(ASISDELEM::SQRDMLAH_Sd_Sn_Em16(SQRDMLAH_Sd_Sn_Em16::from(
            bits,
        )))
    }
}
impl InsnOpcode for SQRDMLAH_Sd_Sn_Em16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQRDMLSH_SVE_Zd_SVE_Zn_SVE_Zm3_22_INDEX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqrdmlsh",
        aliases: &[],
        opcode: 0x44201400,
        mask: 0xffa0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm3_22_INDEX,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_i3h,
                        lsb: 22,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zm_16,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::SQRDMLSH_SVE_Zd_SVE_Zn_SVE_Zm3_22_INDEX(
            SQRDMLSH_SVE_Zd_SVE_Zn_SVE_Zm3_22_INDEX::from(bits),
        ))
    }
}
impl InsnOpcode for SQRDMLSH_SVE_Zd_SVE_Zn_SVE_Zm3_22_INDEX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQRDMLSH_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqrdmlsh",
        aliases: &[],
        opcode: 0x44a01400,
        mask: 0xffe0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm3_INDEX,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::SQRDMLSH_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX(
            SQRDMLSH_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX::from(bits),
        ))
    }
}
impl InsnOpcode for SQRDMLSH_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQRDMLSH_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqrdmlsh",
        aliases: &[],
        opcode: 0x44e01400,
        mask: 0xffe0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm4_INDEX,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::SQRDMLSH_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX(
            SQRDMLSH_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX::from(bits),
        ))
    }
}
impl InsnOpcode for SQRDMLSH_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQRDMLSH_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqrdmlsh",
        aliases: &[],
        opcode: 0x44007400,
        mask: 0xff20fc00,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::SQRDMLSH_SVE_Zd_SVE_Zn_SVE_Zm_16(
            SQRDMLSH_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for SQRDMLSH_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQRDMLSH_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqrdmlsh",
        aliases: &[],
        opcode: 0x2e008c00,
        mask: 0xbf20fc00,
        class: InsnClass::ASIMDSAME,
        feature_set: InsnFeatureSet::RDMA,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSAME(ASIMDSAME::SQRDMLSH_Vd_Vn_Vm(SQRDMLSH_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for SQRDMLSH_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQRDMLSH_Sd_Sn_Sm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqrdmlsh",
        aliases: &[],
        opcode: 0x7e008c00,
        mask: 0xff20fc00,
        class: InsnClass::ASIMDSAME,
        feature_set: InsnFeatureSet::RDMA,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sm,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMD_SCALAR_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSAME(ASIMDSAME::SQRDMLSH_Sd_Sn_Sm(SQRDMLSH_Sd_Sn_Sm::from(bits)))
    }
}
impl InsnOpcode for SQRDMLSH_Sd_Sn_Sm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQRDMLSH_Vd_Vn_Em16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqrdmlsh",
        aliases: &[],
        opcode: 0x2f00f000,
        mask: 0xbf00f400,
        class: InsnClass::ASIMDELEM,
        feature_set: InsnFeatureSet::RDMA,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Em16,
                class: InsnOperandClass::SIMD_ELEMENT,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDELEM(ASIMDELEM::SQRDMLSH_Vd_Vn_Em16(SQRDMLSH_Vd_Vn_Em16::from(
            bits,
        )))
    }
}
impl InsnOpcode for SQRDMLSH_Vd_Vn_Em16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQRDMLSH_Sd_Sn_Em16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqrdmlsh",
        aliases: &[],
        opcode: 0x7f00f000,
        mask: 0xff00f400,
        class: InsnClass::ASISDELEM,
        feature_set: InsnFeatureSet::RDMA,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Em16,
                class: InsnOperandClass::SIMD_ELEMENT,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMD_SCALAR_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDELEM(ASISDELEM::SQRDMLSH_Sd_Sn_Em16(SQRDMLSH_Sd_Sn_Em16::from(
            bits,
        )))
    }
}
impl InsnOpcode for SQRDMLSH_Sd_Sn_Em16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQRDMULH_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqrdmulh",
        aliases: &[],
        opcode: 0x4207400,
        mask: 0xff20fc00,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::SQRDMULH_SVE_Zd_SVE_Zn_SVE_Zm_16(
            SQRDMULH_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for SQRDMULH_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQRDMULH_SVE_Zd_SVE_Zn_SVE_Zm3_22_INDEX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqrdmulh",
        aliases: &[],
        opcode: 0x4420f400,
        mask: 0xffa0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm3_22_INDEX,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_i3h,
                        lsb: 22,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zm_16,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::SQRDMULH_SVE_Zd_SVE_Zn_SVE_Zm3_22_INDEX(
            SQRDMULH_SVE_Zd_SVE_Zn_SVE_Zm3_22_INDEX::from(bits),
        ))
    }
}
impl InsnOpcode for SQRDMULH_SVE_Zd_SVE_Zn_SVE_Zm3_22_INDEX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQRDMULH_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqrdmulh",
        aliases: &[],
        opcode: 0x44a0f400,
        mask: 0xffe0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm3_INDEX,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::SQRDMULH_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX(
            SQRDMULH_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX::from(bits),
        ))
    }
}
impl InsnOpcode for SQRDMULH_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQRDMULH_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqrdmulh",
        aliases: &[],
        opcode: 0x44e0f400,
        mask: 0xffe0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm4_INDEX,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::SQRDMULH_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX(
            SQRDMULH_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX::from(bits),
        ))
    }
}
impl InsnOpcode for SQRDMULH_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQRDMULH_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqrdmulh",
        aliases: &[],
        opcode: 0x2e20b400,
        mask: 0xbf20fc00,
        class: InsnClass::ASIMDSAME,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSAME(ASIMDSAME::SQRDMULH_Vd_Vn_Vm(SQRDMULH_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for SQRDMULH_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQRDMULH_Sd_Sn_Sm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqrdmulh",
        aliases: &[],
        opcode: 0x7e20b400,
        mask: 0xff20fc00,
        class: InsnClass::ASISDSAME,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sm,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMD_SCALAR_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDSAME(ASISDSAME::SQRDMULH_Sd_Sn_Sm(SQRDMULH_Sd_Sn_Sm::from(bits)))
    }
}
impl InsnOpcode for SQRDMULH_Sd_Sn_Sm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQRDMULH_Vd_Vn_Em16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqrdmulh",
        aliases: &[],
        opcode: 0xf00d000,
        mask: 0xbf00f400,
        class: InsnClass::ASIMDELEM,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Em16,
                class: InsnOperandClass::SIMD_ELEMENT,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDELEM(ASIMDELEM::SQRDMULH_Vd_Vn_Em16(SQRDMULH_Vd_Vn_Em16::from(
            bits,
        )))
    }
}
impl InsnOpcode for SQRDMULH_Vd_Vn_Em16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQRDMULH_Sd_Sn_Em16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqrdmulh",
        aliases: &[],
        opcode: 0x5f00d000,
        mask: 0xff00f400,
        class: InsnClass::ASISDELEM,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Em16,
                class: InsnOperandClass::SIMD_ELEMENT,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMD_SCALAR_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDELEM(ASISDELEM::SQRDMULH_Sd_Sn_Em16(SQRDMULH_Sd_Sn_Em16::from(
            bits,
        )))
    }
}
impl InsnOpcode for SQRDMULH_Sd_Sn_Em16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQRSHL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqrshl",
        aliases: &[],
        opcode: 0x440a8000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::SQRSHL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(
            SQRSHL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for SQRSHL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQRSHL_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqrshl",
        aliases: &[],
        opcode: 0xe205c00,
        mask: 0xbf20fc00,
        class: InsnClass::ASIMDSAME,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSAME(ASIMDSAME::SQRSHL_Vd_Vn_Vm(SQRSHL_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for SQRSHL_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQRSHL_Sd_Sn_Sm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqrshl",
        aliases: &[],
        opcode: 0x5e205c00,
        mask: 0xff20fc00,
        class: InsnClass::ASISDSAME,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sm,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMD_SCALAR_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDSAME(ASISDSAME::SQRSHL_Sd_Sn_Sm(SQRSHL_Sd_Sn_Sm::from(bits)))
    }
}
impl InsnOpcode for SQRSHL_Sd_Sn_Sm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQRSHLR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqrshlr",
        aliases: &[],
        opcode: 0x440e8000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::SQRSHLR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(
            SQRSHLR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for SQRSHLR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQRSHR_SVE_Zd_SME_Znx4_SME_SHRIMM5 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqrshr",
        aliases: &[],
        opcode: 0xc120d800,
        mask: 0xff20fc60,
        class: InsnClass::SME_SHIFT,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn4,
                    lsb: 7,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_SHRIMM5,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_tszh,
                        lsb: 22,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_imm5b,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_SHIFT(SME_SHIFT::SQRSHR_SVE_Zd_SME_Znx4_SME_SHRIMM5(
            SQRSHR_SVE_Zd_SME_Znx4_SME_SHRIMM5::from(bits),
        ))
    }
}
impl InsnOpcode for SQRSHR_SVE_Zd_SME_Znx4_SME_SHRIMM5 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQRSHR_SVE_Zd_SME_Znx2_SME_SHRIMM4 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqrshr",
        aliases: &[],
        opcode: 0xc1e0d400,
        mask: 0xfff0fc20,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn2,
                    lsb: 6,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_SHRIMM4,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_imm4,
                    lsb: 16,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::SQRSHR_SVE_Zd_SME_Znx2_SME_SHRIMM4(
            SQRSHR_SVE_Zd_SME_Znx2_SME_SHRIMM4::from(bits),
        ))
    }
}
impl InsnOpcode for SQRSHR_SVE_Zd_SME_Znx2_SME_SHRIMM4 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQRSHRN_SVE_Zd_SME_Znx4_SME_SHRIMM5 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqrshrn",
        aliases: &[],
        opcode: 0xc120dc00,
        mask: 0xff20fc60,
        class: InsnClass::SME_SHIFT,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn4,
                    lsb: 7,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_SHRIMM5,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_tszh,
                        lsb: 22,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_imm5b,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_SHIFT(SME_SHIFT::SQRSHRN_SVE_Zd_SME_Znx4_SME_SHRIMM5(
            SQRSHRN_SVE_Zd_SME_Znx4_SME_SHRIMM5::from(bits),
        ))
    }
}
impl InsnOpcode for SQRSHRN_SVE_Zd_SME_Znx4_SME_SHRIMM5 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQRSHRN_SVE_Zd_SME_Znx2_SME_SHRIMM4 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqrshrn",
        aliases: &[],
        opcode: 0x45b02800,
        mask: 0xfff0fc20,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn2,
                    lsb: 6,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_SHRIMM4,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_imm4,
                    lsb: 16,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::SQRSHRN_SVE_Zd_SME_Znx2_SME_SHRIMM4(
            SQRSHRN_SVE_Zd_SME_Znx2_SME_SHRIMM4::from(bits),
        ))
    }
}
impl InsnOpcode for SQRSHRN_SVE_Zd_SME_Znx2_SME_SHRIMM4 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQRSHRN_Vd_Vn_IMM_VLSR {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqrshrn",
        aliases: &[],
        opcode: 0xf009c00,
        mask: 0xff80fc00,
        class: InsnClass::ASIMDSHF,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_4H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8H, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::IMM_VLSR,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_4H],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSHF(ASIMDSHF::SQRSHRN_Vd_Vn_IMM_VLSR(
            SQRSHRN_Vd_Vn_IMM_VLSR::from(bits),
        ))
    }
}
impl InsnOpcode for SQRSHRN_Vd_Vn_IMM_VLSR {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQRSHRN_Sd_Sn_IMM_VLSR {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqrshrn",
        aliases: &[],
        opcode: 0x5f009c00,
        mask: 0xff80fc00,
        class: InsnClass::ASISDSHF,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::IMM_VLSR,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDSHF(ASISDSHF::SQRSHRN_Sd_Sn_IMM_VLSR(
            SQRSHRN_Sd_Sn_IMM_VLSR::from(bits),
        ))
    }
}
impl InsnOpcode for SQRSHRN_Sd_Sn_IMM_VLSR {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQRSHRN2_Vd_Vn_IMM_VLSR {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqrshrn2",
        aliases: &[],
        opcode: 0x4f009c00,
        mask: 0xff80fc00,
        class: InsnClass::ASIMDSHF,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_16B, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8H, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::IMM_VLSR,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[InsnOperandQualifier::V_16B, InsnOperandQualifier::V_8H],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSHF(ASIMDSHF::SQRSHRN2_Vd_Vn_IMM_VLSR(
            SQRSHRN2_Vd_Vn_IMM_VLSR::from(bits),
        ))
    }
}
impl InsnOpcode for SQRSHRN2_Vd_Vn_IMM_VLSR {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQRSHRNB_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqrshrnb",
        aliases: &[],
        opcode: 0x45202800,
        mask: 0xffa0fc00,
        class: InsnClass::SVE_SHIFT_TSZ_HSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_SHRIMM_UNPRED_22,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_sz,
                        lsb: 22,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_tszl_19,
                        lsb: 19,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_imm3,
                        lsb: 16,
                        width: 3,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SHIFT_TSZ_HSD(
            SVE_SHIFT_TSZ_HSD::SQRSHRNB_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22(
                SQRSHRNB_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22::from(bits),
            ),
        )
    }
}
impl InsnOpcode for SQRSHRNB_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQRSHRNT_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqrshrnt",
        aliases: &[],
        opcode: 0x45202c00,
        mask: 0xffa0fc00,
        class: InsnClass::SVE_SHIFT_TSZ_HSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_SHRIMM_UNPRED_22,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_sz,
                        lsb: 22,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_tszl_19,
                        lsb: 19,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_imm3,
                        lsb: 16,
                        width: 3,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SHIFT_TSZ_HSD(
            SVE_SHIFT_TSZ_HSD::SQRSHRNT_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22(
                SQRSHRNT_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22::from(bits),
            ),
        )
    }
}
impl InsnOpcode for SQRSHRNT_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQRSHRU_SVE_Zd_SME_Znx4_SME_SHRIMM5 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqrshru",
        aliases: &[],
        opcode: 0xc120d840,
        mask: 0xff20fc60,
        class: InsnClass::SME_SHIFT,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn4,
                    lsb: 7,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_SHRIMM5,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_tszh,
                        lsb: 22,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_imm5b,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_SHIFT(SME_SHIFT::SQRSHRU_SVE_Zd_SME_Znx4_SME_SHRIMM5(
            SQRSHRU_SVE_Zd_SME_Znx4_SME_SHRIMM5::from(bits),
        ))
    }
}
impl InsnOpcode for SQRSHRU_SVE_Zd_SME_Znx4_SME_SHRIMM5 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQRSHRU_SVE_Zd_SME_Znx2_SME_SHRIMM4 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqrshru",
        aliases: &[],
        opcode: 0xc1f0d400,
        mask: 0xfff0fc20,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn2,
                    lsb: 6,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_SHRIMM4,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_imm4,
                    lsb: 16,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::SQRSHRU_SVE_Zd_SME_Znx2_SME_SHRIMM4(
            SQRSHRU_SVE_Zd_SME_Znx2_SME_SHRIMM4::from(bits),
        ))
    }
}
impl InsnOpcode for SQRSHRU_SVE_Zd_SME_Znx2_SME_SHRIMM4 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQRSHRUN_SVE_Zd_SME_Znx4_SME_SHRIMM5 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqrshrun",
        aliases: &[],
        opcode: 0xc120dc40,
        mask: 0xff20fc60,
        class: InsnClass::SME_SHIFT,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn4,
                    lsb: 7,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_SHRIMM5,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_tszh,
                        lsb: 22,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_imm5b,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_SHIFT(SME_SHIFT::SQRSHRUN_SVE_Zd_SME_Znx4_SME_SHRIMM5(
            SQRSHRUN_SVE_Zd_SME_Znx4_SME_SHRIMM5::from(bits),
        ))
    }
}
impl InsnOpcode for SQRSHRUN_SVE_Zd_SME_Znx4_SME_SHRIMM5 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQRSHRUN_SVE_Zd_SME_Znx2_SME_SHRIMM4 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqrshrun",
        aliases: &[],
        opcode: 0x45b00800,
        mask: 0xfff0fc20,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn2,
                    lsb: 6,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_SHRIMM4,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_imm4,
                    lsb: 16,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::SQRSHRUN_SVE_Zd_SME_Znx2_SME_SHRIMM4(
            SQRSHRUN_SVE_Zd_SME_Znx2_SME_SHRIMM4::from(bits),
        ))
    }
}
impl InsnOpcode for SQRSHRUN_SVE_Zd_SME_Znx2_SME_SHRIMM4 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQRSHRUN_Vd_Vn_IMM_VLSR {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqrshrun",
        aliases: &[],
        opcode: 0x2f008c00,
        mask: 0xff80fc00,
        class: InsnClass::ASIMDSHF,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_4H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8H, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::IMM_VLSR,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_4H],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSHF(ASIMDSHF::SQRSHRUN_Vd_Vn_IMM_VLSR(
            SQRSHRUN_Vd_Vn_IMM_VLSR::from(bits),
        ))
    }
}
impl InsnOpcode for SQRSHRUN_Vd_Vn_IMM_VLSR {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQRSHRUN_Sd_Sn_IMM_VLSR {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqrshrun",
        aliases: &[],
        opcode: 0x7f008c00,
        mask: 0xff80fc00,
        class: InsnClass::ASISDSHF,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::IMM_VLSR,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDSHF(ASISDSHF::SQRSHRUN_Sd_Sn_IMM_VLSR(
            SQRSHRUN_Sd_Sn_IMM_VLSR::from(bits),
        ))
    }
}
impl InsnOpcode for SQRSHRUN_Sd_Sn_IMM_VLSR {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQRSHRUN2_Vd_Vn_IMM_VLSR {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqrshrun2",
        aliases: &[],
        opcode: 0x6f008c00,
        mask: 0xff80fc00,
        class: InsnClass::ASIMDSHF,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_16B, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8H, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::IMM_VLSR,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[InsnOperandQualifier::V_16B, InsnOperandQualifier::V_8H],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSHF(ASIMDSHF::SQRSHRUN2_Vd_Vn_IMM_VLSR(
            SQRSHRUN2_Vd_Vn_IMM_VLSR::from(bits),
        ))
    }
}
impl InsnOpcode for SQRSHRUN2_Vd_Vn_IMM_VLSR {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQRSHRUNB_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqrshrunb",
        aliases: &[],
        opcode: 0x45200800,
        mask: 0xffa0fc00,
        class: InsnClass::SVE_SHIFT_TSZ_HSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_SHRIMM_UNPRED_22,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_sz,
                        lsb: 22,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_tszl_19,
                        lsb: 19,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_imm3,
                        lsb: 16,
                        width: 3,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SHIFT_TSZ_HSD(
            SVE_SHIFT_TSZ_HSD::SQRSHRUNB_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22(
                SQRSHRUNB_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22::from(bits),
            ),
        )
    }
}
impl InsnOpcode for SQRSHRUNB_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQRSHRUNT_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqrshrunt",
        aliases: &[],
        opcode: 0x45200c00,
        mask: 0xffa0fc00,
        class: InsnClass::SVE_SHIFT_TSZ_HSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_SHRIMM_UNPRED_22,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_sz,
                        lsb: 22,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_tszl_19,
                        lsb: 19,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_imm3,
                        lsb: 16,
                        width: 3,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SHIFT_TSZ_HSD(
            SVE_SHIFT_TSZ_HSD::SQRSHRUNT_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22(
                SQRSHRUNT_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22::from(bits),
            ),
        )
    }
}
impl InsnOpcode for SQRSHRUNT_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQSHL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqshl",
        aliases: &[],
        opcode: 0x44088000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::SQSHL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(
            SQSHL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for SQSHL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQSHL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_SHLIMM_PRED {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqshl",
        aliases: &[],
        opcode: 0x4068000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SHIFT_PRED,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_SHLIMM_PRED,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_tszh,
                        lsb: 22,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_imm5,
                        lsb: 5,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SHIFT_PRED(SVE_SHIFT_PRED::SQSHL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_SHLIMM_PRED(
            SQSHL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_SHLIMM_PRED::from(bits),
        ))
    }
}
impl InsnOpcode for SQSHL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_SHLIMM_PRED {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQSHL_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqshl",
        aliases: &[],
        opcode: 0xe204c00,
        mask: 0xbf20fc00,
        class: InsnClass::ASIMDSAME,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSAME(ASIMDSAME::SQSHL_Vd_Vn_Vm(SQSHL_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for SQSHL_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQSHL_Sd_Sn_Sm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqshl",
        aliases: &[],
        opcode: 0x5e204c00,
        mask: 0xff20fc00,
        class: InsnClass::ASISDSAME,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sm,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMD_SCALAR_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDSAME(ASISDSAME::SQSHL_Sd_Sn_Sm(SQSHL_Sd_Sn_Sm::from(bits)))
    }
}
impl InsnOpcode for SQSHL_Sd_Sn_Sm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQSHL_Vd_Vn_IMM_VLSL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqshl",
        aliases: &[],
        opcode: 0xf007400,
        mask: 0xbf80fc00,
        class: InsnClass::ASIMDSHF,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::IMM_VLSL,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSHF(ASIMDSHF::SQSHL_Vd_Vn_IMM_VLSL(SQSHL_Vd_Vn_IMM_VLSL::from(
            bits,
        )))
    }
}
impl InsnOpcode for SQSHL_Vd_Vn_IMM_VLSL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQSHL_Sd_Sn_IMM_VLSL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqshl",
        aliases: &[],
        opcode: 0x5f007400,
        mask: 0xff80fc00,
        class: InsnClass::ASISDSHF,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::IMM_VLSL,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDSHF(ASISDSHF::SQSHL_Sd_Sn_IMM_VLSL(SQSHL_Sd_Sn_IMM_VLSL::from(
            bits,
        )))
    }
}
impl InsnOpcode for SQSHL_Sd_Sn_IMM_VLSL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQSHLR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqshlr",
        aliases: &[],
        opcode: 0x440c8000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::SQSHLR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(
            SQSHLR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for SQSHLR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQSHLU_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_SHLIMM_PRED {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqshlu",
        aliases: &[],
        opcode: 0x40f8000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SHIFT_PRED,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_SHLIMM_PRED,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_tszh,
                        lsb: 22,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_imm5,
                        lsb: 5,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SHIFT_PRED(
            SVE_SHIFT_PRED::SQSHLU_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_SHLIMM_PRED(
                SQSHLU_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_SHLIMM_PRED::from(bits),
            ),
        )
    }
}
impl InsnOpcode for SQSHLU_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_SHLIMM_PRED {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQSHLU_Vd_Vn_IMM_VLSL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqshlu",
        aliases: &[],
        opcode: 0x2f006400,
        mask: 0xbf80fc00,
        class: InsnClass::ASIMDSHF,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::IMM_VLSL,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSHF(ASIMDSHF::SQSHLU_Vd_Vn_IMM_VLSL(
            SQSHLU_Vd_Vn_IMM_VLSL::from(bits),
        ))
    }
}
impl InsnOpcode for SQSHLU_Vd_Vn_IMM_VLSL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQSHLU_Sd_Sn_IMM_VLSL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqshlu",
        aliases: &[],
        opcode: 0x7f006400,
        mask: 0xff80fc00,
        class: InsnClass::ASISDSHF,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::IMM_VLSL,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDSHF(ASISDSHF::SQSHLU_Sd_Sn_IMM_VLSL(
            SQSHLU_Sd_Sn_IMM_VLSL::from(bits),
        ))
    }
}
impl InsnOpcode for SQSHLU_Sd_Sn_IMM_VLSL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQSHRN_Vd_Vn_IMM_VLSR {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqshrn",
        aliases: &[],
        opcode: 0xf009400,
        mask: 0xff80fc00,
        class: InsnClass::ASIMDSHF,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_4H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8H, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::IMM_VLSR,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_4H],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSHF(ASIMDSHF::SQSHRN_Vd_Vn_IMM_VLSR(
            SQSHRN_Vd_Vn_IMM_VLSR::from(bits),
        ))
    }
}
impl InsnOpcode for SQSHRN_Vd_Vn_IMM_VLSR {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQSHRN_Sd_Sn_IMM_VLSR {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqshrn",
        aliases: &[],
        opcode: 0x5f009400,
        mask: 0xff80fc00,
        class: InsnClass::ASISDSHF,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::IMM_VLSR,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDSHF(ASISDSHF::SQSHRN_Sd_Sn_IMM_VLSR(
            SQSHRN_Sd_Sn_IMM_VLSR::from(bits),
        ))
    }
}
impl InsnOpcode for SQSHRN_Sd_Sn_IMM_VLSR {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQSHRN2_Vd_Vn_IMM_VLSR {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqshrn2",
        aliases: &[],
        opcode: 0x4f009400,
        mask: 0xff80fc00,
        class: InsnClass::ASIMDSHF,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_16B, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8H, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::IMM_VLSR,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[InsnOperandQualifier::V_16B, InsnOperandQualifier::V_8H],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSHF(ASIMDSHF::SQSHRN2_Vd_Vn_IMM_VLSR(
            SQSHRN2_Vd_Vn_IMM_VLSR::from(bits),
        ))
    }
}
impl InsnOpcode for SQSHRN2_Vd_Vn_IMM_VLSR {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQSHRNB_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqshrnb",
        aliases: &[],
        opcode: 0x45202000,
        mask: 0xffa0fc00,
        class: InsnClass::SVE_SHIFT_TSZ_HSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_SHRIMM_UNPRED_22,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_sz,
                        lsb: 22,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_tszl_19,
                        lsb: 19,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_imm3,
                        lsb: 16,
                        width: 3,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SHIFT_TSZ_HSD(
            SVE_SHIFT_TSZ_HSD::SQSHRNB_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22(
                SQSHRNB_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22::from(bits),
            ),
        )
    }
}
impl InsnOpcode for SQSHRNB_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQSHRNT_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqshrnt",
        aliases: &[],
        opcode: 0x45202400,
        mask: 0xffa0fc00,
        class: InsnClass::SVE_SHIFT_TSZ_HSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_SHRIMM_UNPRED_22,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_sz,
                        lsb: 22,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_tszl_19,
                        lsb: 19,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_imm3,
                        lsb: 16,
                        width: 3,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SHIFT_TSZ_HSD(
            SVE_SHIFT_TSZ_HSD::SQSHRNT_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22(
                SQSHRNT_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22::from(bits),
            ),
        )
    }
}
impl InsnOpcode for SQSHRNT_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQSHRUN_Vd_Vn_IMM_VLSR {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqshrun",
        aliases: &[],
        opcode: 0x2f008400,
        mask: 0xff80fc00,
        class: InsnClass::ASIMDSHF,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_4H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8H, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::IMM_VLSR,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_4H],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSHF(ASIMDSHF::SQSHRUN_Vd_Vn_IMM_VLSR(
            SQSHRUN_Vd_Vn_IMM_VLSR::from(bits),
        ))
    }
}
impl InsnOpcode for SQSHRUN_Vd_Vn_IMM_VLSR {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQSHRUN_Sd_Sn_IMM_VLSR {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqshrun",
        aliases: &[],
        opcode: 0x7f008400,
        mask: 0xff80fc00,
        class: InsnClass::ASISDSHF,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::IMM_VLSR,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDSHF(ASISDSHF::SQSHRUN_Sd_Sn_IMM_VLSR(
            SQSHRUN_Sd_Sn_IMM_VLSR::from(bits),
        ))
    }
}
impl InsnOpcode for SQSHRUN_Sd_Sn_IMM_VLSR {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQSHRUN2_Vd_Vn_IMM_VLSR {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqshrun2",
        aliases: &[],
        opcode: 0x6f008400,
        mask: 0xff80fc00,
        class: InsnClass::ASIMDSHF,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_16B, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8H, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::IMM_VLSR,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[InsnOperandQualifier::V_16B, InsnOperandQualifier::V_8H],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSHF(ASIMDSHF::SQSHRUN2_Vd_Vn_IMM_VLSR(
            SQSHRUN2_Vd_Vn_IMM_VLSR::from(bits),
        ))
    }
}
impl InsnOpcode for SQSHRUN2_Vd_Vn_IMM_VLSR {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQSHRUNB_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqshrunb",
        aliases: &[],
        opcode: 0x45200000,
        mask: 0xffa0fc00,
        class: InsnClass::SVE_SHIFT_TSZ_HSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_SHRIMM_UNPRED_22,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_sz,
                        lsb: 22,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_tszl_19,
                        lsb: 19,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_imm3,
                        lsb: 16,
                        width: 3,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SHIFT_TSZ_HSD(
            SVE_SHIFT_TSZ_HSD::SQSHRUNB_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22(
                SQSHRUNB_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22::from(bits),
            ),
        )
    }
}
impl InsnOpcode for SQSHRUNB_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQSHRUNT_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqshrunt",
        aliases: &[],
        opcode: 0x45200400,
        mask: 0xffa0fc00,
        class: InsnClass::SVE_SHIFT_TSZ_HSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_SHRIMM_UNPRED_22,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_sz,
                        lsb: 22,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_tszl_19,
                        lsb: 19,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_imm3,
                        lsb: 16,
                        width: 3,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SHIFT_TSZ_HSD(
            SVE_SHIFT_TSZ_HSD::SQSHRUNT_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22(
                SQSHRUNT_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22::from(bits),
            ),
        )
    }
}
impl InsnOpcode for SQSHRUNT_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQSUB_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqsub",
        aliases: &[],
        opcode: 0x4201800,
        mask: 0xff20fc00,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::SQSUB_SVE_Zd_SVE_Zn_SVE_Zm_16(
            SQSUB_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for SQSUB_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQSUB_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqsub",
        aliases: &[],
        opcode: 0x441a8000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::SQSUB_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(
            SQSUB_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for SQSUB_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQSUB_SVE_Zd_SVE_Zd_SVE_AIMM {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqsub",
        aliases: &[],
        opcode: 0x2526c000,
        mask: 0xff3fc000,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_AIMM,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_imm9,
                    lsb: 5,
                    width: 9,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::SQSUB_SVE_Zd_SVE_Zd_SVE_AIMM(
            SQSUB_SVE_Zd_SVE_Zd_SVE_AIMM::from(bits),
        ))
    }
}
impl InsnOpcode for SQSUB_SVE_Zd_SVE_Zd_SVE_AIMM {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQSUB_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqsub",
        aliases: &[],
        opcode: 0xe202c00,
        mask: 0xbf20fc00,
        class: InsnClass::ASIMDSAME,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSAME(ASIMDSAME::SQSUB_Vd_Vn_Vm(SQSUB_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for SQSUB_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQSUB_Sd_Sn_Sm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqsub",
        aliases: &[],
        opcode: 0x5e202c00,
        mask: 0xff20fc00,
        class: InsnClass::ASISDSAME,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sm,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMD_SCALAR_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDSAME(ASISDSAME::SQSUB_Sd_Sn_Sm(SQSUB_Sd_Sn_Sm::from(bits)))
    }
}
impl InsnOpcode for SQSUB_Sd_Sn_Sm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQSUBR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqsubr",
        aliases: &[],
        opcode: 0x441e8000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::SQSUBR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(
            SQSUBR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for SQSUBR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQXTN_Vd_Vn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqxtn",
        aliases: &[],
        opcode: 0xe214800,
        mask: 0xff3ffc00,
        class: InsnClass::ASIMDMISC,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDMISC(ASIMDMISC::SQXTN_Vd_Vn(SQXTN_Vd_Vn::from(bits)))
    }
}
impl InsnOpcode for SQXTN_Vd_Vn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQXTN_Sd_Sn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqxtn",
        aliases: &[],
        opcode: 0x5e214800,
        mask: 0xff3ffc00,
        class: InsnClass::ASISDMISC,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMD_SCALAR_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDMISC(ASISDMISC::SQXTN_Sd_Sn(SQXTN_Sd_Sn::from(bits)))
    }
}
impl InsnOpcode for SQXTN_Sd_Sn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQXTN2_Vd_Vn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqxtn2",
        aliases: &[],
        opcode: 0x4e214800,
        mask: 0xff3ffc00,
        class: InsnClass::ASIMDMISC,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDMISC(ASIMDMISC::SQXTN2_Vd_Vn(SQXTN2_Vd_Vn::from(bits)))
    }
}
impl InsnOpcode for SQXTN2_Vd_Vn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQXTNB_SVE_Zd_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqxtnb",
        aliases: &[],
        opcode: 0x45204000,
        mask: 0xffa7fc00,
        class: InsnClass::SVE_SIZE_TSZ_BHS,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_TSZ_BHS(SVE_SIZE_TSZ_BHS::SQXTNB_SVE_Zd_SVE_Zn(
            SQXTNB_SVE_Zd_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for SQXTNB_SVE_Zd_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQXTNT_SVE_Zd_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqxtnt",
        aliases: &[],
        opcode: 0x45204400,
        mask: 0xffa7fc00,
        class: InsnClass::SVE_SIZE_TSZ_BHS,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_TSZ_BHS(SVE_SIZE_TSZ_BHS::SQXTNT_SVE_Zd_SVE_Zn(
            SQXTNT_SVE_Zd_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for SQXTNT_SVE_Zd_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQXTUN_Vd_Vn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqxtun",
        aliases: &[],
        opcode: 0x2e212800,
        mask: 0xff3ffc00,
        class: InsnClass::ASIMDMISC,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDMISC(ASIMDMISC::SQXTUN_Vd_Vn(SQXTUN_Vd_Vn::from(bits)))
    }
}
impl InsnOpcode for SQXTUN_Vd_Vn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQXTUN_Sd_Sn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqxtun",
        aliases: &[],
        opcode: 0x7e212800,
        mask: 0xff3ffc00,
        class: InsnClass::ASISDMISC,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMD_SCALAR_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDMISC(ASISDMISC::SQXTUN_Sd_Sn(SQXTUN_Sd_Sn::from(bits)))
    }
}
impl InsnOpcode for SQXTUN_Sd_Sn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQXTUN2_Vd_Vn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqxtun2",
        aliases: &[],
        opcode: 0x6e212800,
        mask: 0xff3ffc00,
        class: InsnClass::ASIMDMISC,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDMISC(ASIMDMISC::SQXTUN2_Vd_Vn(SQXTUN2_Vd_Vn::from(bits)))
    }
}
impl InsnOpcode for SQXTUN2_Vd_Vn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQXTUNB_SVE_Zd_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqxtunb",
        aliases: &[],
        opcode: 0x45205000,
        mask: 0xffa7fc00,
        class: InsnClass::SVE_SIZE_TSZ_BHS,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_TSZ_BHS(SVE_SIZE_TSZ_BHS::SQXTUNB_SVE_Zd_SVE_Zn(
            SQXTUNB_SVE_Zd_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for SQXTUNB_SVE_Zd_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SQXTUNT_SVE_Zd_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sqxtunt",
        aliases: &[],
        opcode: 0x45205400,
        mask: 0xffa7fc00,
        class: InsnClass::SVE_SIZE_TSZ_BHS,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_TSZ_BHS(SVE_SIZE_TSZ_BHS::SQXTUNT_SVE_Zd_SVE_Zn(
            SQXTUNT_SVE_Zd_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for SQXTUNT_SVE_Zd_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SRHADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "srhadd",
        aliases: &[],
        opcode: 0x44148000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::SRHADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(
            SRHADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for SRHADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SRHADD_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "srhadd",
        aliases: &[],
        opcode: 0xe201400,
        mask: 0xbf20fc00,
        class: InsnClass::ASIMDSAME,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSAME(ASIMDSAME::SRHADD_Vd_Vn_Vm(SRHADD_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for SRHADD_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SRI_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sri",
        aliases: &[],
        opcode: 0x4500f000,
        mask: 0xff20fc00,
        class: InsnClass::SVE_SHIFT_TSZ_BHSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_SHRIMM_UNPRED,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_tszh,
                        lsb: 22,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm5,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SHIFT_TSZ_BHSD(SVE_SHIFT_TSZ_BHSD::SRI_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED(
            SRI_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED::from(bits),
        ))
    }
}
impl InsnOpcode for SRI_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SRI_Vd_Vn_IMM_VLSR {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sri",
        aliases: &[],
        opcode: 0x2f004400,
        mask: 0xbf80fc00,
        class: InsnClass::ASIMDSHF,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::IMM_VLSR,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSHF(ASIMDSHF::SRI_Vd_Vn_IMM_VLSR(SRI_Vd_Vn_IMM_VLSR::from(bits)))
    }
}
impl InsnOpcode for SRI_Vd_Vn_IMM_VLSR {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SRI_Sd_Sn_IMM_VLSR {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sri",
        aliases: &[],
        opcode: 0x7f004400,
        mask: 0xff80fc00,
        class: InsnClass::ASISDSHF,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::IMM_VLSR,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDSHF(ASISDSHF::SRI_Sd_Sn_IMM_VLSR(SRI_Sd_Sn_IMM_VLSR::from(bits)))
    }
}
impl InsnOpcode for SRI_Sd_Sn_IMM_VLSR {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SRSHL_SME_Zdnx2_SME_Zdnx2_SME_Zm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "srshl",
        aliases: &[],
        opcode: 0xc120a220,
        mask: 0xff30ffe1,
        class: InsnClass::SME_SIZE_22,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn2,
                    lsb: 1,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn2,
                    lsb: 1,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm,
                    lsb: 16,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_SIZE_22(SME_SIZE_22::SRSHL_SME_Zdnx2_SME_Zdnx2_SME_Zm(
            SRSHL_SME_Zdnx2_SME_Zdnx2_SME_Zm::from(bits),
        ))
    }
}
impl InsnOpcode for SRSHL_SME_Zdnx2_SME_Zdnx2_SME_Zm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SRSHL_SME_Zdnx2_SME_Zdnx2_SME_Zmx2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "srshl",
        aliases: &[],
        opcode: 0xc120b220,
        mask: 0xff21ffe1,
        class: InsnClass::SME_SIZE_22,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn2,
                    lsb: 1,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn2,
                    lsb: 1,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zmx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm2,
                    lsb: 17,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_SIZE_22(SME_SIZE_22::SRSHL_SME_Zdnx2_SME_Zdnx2_SME_Zmx2(
            SRSHL_SME_Zdnx2_SME_Zdnx2_SME_Zmx2::from(bits),
        ))
    }
}
impl InsnOpcode for SRSHL_SME_Zdnx2_SME_Zdnx2_SME_Zmx2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SRSHL_SME_Zdnx4_SME_Zdnx4_SME_Zm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "srshl",
        aliases: &[],
        opcode: 0xc120aa20,
        mask: 0xff30ffe3,
        class: InsnClass::SME_SIZE_22,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn4,
                    lsb: 2,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn4,
                    lsb: 2,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm,
                    lsb: 16,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_SIZE_22(SME_SIZE_22::SRSHL_SME_Zdnx4_SME_Zdnx4_SME_Zm(
            SRSHL_SME_Zdnx4_SME_Zdnx4_SME_Zm::from(bits),
        ))
    }
}
impl InsnOpcode for SRSHL_SME_Zdnx4_SME_Zdnx4_SME_Zm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SRSHL_SME_Zdnx4_SME_Zdnx4_SME_Zmx4 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "srshl",
        aliases: &[],
        opcode: 0xc120ba20,
        mask: 0xff23ffe3,
        class: InsnClass::SME_SIZE_22,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn4,
                    lsb: 2,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn4,
                    lsb: 2,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zmx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm4,
                    lsb: 18,
                    width: 3,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_SIZE_22(SME_SIZE_22::SRSHL_SME_Zdnx4_SME_Zdnx4_SME_Zmx4(
            SRSHL_SME_Zdnx4_SME_Zdnx4_SME_Zmx4::from(bits),
        ))
    }
}
impl InsnOpcode for SRSHL_SME_Zdnx4_SME_Zdnx4_SME_Zmx4 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SRSHL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "srshl",
        aliases: &[],
        opcode: 0x44028000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::SRSHL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(
            SRSHL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for SRSHL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SRSHL_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "srshl",
        aliases: &[],
        opcode: 0xe205400,
        mask: 0xbf20fc00,
        class: InsnClass::ASIMDSAME,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSAME(ASIMDSAME::SRSHL_Vd_Vn_Vm(SRSHL_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for SRSHL_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SRSHL_Sd_Sn_Sm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "srshl",
        aliases: &[],
        opcode: 0x5ee05400,
        mask: 0xffe0fc00,
        class: InsnClass::ASISDSAME,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sm,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMD_SCALAR_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDSAME(ASISDSAME::SRSHL_Sd_Sn_Sm(SRSHL_Sd_Sn_Sm::from(bits)))
    }
}
impl InsnOpcode for SRSHL_Sd_Sn_Sm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SRSHLR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "srshlr",
        aliases: &[],
        opcode: 0x44068000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::SRSHLR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(
            SRSHLR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for SRSHLR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SRSHR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_SHRIMM_PRED {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "srshr",
        aliases: &[],
        opcode: 0x40c8000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SHIFT_PRED,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_SHRIMM_PRED,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_tszh,
                        lsb: 22,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_imm5,
                        lsb: 5,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SHIFT_PRED(SVE_SHIFT_PRED::SRSHR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_SHRIMM_PRED(
            SRSHR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_SHRIMM_PRED::from(bits),
        ))
    }
}
impl InsnOpcode for SRSHR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_SHRIMM_PRED {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SRSHR_Vd_Vn_IMM_VLSR {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "srshr",
        aliases: &[],
        opcode: 0xf002400,
        mask: 0xbf80fc00,
        class: InsnClass::ASIMDSHF,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::IMM_VLSR,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSHF(ASIMDSHF::SRSHR_Vd_Vn_IMM_VLSR(SRSHR_Vd_Vn_IMM_VLSR::from(
            bits,
        )))
    }
}
impl InsnOpcode for SRSHR_Vd_Vn_IMM_VLSR {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SRSHR_Sd_Sn_IMM_VLSR {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "srshr",
        aliases: &[],
        opcode: 0x5f002400,
        mask: 0xff80fc00,
        class: InsnClass::ASISDSHF,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::IMM_VLSR,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDSHF(ASISDSHF::SRSHR_Sd_Sn_IMM_VLSR(SRSHR_Sd_Sn_IMM_VLSR::from(
            bits,
        )))
    }
}
impl InsnOpcode for SRSHR_Sd_Sn_IMM_VLSR {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SRSRA_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "srsra",
        aliases: &[],
        opcode: 0x4500e800,
        mask: 0xff20fc00,
        class: InsnClass::SVE_SHIFT_TSZ_BHSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_SHRIMM_UNPRED,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_tszh,
                        lsb: 22,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm5,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SHIFT_TSZ_BHSD(SVE_SHIFT_TSZ_BHSD::SRSRA_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED(
            SRSRA_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED::from(bits),
        ))
    }
}
impl InsnOpcode for SRSRA_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SRSRA_Vd_Vn_IMM_VLSR {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "srsra",
        aliases: &[],
        opcode: 0xf003400,
        mask: 0xbf80fc00,
        class: InsnClass::ASIMDSHF,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::IMM_VLSR,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSHF(ASIMDSHF::SRSRA_Vd_Vn_IMM_VLSR(SRSRA_Vd_Vn_IMM_VLSR::from(
            bits,
        )))
    }
}
impl InsnOpcode for SRSRA_Vd_Vn_IMM_VLSR {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SRSRA_Sd_Sn_IMM_VLSR {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "srsra",
        aliases: &[],
        opcode: 0x5f003400,
        mask: 0xff80fc00,
        class: InsnClass::ASISDSHF,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::IMM_VLSR,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDSHF(ASISDSHF::SRSRA_Sd_Sn_IMM_VLSR(SRSRA_Sd_Sn_IMM_VLSR::from(
            bits,
        )))
    }
}
impl InsnOpcode for SRSRA_Sd_Sn_IMM_VLSR {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SSHL_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sshl",
        aliases: &[],
        opcode: 0xe204400,
        mask: 0xbf20fc00,
        class: InsnClass::ASIMDSAME,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSAME(ASIMDSAME::SSHL_Vd_Vn_Vm(SSHL_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for SSHL_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SSHL_Sd_Sn_Sm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sshl",
        aliases: &[],
        opcode: 0x5ee04400,
        mask: 0xffe0fc00,
        class: InsnClass::ASISDSAME,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sm,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMD_SCALAR_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDSAME(ASISDSAME::SSHL_Sd_Sn_Sm(SSHL_Sd_Sn_Sm::from(bits)))
    }
}
impl InsnOpcode for SSHL_Sd_Sn_Sm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SSHLL_Vd_Vn_IMM_VLSL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sshll",
        aliases: &[],
        opcode: 0xf00a400,
        mask: 0xff80fc00,
        class: InsnClass::ASIMDSHF,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8H, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_4H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::IMM_VLSL,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_4H],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ALIAS.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSHF(ASIMDSHF::SSHLL_Vd_Vn_IMM_VLSL(SSHLL_Vd_Vn_IMM_VLSL::from(
            bits,
        )))
    }
}
impl InsnOpcode for SSHLL_Vd_Vn_IMM_VLSL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SSHLL2_Vd_Vn_IMM_VLSL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sshll2",
        aliases: &[],
        opcode: 0x4f00a400,
        mask: 0xff80fc00,
        class: InsnClass::ASIMDSHF,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8H, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_16B, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::IMM_VLSL,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[InsnOperandQualifier::V_16B, InsnOperandQualifier::V_8H],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ALIAS.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSHF(ASIMDSHF::SSHLL2_Vd_Vn_IMM_VLSL(
            SSHLL2_Vd_Vn_IMM_VLSL::from(bits),
        ))
    }
}
impl InsnOpcode for SSHLL2_Vd_Vn_IMM_VLSL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SSHLLB_SVE_Zd_SVE_Zn_SVE_SHLIMM_UNPRED_22 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sshllb",
        aliases: &[],
        opcode: 0x4500a000,
        mask: 0xffa0fc00,
        class: InsnClass::SVE_SHIFT_TSZ_HSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_SHLIMM_UNPRED_22,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_sz,
                        lsb: 22,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_tszl_19,
                        lsb: 19,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_imm3,
                        lsb: 16,
                        width: 3,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SHIFT_TSZ_HSD(
            SVE_SHIFT_TSZ_HSD::SSHLLB_SVE_Zd_SVE_Zn_SVE_SHLIMM_UNPRED_22(
                SSHLLB_SVE_Zd_SVE_Zn_SVE_SHLIMM_UNPRED_22::from(bits),
            ),
        )
    }
}
impl InsnOpcode for SSHLLB_SVE_Zd_SVE_Zn_SVE_SHLIMM_UNPRED_22 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SSHLLT_SVE_Zd_SVE_Zn_SVE_SHLIMM_UNPRED_22 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sshllt",
        aliases: &[],
        opcode: 0x4500a400,
        mask: 0xffa0fc00,
        class: InsnClass::SVE_SHIFT_TSZ_HSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_SHLIMM_UNPRED_22,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_sz,
                        lsb: 22,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_tszl_19,
                        lsb: 19,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_imm3,
                        lsb: 16,
                        width: 3,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SHIFT_TSZ_HSD(
            SVE_SHIFT_TSZ_HSD::SSHLLT_SVE_Zd_SVE_Zn_SVE_SHLIMM_UNPRED_22(
                SSHLLT_SVE_Zd_SVE_Zn_SVE_SHLIMM_UNPRED_22::from(bits),
            ),
        )
    }
}
impl InsnOpcode for SSHLLT_SVE_Zd_SVE_Zn_SVE_SHLIMM_UNPRED_22 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SSHR_Vd_Vn_IMM_VLSR {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sshr",
        aliases: &[],
        opcode: 0xf000400,
        mask: 0xbf80fc00,
        class: InsnClass::ASIMDSHF,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::IMM_VLSR,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSHF(ASIMDSHF::SSHR_Vd_Vn_IMM_VLSR(SSHR_Vd_Vn_IMM_VLSR::from(
            bits,
        )))
    }
}
impl InsnOpcode for SSHR_Vd_Vn_IMM_VLSR {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SSHR_Sd_Sn_IMM_VLSR {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sshr",
        aliases: &[],
        opcode: 0x5f000400,
        mask: 0xff80fc00,
        class: InsnClass::ASISDSHF,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::IMM_VLSR,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDSHF(ASISDSHF::SSHR_Sd_Sn_IMM_VLSR(SSHR_Sd_Sn_IMM_VLSR::from(
            bits,
        )))
    }
}
impl InsnOpcode for SSHR_Sd_Sn_IMM_VLSR {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SSRA_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ssra",
        aliases: &[],
        opcode: 0x4500e000,
        mask: 0xff20fc00,
        class: InsnClass::SVE_SHIFT_TSZ_BHSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_SHRIMM_UNPRED,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_tszh,
                        lsb: 22,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm5,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SHIFT_TSZ_BHSD(SVE_SHIFT_TSZ_BHSD::SSRA_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED(
            SSRA_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED::from(bits),
        ))
    }
}
impl InsnOpcode for SSRA_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SSRA_Vd_Vn_IMM_VLSR {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ssra",
        aliases: &[],
        opcode: 0xf001400,
        mask: 0xbf80fc00,
        class: InsnClass::ASIMDSHF,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::IMM_VLSR,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSHF(ASIMDSHF::SSRA_Vd_Vn_IMM_VLSR(SSRA_Vd_Vn_IMM_VLSR::from(
            bits,
        )))
    }
}
impl InsnOpcode for SSRA_Vd_Vn_IMM_VLSR {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SSRA_Sd_Sn_IMM_VLSR {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ssra",
        aliases: &[],
        opcode: 0x5f001400,
        mask: 0xff80fc00,
        class: InsnClass::ASISDSHF,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::IMM_VLSR,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDSHF(ASISDSHF::SSRA_Sd_Sn_IMM_VLSR(SSRA_Sd_Sn_IMM_VLSR::from(
            bits,
        )))
    }
}
impl InsnOpcode for SSRA_Sd_Sn_IMM_VLSR {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SSUBL_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ssubl",
        aliases: &[],
        opcode: 0xe202000,
        mask: 0xff20fc00,
        class: InsnClass::ASIMDDIFF,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8H, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_4H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_4H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDDIFF(ASIMDDIFF::SSUBL_Vd_Vn_Vm(SSUBL_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for SSUBL_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SSUBL2_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ssubl2",
        aliases: &[],
        opcode: 0x4e202000,
        mask: 0xff20fc00,
        class: InsnClass::ASIMDDIFF,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8H, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_16B, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_16B, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDDIFF(ASIMDDIFF::SSUBL2_Vd_Vn_Vm(SSUBL2_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for SSUBL2_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SSUBLB_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ssublb",
        aliases: &[],
        opcode: 0x45001000,
        mask: 0xff20fc00,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::SSUBLB_SVE_Zd_SVE_Zn_SVE_Zm_16(
            SSUBLB_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for SSUBLB_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SSUBLBT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ssublbt",
        aliases: &[],
        opcode: 0x45008800,
        mask: 0xff20fc00,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::SSUBLBT_SVE_Zd_SVE_Zn_SVE_Zm_16(
            SSUBLBT_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for SSUBLBT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SSUBLT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ssublt",
        aliases: &[],
        opcode: 0x45001400,
        mask: 0xff20fc00,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::SSUBLT_SVE_Zd_SVE_Zn_SVE_Zm_16(
            SSUBLT_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for SSUBLT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SSUBLTB_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ssubltb",
        aliases: &[],
        opcode: 0x45008c00,
        mask: 0xff20fc00,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::SSUBLTB_SVE_Zd_SVE_Zn_SVE_Zm_16(
            SSUBLTB_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for SSUBLTB_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SSUBW_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ssubw",
        aliases: &[],
        opcode: 0xe203000,
        mask: 0xff20fc00,
        class: InsnClass::ASIMDDIFF,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8H, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8H, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_4H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDDIFF(ASIMDDIFF::SSUBW_Vd_Vn_Vm(SSUBW_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for SSUBW_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SSUBW2_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ssubw2",
        aliases: &[],
        opcode: 0x4e203000,
        mask: 0xff20fc00,
        class: InsnClass::ASIMDDIFF,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8H, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8H, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_16B, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDDIFF(ASIMDDIFF::SSUBW2_Vd_Vn_Vm(SSUBW2_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for SSUBW2_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SSUBWB_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ssubwb",
        aliases: &[],
        opcode: 0x45005000,
        mask: 0xff20fc00,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::SSUBWB_SVE_Zd_SVE_Zn_SVE_Zm_16(
            SSUBWB_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for SSUBWB_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SSUBWT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ssubwt",
        aliases: &[],
        opcode: 0x45005400,
        mask: 0xff20fc00,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::SSUBWT_SVE_Zd_SVE_Zn_SVE_Zm_16(
            SSUBWT_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for SSUBWT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST1_LVt_SIMD_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st1",
        aliases: &[],
        opcode: 0xc000000,
        mask: 0xbfff0000,
        class: InsnClass::ASISDLSE,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::LVt,
                class: InsnOperandClass::SIMD_REGLIST,
                qualifiers: &[InsnOperandQualifier::V_8B],
                bit_fields: &[],
            },
            InsnOperand {
                kind: InsnOperandKind::SIMD_ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits()
                | InsnFlags::HAS_SIZEQ_FIELD.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDLSE(ASISDLSE::ST1_LVt_SIMD_ADDR_SIMPLE(
            ST1_LVt_SIMD_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for ST1_LVt_SIMD_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST1_LEt_SIMD_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st1",
        aliases: &[],
        opcode: 0xd000000,
        mask: 0xbfff2000,
        class: InsnClass::ASISDLSO,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::LEt,
                class: InsnOperandClass::SIMD_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[],
            },
            InsnOperand {
                kind: InsnOperandKind::SIMD_ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDLSO(ASISDLSO::ST1_LEt_SIMD_ADDR_SIMPLE(
            ST1_LEt_SIMD_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for ST1_LEt_SIMD_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST1_LVt_SIMD_ADDR_POST {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st1",
        aliases: &[],
        opcode: 0xc800000,
        mask: 0xbfe00000,
        class: InsnClass::ASISDLSEP,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::LVt,
                class: InsnOperandClass::SIMD_REGLIST,
                qualifiers: &[InsnOperandQualifier::V_8B],
                bit_fields: &[],
            },
            InsnOperand {
                kind: InsnOperandKind::SIMD_ADDR_POST,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits()
                | InsnFlags::HAS_SIZEQ_FIELD.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDLSEP(ASISDLSEP::ST1_LVt_SIMD_ADDR_POST(
            ST1_LVt_SIMD_ADDR_POST::from(bits),
        ))
    }
}
impl InsnOpcode for ST1_LVt_SIMD_ADDR_POST {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST1_LEt_SIMD_ADDR_POST {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st1",
        aliases: &[],
        opcode: 0xd800000,
        mask: 0xbfe02000,
        class: InsnClass::ASISDLSOP,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::LEt,
                class: InsnOperandClass::SIMD_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[],
            },
            InsnOperand {
                kind: InsnOperandKind::SIMD_ADDR_POST,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDLSOP(ASISDLSOP::ST1_LEt_SIMD_ADDR_POST(
            ST1_LEt_SIMD_ADDR_POST::from(bits),
        ))
    }
}
impl InsnOpcode for ST1_LEt_SIMD_ADDR_POST {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST1B_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st1b",
        aliases: &[],
        opcode: 0xa0200000,
        mask: 0xffe0e001,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn2,
                    lsb: 1,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RR,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::ST1B_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR(
            ST1B_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR::from(bits),
        ))
    }
}
impl InsnOpcode for ST1B_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST1B_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st1b",
        aliases: &[],
        opcode: 0xa0208000,
        mask: 0xffe0e003,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn4,
                    lsb: 2,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RR,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::ST1B_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR(
            ST1B_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR::from(bits),
        ))
    }
}
impl InsnOpcode for ST1B_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST1B_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_RR {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st1b",
        aliases: &[],
        opcode: 0xe0200000,
        mask: 0xffe00010,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_HV_idx_ldstr,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_size_22,
                        lsb: 22,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::index2,
                        lsb: 24,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_V,
                        lsb: 15,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm4_0,
                        lsb: 0,
                        width: 4,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RR,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::ST1B_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_RR(
            ST1B_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_RR::from(bits),
        ))
    }
}
impl InsnOpcode for ST1B_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_RR {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST1B_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_R {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st1b",
        aliases: &[],
        opcode: 0xe0200000,
        mask: 0xffe00010,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_HV_idx_ldstr,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_size_22,
                        lsb: 22,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::index2,
                        lsb: 24,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_V,
                        lsb: 15,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm4_0,
                        lsb: 0,
                        width: 4,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_R,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::ST1B_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_R(
            ST1B_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_R::from(bits),
        ))
    }
}
impl InsnOpcode for ST1B_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_R {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST1B_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st1b",
        aliases: &[],
        opcode: 0xa0600000,
        mask: 0xfff0e001,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn2,
                    lsb: 1,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4x2xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::ST1B_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL(
            ST1B_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL::from(bits),
        ))
    }
}
impl InsnOpcode for ST1B_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST1B_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st1b",
        aliases: &[],
        opcode: 0xa0608000,
        mask: 0xfff0e003,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn4,
                    lsb: 2,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4x4xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::ST1B_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL(
            ST1B_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL::from(bits),
        ))
    }
}
impl InsnOpcode for ST1B_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST1B_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st1b",
        aliases: &[],
        opcode: 0xa1200000,
        mask: 0xffe0e008,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Ztx2_STRIDED,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_ZtT,
                        lsb: 4,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zt3,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RR,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::ST1B_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR(
            ST1B_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR::from(bits),
        ))
    }
}
impl InsnOpcode for ST1B_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST1B_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st1b",
        aliases: &[],
        opcode: 0xa1208000,
        mask: 0xffe0e00c,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Ztx4_STRIDED,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_ZtT,
                        lsb: 4,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zt2,
                        lsb: 0,
                        width: 2,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RR,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::ST1B_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR(
            ST1B_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR::from(bits),
        ))
    }
}
impl InsnOpcode for ST1B_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST1B_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st1b",
        aliases: &[],
        opcode: 0xa1600000,
        mask: 0xfff0e008,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Ztx2_STRIDED,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_ZtT,
                        lsb: 4,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zt3,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4x2xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(
            SVE_MISC::ST1B_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL(
                ST1B_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL::from(bits),
            ),
        )
    }
}
impl InsnOpcode for ST1B_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST1B_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st1b",
        aliases: &[],
        opcode: 0xa1608000,
        mask: 0xfff0e00c,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Ztx4_STRIDED,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_ZtT,
                        lsb: 4,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zt2,
                        lsb: 0,
                        width: 2,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4x4xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(
            SVE_MISC::ST1B_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL(
                ST1B_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL::from(bits),
            ),
        )
    }
}
impl InsnOpcode for ST1B_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st1b",
        aliases: &[],
        opcode: 0xe4004000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RX,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::ST1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX(
            ST1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX::from(bits),
        ))
    }
}
impl InsnOpcode for ST1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST1B_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_RX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st1b",
        aliases: &[],
        opcode: 0xe4404000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RX,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::ST1B_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_RX(
            ST1B_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_RX::from(bits),
        ))
    }
}
impl InsnOpcode for ST1B_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_RX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_14 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st1b",
        aliases: &[],
        opcode: 0xe4008000,
        mask: 0xffe0a000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RZ_XTW_14,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zm_16,
                        lsb: 16,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_xs_14,
                        lsb: 14,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::ST1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_14(
            ST1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_14::from(bits),
        ))
    }
}
impl InsnOpcode for ST1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_14 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST1B_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_RZ_XTW_14 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st1b",
        aliases: &[],
        opcode: 0xe4408000,
        mask: 0xffe0a000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RZ_XTW_14,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zm_16,
                        lsb: 16,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_xs_14,
                        lsb: 14,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::ST1B_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_RZ_XTW_14(
            ST1B_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_RZ_XTW_14::from(bits),
        ))
    }
}
impl InsnOpcode for ST1B_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_RZ_XTW_14 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st1b",
        aliases: &[],
        opcode: 0xe400a000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RZ,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zm_16,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::ST1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ(
            ST1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ::from(bits),
        ))
    }
}
impl InsnOpcode for ST1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st1b",
        aliases: &[],
        opcode: 0xe440a000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_ZI_U5,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::ST1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5(
            ST1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5::from(bits),
        ))
    }
}
impl InsnOpcode for ST1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st1b",
        aliases: &[],
        opcode: 0xe400e000,
        mask: 0xfff0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::ST1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL(
            ST1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL::from(bits),
        ))
    }
}
impl InsnOpcode for ST1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST1B_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_RI_S4xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st1b",
        aliases: &[],
        opcode: 0xe440e000,
        mask: 0xfff0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::ST1B_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_RI_S4xVL(
            ST1B_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_RI_S4xVL::from(bits),
        ))
    }
}
impl InsnOpcode for ST1B_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_RI_S4xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST1B_SVE_ZtxN_S_H_SVE_Pg3_SVE_ADDR_RX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st1b",
        aliases: &[],
        opcode: 0xe4204000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RX,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::ST1B_SVE_ZtxN_S_H_SVE_Pg3_SVE_ADDR_RX(
            ST1B_SVE_ZtxN_S_H_SVE_Pg3_SVE_ADDR_RX::from(bits),
        ))
    }
}
impl InsnOpcode for ST1B_SVE_ZtxN_S_H_SVE_Pg3_SVE_ADDR_RX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST1B_SVE_ZtxN_S_D_SVE_Pg3_SVE_ADDR_RX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st1b",
        aliases: &[],
        opcode: 0xe4604000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RX,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::ST1B_SVE_ZtxN_S_D_SVE_Pg3_SVE_ADDR_RX(
            ST1B_SVE_ZtxN_S_D_SVE_Pg3_SVE_ADDR_RX::from(bits),
        ))
    }
}
impl InsnOpcode for ST1B_SVE_ZtxN_S_D_SVE_Pg3_SVE_ADDR_RX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST1B_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_ZI_U5 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st1b",
        aliases: &[],
        opcode: 0xe460a000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_ZI_U5,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::ST1B_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_ZI_U5(
            ST1B_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_ZI_U5::from(bits),
        ))
    }
}
impl InsnOpcode for ST1B_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_ZI_U5 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST1B_SVE_ZtxN_S_H_SVE_Pg3_SVE_ADDR_RI_S4xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st1b",
        aliases: &[],
        opcode: 0xe420e000,
        mask: 0xfff0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::ST1B_SVE_ZtxN_S_H_SVE_Pg3_SVE_ADDR_RI_S4xVL(
            ST1B_SVE_ZtxN_S_H_SVE_Pg3_SVE_ADDR_RI_S4xVL::from(bits),
        ))
    }
}
impl InsnOpcode for ST1B_SVE_ZtxN_S_H_SVE_Pg3_SVE_ADDR_RI_S4xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST1B_SVE_ZtxN_S_D_SVE_Pg3_SVE_ADDR_RI_S4xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st1b",
        aliases: &[],
        opcode: 0xe460e000,
        mask: 0xfff0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::ST1B_SVE_ZtxN_S_D_SVE_Pg3_SVE_ADDR_RI_S4xVL(
            ST1B_SVE_ZtxN_S_D_SVE_Pg3_SVE_ADDR_RI_S4xVL::from(bits),
        ))
    }
}
impl InsnOpcode for ST1B_SVE_ZtxN_S_D_SVE_Pg3_SVE_ADDR_RI_S4xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST1D_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR_LSL3 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st1d",
        aliases: &[],
        opcode: 0xa0206000,
        mask: 0xffe0e001,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn2,
                    lsb: 1,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RR_LSL3,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::ST1D_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR_LSL3(
            ST1D_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR_LSL3::from(bits),
        ))
    }
}
impl InsnOpcode for ST1D_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR_LSL3 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST1D_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR_LSL3 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st1d",
        aliases: &[],
        opcode: 0xa020e000,
        mask: 0xffe0e003,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn4,
                    lsb: 2,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RR_LSL3,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::ST1D_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR_LSL3(
            ST1D_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR_LSL3::from(bits),
        ))
    }
}
impl InsnOpcode for ST1D_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR_LSL3 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST1D_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st1d",
        aliases: &[],
        opcode: 0xa0606000,
        mask: 0xfff0e001,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn2,
                    lsb: 1,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4x2xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::ST1D_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL(
            ST1D_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL::from(bits),
        ))
    }
}
impl InsnOpcode for ST1D_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST1D_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st1d",
        aliases: &[],
        opcode: 0xa060e000,
        mask: 0xfff0e003,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn4,
                    lsb: 2,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4x4xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::ST1D_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL(
            ST1D_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL::from(bits),
        ))
    }
}
impl InsnOpcode for ST1D_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST1D_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_RR_LSL3 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st1d",
        aliases: &[],
        opcode: 0xe0e00000,
        mask: 0xffe00010,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_HV_idx_ldstr,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_size_22,
                        lsb: 22,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::index2,
                        lsb: 24,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_V,
                        lsb: 15,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm4_0,
                        lsb: 0,
                        width: 4,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RR_LSL3,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::ST1D_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_RR_LSL3(
            ST1D_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_RR_LSL3::from(bits),
        ))
    }
}
impl InsnOpcode for ST1D_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_RR_LSL3 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST1D_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_R {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st1d",
        aliases: &[],
        opcode: 0xe0e00000,
        mask: 0xffe00010,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_HV_idx_ldstr,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_size_22,
                        lsb: 22,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::index2,
                        lsb: 24,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_V,
                        lsb: 15,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm4_0,
                        lsb: 0,
                        width: 4,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_R,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::ST1D_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_R(
            ST1D_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_R::from(bits),
        ))
    }
}
impl InsnOpcode for ST1D_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_R {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST1D_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL3 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st1d",
        aliases: &[],
        opcode: 0xa1206000,
        mask: 0xffe0e008,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Ztx2_STRIDED,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_ZtT,
                        lsb: 4,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zt3,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RR_LSL3,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::ST1D_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL3(
            ST1D_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL3::from(bits),
        ))
    }
}
impl InsnOpcode for ST1D_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL3 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST1D_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL3 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st1d",
        aliases: &[],
        opcode: 0xa120e000,
        mask: 0xffe0e00c,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Ztx4_STRIDED,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_ZtT,
                        lsb: 4,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zt2,
                        lsb: 0,
                        width: 2,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RR_LSL3,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::ST1D_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL3(
            ST1D_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL3::from(bits),
        ))
    }
}
impl InsnOpcode for ST1D_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL3 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST1D_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st1d",
        aliases: &[],
        opcode: 0xa1606000,
        mask: 0xfff0e008,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Ztx2_STRIDED,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_ZtT,
                        lsb: 4,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zt3,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4x2xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(
            SVE_MISC::ST1D_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL(
                ST1D_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL::from(bits),
            ),
        )
    }
}
impl InsnOpcode for ST1D_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST1D_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st1d",
        aliases: &[],
        opcode: 0xa160e000,
        mask: 0xfff0e00c,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Ztx4_STRIDED,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_ZtT,
                        lsb: 4,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zt2,
                        lsb: 0,
                        width: 2,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4x4xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(
            SVE_MISC::ST1D_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL(
                ST1D_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL::from(bits),
            ),
        )
    }
}
impl InsnOpcode for ST1D_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL3 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st1d",
        aliases: &[],
        opcode: 0xe5e04000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RX_LSL3,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::ST1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL3(
            ST1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL3::from(bits),
        ))
    }
}
impl InsnOpcode for ST1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL3 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_14 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st1d",
        aliases: &[],
        opcode: 0xe5808000,
        mask: 0xffe0a000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RZ_XTW_14,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zm_16,
                        lsb: 16,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_xs_14,
                        lsb: 14,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::ST1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_14(
            ST1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_14::from(bits),
        ))
    }
}
impl InsnOpcode for ST1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_14 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st1d",
        aliases: &[],
        opcode: 0xe580a000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RZ,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zm_16,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::ST1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ(
            ST1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ::from(bits),
        ))
    }
}
impl InsnOpcode for ST1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x8 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st1d",
        aliases: &[],
        opcode: 0xe5c0a000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_ZI_U5x8,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::ST1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x8(
            ST1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x8::from(bits),
        ))
    }
}
impl InsnOpcode for ST1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x8 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW3_14 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st1d",
        aliases: &[],
        opcode: 0xe5a08000,
        mask: 0xffe0a000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RZ_XTW3_14,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zm_16,
                        lsb: 16,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_xs_14,
                        lsb: 14,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::ST1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW3_14(
            ST1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW3_14::from(bits),
        ))
    }
}
impl InsnOpcode for ST1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW3_14 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL3 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st1d",
        aliases: &[],
        opcode: 0xe5a0a000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RZ_LSL3,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zm_16,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::ST1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL3(
            ST1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL3::from(bits),
        ))
    }
}
impl InsnOpcode for ST1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL3 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st1d",
        aliases: &[],
        opcode: 0xe5e0e000,
        mask: 0xfff0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::ST1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL(
            ST1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL::from(bits),
        ))
    }
}
impl InsnOpcode for ST1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST1H_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR_LSL1 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st1h",
        aliases: &[],
        opcode: 0xa0202000,
        mask: 0xffe0e001,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn2,
                    lsb: 1,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RR_LSL1,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::ST1H_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR_LSL1(
            ST1H_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR_LSL1::from(bits),
        ))
    }
}
impl InsnOpcode for ST1H_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR_LSL1 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST1H_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR_LSL1 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st1h",
        aliases: &[],
        opcode: 0xa020a000,
        mask: 0xffe0e003,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn4,
                    lsb: 2,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RR_LSL1,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::ST1H_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR_LSL1(
            ST1H_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR_LSL1::from(bits),
        ))
    }
}
impl InsnOpcode for ST1H_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR_LSL1 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST1H_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st1h",
        aliases: &[],
        opcode: 0xa0602000,
        mask: 0xfff0e001,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn2,
                    lsb: 1,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4x2xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::ST1H_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL(
            ST1H_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL::from(bits),
        ))
    }
}
impl InsnOpcode for ST1H_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST1H_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st1h",
        aliases: &[],
        opcode: 0xa060a000,
        mask: 0xfff0e003,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn4,
                    lsb: 2,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4x4xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::ST1H_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL(
            ST1H_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL::from(bits),
        ))
    }
}
impl InsnOpcode for ST1H_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST1H_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_RR_LSL1 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st1h",
        aliases: &[],
        opcode: 0xe0600000,
        mask: 0xffe00010,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_HV_idx_ldstr,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_size_22,
                        lsb: 22,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::index2,
                        lsb: 24,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_V,
                        lsb: 15,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm4_0,
                        lsb: 0,
                        width: 4,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RR_LSL1,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::ST1H_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_RR_LSL1(
            ST1H_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_RR_LSL1::from(bits),
        ))
    }
}
impl InsnOpcode for ST1H_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_RR_LSL1 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST1H_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_R {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st1h",
        aliases: &[],
        opcode: 0xe0600000,
        mask: 0xffe00010,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_HV_idx_ldstr,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_size_22,
                        lsb: 22,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::index2,
                        lsb: 24,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_V,
                        lsb: 15,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm4_0,
                        lsb: 0,
                        width: 4,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_R,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::ST1H_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_R(
            ST1H_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_R::from(bits),
        ))
    }
}
impl InsnOpcode for ST1H_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_R {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST1H_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL1 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st1h",
        aliases: &[],
        opcode: 0xa1202000,
        mask: 0xffe0e008,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Ztx2_STRIDED,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_ZtT,
                        lsb: 4,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zt3,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RR_LSL1,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::ST1H_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL1(
            ST1H_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL1::from(bits),
        ))
    }
}
impl InsnOpcode for ST1H_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL1 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST1H_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL1 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st1h",
        aliases: &[],
        opcode: 0xa120a000,
        mask: 0xffe0e00c,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Ztx4_STRIDED,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_ZtT,
                        lsb: 4,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zt2,
                        lsb: 0,
                        width: 2,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RR_LSL1,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::ST1H_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL1(
            ST1H_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL1::from(bits),
        ))
    }
}
impl InsnOpcode for ST1H_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL1 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST1H_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st1h",
        aliases: &[],
        opcode: 0xa1602000,
        mask: 0xfff0e008,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Ztx2_STRIDED,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_ZtT,
                        lsb: 4,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zt3,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4x2xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(
            SVE_MISC::ST1H_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL(
                ST1H_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL::from(bits),
            ),
        )
    }
}
impl InsnOpcode for ST1H_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST1H_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st1h",
        aliases: &[],
        opcode: 0xa160a000,
        mask: 0xfff0e00c,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Ztx4_STRIDED,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_ZtT,
                        lsb: 4,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zt2,
                        lsb: 0,
                        width: 2,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4x4xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(
            SVE_MISC::ST1H_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL(
                ST1H_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL::from(bits),
            ),
        )
    }
}
impl InsnOpcode for ST1H_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st1h",
        aliases: &[],
        opcode: 0xe4c04000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RX_LSL1,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::ST1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1(
            ST1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1::from(bits),
        ))
    }
}
impl InsnOpcode for ST1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_14 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st1h",
        aliases: &[],
        opcode: 0xe4808000,
        mask: 0xffe0a000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RZ_XTW_14,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zm_16,
                        lsb: 16,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_xs_14,
                        lsb: 14,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::ST1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_14(
            ST1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_14::from(bits),
        ))
    }
}
impl InsnOpcode for ST1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_14 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST1H_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_RZ_XTW_14 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st1h",
        aliases: &[],
        opcode: 0xe4c08000,
        mask: 0xffe0a000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RZ_XTW_14,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zm_16,
                        lsb: 16,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_xs_14,
                        lsb: 14,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::ST1H_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_RZ_XTW_14(
            ST1H_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_RZ_XTW_14::from(bits),
        ))
    }
}
impl InsnOpcode for ST1H_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_RZ_XTW_14 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st1h",
        aliases: &[],
        opcode: 0xe480a000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RZ,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zm_16,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::ST1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ(
            ST1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ::from(bits),
        ))
    }
}
impl InsnOpcode for ST1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st1h",
        aliases: &[],
        opcode: 0xe4c0a000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_ZI_U5x2,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::ST1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x2(
            ST1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x2::from(bits),
        ))
    }
}
impl InsnOpcode for ST1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st1h",
        aliases: &[],
        opcode: 0xe4c0e000,
        mask: 0xfff0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::ST1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL(
            ST1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL::from(bits),
        ))
    }
}
impl InsnOpcode for ST1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST1H_SVE_ZtxN_S_H_SVE_Pg3_SVE_ADDR_RX_LSL1 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st1h",
        aliases: &[],
        opcode: 0xe4a04000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RX_LSL1,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::ST1H_SVE_ZtxN_S_H_SVE_Pg3_SVE_ADDR_RX_LSL1(
            ST1H_SVE_ZtxN_S_H_SVE_Pg3_SVE_ADDR_RX_LSL1::from(bits),
        ))
    }
}
impl InsnOpcode for ST1H_SVE_ZtxN_S_H_SVE_Pg3_SVE_ADDR_RX_LSL1 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST1H_SVE_ZtxN_S_D_SVE_Pg3_SVE_ADDR_RX_LSL1 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st1h",
        aliases: &[],
        opcode: 0xe4e04000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RX_LSL1,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::ST1H_SVE_ZtxN_S_D_SVE_Pg3_SVE_ADDR_RX_LSL1(
            ST1H_SVE_ZtxN_S_D_SVE_Pg3_SVE_ADDR_RX_LSL1::from(bits),
        ))
    }
}
impl InsnOpcode for ST1H_SVE_ZtxN_S_D_SVE_Pg3_SVE_ADDR_RX_LSL1 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW1_14 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st1h",
        aliases: &[],
        opcode: 0xe4a08000,
        mask: 0xffe0a000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RZ_XTW1_14,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zm_16,
                        lsb: 16,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_xs_14,
                        lsb: 14,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::ST1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW1_14(
            ST1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW1_14::from(bits),
        ))
    }
}
impl InsnOpcode for ST1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW1_14 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST1H_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_RZ_XTW1_14 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st1h",
        aliases: &[],
        opcode: 0xe4e08000,
        mask: 0xffe0a000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RZ_XTW1_14,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zm_16,
                        lsb: 16,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_xs_14,
                        lsb: 14,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::ST1H_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_RZ_XTW1_14(
            ST1H_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_RZ_XTW1_14::from(bits),
        ))
    }
}
impl InsnOpcode for ST1H_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_RZ_XTW1_14 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL1 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st1h",
        aliases: &[],
        opcode: 0xe4a0a000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RZ_LSL1,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zm_16,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::ST1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL1(
            ST1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL1::from(bits),
        ))
    }
}
impl InsnOpcode for ST1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL1 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST1H_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_ZI_U5x2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st1h",
        aliases: &[],
        opcode: 0xe4e0a000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_ZI_U5x2,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::ST1H_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_ZI_U5x2(
            ST1H_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_ZI_U5x2::from(bits),
        ))
    }
}
impl InsnOpcode for ST1H_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_ZI_U5x2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST1H_SVE_ZtxN_S_H_SVE_Pg3_SVE_ADDR_RI_S4xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st1h",
        aliases: &[],
        opcode: 0xe4a0e000,
        mask: 0xfff0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::ST1H_SVE_ZtxN_S_H_SVE_Pg3_SVE_ADDR_RI_S4xVL(
            ST1H_SVE_ZtxN_S_H_SVE_Pg3_SVE_ADDR_RI_S4xVL::from(bits),
        ))
    }
}
impl InsnOpcode for ST1H_SVE_ZtxN_S_H_SVE_Pg3_SVE_ADDR_RI_S4xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST1H_SVE_ZtxN_S_D_SVE_Pg3_SVE_ADDR_RI_S4xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st1h",
        aliases: &[],
        opcode: 0xe4e0e000,
        mask: 0xfff0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::ST1H_SVE_ZtxN_S_D_SVE_Pg3_SVE_ADDR_RI_S4xVL(
            ST1H_SVE_ZtxN_S_D_SVE_Pg3_SVE_ADDR_RI_S4xVL::from(bits),
        ))
    }
}
impl InsnOpcode for ST1H_SVE_ZtxN_S_D_SVE_Pg3_SVE_ADDR_RI_S4xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST1Q_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_RR_LSL4 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st1q",
        aliases: &[],
        opcode: 0xe1e00000,
        mask: 0xffe00010,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_HV_idx_ldstr,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_Q],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_size_22,
                        lsb: 22,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::index2,
                        lsb: 24,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_V,
                        lsb: 15,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm4_0,
                        lsb: 0,
                        width: 4,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RR_LSL4,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::ST1Q_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_RR_LSL4(
            ST1Q_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_RR_LSL4::from(bits),
        ))
    }
}
impl InsnOpcode for ST1Q_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_RR_LSL4 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST1Q_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_R {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st1q",
        aliases: &[],
        opcode: 0xe1e00000,
        mask: 0xffe00010,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_HV_idx_ldstr,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_Q],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_size_22,
                        lsb: 22,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::index2,
                        lsb: 24,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_V,
                        lsb: 15,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm4_0,
                        lsb: 0,
                        width: 4,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_R,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::ST1Q_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_R(
            ST1Q_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_R::from(bits),
        ))
    }
}
impl InsnOpcode for ST1Q_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_R {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST1Q_SVE_Zt_SVE_Pg3_SVE_ADDR_ZX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st1q",
        aliases: &[],
        opcode: 0xe4202000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE2P1,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zt,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_Q],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_ZX,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::ST1Q_SVE_Zt_SVE_Pg3_SVE_ADDR_ZX(
            ST1Q_SVE_Zt_SVE_Pg3_SVE_ADDR_ZX::from(bits),
        ))
    }
}
impl InsnOpcode for ST1Q_SVE_Zt_SVE_Pg3_SVE_ADDR_ZX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST1W_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR_LSL2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st1w",
        aliases: &[],
        opcode: 0xa0204000,
        mask: 0xffe0e001,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn2,
                    lsb: 1,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RR_LSL2,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::ST1W_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR_LSL2(
            ST1W_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR_LSL2::from(bits),
        ))
    }
}
impl InsnOpcode for ST1W_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR_LSL2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST1W_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR_LSL2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st1w",
        aliases: &[],
        opcode: 0xa020c000,
        mask: 0xffe0e003,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn4,
                    lsb: 2,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RR_LSL2,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::ST1W_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR_LSL2(
            ST1W_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR_LSL2::from(bits),
        ))
    }
}
impl InsnOpcode for ST1W_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR_LSL2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST1W_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_RR_LSL2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st1w",
        aliases: &[],
        opcode: 0xe0a00000,
        mask: 0xffe00010,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_HV_idx_ldstr,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_size_22,
                        lsb: 22,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::index2,
                        lsb: 24,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_V,
                        lsb: 15,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm4_0,
                        lsb: 0,
                        width: 4,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RR_LSL2,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::ST1W_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_RR_LSL2(
            ST1W_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_RR_LSL2::from(bits),
        ))
    }
}
impl InsnOpcode for ST1W_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_RR_LSL2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST1W_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_R {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st1w",
        aliases: &[],
        opcode: 0xe0a00000,
        mask: 0xffe00010,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_HV_idx_ldstr,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_size_22,
                        lsb: 22,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::index2,
                        lsb: 24,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_V,
                        lsb: 15,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm4_0,
                        lsb: 0,
                        width: 4,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_R,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::ST1W_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_R(
            ST1W_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_R::from(bits),
        ))
    }
}
impl InsnOpcode for ST1W_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_R {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST1W_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st1w",
        aliases: &[],
        opcode: 0xa0604000,
        mask: 0xfff0e001,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn2,
                    lsb: 1,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4x2xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::ST1W_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL(
            ST1W_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL::from(bits),
        ))
    }
}
impl InsnOpcode for ST1W_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST1W_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st1w",
        aliases: &[],
        opcode: 0xa060c000,
        mask: 0xfff0e003,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn4,
                    lsb: 2,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4x4xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::ST1W_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL(
            ST1W_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL::from(bits),
        ))
    }
}
impl InsnOpcode for ST1W_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST1W_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st1w",
        aliases: &[],
        opcode: 0xa1204000,
        mask: 0xffe0e008,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Ztx2_STRIDED,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_ZtT,
                        lsb: 4,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zt3,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RR_LSL2,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::ST1W_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL2(
            ST1W_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL2::from(bits),
        ))
    }
}
impl InsnOpcode for ST1W_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST1W_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st1w",
        aliases: &[],
        opcode: 0xa120c000,
        mask: 0xffe0e00c,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Ztx4_STRIDED,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_ZtT,
                        lsb: 4,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zt2,
                        lsb: 0,
                        width: 2,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RR_LSL2,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::ST1W_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL2(
            ST1W_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL2::from(bits),
        ))
    }
}
impl InsnOpcode for ST1W_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST1W_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st1w",
        aliases: &[],
        opcode: 0xa1604000,
        mask: 0xfff0e008,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Ztx2_STRIDED,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_ZtT,
                        lsb: 4,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zt3,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4x2xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(
            SVE_MISC::ST1W_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL(
                ST1W_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL::from(bits),
            ),
        )
    }
}
impl InsnOpcode for ST1W_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST1W_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st1w",
        aliases: &[],
        opcode: 0xa160c000,
        mask: 0xfff0e00c,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Ztx4_STRIDED,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_ZtT,
                        lsb: 4,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zt2,
                        lsb: 0,
                        width: 2,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4x4xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(
            SVE_MISC::ST1W_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL(
                ST1W_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL::from(bits),
            ),
        )
    }
}
impl InsnOpcode for ST1W_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st1w",
        aliases: &[],
        opcode: 0xe5404000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RX_LSL2,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::ST1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2(
            ST1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2::from(bits),
        ))
    }
}
impl InsnOpcode for ST1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST1W_SVE_ZtxN_S_D_SVE_Pg3_SVE_ADDR_RX_LSL2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st1w",
        aliases: &[],
        opcode: 0xe5604000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RX_LSL2,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::ST1W_SVE_ZtxN_S_D_SVE_Pg3_SVE_ADDR_RX_LSL2(
            ST1W_SVE_ZtxN_S_D_SVE_Pg3_SVE_ADDR_RX_LSL2::from(bits),
        ))
    }
}
impl InsnOpcode for ST1W_SVE_ZtxN_S_D_SVE_Pg3_SVE_ADDR_RX_LSL2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_14 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st1w",
        aliases: &[],
        opcode: 0xe5008000,
        mask: 0xffe0a000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RZ_XTW_14,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zm_16,
                        lsb: 16,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_xs_14,
                        lsb: 14,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::ST1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_14(
            ST1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_14::from(bits),
        ))
    }
}
impl InsnOpcode for ST1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_14 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST1W_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_RZ_XTW_14 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st1w",
        aliases: &[],
        opcode: 0xe5408000,
        mask: 0xffe0a000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RZ_XTW_14,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zm_16,
                        lsb: 16,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_xs_14,
                        lsb: 14,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::ST1W_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_RZ_XTW_14(
            ST1W_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_RZ_XTW_14::from(bits),
        ))
    }
}
impl InsnOpcode for ST1W_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_RZ_XTW_14 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st1w",
        aliases: &[],
        opcode: 0xe500a000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RZ,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zm_16,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::ST1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ(
            ST1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ::from(bits),
        ))
    }
}
impl InsnOpcode for ST1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x4 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st1w",
        aliases: &[],
        opcode: 0xe540a000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_ZI_U5x4,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::ST1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x4(
            ST1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x4::from(bits),
        ))
    }
}
impl InsnOpcode for ST1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x4 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st1w",
        aliases: &[],
        opcode: 0xe540e000,
        mask: 0xfff0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::ST1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL(
            ST1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL::from(bits),
        ))
    }
}
impl InsnOpcode for ST1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW2_14 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st1w",
        aliases: &[],
        opcode: 0xe5208000,
        mask: 0xffe0a000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RZ_XTW2_14,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zm_16,
                        lsb: 16,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_xs_14,
                        lsb: 14,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::ST1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW2_14(
            ST1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW2_14::from(bits),
        ))
    }
}
impl InsnOpcode for ST1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW2_14 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST1W_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_RZ_XTW2_14 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st1w",
        aliases: &[],
        opcode: 0xe5608000,
        mask: 0xffe0a000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RZ_XTW2_14,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zm_16,
                        lsb: 16,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_xs_14,
                        lsb: 14,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::ST1W_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_RZ_XTW2_14(
            ST1W_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_RZ_XTW2_14::from(bits),
        ))
    }
}
impl InsnOpcode for ST1W_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_RZ_XTW2_14 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st1w",
        aliases: &[],
        opcode: 0xe520a000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RZ_LSL2,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zm_16,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::ST1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL2(
            ST1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL2::from(bits),
        ))
    }
}
impl InsnOpcode for ST1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST1W_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_ZI_U5x4 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st1w",
        aliases: &[],
        opcode: 0xe560a000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_ZI_U5x4,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::ST1W_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_ZI_U5x4(
            ST1W_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_ZI_U5x4::from(bits),
        ))
    }
}
impl InsnOpcode for ST1W_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_ZI_U5x4 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST1W_SVE_ZtxN_S_D_SVE_Pg3_SVE_ADDR_RI_S4xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st1w",
        aliases: &[],
        opcode: 0xe560e000,
        mask: 0xfff0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::ST1W_SVE_ZtxN_S_D_SVE_Pg3_SVE_ADDR_RI_S4xVL(
            ST1W_SVE_ZtxN_S_D_SVE_Pg3_SVE_ADDR_RI_S4xVL::from(bits),
        ))
    }
}
impl InsnOpcode for ST1W_SVE_ZtxN_S_D_SVE_Pg3_SVE_ADDR_RI_S4xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST2_LVt_SIMD_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st2",
        aliases: &[],
        opcode: 0xc000000,
        mask: 0xbfff0000,
        class: InsnClass::ASISDLSE,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::LVt,
                class: InsnOperandClass::SIMD_REGLIST,
                qualifiers: &[InsnOperandQualifier::V_8B],
                bit_fields: &[],
            },
            InsnOperand {
                kind: InsnOperandKind::SIMD_ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits()
                | InsnFlags::HAS_SIZEQ_FIELD.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDLSE(ASISDLSE::ST2_LVt_SIMD_ADDR_SIMPLE(
            ST2_LVt_SIMD_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for ST2_LVt_SIMD_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST2_LEt_SIMD_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st2",
        aliases: &[],
        opcode: 0xd200000,
        mask: 0xbfff2000,
        class: InsnClass::ASISDLSO,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::LEt,
                class: InsnOperandClass::SIMD_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[],
            },
            InsnOperand {
                kind: InsnOperandKind::SIMD_ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDLSO(ASISDLSO::ST2_LEt_SIMD_ADDR_SIMPLE(
            ST2_LEt_SIMD_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for ST2_LEt_SIMD_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST2_LVt_SIMD_ADDR_POST {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st2",
        aliases: &[],
        opcode: 0xc800000,
        mask: 0xbfe00000,
        class: InsnClass::ASISDLSEP,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::LVt,
                class: InsnOperandClass::SIMD_REGLIST,
                qualifiers: &[InsnOperandQualifier::V_8B],
                bit_fields: &[],
            },
            InsnOperand {
                kind: InsnOperandKind::SIMD_ADDR_POST,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits()
                | InsnFlags::HAS_SIZEQ_FIELD.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDLSEP(ASISDLSEP::ST2_LVt_SIMD_ADDR_POST(
            ST2_LVt_SIMD_ADDR_POST::from(bits),
        ))
    }
}
impl InsnOpcode for ST2_LVt_SIMD_ADDR_POST {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST2_LEt_SIMD_ADDR_POST {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st2",
        aliases: &[],
        opcode: 0xda00000,
        mask: 0xbfe02000,
        class: InsnClass::ASISDLSOP,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::LEt,
                class: InsnOperandClass::SIMD_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[],
            },
            InsnOperand {
                kind: InsnOperandKind::SIMD_ADDR_POST,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDLSOP(ASISDLSOP::ST2_LEt_SIMD_ADDR_POST(
            ST2_LEt_SIMD_ADDR_POST::from(bits),
        ))
    }
}
impl InsnOpcode for ST2_LEt_SIMD_ADDR_POST {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST2B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st2b",
        aliases: &[],
        opcode: 0xe4206000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RX,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::ST2B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX(
            ST2B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX::from(bits),
        ))
    }
}
impl InsnOpcode for ST2B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST2B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x2xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st2b",
        aliases: &[],
        opcode: 0xe430e000,
        mask: 0xfff0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4x2xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::ST2B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x2xVL(
            ST2B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x2xVL::from(bits),
        ))
    }
}
impl InsnOpcode for ST2B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x2xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST2D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL3 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st2d",
        aliases: &[],
        opcode: 0xe5a06000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RX_LSL3,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::ST2D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL3(
            ST2D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL3::from(bits),
        ))
    }
}
impl InsnOpcode for ST2D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL3 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST2D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x2xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st2d",
        aliases: &[],
        opcode: 0xe5b0e000,
        mask: 0xfff0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4x2xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::ST2D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x2xVL(
            ST2D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x2xVL::from(bits),
        ))
    }
}
impl InsnOpcode for ST2D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x2xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST2G_Rt_SP_ADDR_SIMM13 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st2g",
        aliases: &[],
        opcode: 0xd9a00800,
        mask: 0xffe00c00,
        class: InsnClass::LDST_UNSCALED,
        feature_set: InsnFeatureSet::MEMTAG,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt_SP,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMM13,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::imm_tag],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::imm9,
                        lsb: 12,
                        width: 9,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::index,
                        lsb: 11,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDST_UNSCALED(LDST_UNSCALED::ST2G_Rt_SP_ADDR_SIMM13(
            ST2G_Rt_SP_ADDR_SIMM13::from(bits),
        ))
    }
}
impl InsnOpcode for ST2G_Rt_SP_ADDR_SIMM13 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST2G_Rt_SP_X_ADDR_SIMM13_imm_tag {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st2g",
        aliases: &[],
        opcode: 0xd9a00400,
        mask: 0xffe00400,
        class: InsnClass::LDST_IMM9,
        feature_set: InsnFeatureSet::MEMTAG,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt_SP,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMM13,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::imm_tag],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::imm9,
                        lsb: 12,
                        width: 9,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::index,
                        lsb: 11,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDST_IMM9(LDST_IMM9::ST2G_Rt_SP_X_ADDR_SIMM13_imm_tag(
            ST2G_Rt_SP_X_ADDR_SIMM13_imm_tag::from(bits),
        ))
    }
}
impl InsnOpcode for ST2G_Rt_SP_X_ADDR_SIMM13_imm_tag {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST2H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st2h",
        aliases: &[],
        opcode: 0xe4a06000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RX_LSL1,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::ST2H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1(
            ST2H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1::from(bits),
        ))
    }
}
impl InsnOpcode for ST2H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST2H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x2xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st2h",
        aliases: &[],
        opcode: 0xe4b0e000,
        mask: 0xfff0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4x2xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::ST2H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x2xVL(
            ST2H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x2xVL::from(bits),
        ))
    }
}
impl InsnOpcode for ST2H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x2xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST2Q_SME_Zt2_SVE_Pg3_SVE_ADDR_RI_S4x2xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st2q",
        aliases: &[],
        opcode: 0xe4400000,
        mask: 0xfff0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE2P1,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zt2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_Q],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4x2xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::ST2Q_SME_Zt2_SVE_Pg3_SVE_ADDR_RI_S4x2xVL(
            ST2Q_SME_Zt2_SVE_Pg3_SVE_ADDR_RI_S4x2xVL::from(bits),
        ))
    }
}
impl InsnOpcode for ST2Q_SME_Zt2_SVE_Pg3_SVE_ADDR_RI_S4x2xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST2Q_SME_Zt2_SVE_Pg3_SVE_ADDR_RR_LSL4 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st2q",
        aliases: &[],
        opcode: 0xe4600000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE2P1,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zt2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_Q],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RR_LSL4,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::ST2Q_SME_Zt2_SVE_Pg3_SVE_ADDR_RR_LSL4(
            ST2Q_SME_Zt2_SVE_Pg3_SVE_ADDR_RR_LSL4::from(bits),
        ))
    }
}
impl InsnOpcode for ST2Q_SME_Zt2_SVE_Pg3_SVE_ADDR_RR_LSL4 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST2W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st2w",
        aliases: &[],
        opcode: 0xe5206000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RX_LSL2,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::ST2W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2(
            ST2W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2::from(bits),
        ))
    }
}
impl InsnOpcode for ST2W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST2W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x2xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st2w",
        aliases: &[],
        opcode: 0xe530e000,
        mask: 0xfff0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4x2xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::ST2W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x2xVL(
            ST2W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x2xVL::from(bits),
        ))
    }
}
impl InsnOpcode for ST2W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x2xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST3_LVt_SIMD_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st3",
        aliases: &[],
        opcode: 0xc000000,
        mask: 0xbfff0000,
        class: InsnClass::ASISDLSE,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::LVt,
                class: InsnOperandClass::SIMD_REGLIST,
                qualifiers: &[InsnOperandQualifier::V_8B],
                bit_fields: &[],
            },
            InsnOperand {
                kind: InsnOperandKind::SIMD_ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits()
                | InsnFlags::HAS_SIZEQ_FIELD.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDLSE(ASISDLSE::ST3_LVt_SIMD_ADDR_SIMPLE(
            ST3_LVt_SIMD_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for ST3_LVt_SIMD_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST3_LEt_SIMD_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st3",
        aliases: &[],
        opcode: 0xd002000,
        mask: 0xbfff2000,
        class: InsnClass::ASISDLSO,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::LEt,
                class: InsnOperandClass::SIMD_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[],
            },
            InsnOperand {
                kind: InsnOperandKind::SIMD_ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDLSO(ASISDLSO::ST3_LEt_SIMD_ADDR_SIMPLE(
            ST3_LEt_SIMD_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for ST3_LEt_SIMD_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST3_LVt_SIMD_ADDR_POST {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st3",
        aliases: &[],
        opcode: 0xc800000,
        mask: 0xbfe00000,
        class: InsnClass::ASISDLSEP,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::LVt,
                class: InsnOperandClass::SIMD_REGLIST,
                qualifiers: &[InsnOperandQualifier::V_8B],
                bit_fields: &[],
            },
            InsnOperand {
                kind: InsnOperandKind::SIMD_ADDR_POST,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits()
                | InsnFlags::HAS_SIZEQ_FIELD.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDLSEP(ASISDLSEP::ST3_LVt_SIMD_ADDR_POST(
            ST3_LVt_SIMD_ADDR_POST::from(bits),
        ))
    }
}
impl InsnOpcode for ST3_LVt_SIMD_ADDR_POST {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST3_LEt_SIMD_ADDR_POST {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st3",
        aliases: &[],
        opcode: 0xd802000,
        mask: 0xbfe02000,
        class: InsnClass::ASISDLSOP,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::LEt,
                class: InsnOperandClass::SIMD_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[],
            },
            InsnOperand {
                kind: InsnOperandKind::SIMD_ADDR_POST,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDLSOP(ASISDLSOP::ST3_LEt_SIMD_ADDR_POST(
            ST3_LEt_SIMD_ADDR_POST::from(bits),
        ))
    }
}
impl InsnOpcode for ST3_LEt_SIMD_ADDR_POST {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST3B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st3b",
        aliases: &[],
        opcode: 0xe4406000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RX,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::ST3B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX(
            ST3B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX::from(bits),
        ))
    }
}
impl InsnOpcode for ST3B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST3B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x3xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st3b",
        aliases: &[],
        opcode: 0xe450e000,
        mask: 0xfff0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4x3xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::ST3B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x3xVL(
            ST3B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x3xVL::from(bits),
        ))
    }
}
impl InsnOpcode for ST3B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x3xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST3D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL3 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st3d",
        aliases: &[],
        opcode: 0xe5c06000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RX_LSL3,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::ST3D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL3(
            ST3D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL3::from(bits),
        ))
    }
}
impl InsnOpcode for ST3D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL3 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST3D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x3xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st3d",
        aliases: &[],
        opcode: 0xe5d0e000,
        mask: 0xfff0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4x3xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::ST3D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x3xVL(
            ST3D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x3xVL::from(bits),
        ))
    }
}
impl InsnOpcode for ST3D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x3xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST3H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st3h",
        aliases: &[],
        opcode: 0xe4c06000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RX_LSL1,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::ST3H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1(
            ST3H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1::from(bits),
        ))
    }
}
impl InsnOpcode for ST3H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST3H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x3xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st3h",
        aliases: &[],
        opcode: 0xe4d0e000,
        mask: 0xfff0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4x3xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::ST3H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x3xVL(
            ST3H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x3xVL::from(bits),
        ))
    }
}
impl InsnOpcode for ST3H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x3xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST3Q_SME_Zt3_SVE_Pg3_SVE_ADDR_RI_S4x2xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st3q",
        aliases: &[],
        opcode: 0xe4800000,
        mask: 0xfff0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE2P1,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zt3,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_Q],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4x2xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::ST3Q_SME_Zt3_SVE_Pg3_SVE_ADDR_RI_S4x2xVL(
            ST3Q_SME_Zt3_SVE_Pg3_SVE_ADDR_RI_S4x2xVL::from(bits),
        ))
    }
}
impl InsnOpcode for ST3Q_SME_Zt3_SVE_Pg3_SVE_ADDR_RI_S4x2xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST3Q_SME_Zt3_SVE_Pg3_SVE_ADDR_RR_LSL4 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st3q",
        aliases: &[],
        opcode: 0xe4a00000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE2P1,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zt3,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_Q],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RR_LSL4,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::ST3Q_SME_Zt3_SVE_Pg3_SVE_ADDR_RR_LSL4(
            ST3Q_SME_Zt3_SVE_Pg3_SVE_ADDR_RR_LSL4::from(bits),
        ))
    }
}
impl InsnOpcode for ST3Q_SME_Zt3_SVE_Pg3_SVE_ADDR_RR_LSL4 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST3W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st3w",
        aliases: &[],
        opcode: 0xe5406000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RX_LSL2,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::ST3W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2(
            ST3W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2::from(bits),
        ))
    }
}
impl InsnOpcode for ST3W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST3W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x3xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st3w",
        aliases: &[],
        opcode: 0xe550e000,
        mask: 0xfff0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4x3xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::ST3W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x3xVL(
            ST3W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x3xVL::from(bits),
        ))
    }
}
impl InsnOpcode for ST3W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x3xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST4_LVt_SIMD_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st4",
        aliases: &[],
        opcode: 0xc000000,
        mask: 0xbfff0000,
        class: InsnClass::ASISDLSE,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::LVt,
                class: InsnOperandClass::SIMD_REGLIST,
                qualifiers: &[InsnOperandQualifier::V_8B],
                bit_fields: &[],
            },
            InsnOperand {
                kind: InsnOperandKind::SIMD_ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_4.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits()
                | InsnFlags::HAS_SIZEQ_FIELD.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDLSE(ASISDLSE::ST4_LVt_SIMD_ADDR_SIMPLE(
            ST4_LVt_SIMD_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for ST4_LVt_SIMD_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST4_LEt_SIMD_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st4",
        aliases: &[],
        opcode: 0xd202000,
        mask: 0xbfff2000,
        class: InsnClass::ASISDLSO,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::LEt,
                class: InsnOperandClass::SIMD_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[],
            },
            InsnOperand {
                kind: InsnOperandKind::SIMD_ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_4.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDLSO(ASISDLSO::ST4_LEt_SIMD_ADDR_SIMPLE(
            ST4_LEt_SIMD_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for ST4_LEt_SIMD_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST4_LVt_SIMD_ADDR_POST {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st4",
        aliases: &[],
        opcode: 0xc800000,
        mask: 0xbfe00000,
        class: InsnClass::ASISDLSEP,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::LVt,
                class: InsnOperandClass::SIMD_REGLIST,
                qualifiers: &[InsnOperandQualifier::V_8B],
                bit_fields: &[],
            },
            InsnOperand {
                kind: InsnOperandKind::SIMD_ADDR_POST,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_4.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits()
                | InsnFlags::HAS_SIZEQ_FIELD.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDLSEP(ASISDLSEP::ST4_LVt_SIMD_ADDR_POST(
            ST4_LVt_SIMD_ADDR_POST::from(bits),
        ))
    }
}
impl InsnOpcode for ST4_LVt_SIMD_ADDR_POST {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST4_LEt_SIMD_ADDR_POST {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st4",
        aliases: &[],
        opcode: 0xda02000,
        mask: 0xbfe02000,
        class: InsnClass::ASISDLSOP,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::LEt,
                class: InsnOperandClass::SIMD_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[],
            },
            InsnOperand {
                kind: InsnOperandKind::SIMD_ADDR_POST,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_4.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDLSOP(ASISDLSOP::ST4_LEt_SIMD_ADDR_POST(
            ST4_LEt_SIMD_ADDR_POST::from(bits),
        ))
    }
}
impl InsnOpcode for ST4_LEt_SIMD_ADDR_POST {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST4B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st4b",
        aliases: &[],
        opcode: 0xe4606000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RX,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_4.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::ST4B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX(
            ST4B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX::from(bits),
        ))
    }
}
impl InsnOpcode for ST4B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST4B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x4xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st4b",
        aliases: &[],
        opcode: 0xe470e000,
        mask: 0xfff0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4x4xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_4.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::ST4B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x4xVL(
            ST4B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x4xVL::from(bits),
        ))
    }
}
impl InsnOpcode for ST4B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x4xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST4D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL3 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st4d",
        aliases: &[],
        opcode: 0xe5e06000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RX_LSL3,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_4.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::ST4D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL3(
            ST4D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL3::from(bits),
        ))
    }
}
impl InsnOpcode for ST4D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL3 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST4D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x4xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st4d",
        aliases: &[],
        opcode: 0xe5f0e000,
        mask: 0xfff0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4x4xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_4.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::ST4D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x4xVL(
            ST4D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x4xVL::from(bits),
        ))
    }
}
impl InsnOpcode for ST4D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x4xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST4H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st4h",
        aliases: &[],
        opcode: 0xe4e06000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RX_LSL1,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_4.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::ST4H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1(
            ST4H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1::from(bits),
        ))
    }
}
impl InsnOpcode for ST4H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST4H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x4xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st4h",
        aliases: &[],
        opcode: 0xe4f0e000,
        mask: 0xfff0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4x4xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_4.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::ST4H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x4xVL(
            ST4H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x4xVL::from(bits),
        ))
    }
}
impl InsnOpcode for ST4H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x4xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST4Q_SME_Zt4_SVE_Pg3_SVE_ADDR_RI_S4x2xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st4q",
        aliases: &[],
        opcode: 0xe4c00000,
        mask: 0xfff0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE2P1,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zt4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_Q],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4x2xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::ST4Q_SME_Zt4_SVE_Pg3_SVE_ADDR_RI_S4x2xVL(
            ST4Q_SME_Zt4_SVE_Pg3_SVE_ADDR_RI_S4x2xVL::from(bits),
        ))
    }
}
impl InsnOpcode for ST4Q_SME_Zt4_SVE_Pg3_SVE_ADDR_RI_S4x2xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST4Q_SME_Zt4_SVE_Pg3_SVE_ADDR_RR_LSL4 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st4q",
        aliases: &[],
        opcode: 0xe4e00000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE2P1,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zt4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_Q],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RR_LSL4,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::ST4Q_SME_Zt4_SVE_Pg3_SVE_ADDR_RR_LSL4(
            ST4Q_SME_Zt4_SVE_Pg3_SVE_ADDR_RR_LSL4::from(bits),
        ))
    }
}
impl InsnOpcode for ST4Q_SME_Zt4_SVE_Pg3_SVE_ADDR_RR_LSL4 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST4W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st4w",
        aliases: &[],
        opcode: 0xe5606000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RX_LSL2,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_4.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::ST4W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2(
            ST4W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2::from(bits),
        ))
    }
}
impl InsnOpcode for ST4W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST4W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x4xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st4w",
        aliases: &[],
        opcode: 0xe570e000,
        mask: 0xfff0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4x4xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_4.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::ST4W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x4xVL(
            ST4W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x4xVL::from(bits),
        ))
    }
}
impl InsnOpcode for ST4W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x4xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST64B_Rt_LS64_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st64b",
        aliases: &[],
        opcode: 0xf83f9000,
        mask: 0xfffffc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LS64,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt_LS64,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::ST64B_Rt_LS64_ADDR_SIMPLE(
            ST64B_Rt_LS64_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for ST64B_Rt_LS64_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST64BV_Rs_Rt_LS64_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st64bv",
        aliases: &[],
        opcode: 0xf820b000,
        mask: 0xffe0fc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LS64,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt_LS64,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::ST64BV_Rs_Rt_LS64_ADDR_SIMPLE(
            ST64BV_Rs_Rt_LS64_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for ST64BV_Rs_Rt_LS64_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ST64BV0_Rs_Rt_LS64_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "st64bv0",
        aliases: &[],
        opcode: 0xf820a000,
        mask: 0xffe0fc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LS64,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt_LS64,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::ST64BV0_Rs_Rt_LS64_ADDR_SIMPLE(
            ST64BV0_Rs_Rt_LS64_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for ST64BV0_Rs_Rt_LS64_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl STG_Rt_SP_ADDR_SIMM13 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "stg",
        aliases: &[],
        opcode: 0xd9200800,
        mask: 0xffe00c00,
        class: InsnClass::LDST_UNSCALED,
        feature_set: InsnFeatureSet::MEMTAG,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt_SP,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMM13,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::imm_tag],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::imm9,
                        lsb: 12,
                        width: 9,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::index,
                        lsb: 11,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDST_UNSCALED(LDST_UNSCALED::STG_Rt_SP_ADDR_SIMM13(
            STG_Rt_SP_ADDR_SIMM13::from(bits),
        ))
    }
}
impl InsnOpcode for STG_Rt_SP_ADDR_SIMM13 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl STG_Rt_SP_X_ADDR_SIMM13_imm_tag {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "stg",
        aliases: &[],
        opcode: 0xd9200400,
        mask: 0xffe00400,
        class: InsnClass::LDST_IMM9,
        feature_set: InsnFeatureSet::MEMTAG,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt_SP,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMM13,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::imm_tag],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::imm9,
                        lsb: 12,
                        width: 9,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::index,
                        lsb: 11,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDST_IMM9(LDST_IMM9::STG_Rt_SP_X_ADDR_SIMM13_imm_tag(
            STG_Rt_SP_X_ADDR_SIMM13_imm_tag::from(bits),
        ))
    }
}
impl InsnOpcode for STG_Rt_SP_X_ADDR_SIMM13_imm_tag {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl STGM_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "stgm",
        aliases: &[],
        opcode: 0xd9a00000,
        mask: 0xfffffc00,
        class: InsnClass::LDSTEXCL,
        feature_set: InsnFeatureSet::MEMTAG,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDSTEXCL(LDSTEXCL::STGM_Rt_ADDR_SIMPLE(STGM_Rt_ADDR_SIMPLE::from(
            bits,
        )))
    }
}
impl InsnOpcode for STGM_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl STGP_Rt_Rt2_ADDR_SIMM11 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "stgp",
        aliases: &[],
        opcode: 0x69000000,
        mask: 0xffc00000,
        class: InsnClass::LDSTPAIR_OFF,
        feature_set: InsnFeatureSet::MEMTAG,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt2,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt2,
                    lsb: 10,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMM11,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::imm_tag],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::imm7,
                        lsb: 15,
                        width: 7,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::index2,
                        lsb: 24,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDSTPAIR_OFF(LDSTPAIR_OFF::STGP_Rt_Rt2_ADDR_SIMM11(
            STGP_Rt_Rt2_ADDR_SIMM11::from(bits),
        ))
    }
}
impl InsnOpcode for STGP_Rt_Rt2_ADDR_SIMM11 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl STGP_Rt_X_Rt2_X_ADDR_SIMM11_imm_tag {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "stgp",
        aliases: &[],
        opcode: 0x68800000,
        mask: 0xfec00000,
        class: InsnClass::LDSTPAIR_INDEXED,
        feature_set: InsnFeatureSet::MEMTAG,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt2,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt2,
                    lsb: 10,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMM11,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::imm_tag],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::imm7,
                        lsb: 15,
                        width: 7,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::index2,
                        lsb: 24,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDSTPAIR_INDEXED(LDSTPAIR_INDEXED::STGP_Rt_X_Rt2_X_ADDR_SIMM11_imm_tag(
            STGP_Rt_X_Rt2_X_ADDR_SIMM11_imm_tag::from(bits),
        ))
    }
}
impl InsnOpcode for STGP_Rt_X_Rt2_X_ADDR_SIMM11_imm_tag {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl STILP_Rt_Rs_RCPC3_ADDR_OPT_PREIND_WB {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "stilp",
        aliases: &[],
        opcode: 0x19000800,
        mask: 0x3fe0ec00,
        class: InsnClass::RCPC3,
        feature_set: InsnFeatureSet::RCPC3,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::RCPC3_ADDR_OPT_PREIND_WB,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::opc2,
                    lsb: 12,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_RCPC3_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::RCPC3(RCPC3::STILP_Rt_Rs_RCPC3_ADDR_OPT_PREIND_WB(
            STILP_Rt_Rs_RCPC3_ADDR_OPT_PREIND_WB::from(bits),
        ))
    }
}
impl InsnOpcode for STILP_Rt_Rs_RCPC3_ADDR_OPT_PREIND_WB {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl STL1_LEt_SIMD_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "stl1",
        aliases: &[],
        opcode: 0xd018400,
        mask: 0xbffffc00,
        class: InsnClass::RCPC3,
        feature_set: InsnFeatureSet::RCPC3,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::LEt,
                class: InsnOperandClass::SIMD_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[],
            },
            InsnOperand {
                kind: InsnOperandKind::SIMD_ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::RCPC3(RCPC3::STL1_LEt_SIMD_ADDR_SIMPLE(
            STL1_LEt_SIMD_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for STL1_LEt_SIMD_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl STLLR_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "stllr",
        aliases: &[],
        opcode: 0x889f7c00,
        mask: 0xbffffc00,
        class: InsnClass::LDSTEXCL,
        feature_set: InsnFeatureSet::LOR,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMV_GPRSIZE_IN_Q.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDSTEXCL(LDSTEXCL::STLLR_Rt_ADDR_SIMPLE(STLLR_Rt_ADDR_SIMPLE::from(
            bits,
        )))
    }
}
impl InsnOpcode for STLLR_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl STLLRB_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "stllrb",
        aliases: &[],
        opcode: 0x89f7c00,
        mask: 0xfffffc00,
        class: InsnClass::LDSTEXCL,
        feature_set: InsnFeatureSet::LOR,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDSTEXCL(LDSTEXCL::STLLRB_Rt_ADDR_SIMPLE(
            STLLRB_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for STLLRB_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl STLLRH_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "stllrh",
        aliases: &[],
        opcode: 0x489f7c00,
        mask: 0xfffffc00,
        class: InsnClass::LDSTEXCL,
        feature_set: InsnFeatureSet::LOR,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDSTEXCL(LDSTEXCL::STLLRH_Rt_ADDR_SIMPLE(
            STLLRH_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for STLLRH_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl STLR_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "stlr",
        aliases: &[],
        opcode: 0x889ffc00,
        mask: 0xbffffc00,
        class: InsnClass::LDSTEXCL,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMV_GPRSIZE_IN_Q.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDSTEXCL(LDSTEXCL::STLR_Rt_ADDR_SIMPLE(STLR_Rt_ADDR_SIMPLE::from(
            bits,
        )))
    }
}
impl InsnOpcode for STLR_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl STLR_Rt_RCPC3_ADDR_PREIND_WB {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "stlr",
        aliases: &[],
        opcode: 0x19800800,
        mask: 0x3ffffc00,
        class: InsnClass::RCPC3,
        feature_set: InsnFeatureSet::RCPC3,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::RCPC3_ADDR_PREIND_WB,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_RCPC3_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::RCPC3(RCPC3::STLR_Rt_RCPC3_ADDR_PREIND_WB(
            STLR_Rt_RCPC3_ADDR_PREIND_WB::from(bits),
        ))
    }
}
impl InsnOpcode for STLR_Rt_RCPC3_ADDR_PREIND_WB {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl STLRB_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "stlrb",
        aliases: &[],
        opcode: 0x89ffc00,
        mask: 0xfffffc00,
        class: InsnClass::LDSTEXCL,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDSTEXCL(LDSTEXCL::STLRB_Rt_ADDR_SIMPLE(STLRB_Rt_ADDR_SIMPLE::from(
            bits,
        )))
    }
}
impl InsnOpcode for STLRB_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl STLRH_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "stlrh",
        aliases: &[],
        opcode: 0x489ffc00,
        mask: 0xfffffc00,
        class: InsnClass::LDSTEXCL,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDSTEXCL(LDSTEXCL::STLRH_Rt_ADDR_SIMPLE(STLRH_Rt_ADDR_SIMPLE::from(
            bits,
        )))
    }
}
impl InsnOpcode for STLRH_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl STLUR_Rt_ADDR_OFFSET {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "stlur",
        aliases: &[],
        opcode: 0x99000000,
        mask: 0xffe00c00,
        class: InsnClass::LDST_UNSCALED,
        feature_set: InsnFeatureSet::RCPC2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_OFFSET,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm9,
                        lsb: 12,
                        width: 9,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::index,
                        lsb: 11,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDST_UNSCALED(LDST_UNSCALED::STLUR_Rt_ADDR_OFFSET(
            STLUR_Rt_ADDR_OFFSET::from(bits),
        ))
    }
}
impl InsnOpcode for STLUR_Rt_ADDR_OFFSET {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl STLUR_Rt_X_ADDR_OFFSET {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "stlur",
        aliases: &[],
        opcode: 0xd9000000,
        mask: 0xffe00c00,
        class: InsnClass::LDST_UNSCALED,
        feature_set: InsnFeatureSet::RCPC2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_OFFSET,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm9,
                        lsb: 12,
                        width: 9,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::index,
                        lsb: 11,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDST_UNSCALED(LDST_UNSCALED::STLUR_Rt_X_ADDR_OFFSET(
            STLUR_Rt_X_ADDR_OFFSET::from(bits),
        ))
    }
}
impl InsnOpcode for STLUR_Rt_X_ADDR_OFFSET {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl STLUR_Ft_RCPC3_ADDR_OFFSET {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "stlur",
        aliases: &[],
        opcode: 0x1d000800,
        mask: 0x3f600c00,
        class: InsnClass::RCPC3,
        feature_set: InsnFeatureSet::RCPC3,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Ft,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::RCPC3_ADDR_OFFSET,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm9,
                        lsb: 12,
                        width: 9,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_RCPC3_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::RCPC3(RCPC3::STLUR_Ft_RCPC3_ADDR_OFFSET(
            STLUR_Ft_RCPC3_ADDR_OFFSET::from(bits),
        ))
    }
}
impl InsnOpcode for STLUR_Ft_RCPC3_ADDR_OFFSET {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl STLURB_Rt_ADDR_OFFSET {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "stlurb",
        aliases: &[],
        opcode: 0x19000000,
        mask: 0xffe00c00,
        class: InsnClass::LDST_UNSCALED,
        feature_set: InsnFeatureSet::RCPC2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_OFFSET,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm9,
                        lsb: 12,
                        width: 9,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::index,
                        lsb: 11,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDST_UNSCALED(LDST_UNSCALED::STLURB_Rt_ADDR_OFFSET(
            STLURB_Rt_ADDR_OFFSET::from(bits),
        ))
    }
}
impl InsnOpcode for STLURB_Rt_ADDR_OFFSET {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl STLURH_Rt_ADDR_OFFSET {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "stlurh",
        aliases: &[],
        opcode: 0x59000000,
        mask: 0xffe00c00,
        class: InsnClass::LDST_UNSCALED,
        feature_set: InsnFeatureSet::RCPC2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_OFFSET,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm9,
                        lsb: 12,
                        width: 9,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::index,
                        lsb: 11,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDST_UNSCALED(LDST_UNSCALED::STLURH_Rt_ADDR_OFFSET(
            STLURH_Rt_ADDR_OFFSET::from(bits),
        ))
    }
}
impl InsnOpcode for STLURH_Rt_ADDR_OFFSET {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl STLXP_Rs_Rt_Rt2_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "stlxp",
        aliases: &[],
        opcode: 0x88208000,
        mask: 0xbfe08000,
        class: InsnClass::LDSTEXCL,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt2,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt2,
                    lsb: 10,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMV_GPRSIZE_IN_Q.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDSTEXCL(LDSTEXCL::STLXP_Rs_Rt_Rt2_ADDR_SIMPLE(
            STLXP_Rs_Rt_Rt2_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for STLXP_Rs_Rt_Rt2_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl STLXR_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "stlxr",
        aliases: &[],
        opcode: 0x8800fc00,
        mask: 0xbfe0fc00,
        class: InsnClass::LDSTEXCL,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMV_GPRSIZE_IN_Q.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDSTEXCL(LDSTEXCL::STLXR_Rs_Rt_ADDR_SIMPLE(
            STLXR_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for STLXR_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl STLXRB_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "stlxrb",
        aliases: &[],
        opcode: 0x800fc00,
        mask: 0xffe0fc00,
        class: InsnClass::LDSTEXCL,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDSTEXCL(LDSTEXCL::STLXRB_Rs_Rt_ADDR_SIMPLE(
            STLXRB_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for STLXRB_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl STLXRH_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "stlxrh",
        aliases: &[],
        opcode: 0x4800fc00,
        mask: 0xffe0fc00,
        class: InsnClass::LDSTEXCL,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDSTEXCL(LDSTEXCL::STLXRH_Rs_Rt_ADDR_SIMPLE(
            STLXRH_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for STLXRH_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl STNP_Rt_Rt2_ADDR_SIMM7 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "stnp",
        aliases: &[],
        opcode: 0x28000000,
        mask: 0x7fc00000,
        class: InsnClass::LDSTNAPAIR_OFFS,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt2,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt2,
                    lsb: 10,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMM7,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::imm7,
                        lsb: 15,
                        width: 7,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::index2,
                        lsb: 24,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SF_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDSTNAPAIR_OFFS(LDSTNAPAIR_OFFS::STNP_Rt_Rt2_ADDR_SIMM7(
            STNP_Rt_Rt2_ADDR_SIMM7::from(bits),
        ))
    }
}
impl InsnOpcode for STNP_Rt_Rt2_ADDR_SIMM7 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl STNP_Ft_Ft2_ADDR_SIMM7 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "stnp",
        aliases: &[],
        opcode: 0x2c000000,
        mask: 0x3fc00000,
        class: InsnClass::LDSTNAPAIR_OFFS,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Ft,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Ft2,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt2,
                    lsb: 10,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMM7,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::imm7,
                        lsb: 15,
                        width: 7,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::index2,
                        lsb: 24,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDSTNAPAIR_OFFS(LDSTNAPAIR_OFFS::STNP_Ft_Ft2_ADDR_SIMM7(
            STNP_Ft_Ft2_ADDR_SIMM7::from(bits),
        ))
    }
}
impl InsnOpcode for STNP_Ft_Ft2_ADDR_SIMM7 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl STNT1B_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "stnt1b",
        aliases: &[],
        opcode: 0xa0200001,
        mask: 0xffe0e001,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn2,
                    lsb: 1,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RR,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::STNT1B_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR(
            STNT1B_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR::from(bits),
        ))
    }
}
impl InsnOpcode for STNT1B_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl STNT1B_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "stnt1b",
        aliases: &[],
        opcode: 0xa0208001,
        mask: 0xffe0e003,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn4,
                    lsb: 2,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RR,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::STNT1B_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR(
            STNT1B_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR::from(bits),
        ))
    }
}
impl InsnOpcode for STNT1B_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl STNT1B_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "stnt1b",
        aliases: &[],
        opcode: 0xa0600001,
        mask: 0xfff0e001,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn2,
                    lsb: 1,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4x2xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::STNT1B_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL(
            STNT1B_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL::from(bits),
        ))
    }
}
impl InsnOpcode for STNT1B_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl STNT1B_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "stnt1b",
        aliases: &[],
        opcode: 0xa0608001,
        mask: 0xfff0e003,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn4,
                    lsb: 2,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4x4xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::STNT1B_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL(
            STNT1B_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL::from(bits),
        ))
    }
}
impl InsnOpcode for STNT1B_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl STNT1B_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "stnt1b",
        aliases: &[],
        opcode: 0xa1200008,
        mask: 0xffe0e008,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Ztx2_STRIDED,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_ZtT,
                        lsb: 4,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zt3,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RR,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::STNT1B_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR(
            STNT1B_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR::from(bits),
        ))
    }
}
impl InsnOpcode for STNT1B_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl STNT1B_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "stnt1b",
        aliases: &[],
        opcode: 0xa1208008,
        mask: 0xffe0e00c,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Ztx4_STRIDED,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_ZtT,
                        lsb: 4,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zt2,
                        lsb: 0,
                        width: 2,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RR,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::STNT1B_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR(
            STNT1B_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR::from(bits),
        ))
    }
}
impl InsnOpcode for STNT1B_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl STNT1B_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "stnt1b",
        aliases: &[],
        opcode: 0xa1600008,
        mask: 0xfff0e008,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Ztx2_STRIDED,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_ZtT,
                        lsb: 4,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zt3,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4x2xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(
            SVE_MISC::STNT1B_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL(
                STNT1B_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL::from(bits),
            ),
        )
    }
}
impl InsnOpcode for STNT1B_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl STNT1B_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "stnt1b",
        aliases: &[],
        opcode: 0xa1608008,
        mask: 0xfff0e00c,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Ztx4_STRIDED,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_ZtT,
                        lsb: 4,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zt2,
                        lsb: 0,
                        width: 2,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4x4xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(
            SVE_MISC::STNT1B_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL(
                STNT1B_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL::from(bits),
            ),
        )
    }
}
impl InsnOpcode for STNT1B_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl STNT1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "stnt1b",
        aliases: &[],
        opcode: 0xe4002000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_ZX,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::STNT1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZX(
            STNT1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZX::from(bits),
        ))
    }
}
impl InsnOpcode for STNT1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl STNT1B_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_ZX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "stnt1b",
        aliases: &[],
        opcode: 0xe4402000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_ZX,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::STNT1B_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_ZX(
            STNT1B_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_ZX::from(bits),
        ))
    }
}
impl InsnOpcode for STNT1B_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_ZX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl STNT1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "stnt1b",
        aliases: &[],
        opcode: 0xe4006000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RX,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::STNT1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX(
            STNT1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX::from(bits),
        ))
    }
}
impl InsnOpcode for STNT1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl STNT1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "stnt1b",
        aliases: &[],
        opcode: 0xe410e000,
        mask: 0xfff0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::STNT1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL(
            STNT1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL::from(bits),
        ))
    }
}
impl InsnOpcode for STNT1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl STNT1D_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR_LSL3 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "stnt1d",
        aliases: &[],
        opcode: 0xa0206001,
        mask: 0xffe0e001,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn2,
                    lsb: 1,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RR_LSL3,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::STNT1D_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR_LSL3(
            STNT1D_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR_LSL3::from(bits),
        ))
    }
}
impl InsnOpcode for STNT1D_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR_LSL3 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl STNT1D_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR_LSL3 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "stnt1d",
        aliases: &[],
        opcode: 0xa020e001,
        mask: 0xffe0e003,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn4,
                    lsb: 2,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RR_LSL3,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::STNT1D_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR_LSL3(
            STNT1D_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR_LSL3::from(bits),
        ))
    }
}
impl InsnOpcode for STNT1D_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR_LSL3 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl STNT1D_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "stnt1d",
        aliases: &[],
        opcode: 0xa0606001,
        mask: 0xfff0e001,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn2,
                    lsb: 1,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4x2xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::STNT1D_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL(
            STNT1D_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL::from(bits),
        ))
    }
}
impl InsnOpcode for STNT1D_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl STNT1D_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "stnt1d",
        aliases: &[],
        opcode: 0xa060e001,
        mask: 0xfff0e003,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn4,
                    lsb: 2,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4x4xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::STNT1D_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL(
            STNT1D_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL::from(bits),
        ))
    }
}
impl InsnOpcode for STNT1D_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl STNT1D_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL3 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "stnt1d",
        aliases: &[],
        opcode: 0xa1206008,
        mask: 0xffe0e008,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Ztx2_STRIDED,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_ZtT,
                        lsb: 4,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zt3,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RR_LSL3,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::STNT1D_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL3(
            STNT1D_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL3::from(bits),
        ))
    }
}
impl InsnOpcode for STNT1D_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL3 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl STNT1D_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL3 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "stnt1d",
        aliases: &[],
        opcode: 0xa120e008,
        mask: 0xffe0e00c,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Ztx4_STRIDED,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_ZtT,
                        lsb: 4,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zt2,
                        lsb: 0,
                        width: 2,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RR_LSL3,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::STNT1D_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL3(
            STNT1D_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL3::from(bits),
        ))
    }
}
impl InsnOpcode for STNT1D_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL3 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl STNT1D_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "stnt1d",
        aliases: &[],
        opcode: 0xa1606008,
        mask: 0xfff0e008,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Ztx2_STRIDED,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_ZtT,
                        lsb: 4,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zt3,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4x2xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(
            SVE_MISC::STNT1D_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL(
                STNT1D_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL::from(bits),
            ),
        )
    }
}
impl InsnOpcode for STNT1D_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl STNT1D_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "stnt1d",
        aliases: &[],
        opcode: 0xa160e008,
        mask: 0xfff0e00c,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Ztx4_STRIDED,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_ZtT,
                        lsb: 4,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zt2,
                        lsb: 0,
                        width: 2,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4x4xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(
            SVE_MISC::STNT1D_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL(
                STNT1D_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL::from(bits),
            ),
        )
    }
}
impl InsnOpcode for STNT1D_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl STNT1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "stnt1d",
        aliases: &[],
        opcode: 0xe5802000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_ZX,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::STNT1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZX(
            STNT1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZX::from(bits),
        ))
    }
}
impl InsnOpcode for STNT1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl STNT1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL3 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "stnt1d",
        aliases: &[],
        opcode: 0xe5806000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RX_LSL3,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::STNT1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL3(
            STNT1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL3::from(bits),
        ))
    }
}
impl InsnOpcode for STNT1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL3 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl STNT1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "stnt1d",
        aliases: &[],
        opcode: 0xe590e000,
        mask: 0xfff0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::STNT1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL(
            STNT1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL::from(bits),
        ))
    }
}
impl InsnOpcode for STNT1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl STNT1H_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR_LSL1 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "stnt1h",
        aliases: &[],
        opcode: 0xa0202001,
        mask: 0xffe0e001,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn2,
                    lsb: 1,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RR_LSL1,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::STNT1H_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR_LSL1(
            STNT1H_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR_LSL1::from(bits),
        ))
    }
}
impl InsnOpcode for STNT1H_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR_LSL1 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl STNT1H_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR_LSL1 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "stnt1h",
        aliases: &[],
        opcode: 0xa020a001,
        mask: 0xffe0e003,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn4,
                    lsb: 2,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RR_LSL1,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::STNT1H_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR_LSL1(
            STNT1H_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR_LSL1::from(bits),
        ))
    }
}
impl InsnOpcode for STNT1H_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR_LSL1 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl STNT1H_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "stnt1h",
        aliases: &[],
        opcode: 0xa0602001,
        mask: 0xfff0e001,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn2,
                    lsb: 1,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4x2xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::STNT1H_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL(
            STNT1H_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL::from(bits),
        ))
    }
}
impl InsnOpcode for STNT1H_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl STNT1H_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "stnt1h",
        aliases: &[],
        opcode: 0xa060a001,
        mask: 0xfff0e003,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn4,
                    lsb: 2,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4x4xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::STNT1H_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL(
            STNT1H_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL::from(bits),
        ))
    }
}
impl InsnOpcode for STNT1H_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl STNT1H_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL1 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "stnt1h",
        aliases: &[],
        opcode: 0xa1202008,
        mask: 0xffe0e008,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Ztx2_STRIDED,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_ZtT,
                        lsb: 4,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zt3,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RR_LSL1,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::STNT1H_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL1(
            STNT1H_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL1::from(bits),
        ))
    }
}
impl InsnOpcode for STNT1H_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL1 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl STNT1H_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL1 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "stnt1h",
        aliases: &[],
        opcode: 0xa120a008,
        mask: 0xffe0e00c,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Ztx4_STRIDED,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_ZtT,
                        lsb: 4,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zt2,
                        lsb: 0,
                        width: 2,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RR_LSL1,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::STNT1H_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL1(
            STNT1H_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL1::from(bits),
        ))
    }
}
impl InsnOpcode for STNT1H_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL1 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl STNT1H_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "stnt1h",
        aliases: &[],
        opcode: 0xa1602008,
        mask: 0xfff0e008,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Ztx2_STRIDED,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_ZtT,
                        lsb: 4,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zt3,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4x2xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(
            SVE_MISC::STNT1H_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL(
                STNT1H_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL::from(bits),
            ),
        )
    }
}
impl InsnOpcode for STNT1H_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl STNT1H_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "stnt1h",
        aliases: &[],
        opcode: 0xa160a008,
        mask: 0xfff0e00c,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Ztx4_STRIDED,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_ZtT,
                        lsb: 4,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zt2,
                        lsb: 0,
                        width: 2,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4x4xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(
            SVE_MISC::STNT1H_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL(
                STNT1H_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL::from(bits),
            ),
        )
    }
}
impl InsnOpcode for STNT1H_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl STNT1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "stnt1h",
        aliases: &[],
        opcode: 0xe4802000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_ZX,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::STNT1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZX(
            STNT1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZX::from(bits),
        ))
    }
}
impl InsnOpcode for STNT1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl STNT1H_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_ZX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "stnt1h",
        aliases: &[],
        opcode: 0xe4c02000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_ZX,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::STNT1H_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_ZX(
            STNT1H_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_ZX::from(bits),
        ))
    }
}
impl InsnOpcode for STNT1H_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_ZX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl STNT1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "stnt1h",
        aliases: &[],
        opcode: 0xe4806000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RX_LSL1,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::STNT1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1(
            STNT1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1::from(bits),
        ))
    }
}
impl InsnOpcode for STNT1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl STNT1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "stnt1h",
        aliases: &[],
        opcode: 0xe490e000,
        mask: 0xfff0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::STNT1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL(
            STNT1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL::from(bits),
        ))
    }
}
impl InsnOpcode for STNT1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl STNT1W_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR_LSL2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "stnt1w",
        aliases: &[],
        opcode: 0xa0204001,
        mask: 0xffe0e001,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn2,
                    lsb: 1,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RR_LSL2,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::STNT1W_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR_LSL2(
            STNT1W_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR_LSL2::from(bits),
        ))
    }
}
impl InsnOpcode for STNT1W_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR_LSL2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl STNT1W_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR_LSL2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "stnt1w",
        aliases: &[],
        opcode: 0xa020c001,
        mask: 0xffe0e003,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn4,
                    lsb: 2,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RR_LSL2,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::STNT1W_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR_LSL2(
            STNT1W_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR_LSL2::from(bits),
        ))
    }
}
impl InsnOpcode for STNT1W_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR_LSL2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl STNT1W_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "stnt1w",
        aliases: &[],
        opcode: 0xa0604001,
        mask: 0xfff0e001,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn2,
                    lsb: 1,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4x2xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::STNT1W_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL(
            STNT1W_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL::from(bits),
        ))
    }
}
impl InsnOpcode for STNT1W_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl STNT1W_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "stnt1w",
        aliases: &[],
        opcode: 0xa060c001,
        mask: 0xfff0e003,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn4,
                    lsb: 2,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4x4xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::STNT1W_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL(
            STNT1W_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL::from(bits),
        ))
    }
}
impl InsnOpcode for STNT1W_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl STNT1W_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "stnt1w",
        aliases: &[],
        opcode: 0xa1204008,
        mask: 0xffe0e008,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Ztx2_STRIDED,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_ZtT,
                        lsb: 4,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zt3,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RR_LSL2,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::STNT1W_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL2(
            STNT1W_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL2::from(bits),
        ))
    }
}
impl InsnOpcode for STNT1W_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl STNT1W_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "stnt1w",
        aliases: &[],
        opcode: 0xa120c008,
        mask: 0xffe0e00c,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Ztx4_STRIDED,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_ZtT,
                        lsb: 4,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zt2,
                        lsb: 0,
                        width: 2,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RR_LSL2,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::STNT1W_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL2(
            STNT1W_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL2::from(bits),
        ))
    }
}
impl InsnOpcode for STNT1W_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl STNT1W_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "stnt1w",
        aliases: &[],
        opcode: 0xa1604008,
        mask: 0xfff0e008,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Ztx2_STRIDED,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_ZtT,
                        lsb: 4,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zt3,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4x2xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(
            SVE_MISC::STNT1W_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL(
                STNT1W_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL::from(bits),
            ),
        )
    }
}
impl InsnOpcode for STNT1W_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl STNT1W_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "stnt1w",
        aliases: &[],
        opcode: 0xa160c008,
        mask: 0xfff0e00c,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Ztx4_STRIDED,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_ZtT,
                        lsb: 4,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zt2,
                        lsb: 0,
                        width: 2,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_PNg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4x4xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(
            SVE_MISC::STNT1W_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL(
                STNT1W_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL::from(bits),
            ),
        )
    }
}
impl InsnOpcode for STNT1W_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl STNT1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "stnt1w",
        aliases: &[],
        opcode: 0xe5002000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_ZX,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::STNT1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZX(
            STNT1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZX::from(bits),
        ))
    }
}
impl InsnOpcode for STNT1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl STNT1W_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_ZX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "stnt1w",
        aliases: &[],
        opcode: 0xe5402000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_ZX,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_Zn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::STNT1W_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_ZX(
            STNT1W_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_ZX::from(bits),
        ))
    }
}
impl InsnOpcode for STNT1W_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_ZX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl STNT1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "stnt1w",
        aliases: &[],
        opcode: 0xe5006000,
        mask: 0xffe0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RX_LSL2,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::Rm,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::STNT1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2(
            STNT1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2::from(bits),
        ))
    }
}
impl InsnOpcode for STNT1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl STNT1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "stnt1w",
        aliases: &[],
        opcode: 0xe510e000,
        mask: 0xfff0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_ZtxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S4xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::STNT1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL(
            STNT1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL::from(bits),
        ))
    }
}
impl InsnOpcode for STNT1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl STP_Rt_Rt2_ADDR_SIMM7 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "stp",
        aliases: &[],
        opcode: 0x29000000,
        mask: 0x7fc00000,
        class: InsnClass::LDSTPAIR_OFF,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt2,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt2,
                    lsb: 10,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMM7,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::imm7,
                        lsb: 15,
                        width: 7,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::index2,
                        lsb: 24,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SF_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDSTPAIR_OFF(LDSTPAIR_OFF::STP_Rt_Rt2_ADDR_SIMM7(
            STP_Rt_Rt2_ADDR_SIMM7::from(bits),
        ))
    }
}
impl InsnOpcode for STP_Rt_Rt2_ADDR_SIMM7 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl STP_Rt_W_Rt2_W_ADDR_SIMM7_S_S {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "stp",
        aliases: &[],
        opcode: 0x28800000,
        mask: 0x7ec00000,
        class: InsnClass::LDSTPAIR_INDEXED,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt2,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt2,
                    lsb: 10,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMM7,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::imm7,
                        lsb: 15,
                        width: 7,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::index2,
                        lsb: 24,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SF_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDSTPAIR_INDEXED(LDSTPAIR_INDEXED::STP_Rt_W_Rt2_W_ADDR_SIMM7_S_S(
            STP_Rt_W_Rt2_W_ADDR_SIMM7_S_S::from(bits),
        ))
    }
}
impl InsnOpcode for STP_Rt_W_Rt2_W_ADDR_SIMM7_S_S {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl STP_Ft_Ft2_ADDR_SIMM7 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "stp",
        aliases: &[],
        opcode: 0x2d000000,
        mask: 0x3fc00000,
        class: InsnClass::LDSTPAIR_OFF,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Ft,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Ft2,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt2,
                    lsb: 10,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMM7,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::imm7,
                        lsb: 15,
                        width: 7,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::index2,
                        lsb: 24,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDSTPAIR_OFF(LDSTPAIR_OFF::STP_Ft_Ft2_ADDR_SIMM7(
            STP_Ft_Ft2_ADDR_SIMM7::from(bits),
        ))
    }
}
impl InsnOpcode for STP_Ft_Ft2_ADDR_SIMM7 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl STP_Ft_S_S_Ft2_S_S_ADDR_SIMM7_S_S {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "stp",
        aliases: &[],
        opcode: 0x2c800000,
        mask: 0x3ec00000,
        class: InsnClass::LDSTPAIR_INDEXED,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Ft,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Ft2,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt2,
                    lsb: 10,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMM7,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::imm7,
                        lsb: 15,
                        width: 7,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::index2,
                        lsb: 24,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDSTPAIR_INDEXED(LDSTPAIR_INDEXED::STP_Ft_S_S_Ft2_S_S_ADDR_SIMM7_S_S(
            STP_Ft_S_S_Ft2_S_S_ADDR_SIMM7_S_S::from(bits),
        ))
    }
}
impl InsnOpcode for STP_Ft_S_S_Ft2_S_S_ADDR_SIMM7_S_S {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl STR_SME_ZA_array_off4_SME_ADDR_RI_U4xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "str",
        aliases: &[],
        opcode: 0xe1200000,
        mask: 0xffff9c10,
        class: InsnClass::SME_STR,
        feature_set: InsnFeatureSet::SME,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off4,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm4_0,
                        lsb: 0,
                        width: 4,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_ADDR_RI_U4xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm4_0,
                        lsb: 0,
                        width: 4,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_STR(SME_STR::STR_SME_ZA_array_off4_SME_ADDR_RI_U4xVL(
            STR_SME_ZA_array_off4_SME_ADDR_RI_U4xVL::from(bits),
        ))
    }
}
impl InsnOpcode for STR_SME_ZA_array_off4_SME_ADDR_RI_U4xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl STR_SME_ZT0_SIMD_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "str",
        aliases: &[],
        opcode: 0xe13f8000,
        mask: 0xfffffc1f,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZT0,
                class: InsnOperandClass::SYSTEM,
                qualifiers: &[],
                bit_fields: &[],
            },
            InsnOperand {
                kind: InsnOperandKind::SIMD_ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::STR_SME_ZT0_SIMD_ADDR_SIMPLE(
            STR_SME_ZT0_SIMD_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for STR_SME_ZT0_SIMD_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl STR_Rt_ADDR_REGOFF {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "str",
        aliases: &[],
        opcode: 0xb8200800,
        mask: 0xbfe00c00,
        class: InsnClass::LDST_REGOFF,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_REGOFF,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMV_GPRSIZE_IN_Q.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDST_REGOFF(LDST_REGOFF::STR_Rt_ADDR_REGOFF(STR_Rt_ADDR_REGOFF::from(
            bits,
        )))
    }
}
impl InsnOpcode for STR_Rt_ADDR_REGOFF {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl STR_Rt_ADDR_SIMM9 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "str",
        aliases: &[],
        opcode: 0xb8000400,
        mask: 0xbfe00400,
        class: InsnClass::LDST_IMM9,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMM9,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::imm9,
                        lsb: 12,
                        width: 9,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::index,
                        lsb: 11,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMV_GPRSIZE_IN_Q.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDST_IMM9(LDST_IMM9::STR_Rt_ADDR_SIMM9(STR_Rt_ADDR_SIMM9::from(bits)))
    }
}
impl InsnOpcode for STR_Rt_ADDR_SIMM9 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl STR_Rt_ADDR_UIMM12 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "str",
        aliases: &[],
        opcode: 0xb9000000,
        mask: 0xbfc00000,
        class: InsnClass::LDST_POS,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_UIMM12,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm12,
                        lsb: 10,
                        width: 12,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMV_GPRSIZE_IN_Q.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDST_POS(LDST_POS::STR_Rt_ADDR_UIMM12(STR_Rt_ADDR_UIMM12::from(bits)))
    }
}
impl InsnOpcode for STR_Rt_ADDR_UIMM12 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl STR_SVE_Pt_SVE_ADDR_RI_S9xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "str",
        aliases: &[],
        opcode: 0xe5800000,
        mask: 0xffc0e010,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Pt,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pt,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S9xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::STR_SVE_Pt_SVE_ADDR_RI_S9xVL(
            STR_SVE_Pt_SVE_ADDR_RI_S9xVL::from(bits),
        ))
    }
}
impl InsnOpcode for STR_SVE_Pt_SVE_ADDR_RI_S9xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl STR_SVE_PNt_SVE_ADDR_RI_S9xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "str",
        aliases: &[],
        opcode: 0xe5800000,
        mask: 0xffc0e010,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_PNt,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pt,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S9xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::STR_SVE_PNt_SVE_ADDR_RI_S9xVL(
            STR_SVE_PNt_SVE_ADDR_RI_S9xVL::from(bits),
        ))
    }
}
impl InsnOpcode for STR_SVE_PNt_SVE_ADDR_RI_S9xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl STR_SVE_Zt_SVE_ADDR_RI_S9xVL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "str",
        aliases: &[],
        opcode: 0xe5804000,
        mask: 0xffc0e000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zt,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ADDR_RI_S9xVL,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::STR_SVE_Zt_SVE_ADDR_RI_S9xVL(
            STR_SVE_Zt_SVE_ADDR_RI_S9xVL::from(bits),
        ))
    }
}
impl InsnOpcode for STR_SVE_Zt_SVE_ADDR_RI_S9xVL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl STR_Ft_ADDR_REGOFF {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "str",
        aliases: &[],
        opcode: 0x3c200800,
        mask: 0x3f600c00,
        class: InsnClass::LDST_REGOFF,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Ft,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_REGOFF,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDST_REGOFF(LDST_REGOFF::STR_Ft_ADDR_REGOFF(STR_Ft_ADDR_REGOFF::from(
            bits,
        )))
    }
}
impl InsnOpcode for STR_Ft_ADDR_REGOFF {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl STR_Ft_ADDR_SIMM9 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "str",
        aliases: &[],
        opcode: 0x3c000400,
        mask: 0x3f600400,
        class: InsnClass::LDST_IMM9,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Ft,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMM9,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::imm9,
                        lsb: 12,
                        width: 9,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::index,
                        lsb: 11,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDST_IMM9(LDST_IMM9::STR_Ft_ADDR_SIMM9(STR_Ft_ADDR_SIMM9::from(bits)))
    }
}
impl InsnOpcode for STR_Ft_ADDR_SIMM9 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl STR_Ft_ADDR_UIMM12 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "str",
        aliases: &[],
        opcode: 0x3d000000,
        mask: 0x3f400000,
        class: InsnClass::LDST_POS,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Ft,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_UIMM12,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm12,
                        lsb: 10,
                        width: 12,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDST_POS(LDST_POS::STR_Ft_ADDR_UIMM12(STR_Ft_ADDR_UIMM12::from(bits)))
    }
}
impl InsnOpcode for STR_Ft_ADDR_UIMM12 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl STRB_Rt_ADDR_REGOFF {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "strb",
        aliases: &[],
        opcode: 0x38200800,
        mask: 0xffe00c00,
        class: InsnClass::LDST_REGOFF,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_REGOFF,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDST_REGOFF(LDST_REGOFF::STRB_Rt_ADDR_REGOFF(STRB_Rt_ADDR_REGOFF::from(
            bits,
        )))
    }
}
impl InsnOpcode for STRB_Rt_ADDR_REGOFF {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl STRB_Rt_ADDR_SIMM9 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "strb",
        aliases: &[],
        opcode: 0x38000400,
        mask: 0xffe00400,
        class: InsnClass::LDST_IMM9,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMM9,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::imm9,
                        lsb: 12,
                        width: 9,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::index,
                        lsb: 11,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDST_IMM9(LDST_IMM9::STRB_Rt_ADDR_SIMM9(STRB_Rt_ADDR_SIMM9::from(
            bits,
        )))
    }
}
impl InsnOpcode for STRB_Rt_ADDR_SIMM9 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl STRB_Rt_ADDR_UIMM12 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "strb",
        aliases: &[],
        opcode: 0x39000000,
        mask: 0xffc00000,
        class: InsnClass::LDST_POS,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_UIMM12,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm12,
                        lsb: 10,
                        width: 12,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDST_POS(LDST_POS::STRB_Rt_ADDR_UIMM12(STRB_Rt_ADDR_UIMM12::from(
            bits,
        )))
    }
}
impl InsnOpcode for STRB_Rt_ADDR_UIMM12 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl STRH_Rt_ADDR_REGOFF {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "strh",
        aliases: &[],
        opcode: 0x78200800,
        mask: 0xffe00c00,
        class: InsnClass::LDST_REGOFF,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_REGOFF,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDST_REGOFF(LDST_REGOFF::STRH_Rt_ADDR_REGOFF(STRH_Rt_ADDR_REGOFF::from(
            bits,
        )))
    }
}
impl InsnOpcode for STRH_Rt_ADDR_REGOFF {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl STRH_Rt_ADDR_SIMM9 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "strh",
        aliases: &[],
        opcode: 0x78000400,
        mask: 0xffe00400,
        class: InsnClass::LDST_IMM9,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMM9,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::imm9,
                        lsb: 12,
                        width: 9,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::index,
                        lsb: 11,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDST_IMM9(LDST_IMM9::STRH_Rt_ADDR_SIMM9(STRH_Rt_ADDR_SIMM9::from(
            bits,
        )))
    }
}
impl InsnOpcode for STRH_Rt_ADDR_SIMM9 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl STRH_Rt_ADDR_UIMM12 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "strh",
        aliases: &[],
        opcode: 0x79000000,
        mask: 0xffc00000,
        class: InsnClass::LDST_POS,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_UIMM12,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::Rn,
                        lsb: 5,
                        width: 5,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm12,
                        lsb: 10,
                        width: 12,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDST_POS(LDST_POS::STRH_Rt_ADDR_UIMM12(STRH_Rt_ADDR_UIMM12::from(
            bits,
        )))
    }
}
impl InsnOpcode for STRH_Rt_ADDR_UIMM12 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl STTR_Rt_ADDR_SIMM9 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sttr",
        aliases: &[],
        opcode: 0xb8000800,
        mask: 0xbfe00c00,
        class: InsnClass::LDST_UNPRIV,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMM9,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::imm9,
                        lsb: 12,
                        width: 9,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::index,
                        lsb: 11,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMV_GPRSIZE_IN_Q.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDST_UNPRIV(LDST_UNPRIV::STTR_Rt_ADDR_SIMM9(STTR_Rt_ADDR_SIMM9::from(
            bits,
        )))
    }
}
impl InsnOpcode for STTR_Rt_ADDR_SIMM9 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl STTRB_Rt_ADDR_SIMM9 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sttrb",
        aliases: &[],
        opcode: 0x38000800,
        mask: 0xffe00c00,
        class: InsnClass::LDST_UNPRIV,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMM9,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::imm9,
                        lsb: 12,
                        width: 9,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::index,
                        lsb: 11,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDST_UNPRIV(LDST_UNPRIV::STTRB_Rt_ADDR_SIMM9(STTRB_Rt_ADDR_SIMM9::from(
            bits,
        )))
    }
}
impl InsnOpcode for STTRB_Rt_ADDR_SIMM9 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl STTRH_Rt_ADDR_SIMM9 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sttrh",
        aliases: &[],
        opcode: 0x78000800,
        mask: 0xffe00c00,
        class: InsnClass::LDST_UNPRIV,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMM9,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::imm9,
                        lsb: 12,
                        width: 9,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::index,
                        lsb: 11,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDST_UNPRIV(LDST_UNPRIV::STTRH_Rt_ADDR_SIMM9(STTRH_Rt_ADDR_SIMM9::from(
            bits,
        )))
    }
}
impl InsnOpcode for STTRH_Rt_ADDR_SIMM9 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl STUR_Rt_ADDR_SIMM9 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "stur",
        aliases: &[],
        opcode: 0xb8000000,
        mask: 0xbfe00c00,
        class: InsnClass::LDST_UNSCALED,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMM9,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::imm9,
                        lsb: 12,
                        width: 9,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::index,
                        lsb: 11,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMV_GPRSIZE_IN_Q.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDST_UNSCALED(LDST_UNSCALED::STUR_Rt_ADDR_SIMM9(STUR_Rt_ADDR_SIMM9::from(
            bits,
        )))
    }
}
impl InsnOpcode for STUR_Rt_ADDR_SIMM9 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl STUR_Ft_ADDR_SIMM9 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "stur",
        aliases: &[],
        opcode: 0x3c000000,
        mask: 0x3f600c00,
        class: InsnClass::LDST_UNSCALED,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Ft,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMM9,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::imm9,
                        lsb: 12,
                        width: 9,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::index,
                        lsb: 11,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDST_UNSCALED(LDST_UNSCALED::STUR_Ft_ADDR_SIMM9(STUR_Ft_ADDR_SIMM9::from(
            bits,
        )))
    }
}
impl InsnOpcode for STUR_Ft_ADDR_SIMM9 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl STURB_Rt_ADDR_SIMM9 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sturb",
        aliases: &[],
        opcode: 0x38000000,
        mask: 0xffe00c00,
        class: InsnClass::LDST_UNSCALED,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMM9,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::imm9,
                        lsb: 12,
                        width: 9,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::index,
                        lsb: 11,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDST_UNSCALED(LDST_UNSCALED::STURB_Rt_ADDR_SIMM9(
            STURB_Rt_ADDR_SIMM9::from(bits),
        ))
    }
}
impl InsnOpcode for STURB_Rt_ADDR_SIMM9 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl STURH_Rt_ADDR_SIMM9 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sturh",
        aliases: &[],
        opcode: 0x78000000,
        mask: 0xffe00c00,
        class: InsnClass::LDST_UNSCALED,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMM9,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::imm9,
                        lsb: 12,
                        width: 9,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::index,
                        lsb: 11,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDST_UNSCALED(LDST_UNSCALED::STURH_Rt_ADDR_SIMM9(
            STURH_Rt_ADDR_SIMM9::from(bits),
        ))
    }
}
impl InsnOpcode for STURH_Rt_ADDR_SIMM9 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl STXP_Rs_Rt_Rt2_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "stxp",
        aliases: &[],
        opcode: 0x88200000,
        mask: 0xbfe08000,
        class: InsnClass::LDSTEXCL,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt2,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt2,
                    lsb: 10,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMV_GPRSIZE_IN_Q.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDSTEXCL(LDSTEXCL::STXP_Rs_Rt_Rt2_ADDR_SIMPLE(
            STXP_Rs_Rt_Rt2_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for STXP_Rs_Rt_Rt2_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl STXR_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "stxr",
        aliases: &[],
        opcode: 0x88007c00,
        mask: 0xbfe0fc00,
        class: InsnClass::LDSTEXCL,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMV_GPRSIZE_IN_Q.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDSTEXCL(LDSTEXCL::STXR_Rs_Rt_ADDR_SIMPLE(
            STXR_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for STXR_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl STXRB_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "stxrb",
        aliases: &[],
        opcode: 0x8007c00,
        mask: 0xffe0fc00,
        class: InsnClass::LDSTEXCL,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDSTEXCL(LDSTEXCL::STXRB_Rs_Rt_ADDR_SIMPLE(
            STXRB_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for STXRB_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl STXRH_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "stxrh",
        aliases: &[],
        opcode: 0x48007c00,
        mask: 0xffe0fc00,
        class: InsnClass::LDSTEXCL,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDSTEXCL(LDSTEXCL::STXRH_Rs_Rt_ADDR_SIMPLE(
            STXRH_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for STXRH_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl STZ2G_Rt_SP_ADDR_SIMM13 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "stz2g",
        aliases: &[],
        opcode: 0xd9e00800,
        mask: 0xffe00c00,
        class: InsnClass::LDST_UNSCALED,
        feature_set: InsnFeatureSet::MEMTAG,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt_SP,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMM13,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::imm_tag],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::imm9,
                        lsb: 12,
                        width: 9,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::index,
                        lsb: 11,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDST_UNSCALED(LDST_UNSCALED::STZ2G_Rt_SP_ADDR_SIMM13(
            STZ2G_Rt_SP_ADDR_SIMM13::from(bits),
        ))
    }
}
impl InsnOpcode for STZ2G_Rt_SP_ADDR_SIMM13 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl STZ2G_Rt_SP_X_ADDR_SIMM13_imm_tag {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "stz2g",
        aliases: &[],
        opcode: 0xd9e00400,
        mask: 0xffe00400,
        class: InsnClass::LDST_IMM9,
        feature_set: InsnFeatureSet::MEMTAG,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt_SP,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMM13,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::imm_tag],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::imm9,
                        lsb: 12,
                        width: 9,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::index,
                        lsb: 11,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDST_IMM9(LDST_IMM9::STZ2G_Rt_SP_X_ADDR_SIMM13_imm_tag(
            STZ2G_Rt_SP_X_ADDR_SIMM13_imm_tag::from(bits),
        ))
    }
}
impl InsnOpcode for STZ2G_Rt_SP_X_ADDR_SIMM13_imm_tag {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl STZG_Rt_SP_ADDR_SIMM13 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "stzg",
        aliases: &[],
        opcode: 0xd9600800,
        mask: 0xffe00c00,
        class: InsnClass::LDST_UNSCALED,
        feature_set: InsnFeatureSet::MEMTAG,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt_SP,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMM13,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::imm_tag],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::imm9,
                        lsb: 12,
                        width: 9,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::index,
                        lsb: 11,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDST_UNSCALED(LDST_UNSCALED::STZG_Rt_SP_ADDR_SIMM13(
            STZG_Rt_SP_ADDR_SIMM13::from(bits),
        ))
    }
}
impl InsnOpcode for STZG_Rt_SP_ADDR_SIMM13 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl STZG_Rt_SP_X_ADDR_SIMM13_imm_tag {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "stzg",
        aliases: &[],
        opcode: 0xd9600400,
        mask: 0xffe00400,
        class: InsnClass::LDST_IMM9,
        feature_set: InsnFeatureSet::MEMTAG,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt_SP,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMM13,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[InsnOperandQualifier::imm_tag],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::imm9,
                        lsb: 12,
                        width: 9,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::index,
                        lsb: 11,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDST_IMM9(LDST_IMM9::STZG_Rt_SP_X_ADDR_SIMM13_imm_tag(
            STZG_Rt_SP_X_ADDR_SIMM13_imm_tag::from(bits),
        ))
    }
}
impl InsnOpcode for STZG_Rt_SP_X_ADDR_SIMM13_imm_tag {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl STZGM_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "stzgm",
        aliases: &[],
        opcode: 0xd9200000,
        mask: 0xfffffc00,
        class: InsnClass::LDSTEXCL,
        feature_set: InsnFeatureSet::MEMTAG,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LDSTEXCL(LDSTEXCL::STZGM_Rt_ADDR_SIMPLE(STZGM_Rt_ADDR_SIMPLE::from(
            bits,
        )))
    }
}
impl InsnOpcode for STZGM_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SUB_SME_ZA_array_off3_0_SVE_ZnxN_SME_Zm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sub",
        aliases: &[],
        opcode: 0xc1201818,
        mask: 0xffb09c18,
        class: InsnClass::SME_INT_SD,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off3_0,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_0,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ZnxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm,
                    lsb: 16,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_INT_SD(SME_INT_SD::SUB_SME_ZA_array_off3_0_SVE_ZnxN_SME_Zm(
            SUB_SME_ZA_array_off3_0_SVE_ZnxN_SME_Zm::from(bits),
        ))
    }
}
impl InsnOpcode for SUB_SME_ZA_array_off3_0_SVE_ZnxN_SME_Zm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SUB_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_S_SME_Zm_S_S {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sub",
        aliases: &[],
        opcode: 0xc1301818,
        mask: 0xffb09c18,
        class: InsnClass::SME_INT_SD,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off3_0,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_0,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ZnxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm,
                    lsb: 16,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_4.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_INT_SD(
            SME_INT_SD::SUB_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_S_SME_Zm_S_S(
                SUB_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_S_SME_Zm_S_S::from(bits),
            ),
        )
    }
}
impl InsnOpcode for SUB_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_S_SME_Zm_S_S {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SUB_SME_ZA_array_off3_0_SME_Znx2_SME_Zmx2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sub",
        aliases: &[],
        opcode: 0xc1a01818,
        mask: 0xffa19c38,
        class: InsnClass::SME_INT_SD,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off3_0,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_0,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn2,
                    lsb: 6,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zmx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm2,
                    lsb: 17,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_INT_SD(SME_INT_SD::SUB_SME_ZA_array_off3_0_SME_Znx2_SME_Zmx2(
            SUB_SME_ZA_array_off3_0_SME_Znx2_SME_Zmx2::from(bits),
        ))
    }
}
impl InsnOpcode for SUB_SME_ZA_array_off3_0_SME_Znx2_SME_Zmx2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SUB_SME_ZA_array_off3_0_SME_Znx4_SME_Zmx4 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sub",
        aliases: &[],
        opcode: 0xc1a11818,
        mask: 0xffa39c78,
        class: InsnClass::SME_INT_SD,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off3_0,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_0,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn4,
                    lsb: 7,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zmx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm4,
                    lsb: 18,
                    width: 3,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_4.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_INT_SD(SME_INT_SD::SUB_SME_ZA_array_off3_0_SME_Znx4_SME_Zmx4(
            SUB_SME_ZA_array_off3_0_SME_Znx4_SME_Zmx4::from(bits),
        ))
    }
}
impl InsnOpcode for SUB_SME_ZA_array_off3_0_SME_Znx4_SME_Zmx4 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SUB_SME_ZA_array_off3_0_SME_Znx2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sub",
        aliases: &[],
        opcode: 0xc1a01c18,
        mask: 0xffbf9c38,
        class: InsnClass::SME_INT_SD,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off3_0,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_0,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn2,
                    lsb: 6,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_INT_SD(SME_INT_SD::SUB_SME_ZA_array_off3_0_SME_Znx2(
            SUB_SME_ZA_array_off3_0_SME_Znx2::from(bits),
        ))
    }
}
impl InsnOpcode for SUB_SME_ZA_array_off3_0_SME_Znx2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SUB_SME_ZA_array_off3_0_SME_Znx4 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sub",
        aliases: &[],
        opcode: 0xc1a11c18,
        mask: 0xffbf9c78,
        class: InsnClass::SME_INT_SD,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off3_0,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_0,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn4,
                    lsb: 7,
                    width: 3,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_4.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_INT_SD(SME_INT_SD::SUB_SME_ZA_array_off3_0_SME_Znx4(
            SUB_SME_ZA_array_off3_0_SME_Znx4::from(bits),
        ))
    }
}
impl InsnOpcode for SUB_SME_ZA_array_off3_0_SME_Znx4 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SUB_Rd_SP_Rn_SP_AIMM {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sub",
        aliases: &[],
        opcode: 0x51000000,
        mask: 0x7f800000,
        class: InsnClass::ADDSUB_IMM,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd_SP,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn_SP,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::AIMM,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::shift,
                        lsb: 22,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm12,
                        lsb: 10,
                        width: 12,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SF_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ADDSUB_IMM(ADDSUB_IMM::SUB_Rd_SP_Rn_SP_AIMM(
            SUB_Rd_SP_Rn_SP_AIMM::from(bits),
        ))
    }
}
impl InsnOpcode for SUB_Rd_SP_Rn_SP_AIMM {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SUB_Rd_Rn_Rm_SFT {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sub",
        aliases: &[],
        opcode: 0x4b000000,
        mask: 0x7f200000,
        class: InsnClass::ADDSUB_SHIFT,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rm_SFT,
                class: InsnOperandClass::MODIFIED_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_ALIAS.bits() | InsnFlags::HAS_SF_FIELD.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ADDSUB_SHIFT(ADDSUB_SHIFT::SUB_Rd_Rn_Rm_SFT(SUB_Rd_Rn_Rm_SFT::from(bits)))
    }
}
impl InsnOpcode for SUB_Rd_Rn_Rm_SFT {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SUB_Rd_SP_Rn_SP_Rm_EXT {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sub",
        aliases: &[],
        opcode: 0x4b200000,
        mask: 0x7fe00000,
        class: InsnClass::ADDSUB_EXT,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd_SP,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn_SP,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rm_EXT,
                class: InsnOperandClass::MODIFIED_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::W],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SF_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ADDSUB_EXT(ADDSUB_EXT::SUB_Rd_SP_Rn_SP_Rm_EXT(
            SUB_Rd_SP_Rn_SP_Rm_EXT::from(bits),
        ))
    }
}
impl InsnOpcode for SUB_Rd_SP_Rn_SP_Rm_EXT {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SUB_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sub",
        aliases: &[],
        opcode: 0x4010000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_5,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_5,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::SUB_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(
            SUB_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5::from(bits),
        ))
    }
}
impl InsnOpcode for SUB_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SUB_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sub",
        aliases: &[],
        opcode: 0x4200400,
        mask: 0xff20fc00,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::SUB_SVE_Zd_SVE_Zn_SVE_Zm_16(
            SUB_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for SUB_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SUB_SVE_Zd_SVE_Zd_SVE_AIMM {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sub",
        aliases: &[],
        opcode: 0x2521c000,
        mask: 0xff3fc000,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_AIMM,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_imm9,
                    lsb: 5,
                    width: 9,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::SUB_SVE_Zd_SVE_Zd_SVE_AIMM(
            SUB_SVE_Zd_SVE_Zd_SVE_AIMM::from(bits),
        ))
    }
}
impl InsnOpcode for SUB_SVE_Zd_SVE_Zd_SVE_AIMM {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SUB_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sub",
        aliases: &[],
        opcode: 0x2e208400,
        mask: 0xbf20fc00,
        class: InsnClass::ASIMDSAME,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSAME(ASIMDSAME::SUB_Vd_Vn_Vm(SUB_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for SUB_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SUB_Sd_Sn_Sm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sub",
        aliases: &[],
        opcode: 0x7ee08400,
        mask: 0xffe0fc00,
        class: InsnClass::ASISDSAME,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sm,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMD_SCALAR_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDSAME(ASISDSAME::SUB_Sd_Sn_Sm(SUB_Sd_Sn_Sm::from(bits)))
    }
}
impl InsnOpcode for SUB_Sd_Sn_Sm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SUBG_Rd_SP_Rn_SP_UIMM10_UIMM4_ADDG {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "subg",
        aliases: &[],
        opcode: 0xd1800000,
        mask: 0xffc0c000,
        class: InsnClass::ADDSUB_IMM,
        feature_set: InsnFeatureSet::MEMTAG,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd_SP,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn_SP,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::UIMM10,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::immr,
                    lsb: 16,
                    width: 6,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::UIMM4_ADDG,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::imm4_10,
                    lsb: 10,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ADDSUB_IMM(ADDSUB_IMM::SUBG_Rd_SP_Rn_SP_UIMM10_UIMM4_ADDG(
            SUBG_Rd_SP_Rn_SP_UIMM10_UIMM4_ADDG::from(bits),
        ))
    }
}
impl InsnOpcode for SUBG_Rd_SP_Rn_SP_UIMM10_UIMM4_ADDG {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SUBHN_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "subhn",
        aliases: &[],
        opcode: 0xe206000,
        mask: 0xff20fc00,
        class: InsnClass::ASIMDDIFF,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_4H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8H, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8H, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDDIFF(ASIMDDIFF::SUBHN_Vd_Vn_Vm(SUBHN_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for SUBHN_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SUBHN2_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "subhn2",
        aliases: &[],
        opcode: 0x4e206000,
        mask: 0xff20fc00,
        class: InsnClass::ASIMDDIFF,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_16B, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8H, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8H, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDDIFF(ASIMDDIFF::SUBHN2_Vd_Vn_Vm(SUBHN2_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for SUBHN2_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SUBHNB_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "subhnb",
        aliases: &[],
        opcode: 0x45207000,
        mask: 0xff20fc00,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::SUBHNB_SVE_Zd_SVE_Zn_SVE_Zm_16(
            SUBHNB_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for SUBHNB_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SUBHNT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "subhnt",
        aliases: &[],
        opcode: 0x45207400,
        mask: 0xff20fc00,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::SUBHNT_SVE_Zd_SVE_Zn_SVE_Zm_16(
            SUBHNT_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for SUBHNT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SUBP_Rd_Rn_SP_Rm_SP {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "subp",
        aliases: &[],
        opcode: 0x9ac00000,
        mask: 0xffe0fc00,
        class: InsnClass::DP_2SRC,
        feature_set: InsnFeatureSet::MEMTAG,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn_SP,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rm_SP,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::DP_2SRC(DP_2SRC::SUBP_Rd_Rn_SP_Rm_SP(SUBP_Rd_Rn_SP_Rm_SP::from(
            bits,
        )))
    }
}
impl InsnOpcode for SUBP_Rd_Rn_SP_Rm_SP {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SUBPS_Rd_Rn_SP_Rm_SP {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "subps",
        aliases: &[],
        opcode: 0xbac00000,
        mask: 0xffe0fc00,
        class: InsnClass::DP_2SRC,
        feature_set: InsnFeatureSet::MEMTAG,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn_SP,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rm_SP,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ALIAS.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::DP_2SRC(DP_2SRC::SUBPS_Rd_Rn_SP_Rm_SP(SUBPS_Rd_Rn_SP_Rm_SP::from(
            bits,
        )))
    }
}
impl InsnOpcode for SUBPS_Rd_Rn_SP_Rm_SP {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SUBR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "subr",
        aliases: &[],
        opcode: 0x4030000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_5,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_5,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::SUBR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(
            SUBR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5::from(bits),
        ))
    }
}
impl InsnOpcode for SUBR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SUBR_SVE_Zd_SVE_Zd_SVE_AIMM {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "subr",
        aliases: &[],
        opcode: 0x2523c000,
        mask: 0xff3fc000,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_AIMM,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_imm9,
                    lsb: 5,
                    width: 9,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::SUBR_SVE_Zd_SVE_Zd_SVE_AIMM(
            SUBR_SVE_Zd_SVE_Zd_SVE_AIMM::from(bits),
        ))
    }
}
impl InsnOpcode for SUBR_SVE_Zd_SVE_Zd_SVE_AIMM {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SUBS_Rd_Rn_SP_AIMM {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "subs",
        aliases: &[],
        opcode: 0x71000000,
        mask: 0x7f800000,
        class: InsnClass::ADDSUB_IMM,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn_SP,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::AIMM,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::shift,
                        lsb: 22,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm12,
                        lsb: 10,
                        width: 12,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_ALIAS.bits() | InsnFlags::HAS_SF_FIELD.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ADDSUB_IMM(ADDSUB_IMM::SUBS_Rd_Rn_SP_AIMM(SUBS_Rd_Rn_SP_AIMM::from(
            bits,
        )))
    }
}
impl InsnOpcode for SUBS_Rd_Rn_SP_AIMM {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SUBS_Rd_Rn_Rm_SFT {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "subs",
        aliases: &[],
        opcode: 0x6b000000,
        mask: 0x7f200000,
        class: InsnClass::ADDSUB_SHIFT,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rm_SFT,
                class: InsnOperandClass::MODIFIED_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_ALIAS.bits() | InsnFlags::HAS_SF_FIELD.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ADDSUB_SHIFT(ADDSUB_SHIFT::SUBS_Rd_Rn_Rm_SFT(SUBS_Rd_Rn_Rm_SFT::from(
            bits,
        )))
    }
}
impl InsnOpcode for SUBS_Rd_Rn_Rm_SFT {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SUBS_Rd_Rn_SP_Rm_EXT {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "subs",
        aliases: &[],
        opcode: 0x6b200000,
        mask: 0x7fe00000,
        class: InsnClass::ADDSUB_EXT,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn_SP,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rm_EXT,
                class: InsnOperandClass::MODIFIED_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::W],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_ALIAS.bits() | InsnFlags::HAS_SF_FIELD.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ADDSUB_EXT(ADDSUB_EXT::SUBS_Rd_Rn_SP_Rm_EXT(
            SUBS_Rd_Rn_SP_Rm_EXT::from(bits),
        ))
    }
}
impl InsnOpcode for SUBS_Rd_Rn_SP_Rm_EXT {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SUDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sudot",
        aliases: &[],
        opcode: 0xc1501038,
        mask: 0xfff09038,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off3_0,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_0,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn2,
                    lsb: 6,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm_INDEX2,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zm,
                        lsb: 16,
                        width: 4,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_10,
                        lsb: 10,
                        width: 2,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::SUDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2(
            SUDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2::from(bits),
        ))
    }
}
impl InsnOpcode for SUDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SUDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sudot",
        aliases: &[],
        opcode: 0xc1509038,
        mask: 0xfff09078,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off3_0,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_0,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn4,
                    lsb: 7,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm_INDEX2,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zm,
                        lsb: 16,
                        width: 4,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_10,
                        lsb: 10,
                        width: 2,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_4.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::SUDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2(
            SUDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2::from(bits),
        ))
    }
}
impl InsnOpcode for SUDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SUDOT_SME_ZA_array_off3_0_SVE_ZnxN_SME_Zm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sudot",
        aliases: &[],
        opcode: 0xc1201418,
        mask: 0xfff09c18,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off3_0,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_0,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ZnxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm,
                    lsb: 16,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::SUDOT_SME_ZA_array_off3_0_SVE_ZnxN_SME_Zm(
            SUDOT_SME_ZA_array_off3_0_SVE_ZnxN_SME_Zm::from(bits),
        ))
    }
}
impl InsnOpcode for SUDOT_SME_ZA_array_off3_0_SVE_ZnxN_SME_Zm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SUDOT_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_B_SME_Zm_S_B {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sudot",
        aliases: &[],
        opcode: 0xc1301418,
        mask: 0xfff09c18,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off3_0,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_0,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ZnxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm,
                    lsb: 16,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_4.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(
            SME_MISC::SUDOT_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_B_SME_Zm_S_B(
                SUDOT_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_B_SME_Zm_S_B::from(bits),
            ),
        )
    }
}
impl InsnOpcode for SUDOT_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_B_SME_Zm_S_B {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SUDOT_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sudot",
        aliases: &[],
        opcode: 0x44a01c00,
        mask: 0xffe0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::I8MM_SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm3_INDEX,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::SUDOT_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX(
            SUDOT_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX::from(bits),
        ))
    }
}
impl InsnOpcode for SUDOT_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SUDOT_Vd_Vn_Em {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sudot",
        aliases: &[],
        opcode: 0xf00f000,
        mask: 0xbfc0f400,
        class: InsnClass::DOTPRODUCT,
        feature_set: InsnFeatureSet::I8MM,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Em,
                class: InsnOperandClass::SIMD_ELEMENT,
                qualifiers: &[InsnOperandQualifier::S_4B, InsnOperandQualifier::S_4B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::DOTPRODUCT(DOTPRODUCT::SUDOT_Vd_Vn_Em(SUDOT_Vd_Vn_Em::from(bits)))
    }
}
impl InsnOpcode for SUDOT_Vd_Vn_Em {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SUMLALL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm_INDEX4_10 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sumlall",
        aliases: &[],
        opcode: 0xc1000014,
        mask: 0xfff0001c,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off2x4,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_0,
                        lsb: 0,
                        width: 2,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm_INDEX4_10,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zm,
                        lsb: 16,
                        width: 4,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm1_15,
                        lsb: 15,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_10,
                        lsb: 10,
                        width: 3,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(
            SME_MISC::SUMLALL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm_INDEX4_10(
                SUMLALL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm_INDEX4_10::from(bits),
            ),
        )
    }
}
impl InsnOpcode for SUMLALL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm_INDEX4_10 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SUMLALL_SME_ZA_array_off1x4_SME_Znx2_SME_Zm_INDEX4_1 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sumlall",
        aliases: &[],
        opcode: 0xc1100030,
        mask: 0xfff09038,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off1x4,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm1_0,
                        lsb: 0,
                        width: 1,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn2,
                    lsb: 6,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm_INDEX4_1,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zm,
                        lsb: 16,
                        width: 4,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_10,
                        lsb: 10,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_1,
                        lsb: 1,
                        width: 2,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(
            SME_MISC::SUMLALL_SME_ZA_array_off1x4_SME_Znx2_SME_Zm_INDEX4_1(
                SUMLALL_SME_ZA_array_off1x4_SME_Znx2_SME_Zm_INDEX4_1::from(bits),
            ),
        )
    }
}
impl InsnOpcode for SUMLALL_SME_ZA_array_off1x4_SME_Znx2_SME_Zm_INDEX4_1 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SUMLALL_SME_ZA_array_off1x4_SME_Znx4_SME_Zm_INDEX4_1 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sumlall",
        aliases: &[],
        opcode: 0xc1108030,
        mask: 0xfff09078,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off1x4,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm1_0,
                        lsb: 0,
                        width: 1,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn4,
                    lsb: 7,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm_INDEX4_1,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zm,
                        lsb: 16,
                        width: 4,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_10,
                        lsb: 10,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_1,
                        lsb: 1,
                        width: 2,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_4.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(
            SME_MISC::SUMLALL_SME_ZA_array_off1x4_SME_Znx4_SME_Zm_INDEX4_1(
                SUMLALL_SME_ZA_array_off1x4_SME_Znx4_SME_Zm_INDEX4_1::from(bits),
            ),
        )
    }
}
impl InsnOpcode for SUMLALL_SME_ZA_array_off1x4_SME_Znx4_SME_Zm_INDEX4_1 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SUMLALL_SME_ZA_array_off1x4_SVE_ZnxN_SME_Zm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sumlall",
        aliases: &[],
        opcode: 0xc1200014,
        mask: 0xfff09c1e,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off1x4,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm1_0,
                        lsb: 0,
                        width: 1,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ZnxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm,
                    lsb: 16,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::SUMLALL_SME_ZA_array_off1x4_SVE_ZnxN_SME_Zm(
            SUMLALL_SME_ZA_array_off1x4_SVE_ZnxN_SME_Zm::from(bits),
        ))
    }
}
impl InsnOpcode for SUMLALL_SME_ZA_array_off1x4_SVE_ZnxN_SME_Zm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SUMLALL_SME_ZA_array_off1x4_S_S_SVE_ZnxN_S_B_SME_Zm_S_B {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sumlall",
        aliases: &[],
        opcode: 0xc1300014,
        mask: 0xfff09c1e,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off1x4,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm1_0,
                        lsb: 0,
                        width: 1,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ZnxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm,
                    lsb: 16,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_4.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(
            SME_MISC::SUMLALL_SME_ZA_array_off1x4_S_S_SVE_ZnxN_S_B_SME_Zm_S_B(
                SUMLALL_SME_ZA_array_off1x4_S_S_SVE_ZnxN_S_B_SME_Zm_S_B::from(bits),
            ),
        )
    }
}
impl InsnOpcode for SUMLALL_SME_ZA_array_off1x4_S_S_SVE_ZnxN_S_B_SME_Zm_S_B {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SUMOPA_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sumopa",
        aliases: &[],
        opcode: 0xa0a00000,
        mask: 0xffe0001c,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZAda_2b,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_ZAda_2b,
                    lsb: 0,
                    width: 2,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Pm,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Pm,
                    lsb: 13,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(
            SME_MISC::SUMOPA_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16(
                SUMOPA_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16::from(bits),
            ),
        )
    }
}
impl InsnOpcode for SUMOPA_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SUMOPA_SME_ZAda_3b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sumopa",
        aliases: &[],
        opcode: 0xa0e00000,
        mask: 0xffe00018,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME_I16I64,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZAda_3b,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_ZAda_3b,
                    lsb: 0,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Pm,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Pm,
                    lsb: 13,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(
            SME_MISC::SUMOPA_SME_ZAda_3b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16(
                SUMOPA_SME_ZAda_3b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16::from(bits),
            ),
        )
    }
}
impl InsnOpcode for SUMOPA_SME_ZAda_3b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SUMOPS_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sumops",
        aliases: &[],
        opcode: 0xa0a00010,
        mask: 0xffe0001c,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZAda_2b,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_ZAda_2b,
                    lsb: 0,
                    width: 2,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Pm,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Pm,
                    lsb: 13,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(
            SME_MISC::SUMOPS_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16(
                SUMOPS_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16::from(bits),
            ),
        )
    }
}
impl InsnOpcode for SUMOPS_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SUMOPS_SME_ZAda_3b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sumops",
        aliases: &[],
        opcode: 0xa0e00010,
        mask: 0xffe00018,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME_I16I64,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZAda_3b,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_ZAda_3b,
                    lsb: 0,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Pm,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Pm,
                    lsb: 13,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(
            SME_MISC::SUMOPS_SME_ZAda_3b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16(
                SUMOPS_SME_ZAda_3b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16::from(bits),
            ),
        )
    }
}
impl InsnOpcode for SUMOPS_SME_ZAda_3b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SUNPK_SME_Zdnx2_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sunpk",
        aliases: &[],
        opcode: 0xc125e000,
        mask: 0xff3ffc01,
        class: InsnClass::SME_SIZE_22_HSD,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn2,
                    lsb: 1,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_SIZE_22_HSD(SME_SIZE_22_HSD::SUNPK_SME_Zdnx2_SVE_Zn(
            SUNPK_SME_Zdnx2_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for SUNPK_SME_Zdnx2_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SUNPK_SME_Zdnx4_SME_Znx2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sunpk",
        aliases: &[],
        opcode: 0xc135e000,
        mask: 0xff3ffc23,
        class: InsnClass::SME_SIZE_22_HSD,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn4,
                    lsb: 2,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn2,
                    lsb: 6,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_SIZE_22_HSD(SME_SIZE_22_HSD::SUNPK_SME_Zdnx4_SME_Znx2(
            SUNPK_SME_Zdnx4_SME_Znx2::from(bits),
        ))
    }
}
impl InsnOpcode for SUNPK_SME_Zdnx4_SME_Znx2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SUNPKHI_SVE_Zd_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sunpkhi",
        aliases: &[],
        opcode: 0x5313800,
        mask: 0xff3ffc00,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::SUNPKHI_SVE_Zd_SVE_Zn(
            SUNPKHI_SVE_Zd_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for SUNPKHI_SVE_Zd_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SUNPKLO_SVE_Zd_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sunpklo",
        aliases: &[],
        opcode: 0x5303800,
        mask: 0xff3ffc00,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::SUNPKLO_SVE_Zd_SVE_Zn(
            SUNPKLO_SVE_Zd_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for SUNPKLO_SVE_Zd_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SUQADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "suqadd",
        aliases: &[],
        opcode: 0x441c8000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::SUQADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(
            SUQADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for SUQADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SUQADD_Vd_Vn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "suqadd",
        aliases: &[],
        opcode: 0xe203800,
        mask: 0xbf3ffc00,
        class: InsnClass::ASIMDMISC,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDMISC(ASIMDMISC::SUQADD_Vd_Vn(SUQADD_Vd_Vn::from(bits)))
    }
}
impl InsnOpcode for SUQADD_Vd_Vn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SUQADD_Sd_Sn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "suqadd",
        aliases: &[],
        opcode: 0x5e203800,
        mask: 0xff3ffc00,
        class: InsnClass::ASISDMISC,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMD_SCALAR_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDMISC(ASISDMISC::SUQADD_Sd_Sn(SUQADD_Sd_Sn::from(bits)))
    }
}
impl InsnOpcode for SUQADD_Sd_Sn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SUVDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "suvdot",
        aliases: &[],
        opcode: 0xc1508038,
        mask: 0xfff09078,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off3_0,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_0,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn4,
                    lsb: 7,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm_INDEX2,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zm,
                        lsb: 16,
                        width: 4,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_10,
                        lsb: 10,
                        width: 2,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_4.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::SUVDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2(
            SUVDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2::from(bits),
        ))
    }
}
impl InsnOpcode for SUVDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SVC_EXCEPTION {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "svc",
        aliases: &[],
        opcode: 0xd4000001,
        mask: 0xffe0001f,
        class: InsnClass::EXCEPTION,
        feature_set: InsnFeatureSet::V8,
        operands: &[InsnOperand {
            kind: InsnOperandKind::EXCEPTION,
            class: InsnOperandClass::IMMEDIATE,
            qualifiers: &[],
            bit_fields: &[BitfieldSpec {
                bitfield: InsnBitField::imm16_5,
                lsb: 5,
                width: 16,
            }],
        }],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::EXCEPTION(EXCEPTION::SVC_EXCEPTION(SVC_EXCEPTION::from(bits)))
    }
}
impl InsnOpcode for SVC_EXCEPTION {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SVDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "svdot",
        aliases: &[],
        opcode: 0xc1500020,
        mask: 0xfff09038,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off3_0,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_0,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn2,
                    lsb: 6,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm_INDEX2,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zm,
                        lsb: 16,
                        width: 4,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_10,
                        lsb: 10,
                        width: 2,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::SVDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2(
            SVDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2::from(bits),
        ))
    }
}
impl InsnOpcode for SVDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SVDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "svdot",
        aliases: &[],
        opcode: 0xc1508020,
        mask: 0xfff09078,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off3_0,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_0,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn4,
                    lsb: 7,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm_INDEX2,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zm,
                        lsb: 16,
                        width: 4,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_10,
                        lsb: 10,
                        width: 2,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_4.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::SVDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2(
            SVDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2::from(bits),
        ))
    }
}
impl InsnOpcode for SVDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SVDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX1 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "svdot",
        aliases: &[],
        opcode: 0xc1d08808,
        mask: 0xfff09878,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2_I16I64,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off3_0,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_0,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn4,
                    lsb: 7,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm_INDEX1,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zm,
                        lsb: 16,
                        width: 4,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm1_10,
                        lsb: 10,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_4.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::SVDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX1(
            SVDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX1::from(bits),
        ))
    }
}
impl InsnOpcode for SVDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX1 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SWP_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "swp",
        aliases: &[],
        opcode: 0xb8208000,
        mask: 0xbfe0fc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LSE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_LSE_SZ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::SWP_Rs_Rt_ADDR_SIMPLE(
            SWP_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for SWP_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SWPA_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "swpa",
        aliases: &[],
        opcode: 0xb8a08000,
        mask: 0xbfe0fc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LSE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_LSE_SZ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::SWPA_Rs_Rt_ADDR_SIMPLE(
            SWPA_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for SWPA_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SWPAB_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "swpab",
        aliases: &[],
        opcode: 0x38a08000,
        mask: 0xffe0fc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LSE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::SWPAB_Rs_Rt_ADDR_SIMPLE(
            SWPAB_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for SWPAB_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SWPAH_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "swpah",
        aliases: &[],
        opcode: 0x78a08000,
        mask: 0xffe0fc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LSE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::SWPAH_Rs_Rt_ADDR_SIMPLE(
            SWPAH_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for SWPAH_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SWPAL_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "swpal",
        aliases: &[],
        opcode: 0xb8e08000,
        mask: 0xbfe0fc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LSE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_LSE_SZ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::SWPAL_Rs_Rt_ADDR_SIMPLE(
            SWPAL_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for SWPAL_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SWPALB_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "swpalb",
        aliases: &[],
        opcode: 0x38e08000,
        mask: 0xffe0fc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LSE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::SWPALB_Rs_Rt_ADDR_SIMPLE(
            SWPALB_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for SWPALB_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SWPALH_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "swpalh",
        aliases: &[],
        opcode: 0x78e08000,
        mask: 0xffe0fc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LSE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::SWPALH_Rs_Rt_ADDR_SIMPLE(
            SWPALH_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for SWPALH_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SWPB_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "swpb",
        aliases: &[],
        opcode: 0x38208000,
        mask: 0xffe0fc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LSE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::SWPB_Rs_Rt_ADDR_SIMPLE(
            SWPB_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for SWPB_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SWPH_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "swph",
        aliases: &[],
        opcode: 0x78208000,
        mask: 0xffe0fc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LSE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::SWPH_Rs_Rt_ADDR_SIMPLE(
            SWPH_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for SWPH_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SWPL_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "swpl",
        aliases: &[],
        opcode: 0xb8608000,
        mask: 0xbfe0fc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LSE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_LSE_SZ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::SWPL_Rs_Rt_ADDR_SIMPLE(
            SWPL_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for SWPL_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SWPLB_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "swplb",
        aliases: &[],
        opcode: 0x38608000,
        mask: 0xffe0fc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LSE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::SWPLB_Rs_Rt_ADDR_SIMPLE(
            SWPLB_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for SWPLB_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SWPLH_Rs_Rt_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "swplh",
        aliases: &[],
        opcode: 0x78608000,
        mask: 0xffe0fc00,
        class: InsnClass::LSE_ATOMIC,
        feature_set: InsnFeatureSet::LSE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rs,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rs,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE_ATOMIC(LSE_ATOMIC::SWPLH_Rs_Rt_ADDR_SIMPLE(
            SWPLH_Rs_Rt_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for SWPLH_Rs_Rt_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SWPP_LSE128_Rt_LSE128_Rt2_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "swpp",
        aliases: &[],
        opcode: 0x19208000,
        mask: 0xffe0fc00,
        class: InsnClass::LSE128_ATOMIC,
        feature_set: InsnFeatureSet::LSE128,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::LSE128_Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::LSE128_Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::LSE128_Rt2,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::LSE128_Rt2,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE128_ATOMIC(LSE128_ATOMIC::SWPP_LSE128_Rt_LSE128_Rt2_ADDR_SIMPLE(
            SWPP_LSE128_Rt_LSE128_Rt2_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for SWPP_LSE128_Rt_LSE128_Rt2_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SWPPA_LSE128_Rt_LSE128_Rt2_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "swppa",
        aliases: &[],
        opcode: 0x19a08000,
        mask: 0xffe0fc00,
        class: InsnClass::LSE128_ATOMIC,
        feature_set: InsnFeatureSet::LSE128,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::LSE128_Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::LSE128_Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::LSE128_Rt2,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::LSE128_Rt2,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE128_ATOMIC(LSE128_ATOMIC::SWPPA_LSE128_Rt_LSE128_Rt2_ADDR_SIMPLE(
            SWPPA_LSE128_Rt_LSE128_Rt2_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for SWPPA_LSE128_Rt_LSE128_Rt2_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SWPPAL_LSE128_Rt_LSE128_Rt2_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "swppal",
        aliases: &[],
        opcode: 0x19e08000,
        mask: 0xffe0fc00,
        class: InsnClass::LSE128_ATOMIC,
        feature_set: InsnFeatureSet::LSE128,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::LSE128_Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::LSE128_Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::LSE128_Rt2,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::LSE128_Rt2,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE128_ATOMIC(LSE128_ATOMIC::SWPPAL_LSE128_Rt_LSE128_Rt2_ADDR_SIMPLE(
            SWPPAL_LSE128_Rt_LSE128_Rt2_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for SWPPAL_LSE128_Rt_LSE128_Rt2_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SWPPL_LSE128_Rt_LSE128_Rt2_ADDR_SIMPLE {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "swppl",
        aliases: &[],
        opcode: 0x19608000,
        mask: 0xffe0fc00,
        class: InsnClass::LSE128_ATOMIC,
        feature_set: InsnFeatureSet::LSE128,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::LSE128_Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::LSE128_Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::LSE128_Rt2,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::LSE128_Rt2,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_SIMPLE,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::LSE128_ATOMIC(LSE128_ATOMIC::SWPPL_LSE128_Rt_LSE128_Rt2_ADDR_SIMPLE(
            SWPPL_LSE128_Rt_LSE128_Rt2_ADDR_SIMPLE::from(bits),
        ))
    }
}
impl InsnOpcode for SWPPL_LSE128_Rt_LSE128_Rt2_ADDR_SIMPLE {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SXTB_SVE_Zd_SVE_Pg3_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sxtb",
        aliases: &[],
        opcode: 0x410a000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M, InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::SXTB_SVE_Zd_SVE_Pg3_SVE_Zn(
            SXTB_SVE_Zd_SVE_Pg3_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for SXTB_SVE_Zd_SVE_Pg3_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SXTH_SVE_Zd_SVE_Pg3_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sxth",
        aliases: &[],
        opcode: 0x492a000,
        mask: 0xffbfe000,
        class: InsnClass::SVE_SIZE_SD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M, InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_SD(SVE_SIZE_SD::SXTH_SVE_Zd_SVE_Pg3_SVE_Zn(
            SXTH_SVE_Zd_SVE_Pg3_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for SXTH_SVE_Zd_SVE_Pg3_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SXTW_SVE_Zd_SVE_Pg3_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sxtw",
        aliases: &[],
        opcode: 0x4d4a000,
        mask: 0xffffe000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::SXTW_SVE_Zd_SVE_Pg3_SVE_Zn(
            SXTW_SVE_Zd_SVE_Pg3_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for SXTW_SVE_Zd_SVE_Pg3_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SYS_UIMM3_OP1_CRn_CRm_UIMM3_OP2_Rt {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sys",
        aliases: &[],
        opcode: 0xd5080000,
        mask: 0xfff80000,
        class: InsnClass::IC_SYSTEM,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::UIMM3_OP1,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::op1,
                    lsb: 16,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::CRn,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::CRn,
                    lsb: 12,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::CRm,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::CRm,
                    lsb: 8,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::UIMM3_OP2,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::op2,
                    lsb: 5,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ALIAS.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::IC_SYSTEM(IC_SYSTEM::SYS_UIMM3_OP1_CRn_CRm_UIMM3_OP2_Rt(
            SYS_UIMM3_OP1_CRn_CRm_UIMM3_OP2_Rt::from(bits),
        ))
    }
}
impl InsnOpcode for SYS_UIMM3_OP1_CRn_CRm_UIMM3_OP2_Rt {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SYSL_Rt_UIMM3_OP1_CRn_CRm_UIMM3_OP2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sysl",
        aliases: &[],
        opcode: 0xd5280000,
        mask: 0xfff80000,
        class: InsnClass::IC_SYSTEM,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::UIMM3_OP1,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::op1,
                    lsb: 16,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::CRn,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::CRn,
                    lsb: 12,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::CRm,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::CRm,
                    lsb: 8,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::UIMM3_OP2,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::op2,
                    lsb: 5,
                    width: 3,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::IC_SYSTEM(IC_SYSTEM::SYSL_Rt_UIMM3_OP1_CRn_CRm_UIMM3_OP2(
            SYSL_Rt_UIMM3_OP1_CRn_CRm_UIMM3_OP2::from(bits),
        ))
    }
}
impl InsnOpcode for SYSL_Rt_UIMM3_OP1_CRn_CRm_UIMM3_OP2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl SYSP_UIMM3_OP1_CRn_CRm_UIMM3_OP2_Rt_PAIRREG_OR_XZR {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "sysp",
        aliases: &[],
        opcode: 0xd5480000,
        mask: 0xfff80000,
        class: InsnClass::IC_SYSTEM,
        feature_set: InsnFeatureSet::D128,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::UIMM3_OP1,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::op1,
                    lsb: 16,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::CRn,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::CRn,
                    lsb: 12,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::CRm,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::CRm,
                    lsb: 8,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::UIMM3_OP2,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::op2,
                    lsb: 5,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::PAIRREG_OR_XZR,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_ALIAS.bits() | InsnFlags::HAS_NARROW.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::IC_SYSTEM(
            IC_SYSTEM::SYSP_UIMM3_OP1_CRn_CRm_UIMM3_OP2_Rt_PAIRREG_OR_XZR(
                SYSP_UIMM3_OP1_CRn_CRm_UIMM3_OP2_Rt_PAIRREG_OR_XZR::from(bits),
            ),
        )
    }
}
impl InsnOpcode for SYSP_UIMM3_OP1_CRn_CRm_UIMM3_OP2_Rt_PAIRREG_OR_XZR {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl TBL_SVE_Zd_SVE_ZnxN_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "tbl",
        aliases: &[],
        opcode: 0x5203000,
        mask: 0xff20fc00,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ZnxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_1.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::TBL_SVE_Zd_SVE_ZnxN_SVE_Zm_16(
            TBL_SVE_Zd_SVE_ZnxN_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for TBL_SVE_Zd_SVE_ZnxN_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl TBL_SVE_Zd_S_B_SVE_ZnxN_S_B_SVE_Zm_16_S_B {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "tbl",
        aliases: &[],
        opcode: 0x5202800,
        mask: 0xff20fc00,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ZnxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::TBL_SVE_Zd_S_B_SVE_ZnxN_S_B_SVE_Zm_16_S_B(
            TBL_SVE_Zd_S_B_SVE_ZnxN_S_B_SVE_Zm_16_S_B::from(bits),
        ))
    }
}
impl InsnOpcode for TBL_SVE_Zd_S_B_SVE_ZnxN_S_B_SVE_Zm_16_S_B {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl TBL_Vd_LVn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "tbl",
        aliases: &[],
        opcode: 0xe000000,
        mask: 0xbfe09c00,
        class: InsnClass::ASIMDTBL,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::LVn,
                class: InsnOperandClass::SIMD_REGLIST,
                qualifiers: &[InsnOperandQualifier::V_16B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDTBL(ASIMDTBL::TBL_Vd_LVn_Vm(TBL_Vd_LVn_Vm::from(bits)))
    }
}
impl InsnOpcode for TBL_Vd_LVn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl TBNZ_Rt_BIT_NUM_ADDR_PCREL14 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "tbnz",
        aliases: &[],
        opcode: 0x37000000,
        mask: 0x7f000000,
        class: InsnClass::TESTBRANCH,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::BIT_NUM,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[InsnOperandQualifier::imm_0_63],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::b5,
                        lsb: 31,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::b40,
                        lsb: 19,
                        width: 5,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_PCREL14,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::imm14,
                    lsb: 5,
                    width: 14,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::TESTBRANCH(TESTBRANCH::TBNZ_Rt_BIT_NUM_ADDR_PCREL14(
            TBNZ_Rt_BIT_NUM_ADDR_PCREL14::from(bits),
        ))
    }
}
impl InsnOpcode for TBNZ_Rt_BIT_NUM_ADDR_PCREL14 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl TBX_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "tbx",
        aliases: &[],
        opcode: 0x5202c00,
        mask: 0xff20fc00,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::TBX_SVE_Zd_SVE_Zn_SVE_Zm_16(
            TBX_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for TBX_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl TBX_Vd_LVn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "tbx",
        aliases: &[],
        opcode: 0xe001000,
        mask: 0xbfe09c00,
        class: InsnClass::ASIMDTBL,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::LVn,
                class: InsnOperandClass::SIMD_REGLIST,
                qualifiers: &[InsnOperandQualifier::V_16B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDTBL(ASIMDTBL::TBX_Vd_LVn_Vm(TBX_Vd_LVn_Vm::from(bits)))
    }
}
impl InsnOpcode for TBX_Vd_LVn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl TBZ_Rt_BIT_NUM_ADDR_PCREL14 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "tbz",
        aliases: &[],
        opcode: 0x36000000,
        mask: 0x7f000000,
        class: InsnClass::TESTBRANCH,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rt,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rt,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::BIT_NUM,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[InsnOperandQualifier::imm_0_63],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::b5,
                        lsb: 31,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::b40,
                        lsb: 19,
                        width: 5,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::ADDR_PCREL14,
                class: InsnOperandClass::ADDRESS,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::imm14,
                    lsb: 5,
                    width: 14,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::TESTBRANCH(TESTBRANCH::TBZ_Rt_BIT_NUM_ADDR_PCREL14(
            TBZ_Rt_BIT_NUM_ADDR_PCREL14::from(bits),
        ))
    }
}
impl InsnOpcode for TBZ_Rt_BIT_NUM_ADDR_PCREL14 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl TCANCEL_TME_UIMM16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "tcancel",
        aliases: &[],
        opcode: 0xd4600000,
        mask: 0xffe0001f,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::TME,
        operands: &[InsnOperand {
            kind: InsnOperandKind::TME_UIMM16,
            class: InsnOperandClass::IMMEDIATE,
            qualifiers: &[],
            bit_fields: &[BitfieldSpec {
                bitfield: InsnBitField::imm16_5,
                lsb: 5,
                width: 16,
            }],
        }],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(AARCH64_MISC::TCANCEL_TME_UIMM16(TCANCEL_TME_UIMM16::from(
            bits,
        )))
    }
}
impl InsnOpcode for TCANCEL_TME_UIMM16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl TCOMMIT {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "tcommit",
        aliases: &[],
        opcode: 0xd503307f,
        mask: 0xffffffff,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::TME,
        operands: &[],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(AARCH64_MISC::TCOMMIT(TCOMMIT::from(bits)))
    }
}
impl InsnOpcode for TCOMMIT {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl TRN1_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "trn1",
        aliases: &[],
        opcode: 0x5a01800,
        mask: 0xffe0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::F64MM_SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_Q],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_Q],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_Q],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::TRN1_SVE_Zd_SVE_Zn_SVE_Zm_16(
            TRN1_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for TRN1_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl TRN1_SVE_Pd_SVE_Pn_SVE_Pm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "trn1",
        aliases: &[],
        opcode: 0x5205000,
        mask: 0xff30fe10,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Pd,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pd,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pn,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pn,
                    lsb: 5,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pm,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pm,
                    lsb: 16,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::TRN1_SVE_Pd_SVE_Pn_SVE_Pm(
            TRN1_SVE_Pd_SVE_Pn_SVE_Pm::from(bits),
        ))
    }
}
impl InsnOpcode for TRN1_SVE_Pd_SVE_Pn_SVE_Pm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl TRN1_SVE_Zd_S_B_SVE_Zn_S_B_SVE_Zm_16_S_B {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "trn1",
        aliases: &[],
        opcode: 0x5207000,
        mask: 0xff20fc00,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::TRN1_SVE_Zd_S_B_SVE_Zn_S_B_SVE_Zm_16_S_B(
            TRN1_SVE_Zd_S_B_SVE_Zn_S_B_SVE_Zm_16_S_B::from(bits),
        ))
    }
}
impl InsnOpcode for TRN1_SVE_Zd_S_B_SVE_Zn_S_B_SVE_Zm_16_S_B {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl TRN1_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "trn1",
        aliases: &[],
        opcode: 0xe002800,
        mask: 0xbf20fc00,
        class: InsnClass::ASIMDPERM,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDPERM(ASIMDPERM::TRN1_Vd_Vn_Vm(TRN1_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for TRN1_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl TRN2_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "trn2",
        aliases: &[],
        opcode: 0x5a01c00,
        mask: 0xffe0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::F64MM_SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_Q],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_Q],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_Q],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::TRN2_SVE_Zd_SVE_Zn_SVE_Zm_16(
            TRN2_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for TRN2_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl TRN2_SVE_Pd_SVE_Pn_SVE_Pm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "trn2",
        aliases: &[],
        opcode: 0x5205400,
        mask: 0xff30fe10,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Pd,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pd,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pn,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pn,
                    lsb: 5,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pm,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pm,
                    lsb: 16,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::TRN2_SVE_Pd_SVE_Pn_SVE_Pm(
            TRN2_SVE_Pd_SVE_Pn_SVE_Pm::from(bits),
        ))
    }
}
impl InsnOpcode for TRN2_SVE_Pd_SVE_Pn_SVE_Pm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl TRN2_SVE_Zd_S_B_SVE_Zn_S_B_SVE_Zm_16_S_B {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "trn2",
        aliases: &[],
        opcode: 0x5207400,
        mask: 0xff20fc00,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::TRN2_SVE_Zd_S_B_SVE_Zn_S_B_SVE_Zm_16_S_B(
            TRN2_SVE_Zd_S_B_SVE_Zn_S_B_SVE_Zm_16_S_B::from(bits),
        ))
    }
}
impl InsnOpcode for TRN2_SVE_Zd_S_B_SVE_Zn_S_B_SVE_Zm_16_S_B {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl TRN2_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "trn2",
        aliases: &[],
        opcode: 0xe006800,
        mask: 0xbf20fc00,
        class: InsnClass::ASIMDPERM,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDPERM(ASIMDPERM::TRN2_Vd_Vn_Vm(TRN2_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for TRN2_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl TSTART_Rd {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "tstart",
        aliases: &[],
        opcode: 0xd5233060,
        mask: 0xffffffe0,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::TME,
        operands: &[InsnOperand {
            kind: InsnOperandKind::Rd,
            class: InsnOperandClass::INT_REG,
            qualifiers: &[],
            bit_fields: &[BitfieldSpec {
                bitfield: InsnBitField::Rd,
                lsb: 0,
                width: 5,
            }],
        }],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(AARCH64_MISC::TSTART_Rd(TSTART_Rd::from(bits)))
    }
}
impl InsnOpcode for TSTART_Rd {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl TTEST_Rd {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ttest",
        aliases: &[],
        opcode: 0xd5233160,
        mask: 0xffffffe0,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::TME,
        operands: &[InsnOperand {
            kind: InsnOperandKind::Rd,
            class: InsnOperandClass::INT_REG,
            qualifiers: &[],
            bit_fields: &[BitfieldSpec {
                bitfield: InsnBitField::Rd,
                lsb: 0,
                width: 5,
            }],
        }],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(AARCH64_MISC::TTEST_Rd(TTEST_Rd::from(bits)))
    }
}
impl InsnOpcode for TTEST_Rd {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UABA_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uaba",
        aliases: &[],
        opcode: 0x4500fc00,
        mask: 0xff20fc00,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::UABA_SVE_Zd_SVE_Zn_SVE_Zm_16(
            UABA_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for UABA_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UABA_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uaba",
        aliases: &[],
        opcode: 0x2e207c00,
        mask: 0xbf20fc00,
        class: InsnClass::ASIMDSAME,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSAME(ASIMDSAME::UABA_Vd_Vn_Vm(UABA_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for UABA_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UABAL_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uabal",
        aliases: &[],
        opcode: 0x2e205000,
        mask: 0xff20fc00,
        class: InsnClass::ASIMDDIFF,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8H, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_4H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_4H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDDIFF(ASIMDDIFF::UABAL_Vd_Vn_Vm(UABAL_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for UABAL_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UABAL2_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uabal2",
        aliases: &[],
        opcode: 0x6e205000,
        mask: 0xff20fc00,
        class: InsnClass::ASIMDDIFF,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8H, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_16B, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_16B, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDDIFF(ASIMDDIFF::UABAL2_Vd_Vn_Vm(UABAL2_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for UABAL2_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UABALB_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uabalb",
        aliases: &[],
        opcode: 0x4500c800,
        mask: 0xff20fc00,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::UABALB_SVE_Zd_SVE_Zn_SVE_Zm_16(
            UABALB_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for UABALB_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UABALT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uabalt",
        aliases: &[],
        opcode: 0x4500cc00,
        mask: 0xff20fc00,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::UABALT_SVE_Zd_SVE_Zn_SVE_Zm_16(
            UABALT_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for UABALT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UABD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uabd",
        aliases: &[],
        opcode: 0x40d0000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_5,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_5,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::UABD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(
            UABD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5::from(bits),
        ))
    }
}
impl InsnOpcode for UABD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UABD_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uabd",
        aliases: &[],
        opcode: 0x2e207400,
        mask: 0xbf20fc00,
        class: InsnClass::ASIMDSAME,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSAME(ASIMDSAME::UABD_Vd_Vn_Vm(UABD_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for UABD_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UABDL_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uabdl",
        aliases: &[],
        opcode: 0x2e207000,
        mask: 0xff20fc00,
        class: InsnClass::ASIMDDIFF,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8H, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_4H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_4H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDDIFF(ASIMDDIFF::UABDL_Vd_Vn_Vm(UABDL_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for UABDL_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UABDL2_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uabdl2",
        aliases: &[],
        opcode: 0x6e207000,
        mask: 0xff20fc00,
        class: InsnClass::ASIMDDIFF,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8H, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_16B, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_16B, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDDIFF(ASIMDDIFF::UABDL2_Vd_Vn_Vm(UABDL2_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for UABDL2_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UABDLB_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uabdlb",
        aliases: &[],
        opcode: 0x45003800,
        mask: 0xff20fc00,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::UABDLB_SVE_Zd_SVE_Zn_SVE_Zm_16(
            UABDLB_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for UABDLB_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UABDLT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uabdlt",
        aliases: &[],
        opcode: 0x45003c00,
        mask: 0xff20fc00,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::UABDLT_SVE_Zd_SVE_Zn_SVE_Zm_16(
            UABDLT_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for UABDLT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UADALP_SVE_Zd_SVE_Pg3_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uadalp",
        aliases: &[],
        opcode: 0x4405a000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M, InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::UADALP_SVE_Zd_SVE_Pg3_SVE_Zn(
            UADALP_SVE_Zd_SVE_Pg3_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for UADALP_SVE_Zd_SVE_Pg3_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UADALP_Vd_Vn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uadalp",
        aliases: &[],
        opcode: 0x2e206800,
        mask: 0xbf3ffc00,
        class: InsnClass::ASIMDMISC,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDMISC(ASIMDMISC::UADALP_Vd_Vn(UADALP_Vd_Vn::from(bits)))
    }
}
impl InsnOpcode for UADALP_Vd_Vn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UADDL_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uaddl",
        aliases: &[],
        opcode: 0x2e200000,
        mask: 0xff20fc00,
        class: InsnClass::ASIMDDIFF,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8H, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_4H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_4H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDDIFF(ASIMDDIFF::UADDL_Vd_Vn_Vm(UADDL_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for UADDL_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UADDL2_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uaddl2",
        aliases: &[],
        opcode: 0x6e200000,
        mask: 0xff20fc00,
        class: InsnClass::ASIMDDIFF,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8H, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_16B, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_16B, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDDIFF(ASIMDDIFF::UADDL2_Vd_Vn_Vm(UADDL2_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for UADDL2_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UADDLB_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uaddlb",
        aliases: &[],
        opcode: 0x45000800,
        mask: 0xff20fc00,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::UADDLB_SVE_Zd_SVE_Zn_SVE_Zm_16(
            UADDLB_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for UADDLB_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UADDLP_Vd_Vn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uaddlp",
        aliases: &[],
        opcode: 0x2e202800,
        mask: 0xbf3ffc00,
        class: InsnClass::ASIMDMISC,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDMISC(ASIMDMISC::UADDLP_Vd_Vn(UADDLP_Vd_Vn::from(bits)))
    }
}
impl InsnOpcode for UADDLP_Vd_Vn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UADDLT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uaddlt",
        aliases: &[],
        opcode: 0x45000c00,
        mask: 0xff20fc00,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::UADDLT_SVE_Zd_SVE_Zn_SVE_Zm_16(
            UADDLT_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for UADDLT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UADDLV_Fd_Vn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uaddlv",
        aliases: &[],
        opcode: 0x2e303800,
        mask: 0xbf3ffc00,
        class: InsnClass::ASIMDALL,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Fd,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDALL(ASIMDALL::UADDLV_Fd_Vn(UADDLV_Fd_Vn::from(bits)))
    }
}
impl InsnOpcode for UADDLV_Fd_Vn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UADDV_SVE_Vd_SVE_Pg3_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uaddv",
        aliases: &[],
        opcode: 0x4012000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::S_D, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Vd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::UADDV_SVE_Vd_SVE_Pg3_SVE_Zn(
            UADDV_SVE_Vd_SVE_Pg3_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for UADDV_SVE_Vd_SVE_Pg3_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UADDW_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uaddw",
        aliases: &[],
        opcode: 0x2e201000,
        mask: 0xff20fc00,
        class: InsnClass::ASIMDDIFF,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8H, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8H, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_4H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDDIFF(ASIMDDIFF::UADDW_Vd_Vn_Vm(UADDW_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for UADDW_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UADDW2_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uaddw2",
        aliases: &[],
        opcode: 0x6e201000,
        mask: 0xff20fc00,
        class: InsnClass::ASIMDDIFF,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8H, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8H, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_16B, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDDIFF(ASIMDDIFF::UADDW2_Vd_Vn_Vm(UADDW2_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for UADDW2_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UADDWB_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uaddwb",
        aliases: &[],
        opcode: 0x45004800,
        mask: 0xff20fc00,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::UADDWB_SVE_Zd_SVE_Zn_SVE_Zm_16(
            UADDWB_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for UADDWB_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UADDWT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uaddwt",
        aliases: &[],
        opcode: 0x45004c00,
        mask: 0xff20fc00,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::UADDWT_SVE_Zd_SVE_Zn_SVE_Zm_16(
            UADDWT_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for UADDWT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UBFM_Rd_Rn_IMMR_IMMS {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ubfm",
        aliases: &[],
        opcode: 0x53000000,
        mask: 0x7f800000,
        class: InsnClass::BITFIELD,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::IMMR,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[
                    InsnOperandQualifier::imm_0_31,
                    InsnOperandQualifier::imm_0_63,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::immr,
                    lsb: 16,
                    width: 6,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::IMMS,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[
                    InsnOperandQualifier::imm_0_31,
                    InsnOperandQualifier::imm_0_63,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::imm6_10,
                    lsb: 10,
                    width: 6,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_ALIAS.bits()
                | InsnFlags::HAS_N_FIELD.bits()
                | InsnFlags::HAS_SF_FIELD.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::BITFIELD(BITFIELD::UBFM_Rd_Rn_IMMR_IMMS(UBFM_Rd_Rn_IMMR_IMMS::from(
            bits,
        )))
    }
}
impl InsnOpcode for UBFM_Rd_Rn_IMMR_IMMS {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UCLAMP_SME_Zdnx2_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uclamp",
        aliases: &[],
        opcode: 0xc120c401,
        mask: 0xff20fc01,
        class: InsnClass::SME_SIZE_22,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn2,
                    lsb: 1,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_SIZE_22(SME_SIZE_22::UCLAMP_SME_Zdnx2_SVE_Zn_SVE_Zm_16(
            UCLAMP_SME_Zdnx2_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for UCLAMP_SME_Zdnx2_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UCLAMP_SME_Zdnx4_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uclamp",
        aliases: &[],
        opcode: 0xc120cc01,
        mask: 0xff20fc03,
        class: InsnClass::SME_SIZE_22,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn4,
                    lsb: 2,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_SIZE_22(SME_SIZE_22::UCLAMP_SME_Zdnx4_SVE_Zn_SVE_Zm_16(
            UCLAMP_SME_Zdnx4_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for UCLAMP_SME_Zdnx4_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UCLAMP_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uclamp",
        aliases: &[],
        opcode: 0x4400c400,
        mask: 0xff20fc00,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SME,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::UCLAMP_SVE_Zd_SVE_Zn_SVE_Zm_16(
            UCLAMP_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for UCLAMP_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UCVTF_SME_Zdnx2_SME_Znx2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ucvtf",
        aliases: &[],
        opcode: 0xc122e020,
        mask: 0xfffffc21,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn2,
                    lsb: 1,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn2,
                    lsb: 6,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::UCVTF_SME_Zdnx2_SME_Znx2(
            UCVTF_SME_Zdnx2_SME_Znx2::from(bits),
        ))
    }
}
impl InsnOpcode for UCVTF_SME_Zdnx2_SME_Znx2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UCVTF_SME_Zdnx4_SME_Znx4 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ucvtf",
        aliases: &[],
        opcode: 0xc132e020,
        mask: 0xfffffc63,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn4,
                    lsb: 2,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn4,
                    lsb: 7,
                    width: 3,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::UCVTF_SME_Zdnx4_SME_Znx4(
            UCVTF_SME_Zdnx4_SME_Znx4::from(bits),
        ))
    }
}
impl InsnOpcode for UCVTF_SME_Zdnx4_SME_Znx4 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UCVTF_SVE_Zd_SVE_Pg3_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ucvtf",
        aliases: &[],
        opcode: 0x65d1a000,
        mask: 0xffffe000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::UCVTF_SVE_Zd_SVE_Pg3_SVE_Zn(
            UCVTF_SVE_Zd_SVE_Pg3_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for UCVTF_SVE_Zd_SVE_Pg3_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UCVTF_SVE_Zd_S_S_SVE_Pg3_P_M_SVE_Zn_S_S {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ucvtf",
        aliases: &[],
        opcode: 0x6595a000,
        mask: 0xffffe000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::UCVTF_SVE_Zd_S_S_SVE_Pg3_P_M_SVE_Zn_S_S(
            UCVTF_SVE_Zd_S_S_SVE_Pg3_P_M_SVE_Zn_S_S::from(bits),
        ))
    }
}
impl InsnOpcode for UCVTF_SVE_Zd_S_S_SVE_Pg3_P_M_SVE_Zn_S_S {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UCVTF_SVE_Zd_S_H_SVE_Pg3_P_M_SVE_Zn_S_S {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ucvtf",
        aliases: &[],
        opcode: 0x6555a000,
        mask: 0xffffe000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::UCVTF_SVE_Zd_S_H_SVE_Pg3_P_M_SVE_Zn_S_S(
            UCVTF_SVE_Zd_S_H_SVE_Pg3_P_M_SVE_Zn_S_S::from(bits),
        ))
    }
}
impl InsnOpcode for UCVTF_SVE_Zd_S_H_SVE_Pg3_P_M_SVE_Zn_S_S {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UCVTF_SVE_Zd_S_S_SVE_Pg3_P_M_SVE_Zn_S_D {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ucvtf",
        aliases: &[],
        opcode: 0x65d5a000,
        mask: 0xffffe000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::UCVTF_SVE_Zd_S_S_SVE_Pg3_P_M_SVE_Zn_S_D(
            UCVTF_SVE_Zd_S_S_SVE_Pg3_P_M_SVE_Zn_S_D::from(bits),
        ))
    }
}
impl InsnOpcode for UCVTF_SVE_Zd_S_S_SVE_Pg3_P_M_SVE_Zn_S_D {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UCVTF_SVE_Zd_S_H_SVE_Pg3_P_M_SVE_Zn_S_H {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ucvtf",
        aliases: &[],
        opcode: 0x6553a000,
        mask: 0xffffe000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::UCVTF_SVE_Zd_S_H_SVE_Pg3_P_M_SVE_Zn_S_H(
            UCVTF_SVE_Zd_S_H_SVE_Pg3_P_M_SVE_Zn_S_H::from(bits),
        ))
    }
}
impl InsnOpcode for UCVTF_SVE_Zd_S_H_SVE_Pg3_P_M_SVE_Zn_S_H {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UCVTF_SVE_Zd_S_H_SVE_Pg3_P_M_SVE_Zn_S_D {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ucvtf",
        aliases: &[],
        opcode: 0x6557a000,
        mask: 0xffffe000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::UCVTF_SVE_Zd_S_H_SVE_Pg3_P_M_SVE_Zn_S_D(
            UCVTF_SVE_Zd_S_H_SVE_Pg3_P_M_SVE_Zn_S_D::from(bits),
        ))
    }
}
impl InsnOpcode for UCVTF_SVE_Zd_S_H_SVE_Pg3_P_M_SVE_Zn_S_D {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UCVTF_SVE_Zd_S_D_SVE_Pg3_P_M_SVE_Zn_S_D {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ucvtf",
        aliases: &[],
        opcode: 0x65d7a000,
        mask: 0xffffe000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::UCVTF_SVE_Zd_S_D_SVE_Pg3_P_M_SVE_Zn_S_D(
            UCVTF_SVE_Zd_S_D_SVE_Pg3_P_M_SVE_Zn_S_D::from(bits),
        ))
    }
}
impl InsnOpcode for UCVTF_SVE_Zd_S_D_SVE_Pg3_P_M_SVE_Zn_S_D {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UCVTF_Fd_Rn_FBITS {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ucvtf",
        aliases: &[],
        opcode: 0x1ec30000,
        mask: 0x7fff0000,
        class: InsnClass::FLOAT2FIX,
        feature_set: InsnFeatureSet::FP_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Fd,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::FBITS,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[
                    InsnOperandQualifier::imm_1_32,
                    InsnOperandQualifier::imm_1_64,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::scale,
                    lsb: 10,
                    width: 6,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_FPTYPE_FIELD.bits() | InsnFlags::HAS_SF_FIELD.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::FLOAT2FIX(FLOAT2FIX::UCVTF_Fd_Rn_FBITS(UCVTF_Fd_Rn_FBITS::from(bits)))
    }
}
impl InsnOpcode for UCVTF_Fd_Rn_FBITS {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UCVTF_Fd_S_D_Rn_W_FBITS_imm_1_32 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ucvtf",
        aliases: &[],
        opcode: 0x1e030000,
        mask: 0x7f3f0000,
        class: InsnClass::FLOAT2FIX,
        feature_set: InsnFeatureSet::FP,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Fd,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_D, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::FBITS,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[
                    InsnOperandQualifier::imm_1_32,
                    InsnOperandQualifier::imm_1_32,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::scale,
                    lsb: 10,
                    width: 6,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_FPTYPE_FIELD.bits() | InsnFlags::HAS_SF_FIELD.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::FLOAT2FIX(FLOAT2FIX::UCVTF_Fd_S_D_Rn_W_FBITS_imm_1_32(
            UCVTF_Fd_S_D_Rn_W_FBITS_imm_1_32::from(bits),
        ))
    }
}
impl InsnOpcode for UCVTF_Fd_S_D_Rn_W_FBITS_imm_1_32 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UCVTF_Vd_Vn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ucvtf",
        aliases: &[],
        opcode: 0x2e21d800,
        mask: 0xbfbffc00,
        class: InsnClass::ASIMDMISC,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDMISC(ASIMDMISC::UCVTF_Vd_Vn(UCVTF_Vd_Vn::from(bits)))
    }
}
impl InsnOpcode for UCVTF_Vd_Vn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UCVTF_Vd_V_4H_Vn_V_4H {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ucvtf",
        aliases: &[],
        opcode: 0x2e79d800,
        mask: 0xbffffc00,
        class: InsnClass::ASIMDMISC,
        feature_set: InsnFeatureSet::SIMD_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDMISC(ASIMDMISC::UCVTF_Vd_V_4H_Vn_V_4H(
            UCVTF_Vd_V_4H_Vn_V_4H::from(bits),
        ))
    }
}
impl InsnOpcode for UCVTF_Vd_V_4H_Vn_V_4H {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UCVTF_Fd_Rn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ucvtf",
        aliases: &[],
        opcode: 0x1ee30000,
        mask: 0x7ffffc00,
        class: InsnClass::FLOAT2INT,
        feature_set: InsnFeatureSet::FP_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Fd,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_FPTYPE_FIELD.bits() | InsnFlags::HAS_SF_FIELD.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::FLOAT2INT(FLOAT2INT::UCVTF_Fd_Rn(UCVTF_Fd_Rn::from(bits)))
    }
}
impl InsnOpcode for UCVTF_Fd_Rn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UCVTF_Fd_S_D_Rn_W {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ucvtf",
        aliases: &[],
        opcode: 0x1e230000,
        mask: 0x7f3ffc00,
        class: InsnClass::FLOAT2INT,
        feature_set: InsnFeatureSet::FP,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Fd,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_FPTYPE_FIELD.bits() | InsnFlags::HAS_SF_FIELD.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::FLOAT2INT(FLOAT2INT::UCVTF_Fd_S_D_Rn_W(UCVTF_Fd_S_D_Rn_W::from(bits)))
    }
}
impl InsnOpcode for UCVTF_Fd_S_D_Rn_W {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UCVTF_Sd_Sn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ucvtf",
        aliases: &[],
        opcode: 0x7e21d800,
        mask: 0xffbffc00,
        class: InsnClass::ASISDMISC,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMD_SCALAR_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDMISC(ASISDMISC::UCVTF_Sd_Sn(UCVTF_Sd_Sn::from(bits)))
    }
}
impl InsnOpcode for UCVTF_Sd_Sn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UCVTF_Sd_S_H_Sn_S_H {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ucvtf",
        aliases: &[],
        opcode: 0x7e79d800,
        mask: 0xfffffc00,
        class: InsnClass::ASISDMISC,
        feature_set: InsnFeatureSet::SIMD_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMD_SCALAR_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDMISC(ASISDMISC::UCVTF_Sd_S_H_Sn_S_H(UCVTF_Sd_S_H_Sn_S_H::from(
            bits,
        )))
    }
}
impl InsnOpcode for UCVTF_Sd_S_H_Sn_S_H {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UCVTF_Vd_Vn_IMM_VLSR {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ucvtf",
        aliases: &[],
        opcode: 0x2f10e400,
        mask: 0xbf90fc00,
        class: InsnClass::ASIMDSHF,
        feature_set: InsnFeatureSet::SIMD_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::IMM_VLSR,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_8H],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSHF(ASIMDSHF::UCVTF_Vd_Vn_IMM_VLSR(UCVTF_Vd_Vn_IMM_VLSR::from(
            bits,
        )))
    }
}
impl InsnOpcode for UCVTF_Vd_Vn_IMM_VLSR {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UCVTF_Vd_V_2S_Vn_V_2S_IMM_VLSR_V_2S {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ucvtf",
        aliases: &[],
        opcode: 0x2f00e400,
        mask: 0xbf80fc00,
        class: InsnClass::ASIMDSHF,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::IMM_VLSR,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[InsnOperandQualifier::V_2S, InsnOperandQualifier::V_4S],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSHF(ASIMDSHF::UCVTF_Vd_V_2S_Vn_V_2S_IMM_VLSR_V_2S(
            UCVTF_Vd_V_2S_Vn_V_2S_IMM_VLSR_V_2S::from(bits),
        ))
    }
}
impl InsnOpcode for UCVTF_Vd_V_2S_Vn_V_2S_IMM_VLSR_V_2S {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UCVTF_Sd_Sn_IMM_VLSR {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ucvtf",
        aliases: &[],
        opcode: 0x7f10e400,
        mask: 0xff90fc00,
        class: InsnClass::ASISDSHF,
        feature_set: InsnFeatureSet::SIMD_F16,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::IMM_VLSR,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDSHF(ASISDSHF::UCVTF_Sd_Sn_IMM_VLSR(UCVTF_Sd_Sn_IMM_VLSR::from(
            bits,
        )))
    }
}
impl InsnOpcode for UCVTF_Sd_Sn_IMM_VLSR {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UCVTF_Sd_S_S_Sn_S_S_IMM_VLSR_S_S {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ucvtf",
        aliases: &[],
        opcode: 0x7f00e400,
        mask: 0xff80fc00,
        class: InsnClass::ASISDSHF,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::IMM_VLSR,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDSHF(ASISDSHF::UCVTF_Sd_S_S_Sn_S_S_IMM_VLSR_S_S(
            UCVTF_Sd_S_S_Sn_S_S_IMM_VLSR_S_S::from(bits),
        ))
    }
}
impl InsnOpcode for UCVTF_Sd_S_S_Sn_S_S_IMM_VLSR_S_S {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UDF_UNDEFINED {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "udf",
        aliases: &[],
        opcode: 0x000000,
        mask: 0xffff0000,
        class: InsnClass::EXCEPTION,
        feature_set: InsnFeatureSet::V8,
        operands: &[InsnOperand {
            kind: InsnOperandKind::UNDEFINED,
            class: InsnOperandClass::IMMEDIATE,
            qualifiers: &[],
            bit_fields: &[BitfieldSpec {
                bitfield: InsnBitField::imm16_0,
                lsb: 0,
                width: 16,
            }],
        }],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::EXCEPTION(EXCEPTION::UDF_UNDEFINED(UDF_UNDEFINED::from(bits)))
    }
}
impl InsnOpcode for UDF_UNDEFINED {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UDIV_Rd_Rn_Rm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "udiv",
        aliases: &[],
        opcode: 0x1ac00800,
        mask: 0x7fe0fc00,
        class: InsnClass::DP_2SRC,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rm,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SF_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::DP_2SRC(DP_2SRC::UDIV_Rd_Rn_Rm(UDIV_Rd_Rn_Rm::from(bits)))
    }
}
impl InsnOpcode for UDIV_Rd_Rn_Rm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UDIV_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "udiv",
        aliases: &[],
        opcode: 0x4950000,
        mask: 0xffbfe000,
        class: InsnClass::SVE_SIZE_SD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M, InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_5,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_5,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_SD(SVE_SIZE_SD::UDIV_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(
            UDIV_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5::from(bits),
        ))
    }
}
impl InsnOpcode for UDIV_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UDIVR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "udivr",
        aliases: &[],
        opcode: 0x4970000,
        mask: 0xffbfe000,
        class: InsnClass::SVE_SIZE_SD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M, InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_5,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_5,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_SD(SVE_SIZE_SD::UDIVR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(
            UDIVR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5::from(bits),
        ))
    }
}
impl InsnOpcode for UDIVR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "udot",
        aliases: &[],
        opcode: 0xc1501010,
        mask: 0xfff09038,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off3_0,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_0,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn2,
                    lsb: 6,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm_INDEX2,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zm,
                        lsb: 16,
                        width: 4,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_10,
                        lsb: 10,
                        width: 2,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::UDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2(
            UDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2::from(bits),
        ))
    }
}
impl InsnOpcode for UDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UDOT_SME_ZA_array_off3_0_S_S_SME_Znx2_S_B_SME_Zm_INDEX2_S_B {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "udot",
        aliases: &[],
        opcode: 0xc1501030,
        mask: 0xfff09038,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off3_0,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_0,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn2,
                    lsb: 6,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm_INDEX2,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zm,
                        lsb: 16,
                        width: 4,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_10,
                        lsb: 10,
                        width: 2,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(
            SME_MISC::UDOT_SME_ZA_array_off3_0_S_S_SME_Znx2_S_B_SME_Zm_INDEX2_S_B(
                UDOT_SME_ZA_array_off3_0_S_S_SME_Znx2_S_B_SME_Zm_INDEX2_S_B::from(bits),
            ),
        )
    }
}
impl InsnOpcode for UDOT_SME_ZA_array_off3_0_S_S_SME_Znx2_S_B_SME_Zm_INDEX2_S_B {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "udot",
        aliases: &[],
        opcode: 0xc1509010,
        mask: 0xfff09078,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off3_0,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_0,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn4,
                    lsb: 7,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm_INDEX2,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zm,
                        lsb: 16,
                        width: 4,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_10,
                        lsb: 10,
                        width: 2,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_4.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::UDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2(
            UDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2::from(bits),
        ))
    }
}
impl InsnOpcode for UDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UDOT_SME_ZA_array_off3_0_S_S_SME_Znx4_S_B_SME_Zm_INDEX2_S_B {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "udot",
        aliases: &[],
        opcode: 0xc1509030,
        mask: 0xfff09078,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off3_0,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_0,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn4,
                    lsb: 7,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm_INDEX2,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zm,
                        lsb: 16,
                        width: 4,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_10,
                        lsb: 10,
                        width: 2,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_4.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(
            SME_MISC::UDOT_SME_ZA_array_off3_0_S_S_SME_Znx4_S_B_SME_Zm_INDEX2_S_B(
                UDOT_SME_ZA_array_off3_0_S_S_SME_Znx4_S_B_SME_Zm_INDEX2_S_B::from(bits),
            ),
        )
    }
}
impl InsnOpcode for UDOT_SME_ZA_array_off3_0_S_S_SME_Znx4_S_B_SME_Zm_INDEX2_S_B {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX1 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "udot",
        aliases: &[],
        opcode: 0xc1d00018,
        mask: 0xfff09838,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2_I16I64,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off3_0,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_0,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn2,
                    lsb: 6,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm_INDEX1,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zm,
                        lsb: 16,
                        width: 4,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm1_10,
                        lsb: 10,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::UDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX1(
            UDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX1::from(bits),
        ))
    }
}
impl InsnOpcode for UDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX1 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX1 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "udot",
        aliases: &[],
        opcode: 0xc1d08018,
        mask: 0xfff09878,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2_I16I64,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off3_0,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_0,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn4,
                    lsb: 7,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm_INDEX1,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zm,
                        lsb: 16,
                        width: 4,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm1_10,
                        lsb: 10,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_4.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::UDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX1(
            UDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX1::from(bits),
        ))
    }
}
impl InsnOpcode for UDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX1 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UDOT_SME_ZA_array_off3_0_SVE_ZnxN_SME_Zm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "udot",
        aliases: &[],
        opcode: 0xc1201410,
        mask: 0xffb09c18,
        class: InsnClass::SME_INT_SD,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off3_0,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_0,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ZnxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm,
                    lsb: 16,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_INT_SD(SME_INT_SD::UDOT_SME_ZA_array_off3_0_SVE_ZnxN_SME_Zm(
            UDOT_SME_ZA_array_off3_0_SVE_ZnxN_SME_Zm::from(bits),
        ))
    }
}
impl InsnOpcode for UDOT_SME_ZA_array_off3_0_SVE_ZnxN_SME_Zm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UDOT_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_B_SME_Zm_S_B {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "udot",
        aliases: &[],
        opcode: 0xc1301410,
        mask: 0xffb09c18,
        class: InsnClass::SME_INT_SD,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off3_0,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_0,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ZnxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm,
                    lsb: 16,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_4.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_INT_SD(
            SME_INT_SD::UDOT_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_B_SME_Zm_S_B(
                UDOT_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_B_SME_Zm_S_B::from(bits),
            ),
        )
    }
}
impl InsnOpcode for UDOT_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_B_SME_Zm_S_B {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zmx2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "udot",
        aliases: &[],
        opcode: 0xc1a01410,
        mask: 0xffa19c38,
        class: InsnClass::SME_INT_SD,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off3_0,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_0,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn2,
                    lsb: 6,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zmx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm2,
                    lsb: 17,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_INT_SD(SME_INT_SD::UDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zmx2(
            UDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zmx2::from(bits),
        ))
    }
}
impl InsnOpcode for UDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zmx2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zmx4 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "udot",
        aliases: &[],
        opcode: 0xc1a11410,
        mask: 0xffa39c78,
        class: InsnClass::SME_INT_SD,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off3_0,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_0,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn4,
                    lsb: 7,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zmx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm4,
                    lsb: 18,
                    width: 3,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_4.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_INT_SD(SME_INT_SD::UDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zmx4(
            UDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zmx4::from(bits),
        ))
    }
}
impl InsnOpcode for UDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zmx4 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UDOT_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_H_SME_Zm_S_H {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "udot",
        aliases: &[],
        opcode: 0xc1601418,
        mask: 0xfff09c18,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off3_0,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_0,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ZnxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm,
                    lsb: 16,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(
            SME_MISC::UDOT_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_H_SME_Zm_S_H(
                UDOT_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_H_SME_Zm_S_H::from(bits),
            ),
        )
    }
}
impl InsnOpcode for UDOT_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_H_SME_Zm_S_H {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UDOT_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_H_SME_Zm_S_H_c1701418 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "udot",
        aliases: &[],
        opcode: 0xc1701418,
        mask: 0xfff09c18,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off3_0,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_0,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ZnxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm,
                    lsb: 16,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_4.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(
            SME_MISC::UDOT_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_H_SME_Zm_S_H_c1701418(
                UDOT_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_H_SME_Zm_S_H_c1701418::from(bits),
            ),
        )
    }
}
impl InsnOpcode for UDOT_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_H_SME_Zm_S_H_c1701418 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UDOT_SME_ZA_array_off3_0_S_S_SME_Znx2_S_H_SME_Zmx2_S_H {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "udot",
        aliases: &[],
        opcode: 0xc1e01418,
        mask: 0xffe19c38,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off3_0,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_0,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn2,
                    lsb: 6,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zmx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm2,
                    lsb: 17,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(
            SME_MISC::UDOT_SME_ZA_array_off3_0_S_S_SME_Znx2_S_H_SME_Zmx2_S_H(
                UDOT_SME_ZA_array_off3_0_S_S_SME_Znx2_S_H_SME_Zmx2_S_H::from(bits),
            ),
        )
    }
}
impl InsnOpcode for UDOT_SME_ZA_array_off3_0_S_S_SME_Znx2_S_H_SME_Zmx2_S_H {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UDOT_SME_ZA_array_off3_0_S_S_SME_Znx4_S_H_SME_Zmx4_S_H {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "udot",
        aliases: &[],
        opcode: 0xc1e11418,
        mask: 0xffe39c78,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off3_0,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_0,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn4,
                    lsb: 7,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zmx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm4,
                    lsb: 18,
                    width: 3,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_4.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(
            SME_MISC::UDOT_SME_ZA_array_off3_0_S_S_SME_Znx4_S_H_SME_Zmx4_S_H(
                UDOT_SME_ZA_array_off3_0_S_S_SME_Znx4_S_H_SME_Zmx4_S_H::from(bits),
            ),
        )
    }
}
impl InsnOpcode for UDOT_SME_ZA_array_off3_0_S_S_SME_Znx4_S_H_SME_Zmx4_S_H {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UDOT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "udot",
        aliases: &[],
        opcode: 0x44800400,
        mask: 0xffa0fc00,
        class: InsnClass::SVE_SIZE_SD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_SD(SVE_SIZE_SD::UDOT_SVE_Zd_SVE_Zn_SVE_Zm_16(
            UDOT_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for UDOT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UDOT_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "udot",
        aliases: &[],
        opcode: 0x44a00400,
        mask: 0xffe0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm3_INDEX,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::UDOT_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX(
            UDOT_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX::from(bits),
        ))
    }
}
impl InsnOpcode for UDOT_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UDOT_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "udot",
        aliases: &[],
        opcode: 0x44e00400,
        mask: 0xffe0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm4_INDEX,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::UDOT_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX(
            UDOT_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX::from(bits),
        ))
    }
}
impl InsnOpcode for UDOT_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UDOT_SVE_Zd_S_S_SVE_Zn_S_H_SVE_Zm_16_S_H {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "udot",
        aliases: &[],
        opcode: 0x4400cc00,
        mask: 0xffe0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::UDOT_SVE_Zd_S_S_SVE_Zn_S_H_SVE_Zm_16_S_H(
            UDOT_SVE_Zd_S_S_SVE_Zn_S_H_SVE_Zm_16_S_H::from(bits),
        ))
    }
}
impl InsnOpcode for UDOT_SVE_Zd_S_S_SVE_Zn_S_H_SVE_Zm_16_S_H {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UDOT_SVE_Zd_SVE_Zn_SVE_Zm3_19_INDEX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "udot",
        aliases: &[],
        opcode: 0x4480cc00,
        mask: 0xffe0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm3_19_INDEX,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_19,
                        lsb: 19,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_imm3,
                        lsb: 16,
                        width: 3,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::UDOT_SVE_Zd_SVE_Zn_SVE_Zm3_19_INDEX(
            UDOT_SVE_Zd_SVE_Zn_SVE_Zm3_19_INDEX::from(bits),
        ))
    }
}
impl InsnOpcode for UDOT_SVE_Zd_SVE_Zn_SVE_Zm3_19_INDEX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UDOT_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "udot",
        aliases: &[],
        opcode: 0x2e009400,
        mask: 0xbf20fc00,
        class: InsnClass::DOTPRODUCT,
        feature_set: InsnFeatureSet::DOTPROD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::DOTPRODUCT(DOTPRODUCT::UDOT_Vd_Vn_Vm(UDOT_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for UDOT_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UDOT_Vd_Vn_Em {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "udot",
        aliases: &[],
        opcode: 0x2f00e000,
        mask: 0xbf00f400,
        class: InsnClass::DOTPRODUCT,
        feature_set: InsnFeatureSet::DOTPROD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Em,
                class: InsnOperandClass::SIMD_ELEMENT,
                qualifiers: &[InsnOperandQualifier::S_4B, InsnOperandQualifier::S_4B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::DOTPRODUCT(DOTPRODUCT::UDOT_Vd_Vn_Em(UDOT_Vd_Vn_Em::from(bits)))
    }
}
impl InsnOpcode for UDOT_Vd_Vn_Em {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UHADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uhadd",
        aliases: &[],
        opcode: 0x44118000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::UHADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(
            UHADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for UHADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UHADD_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uhadd",
        aliases: &[],
        opcode: 0x2e200400,
        mask: 0xbf20fc00,
        class: InsnClass::ASIMDSAME,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSAME(ASIMDSAME::UHADD_Vd_Vn_Vm(UHADD_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for UHADD_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UHSUB_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uhsub",
        aliases: &[],
        opcode: 0x44138000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::UHSUB_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(
            UHSUB_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for UHSUB_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UHSUB_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uhsub",
        aliases: &[],
        opcode: 0x2e202400,
        mask: 0xbf20fc00,
        class: InsnClass::ASIMDSAME,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSAME(ASIMDSAME::UHSUB_Vd_Vn_Vm(UHSUB_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for UHSUB_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UHSUBR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uhsubr",
        aliases: &[],
        opcode: 0x44178000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::UHSUBR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(
            UHSUBR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for UHSUBR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UMADDL_Rd_Rn_Rm_Ra {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "umaddl",
        aliases: &[],
        opcode: 0x9ba00000,
        mask: 0xffe08000,
        class: InsnClass::DP_3SRC,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rm,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Ra,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Ra,
                    lsb: 10,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ALIAS.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::DP_3SRC(DP_3SRC::UMADDL_Rd_Rn_Rm_Ra(UMADDL_Rd_Rn_Rm_Ra::from(bits)))
    }
}
impl InsnOpcode for UMADDL_Rd_Rn_Rm_Ra {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UMAX_SME_Zdnx2_SME_Zdnx2_SME_Zm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "umax",
        aliases: &[],
        opcode: 0xc120a001,
        mask: 0xff30ffe1,
        class: InsnClass::SME_SIZE_22,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn2,
                    lsb: 1,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn2,
                    lsb: 1,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm,
                    lsb: 16,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_SIZE_22(SME_SIZE_22::UMAX_SME_Zdnx2_SME_Zdnx2_SME_Zm(
            UMAX_SME_Zdnx2_SME_Zdnx2_SME_Zm::from(bits),
        ))
    }
}
impl InsnOpcode for UMAX_SME_Zdnx2_SME_Zdnx2_SME_Zm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UMAX_SME_Zdnx2_SME_Zdnx2_SME_Zmx2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "umax",
        aliases: &[],
        opcode: 0xc120b001,
        mask: 0xff21ffe1,
        class: InsnClass::SME_SIZE_22,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn2,
                    lsb: 1,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn2,
                    lsb: 1,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zmx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm2,
                    lsb: 17,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_SIZE_22(SME_SIZE_22::UMAX_SME_Zdnx2_SME_Zdnx2_SME_Zmx2(
            UMAX_SME_Zdnx2_SME_Zdnx2_SME_Zmx2::from(bits),
        ))
    }
}
impl InsnOpcode for UMAX_SME_Zdnx2_SME_Zdnx2_SME_Zmx2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UMAX_SME_Zdnx4_SME_Zdnx4_SME_Zm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "umax",
        aliases: &[],
        opcode: 0xc120a801,
        mask: 0xff30ffe3,
        class: InsnClass::SME_SIZE_22,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn4,
                    lsb: 2,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn4,
                    lsb: 2,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm,
                    lsb: 16,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_SIZE_22(SME_SIZE_22::UMAX_SME_Zdnx4_SME_Zdnx4_SME_Zm(
            UMAX_SME_Zdnx4_SME_Zdnx4_SME_Zm::from(bits),
        ))
    }
}
impl InsnOpcode for UMAX_SME_Zdnx4_SME_Zdnx4_SME_Zm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UMAX_SME_Zdnx4_SME_Zdnx4_SME_Zmx4 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "umax",
        aliases: &[],
        opcode: 0xc120b801,
        mask: 0xff23ffe3,
        class: InsnClass::SME_SIZE_22,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn4,
                    lsb: 2,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn4,
                    lsb: 2,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zmx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm4,
                    lsb: 18,
                    width: 3,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_SIZE_22(SME_SIZE_22::UMAX_SME_Zdnx4_SME_Zdnx4_SME_Zmx4(
            UMAX_SME_Zdnx4_SME_Zdnx4_SME_Zmx4::from(bits),
        ))
    }
}
impl InsnOpcode for UMAX_SME_Zdnx4_SME_Zdnx4_SME_Zmx4 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UMAX_Rd_Rn_CSSC_UIMM8 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "umax",
        aliases: &[],
        opcode: 0x11c40000,
        mask: 0x7ffc0000,
        class: InsnClass::CSSC,
        feature_set: InsnFeatureSet::CSSC,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::CSSC_UIMM8,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::CSSC_imm8,
                    lsb: 10,
                    width: 8,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SF_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::CSSC(CSSC::UMAX_Rd_Rn_CSSC_UIMM8(UMAX_Rd_Rn_CSSC_UIMM8::from(
            bits,
        )))
    }
}
impl InsnOpcode for UMAX_Rd_Rn_CSSC_UIMM8 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UMAX_Rd_Rn_Rm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "umax",
        aliases: &[],
        opcode: 0x1ac06400,
        mask: 0x7fe0fc00,
        class: InsnClass::CSSC,
        feature_set: InsnFeatureSet::CSSC,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rm,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SF_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::CSSC(CSSC::UMAX_Rd_Rn_Rm(UMAX_Rd_Rn_Rm::from(bits)))
    }
}
impl InsnOpcode for UMAX_Rd_Rn_Rm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UMAX_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "umax",
        aliases: &[],
        opcode: 0x4090000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_5,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_5,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::UMAX_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(
            UMAX_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5::from(bits),
        ))
    }
}
impl InsnOpcode for UMAX_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UMAX_SVE_Zd_SVE_Zd_SVE_UIMM8 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "umax",
        aliases: &[],
        opcode: 0x2529c000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_UIMM8,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_imm8,
                    lsb: 5,
                    width: 8,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::UMAX_SVE_Zd_SVE_Zd_SVE_UIMM8(
            UMAX_SVE_Zd_SVE_Zd_SVE_UIMM8::from(bits),
        ))
    }
}
impl InsnOpcode for UMAX_SVE_Zd_SVE_Zd_SVE_UIMM8 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UMAX_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "umax",
        aliases: &[],
        opcode: 0x2e206400,
        mask: 0xbf20fc00,
        class: InsnClass::ASIMDSAME,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSAME(ASIMDSAME::UMAX_Vd_Vn_Vm(UMAX_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for UMAX_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UMAXP_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "umaxp",
        aliases: &[],
        opcode: 0x4415a000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::UMAXP_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(
            UMAXP_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for UMAXP_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UMAXP_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "umaxp",
        aliases: &[],
        opcode: 0x2e20a400,
        mask: 0xbf20fc00,
        class: InsnClass::ASIMDSAME,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSAME(ASIMDSAME::UMAXP_Vd_Vn_Vm(UMAXP_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for UMAXP_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UMAXQV_Vd_SVE_Pg3_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "umaxqv",
        aliases: &[],
        opcode: 0x40d2000,
        mask: 0xff3fe000,
        class: InsnClass::SVE2_URQVS,
        feature_set: InsnFeatureSet::SVE2P1,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_16B, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE2_URQVS(SVE2_URQVS::UMAXQV_Vd_SVE_Pg3_SVE_Zn(
            UMAXQV_Vd_SVE_Pg3_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for UMAXQV_Vd_SVE_Pg3_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UMAXV_SVE_Vd_SVE_Pg3_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "umaxv",
        aliases: &[],
        opcode: 0x4092000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Vd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::UMAXV_SVE_Vd_SVE_Pg3_SVE_Zn(
            UMAXV_SVE_Vd_SVE_Pg3_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for UMAXV_SVE_Vd_SVE_Pg3_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UMAXV_Fd_Vn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "umaxv",
        aliases: &[],
        opcode: 0x2e30a800,
        mask: 0xbf3ffc00,
        class: InsnClass::ASIMDALL,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Fd,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDALL(ASIMDALL::UMAXV_Fd_Vn(UMAXV_Fd_Vn::from(bits)))
    }
}
impl InsnOpcode for UMAXV_Fd_Vn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UMIN_SME_Zdnx2_SME_Zdnx2_SME_Zm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "umin",
        aliases: &[],
        opcode: 0xc120a021,
        mask: 0xff30ffe1,
        class: InsnClass::SME_SIZE_22,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn2,
                    lsb: 1,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn2,
                    lsb: 1,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm,
                    lsb: 16,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_SIZE_22(SME_SIZE_22::UMIN_SME_Zdnx2_SME_Zdnx2_SME_Zm(
            UMIN_SME_Zdnx2_SME_Zdnx2_SME_Zm::from(bits),
        ))
    }
}
impl InsnOpcode for UMIN_SME_Zdnx2_SME_Zdnx2_SME_Zm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UMIN_SME_Zdnx2_SME_Zdnx2_SME_Zmx2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "umin",
        aliases: &[],
        opcode: 0xc120b021,
        mask: 0xff21ffe1,
        class: InsnClass::SME_SIZE_22,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn2,
                    lsb: 1,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn2,
                    lsb: 1,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zmx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm2,
                    lsb: 17,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_SIZE_22(SME_SIZE_22::UMIN_SME_Zdnx2_SME_Zdnx2_SME_Zmx2(
            UMIN_SME_Zdnx2_SME_Zdnx2_SME_Zmx2::from(bits),
        ))
    }
}
impl InsnOpcode for UMIN_SME_Zdnx2_SME_Zdnx2_SME_Zmx2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UMIN_SME_Zdnx4_SME_Zdnx4_SME_Zm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "umin",
        aliases: &[],
        opcode: 0xc120a821,
        mask: 0xff30ffe3,
        class: InsnClass::SME_SIZE_22,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn4,
                    lsb: 2,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn4,
                    lsb: 2,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm,
                    lsb: 16,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_SIZE_22(SME_SIZE_22::UMIN_SME_Zdnx4_SME_Zdnx4_SME_Zm(
            UMIN_SME_Zdnx4_SME_Zdnx4_SME_Zm::from(bits),
        ))
    }
}
impl InsnOpcode for UMIN_SME_Zdnx4_SME_Zdnx4_SME_Zm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UMIN_SME_Zdnx4_SME_Zdnx4_SME_Zmx4 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "umin",
        aliases: &[],
        opcode: 0xc120b821,
        mask: 0xff23ffe3,
        class: InsnClass::SME_SIZE_22,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn4,
                    lsb: 2,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn4,
                    lsb: 2,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zmx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm4,
                    lsb: 18,
                    width: 3,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_SIZE_22(SME_SIZE_22::UMIN_SME_Zdnx4_SME_Zdnx4_SME_Zmx4(
            UMIN_SME_Zdnx4_SME_Zdnx4_SME_Zmx4::from(bits),
        ))
    }
}
impl InsnOpcode for UMIN_SME_Zdnx4_SME_Zdnx4_SME_Zmx4 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UMIN_Rd_Rn_CSSC_UIMM8 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "umin",
        aliases: &[],
        opcode: 0x11cc0000,
        mask: 0x7ffc0000,
        class: InsnClass::CSSC,
        feature_set: InsnFeatureSet::CSSC,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::CSSC_UIMM8,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::CSSC_imm8,
                    lsb: 10,
                    width: 8,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SF_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::CSSC(CSSC::UMIN_Rd_Rn_CSSC_UIMM8(UMIN_Rd_Rn_CSSC_UIMM8::from(
            bits,
        )))
    }
}
impl InsnOpcode for UMIN_Rd_Rn_CSSC_UIMM8 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UMIN_Rd_Rn_Rm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "umin",
        aliases: &[],
        opcode: 0x1ac06c00,
        mask: 0x7fe0fc00,
        class: InsnClass::CSSC,
        feature_set: InsnFeatureSet::CSSC,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rm,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SF_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::CSSC(CSSC::UMIN_Rd_Rn_Rm(UMIN_Rd_Rn_Rm::from(bits)))
    }
}
impl InsnOpcode for UMIN_Rd_Rn_Rm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UMIN_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "umin",
        aliases: &[],
        opcode: 0x40b0000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_5,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_5,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::UMIN_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(
            UMIN_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5::from(bits),
        ))
    }
}
impl InsnOpcode for UMIN_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UMIN_SVE_Zd_SVE_Zd_SVE_UIMM8 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "umin",
        aliases: &[],
        opcode: 0x252bc000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_UIMM8,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_imm8,
                    lsb: 5,
                    width: 8,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::UMIN_SVE_Zd_SVE_Zd_SVE_UIMM8(
            UMIN_SVE_Zd_SVE_Zd_SVE_UIMM8::from(bits),
        ))
    }
}
impl InsnOpcode for UMIN_SVE_Zd_SVE_Zd_SVE_UIMM8 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UMIN_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "umin",
        aliases: &[],
        opcode: 0x2e206c00,
        mask: 0xbf20fc00,
        class: InsnClass::ASIMDSAME,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSAME(ASIMDSAME::UMIN_Vd_Vn_Vm(UMIN_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for UMIN_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UMINP_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uminp",
        aliases: &[],
        opcode: 0x4417a000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::UMINP_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(
            UMINP_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for UMINP_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UMINP_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uminp",
        aliases: &[],
        opcode: 0x2e20ac00,
        mask: 0xbf20fc00,
        class: InsnClass::ASIMDSAME,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSAME(ASIMDSAME::UMINP_Vd_Vn_Vm(UMINP_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for UMINP_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UMINQV_Vd_SVE_Pg3_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uminqv",
        aliases: &[],
        opcode: 0x40f2000,
        mask: 0xff3fe000,
        class: InsnClass::SVE2_URQVS,
        feature_set: InsnFeatureSet::SVE2P1,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_16B, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE2_URQVS(SVE2_URQVS::UMINQV_Vd_SVE_Pg3_SVE_Zn(
            UMINQV_Vd_SVE_Pg3_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for UMINQV_Vd_SVE_Pg3_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UMINV_SVE_Vd_SVE_Pg3_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uminv",
        aliases: &[],
        opcode: 0x40b2000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Vd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::UMINV_SVE_Vd_SVE_Pg3_SVE_Zn(
            UMINV_SVE_Vd_SVE_Pg3_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for UMINV_SVE_Vd_SVE_Pg3_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UMINV_Fd_Vn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uminv",
        aliases: &[],
        opcode: 0x2e31a800,
        mask: 0xbf3ffc00,
        class: InsnClass::ASIMDALL,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Fd,
                class: InsnOperandClass::FP_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDALL(ASIMDALL::UMINV_Fd_Vn(UMINV_Fd_Vn::from(bits)))
    }
}
impl InsnOpcode for UMINV_Fd_Vn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UMLAL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm_INDEX3_10 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "umlal",
        aliases: &[],
        opcode: 0xc1c01010,
        mask: 0xfff01018,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off3x2,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_0,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm_INDEX3_10,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zm,
                        lsb: 16,
                        width: 4,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm1_15,
                        lsb: 15,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_10,
                        lsb: 10,
                        width: 2,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::UMLAL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm_INDEX3_10(
            UMLAL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm_INDEX3_10::from(bits),
        ))
    }
}
impl InsnOpcode for UMLAL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm_INDEX3_10 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UMLAL_SME_ZA_array_off2x2_SME_Znx2_SME_Zm_INDEX3_2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "umlal",
        aliases: &[],
        opcode: 0xc1d01010,
        mask: 0xfff09038,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off2x2,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_0,
                        lsb: 0,
                        width: 2,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn2,
                    lsb: 6,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm_INDEX3_2,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zm,
                        lsb: 16,
                        width: 4,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_10,
                        lsb: 10,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm1_2,
                        lsb: 2,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(
            SME_MISC::UMLAL_SME_ZA_array_off2x2_SME_Znx2_SME_Zm_INDEX3_2(
                UMLAL_SME_ZA_array_off2x2_SME_Znx2_SME_Zm_INDEX3_2::from(bits),
            ),
        )
    }
}
impl InsnOpcode for UMLAL_SME_ZA_array_off2x2_SME_Znx2_SME_Zm_INDEX3_2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UMLAL_SME_ZA_array_off2x2_SME_Znx4_SME_Zm_INDEX3_2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "umlal",
        aliases: &[],
        opcode: 0xc1d09010,
        mask: 0xfff09078,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off2x2,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_0,
                        lsb: 0,
                        width: 2,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn4,
                    lsb: 7,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm_INDEX3_2,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zm,
                        lsb: 16,
                        width: 4,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_10,
                        lsb: 10,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm1_2,
                        lsb: 2,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_4.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(
            SME_MISC::UMLAL_SME_ZA_array_off2x2_SME_Znx4_SME_Zm_INDEX3_2(
                UMLAL_SME_ZA_array_off2x2_SME_Znx4_SME_Zm_INDEX3_2::from(bits),
            ),
        )
    }
}
impl InsnOpcode for UMLAL_SME_ZA_array_off2x2_SME_Znx4_SME_Zm_INDEX3_2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UMLAL_SME_ZA_array_off2x2_SVE_ZnxN_SME_Zm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "umlal",
        aliases: &[],
        opcode: 0xc1600810,
        mask: 0xfff09c1c,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off2x2,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_0,
                        lsb: 0,
                        width: 2,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ZnxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm,
                    lsb: 16,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::UMLAL_SME_ZA_array_off2x2_SVE_ZnxN_SME_Zm(
            UMLAL_SME_ZA_array_off2x2_SVE_ZnxN_SME_Zm::from(bits),
        ))
    }
}
impl InsnOpcode for UMLAL_SME_ZA_array_off2x2_SVE_ZnxN_SME_Zm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UMLAL_SME_ZA_array_off2x2_S_S_SVE_ZnxN_S_H_SME_Zm_S_H {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "umlal",
        aliases: &[],
        opcode: 0xc1700810,
        mask: 0xfff09c1c,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off2x2,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_0,
                        lsb: 0,
                        width: 2,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ZnxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm,
                    lsb: 16,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_4.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(
            SME_MISC::UMLAL_SME_ZA_array_off2x2_S_S_SVE_ZnxN_S_H_SME_Zm_S_H(
                UMLAL_SME_ZA_array_off2x2_S_S_SVE_ZnxN_S_H_SME_Zm_S_H::from(bits),
            ),
        )
    }
}
impl InsnOpcode for UMLAL_SME_ZA_array_off2x2_S_S_SVE_ZnxN_S_H_SME_Zm_S_H {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UMLAL_SME_ZA_array_off2x2_SME_Znx2_SME_Zmx2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "umlal",
        aliases: &[],
        opcode: 0xc1e00810,
        mask: 0xffe19c3c,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off2x2,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_0,
                        lsb: 0,
                        width: 2,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn2,
                    lsb: 6,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zmx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm2,
                    lsb: 17,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::UMLAL_SME_ZA_array_off2x2_SME_Znx2_SME_Zmx2(
            UMLAL_SME_ZA_array_off2x2_SME_Znx2_SME_Zmx2::from(bits),
        ))
    }
}
impl InsnOpcode for UMLAL_SME_ZA_array_off2x2_SME_Znx2_SME_Zmx2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UMLAL_SME_ZA_array_off2x2_SME_Znx4_SME_Zmx4 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "umlal",
        aliases: &[],
        opcode: 0xc1e10810,
        mask: 0xffe39c7c,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off2x2,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_0,
                        lsb: 0,
                        width: 2,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn4,
                    lsb: 7,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zmx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm4,
                    lsb: 18,
                    width: 3,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_4.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::UMLAL_SME_ZA_array_off2x2_SME_Znx4_SME_Zmx4(
            UMLAL_SME_ZA_array_off2x2_SME_Znx4_SME_Zmx4::from(bits),
        ))
    }
}
impl InsnOpcode for UMLAL_SME_ZA_array_off2x2_SME_Znx4_SME_Zmx4 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UMLAL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "umlal",
        aliases: &[],
        opcode: 0xc1600c10,
        mask: 0xfff09c18,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off3x2,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_0,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm,
                    lsb: 16,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::UMLAL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm(
            UMLAL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm::from(bits),
        ))
    }
}
impl InsnOpcode for UMLAL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UMLAL_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "umlal",
        aliases: &[],
        opcode: 0x2e208000,
        mask: 0xff20fc00,
        class: InsnClass::ASIMDDIFF,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8H, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_4H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_4H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDDIFF(ASIMDDIFF::UMLAL_Vd_Vn_Vm(UMLAL_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for UMLAL_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UMLAL_Vd_Vn_Em16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "umlal",
        aliases: &[],
        opcode: 0x2f002000,
        mask: 0xff00f400,
        class: InsnClass::ASIMDELEM,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4S, InsnOperandQualifier::V_2D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_2S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Em16,
                class: InsnOperandClass::SIMD_ELEMENT,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDELEM(ASIMDELEM::UMLAL_Vd_Vn_Em16(UMLAL_Vd_Vn_Em16::from(bits)))
    }
}
impl InsnOpcode for UMLAL_Vd_Vn_Em16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UMLAL2_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "umlal2",
        aliases: &[],
        opcode: 0x6e208000,
        mask: 0xff20fc00,
        class: InsnClass::ASIMDDIFF,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8H, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_16B, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_16B, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDDIFF(ASIMDDIFF::UMLAL2_Vd_Vn_Vm(UMLAL2_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for UMLAL2_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UMLAL2_Vd_Vn_Em16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "umlal2",
        aliases: &[],
        opcode: 0x6f002000,
        mask: 0xff00f400,
        class: InsnClass::ASIMDELEM,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4S, InsnOperandQualifier::V_2D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8H, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Em16,
                class: InsnOperandClass::SIMD_ELEMENT,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDELEM(ASIMDELEM::UMLAL2_Vd_Vn_Em16(UMLAL2_Vd_Vn_Em16::from(bits)))
    }
}
impl InsnOpcode for UMLAL2_Vd_Vn_Em16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UMLALB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "umlalb",
        aliases: &[],
        opcode: 0x44a09000,
        mask: 0xffe0f400,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm3_11_INDEX,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_i3h2,
                        lsb: 19,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_i3l,
                        lsb: 11,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_imm3,
                        lsb: 16,
                        width: 3,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::UMLALB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX(
            UMLALB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX::from(bits),
        ))
    }
}
impl InsnOpcode for UMLALB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UMLALB_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "umlalb",
        aliases: &[],
        opcode: 0x44e09000,
        mask: 0xffe0f400,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm4_11_INDEX,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_i2h,
                        lsb: 20,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_i3l,
                        lsb: 11,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_imm4,
                        lsb: 16,
                        width: 4,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::UMLALB_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX(
            UMLALB_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX::from(bits),
        ))
    }
}
impl InsnOpcode for UMLALB_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UMLALB_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "umlalb",
        aliases: &[],
        opcode: 0x44004800,
        mask: 0xff20fc00,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::UMLALB_SVE_Zd_SVE_Zn_SVE_Zm_16(
            UMLALB_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for UMLALB_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UMLALL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm_INDEX4_10 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "umlall",
        aliases: &[],
        opcode: 0xc1000010,
        mask: 0xfff0001c,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off2x4,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_0,
                        lsb: 0,
                        width: 2,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm_INDEX4_10,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zm,
                        lsb: 16,
                        width: 4,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm1_15,
                        lsb: 15,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_10,
                        lsb: 10,
                        width: 3,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(
            SME_MISC::UMLALL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm_INDEX4_10(
                UMLALL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm_INDEX4_10::from(bits),
            ),
        )
    }
}
impl InsnOpcode for UMLALL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm_INDEX4_10 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UMLALL_SME_ZA_array_off1x4_SME_Znx2_SME_Zm_INDEX4_1 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "umlall",
        aliases: &[],
        opcode: 0xc1100010,
        mask: 0xfff09038,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off1x4,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm1_0,
                        lsb: 0,
                        width: 1,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn2,
                    lsb: 6,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm_INDEX4_1,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zm,
                        lsb: 16,
                        width: 4,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_10,
                        lsb: 10,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_1,
                        lsb: 1,
                        width: 2,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(
            SME_MISC::UMLALL_SME_ZA_array_off1x4_SME_Znx2_SME_Zm_INDEX4_1(
                UMLALL_SME_ZA_array_off1x4_SME_Znx2_SME_Zm_INDEX4_1::from(bits),
            ),
        )
    }
}
impl InsnOpcode for UMLALL_SME_ZA_array_off1x4_SME_Znx2_SME_Zm_INDEX4_1 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UMLALL_SME_ZA_array_off1x4_SME_Znx4_SME_Zm_INDEX4_1 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "umlall",
        aliases: &[],
        opcode: 0xc1108010,
        mask: 0xfff09078,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off1x4,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm1_0,
                        lsb: 0,
                        width: 1,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn4,
                    lsb: 7,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm_INDEX4_1,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zm,
                        lsb: 16,
                        width: 4,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_10,
                        lsb: 10,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_1,
                        lsb: 1,
                        width: 2,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_4.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(
            SME_MISC::UMLALL_SME_ZA_array_off1x4_SME_Znx4_SME_Zm_INDEX4_1(
                UMLALL_SME_ZA_array_off1x4_SME_Znx4_SME_Zm_INDEX4_1::from(bits),
            ),
        )
    }
}
impl InsnOpcode for UMLALL_SME_ZA_array_off1x4_SME_Znx4_SME_Zm_INDEX4_1 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UMLALL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm_INDEX3_10 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "umlall",
        aliases: &[],
        opcode: 0xc1800010,
        mask: 0xfff0101c,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2_I16I64,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off2x4,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_0,
                        lsb: 0,
                        width: 2,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm_INDEX3_10,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zm,
                        lsb: 16,
                        width: 4,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm1_15,
                        lsb: 15,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_10,
                        lsb: 10,
                        width: 2,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(
            SME_MISC::UMLALL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm_INDEX3_10(
                UMLALL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm_INDEX3_10::from(bits),
            ),
        )
    }
}
impl InsnOpcode for UMLALL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm_INDEX3_10 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UMLALL_SME_ZA_array_off1x4_SME_Znx2_SME_Zm_INDEX3_1 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "umlall",
        aliases: &[],
        opcode: 0xc1900010,
        mask: 0xfff09838,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2_I16I64,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off1x4,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm1_0,
                        lsb: 0,
                        width: 1,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn2,
                    lsb: 6,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm_INDEX3_1,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zm,
                        lsb: 16,
                        width: 4,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm1_10,
                        lsb: 10,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_1,
                        lsb: 1,
                        width: 2,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(
            SME_MISC::UMLALL_SME_ZA_array_off1x4_SME_Znx2_SME_Zm_INDEX3_1(
                UMLALL_SME_ZA_array_off1x4_SME_Znx2_SME_Zm_INDEX3_1::from(bits),
            ),
        )
    }
}
impl InsnOpcode for UMLALL_SME_ZA_array_off1x4_SME_Znx2_SME_Zm_INDEX3_1 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UMLALL_SME_ZA_array_off1x4_SME_Znx4_SME_Zm_INDEX3_1 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "umlall",
        aliases: &[],
        opcode: 0xc1908010,
        mask: 0xfff09878,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2_I16I64,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off1x4,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm1_0,
                        lsb: 0,
                        width: 1,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn4,
                    lsb: 7,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm_INDEX3_1,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zm,
                        lsb: 16,
                        width: 4,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm1_10,
                        lsb: 10,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_1,
                        lsb: 1,
                        width: 2,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_4.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(
            SME_MISC::UMLALL_SME_ZA_array_off1x4_SME_Znx4_SME_Zm_INDEX3_1(
                UMLALL_SME_ZA_array_off1x4_SME_Znx4_SME_Zm_INDEX3_1::from(bits),
            ),
        )
    }
}
impl InsnOpcode for UMLALL_SME_ZA_array_off1x4_SME_Znx4_SME_Zm_INDEX3_1 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UMLALL_SME_ZA_array_off1x4_SVE_ZnxN_SME_Zm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "umlall",
        aliases: &[],
        opcode: 0xc1200010,
        mask: 0xffb09c1e,
        class: InsnClass::SME_INT_SD,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off1x4,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm1_0,
                        lsb: 0,
                        width: 1,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ZnxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm,
                    lsb: 16,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_INT_SD(SME_INT_SD::UMLALL_SME_ZA_array_off1x4_SVE_ZnxN_SME_Zm(
            UMLALL_SME_ZA_array_off1x4_SVE_ZnxN_SME_Zm::from(bits),
        ))
    }
}
impl InsnOpcode for UMLALL_SME_ZA_array_off1x4_SVE_ZnxN_SME_Zm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UMLALL_SME_ZA_array_off1x4_S_S_SVE_ZnxN_S_B_SME_Zm_S_B {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "umlall",
        aliases: &[],
        opcode: 0xc1300010,
        mask: 0xffb09c1e,
        class: InsnClass::SME_INT_SD,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off1x4,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm1_0,
                        lsb: 0,
                        width: 1,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ZnxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm,
                    lsb: 16,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_4.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_INT_SD(
            SME_INT_SD::UMLALL_SME_ZA_array_off1x4_S_S_SVE_ZnxN_S_B_SME_Zm_S_B(
                UMLALL_SME_ZA_array_off1x4_S_S_SVE_ZnxN_S_B_SME_Zm_S_B::from(bits),
            ),
        )
    }
}
impl InsnOpcode for UMLALL_SME_ZA_array_off1x4_S_S_SVE_ZnxN_S_B_SME_Zm_S_B {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UMLALL_SME_ZA_array_off1x4_SME_Znx2_SME_Zmx2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "umlall",
        aliases: &[],
        opcode: 0xc1a00010,
        mask: 0xffa19c3e,
        class: InsnClass::SME_INT_SD,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off1x4,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm1_0,
                        lsb: 0,
                        width: 1,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn2,
                    lsb: 6,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zmx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm2,
                    lsb: 17,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_INT_SD(SME_INT_SD::UMLALL_SME_ZA_array_off1x4_SME_Znx2_SME_Zmx2(
            UMLALL_SME_ZA_array_off1x4_SME_Znx2_SME_Zmx2::from(bits),
        ))
    }
}
impl InsnOpcode for UMLALL_SME_ZA_array_off1x4_SME_Znx2_SME_Zmx2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UMLALL_SME_ZA_array_off1x4_SME_Znx4_SME_Zmx4 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "umlall",
        aliases: &[],
        opcode: 0xc1a10010,
        mask: 0xffa39c7e,
        class: InsnClass::SME_INT_SD,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off1x4,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm1_0,
                        lsb: 0,
                        width: 1,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn4,
                    lsb: 7,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zmx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm4,
                    lsb: 18,
                    width: 3,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_4.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_INT_SD(SME_INT_SD::UMLALL_SME_ZA_array_off1x4_SME_Znx4_SME_Zmx4(
            UMLALL_SME_ZA_array_off1x4_SME_Znx4_SME_Zmx4::from(bits),
        ))
    }
}
impl InsnOpcode for UMLALL_SME_ZA_array_off1x4_SME_Znx4_SME_Zmx4 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UMLALL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "umlall",
        aliases: &[],
        opcode: 0xc1200410,
        mask: 0xffb09c1c,
        class: InsnClass::SME_INT_SD,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off2x4,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_0,
                        lsb: 0,
                        width: 2,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm,
                    lsb: 16,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_INT_SD(SME_INT_SD::UMLALL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm(
            UMLALL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm::from(bits),
        ))
    }
}
impl InsnOpcode for UMLALL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UMLALT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "umlalt",
        aliases: &[],
        opcode: 0x44a09400,
        mask: 0xffe0f400,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm3_11_INDEX,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_i3h2,
                        lsb: 19,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_i3l,
                        lsb: 11,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_imm3,
                        lsb: 16,
                        width: 3,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::UMLALT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX(
            UMLALT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX::from(bits),
        ))
    }
}
impl InsnOpcode for UMLALT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UMLALT_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "umlalt",
        aliases: &[],
        opcode: 0x44e09400,
        mask: 0xffe0f400,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm4_11_INDEX,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_i2h,
                        lsb: 20,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_i3l,
                        lsb: 11,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_imm4,
                        lsb: 16,
                        width: 4,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::UMLALT_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX(
            UMLALT_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX::from(bits),
        ))
    }
}
impl InsnOpcode for UMLALT_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UMLALT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "umlalt",
        aliases: &[],
        opcode: 0x44004c00,
        mask: 0xff20fc00,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::UMLALT_SVE_Zd_SVE_Zn_SVE_Zm_16(
            UMLALT_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for UMLALT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UMLSL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm_INDEX3_10 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "umlsl",
        aliases: &[],
        opcode: 0xc1c01018,
        mask: 0xfff01018,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off3x2,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_0,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm_INDEX3_10,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zm,
                        lsb: 16,
                        width: 4,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm1_15,
                        lsb: 15,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_10,
                        lsb: 10,
                        width: 2,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::UMLSL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm_INDEX3_10(
            UMLSL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm_INDEX3_10::from(bits),
        ))
    }
}
impl InsnOpcode for UMLSL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm_INDEX3_10 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UMLSL_SME_ZA_array_off2x2_SME_Znx2_SME_Zm_INDEX3_2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "umlsl",
        aliases: &[],
        opcode: 0xc1d01018,
        mask: 0xfff09038,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off2x2,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_0,
                        lsb: 0,
                        width: 2,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn2,
                    lsb: 6,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm_INDEX3_2,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zm,
                        lsb: 16,
                        width: 4,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_10,
                        lsb: 10,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm1_2,
                        lsb: 2,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(
            SME_MISC::UMLSL_SME_ZA_array_off2x2_SME_Znx2_SME_Zm_INDEX3_2(
                UMLSL_SME_ZA_array_off2x2_SME_Znx2_SME_Zm_INDEX3_2::from(bits),
            ),
        )
    }
}
impl InsnOpcode for UMLSL_SME_ZA_array_off2x2_SME_Znx2_SME_Zm_INDEX3_2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UMLSL_SME_ZA_array_off2x2_SME_Znx4_SME_Zm_INDEX3_2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "umlsl",
        aliases: &[],
        opcode: 0xc1d09018,
        mask: 0xfff09078,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off2x2,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_0,
                        lsb: 0,
                        width: 2,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn4,
                    lsb: 7,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm_INDEX3_2,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zm,
                        lsb: 16,
                        width: 4,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_10,
                        lsb: 10,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm1_2,
                        lsb: 2,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_4.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(
            SME_MISC::UMLSL_SME_ZA_array_off2x2_SME_Znx4_SME_Zm_INDEX3_2(
                UMLSL_SME_ZA_array_off2x2_SME_Znx4_SME_Zm_INDEX3_2::from(bits),
            ),
        )
    }
}
impl InsnOpcode for UMLSL_SME_ZA_array_off2x2_SME_Znx4_SME_Zm_INDEX3_2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UMLSL_SME_ZA_array_off2x2_SVE_ZnxN_SME_Zm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "umlsl",
        aliases: &[],
        opcode: 0xc1600818,
        mask: 0xfff09c1c,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off2x2,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_0,
                        lsb: 0,
                        width: 2,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ZnxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm,
                    lsb: 16,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::UMLSL_SME_ZA_array_off2x2_SVE_ZnxN_SME_Zm(
            UMLSL_SME_ZA_array_off2x2_SVE_ZnxN_SME_Zm::from(bits),
        ))
    }
}
impl InsnOpcode for UMLSL_SME_ZA_array_off2x2_SVE_ZnxN_SME_Zm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UMLSL_SME_ZA_array_off2x2_S_S_SVE_ZnxN_S_H_SME_Zm_S_H {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "umlsl",
        aliases: &[],
        opcode: 0xc1700818,
        mask: 0xfff09c1c,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off2x2,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_0,
                        lsb: 0,
                        width: 2,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ZnxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm,
                    lsb: 16,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_4.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(
            SME_MISC::UMLSL_SME_ZA_array_off2x2_S_S_SVE_ZnxN_S_H_SME_Zm_S_H(
                UMLSL_SME_ZA_array_off2x2_S_S_SVE_ZnxN_S_H_SME_Zm_S_H::from(bits),
            ),
        )
    }
}
impl InsnOpcode for UMLSL_SME_ZA_array_off2x2_S_S_SVE_ZnxN_S_H_SME_Zm_S_H {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UMLSL_SME_ZA_array_off2x2_SME_Znx2_SME_Zmx2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "umlsl",
        aliases: &[],
        opcode: 0xc1e00818,
        mask: 0xffe19c3c,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off2x2,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_0,
                        lsb: 0,
                        width: 2,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn2,
                    lsb: 6,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zmx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm2,
                    lsb: 17,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::UMLSL_SME_ZA_array_off2x2_SME_Znx2_SME_Zmx2(
            UMLSL_SME_ZA_array_off2x2_SME_Znx2_SME_Zmx2::from(bits),
        ))
    }
}
impl InsnOpcode for UMLSL_SME_ZA_array_off2x2_SME_Znx2_SME_Zmx2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UMLSL_SME_ZA_array_off2x2_SME_Znx4_SME_Zmx4 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "umlsl",
        aliases: &[],
        opcode: 0xc1e10818,
        mask: 0xffe39c7c,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off2x2,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_0,
                        lsb: 0,
                        width: 2,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn4,
                    lsb: 7,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zmx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm4,
                    lsb: 18,
                    width: 3,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_4.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::UMLSL_SME_ZA_array_off2x2_SME_Znx4_SME_Zmx4(
            UMLSL_SME_ZA_array_off2x2_SME_Znx4_SME_Zmx4::from(bits),
        ))
    }
}
impl InsnOpcode for UMLSL_SME_ZA_array_off2x2_SME_Znx4_SME_Zmx4 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UMLSL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "umlsl",
        aliases: &[],
        opcode: 0xc1600c18,
        mask: 0xfff09c18,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off3x2,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_0,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm,
                    lsb: 16,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::UMLSL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm(
            UMLSL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm::from(bits),
        ))
    }
}
impl InsnOpcode for UMLSL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UMLSL_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "umlsl",
        aliases: &[],
        opcode: 0x2e20a000,
        mask: 0xff20fc00,
        class: InsnClass::ASIMDDIFF,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8H, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_4H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_4H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDDIFF(ASIMDDIFF::UMLSL_Vd_Vn_Vm(UMLSL_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for UMLSL_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UMLSL_Vd_Vn_Em16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "umlsl",
        aliases: &[],
        opcode: 0x2f006000,
        mask: 0xff00f400,
        class: InsnClass::ASIMDELEM,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4S, InsnOperandQualifier::V_2D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_2S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Em16,
                class: InsnOperandClass::SIMD_ELEMENT,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDELEM(ASIMDELEM::UMLSL_Vd_Vn_Em16(UMLSL_Vd_Vn_Em16::from(bits)))
    }
}
impl InsnOpcode for UMLSL_Vd_Vn_Em16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UMLSL2_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "umlsl2",
        aliases: &[],
        opcode: 0x6e20a000,
        mask: 0xff20fc00,
        class: InsnClass::ASIMDDIFF,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8H, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_16B, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_16B, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDDIFF(ASIMDDIFF::UMLSL2_Vd_Vn_Vm(UMLSL2_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for UMLSL2_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UMLSL2_Vd_Vn_Em16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "umlsl2",
        aliases: &[],
        opcode: 0x6f006000,
        mask: 0xff00f400,
        class: InsnClass::ASIMDELEM,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4S, InsnOperandQualifier::V_2D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8H, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Em16,
                class: InsnOperandClass::SIMD_ELEMENT,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDELEM(ASIMDELEM::UMLSL2_Vd_Vn_Em16(UMLSL2_Vd_Vn_Em16::from(bits)))
    }
}
impl InsnOpcode for UMLSL2_Vd_Vn_Em16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UMLSLB_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "umlslb",
        aliases: &[],
        opcode: 0x44005800,
        mask: 0xff20fc00,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::UMLSLB_SVE_Zd_SVE_Zn_SVE_Zm_16(
            UMLSLB_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for UMLSLB_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UMLSLB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "umlslb",
        aliases: &[],
        opcode: 0x44a0b000,
        mask: 0xffe0f400,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm3_11_INDEX,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_i3h2,
                        lsb: 19,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_i3l,
                        lsb: 11,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_imm3,
                        lsb: 16,
                        width: 3,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::UMLSLB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX(
            UMLSLB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX::from(bits),
        ))
    }
}
impl InsnOpcode for UMLSLB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UMLSLB_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "umlslb",
        aliases: &[],
        opcode: 0x44e0b000,
        mask: 0xffe0f400,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm4_11_INDEX,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_i2h,
                        lsb: 20,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_i3l,
                        lsb: 11,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_imm4,
                        lsb: 16,
                        width: 4,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::UMLSLB_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX(
            UMLSLB_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX::from(bits),
        ))
    }
}
impl InsnOpcode for UMLSLB_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UMLSLL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm_INDEX4_10 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "umlsll",
        aliases: &[],
        opcode: 0xc1000018,
        mask: 0xfff0001c,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off2x4,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_0,
                        lsb: 0,
                        width: 2,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm_INDEX4_10,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zm,
                        lsb: 16,
                        width: 4,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm1_15,
                        lsb: 15,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_10,
                        lsb: 10,
                        width: 3,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(
            SME_MISC::UMLSLL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm_INDEX4_10(
                UMLSLL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm_INDEX4_10::from(bits),
            ),
        )
    }
}
impl InsnOpcode for UMLSLL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm_INDEX4_10 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UMLSLL_SME_ZA_array_off1x4_SME_Znx2_SME_Zm_INDEX4_1 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "umlsll",
        aliases: &[],
        opcode: 0xc1100018,
        mask: 0xfff09038,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off1x4,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm1_0,
                        lsb: 0,
                        width: 1,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn2,
                    lsb: 6,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm_INDEX4_1,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zm,
                        lsb: 16,
                        width: 4,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_10,
                        lsb: 10,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_1,
                        lsb: 1,
                        width: 2,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(
            SME_MISC::UMLSLL_SME_ZA_array_off1x4_SME_Znx2_SME_Zm_INDEX4_1(
                UMLSLL_SME_ZA_array_off1x4_SME_Znx2_SME_Zm_INDEX4_1::from(bits),
            ),
        )
    }
}
impl InsnOpcode for UMLSLL_SME_ZA_array_off1x4_SME_Znx2_SME_Zm_INDEX4_1 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UMLSLL_SME_ZA_array_off1x4_SME_Znx4_SME_Zm_INDEX4_1 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "umlsll",
        aliases: &[],
        opcode: 0xc1108018,
        mask: 0xfff09078,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off1x4,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm1_0,
                        lsb: 0,
                        width: 1,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn4,
                    lsb: 7,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm_INDEX4_1,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zm,
                        lsb: 16,
                        width: 4,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_10,
                        lsb: 10,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_1,
                        lsb: 1,
                        width: 2,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_4.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(
            SME_MISC::UMLSLL_SME_ZA_array_off1x4_SME_Znx4_SME_Zm_INDEX4_1(
                UMLSLL_SME_ZA_array_off1x4_SME_Znx4_SME_Zm_INDEX4_1::from(bits),
            ),
        )
    }
}
impl InsnOpcode for UMLSLL_SME_ZA_array_off1x4_SME_Znx4_SME_Zm_INDEX4_1 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UMLSLL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm_INDEX3_10 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "umlsll",
        aliases: &[],
        opcode: 0xc1800018,
        mask: 0xfff0101c,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2_I16I64,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off2x4,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_0,
                        lsb: 0,
                        width: 2,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm_INDEX3_10,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zm,
                        lsb: 16,
                        width: 4,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm1_15,
                        lsb: 15,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_10,
                        lsb: 10,
                        width: 2,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(
            SME_MISC::UMLSLL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm_INDEX3_10(
                UMLSLL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm_INDEX3_10::from(bits),
            ),
        )
    }
}
impl InsnOpcode for UMLSLL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm_INDEX3_10 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UMLSLL_SME_ZA_array_off1x4_SME_Znx2_SME_Zm_INDEX3_1 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "umlsll",
        aliases: &[],
        opcode: 0xc1900018,
        mask: 0xfff09838,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2_I16I64,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off1x4,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm1_0,
                        lsb: 0,
                        width: 1,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn2,
                    lsb: 6,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm_INDEX3_1,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zm,
                        lsb: 16,
                        width: 4,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm1_10,
                        lsb: 10,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_1,
                        lsb: 1,
                        width: 2,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(
            SME_MISC::UMLSLL_SME_ZA_array_off1x4_SME_Znx2_SME_Zm_INDEX3_1(
                UMLSLL_SME_ZA_array_off1x4_SME_Znx2_SME_Zm_INDEX3_1::from(bits),
            ),
        )
    }
}
impl InsnOpcode for UMLSLL_SME_ZA_array_off1x4_SME_Znx2_SME_Zm_INDEX3_1 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UMLSLL_SME_ZA_array_off1x4_SME_Znx4_SME_Zm_INDEX3_1 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "umlsll",
        aliases: &[],
        opcode: 0xc1908018,
        mask: 0xfff09878,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2_I16I64,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off1x4,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm1_0,
                        lsb: 0,
                        width: 1,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn4,
                    lsb: 7,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm_INDEX3_1,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zm,
                        lsb: 16,
                        width: 4,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm1_10,
                        lsb: 10,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_1,
                        lsb: 1,
                        width: 2,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_4.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(
            SME_MISC::UMLSLL_SME_ZA_array_off1x4_SME_Znx4_SME_Zm_INDEX3_1(
                UMLSLL_SME_ZA_array_off1x4_SME_Znx4_SME_Zm_INDEX3_1::from(bits),
            ),
        )
    }
}
impl InsnOpcode for UMLSLL_SME_ZA_array_off1x4_SME_Znx4_SME_Zm_INDEX3_1 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UMLSLL_SME_ZA_array_off1x4_SVE_ZnxN_SME_Zm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "umlsll",
        aliases: &[],
        opcode: 0xc1200018,
        mask: 0xffb09c1e,
        class: InsnClass::SME_INT_SD,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off1x4,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm1_0,
                        lsb: 0,
                        width: 1,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ZnxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm,
                    lsb: 16,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_INT_SD(SME_INT_SD::UMLSLL_SME_ZA_array_off1x4_SVE_ZnxN_SME_Zm(
            UMLSLL_SME_ZA_array_off1x4_SVE_ZnxN_SME_Zm::from(bits),
        ))
    }
}
impl InsnOpcode for UMLSLL_SME_ZA_array_off1x4_SVE_ZnxN_SME_Zm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UMLSLL_SME_ZA_array_off1x4_S_S_SVE_ZnxN_S_B_SME_Zm_S_B {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "umlsll",
        aliases: &[],
        opcode: 0xc1300018,
        mask: 0xffb09c1e,
        class: InsnClass::SME_INT_SD,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off1x4,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm1_0,
                        lsb: 0,
                        width: 1,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ZnxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm,
                    lsb: 16,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_4.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_INT_SD(
            SME_INT_SD::UMLSLL_SME_ZA_array_off1x4_S_S_SVE_ZnxN_S_B_SME_Zm_S_B(
                UMLSLL_SME_ZA_array_off1x4_S_S_SVE_ZnxN_S_B_SME_Zm_S_B::from(bits),
            ),
        )
    }
}
impl InsnOpcode for UMLSLL_SME_ZA_array_off1x4_S_S_SVE_ZnxN_S_B_SME_Zm_S_B {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UMLSLL_SME_ZA_array_off1x4_SME_Znx2_SME_Zmx2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "umlsll",
        aliases: &[],
        opcode: 0xc1a00018,
        mask: 0xffa19c3e,
        class: InsnClass::SME_INT_SD,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off1x4,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm1_0,
                        lsb: 0,
                        width: 1,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn2,
                    lsb: 6,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zmx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm2,
                    lsb: 17,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_INT_SD(SME_INT_SD::UMLSLL_SME_ZA_array_off1x4_SME_Znx2_SME_Zmx2(
            UMLSLL_SME_ZA_array_off1x4_SME_Znx2_SME_Zmx2::from(bits),
        ))
    }
}
impl InsnOpcode for UMLSLL_SME_ZA_array_off1x4_SME_Znx2_SME_Zmx2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UMLSLL_SME_ZA_array_off1x4_SME_Znx4_SME_Zmx4 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "umlsll",
        aliases: &[],
        opcode: 0xc1a10018,
        mask: 0xffa39c7e,
        class: InsnClass::SME_INT_SD,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off1x4,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm1_0,
                        lsb: 0,
                        width: 1,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn4,
                    lsb: 7,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zmx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm4,
                    lsb: 18,
                    width: 3,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_4.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_INT_SD(SME_INT_SD::UMLSLL_SME_ZA_array_off1x4_SME_Znx4_SME_Zmx4(
            UMLSLL_SME_ZA_array_off1x4_SME_Znx4_SME_Zmx4::from(bits),
        ))
    }
}
impl InsnOpcode for UMLSLL_SME_ZA_array_off1x4_SME_Znx4_SME_Zmx4 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UMLSLL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "umlsll",
        aliases: &[],
        opcode: 0xc1200418,
        mask: 0xffb09c1c,
        class: InsnClass::SME_INT_SD,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off2x4,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_0,
                        lsb: 0,
                        width: 2,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm,
                    lsb: 16,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_INT_SD(SME_INT_SD::UMLSLL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm(
            UMLSLL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm::from(bits),
        ))
    }
}
impl InsnOpcode for UMLSLL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UMLSLT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "umlslt",
        aliases: &[],
        opcode: 0x44005c00,
        mask: 0xff20fc00,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::UMLSLT_SVE_Zd_SVE_Zn_SVE_Zm_16(
            UMLSLT_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for UMLSLT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UMLSLT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "umlslt",
        aliases: &[],
        opcode: 0x44a0b400,
        mask: 0xffe0f400,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm3_11_INDEX,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_i3h2,
                        lsb: 19,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_i3l,
                        lsb: 11,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_imm3,
                        lsb: 16,
                        width: 3,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::UMLSLT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX(
            UMLSLT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX::from(bits),
        ))
    }
}
impl InsnOpcode for UMLSLT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UMLSLT_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "umlslt",
        aliases: &[],
        opcode: 0x44e0b400,
        mask: 0xffe0f400,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm4_11_INDEX,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_i2h,
                        lsb: 20,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_i3l,
                        lsb: 11,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_imm4,
                        lsb: 16,
                        width: 4,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::UMLSLT_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX(
            UMLSLT_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX::from(bits),
        ))
    }
}
impl InsnOpcode for UMLSLT_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UMMLA_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ummla",
        aliases: &[],
        opcode: 0x45c09800,
        mask: 0xffe0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::I8MM_SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::UMMLA_SVE_Zd_SVE_Zn_SVE_Zm_16(
            UMMLA_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for UMMLA_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UMMLA_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ummla",
        aliases: &[],
        opcode: 0x6e80a400,
        mask: 0xffe0fc00,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::I8MM,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(AARCH64_MISC::UMMLA_Vd_Vn_Vm(UMMLA_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for UMMLA_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UMOPA_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "umopa",
        aliases: &[],
        opcode: 0xa1800008,
        mask: 0xffe0001c,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZAda_2b,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_ZAda_2b,
                    lsb: 0,
                    width: 2,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Pm,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Pm,
                    lsb: 13,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::UMOPA_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16(
            UMOPA_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for UMOPA_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UMOPA_SME_ZAda_2b_S_S_SVE_Pg3_P_M_SME_Pm_P_M_SVE_Zn_S_B_SVE_Zm_16_S_B {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "umopa",
        aliases: &[],
        opcode: 0xa1a00000,
        mask: 0xffe0001c,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZAda_2b,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_ZAda_2b,
                    lsb: 0,
                    width: 2,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Pm,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Pm,
                    lsb: 13,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(
            SME_MISC::UMOPA_SME_ZAda_2b_S_S_SVE_Pg3_P_M_SME_Pm_P_M_SVE_Zn_S_B_SVE_Zm_16_S_B(
                UMOPA_SME_ZAda_2b_S_S_SVE_Pg3_P_M_SME_Pm_P_M_SVE_Zn_S_B_SVE_Zm_16_S_B::from(bits),
            ),
        )
    }
}
impl InsnOpcode for UMOPA_SME_ZAda_2b_S_S_SVE_Pg3_P_M_SME_Pm_P_M_SVE_Zn_S_B_SVE_Zm_16_S_B {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UMOPA_SME_ZAda_3b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "umopa",
        aliases: &[],
        opcode: 0xa1e00000,
        mask: 0xffe00018,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME_I16I64,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZAda_3b,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_ZAda_3b,
                    lsb: 0,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Pm,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Pm,
                    lsb: 13,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::UMOPA_SME_ZAda_3b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16(
            UMOPA_SME_ZAda_3b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for UMOPA_SME_ZAda_3b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UMOPS_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "umops",
        aliases: &[],
        opcode: 0xa1800018,
        mask: 0xffe0001c,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZAda_2b,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_ZAda_2b,
                    lsb: 0,
                    width: 2,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Pm,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Pm,
                    lsb: 13,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::UMOPS_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16(
            UMOPS_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for UMOPS_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UMOPS_SME_ZAda_2b_S_S_SVE_Pg3_P_M_SME_Pm_P_M_SVE_Zn_S_B_SVE_Zm_16_S_B {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "umops",
        aliases: &[],
        opcode: 0xa1a00010,
        mask: 0xffe0001c,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZAda_2b,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_ZAda_2b,
                    lsb: 0,
                    width: 2,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Pm,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Pm,
                    lsb: 13,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(
            SME_MISC::UMOPS_SME_ZAda_2b_S_S_SVE_Pg3_P_M_SME_Pm_P_M_SVE_Zn_S_B_SVE_Zm_16_S_B(
                UMOPS_SME_ZAda_2b_S_S_SVE_Pg3_P_M_SME_Pm_P_M_SVE_Zn_S_B_SVE_Zm_16_S_B::from(bits),
            ),
        )
    }
}
impl InsnOpcode for UMOPS_SME_ZAda_2b_S_S_SVE_Pg3_P_M_SME_Pm_P_M_SVE_Zn_S_B_SVE_Zm_16_S_B {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UMOPS_SME_ZAda_3b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "umops",
        aliases: &[],
        opcode: 0xa1e00010,
        mask: 0xffe00018,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME_I16I64,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZAda_3b,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_ZAda_3b,
                    lsb: 0,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Pm,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Pm,
                    lsb: 13,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::UMOPS_SME_ZAda_3b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16(
            UMOPS_SME_ZAda_3b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for UMOPS_SME_ZAda_3b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UMOV_Rd_En {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "umov",
        aliases: &[],
        opcode: 0xe003c00,
        mask: 0xbfe0fc00,
        class: InsnClass::ASIMDINS,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::En,
                class: InsnOperandClass::SIMD_ELEMENT,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_ADVSIMV_GPRSIZE_IN_Q.bits() | InsnFlags::HAS_ALIAS.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDINS(ASIMDINS::UMOV_Rd_En(UMOV_Rd_En::from(bits)))
    }
}
impl InsnOpcode for UMOV_Rd_En {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UMSUBL_Rd_Rn_Rm_Ra {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "umsubl",
        aliases: &[],
        opcode: 0x9ba08000,
        mask: 0xffe08000,
        class: InsnClass::DP_3SRC,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rm,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Ra,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Ra,
                    lsb: 10,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ALIAS.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::DP_3SRC(DP_3SRC::UMSUBL_Rd_Rn_Rm_Ra(UMSUBL_Rd_Rn_Rm_Ra::from(bits)))
    }
}
impl InsnOpcode for UMSUBL_Rd_Rn_Rm_Ra {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UMULH_Rd_Rn_Rm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "umulh",
        aliases: &[],
        opcode: 0x9bc07c00,
        mask: 0xffe0fc00,
        class: InsnClass::DP_3SRC,
        feature_set: InsnFeatureSet::V8,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rm,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::DP_3SRC(DP_3SRC::UMULH_Rd_Rn_Rm(UMULH_Rd_Rn_Rm::from(bits)))
    }
}
impl InsnOpcode for UMULH_Rd_Rn_Rm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UMULH_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "umulh",
        aliases: &[],
        opcode: 0x4130000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_5,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_5,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::UMULH_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(
            UMULH_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5::from(bits),
        ))
    }
}
impl InsnOpcode for UMULH_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UMULH_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "umulh",
        aliases: &[],
        opcode: 0x4206c00,
        mask: 0xff20fc00,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::UMULH_SVE_Zd_SVE_Zn_SVE_Zm_16(
            UMULH_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for UMULH_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UMULL_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "umull",
        aliases: &[],
        opcode: 0x2e20c000,
        mask: 0xff20fc00,
        class: InsnClass::ASIMDDIFF,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8H, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_4H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_4H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDDIFF(ASIMDDIFF::UMULL_Vd_Vn_Vm(UMULL_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for UMULL_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UMULL_Vd_Vn_Em16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "umull",
        aliases: &[],
        opcode: 0x2f00a000,
        mask: 0xff00f400,
        class: InsnClass::ASIMDELEM,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4S, InsnOperandQualifier::V_2D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4H, InsnOperandQualifier::V_2S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Em16,
                class: InsnOperandClass::SIMD_ELEMENT,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDELEM(ASIMDELEM::UMULL_Vd_Vn_Em16(UMULL_Vd_Vn_Em16::from(bits)))
    }
}
impl InsnOpcode for UMULL_Vd_Vn_Em16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UMULL2_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "umull2",
        aliases: &[],
        opcode: 0x6e20c000,
        mask: 0xff20fc00,
        class: InsnClass::ASIMDDIFF,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8H, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_16B, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_16B, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDDIFF(ASIMDDIFF::UMULL2_Vd_Vn_Vm(UMULL2_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for UMULL2_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UMULL2_Vd_Vn_Em16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "umull2",
        aliases: &[],
        opcode: 0x6f00a000,
        mask: 0xff00f400,
        class: InsnClass::ASIMDELEM,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4S, InsnOperandQualifier::V_2D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8H, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Em16,
                class: InsnOperandClass::SIMD_ELEMENT,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDELEM(ASIMDELEM::UMULL2_Vd_Vn_Em16(UMULL2_Vd_Vn_Em16::from(bits)))
    }
}
impl InsnOpcode for UMULL2_Vd_Vn_Em16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UMULLB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "umullb",
        aliases: &[],
        opcode: 0x44a0d000,
        mask: 0xffe0f400,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm3_11_INDEX,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_i3h2,
                        lsb: 19,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_i3l,
                        lsb: 11,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_imm3,
                        lsb: 16,
                        width: 3,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::UMULLB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX(
            UMULLB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX::from(bits),
        ))
    }
}
impl InsnOpcode for UMULLB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UMULLB_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "umullb",
        aliases: &[],
        opcode: 0x44e0d000,
        mask: 0xffe0f400,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm4_11_INDEX,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_i2h,
                        lsb: 20,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_i3l,
                        lsb: 11,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_imm4,
                        lsb: 16,
                        width: 4,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::UMULLB_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX(
            UMULLB_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX::from(bits),
        ))
    }
}
impl InsnOpcode for UMULLB_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UMULLB_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "umullb",
        aliases: &[],
        opcode: 0x45007800,
        mask: 0xff20fc00,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::UMULLB_SVE_Zd_SVE_Zn_SVE_Zm_16(
            UMULLB_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for UMULLB_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UMULLT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "umullt",
        aliases: &[],
        opcode: 0x44a0d400,
        mask: 0xffe0f400,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm3_11_INDEX,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_i3h2,
                        lsb: 19,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_i3l,
                        lsb: 11,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_imm3,
                        lsb: 16,
                        width: 3,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::UMULLT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX(
            UMULLT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX::from(bits),
        ))
    }
}
impl InsnOpcode for UMULLT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UMULLT_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "umullt",
        aliases: &[],
        opcode: 0x44e0d400,
        mask: 0xffe0f400,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm4_11_INDEX,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_i2h,
                        lsb: 20,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_i3l,
                        lsb: 11,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_imm4,
                        lsb: 16,
                        width: 4,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::UMULLT_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX(
            UMULLT_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX::from(bits),
        ))
    }
}
impl InsnOpcode for UMULLT_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UMULLT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "umullt",
        aliases: &[],
        opcode: 0x45007c00,
        mask: 0xff20fc00,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::UMULLT_SVE_Zd_SVE_Zn_SVE_Zm_16(
            UMULLT_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for UMULLT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UQADD_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uqadd",
        aliases: &[],
        opcode: 0x4201400,
        mask: 0xff20fc00,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::UQADD_SVE_Zd_SVE_Zn_SVE_Zm_16(
            UQADD_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for UQADD_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UQADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uqadd",
        aliases: &[],
        opcode: 0x44198000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::UQADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(
            UQADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for UQADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UQADD_SVE_Zd_SVE_Zd_SVE_AIMM {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uqadd",
        aliases: &[],
        opcode: 0x2525c000,
        mask: 0xff3fc000,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_AIMM,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_imm9,
                    lsb: 5,
                    width: 9,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::UQADD_SVE_Zd_SVE_Zd_SVE_AIMM(
            UQADD_SVE_Zd_SVE_Zd_SVE_AIMM::from(bits),
        ))
    }
}
impl InsnOpcode for UQADD_SVE_Zd_SVE_Zd_SVE_AIMM {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UQADD_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uqadd",
        aliases: &[],
        opcode: 0x2e200c00,
        mask: 0xbf20fc00,
        class: InsnClass::ASIMDSAME,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSAME(ASIMDSAME::UQADD_Vd_Vn_Vm(UQADD_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for UQADD_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UQADD_Sd_Sn_Sm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uqadd",
        aliases: &[],
        opcode: 0x7e200c00,
        mask: 0xff20fc00,
        class: InsnClass::ASISDSAME,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sm,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMD_SCALAR_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDSAME(ASISDSAME::UQADD_Sd_Sn_Sm(UQADD_Sd_Sn_Sm::from(bits)))
    }
}
impl InsnOpcode for UQADD_Sd_Sn_Sm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UQCVT_SVE_Zd_SME_Znx2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uqcvt",
        aliases: &[],
        opcode: 0xc123e020,
        mask: 0xfffffc20,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn2,
                    lsb: 6,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::UQCVT_SVE_Zd_SME_Znx2(
            UQCVT_SVE_Zd_SME_Znx2::from(bits),
        ))
    }
}
impl InsnOpcode for UQCVT_SVE_Zd_SME_Znx2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UQCVT_SVE_Zd_SME_Znx4 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uqcvt",
        aliases: &[],
        opcode: 0xc133e020,
        mask: 0xff7ffc60,
        class: InsnClass::SME_SZ_23,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn4,
                    lsb: 7,
                    width: 3,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_SZ_23(SME_SZ_23::UQCVT_SVE_Zd_SME_Znx4(
            UQCVT_SVE_Zd_SME_Znx4::from(bits),
        ))
    }
}
impl InsnOpcode for UQCVT_SVE_Zd_SME_Znx4 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UQCVTN_SVE_Zd_SME_Znx4 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uqcvtn",
        aliases: &[],
        opcode: 0xc133e060,
        mask: 0xff7ffc60,
        class: InsnClass::SME_SZ_23,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn4,
                    lsb: 7,
                    width: 3,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_SZ_23(SME_SZ_23::UQCVTN_SVE_Zd_SME_Znx4(
            UQCVTN_SVE_Zd_SME_Znx4::from(bits),
        ))
    }
}
impl InsnOpcode for UQCVTN_SVE_Zd_SME_Znx4 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UQCVTN_SVE_Zd_SME_Znx2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uqcvtn",
        aliases: &[],
        opcode: 0x45314800,
        mask: 0xfffffc20,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn2,
                    lsb: 6,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::UQCVTN_SVE_Zd_SME_Znx2(
            UQCVTN_SVE_Zd_SME_Znx2::from(bits),
        ))
    }
}
impl InsnOpcode for UQCVTN_SVE_Zd_SME_Znx2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UQDECB_Rd_SVE_PATTERN_SCALED {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uqdecb",
        aliases: &[],
        opcode: 0x420fc00,
        mask: 0xfff0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_PATTERN_SCALED,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_pattern,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::UQDECB_Rd_SVE_PATTERN_SCALED(
            UQDECB_Rd_SVE_PATTERN_SCALED::from(bits),
        ))
    }
}
impl InsnOpcode for UQDECB_Rd_SVE_PATTERN_SCALED {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UQDECB_Rd_X_SVE_PATTERN_SCALED {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uqdecb",
        aliases: &[],
        opcode: 0x430fc00,
        mask: 0xfff0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_PATTERN_SCALED,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_pattern,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::UQDECB_Rd_X_SVE_PATTERN_SCALED(
            UQDECB_Rd_X_SVE_PATTERN_SCALED::from(bits),
        ))
    }
}
impl InsnOpcode for UQDECB_Rd_X_SVE_PATTERN_SCALED {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UQDECD_SVE_Zd_SVE_PATTERN_SCALED {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uqdecd",
        aliases: &[],
        opcode: 0x4e0cc00,
        mask: 0xfff0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_PATTERN_SCALED,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_pattern,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::UQDECD_SVE_Zd_SVE_PATTERN_SCALED(
            UQDECD_SVE_Zd_SVE_PATTERN_SCALED::from(bits),
        ))
    }
}
impl InsnOpcode for UQDECD_SVE_Zd_SVE_PATTERN_SCALED {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UQDECD_Rd_SVE_PATTERN_SCALED {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uqdecd",
        aliases: &[],
        opcode: 0x4e0fc00,
        mask: 0xfff0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_PATTERN_SCALED,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_pattern,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::UQDECD_Rd_SVE_PATTERN_SCALED(
            UQDECD_Rd_SVE_PATTERN_SCALED::from(bits),
        ))
    }
}
impl InsnOpcode for UQDECD_Rd_SVE_PATTERN_SCALED {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UQDECD_Rd_X_SVE_PATTERN_SCALED {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uqdecd",
        aliases: &[],
        opcode: 0x4f0fc00,
        mask: 0xfff0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_PATTERN_SCALED,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_pattern,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::UQDECD_Rd_X_SVE_PATTERN_SCALED(
            UQDECD_Rd_X_SVE_PATTERN_SCALED::from(bits),
        ))
    }
}
impl InsnOpcode for UQDECD_Rd_X_SVE_PATTERN_SCALED {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UQDECH_SVE_Zd_SVE_PATTERN_SCALED {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uqdech",
        aliases: &[],
        opcode: 0x460cc00,
        mask: 0xfff0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_PATTERN_SCALED,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_pattern,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::UQDECH_SVE_Zd_SVE_PATTERN_SCALED(
            UQDECH_SVE_Zd_SVE_PATTERN_SCALED::from(bits),
        ))
    }
}
impl InsnOpcode for UQDECH_SVE_Zd_SVE_PATTERN_SCALED {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UQDECH_Rd_SVE_PATTERN_SCALED {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uqdech",
        aliases: &[],
        opcode: 0x460fc00,
        mask: 0xfff0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_PATTERN_SCALED,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_pattern,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::UQDECH_Rd_SVE_PATTERN_SCALED(
            UQDECH_Rd_SVE_PATTERN_SCALED::from(bits),
        ))
    }
}
impl InsnOpcode for UQDECH_Rd_SVE_PATTERN_SCALED {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UQDECH_Rd_X_SVE_PATTERN_SCALED {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uqdech",
        aliases: &[],
        opcode: 0x470fc00,
        mask: 0xfff0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_PATTERN_SCALED,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_pattern,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::UQDECH_Rd_X_SVE_PATTERN_SCALED(
            UQDECH_Rd_X_SVE_PATTERN_SCALED::from(bits),
        ))
    }
}
impl InsnOpcode for UQDECH_Rd_X_SVE_PATTERN_SCALED {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UQDECP_SVE_Zd_SVE_Pg4_5 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uqdecp",
        aliases: &[],
        opcode: 0x252b8000,
        mask: 0xff3ffe00,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg4_5,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg4_5,
                    lsb: 5,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::UQDECP_SVE_Zd_SVE_Pg4_5(
            UQDECP_SVE_Zd_SVE_Pg4_5::from(bits),
        ))
    }
}
impl InsnOpcode for UQDECP_SVE_Zd_SVE_Pg4_5 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UQDECP_Rd_SVE_Pg4_5 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uqdecp",
        aliases: &[],
        opcode: 0x252b8800,
        mask: 0xff3ffe00,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg4_5,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg4_5,
                    lsb: 5,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::UQDECP_Rd_SVE_Pg4_5(
            UQDECP_Rd_SVE_Pg4_5::from(bits),
        ))
    }
}
impl InsnOpcode for UQDECP_Rd_SVE_Pg4_5 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UQDECP_Rd_X_SVE_Pg4_5_S_B {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uqdecp",
        aliases: &[],
        opcode: 0x252b8c00,
        mask: 0xff3ffe00,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg4_5,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg4_5,
                    lsb: 5,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::UQDECP_Rd_X_SVE_Pg4_5_S_B(
            UQDECP_Rd_X_SVE_Pg4_5_S_B::from(bits),
        ))
    }
}
impl InsnOpcode for UQDECP_Rd_X_SVE_Pg4_5_S_B {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UQDECW_SVE_Zd_SVE_PATTERN_SCALED {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uqdecw",
        aliases: &[],
        opcode: 0x4a0cc00,
        mask: 0xfff0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_PATTERN_SCALED,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_pattern,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::UQDECW_SVE_Zd_SVE_PATTERN_SCALED(
            UQDECW_SVE_Zd_SVE_PATTERN_SCALED::from(bits),
        ))
    }
}
impl InsnOpcode for UQDECW_SVE_Zd_SVE_PATTERN_SCALED {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UQDECW_Rd_SVE_PATTERN_SCALED {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uqdecw",
        aliases: &[],
        opcode: 0x4a0fc00,
        mask: 0xfff0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_PATTERN_SCALED,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_pattern,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::UQDECW_Rd_SVE_PATTERN_SCALED(
            UQDECW_Rd_SVE_PATTERN_SCALED::from(bits),
        ))
    }
}
impl InsnOpcode for UQDECW_Rd_SVE_PATTERN_SCALED {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UQDECW_Rd_X_SVE_PATTERN_SCALED {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uqdecw",
        aliases: &[],
        opcode: 0x4b0fc00,
        mask: 0xfff0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_PATTERN_SCALED,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_pattern,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::UQDECW_Rd_X_SVE_PATTERN_SCALED(
            UQDECW_Rd_X_SVE_PATTERN_SCALED::from(bits),
        ))
    }
}
impl InsnOpcode for UQDECW_Rd_X_SVE_PATTERN_SCALED {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UQINCB_Rd_SVE_PATTERN_SCALED {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uqincb",
        aliases: &[],
        opcode: 0x420f400,
        mask: 0xfff0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_PATTERN_SCALED,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_pattern,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::UQINCB_Rd_SVE_PATTERN_SCALED(
            UQINCB_Rd_SVE_PATTERN_SCALED::from(bits),
        ))
    }
}
impl InsnOpcode for UQINCB_Rd_SVE_PATTERN_SCALED {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UQINCB_Rd_X_SVE_PATTERN_SCALED {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uqincb",
        aliases: &[],
        opcode: 0x430f400,
        mask: 0xfff0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_PATTERN_SCALED,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_pattern,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::UQINCB_Rd_X_SVE_PATTERN_SCALED(
            UQINCB_Rd_X_SVE_PATTERN_SCALED::from(bits),
        ))
    }
}
impl InsnOpcode for UQINCB_Rd_X_SVE_PATTERN_SCALED {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UQINCD_SVE_Zd_SVE_PATTERN_SCALED {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uqincd",
        aliases: &[],
        opcode: 0x4e0c400,
        mask: 0xfff0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_PATTERN_SCALED,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_pattern,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::UQINCD_SVE_Zd_SVE_PATTERN_SCALED(
            UQINCD_SVE_Zd_SVE_PATTERN_SCALED::from(bits),
        ))
    }
}
impl InsnOpcode for UQINCD_SVE_Zd_SVE_PATTERN_SCALED {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UQINCD_Rd_SVE_PATTERN_SCALED {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uqincd",
        aliases: &[],
        opcode: 0x4e0f400,
        mask: 0xfff0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_PATTERN_SCALED,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_pattern,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::UQINCD_Rd_SVE_PATTERN_SCALED(
            UQINCD_Rd_SVE_PATTERN_SCALED::from(bits),
        ))
    }
}
impl InsnOpcode for UQINCD_Rd_SVE_PATTERN_SCALED {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UQINCD_Rd_X_SVE_PATTERN_SCALED {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uqincd",
        aliases: &[],
        opcode: 0x4f0f400,
        mask: 0xfff0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_PATTERN_SCALED,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_pattern,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::UQINCD_Rd_X_SVE_PATTERN_SCALED(
            UQINCD_Rd_X_SVE_PATTERN_SCALED::from(bits),
        ))
    }
}
impl InsnOpcode for UQINCD_Rd_X_SVE_PATTERN_SCALED {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UQINCH_SVE_Zd_SVE_PATTERN_SCALED {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uqinch",
        aliases: &[],
        opcode: 0x460c400,
        mask: 0xfff0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_PATTERN_SCALED,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_pattern,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::UQINCH_SVE_Zd_SVE_PATTERN_SCALED(
            UQINCH_SVE_Zd_SVE_PATTERN_SCALED::from(bits),
        ))
    }
}
impl InsnOpcode for UQINCH_SVE_Zd_SVE_PATTERN_SCALED {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UQINCH_Rd_SVE_PATTERN_SCALED {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uqinch",
        aliases: &[],
        opcode: 0x460f400,
        mask: 0xfff0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_PATTERN_SCALED,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_pattern,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::UQINCH_Rd_SVE_PATTERN_SCALED(
            UQINCH_Rd_SVE_PATTERN_SCALED::from(bits),
        ))
    }
}
impl InsnOpcode for UQINCH_Rd_SVE_PATTERN_SCALED {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UQINCH_Rd_X_SVE_PATTERN_SCALED {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uqinch",
        aliases: &[],
        opcode: 0x470f400,
        mask: 0xfff0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_PATTERN_SCALED,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_pattern,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::UQINCH_Rd_X_SVE_PATTERN_SCALED(
            UQINCH_Rd_X_SVE_PATTERN_SCALED::from(bits),
        ))
    }
}
impl InsnOpcode for UQINCH_Rd_X_SVE_PATTERN_SCALED {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UQINCP_SVE_Zd_SVE_Pg4_5 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uqincp",
        aliases: &[],
        opcode: 0x25298000,
        mask: 0xff3ffe00,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg4_5,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg4_5,
                    lsb: 5,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::UQINCP_SVE_Zd_SVE_Pg4_5(
            UQINCP_SVE_Zd_SVE_Pg4_5::from(bits),
        ))
    }
}
impl InsnOpcode for UQINCP_SVE_Zd_SVE_Pg4_5 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UQINCP_Rd_SVE_Pg4_5 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uqincp",
        aliases: &[],
        opcode: 0x25298800,
        mask: 0xff3ffe00,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg4_5,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg4_5,
                    lsb: 5,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::UQINCP_Rd_SVE_Pg4_5(
            UQINCP_Rd_SVE_Pg4_5::from(bits),
        ))
    }
}
impl InsnOpcode for UQINCP_Rd_SVE_Pg4_5 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UQINCP_Rd_X_SVE_Pg4_5_S_B {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uqincp",
        aliases: &[],
        opcode: 0x25298c00,
        mask: 0xff3ffe00,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg4_5,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg4_5,
                    lsb: 5,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::UQINCP_Rd_X_SVE_Pg4_5_S_B(
            UQINCP_Rd_X_SVE_Pg4_5_S_B::from(bits),
        ))
    }
}
impl InsnOpcode for UQINCP_Rd_X_SVE_Pg4_5_S_B {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UQINCW_SVE_Zd_SVE_PATTERN_SCALED {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uqincw",
        aliases: &[],
        opcode: 0x4a0c400,
        mask: 0xfff0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_PATTERN_SCALED,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_pattern,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::UQINCW_SVE_Zd_SVE_PATTERN_SCALED(
            UQINCW_SVE_Zd_SVE_PATTERN_SCALED::from(bits),
        ))
    }
}
impl InsnOpcode for UQINCW_SVE_Zd_SVE_PATTERN_SCALED {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UQINCW_Rd_SVE_PATTERN_SCALED {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uqincw",
        aliases: &[],
        opcode: 0x4a0f400,
        mask: 0xfff0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_PATTERN_SCALED,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_pattern,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::UQINCW_Rd_SVE_PATTERN_SCALED(
            UQINCW_Rd_SVE_PATTERN_SCALED::from(bits),
        ))
    }
}
impl InsnOpcode for UQINCW_Rd_SVE_PATTERN_SCALED {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UQINCW_Rd_X_SVE_PATTERN_SCALED {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uqincw",
        aliases: &[],
        opcode: 0x4b0f400,
        mask: 0xfff0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Rd,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_PATTERN_SCALED,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_pattern,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::UQINCW_Rd_X_SVE_PATTERN_SCALED(
            UQINCW_Rd_X_SVE_PATTERN_SCALED::from(bits),
        ))
    }
}
impl InsnOpcode for UQINCW_Rd_X_SVE_PATTERN_SCALED {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UQRSHL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uqrshl",
        aliases: &[],
        opcode: 0x440b8000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::UQRSHL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(
            UQRSHL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for UQRSHL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UQRSHL_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uqrshl",
        aliases: &[],
        opcode: 0x2e205c00,
        mask: 0xbf20fc00,
        class: InsnClass::ASIMDSAME,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSAME(ASIMDSAME::UQRSHL_Vd_Vn_Vm(UQRSHL_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for UQRSHL_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UQRSHL_Sd_Sn_Sm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uqrshl",
        aliases: &[],
        opcode: 0x7e205c00,
        mask: 0xff20fc00,
        class: InsnClass::ASISDSAME,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sm,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMD_SCALAR_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDSAME(ASISDSAME::UQRSHL_Sd_Sn_Sm(UQRSHL_Sd_Sn_Sm::from(bits)))
    }
}
impl InsnOpcode for UQRSHL_Sd_Sn_Sm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UQRSHLR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uqrshlr",
        aliases: &[],
        opcode: 0x440f8000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::UQRSHLR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(
            UQRSHLR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for UQRSHLR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UQRSHR_SVE_Zd_SME_Znx4_SME_SHRIMM5 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uqrshr",
        aliases: &[],
        opcode: 0xc120d820,
        mask: 0xff20fc60,
        class: InsnClass::SME_SHIFT,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn4,
                    lsb: 7,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_SHRIMM5,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_tszh,
                        lsb: 22,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_imm5b,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_SHIFT(SME_SHIFT::UQRSHR_SVE_Zd_SME_Znx4_SME_SHRIMM5(
            UQRSHR_SVE_Zd_SME_Znx4_SME_SHRIMM5::from(bits),
        ))
    }
}
impl InsnOpcode for UQRSHR_SVE_Zd_SME_Znx4_SME_SHRIMM5 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UQRSHR_SVE_Zd_SME_Znx2_SME_SHRIMM4 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uqrshr",
        aliases: &[],
        opcode: 0xc1e0d420,
        mask: 0xfff0fc20,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn2,
                    lsb: 6,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_SHRIMM4,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_imm4,
                    lsb: 16,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::UQRSHR_SVE_Zd_SME_Znx2_SME_SHRIMM4(
            UQRSHR_SVE_Zd_SME_Znx2_SME_SHRIMM4::from(bits),
        ))
    }
}
impl InsnOpcode for UQRSHR_SVE_Zd_SME_Znx2_SME_SHRIMM4 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UQRSHRN_SVE_Zd_SME_Znx4_SME_SHRIMM5 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uqrshrn",
        aliases: &[],
        opcode: 0xc120dc20,
        mask: 0xff20fc60,
        class: InsnClass::SME_SHIFT,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn4,
                    lsb: 7,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_SHRIMM5,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_tszh,
                        lsb: 22,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_imm5b,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_SHIFT(SME_SHIFT::UQRSHRN_SVE_Zd_SME_Znx4_SME_SHRIMM5(
            UQRSHRN_SVE_Zd_SME_Znx4_SME_SHRIMM5::from(bits),
        ))
    }
}
impl InsnOpcode for UQRSHRN_SVE_Zd_SME_Znx4_SME_SHRIMM5 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UQRSHRN_SVE_Zd_SME_Znx2_SME_SHRIMM4 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uqrshrn",
        aliases: &[],
        opcode: 0x45b03800,
        mask: 0xfff0fc20,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn2,
                    lsb: 6,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_SHRIMM4,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_imm4,
                    lsb: 16,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::UQRSHRN_SVE_Zd_SME_Znx2_SME_SHRIMM4(
            UQRSHRN_SVE_Zd_SME_Znx2_SME_SHRIMM4::from(bits),
        ))
    }
}
impl InsnOpcode for UQRSHRN_SVE_Zd_SME_Znx2_SME_SHRIMM4 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UQRSHRN_Vd_Vn_IMM_VLSR {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uqrshrn",
        aliases: &[],
        opcode: 0x2f009c00,
        mask: 0xff80fc00,
        class: InsnClass::ASIMDSHF,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_4H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8H, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::IMM_VLSR,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_4H],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSHF(ASIMDSHF::UQRSHRN_Vd_Vn_IMM_VLSR(
            UQRSHRN_Vd_Vn_IMM_VLSR::from(bits),
        ))
    }
}
impl InsnOpcode for UQRSHRN_Vd_Vn_IMM_VLSR {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UQRSHRN_Sd_Sn_IMM_VLSR {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uqrshrn",
        aliases: &[],
        opcode: 0x7f009c00,
        mask: 0xff80fc00,
        class: InsnClass::ASISDSHF,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::IMM_VLSR,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDSHF(ASISDSHF::UQRSHRN_Sd_Sn_IMM_VLSR(
            UQRSHRN_Sd_Sn_IMM_VLSR::from(bits),
        ))
    }
}
impl InsnOpcode for UQRSHRN_Sd_Sn_IMM_VLSR {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UQRSHRN2_Vd_Vn_IMM_VLSR {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uqrshrn2",
        aliases: &[],
        opcode: 0x6f009c00,
        mask: 0xff80fc00,
        class: InsnClass::ASIMDSHF,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_16B, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8H, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::IMM_VLSR,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[InsnOperandQualifier::V_16B, InsnOperandQualifier::V_8H],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSHF(ASIMDSHF::UQRSHRN2_Vd_Vn_IMM_VLSR(
            UQRSHRN2_Vd_Vn_IMM_VLSR::from(bits),
        ))
    }
}
impl InsnOpcode for UQRSHRN2_Vd_Vn_IMM_VLSR {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UQRSHRNB_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uqrshrnb",
        aliases: &[],
        opcode: 0x45203800,
        mask: 0xffa0fc00,
        class: InsnClass::SVE_SHIFT_TSZ_HSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_SHRIMM_UNPRED_22,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_sz,
                        lsb: 22,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_tszl_19,
                        lsb: 19,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_imm3,
                        lsb: 16,
                        width: 3,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SHIFT_TSZ_HSD(
            SVE_SHIFT_TSZ_HSD::UQRSHRNB_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22(
                UQRSHRNB_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22::from(bits),
            ),
        )
    }
}
impl InsnOpcode for UQRSHRNB_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UQRSHRNT_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uqrshrnt",
        aliases: &[],
        opcode: 0x45203c00,
        mask: 0xffa0fc00,
        class: InsnClass::SVE_SHIFT_TSZ_HSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_SHRIMM_UNPRED_22,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_sz,
                        lsb: 22,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_tszl_19,
                        lsb: 19,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_imm3,
                        lsb: 16,
                        width: 3,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SHIFT_TSZ_HSD(
            SVE_SHIFT_TSZ_HSD::UQRSHRNT_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22(
                UQRSHRNT_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22::from(bits),
            ),
        )
    }
}
impl InsnOpcode for UQRSHRNT_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UQSHL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uqshl",
        aliases: &[],
        opcode: 0x44098000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::UQSHL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(
            UQSHL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for UQSHL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UQSHL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_SHLIMM_PRED {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uqshl",
        aliases: &[],
        opcode: 0x4078000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SHIFT_PRED,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_SHLIMM_PRED,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_tszh,
                        lsb: 22,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_imm5,
                        lsb: 5,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SHIFT_PRED(SVE_SHIFT_PRED::UQSHL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_SHLIMM_PRED(
            UQSHL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_SHLIMM_PRED::from(bits),
        ))
    }
}
impl InsnOpcode for UQSHL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_SHLIMM_PRED {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UQSHL_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uqshl",
        aliases: &[],
        opcode: 0x2e204c00,
        mask: 0xbf20fc00,
        class: InsnClass::ASIMDSAME,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSAME(ASIMDSAME::UQSHL_Vd_Vn_Vm(UQSHL_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for UQSHL_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UQSHL_Sd_Sn_Sm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uqshl",
        aliases: &[],
        opcode: 0x7e204c00,
        mask: 0xff20fc00,
        class: InsnClass::ASISDSAME,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sm,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMD_SCALAR_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDSAME(ASISDSAME::UQSHL_Sd_Sn_Sm(UQSHL_Sd_Sn_Sm::from(bits)))
    }
}
impl InsnOpcode for UQSHL_Sd_Sn_Sm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UQSHL_Vd_Vn_IMM_VLSL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uqshl",
        aliases: &[],
        opcode: 0x2f007400,
        mask: 0xbf80fc00,
        class: InsnClass::ASIMDSHF,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::IMM_VLSL,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSHF(ASIMDSHF::UQSHL_Vd_Vn_IMM_VLSL(UQSHL_Vd_Vn_IMM_VLSL::from(
            bits,
        )))
    }
}
impl InsnOpcode for UQSHL_Vd_Vn_IMM_VLSL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UQSHL_Sd_Sn_IMM_VLSL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uqshl",
        aliases: &[],
        opcode: 0x7f007400,
        mask: 0xff80fc00,
        class: InsnClass::ASISDSHF,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::IMM_VLSL,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDSHF(ASISDSHF::UQSHL_Sd_Sn_IMM_VLSL(UQSHL_Sd_Sn_IMM_VLSL::from(
            bits,
        )))
    }
}
impl InsnOpcode for UQSHL_Sd_Sn_IMM_VLSL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UQSHLR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uqshlr",
        aliases: &[],
        opcode: 0x440d8000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::UQSHLR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(
            UQSHLR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for UQSHLR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UQSHRN_Vd_Vn_IMM_VLSR {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uqshrn",
        aliases: &[],
        opcode: 0x2f009400,
        mask: 0xff80fc00,
        class: InsnClass::ASIMDSHF,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_4H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8H, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::IMM_VLSR,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_4H],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSHF(ASIMDSHF::UQSHRN_Vd_Vn_IMM_VLSR(
            UQSHRN_Vd_Vn_IMM_VLSR::from(bits),
        ))
    }
}
impl InsnOpcode for UQSHRN_Vd_Vn_IMM_VLSR {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UQSHRN_Sd_Sn_IMM_VLSR {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uqshrn",
        aliases: &[],
        opcode: 0x7f009400,
        mask: 0xff80fc00,
        class: InsnClass::ASISDSHF,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::IMM_VLSR,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDSHF(ASISDSHF::UQSHRN_Sd_Sn_IMM_VLSR(
            UQSHRN_Sd_Sn_IMM_VLSR::from(bits),
        ))
    }
}
impl InsnOpcode for UQSHRN_Sd_Sn_IMM_VLSR {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UQSHRN2_Vd_Vn_IMM_VLSR {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uqshrn2",
        aliases: &[],
        opcode: 0x6f009400,
        mask: 0xff80fc00,
        class: InsnClass::ASIMDSHF,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_16B, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8H, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::IMM_VLSR,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[InsnOperandQualifier::V_16B, InsnOperandQualifier::V_8H],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSHF(ASIMDSHF::UQSHRN2_Vd_Vn_IMM_VLSR(
            UQSHRN2_Vd_Vn_IMM_VLSR::from(bits),
        ))
    }
}
impl InsnOpcode for UQSHRN2_Vd_Vn_IMM_VLSR {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UQSHRNB_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uqshrnb",
        aliases: &[],
        opcode: 0x45203000,
        mask: 0xffa0fc00,
        class: InsnClass::SVE_SHIFT_TSZ_HSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_SHRIMM_UNPRED_22,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_sz,
                        lsb: 22,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_tszl_19,
                        lsb: 19,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_imm3,
                        lsb: 16,
                        width: 3,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SHIFT_TSZ_HSD(
            SVE_SHIFT_TSZ_HSD::UQSHRNB_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22(
                UQSHRNB_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22::from(bits),
            ),
        )
    }
}
impl InsnOpcode for UQSHRNB_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UQSHRNT_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uqshrnt",
        aliases: &[],
        opcode: 0x45203400,
        mask: 0xffa0fc00,
        class: InsnClass::SVE_SHIFT_TSZ_HSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_SHRIMM_UNPRED_22,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_sz,
                        lsb: 22,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_tszl_19,
                        lsb: 19,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_imm3,
                        lsb: 16,
                        width: 3,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SHIFT_TSZ_HSD(
            SVE_SHIFT_TSZ_HSD::UQSHRNT_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22(
                UQSHRNT_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22::from(bits),
            ),
        )
    }
}
impl InsnOpcode for UQSHRNT_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UQSUB_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uqsub",
        aliases: &[],
        opcode: 0x4201c00,
        mask: 0xff20fc00,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::UQSUB_SVE_Zd_SVE_Zn_SVE_Zm_16(
            UQSUB_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for UQSUB_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UQSUB_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uqsub",
        aliases: &[],
        opcode: 0x441b8000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::UQSUB_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(
            UQSUB_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for UQSUB_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UQSUB_SVE_Zd_SVE_Zd_SVE_AIMM {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uqsub",
        aliases: &[],
        opcode: 0x2527c000,
        mask: 0xff3fc000,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_AIMM,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_imm9,
                    lsb: 5,
                    width: 9,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::UQSUB_SVE_Zd_SVE_Zd_SVE_AIMM(
            UQSUB_SVE_Zd_SVE_Zd_SVE_AIMM::from(bits),
        ))
    }
}
impl InsnOpcode for UQSUB_SVE_Zd_SVE_Zd_SVE_AIMM {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UQSUB_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uqsub",
        aliases: &[],
        opcode: 0x2e202c00,
        mask: 0xbf20fc00,
        class: InsnClass::ASIMDSAME,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSAME(ASIMDSAME::UQSUB_Vd_Vn_Vm(UQSUB_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for UQSUB_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UQSUB_Sd_Sn_Sm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uqsub",
        aliases: &[],
        opcode: 0x7e202c00,
        mask: 0xff20fc00,
        class: InsnClass::ASISDSAME,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sm,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMD_SCALAR_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDSAME(ASISDSAME::UQSUB_Sd_Sn_Sm(UQSUB_Sd_Sn_Sm::from(bits)))
    }
}
impl InsnOpcode for UQSUB_Sd_Sn_Sm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UQSUBR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uqsubr",
        aliases: &[],
        opcode: 0x441f8000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::UQSUBR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(
            UQSUBR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for UQSUBR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UQXTN_Vd_Vn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uqxtn",
        aliases: &[],
        opcode: 0x2e214800,
        mask: 0xff3ffc00,
        class: InsnClass::ASIMDMISC,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDMISC(ASIMDMISC::UQXTN_Vd_Vn(UQXTN_Vd_Vn::from(bits)))
    }
}
impl InsnOpcode for UQXTN_Vd_Vn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UQXTN_Sd_Sn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uqxtn",
        aliases: &[],
        opcode: 0x7e214800,
        mask: 0xff3ffc00,
        class: InsnClass::ASISDMISC,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMD_SCALAR_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDMISC(ASISDMISC::UQXTN_Sd_Sn(UQXTN_Sd_Sn::from(bits)))
    }
}
impl InsnOpcode for UQXTN_Sd_Sn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UQXTN2_Vd_Vn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uqxtn2",
        aliases: &[],
        opcode: 0x6e214800,
        mask: 0xff3ffc00,
        class: InsnClass::ASIMDMISC,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDMISC(ASIMDMISC::UQXTN2_Vd_Vn(UQXTN2_Vd_Vn::from(bits)))
    }
}
impl InsnOpcode for UQXTN2_Vd_Vn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UQXTNB_SVE_Zd_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uqxtnb",
        aliases: &[],
        opcode: 0x45204800,
        mask: 0xffa7fc00,
        class: InsnClass::SVE_SIZE_TSZ_BHS,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_TSZ_BHS(SVE_SIZE_TSZ_BHS::UQXTNB_SVE_Zd_SVE_Zn(
            UQXTNB_SVE_Zd_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for UQXTNB_SVE_Zd_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UQXTNT_SVE_Zd_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uqxtnt",
        aliases: &[],
        opcode: 0x45204c00,
        mask: 0xffa7fc00,
        class: InsnClass::SVE_SIZE_TSZ_BHS,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_TSZ_BHS(SVE_SIZE_TSZ_BHS::UQXTNT_SVE_Zd_SVE_Zn(
            UQXTNT_SVE_Zd_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for UQXTNT_SVE_Zd_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl URECPE_SVE_Zd_SVE_Pg3_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "urecpe",
        aliases: &[],
        opcode: 0x4480a000,
        mask: 0xffffe000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::URECPE_SVE_Zd_SVE_Pg3_SVE_Zn(
            URECPE_SVE_Zd_SVE_Pg3_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for URECPE_SVE_Zd_SVE_Pg3_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl URECPE_Vd_Vn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "urecpe",
        aliases: &[],
        opcode: 0xea1c800,
        mask: 0xbfbffc00,
        class: InsnClass::ASIMDMISC,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDMISC(ASIMDMISC::URECPE_Vd_Vn(URECPE_Vd_Vn::from(bits)))
    }
}
impl InsnOpcode for URECPE_Vd_Vn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl URHADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "urhadd",
        aliases: &[],
        opcode: 0x44158000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::URHADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(
            URHADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for URHADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl URHADD_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "urhadd",
        aliases: &[],
        opcode: 0x2e201400,
        mask: 0xbf20fc00,
        class: InsnClass::ASIMDSAME,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSAME(ASIMDSAME::URHADD_Vd_Vn_Vm(URHADD_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for URHADD_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl URSHL_SME_Zdnx2_SME_Zdnx2_SME_Zm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "urshl",
        aliases: &[],
        opcode: 0xc120a221,
        mask: 0xff30ffe1,
        class: InsnClass::SME_SIZE_22,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn2,
                    lsb: 1,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn2,
                    lsb: 1,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm,
                    lsb: 16,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_SIZE_22(SME_SIZE_22::URSHL_SME_Zdnx2_SME_Zdnx2_SME_Zm(
            URSHL_SME_Zdnx2_SME_Zdnx2_SME_Zm::from(bits),
        ))
    }
}
impl InsnOpcode for URSHL_SME_Zdnx2_SME_Zdnx2_SME_Zm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl URSHL_SME_Zdnx2_SME_Zdnx2_SME_Zmx2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "urshl",
        aliases: &[],
        opcode: 0xc120b221,
        mask: 0xff21ffe1,
        class: InsnClass::SME_SIZE_22,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn2,
                    lsb: 1,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn2,
                    lsb: 1,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zmx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm2,
                    lsb: 17,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_SIZE_22(SME_SIZE_22::URSHL_SME_Zdnx2_SME_Zdnx2_SME_Zmx2(
            URSHL_SME_Zdnx2_SME_Zdnx2_SME_Zmx2::from(bits),
        ))
    }
}
impl InsnOpcode for URSHL_SME_Zdnx2_SME_Zdnx2_SME_Zmx2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl URSHL_SME_Zdnx4_SME_Zdnx4_SME_Zm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "urshl",
        aliases: &[],
        opcode: 0xc120aa21,
        mask: 0xff30ffe3,
        class: InsnClass::SME_SIZE_22,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn4,
                    lsb: 2,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn4,
                    lsb: 2,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm,
                    lsb: 16,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_SIZE_22(SME_SIZE_22::URSHL_SME_Zdnx4_SME_Zdnx4_SME_Zm(
            URSHL_SME_Zdnx4_SME_Zdnx4_SME_Zm::from(bits),
        ))
    }
}
impl InsnOpcode for URSHL_SME_Zdnx4_SME_Zdnx4_SME_Zm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl URSHL_SME_Zdnx4_SME_Zdnx4_SME_Zmx4 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "urshl",
        aliases: &[],
        opcode: 0xc120ba21,
        mask: 0xff23ffe3,
        class: InsnClass::SME_SIZE_22,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn4,
                    lsb: 2,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn4,
                    lsb: 2,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zmx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm4,
                    lsb: 18,
                    width: 3,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_SIZE_22(SME_SIZE_22::URSHL_SME_Zdnx4_SME_Zdnx4_SME_Zmx4(
            URSHL_SME_Zdnx4_SME_Zdnx4_SME_Zmx4::from(bits),
        ))
    }
}
impl InsnOpcode for URSHL_SME_Zdnx4_SME_Zdnx4_SME_Zmx4 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl URSHL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "urshl",
        aliases: &[],
        opcode: 0x44038000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::URSHL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(
            URSHL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for URSHL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl URSHL_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "urshl",
        aliases: &[],
        opcode: 0x2e205400,
        mask: 0xbf20fc00,
        class: InsnClass::ASIMDSAME,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSAME(ASIMDSAME::URSHL_Vd_Vn_Vm(URSHL_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for URSHL_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl URSHL_Sd_Sn_Sm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "urshl",
        aliases: &[],
        opcode: 0x7ee05400,
        mask: 0xffe0fc00,
        class: InsnClass::ASISDSAME,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sm,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMD_SCALAR_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDSAME(ASISDSAME::URSHL_Sd_Sn_Sm(URSHL_Sd_Sn_Sm::from(bits)))
    }
}
impl InsnOpcode for URSHL_Sd_Sn_Sm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl URSHLR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "urshlr",
        aliases: &[],
        opcode: 0x44078000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::URSHLR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(
            URSHLR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for URSHLR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl URSHR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_SHRIMM_PRED {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "urshr",
        aliases: &[],
        opcode: 0x40d8000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SHIFT_PRED,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_SHRIMM_PRED,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_tszh,
                        lsb: 22,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_imm5,
                        lsb: 5,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SHIFT_PRED(SVE_SHIFT_PRED::URSHR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_SHRIMM_PRED(
            URSHR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_SHRIMM_PRED::from(bits),
        ))
    }
}
impl InsnOpcode for URSHR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_SHRIMM_PRED {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl URSHR_Vd_Vn_IMM_VLSR {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "urshr",
        aliases: &[],
        opcode: 0x2f002400,
        mask: 0xbf80fc00,
        class: InsnClass::ASIMDSHF,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::IMM_VLSR,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSHF(ASIMDSHF::URSHR_Vd_Vn_IMM_VLSR(URSHR_Vd_Vn_IMM_VLSR::from(
            bits,
        )))
    }
}
impl InsnOpcode for URSHR_Vd_Vn_IMM_VLSR {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl URSHR_Sd_Sn_IMM_VLSR {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "urshr",
        aliases: &[],
        opcode: 0x7f002400,
        mask: 0xff80fc00,
        class: InsnClass::ASISDSHF,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::IMM_VLSR,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDSHF(ASISDSHF::URSHR_Sd_Sn_IMM_VLSR(URSHR_Sd_Sn_IMM_VLSR::from(
            bits,
        )))
    }
}
impl InsnOpcode for URSHR_Sd_Sn_IMM_VLSR {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl URSQRTE_SVE_Zd_SVE_Pg3_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ursqrte",
        aliases: &[],
        opcode: 0x4481a000,
        mask: 0xffffe000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::URSQRTE_SVE_Zd_SVE_Pg3_SVE_Zn(
            URSQRTE_SVE_Zd_SVE_Pg3_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for URSQRTE_SVE_Zd_SVE_Pg3_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl URSQRTE_Vd_Vn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ursqrte",
        aliases: &[],
        opcode: 0x2ea1c800,
        mask: 0xbfbffc00,
        class: InsnClass::ASIMDMISC,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDMISC(ASIMDMISC::URSQRTE_Vd_Vn(URSQRTE_Vd_Vn::from(bits)))
    }
}
impl InsnOpcode for URSQRTE_Vd_Vn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl URSRA_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ursra",
        aliases: &[],
        opcode: 0x4500ec00,
        mask: 0xff20fc00,
        class: InsnClass::SVE_SHIFT_TSZ_BHSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_SHRIMM_UNPRED,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_tszh,
                        lsb: 22,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm5,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SHIFT_TSZ_BHSD(SVE_SHIFT_TSZ_BHSD::URSRA_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED(
            URSRA_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED::from(bits),
        ))
    }
}
impl InsnOpcode for URSRA_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl URSRA_Vd_Vn_IMM_VLSR {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ursra",
        aliases: &[],
        opcode: 0x2f003400,
        mask: 0xbf80fc00,
        class: InsnClass::ASIMDSHF,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::IMM_VLSR,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSHF(ASIMDSHF::URSRA_Vd_Vn_IMM_VLSR(URSRA_Vd_Vn_IMM_VLSR::from(
            bits,
        )))
    }
}
impl InsnOpcode for URSRA_Vd_Vn_IMM_VLSR {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl URSRA_Sd_Sn_IMM_VLSR {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ursra",
        aliases: &[],
        opcode: 0x7f003400,
        mask: 0xff80fc00,
        class: InsnClass::ASISDSHF,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::IMM_VLSR,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDSHF(ASISDSHF::URSRA_Sd_Sn_IMM_VLSR(URSRA_Sd_Sn_IMM_VLSR::from(
            bits,
        )))
    }
}
impl InsnOpcode for URSRA_Sd_Sn_IMM_VLSR {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl USDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "usdot",
        aliases: &[],
        opcode: 0xc1501028,
        mask: 0xfff09038,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off3_0,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_0,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn2,
                    lsb: 6,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm_INDEX2,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zm,
                        lsb: 16,
                        width: 4,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_10,
                        lsb: 10,
                        width: 2,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::USDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2(
            USDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2::from(bits),
        ))
    }
}
impl InsnOpcode for USDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl USDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "usdot",
        aliases: &[],
        opcode: 0xc1509028,
        mask: 0xfff09078,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off3_0,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_0,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn4,
                    lsb: 7,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm_INDEX2,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zm,
                        lsb: 16,
                        width: 4,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_10,
                        lsb: 10,
                        width: 2,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_4.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::USDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2(
            USDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2::from(bits),
        ))
    }
}
impl InsnOpcode for USDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl USDOT_SME_ZA_array_off3_0_SVE_ZnxN_SME_Zm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "usdot",
        aliases: &[],
        opcode: 0xc1201408,
        mask: 0xfff09c18,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off3_0,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_0,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ZnxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm,
                    lsb: 16,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::USDOT_SME_ZA_array_off3_0_SVE_ZnxN_SME_Zm(
            USDOT_SME_ZA_array_off3_0_SVE_ZnxN_SME_Zm::from(bits),
        ))
    }
}
impl InsnOpcode for USDOT_SME_ZA_array_off3_0_SVE_ZnxN_SME_Zm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl USDOT_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_B_SME_Zm_S_B {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "usdot",
        aliases: &[],
        opcode: 0xc1301408,
        mask: 0xfff09c18,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off3_0,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_0,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ZnxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm,
                    lsb: 16,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_4.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(
            SME_MISC::USDOT_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_B_SME_Zm_S_B(
                USDOT_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_B_SME_Zm_S_B::from(bits),
            ),
        )
    }
}
impl InsnOpcode for USDOT_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_B_SME_Zm_S_B {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl USDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zmx2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "usdot",
        aliases: &[],
        opcode: 0xc1a01408,
        mask: 0xffe19c38,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off3_0,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_0,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn2,
                    lsb: 6,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zmx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm2,
                    lsb: 17,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::USDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zmx2(
            USDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zmx2::from(bits),
        ))
    }
}
impl InsnOpcode for USDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zmx2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl USDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zmx4 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "usdot",
        aliases: &[],
        opcode: 0xc1a11408,
        mask: 0xffe39c78,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off3_0,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_0,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn4,
                    lsb: 7,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zmx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm4,
                    lsb: 18,
                    width: 3,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_4.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::USDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zmx4(
            USDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zmx4::from(bits),
        ))
    }
}
impl InsnOpcode for USDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zmx4 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl USDOT_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "usdot",
        aliases: &[],
        opcode: 0x44a01800,
        mask: 0xffe0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::I8MM_SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm3_INDEX,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::USDOT_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX(
            USDOT_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX::from(bits),
        ))
    }
}
impl InsnOpcode for USDOT_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl USDOT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "usdot",
        aliases: &[],
        opcode: 0x44807800,
        mask: 0xffe0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::I8MM_SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::USDOT_SVE_Zd_SVE_Zn_SVE_Zm_16(
            USDOT_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for USDOT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl USDOT_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "usdot",
        aliases: &[],
        opcode: 0xe809c00,
        mask: 0xbfe0fc00,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::I8MM,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(AARCH64_MISC::USDOT_Vd_Vn_Vm(USDOT_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for USDOT_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl USDOT_Vd_Vn_Em {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "usdot",
        aliases: &[],
        opcode: 0xf80f000,
        mask: 0xbfc0f400,
        class: InsnClass::DOTPRODUCT,
        feature_set: InsnFeatureSet::I8MM,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2S, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Em,
                class: InsnOperandClass::SIMD_ELEMENT,
                qualifiers: &[InsnOperandQualifier::S_4B, InsnOperandQualifier::S_4B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::DOTPRODUCT(DOTPRODUCT::USDOT_Vd_Vn_Em(USDOT_Vd_Vn_Em::from(bits)))
    }
}
impl InsnOpcode for USDOT_Vd_Vn_Em {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl USHL_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ushl",
        aliases: &[],
        opcode: 0x2e204400,
        mask: 0xbf20fc00,
        class: InsnClass::ASIMDSAME,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSAME(ASIMDSAME::USHL_Vd_Vn_Vm(USHL_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for USHL_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl USHL_Sd_Sn_Sm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ushl",
        aliases: &[],
        opcode: 0x7ee04400,
        mask: 0xffe0fc00,
        class: InsnClass::ASISDSAME,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sm,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMD_SCALAR_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDSAME(ASISDSAME::USHL_Sd_Sn_Sm(USHL_Sd_Sn_Sm::from(bits)))
    }
}
impl InsnOpcode for USHL_Sd_Sn_Sm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl USHLL_Vd_Vn_IMM_VLSL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ushll",
        aliases: &[],
        opcode: 0x2f00a400,
        mask: 0xff80fc00,
        class: InsnClass::ASIMDSHF,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8H, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_4H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::IMM_VLSL,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_4H],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ALIAS.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSHF(ASIMDSHF::USHLL_Vd_Vn_IMM_VLSL(USHLL_Vd_Vn_IMM_VLSL::from(
            bits,
        )))
    }
}
impl InsnOpcode for USHLL_Vd_Vn_IMM_VLSL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl USHLL2_Vd_Vn_IMM_VLSL {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ushll2",
        aliases: &[],
        opcode: 0x6f00a400,
        mask: 0xff80fc00,
        class: InsnClass::ASIMDSHF,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8H, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_16B, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::IMM_VLSL,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[InsnOperandQualifier::V_16B, InsnOperandQualifier::V_8H],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ALIAS.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSHF(ASIMDSHF::USHLL2_Vd_Vn_IMM_VLSL(
            USHLL2_Vd_Vn_IMM_VLSL::from(bits),
        ))
    }
}
impl InsnOpcode for USHLL2_Vd_Vn_IMM_VLSL {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl USHLLB_SVE_Zd_SVE_Zn_SVE_SHLIMM_UNPRED_22 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ushllb",
        aliases: &[],
        opcode: 0x4500a800,
        mask: 0xffa0fc00,
        class: InsnClass::SVE_SHIFT_TSZ_HSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_SHLIMM_UNPRED_22,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_sz,
                        lsb: 22,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_tszl_19,
                        lsb: 19,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_imm3,
                        lsb: 16,
                        width: 3,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SHIFT_TSZ_HSD(
            SVE_SHIFT_TSZ_HSD::USHLLB_SVE_Zd_SVE_Zn_SVE_SHLIMM_UNPRED_22(
                USHLLB_SVE_Zd_SVE_Zn_SVE_SHLIMM_UNPRED_22::from(bits),
            ),
        )
    }
}
impl InsnOpcode for USHLLB_SVE_Zd_SVE_Zn_SVE_SHLIMM_UNPRED_22 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl USHLLT_SVE_Zd_SVE_Zn_SVE_SHLIMM_UNPRED_22 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ushllt",
        aliases: &[],
        opcode: 0x4500ac00,
        mask: 0xffa0fc00,
        class: InsnClass::SVE_SHIFT_TSZ_HSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_SHLIMM_UNPRED_22,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_sz,
                        lsb: 22,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_tszl_19,
                        lsb: 19,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_imm3,
                        lsb: 16,
                        width: 3,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SHIFT_TSZ_HSD(
            SVE_SHIFT_TSZ_HSD::USHLLT_SVE_Zd_SVE_Zn_SVE_SHLIMM_UNPRED_22(
                USHLLT_SVE_Zd_SVE_Zn_SVE_SHLIMM_UNPRED_22::from(bits),
            ),
        )
    }
}
impl InsnOpcode for USHLLT_SVE_Zd_SVE_Zn_SVE_SHLIMM_UNPRED_22 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl USHR_Vd_Vn_IMM_VLSR {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ushr",
        aliases: &[],
        opcode: 0x2f000400,
        mask: 0xbf80fc00,
        class: InsnClass::ASIMDSHF,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::IMM_VLSR,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSHF(ASIMDSHF::USHR_Vd_Vn_IMM_VLSR(USHR_Vd_Vn_IMM_VLSR::from(
            bits,
        )))
    }
}
impl InsnOpcode for USHR_Vd_Vn_IMM_VLSR {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl USHR_Sd_Sn_IMM_VLSR {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "ushr",
        aliases: &[],
        opcode: 0x7f000400,
        mask: 0xff80fc00,
        class: InsnClass::ASISDSHF,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::IMM_VLSR,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDSHF(ASISDSHF::USHR_Sd_Sn_IMM_VLSR(USHR_Sd_Sn_IMM_VLSR::from(
            bits,
        )))
    }
}
impl InsnOpcode for USHR_Sd_Sn_IMM_VLSR {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl USMLALL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm_INDEX4_10 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "usmlall",
        aliases: &[],
        opcode: 0xc1000004,
        mask: 0xfff0001c,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off2x4,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_0,
                        lsb: 0,
                        width: 2,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm_INDEX4_10,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zm,
                        lsb: 16,
                        width: 4,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm1_15,
                        lsb: 15,
                        width: 1,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_10,
                        lsb: 10,
                        width: 3,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(
            SME_MISC::USMLALL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm_INDEX4_10(
                USMLALL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm_INDEX4_10::from(bits),
            ),
        )
    }
}
impl InsnOpcode for USMLALL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm_INDEX4_10 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl USMLALL_SME_ZA_array_off1x4_SME_Znx2_SME_Zm_INDEX4_1 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "usmlall",
        aliases: &[],
        opcode: 0xc1100020,
        mask: 0xfff09038,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off1x4,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm1_0,
                        lsb: 0,
                        width: 1,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn2,
                    lsb: 6,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm_INDEX4_1,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zm,
                        lsb: 16,
                        width: 4,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_10,
                        lsb: 10,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_1,
                        lsb: 1,
                        width: 2,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(
            SME_MISC::USMLALL_SME_ZA_array_off1x4_SME_Znx2_SME_Zm_INDEX4_1(
                USMLALL_SME_ZA_array_off1x4_SME_Znx2_SME_Zm_INDEX4_1::from(bits),
            ),
        )
    }
}
impl InsnOpcode for USMLALL_SME_ZA_array_off1x4_SME_Znx2_SME_Zm_INDEX4_1 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl USMLALL_SME_ZA_array_off1x4_SME_Znx4_SME_Zm_INDEX4_1 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "usmlall",
        aliases: &[],
        opcode: 0xc1108020,
        mask: 0xfff09078,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off1x4,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm1_0,
                        lsb: 0,
                        width: 1,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn4,
                    lsb: 7,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm_INDEX4_1,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zm,
                        lsb: 16,
                        width: 4,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_10,
                        lsb: 10,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_1,
                        lsb: 1,
                        width: 2,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_4.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(
            SME_MISC::USMLALL_SME_ZA_array_off1x4_SME_Znx4_SME_Zm_INDEX4_1(
                USMLALL_SME_ZA_array_off1x4_SME_Znx4_SME_Zm_INDEX4_1::from(bits),
            ),
        )
    }
}
impl InsnOpcode for USMLALL_SME_ZA_array_off1x4_SME_Znx4_SME_Zm_INDEX4_1 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl USMLALL_SME_ZA_array_off1x4_SVE_ZnxN_SME_Zm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "usmlall",
        aliases: &[],
        opcode: 0xc1200004,
        mask: 0xfff09c1e,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off1x4,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm1_0,
                        lsb: 0,
                        width: 1,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ZnxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm,
                    lsb: 16,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::USMLALL_SME_ZA_array_off1x4_SVE_ZnxN_SME_Zm(
            USMLALL_SME_ZA_array_off1x4_SVE_ZnxN_SME_Zm::from(bits),
        ))
    }
}
impl InsnOpcode for USMLALL_SME_ZA_array_off1x4_SVE_ZnxN_SME_Zm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl USMLALL_SME_ZA_array_off1x4_S_S_SVE_ZnxN_S_B_SME_Zm_S_B {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "usmlall",
        aliases: &[],
        opcode: 0xc1300004,
        mask: 0xfff09c1e,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off1x4,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm1_0,
                        lsb: 0,
                        width: 1,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_ZnxN,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm,
                    lsb: 16,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_4.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(
            SME_MISC::USMLALL_SME_ZA_array_off1x4_S_S_SVE_ZnxN_S_B_SME_Zm_S_B(
                USMLALL_SME_ZA_array_off1x4_S_S_SVE_ZnxN_S_B_SME_Zm_S_B::from(bits),
            ),
        )
    }
}
impl InsnOpcode for USMLALL_SME_ZA_array_off1x4_S_S_SVE_ZnxN_S_B_SME_Zm_S_B {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl USMLALL_SME_ZA_array_off1x4_SME_Znx2_SME_Zmx2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "usmlall",
        aliases: &[],
        opcode: 0xc1a00004,
        mask: 0xffe19c3e,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off1x4,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm1_0,
                        lsb: 0,
                        width: 1,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn2,
                    lsb: 6,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zmx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm2,
                    lsb: 17,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::USMLALL_SME_ZA_array_off1x4_SME_Znx2_SME_Zmx2(
            USMLALL_SME_ZA_array_off1x4_SME_Znx2_SME_Zmx2::from(bits),
        ))
    }
}
impl InsnOpcode for USMLALL_SME_ZA_array_off1x4_SME_Znx2_SME_Zmx2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl USMLALL_SME_ZA_array_off1x4_SME_Znx4_SME_Zmx4 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "usmlall",
        aliases: &[],
        opcode: 0xc1a10004,
        mask: 0xffe39c7e,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off1x4,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm1_0,
                        lsb: 0,
                        width: 1,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn4,
                    lsb: 7,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zmx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm4,
                    lsb: 18,
                    width: 3,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_4.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::USMLALL_SME_ZA_array_off1x4_SME_Znx4_SME_Zmx4(
            USMLALL_SME_ZA_array_off1x4_SME_Znx4_SME_Zmx4::from(bits),
        ))
    }
}
impl InsnOpcode for USMLALL_SME_ZA_array_off1x4_SME_Znx4_SME_Zmx4 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl USMLALL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "usmlall",
        aliases: &[],
        opcode: 0xc1200404,
        mask: 0xfff09c1c,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off2x4,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_0,
                        lsb: 0,
                        width: 2,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zm,
                    lsb: 16,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::USMLALL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm(
            USMLALL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm::from(bits),
        ))
    }
}
impl InsnOpcode for USMLALL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl USMMLA_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "usmmla",
        aliases: &[],
        opcode: 0x45809800,
        mask: 0xffe0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::I8MM_SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::USMMLA_SVE_Zd_SVE_Zn_SVE_Zm_16(
            USMMLA_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for USMMLA_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl USMMLA_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "usmmla",
        aliases: &[],
        opcode: 0x4e80ac00,
        mask: 0xffe0fc00,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::I8MM,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(AARCH64_MISC::USMMLA_Vd_Vn_Vm(USMMLA_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for USMMLA_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl USMOPA_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "usmopa",
        aliases: &[],
        opcode: 0xa1800000,
        mask: 0xffe0001c,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZAda_2b,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_ZAda_2b,
                    lsb: 0,
                    width: 2,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Pm,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Pm,
                    lsb: 13,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(
            SME_MISC::USMOPA_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16(
                USMOPA_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16::from(bits),
            ),
        )
    }
}
impl InsnOpcode for USMOPA_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl USMOPA_SME_ZAda_3b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "usmopa",
        aliases: &[],
        opcode: 0xa1c00000,
        mask: 0xffe00018,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME_I16I64,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZAda_3b,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_ZAda_3b,
                    lsb: 0,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Pm,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Pm,
                    lsb: 13,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(
            SME_MISC::USMOPA_SME_ZAda_3b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16(
                USMOPA_SME_ZAda_3b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16::from(bits),
            ),
        )
    }
}
impl InsnOpcode for USMOPA_SME_ZAda_3b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl USMOPS_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "usmops",
        aliases: &[],
        opcode: 0xa1800010,
        mask: 0xffe0001c,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZAda_2b,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_ZAda_2b,
                    lsb: 0,
                    width: 2,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Pm,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Pm,
                    lsb: 13,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(
            SME_MISC::USMOPS_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16(
                USMOPS_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16::from(bits),
            ),
        )
    }
}
impl InsnOpcode for USMOPS_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl USMOPS_SME_ZAda_3b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "usmops",
        aliases: &[],
        opcode: 0xa1c00010,
        mask: 0xffe00018,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME_I16I64,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZAda_3b,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_ZAda_3b,
                    lsb: 0,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Pm,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Pm,
                    lsb: 13,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(
            SME_MISC::USMOPS_SME_ZAda_3b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16(
                USMOPS_SME_ZAda_3b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16::from(bits),
            ),
        )
    }
}
impl InsnOpcode for USMOPS_SME_ZAda_3b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl USQADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "usqadd",
        aliases: &[],
        opcode: 0x441d8000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                    InsnOperandQualifier::P_M,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::USQADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(
            USQADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for USQADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl USQADD_Vd_Vn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "usqadd",
        aliases: &[],
        opcode: 0x2e203800,
        mask: 0xbf3ffc00,
        class: InsnClass::ASIMDMISC,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDMISC(ASIMDMISC::USQADD_Vd_Vn(USQADD_Vd_Vn::from(bits)))
    }
}
impl InsnOpcode for USQADD_Vd_Vn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl USQADD_Sd_Sn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "usqadd",
        aliases: &[],
        opcode: 0x7e203800,
        mask: 0xff3ffc00,
        class: InsnClass::ASISDMISC,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ADVSIMD_SCALAR_SIZE.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDMISC(ASISDMISC::USQADD_Sd_Sn(USQADD_Sd_Sn::from(bits)))
    }
}
impl InsnOpcode for USQADD_Sd_Sn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl USRA_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "usra",
        aliases: &[],
        opcode: 0x4500e400,
        mask: 0xff20fc00,
        class: InsnClass::SVE_SHIFT_TSZ_BHSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_SHRIMM_UNPRED,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_tszh,
                        lsb: 22,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm5,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SHIFT_TSZ_BHSD(SVE_SHIFT_TSZ_BHSD::USRA_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED(
            USRA_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED::from(bits),
        ))
    }
}
impl InsnOpcode for USRA_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl USRA_Vd_Vn_IMM_VLSR {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "usra",
        aliases: &[],
        opcode: 0x2f001400,
        mask: 0xbf80fc00,
        class: InsnClass::ASIMDSHF,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::IMM_VLSR,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDSHF(ASIMDSHF::USRA_Vd_Vn_IMM_VLSR(USRA_Vd_Vn_IMM_VLSR::from(
            bits,
        )))
    }
}
impl InsnOpcode for USRA_Vd_Vn_IMM_VLSR {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl USRA_Sd_Sn_IMM_VLSR {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "usra",
        aliases: &[],
        opcode: 0x7f001400,
        mask: 0xff80fc00,
        class: InsnClass::ASISDSHF,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Sd,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Sn,
                class: InsnOperandClass::SISD_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::IMM_VLSR,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASISDSHF(ASISDSHF::USRA_Sd_Sn_IMM_VLSR(USRA_Sd_Sn_IMM_VLSR::from(
            bits,
        )))
    }
}
impl InsnOpcode for USRA_Sd_Sn_IMM_VLSR {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl USUBL_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "usubl",
        aliases: &[],
        opcode: 0x2e202000,
        mask: 0xff20fc00,
        class: InsnClass::ASIMDDIFF,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8H, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_4H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_4H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDDIFF(ASIMDDIFF::USUBL_Vd_Vn_Vm(USUBL_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for USUBL_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl USUBL2_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "usubl2",
        aliases: &[],
        opcode: 0x6e202000,
        mask: 0xff20fc00,
        class: InsnClass::ASIMDDIFF,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8H, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_16B, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_16B, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDDIFF(ASIMDDIFF::USUBL2_Vd_Vn_Vm(USUBL2_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for USUBL2_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl USUBLB_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "usublb",
        aliases: &[],
        opcode: 0x45001800,
        mask: 0xff20fc00,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::USUBLB_SVE_Zd_SVE_Zn_SVE_Zm_16(
            USUBLB_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for USUBLB_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl USUBLT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "usublt",
        aliases: &[],
        opcode: 0x45001c00,
        mask: 0xff20fc00,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::USUBLT_SVE_Zd_SVE_Zn_SVE_Zm_16(
            USUBLT_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for USUBLT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl USUBW_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "usubw",
        aliases: &[],
        opcode: 0x2e203000,
        mask: 0xff20fc00,
        class: InsnClass::ASIMDDIFF,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8H, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8H, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_4H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDDIFF(ASIMDDIFF::USUBW_Vd_Vn_Vm(USUBW_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for USUBW_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl USUBW2_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "usubw2",
        aliases: &[],
        opcode: 0x6e203000,
        mask: 0xff20fc00,
        class: InsnClass::ASIMDDIFF,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8H, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8H, InsnOperandQualifier::V_4S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_16B, InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDDIFF(ASIMDDIFF::USUBW2_Vd_Vn_Vm(USUBW2_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for USUBW2_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl USUBWB_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "usubwb",
        aliases: &[],
        opcode: 0x45005800,
        mask: 0xff20fc00,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::USUBWB_SVE_Zd_SVE_Zn_SVE_Zm_16(
            USUBWB_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for USUBWB_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl USUBWT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "usubwt",
        aliases: &[],
        opcode: 0x45005c00,
        mask: 0xff20fc00,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::USUBWT_SVE_Zd_SVE_Zn_SVE_Zm_16(
            USUBWT_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for USUBWT_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl USVDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "usvdot",
        aliases: &[],
        opcode: 0xc1508028,
        mask: 0xfff09078,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off3_0,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_0,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn4,
                    lsb: 7,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm_INDEX2,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zm,
                        lsb: 16,
                        width: 4,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_10,
                        lsb: 10,
                        width: 2,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_4.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::USVDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2(
            USVDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2::from(bits),
        ))
    }
}
impl InsnOpcode for USVDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UUNPK_SME_Zdnx2_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uunpk",
        aliases: &[],
        opcode: 0xc125e001,
        mask: 0xff3ffc01,
        class: InsnClass::SME_SIZE_22_HSD,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn2,
                    lsb: 1,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_SIZE_22_HSD(SME_SIZE_22_HSD::UUNPK_SME_Zdnx2_SVE_Zn(
            UUNPK_SME_Zdnx2_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for UUNPK_SME_Zdnx2_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UUNPK_SME_Zdnx4_SME_Znx2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uunpk",
        aliases: &[],
        opcode: 0xc135e001,
        mask: 0xff3ffc23,
        class: InsnClass::SME_SIZE_22_HSD,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn4,
                    lsb: 2,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn2,
                    lsb: 6,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_SIZE_22_HSD(SME_SIZE_22_HSD::UUNPK_SME_Zdnx4_SME_Znx2(
            UUNPK_SME_Zdnx4_SME_Znx2::from(bits),
        ))
    }
}
impl InsnOpcode for UUNPK_SME_Zdnx4_SME_Znx2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UUNPKHI_SVE_Zd_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uunpkhi",
        aliases: &[],
        opcode: 0x5333800,
        mask: 0xff3ffc00,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::UUNPKHI_SVE_Zd_SVE_Zn(
            UUNPKHI_SVE_Zd_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for UUNPKHI_SVE_Zd_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UUNPKLO_SVE_Zd_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uunpklo",
        aliases: &[],
        opcode: 0x5323800,
        mask: 0xff3ffc00,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::UUNPKLO_SVE_Zd_SVE_Zn(
            UUNPKLO_SVE_Zd_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for UUNPKLO_SVE_Zd_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UVDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uvdot",
        aliases: &[],
        opcode: 0xc1500030,
        mask: 0xfff09038,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off3_0,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_0,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn2,
                    lsb: 6,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm_INDEX2,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zm,
                        lsb: 16,
                        width: 4,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_10,
                        lsb: 10,
                        width: 2,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_2.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_3.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::UVDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2(
            UVDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2::from(bits),
        ))
    }
}
impl InsnOpcode for UVDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UVDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uvdot",
        aliases: &[],
        opcode: 0xc1508030,
        mask: 0xfff09078,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off3_0,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_S],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_0,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn4,
                    lsb: 7,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm_INDEX2,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zm,
                        lsb: 16,
                        width: 4,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm2_10,
                        lsb: 10,
                        width: 2,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_4.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::UVDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2(
            UVDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2::from(bits),
        ))
    }
}
impl InsnOpcode for UVDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UVDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX1 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uvdot",
        aliases: &[],
        opcode: 0xc1d08818,
        mask: 0xfff09878,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2_I16I64,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_ZA_array_off3_0,
                class: InsnOperandClass::ZA_ACCESS,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Rv,
                        lsb: 13,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm3_0,
                        lsb: 0,
                        width: 3,
                    },
                ],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn4,
                    lsb: 7,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Zm_INDEX1,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SME_Zm,
                        lsb: 16,
                        width: 4,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm1_10,
                        lsb: 10,
                        width: 1,
                    },
                ],
            },
        ],
        flags: InsnFlags::const_from_bits(
            InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_4.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_5.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_6.bits()
                | InsnFlags::HAS_OPCODE_DEPENDENT_FIELD_7.bits(),
        ),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::UVDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX1(
            UVDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX1::from(bits),
        ))
    }
}
impl InsnOpcode for UVDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX1 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UXTB_SVE_Zd_SVE_Pg3_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uxtb",
        aliases: &[],
        opcode: 0x411a000,
        mask: 0xff3fe000,
        class: InsnClass::SVE_SIZE_HSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M, InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_H, InsnOperandQualifier::S_S],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_HSD(SVE_SIZE_HSD::UXTB_SVE_Zd_SVE_Pg3_SVE_Zn(
            UXTB_SVE_Zd_SVE_Pg3_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for UXTB_SVE_Zd_SVE_Pg3_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UXTH_SVE_Zd_SVE_Pg3_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uxth",
        aliases: &[],
        opcode: 0x493a000,
        mask: 0xffbfe000,
        class: InsnClass::SVE_SIZE_SD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M, InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_S, InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_SD(SVE_SIZE_SD::UXTH_SVE_Zd_SVE_Pg3_SVE_Zn(
            UXTH_SVE_Zd_SVE_Pg3_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for UXTH_SVE_Zd_SVE_Pg3_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UXTW_SVE_Zd_SVE_Pg3_SVE_Zn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uxtw",
        aliases: &[],
        opcode: 0x4d5a000,
        mask: 0xffffe000,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pg3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::P_M],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pg3,
                    lsb: 10,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::UXTW_SVE_Zd_SVE_Pg3_SVE_Zn(
            UXTW_SVE_Zd_SVE_Pg3_SVE_Zn::from(bits),
        ))
    }
}
impl InsnOpcode for UXTW_SVE_Zd_SVE_Pg3_SVE_Zn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UZP_SME_Zdnx2_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uzp",
        aliases: &[],
        opcode: 0xc120d001,
        mask: 0xff20fc01,
        class: InsnClass::SME_SIZE_22,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn2,
                    lsb: 1,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_SIZE_22(SME_SIZE_22::UZP_SME_Zdnx2_SVE_Zn_SVE_Zm_16(
            UZP_SME_Zdnx2_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for UZP_SME_Zdnx2_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UZP_SME_Zdnx2_S_Q_SVE_Zn_S_Q_SVE_Zm_16_S_Q {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uzp",
        aliases: &[],
        opcode: 0xc120d401,
        mask: 0xffe0fc01,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_Q],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn2,
                    lsb: 1,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_Q],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_Q],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::UZP_SME_Zdnx2_S_Q_SVE_Zn_S_Q_SVE_Zm_16_S_Q(
            UZP_SME_Zdnx2_S_Q_SVE_Zn_S_Q_SVE_Zm_16_S_Q::from(bits),
        ))
    }
}
impl InsnOpcode for UZP_SME_Zdnx2_S_Q_SVE_Zn_S_Q_SVE_Zm_16_S_Q {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UZP_SME_Zdnx4_SME_Znx4 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uzp",
        aliases: &[],
        opcode: 0xc136e002,
        mask: 0xff3ffc63,
        class: InsnClass::SME_SIZE_22,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn4,
                    lsb: 2,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn4,
                    lsb: 7,
                    width: 3,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_SIZE_22(SME_SIZE_22::UZP_SME_Zdnx4_SME_Znx4(
            UZP_SME_Zdnx4_SME_Znx4::from(bits),
        ))
    }
}
impl InsnOpcode for UZP_SME_Zdnx4_SME_Znx4 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UZP_SME_Zdnx4_S_Q_SME_Znx4_S_Q {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uzp",
        aliases: &[],
        opcode: 0xc137e002,
        mask: 0xfffffc63,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_Q],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn4,
                    lsb: 2,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_Q],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn4,
                    lsb: 7,
                    width: 3,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::UZP_SME_Zdnx4_S_Q_SME_Znx4_S_Q(
            UZP_SME_Zdnx4_S_Q_SME_Znx4_S_Q::from(bits),
        ))
    }
}
impl InsnOpcode for UZP_SME_Zdnx4_S_Q_SME_Znx4_S_Q {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UZP1_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uzp1",
        aliases: &[],
        opcode: 0x5a00800,
        mask: 0xffe0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::F64MM_SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_Q],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_Q],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_Q],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::UZP1_SVE_Zd_SVE_Zn_SVE_Zm_16(
            UZP1_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for UZP1_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UZP1_SVE_Pd_SVE_Pn_SVE_Pm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uzp1",
        aliases: &[],
        opcode: 0x5204800,
        mask: 0xff30fe10,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Pd,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pd,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pn,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pn,
                    lsb: 5,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pm,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pm,
                    lsb: 16,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::UZP1_SVE_Pd_SVE_Pn_SVE_Pm(
            UZP1_SVE_Pd_SVE_Pn_SVE_Pm::from(bits),
        ))
    }
}
impl InsnOpcode for UZP1_SVE_Pd_SVE_Pn_SVE_Pm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UZP1_SVE_Zd_S_B_SVE_Zn_S_B_SVE_Zm_16_S_B {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uzp1",
        aliases: &[],
        opcode: 0x5206800,
        mask: 0xff20fc00,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::UZP1_SVE_Zd_S_B_SVE_Zn_S_B_SVE_Zm_16_S_B(
            UZP1_SVE_Zd_S_B_SVE_Zn_S_B_SVE_Zm_16_S_B::from(bits),
        ))
    }
}
impl InsnOpcode for UZP1_SVE_Zd_S_B_SVE_Zn_S_B_SVE_Zm_16_S_B {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UZP1_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uzp1",
        aliases: &[],
        opcode: 0xe001800,
        mask: 0xbf20fc00,
        class: InsnClass::ASIMDPERM,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDPERM(ASIMDPERM::UZP1_Vd_Vn_Vm(UZP1_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for UZP1_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UZP2_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uzp2",
        aliases: &[],
        opcode: 0x5a00c00,
        mask: 0xffe0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::F64MM_SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_Q],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_Q],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_Q],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::UZP2_SVE_Zd_SVE_Zn_SVE_Zm_16(
            UZP2_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for UZP2_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UZP2_SVE_Pd_SVE_Pn_SVE_Pm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uzp2",
        aliases: &[],
        opcode: 0x5204c00,
        mask: 0xff30fe10,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Pd,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pd,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pn,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pn,
                    lsb: 5,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pm,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pm,
                    lsb: 16,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::UZP2_SVE_Pd_SVE_Pn_SVE_Pm(
            UZP2_SVE_Pd_SVE_Pn_SVE_Pm::from(bits),
        ))
    }
}
impl InsnOpcode for UZP2_SVE_Pd_SVE_Pn_SVE_Pm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UZP2_SVE_Zd_S_B_SVE_Zn_S_B_SVE_Zm_16_S_B {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uzp2",
        aliases: &[],
        opcode: 0x5206c00,
        mask: 0xff20fc00,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::UZP2_SVE_Zd_S_B_SVE_Zn_S_B_SVE_Zm_16_S_B(
            UZP2_SVE_Zd_S_B_SVE_Zn_S_B_SVE_Zm_16_S_B::from(bits),
        ))
    }
}
impl InsnOpcode for UZP2_SVE_Zd_S_B_SVE_Zn_S_B_SVE_Zm_16_S_B {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl UZP2_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "uzp2",
        aliases: &[],
        opcode: 0xe005800,
        mask: 0xbf20fc00,
        class: InsnClass::ASIMDPERM,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDPERM(ASIMDPERM::UZP2_Vd_Vn_Vm(UZP2_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for UZP2_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl WFET_Rd {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "wfet",
        aliases: &[],
        opcode: 0xd5031000,
        mask: 0xffffffe0,
        class: InsnClass::IC_SYSTEM,
        feature_set: InsnFeatureSet::WFXT,
        operands: &[InsnOperand {
            kind: InsnOperandKind::Rd,
            class: InsnOperandClass::INT_REG,
            qualifiers: &[],
            bit_fields: &[BitfieldSpec {
                bitfield: InsnBitField::Rd,
                lsb: 0,
                width: 5,
            }],
        }],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ALIAS.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::IC_SYSTEM(IC_SYSTEM::WFET_Rd(WFET_Rd::from(bits)))
    }
}
impl InsnOpcode for WFET_Rd {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl WFIT_Rd {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "wfit",
        aliases: &[],
        opcode: 0xd5031020,
        mask: 0xffffffe0,
        class: InsnClass::IC_SYSTEM,
        feature_set: InsnFeatureSet::WFXT,
        operands: &[InsnOperand {
            kind: InsnOperandKind::Rd,
            class: InsnOperandClass::INT_REG,
            qualifiers: &[],
            bit_fields: &[BitfieldSpec {
                bitfield: InsnBitField::Rd,
                lsb: 0,
                width: 5,
            }],
        }],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_ALIAS.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::IC_SYSTEM(IC_SYSTEM::WFIT_Rd(WFIT_Rd::from(bits)))
    }
}
impl InsnOpcode for WFIT_Rd {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl WHILEGE_SVE_Pd_Rn_Rm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "whilege",
        aliases: &[],
        opcode: 0x25200000,
        mask: 0xff20fc10,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Pd,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pd,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rm,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::WHILEGE_SVE_Pd_Rn_Rm(
            WHILEGE_SVE_Pd_Rn_Rm::from(bits),
        ))
    }
}
impl InsnOpcode for WHILEGE_SVE_Pd_Rn_Rm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl WHILEGE_SVE_Pd_S_B_Rn_X_Rm_X {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "whilege",
        aliases: &[],
        opcode: 0x25201000,
        mask: 0xff20fc10,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Pd,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pd,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rm,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::WHILEGE_SVE_Pd_S_B_Rn_X_Rm_X(
            WHILEGE_SVE_Pd_S_B_Rn_X_Rm_X::from(bits),
        ))
    }
}
impl InsnOpcode for WHILEGE_SVE_Pd_S_B_Rn_X_Rm_X {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl WHILEGE_SME_PNd3_Rn_Rm_SME_VLxN_13 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "whilege",
        aliases: &[],
        opcode: 0x25204010,
        mask: 0xff20dc18,
        class: InsnClass::SME_SIZE_22,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_PNd3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_PNd3,
                    lsb: 0,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[
                    InsnOperandQualifier::X,
                    InsnOperandQualifier::X,
                    InsnOperandQualifier::X,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rm,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[
                    InsnOperandQualifier::X,
                    InsnOperandQualifier::X,
                    InsnOperandQualifier::X,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_VLxN_13,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_VL_13,
                    lsb: 13,
                    width: 1,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_SIZE_22(SME_SIZE_22::WHILEGE_SME_PNd3_Rn_Rm_SME_VLxN_13(
            WHILEGE_SME_PNd3_Rn_Rm_SME_VLxN_13::from(bits),
        ))
    }
}
impl InsnOpcode for WHILEGE_SME_PNd3_Rn_Rm_SME_VLxN_13 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl WHILEGE_SME_Pdx2_Rn_Rm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "whilege",
        aliases: &[],
        opcode: 0x25205010,
        mask: 0xff20fc11,
        class: InsnClass::SME_SIZE_22,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Pdx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Pdx2,
                    lsb: 1,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rm,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_SIZE_22(SME_SIZE_22::WHILEGE_SME_Pdx2_Rn_Rm(
            WHILEGE_SME_Pdx2_Rn_Rm::from(bits),
        ))
    }
}
impl InsnOpcode for WHILEGE_SME_Pdx2_Rn_Rm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl WHILEGT_SVE_Pd_Rn_Rm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "whilegt",
        aliases: &[],
        opcode: 0x25200010,
        mask: 0xff20fc10,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Pd,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pd,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rm,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::WHILEGT_SVE_Pd_Rn_Rm(
            WHILEGT_SVE_Pd_Rn_Rm::from(bits),
        ))
    }
}
impl InsnOpcode for WHILEGT_SVE_Pd_Rn_Rm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl WHILEGT_SVE_Pd_S_B_Rn_X_Rm_X {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "whilegt",
        aliases: &[],
        opcode: 0x25201010,
        mask: 0xff20fc10,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Pd,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pd,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rm,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::WHILEGT_SVE_Pd_S_B_Rn_X_Rm_X(
            WHILEGT_SVE_Pd_S_B_Rn_X_Rm_X::from(bits),
        ))
    }
}
impl InsnOpcode for WHILEGT_SVE_Pd_S_B_Rn_X_Rm_X {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl WHILEGT_SME_PNd3_Rn_Rm_SME_VLxN_13 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "whilegt",
        aliases: &[],
        opcode: 0x25204018,
        mask: 0xff20dc18,
        class: InsnClass::SME_SIZE_22,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_PNd3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_PNd3,
                    lsb: 0,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[
                    InsnOperandQualifier::X,
                    InsnOperandQualifier::X,
                    InsnOperandQualifier::X,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rm,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[
                    InsnOperandQualifier::X,
                    InsnOperandQualifier::X,
                    InsnOperandQualifier::X,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_VLxN_13,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_VL_13,
                    lsb: 13,
                    width: 1,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_SIZE_22(SME_SIZE_22::WHILEGT_SME_PNd3_Rn_Rm_SME_VLxN_13(
            WHILEGT_SME_PNd3_Rn_Rm_SME_VLxN_13::from(bits),
        ))
    }
}
impl InsnOpcode for WHILEGT_SME_PNd3_Rn_Rm_SME_VLxN_13 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl WHILEGT_SME_Pdx2_Rn_Rm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "whilegt",
        aliases: &[],
        opcode: 0x25205011,
        mask: 0xff20fc11,
        class: InsnClass::SME_SIZE_22,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Pdx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Pdx2,
                    lsb: 1,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rm,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_SIZE_22(SME_SIZE_22::WHILEGT_SME_Pdx2_Rn_Rm(
            WHILEGT_SME_Pdx2_Rn_Rm::from(bits),
        ))
    }
}
impl InsnOpcode for WHILEGT_SME_Pdx2_Rn_Rm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl WHILEHI_SVE_Pd_Rn_Rm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "whilehi",
        aliases: &[],
        opcode: 0x25200810,
        mask: 0xff20fc10,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Pd,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pd,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rm,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::WHILEHI_SVE_Pd_Rn_Rm(
            WHILEHI_SVE_Pd_Rn_Rm::from(bits),
        ))
    }
}
impl InsnOpcode for WHILEHI_SVE_Pd_Rn_Rm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl WHILEHI_SVE_Pd_S_B_Rn_X_Rm_X {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "whilehi",
        aliases: &[],
        opcode: 0x25201810,
        mask: 0xff20fc10,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Pd,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pd,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rm,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::WHILEHI_SVE_Pd_S_B_Rn_X_Rm_X(
            WHILEHI_SVE_Pd_S_B_Rn_X_Rm_X::from(bits),
        ))
    }
}
impl InsnOpcode for WHILEHI_SVE_Pd_S_B_Rn_X_Rm_X {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl WHILEHI_SME_PNd3_Rn_Rm_SME_VLxN_13 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "whilehi",
        aliases: &[],
        opcode: 0x25204818,
        mask: 0xff20dc18,
        class: InsnClass::SME_SIZE_22,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_PNd3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_PNd3,
                    lsb: 0,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[
                    InsnOperandQualifier::X,
                    InsnOperandQualifier::X,
                    InsnOperandQualifier::X,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rm,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[
                    InsnOperandQualifier::X,
                    InsnOperandQualifier::X,
                    InsnOperandQualifier::X,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_VLxN_13,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_VL_13,
                    lsb: 13,
                    width: 1,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_SIZE_22(SME_SIZE_22::WHILEHI_SME_PNd3_Rn_Rm_SME_VLxN_13(
            WHILEHI_SME_PNd3_Rn_Rm_SME_VLxN_13::from(bits),
        ))
    }
}
impl InsnOpcode for WHILEHI_SME_PNd3_Rn_Rm_SME_VLxN_13 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl WHILEHI_SME_Pdx2_Rn_Rm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "whilehi",
        aliases: &[],
        opcode: 0x25205811,
        mask: 0xff20fc11,
        class: InsnClass::SME_SIZE_22,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Pdx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Pdx2,
                    lsb: 1,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rm,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_SIZE_22(SME_SIZE_22::WHILEHI_SME_Pdx2_Rn_Rm(
            WHILEHI_SME_Pdx2_Rn_Rm::from(bits),
        ))
    }
}
impl InsnOpcode for WHILEHI_SME_Pdx2_Rn_Rm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl WHILEHS_SVE_Pd_Rn_Rm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "whilehs",
        aliases: &[],
        opcode: 0x25200800,
        mask: 0xff20fc10,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Pd,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pd,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rm,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::WHILEHS_SVE_Pd_Rn_Rm(
            WHILEHS_SVE_Pd_Rn_Rm::from(bits),
        ))
    }
}
impl InsnOpcode for WHILEHS_SVE_Pd_Rn_Rm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl WHILEHS_SVE_Pd_S_B_Rn_X_Rm_X {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "whilehs",
        aliases: &[],
        opcode: 0x25201800,
        mask: 0xff20fc10,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Pd,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pd,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rm,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::WHILEHS_SVE_Pd_S_B_Rn_X_Rm_X(
            WHILEHS_SVE_Pd_S_B_Rn_X_Rm_X::from(bits),
        ))
    }
}
impl InsnOpcode for WHILEHS_SVE_Pd_S_B_Rn_X_Rm_X {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl WHILEHS_SME_PNd3_Rn_Rm_SME_VLxN_13 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "whilehs",
        aliases: &[],
        opcode: 0x25204810,
        mask: 0xff20dc18,
        class: InsnClass::SME_SIZE_22,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_PNd3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_PNd3,
                    lsb: 0,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[
                    InsnOperandQualifier::X,
                    InsnOperandQualifier::X,
                    InsnOperandQualifier::X,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rm,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[
                    InsnOperandQualifier::X,
                    InsnOperandQualifier::X,
                    InsnOperandQualifier::X,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_VLxN_13,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_VL_13,
                    lsb: 13,
                    width: 1,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_SIZE_22(SME_SIZE_22::WHILEHS_SME_PNd3_Rn_Rm_SME_VLxN_13(
            WHILEHS_SME_PNd3_Rn_Rm_SME_VLxN_13::from(bits),
        ))
    }
}
impl InsnOpcode for WHILEHS_SME_PNd3_Rn_Rm_SME_VLxN_13 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl WHILEHS_SME_Pdx2_Rn_Rm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "whilehs",
        aliases: &[],
        opcode: 0x25205810,
        mask: 0xff20fc11,
        class: InsnClass::SME_SIZE_22,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Pdx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Pdx2,
                    lsb: 1,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rm,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_SIZE_22(SME_SIZE_22::WHILEHS_SME_Pdx2_Rn_Rm(
            WHILEHS_SME_Pdx2_Rn_Rm::from(bits),
        ))
    }
}
impl InsnOpcode for WHILEHS_SME_Pdx2_Rn_Rm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl WHILELE_SVE_Pd_Rn_Rm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "whilele",
        aliases: &[],
        opcode: 0x25200410,
        mask: 0xff20fc10,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Pd,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pd,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rm,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::WHILELE_SVE_Pd_Rn_Rm(
            WHILELE_SVE_Pd_Rn_Rm::from(bits),
        ))
    }
}
impl InsnOpcode for WHILELE_SVE_Pd_Rn_Rm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl WHILELE_SVE_Pd_S_B_Rn_X_Rm_X {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "whilele",
        aliases: &[],
        opcode: 0x25201410,
        mask: 0xff20fc10,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Pd,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pd,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rm,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::WHILELE_SVE_Pd_S_B_Rn_X_Rm_X(
            WHILELE_SVE_Pd_S_B_Rn_X_Rm_X::from(bits),
        ))
    }
}
impl InsnOpcode for WHILELE_SVE_Pd_S_B_Rn_X_Rm_X {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl WHILELE_SME_PNd3_Rn_Rm_SME_VLxN_13 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "whilele",
        aliases: &[],
        opcode: 0x25204418,
        mask: 0xff20dc18,
        class: InsnClass::SME_SIZE_22,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_PNd3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_PNd3,
                    lsb: 0,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[
                    InsnOperandQualifier::X,
                    InsnOperandQualifier::X,
                    InsnOperandQualifier::X,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rm,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[
                    InsnOperandQualifier::X,
                    InsnOperandQualifier::X,
                    InsnOperandQualifier::X,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_VLxN_13,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_VL_13,
                    lsb: 13,
                    width: 1,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_SIZE_22(SME_SIZE_22::WHILELE_SME_PNd3_Rn_Rm_SME_VLxN_13(
            WHILELE_SME_PNd3_Rn_Rm_SME_VLxN_13::from(bits),
        ))
    }
}
impl InsnOpcode for WHILELE_SME_PNd3_Rn_Rm_SME_VLxN_13 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl WHILELE_SME_Pdx2_Rn_Rm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "whilele",
        aliases: &[],
        opcode: 0x25205411,
        mask: 0xff20fc11,
        class: InsnClass::SME_SIZE_22,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Pdx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Pdx2,
                    lsb: 1,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rm,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_SIZE_22(SME_SIZE_22::WHILELE_SME_Pdx2_Rn_Rm(
            WHILELE_SME_Pdx2_Rn_Rm::from(bits),
        ))
    }
}
impl InsnOpcode for WHILELE_SME_Pdx2_Rn_Rm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl WHILELO_SVE_Pd_Rn_Rm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "whilelo",
        aliases: &[],
        opcode: 0x25200c00,
        mask: 0xff20fc10,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Pd,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pd,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rm,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::WHILELO_SVE_Pd_Rn_Rm(
            WHILELO_SVE_Pd_Rn_Rm::from(bits),
        ))
    }
}
impl InsnOpcode for WHILELO_SVE_Pd_Rn_Rm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl WHILELO_SVE_Pd_S_B_Rn_X_Rm_X {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "whilelo",
        aliases: &[],
        opcode: 0x25201c00,
        mask: 0xff20fc10,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Pd,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pd,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rm,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::WHILELO_SVE_Pd_S_B_Rn_X_Rm_X(
            WHILELO_SVE_Pd_S_B_Rn_X_Rm_X::from(bits),
        ))
    }
}
impl InsnOpcode for WHILELO_SVE_Pd_S_B_Rn_X_Rm_X {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl WHILELO_SME_PNd3_Rn_Rm_SME_VLxN_13 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "whilelo",
        aliases: &[],
        opcode: 0x25204c10,
        mask: 0xff20dc18,
        class: InsnClass::SME_SIZE_22,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_PNd3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_PNd3,
                    lsb: 0,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[
                    InsnOperandQualifier::X,
                    InsnOperandQualifier::X,
                    InsnOperandQualifier::X,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rm,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[
                    InsnOperandQualifier::X,
                    InsnOperandQualifier::X,
                    InsnOperandQualifier::X,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_VLxN_13,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_VL_13,
                    lsb: 13,
                    width: 1,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_SIZE_22(SME_SIZE_22::WHILELO_SME_PNd3_Rn_Rm_SME_VLxN_13(
            WHILELO_SME_PNd3_Rn_Rm_SME_VLxN_13::from(bits),
        ))
    }
}
impl InsnOpcode for WHILELO_SME_PNd3_Rn_Rm_SME_VLxN_13 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl WHILELO_SME_Pdx2_Rn_Rm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "whilelo",
        aliases: &[],
        opcode: 0x25205c10,
        mask: 0xff20fc11,
        class: InsnClass::SME_SIZE_22,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Pdx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Pdx2,
                    lsb: 1,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rm,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_SIZE_22(SME_SIZE_22::WHILELO_SME_Pdx2_Rn_Rm(
            WHILELO_SME_Pdx2_Rn_Rm::from(bits),
        ))
    }
}
impl InsnOpcode for WHILELO_SME_Pdx2_Rn_Rm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl WHILELS_SVE_Pd_Rn_Rm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "whilels",
        aliases: &[],
        opcode: 0x25200c10,
        mask: 0xff20fc10,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Pd,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pd,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rm,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::WHILELS_SVE_Pd_Rn_Rm(
            WHILELS_SVE_Pd_Rn_Rm::from(bits),
        ))
    }
}
impl InsnOpcode for WHILELS_SVE_Pd_Rn_Rm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl WHILELS_SVE_Pd_S_B_Rn_X_Rm_X {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "whilels",
        aliases: &[],
        opcode: 0x25201c10,
        mask: 0xff20fc10,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Pd,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pd,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rm,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::WHILELS_SVE_Pd_S_B_Rn_X_Rm_X(
            WHILELS_SVE_Pd_S_B_Rn_X_Rm_X::from(bits),
        ))
    }
}
impl InsnOpcode for WHILELS_SVE_Pd_S_B_Rn_X_Rm_X {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl WHILELS_SME_PNd3_Rn_Rm_SME_VLxN_13 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "whilels",
        aliases: &[],
        opcode: 0x25204c18,
        mask: 0xff20dc18,
        class: InsnClass::SME_SIZE_22,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_PNd3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_PNd3,
                    lsb: 0,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[
                    InsnOperandQualifier::X,
                    InsnOperandQualifier::X,
                    InsnOperandQualifier::X,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rm,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[
                    InsnOperandQualifier::X,
                    InsnOperandQualifier::X,
                    InsnOperandQualifier::X,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_VLxN_13,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_VL_13,
                    lsb: 13,
                    width: 1,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_SIZE_22(SME_SIZE_22::WHILELS_SME_PNd3_Rn_Rm_SME_VLxN_13(
            WHILELS_SME_PNd3_Rn_Rm_SME_VLxN_13::from(bits),
        ))
    }
}
impl InsnOpcode for WHILELS_SME_PNd3_Rn_Rm_SME_VLxN_13 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl WHILELS_SME_Pdx2_Rn_Rm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "whilels",
        aliases: &[],
        opcode: 0x25205c11,
        mask: 0xff20fc11,
        class: InsnClass::SME_SIZE_22,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Pdx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Pdx2,
                    lsb: 1,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rm,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_SIZE_22(SME_SIZE_22::WHILELS_SME_Pdx2_Rn_Rm(
            WHILELS_SME_Pdx2_Rn_Rm::from(bits),
        ))
    }
}
impl InsnOpcode for WHILELS_SME_Pdx2_Rn_Rm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl WHILELT_SVE_Pd_Rn_Rm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "whilelt",
        aliases: &[],
        opcode: 0x25200400,
        mask: 0xff20fc10,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Pd,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pd,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rm,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::W, InsnOperandQualifier::W],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::WHILELT_SVE_Pd_Rn_Rm(
            WHILELT_SVE_Pd_Rn_Rm::from(bits),
        ))
    }
}
impl InsnOpcode for WHILELT_SVE_Pd_Rn_Rm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl WHILELT_SVE_Pd_S_B_Rn_X_Rm_X {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "whilelt",
        aliases: &[],
        opcode: 0x25201400,
        mask: 0xff20fc10,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Pd,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pd,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rm,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::WHILELT_SVE_Pd_S_B_Rn_X_Rm_X(
            WHILELT_SVE_Pd_S_B_Rn_X_Rm_X::from(bits),
        ))
    }
}
impl InsnOpcode for WHILELT_SVE_Pd_S_B_Rn_X_Rm_X {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl WHILELT_SME_PNd3_Rn_Rm_SME_VLxN_13 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "whilelt",
        aliases: &[],
        opcode: 0x25204410,
        mask: 0xff20dc18,
        class: InsnClass::SME_SIZE_22,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_PNd3,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_PNd3,
                    lsb: 0,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[
                    InsnOperandQualifier::X,
                    InsnOperandQualifier::X,
                    InsnOperandQualifier::X,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rm,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[
                    InsnOperandQualifier::X,
                    InsnOperandQualifier::X,
                    InsnOperandQualifier::X,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_VLxN_13,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_VL_13,
                    lsb: 13,
                    width: 1,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_SIZE_22(SME_SIZE_22::WHILELT_SME_PNd3_Rn_Rm_SME_VLxN_13(
            WHILELT_SME_PNd3_Rn_Rm_SME_VLxN_13::from(bits),
        ))
    }
}
impl InsnOpcode for WHILELT_SME_PNd3_Rn_Rm_SME_VLxN_13 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl WHILELT_SME_Pdx2_Rn_Rm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "whilelt",
        aliases: &[],
        opcode: 0x25205410,
        mask: 0xff20fc11,
        class: InsnClass::SME_SIZE_22,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Pdx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Pdx2,
                    lsb: 1,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rm,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_SIZE_22(SME_SIZE_22::WHILELT_SME_Pdx2_Rn_Rm(
            WHILELT_SME_Pdx2_Rn_Rm::from(bits),
        ))
    }
}
impl InsnOpcode for WHILELT_SME_Pdx2_Rn_Rm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl WHILERW_SVE_Pd_Rn_Rm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "whilerw",
        aliases: &[],
        opcode: 0x25203010,
        mask: 0xff20fc10,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Pd,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pd,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rm,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::WHILERW_SVE_Pd_Rn_Rm(
            WHILERW_SVE_Pd_Rn_Rm::from(bits),
        ))
    }
}
impl InsnOpcode for WHILERW_SVE_Pd_Rn_Rm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl WHILEWR_SVE_Pd_Rn_Rm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "whilewr",
        aliases: &[],
        opcode: 0x25203000,
        mask: 0xff20fc10,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Pd,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pd,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rn,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Rm,
                class: InsnOperandClass::INT_REG,
                qualifiers: &[InsnOperandQualifier::X, InsnOperandQualifier::X],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::WHILEWR_SVE_Pd_Rn_Rm(
            WHILEWR_SVE_Pd_Rn_Rm::from(bits),
        ))
    }
}
impl InsnOpcode for WHILEWR_SVE_Pd_Rn_Rm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl WRFFR_SVE_Pn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "wrffr",
        aliases: &[],
        opcode: 0x25289000,
        mask: 0xfffffe1f,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::SVE,
        operands: &[InsnOperand {
            kind: InsnOperandKind::SVE_Pn,
            class: InsnOperandClass::PRED_REG,
            qualifiers: &[],
            bit_fields: &[BitfieldSpec {
                bitfield: InsnBitField::SVE_Pn,
                lsb: 5,
                width: 4,
            }],
        }],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::WRFFR_SVE_Pn(WRFFR_SVE_Pn::from(bits)))
    }
}
impl InsnOpcode for WRFFR_SVE_Pn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl XAFLAG {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "xaflag",
        aliases: &[],
        opcode: 0xd500403f,
        mask: 0xffffffff,
        class: InsnClass::AARCH64_MISC,
        feature_set: InsnFeatureSet::FLAGMANIP,
        operands: &[],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::AARCH64_MISC(AARCH64_MISC::XAFLAG(XAFLAG::from(bits)))
    }
}
impl InsnOpcode for XAFLAG {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl XAR_SVE_Zd_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "xar",
        aliases: &[],
        opcode: 0x4203400,
        mask: 0xff20fc00,
        class: InsnClass::SVE_SHIFT_TSZ_BHSD,
        feature_set: InsnFeatureSet::SVE2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[
                    InsnOperandQualifier::S_B,
                    InsnOperandQualifier::S_H,
                    InsnOperandQualifier::S_S,
                ],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_SHRIMM_UNPRED,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[],
                bit_fields: &[
                    BitfieldSpec {
                        bitfield: InsnBitField::SVE_tszh,
                        lsb: 22,
                        width: 2,
                    },
                    BitfieldSpec {
                        bitfield: InsnBitField::imm5,
                        lsb: 16,
                        width: 5,
                    },
                ],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SHIFT_TSZ_BHSD(
            SVE_SHIFT_TSZ_BHSD::XAR_SVE_Zd_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED(
                XAR_SVE_Zd_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED::from(bits),
            ),
        )
    }
}
impl InsnOpcode for XAR_SVE_Zd_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl XAR_Vd_Vn_Vm_IMM {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "xar",
        aliases: &[],
        opcode: 0xce800000,
        mask: 0xffe00000,
        class: InsnClass::CRYPTOSHA3,
        feature_set: InsnFeatureSet::SHA3,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_2D],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::IMM,
                class: InsnOperandClass::IMMEDIATE,
                qualifiers: &[InsnOperandQualifier::imm_0_63],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::imm6_10,
                    lsb: 10,
                    width: 6,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::CRYPTOSHA3(CRYPTOSHA3::XAR_Vd_Vn_Vm_IMM(XAR_Vd_Vn_Vm_IMM::from(bits)))
    }
}
impl InsnOpcode for XAR_Vd_Vn_Vm_IMM {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl XPACD_Rd {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "xpacd",
        aliases: &[],
        opcode: 0xdac147e0,
        mask: 0xffffffe0,
        class: InsnClass::DP_1SRC,
        feature_set: InsnFeatureSet::PAC,
        operands: &[InsnOperand {
            kind: InsnOperandKind::Rd,
            class: InsnOperandClass::INT_REG,
            qualifiers: &[],
            bit_fields: &[BitfieldSpec {
                bitfield: InsnBitField::Rd,
                lsb: 0,
                width: 5,
            }],
        }],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::DP_1SRC(DP_1SRC::XPACD_Rd(XPACD_Rd::from(bits)))
    }
}
impl InsnOpcode for XPACD_Rd {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl XPACI_Rd {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "xpaci",
        aliases: &[],
        opcode: 0xdac143e0,
        mask: 0xffffffe0,
        class: InsnClass::DP_1SRC,
        feature_set: InsnFeatureSet::PAC,
        operands: &[InsnOperand {
            kind: InsnOperandKind::Rd,
            class: InsnOperandClass::INT_REG,
            qualifiers: &[],
            bit_fields: &[BitfieldSpec {
                bitfield: InsnBitField::Rd,
                lsb: 0,
                width: 5,
            }],
        }],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::DP_1SRC(DP_1SRC::XPACI_Rd(XPACI_Rd::from(bits)))
    }
}
impl InsnOpcode for XPACI_Rd {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl XTN_Vd_Vn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "xtn",
        aliases: &[],
        opcode: 0xe212800,
        mask: 0xff3ffc00,
        class: InsnClass::ASIMDMISC,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDMISC(ASIMDMISC::XTN_Vd_Vn(XTN_Vd_Vn::from(bits)))
    }
}
impl InsnOpcode for XTN_Vd_Vn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl XTN2_Vd_Vn {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "xtn2",
        aliases: &[],
        opcode: 0x4e212800,
        mask: 0xff3ffc00,
        class: InsnClass::ASIMDMISC,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDMISC(ASIMDMISC::XTN2_Vd_Vn(XTN2_Vd_Vn::from(bits)))
    }
}
impl InsnOpcode for XTN2_Vd_Vn {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ZERO_SME_list_of_64bit_tiles {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "zero",
        aliases: &[],
        opcode: 0xc0080000,
        mask: 0xffffff00,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME,
        operands: &[InsnOperand {
            kind: InsnOperandKind::SME_list_of_64bit_tiles,
            class: InsnOperandClass::SVE_REG,
            qualifiers: &[],
            bit_fields: &[BitfieldSpec {
                bitfield: InsnBitField::SME_zero_mask,
                lsb: 0,
                width: 8,
            }],
        }],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::ZERO_SME_list_of_64bit_tiles(
            ZERO_SME_list_of_64bit_tiles::from(bits),
        ))
    }
}
impl InsnOpcode for ZERO_SME_list_of_64bit_tiles {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ZERO_SME_ZT0_LIST {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "zero",
        aliases: &[],
        opcode: 0xc0480001,
        mask: 0xffffffff,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[InsnOperand {
            kind: InsnOperandKind::SME_ZT0_LIST,
            class: InsnOperandClass::SYSTEM,
            qualifiers: &[],
            bit_fields: &[],
        }],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::ZERO_SME_ZT0_LIST(ZERO_SME_ZT0_LIST::from(bits)))
    }
}
impl InsnOpcode for ZERO_SME_ZT0_LIST {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ZIP_SME_Zdnx2_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "zip",
        aliases: &[],
        opcode: 0xc120d000,
        mask: 0xff20fc01,
        class: InsnClass::SME_SIZE_22,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn2,
                    lsb: 1,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_SIZE_22(SME_SIZE_22::ZIP_SME_Zdnx2_SVE_Zn_SVE_Zm_16(
            ZIP_SME_Zdnx2_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for ZIP_SME_Zdnx2_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ZIP_SME_Zdnx2_S_Q_SVE_Zn_S_Q_SVE_Zm_16_S_Q {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "zip",
        aliases: &[],
        opcode: 0xc120d400,
        mask: 0xffe0fc01,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx2,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_Q],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn2,
                    lsb: 1,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_Q],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_Q],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::ZIP_SME_Zdnx2_S_Q_SVE_Zn_S_Q_SVE_Zm_16_S_Q(
            ZIP_SME_Zdnx2_S_Q_SVE_Zn_S_Q_SVE_Zm_16_S_Q::from(bits),
        ))
    }
}
impl InsnOpcode for ZIP_SME_Zdnx2_S_Q_SVE_Zn_S_Q_SVE_Zm_16_S_Q {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ZIP_SME_Zdnx4_SME_Znx4 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "zip",
        aliases: &[],
        opcode: 0xc136e000,
        mask: 0xff3ffc63,
        class: InsnClass::SME_SIZE_22,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn4,
                    lsb: 2,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn4,
                    lsb: 7,
                    width: 3,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_SIZE_22(SME_SIZE_22::ZIP_SME_Zdnx4_SME_Znx4(
            ZIP_SME_Zdnx4_SME_Znx4::from(bits),
        ))
    }
}
impl InsnOpcode for ZIP_SME_Zdnx4_SME_Znx4 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ZIP_SME_Zdnx4_S_Q_SME_Znx4_S_Q {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "zip",
        aliases: &[],
        opcode: 0xc137e000,
        mask: 0xfffffc63,
        class: InsnClass::SME_MISC,
        feature_set: InsnFeatureSet::SME2,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SME_Zdnx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_Q],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zdn4,
                    lsb: 2,
                    width: 3,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SME_Znx4,
                class: InsnOperandClass::SVE_REGLIST,
                qualifiers: &[InsnOperandQualifier::S_Q],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SME_Zn4,
                    lsb: 7,
                    width: 3,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SME_MISC(SME_MISC::ZIP_SME_Zdnx4_S_Q_SME_Znx4_S_Q(
            ZIP_SME_Zdnx4_S_Q_SME_Znx4_S_Q::from(bits),
        ))
    }
}
impl InsnOpcode for ZIP_SME_Zdnx4_S_Q_SME_Znx4_S_Q {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ZIP1_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "zip1",
        aliases: &[],
        opcode: 0x5a00000,
        mask: 0xffe0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::F64MM_SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_Q],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_Q],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_Q],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::ZIP1_SVE_Zd_SVE_Zn_SVE_Zm_16(
            ZIP1_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for ZIP1_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ZIP1_SVE_Pd_SVE_Pn_SVE_Pm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "zip1",
        aliases: &[],
        opcode: 0x5204000,
        mask: 0xff30fe10,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Pd,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pd,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pn,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pn,
                    lsb: 5,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pm,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pm,
                    lsb: 16,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::ZIP1_SVE_Pd_SVE_Pn_SVE_Pm(
            ZIP1_SVE_Pd_SVE_Pn_SVE_Pm::from(bits),
        ))
    }
}
impl InsnOpcode for ZIP1_SVE_Pd_SVE_Pn_SVE_Pm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ZIP1_SVE_Zd_S_B_SVE_Zn_S_B_SVE_Zm_16_S_B {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "zip1",
        aliases: &[],
        opcode: 0x5206000,
        mask: 0xff20fc00,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::ZIP1_SVE_Zd_S_B_SVE_Zn_S_B_SVE_Zm_16_S_B(
            ZIP1_SVE_Zd_S_B_SVE_Zn_S_B_SVE_Zm_16_S_B::from(bits),
        ))
    }
}
impl InsnOpcode for ZIP1_SVE_Zd_S_B_SVE_Zn_S_B_SVE_Zm_16_S_B {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ZIP1_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "zip1",
        aliases: &[],
        opcode: 0xe003800,
        mask: 0xbf20fc00,
        class: InsnClass::ASIMDPERM,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDPERM(ASIMDPERM::ZIP1_Vd_Vn_Vm(ZIP1_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for ZIP1_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ZIP2_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "zip2",
        aliases: &[],
        opcode: 0x5a00400,
        mask: 0xffe0fc00,
        class: InsnClass::SVE_MISC,
        feature_set: InsnFeatureSet::F64MM_SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_Q],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_Q],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_Q],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_MISC(SVE_MISC::ZIP2_SVE_Zd_SVE_Zn_SVE_Zm_16(
            ZIP2_SVE_Zd_SVE_Zn_SVE_Zm_16::from(bits),
        ))
    }
}
impl InsnOpcode for ZIP2_SVE_Zd_SVE_Zn_SVE_Zm_16 {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ZIP2_SVE_Pd_SVE_Pn_SVE_Pm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "zip2",
        aliases: &[],
        opcode: 0x5204400,
        mask: 0xff30fe10,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Pd,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pd,
                    lsb: 0,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pn,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pn,
                    lsb: 5,
                    width: 4,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Pm,
                class: InsnOperandClass::PRED_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Pm,
                    lsb: 16,
                    width: 4,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::ZIP2_SVE_Pd_SVE_Pn_SVE_Pm(
            ZIP2_SVE_Pd_SVE_Pn_SVE_Pm::from(bits),
        ))
    }
}
impl InsnOpcode for ZIP2_SVE_Pd_SVE_Pn_SVE_Pm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ZIP2_SVE_Zd_S_B_SVE_Zn_S_B_SVE_Zm_16_S_B {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "zip2",
        aliases: &[],
        opcode: 0x5206400,
        mask: 0xff20fc00,
        class: InsnClass::SVE_SIZE_BHSD,
        feature_set: InsnFeatureSet::SVE,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::SVE_Zd,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zn,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::SVE_Zm_16,
                class: InsnOperandClass::SVE_REG,
                qualifiers: &[InsnOperandQualifier::S_B, InsnOperandQualifier::S_H],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::SVE_Zm_16,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::empty(),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::SVE_SIZE_BHSD(SVE_SIZE_BHSD::ZIP2_SVE_Zd_S_B_SVE_Zn_S_B_SVE_Zm_16_S_B(
            ZIP2_SVE_Zd_S_B_SVE_Zn_S_B_SVE_Zm_16_S_B::from(bits),
        ))
    }
}
impl InsnOpcode for ZIP2_SVE_Zd_S_B_SVE_Zn_S_B_SVE_Zm_16_S_B {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl ZIP2_Vd_Vn_Vm {
    pub const DEFINITION: Insn = Insn {
        mnemonic: "zip2",
        aliases: &[],
        opcode: 0xe007800,
        mask: 0xbf20fc00,
        class: InsnClass::ASIMDPERM,
        feature_set: InsnFeatureSet::SIMD,
        operands: &[
            InsnOperand {
                kind: InsnOperandKind::Vd,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rd,
                    lsb: 0,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vn,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rn,
                    lsb: 5,
                    width: 5,
                }],
            },
            InsnOperand {
                kind: InsnOperandKind::Vm,
                class: InsnOperandClass::SIMD_REG,
                qualifiers: &[InsnOperandQualifier::V_8B, InsnOperandQualifier::V_16B],
                bit_fields: &[BitfieldSpec {
                    bitfield: InsnBitField::Rm,
                    lsb: 16,
                    width: 5,
                }],
            },
        ],
        flags: InsnFlags::const_from_bits(InsnFlags::HAS_SIZEQ_FIELD.bits()),
    };
    fn make_opcode(bits: u32) -> Opcode {
        Opcode::ASIMDPERM(ASIMDPERM::ZIP2_Vd_Vn_Vm(ZIP2_Vd_Vn_Vm::from(bits)))
    }
}
impl InsnOpcode for ZIP2_Vd_Vn_Vm {
    fn definition(&self) -> &'static Insn {
        &Self::DEFINITION
    }
    fn bits(&self) -> u32 {
        (*self).into()
    }
}
impl InsnOpcode for SME_SIZE_22_HSD {
    fn definition(&self) -> &'static Insn {
        match self {
            SME_SIZE_22_HSD::FCLAMP_SME_Zdnx2_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SME_SIZE_22_HSD::FCLAMP_SME_Zdnx4_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SME_SIZE_22_HSD::FCLAMP_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SME_SIZE_22_HSD::FMAXNM_SME_Zdnx2_SME_Zdnx2_SME_Zm(opcode) => opcode.definition(),
            SME_SIZE_22_HSD::FMAXNM_SME_Zdnx2_SME_Zdnx2_SME_Zmx2(opcode) => opcode.definition(),
            SME_SIZE_22_HSD::FMAXNM_SME_Zdnx4_SME_Zdnx4_SME_Zm(opcode) => opcode.definition(),
            SME_SIZE_22_HSD::FMAXNM_SME_Zdnx4_SME_Zdnx4_SME_Zmx4(opcode) => opcode.definition(),
            SME_SIZE_22_HSD::FMAX_SME_Zdnx2_SME_Zdnx2_SME_Zm(opcode) => opcode.definition(),
            SME_SIZE_22_HSD::FMAX_SME_Zdnx2_SME_Zdnx2_SME_Zmx2(opcode) => opcode.definition(),
            SME_SIZE_22_HSD::FMAX_SME_Zdnx4_SME_Zdnx4_SME_Zm(opcode) => opcode.definition(),
            SME_SIZE_22_HSD::FMAX_SME_Zdnx4_SME_Zdnx4_SME_Zmx4(opcode) => opcode.definition(),
            SME_SIZE_22_HSD::FMINNM_SME_Zdnx2_SME_Zdnx2_SME_Zm(opcode) => opcode.definition(),
            SME_SIZE_22_HSD::FMINNM_SME_Zdnx2_SME_Zdnx2_SME_Zmx2(opcode) => opcode.definition(),
            SME_SIZE_22_HSD::FMINNM_SME_Zdnx4_SME_Zdnx4_SME_Zm(opcode) => opcode.definition(),
            SME_SIZE_22_HSD::FMINNM_SME_Zdnx4_SME_Zdnx4_SME_Zmx4(opcode) => opcode.definition(),
            SME_SIZE_22_HSD::FMIN_SME_Zdnx2_SME_Zdnx2_SME_Zm(opcode) => opcode.definition(),
            SME_SIZE_22_HSD::FMIN_SME_Zdnx2_SME_Zdnx2_SME_Zmx2(opcode) => opcode.definition(),
            SME_SIZE_22_HSD::FMIN_SME_Zdnx4_SME_Zdnx4_SME_Zm(opcode) => opcode.definition(),
            SME_SIZE_22_HSD::FMIN_SME_Zdnx4_SME_Zdnx4_SME_Zmx4(opcode) => opcode.definition(),
            SME_SIZE_22_HSD::SUNPK_SME_Zdnx2_SVE_Zn(opcode) => opcode.definition(),
            SME_SIZE_22_HSD::SUNPK_SME_Zdnx4_SME_Znx2(opcode) => opcode.definition(),
            SME_SIZE_22_HSD::UUNPK_SME_Zdnx2_SVE_Zn(opcode) => opcode.definition(),
            SME_SIZE_22_HSD::UUNPK_SME_Zdnx4_SME_Znx2(opcode) => opcode.definition(),
        }
    }
    fn bits(&self) -> u32 {
        match self {
            SME_SIZE_22_HSD::FCLAMP_SME_Zdnx2_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SME_SIZE_22_HSD::FCLAMP_SME_Zdnx4_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SME_SIZE_22_HSD::FCLAMP_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SME_SIZE_22_HSD::FMAXNM_SME_Zdnx2_SME_Zdnx2_SME_Zm(opcode) => opcode.bits(),
            SME_SIZE_22_HSD::FMAXNM_SME_Zdnx2_SME_Zdnx2_SME_Zmx2(opcode) => opcode.bits(),
            SME_SIZE_22_HSD::FMAXNM_SME_Zdnx4_SME_Zdnx4_SME_Zm(opcode) => opcode.bits(),
            SME_SIZE_22_HSD::FMAXNM_SME_Zdnx4_SME_Zdnx4_SME_Zmx4(opcode) => opcode.bits(),
            SME_SIZE_22_HSD::FMAX_SME_Zdnx2_SME_Zdnx2_SME_Zm(opcode) => opcode.bits(),
            SME_SIZE_22_HSD::FMAX_SME_Zdnx2_SME_Zdnx2_SME_Zmx2(opcode) => opcode.bits(),
            SME_SIZE_22_HSD::FMAX_SME_Zdnx4_SME_Zdnx4_SME_Zm(opcode) => opcode.bits(),
            SME_SIZE_22_HSD::FMAX_SME_Zdnx4_SME_Zdnx4_SME_Zmx4(opcode) => opcode.bits(),
            SME_SIZE_22_HSD::FMINNM_SME_Zdnx2_SME_Zdnx2_SME_Zm(opcode) => opcode.bits(),
            SME_SIZE_22_HSD::FMINNM_SME_Zdnx2_SME_Zdnx2_SME_Zmx2(opcode) => opcode.bits(),
            SME_SIZE_22_HSD::FMINNM_SME_Zdnx4_SME_Zdnx4_SME_Zm(opcode) => opcode.bits(),
            SME_SIZE_22_HSD::FMINNM_SME_Zdnx4_SME_Zdnx4_SME_Zmx4(opcode) => opcode.bits(),
            SME_SIZE_22_HSD::FMIN_SME_Zdnx2_SME_Zdnx2_SME_Zm(opcode) => opcode.bits(),
            SME_SIZE_22_HSD::FMIN_SME_Zdnx2_SME_Zdnx2_SME_Zmx2(opcode) => opcode.bits(),
            SME_SIZE_22_HSD::FMIN_SME_Zdnx4_SME_Zdnx4_SME_Zm(opcode) => opcode.bits(),
            SME_SIZE_22_HSD::FMIN_SME_Zdnx4_SME_Zdnx4_SME_Zmx4(opcode) => opcode.bits(),
            SME_SIZE_22_HSD::SUNPK_SME_Zdnx2_SVE_Zn(opcode) => opcode.bits(),
            SME_SIZE_22_HSD::SUNPK_SME_Zdnx4_SME_Znx2(opcode) => opcode.bits(),
            SME_SIZE_22_HSD::UUNPK_SME_Zdnx2_SVE_Zn(opcode) => opcode.bits(),
            SME_SIZE_22_HSD::UUNPK_SME_Zdnx4_SME_Znx2(opcode) => opcode.bits(),
        }
    }
}
impl InsnOpcode for DP_3SRC {
    fn definition(&self) -> &'static Insn {
        match self {
            DP_3SRC::MADD_Rd_Rn_Rm_Ra(opcode) => opcode.definition(),
            DP_3SRC::MSUB_Rd_Rn_Rm_Ra(opcode) => opcode.definition(),
            DP_3SRC::SMADDL_Rd_Rn_Rm_Ra(opcode) => opcode.definition(),
            DP_3SRC::SMSUBL_Rd_Rn_Rm_Ra(opcode) => opcode.definition(),
            DP_3SRC::SMULH_Rd_Rn_Rm(opcode) => opcode.definition(),
            DP_3SRC::UMADDL_Rd_Rn_Rm_Ra(opcode) => opcode.definition(),
            DP_3SRC::UMSUBL_Rd_Rn_Rm_Ra(opcode) => opcode.definition(),
            DP_3SRC::UMULH_Rd_Rn_Rm(opcode) => opcode.definition(),
        }
    }
    fn bits(&self) -> u32 {
        match self {
            DP_3SRC::MADD_Rd_Rn_Rm_Ra(opcode) => opcode.bits(),
            DP_3SRC::MSUB_Rd_Rn_Rm_Ra(opcode) => opcode.bits(),
            DP_3SRC::SMADDL_Rd_Rn_Rm_Ra(opcode) => opcode.bits(),
            DP_3SRC::SMSUBL_Rd_Rn_Rm_Ra(opcode) => opcode.bits(),
            DP_3SRC::SMULH_Rd_Rn_Rm(opcode) => opcode.bits(),
            DP_3SRC::UMADDL_Rd_Rn_Rm_Ra(opcode) => opcode.bits(),
            DP_3SRC::UMSUBL_Rd_Rn_Rm_Ra(opcode) => opcode.bits(),
            DP_3SRC::UMULH_Rd_Rn_Rm(opcode) => opcode.bits(),
        }
    }
}
impl InsnOpcode for SME_START {
    fn definition(&self) -> &'static Insn {
        match self {
            SME_START::SMSTART(opcode) => opcode.definition(),
            SME_START::SMSTART_SME_SM_ZA(opcode) => opcode.definition(),
        }
    }
    fn bits(&self) -> u32 {
        match self {
            SME_START::SMSTART(opcode) => opcode.bits(),
            SME_START::SMSTART_SME_SM_ZA(opcode) => opcode.bits(),
        }
    }
}
impl InsnOpcode for ASIMDIMM {
    fn definition(&self) -> &'static Insn {
        match self {
            ASIMDIMM::BIC_Vd_SIMD_IMM_SFT(opcode) => opcode.definition(),
            ASIMDIMM::BIC_Vd_V_4H_SIMD_IMM_SFT_LSL(opcode) => opcode.definition(),
            ASIMDIMM::FMOV_Vd_SIMD_FPIMM(opcode) => opcode.definition(),
            ASIMDIMM::FMOV_Vd_V_2D_SIMD_FPIMM(opcode) => opcode.definition(),
            ASIMDIMM::FMOV_Vd_V_4H_SIMD_FPIMM(opcode) => opcode.definition(),
            ASIMDIMM::MOVI_Sd_SIMD_IMM(opcode) => opcode.definition(),
            ASIMDIMM::MOVI_Vd_SIMD_IMM(opcode) => opcode.definition(),
            ASIMDIMM::MOVI_Vd_SIMD_IMM_SFT(opcode) => opcode.definition(),
            ASIMDIMM::MOVI_Vd_V_2S_SIMD_IMM_SFT_MSL(opcode) => opcode.definition(),
            ASIMDIMM::MOVI_Vd_V_4H_SIMD_IMM_SFT_LSL(opcode) => opcode.definition(),
            ASIMDIMM::MOVI_Vd_V_8B_SIMD_IMM_SFT_LSL(opcode) => opcode.definition(),
            ASIMDIMM::MVNI_Vd_SIMD_IMM_SFT(opcode) => opcode.definition(),
            ASIMDIMM::MVNI_Vd_V_2S_SIMD_IMM_SFT_MSL(opcode) => opcode.definition(),
            ASIMDIMM::MVNI_Vd_V_4H_SIMD_IMM_SFT_LSL(opcode) => opcode.definition(),
            ASIMDIMM::ORR_Vd_SIMD_IMM_SFT(opcode) => opcode.definition(),
            ASIMDIMM::ORR_Vd_V_4H_SIMD_IMM_SFT_LSL(opcode) => opcode.definition(),
        }
    }
    fn bits(&self) -> u32 {
        match self {
            ASIMDIMM::BIC_Vd_SIMD_IMM_SFT(opcode) => opcode.bits(),
            ASIMDIMM::BIC_Vd_V_4H_SIMD_IMM_SFT_LSL(opcode) => opcode.bits(),
            ASIMDIMM::FMOV_Vd_SIMD_FPIMM(opcode) => opcode.bits(),
            ASIMDIMM::FMOV_Vd_V_2D_SIMD_FPIMM(opcode) => opcode.bits(),
            ASIMDIMM::FMOV_Vd_V_4H_SIMD_FPIMM(opcode) => opcode.bits(),
            ASIMDIMM::MOVI_Sd_SIMD_IMM(opcode) => opcode.bits(),
            ASIMDIMM::MOVI_Vd_SIMD_IMM(opcode) => opcode.bits(),
            ASIMDIMM::MOVI_Vd_SIMD_IMM_SFT(opcode) => opcode.bits(),
            ASIMDIMM::MOVI_Vd_V_2S_SIMD_IMM_SFT_MSL(opcode) => opcode.bits(),
            ASIMDIMM::MOVI_Vd_V_4H_SIMD_IMM_SFT_LSL(opcode) => opcode.bits(),
            ASIMDIMM::MOVI_Vd_V_8B_SIMD_IMM_SFT_LSL(opcode) => opcode.bits(),
            ASIMDIMM::MVNI_Vd_SIMD_IMM_SFT(opcode) => opcode.bits(),
            ASIMDIMM::MVNI_Vd_V_2S_SIMD_IMM_SFT_MSL(opcode) => opcode.bits(),
            ASIMDIMM::MVNI_Vd_V_4H_SIMD_IMM_SFT_LSL(opcode) => opcode.bits(),
            ASIMDIMM::ORR_Vd_SIMD_IMM_SFT(opcode) => opcode.bits(),
            ASIMDIMM::ORR_Vd_V_4H_SIMD_IMM_SFT_LSL(opcode) => opcode.bits(),
        }
    }
}
impl InsnOpcode for ASIMDTBL {
    fn definition(&self) -> &'static Insn {
        match self {
            ASIMDTBL::TBL_Vd_LVn_Vm(opcode) => opcode.definition(),
            ASIMDTBL::TBX_Vd_LVn_Vm(opcode) => opcode.definition(),
        }
    }
    fn bits(&self) -> u32 {
        match self {
            ASIMDTBL::TBL_Vd_LVn_Vm(opcode) => opcode.bits(),
            ASIMDTBL::TBX_Vd_LVn_Vm(opcode) => opcode.bits(),
        }
    }
}
impl InsnOpcode for SVE_LIMM {
    fn definition(&self) -> &'static Insn {
        match self {
            SVE_LIMM::AND_SVE_Zd_SVE_Zd_SVE_LIMM(opcode) => opcode.definition(),
            SVE_LIMM::DUPM_SVE_Zd_SVE_LIMM(opcode) => opcode.definition(),
            SVE_LIMM::EOR_SVE_Zd_SVE_Zd_SVE_LIMM(opcode) => opcode.definition(),
            SVE_LIMM::ORR_SVE_Zd_SVE_Zd_SVE_LIMM(opcode) => opcode.definition(),
        }
    }
    fn bits(&self) -> u32 {
        match self {
            SVE_LIMM::AND_SVE_Zd_SVE_Zd_SVE_LIMM(opcode) => opcode.bits(),
            SVE_LIMM::DUPM_SVE_Zd_SVE_LIMM(opcode) => opcode.bits(),
            SVE_LIMM::EOR_SVE_Zd_SVE_Zd_SVE_LIMM(opcode) => opcode.bits(),
            SVE_LIMM::ORR_SVE_Zd_SVE_Zd_SVE_LIMM(opcode) => opcode.bits(),
        }
    }
}
impl InsnOpcode for LDST_POS {
    fn definition(&self) -> &'static Insn {
        match self {
            LDST_POS::LDRB_Rt_ADDR_UIMM12(opcode) => opcode.definition(),
            LDST_POS::LDRH_Rt_ADDR_UIMM12(opcode) => opcode.definition(),
            LDST_POS::LDRSB_Rt_ADDR_UIMM12(opcode) => opcode.definition(),
            LDST_POS::LDRSH_Rt_ADDR_UIMM12(opcode) => opcode.definition(),
            LDST_POS::LDRSW_Rt_ADDR_UIMM12(opcode) => opcode.definition(),
            LDST_POS::LDR_Ft_ADDR_UIMM12(opcode) => opcode.definition(),
            LDST_POS::LDR_Rt_ADDR_UIMM12(opcode) => opcode.definition(),
            LDST_POS::PRFM_PRFOP_ADDR_UIMM12(opcode) => opcode.definition(),
            LDST_POS::STRB_Rt_ADDR_UIMM12(opcode) => opcode.definition(),
            LDST_POS::STRH_Rt_ADDR_UIMM12(opcode) => opcode.definition(),
            LDST_POS::STR_Ft_ADDR_UIMM12(opcode) => opcode.definition(),
            LDST_POS::STR_Rt_ADDR_UIMM12(opcode) => opcode.definition(),
        }
    }
    fn bits(&self) -> u32 {
        match self {
            LDST_POS::LDRB_Rt_ADDR_UIMM12(opcode) => opcode.bits(),
            LDST_POS::LDRH_Rt_ADDR_UIMM12(opcode) => opcode.bits(),
            LDST_POS::LDRSB_Rt_ADDR_UIMM12(opcode) => opcode.bits(),
            LDST_POS::LDRSH_Rt_ADDR_UIMM12(opcode) => opcode.bits(),
            LDST_POS::LDRSW_Rt_ADDR_UIMM12(opcode) => opcode.bits(),
            LDST_POS::LDR_Ft_ADDR_UIMM12(opcode) => opcode.bits(),
            LDST_POS::LDR_Rt_ADDR_UIMM12(opcode) => opcode.bits(),
            LDST_POS::PRFM_PRFOP_ADDR_UIMM12(opcode) => opcode.bits(),
            LDST_POS::STRB_Rt_ADDR_UIMM12(opcode) => opcode.bits(),
            LDST_POS::STRH_Rt_ADDR_UIMM12(opcode) => opcode.bits(),
            LDST_POS::STR_Ft_ADDR_UIMM12(opcode) => opcode.bits(),
            LDST_POS::STR_Rt_ADDR_UIMM12(opcode) => opcode.bits(),
        }
    }
}
impl InsnOpcode for ADDSUB_SHIFT {
    fn definition(&self) -> &'static Insn {
        match self {
            ADDSUB_SHIFT::ADDS_Rd_Rn_Rm_SFT(opcode) => opcode.definition(),
            ADDSUB_SHIFT::ADD_Rd_Rn_Rm_SFT(opcode) => opcode.definition(),
            ADDSUB_SHIFT::SUBS_Rd_Rn_Rm_SFT(opcode) => opcode.definition(),
            ADDSUB_SHIFT::SUB_Rd_Rn_Rm_SFT(opcode) => opcode.definition(),
        }
    }
    fn bits(&self) -> u32 {
        match self {
            ADDSUB_SHIFT::ADDS_Rd_Rn_Rm_SFT(opcode) => opcode.bits(),
            ADDSUB_SHIFT::ADD_Rd_Rn_Rm_SFT(opcode) => opcode.bits(),
            ADDSUB_SHIFT::SUBS_Rd_Rn_Rm_SFT(opcode) => opcode.bits(),
            ADDSUB_SHIFT::SUB_Rd_Rn_Rm_SFT(opcode) => opcode.bits(),
        }
    }
}
impl InsnOpcode for ASIMDSAME {
    fn definition(&self) -> &'static Insn {
        match self {
            ASIMDSAME::ADDP_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDSAME::ADD_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDSAME::AND_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDSAME::BIC_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDSAME::BIF_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDSAME::BIT_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDSAME::BSL_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDSAME::CMEQ_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDSAME::CMGE_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDSAME::CMGT_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDSAME::CMHI_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDSAME::CMHS_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDSAME::CMTST_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDSAME::EOR_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDSAME::FABD_Vd_V_2S_Vn_V_2S_Vm_V_2S(opcode) => opcode.definition(),
            ASIMDSAME::FABD_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDSAME::FACGE_Vd_V_2S_Vn_V_2S_Vm_V_2S(opcode) => opcode.definition(),
            ASIMDSAME::FACGE_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDSAME::FACGT_Vd_V_2S_Vn_V_2S_Vm_V_2S(opcode) => opcode.definition(),
            ASIMDSAME::FACGT_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDSAME::FADDP_Vd_V_2S_Vn_V_2S_Vm_V_2S(opcode) => opcode.definition(),
            ASIMDSAME::FADDP_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDSAME::FADD_Vd_V_2S_Vn_V_2S_Vm_V_2S(opcode) => opcode.definition(),
            ASIMDSAME::FADD_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDSAME::FCADD_Vd_Vn_Vm_IMM_ROT3(opcode) => opcode.definition(),
            ASIMDSAME::FCMEQ_Vd_V_2S_Vn_V_2S_Vm_V_2S(opcode) => opcode.definition(),
            ASIMDSAME::FCMEQ_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDSAME::FCMGE_Vd_V_2S_Vn_V_2S_Vm_V_2S(opcode) => opcode.definition(),
            ASIMDSAME::FCMGE_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDSAME::FCMGT_Vd_V_2S_Vn_V_2S_Vm_V_2S(opcode) => opcode.definition(),
            ASIMDSAME::FCMGT_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDSAME::FCMLA_Vd_Vn_Vm_IMM_ROT1(opcode) => opcode.definition(),
            ASIMDSAME::FDIV_Vd_V_2S_Vn_V_2S_Vm_V_2S(opcode) => opcode.definition(),
            ASIMDSAME::FDIV_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDSAME::FMAXNMP_Vd_V_2S_Vn_V_2S_Vm_V_2S(opcode) => opcode.definition(),
            ASIMDSAME::FMAXNMP_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDSAME::FMAXNM_Vd_V_2S_Vn_V_2S_Vm_V_2S(opcode) => opcode.definition(),
            ASIMDSAME::FMAXNM_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDSAME::FMAXP_Vd_V_2S_Vn_V_2S_Vm_V_2S(opcode) => opcode.definition(),
            ASIMDSAME::FMAXP_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDSAME::FMAX_Vd_V_2S_Vn_V_2S_Vm_V_2S(opcode) => opcode.definition(),
            ASIMDSAME::FMAX_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDSAME::FMINNMP_Vd_V_2S_Vn_V_2S_Vm_V_2S(opcode) => opcode.definition(),
            ASIMDSAME::FMINNMP_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDSAME::FMINNM_Vd_V_2S_Vn_V_2S_Vm_V_2S(opcode) => opcode.definition(),
            ASIMDSAME::FMINNM_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDSAME::FMINP_Vd_V_2S_Vn_V_2S_Vm_V_2S(opcode) => opcode.definition(),
            ASIMDSAME::FMINP_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDSAME::FMIN_Vd_V_2S_Vn_V_2S_Vm_V_2S(opcode) => opcode.definition(),
            ASIMDSAME::FMIN_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDSAME::FMLAL2_Vd_V_4S_Vn_V_4H_Vm_V_4H(opcode) => opcode.definition(),
            ASIMDSAME::FMLAL2_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDSAME::FMLAL_Vd_V_4S_Vn_V_4H_Vm_V_4H(opcode) => opcode.definition(),
            ASIMDSAME::FMLAL_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDSAME::FMLA_Vd_V_2S_Vn_V_2S_Vm_V_2S(opcode) => opcode.definition(),
            ASIMDSAME::FMLA_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDSAME::FMLSL2_Vd_V_4S_Vn_V_4H_Vm_V_4H(opcode) => opcode.definition(),
            ASIMDSAME::FMLSL2_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDSAME::FMLSL_Vd_V_4S_Vn_V_4H_Vm_V_4H(opcode) => opcode.definition(),
            ASIMDSAME::FMLSL_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDSAME::FMLS_Vd_V_2S_Vn_V_2S_Vm_V_2S(opcode) => opcode.definition(),
            ASIMDSAME::FMLS_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDSAME::FMULX_Vd_V_2S_Vn_V_2S_Vm_V_2S(opcode) => opcode.definition(),
            ASIMDSAME::FMULX_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDSAME::FMUL_Vd_V_2S_Vn_V_2S_Vm_V_2S(opcode) => opcode.definition(),
            ASIMDSAME::FMUL_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDSAME::FRECPS_Vd_V_2S_Vn_V_2S_Vm_V_2S(opcode) => opcode.definition(),
            ASIMDSAME::FRECPS_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDSAME::FRSQRTS_Vd_V_2S_Vn_V_2S_Vm_V_2S(opcode) => opcode.definition(),
            ASIMDSAME::FRSQRTS_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDSAME::FSUB_Vd_V_2S_Vn_V_2S_Vm_V_2S(opcode) => opcode.definition(),
            ASIMDSAME::FSUB_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDSAME::MLA_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDSAME::MLS_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDSAME::MUL_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDSAME::ORN_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDSAME::ORR_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDSAME::PMUL_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDSAME::SABA_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDSAME::SABD_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDSAME::SHADD_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDSAME::SHSUB_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDSAME::SMAXP_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDSAME::SMAX_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDSAME::SMINP_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDSAME::SMIN_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDSAME::SQADD_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDSAME::SQDMULH_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDSAME::SQRDMLAH_Sd_Sn_Sm(opcode) => opcode.definition(),
            ASIMDSAME::SQRDMLAH_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDSAME::SQRDMLSH_Sd_Sn_Sm(opcode) => opcode.definition(),
            ASIMDSAME::SQRDMLSH_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDSAME::SQRDMULH_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDSAME::SQRSHL_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDSAME::SQSHL_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDSAME::SQSUB_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDSAME::SRHADD_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDSAME::SRSHL_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDSAME::SSHL_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDSAME::SUB_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDSAME::UABA_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDSAME::UABD_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDSAME::UHADD_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDSAME::UHSUB_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDSAME::UMAXP_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDSAME::UMAX_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDSAME::UMINP_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDSAME::UMIN_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDSAME::UQADD_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDSAME::UQRSHL_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDSAME::UQSHL_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDSAME::UQSUB_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDSAME::URHADD_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDSAME::URSHL_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDSAME::USHL_Vd_Vn_Vm(opcode) => opcode.definition(),
        }
    }
    fn bits(&self) -> u32 {
        match self {
            ASIMDSAME::ADDP_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDSAME::ADD_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDSAME::AND_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDSAME::BIC_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDSAME::BIF_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDSAME::BIT_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDSAME::BSL_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDSAME::CMEQ_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDSAME::CMGE_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDSAME::CMGT_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDSAME::CMHI_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDSAME::CMHS_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDSAME::CMTST_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDSAME::EOR_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDSAME::FABD_Vd_V_2S_Vn_V_2S_Vm_V_2S(opcode) => opcode.bits(),
            ASIMDSAME::FABD_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDSAME::FACGE_Vd_V_2S_Vn_V_2S_Vm_V_2S(opcode) => opcode.bits(),
            ASIMDSAME::FACGE_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDSAME::FACGT_Vd_V_2S_Vn_V_2S_Vm_V_2S(opcode) => opcode.bits(),
            ASIMDSAME::FACGT_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDSAME::FADDP_Vd_V_2S_Vn_V_2S_Vm_V_2S(opcode) => opcode.bits(),
            ASIMDSAME::FADDP_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDSAME::FADD_Vd_V_2S_Vn_V_2S_Vm_V_2S(opcode) => opcode.bits(),
            ASIMDSAME::FADD_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDSAME::FCADD_Vd_Vn_Vm_IMM_ROT3(opcode) => opcode.bits(),
            ASIMDSAME::FCMEQ_Vd_V_2S_Vn_V_2S_Vm_V_2S(opcode) => opcode.bits(),
            ASIMDSAME::FCMEQ_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDSAME::FCMGE_Vd_V_2S_Vn_V_2S_Vm_V_2S(opcode) => opcode.bits(),
            ASIMDSAME::FCMGE_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDSAME::FCMGT_Vd_V_2S_Vn_V_2S_Vm_V_2S(opcode) => opcode.bits(),
            ASIMDSAME::FCMGT_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDSAME::FCMLA_Vd_Vn_Vm_IMM_ROT1(opcode) => opcode.bits(),
            ASIMDSAME::FDIV_Vd_V_2S_Vn_V_2S_Vm_V_2S(opcode) => opcode.bits(),
            ASIMDSAME::FDIV_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDSAME::FMAXNMP_Vd_V_2S_Vn_V_2S_Vm_V_2S(opcode) => opcode.bits(),
            ASIMDSAME::FMAXNMP_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDSAME::FMAXNM_Vd_V_2S_Vn_V_2S_Vm_V_2S(opcode) => opcode.bits(),
            ASIMDSAME::FMAXNM_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDSAME::FMAXP_Vd_V_2S_Vn_V_2S_Vm_V_2S(opcode) => opcode.bits(),
            ASIMDSAME::FMAXP_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDSAME::FMAX_Vd_V_2S_Vn_V_2S_Vm_V_2S(opcode) => opcode.bits(),
            ASIMDSAME::FMAX_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDSAME::FMINNMP_Vd_V_2S_Vn_V_2S_Vm_V_2S(opcode) => opcode.bits(),
            ASIMDSAME::FMINNMP_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDSAME::FMINNM_Vd_V_2S_Vn_V_2S_Vm_V_2S(opcode) => opcode.bits(),
            ASIMDSAME::FMINNM_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDSAME::FMINP_Vd_V_2S_Vn_V_2S_Vm_V_2S(opcode) => opcode.bits(),
            ASIMDSAME::FMINP_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDSAME::FMIN_Vd_V_2S_Vn_V_2S_Vm_V_2S(opcode) => opcode.bits(),
            ASIMDSAME::FMIN_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDSAME::FMLAL2_Vd_V_4S_Vn_V_4H_Vm_V_4H(opcode) => opcode.bits(),
            ASIMDSAME::FMLAL2_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDSAME::FMLAL_Vd_V_4S_Vn_V_4H_Vm_V_4H(opcode) => opcode.bits(),
            ASIMDSAME::FMLAL_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDSAME::FMLA_Vd_V_2S_Vn_V_2S_Vm_V_2S(opcode) => opcode.bits(),
            ASIMDSAME::FMLA_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDSAME::FMLSL2_Vd_V_4S_Vn_V_4H_Vm_V_4H(opcode) => opcode.bits(),
            ASIMDSAME::FMLSL2_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDSAME::FMLSL_Vd_V_4S_Vn_V_4H_Vm_V_4H(opcode) => opcode.bits(),
            ASIMDSAME::FMLSL_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDSAME::FMLS_Vd_V_2S_Vn_V_2S_Vm_V_2S(opcode) => opcode.bits(),
            ASIMDSAME::FMLS_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDSAME::FMULX_Vd_V_2S_Vn_V_2S_Vm_V_2S(opcode) => opcode.bits(),
            ASIMDSAME::FMULX_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDSAME::FMUL_Vd_V_2S_Vn_V_2S_Vm_V_2S(opcode) => opcode.bits(),
            ASIMDSAME::FMUL_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDSAME::FRECPS_Vd_V_2S_Vn_V_2S_Vm_V_2S(opcode) => opcode.bits(),
            ASIMDSAME::FRECPS_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDSAME::FRSQRTS_Vd_V_2S_Vn_V_2S_Vm_V_2S(opcode) => opcode.bits(),
            ASIMDSAME::FRSQRTS_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDSAME::FSUB_Vd_V_2S_Vn_V_2S_Vm_V_2S(opcode) => opcode.bits(),
            ASIMDSAME::FSUB_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDSAME::MLA_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDSAME::MLS_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDSAME::MUL_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDSAME::ORN_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDSAME::ORR_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDSAME::PMUL_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDSAME::SABA_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDSAME::SABD_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDSAME::SHADD_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDSAME::SHSUB_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDSAME::SMAXP_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDSAME::SMAX_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDSAME::SMINP_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDSAME::SMIN_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDSAME::SQADD_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDSAME::SQDMULH_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDSAME::SQRDMLAH_Sd_Sn_Sm(opcode) => opcode.bits(),
            ASIMDSAME::SQRDMLAH_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDSAME::SQRDMLSH_Sd_Sn_Sm(opcode) => opcode.bits(),
            ASIMDSAME::SQRDMLSH_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDSAME::SQRDMULH_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDSAME::SQRSHL_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDSAME::SQSHL_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDSAME::SQSUB_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDSAME::SRHADD_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDSAME::SRSHL_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDSAME::SSHL_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDSAME::SUB_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDSAME::UABA_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDSAME::UABD_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDSAME::UHADD_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDSAME::UHSUB_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDSAME::UMAXP_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDSAME::UMAX_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDSAME::UMINP_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDSAME::UMIN_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDSAME::UQADD_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDSAME::UQRSHL_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDSAME::UQSHL_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDSAME::UQSUB_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDSAME::URHADD_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDSAME::URSHL_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDSAME::USHL_Vd_Vn_Vm(opcode) => opcode.bits(),
        }
    }
}
impl InsnOpcode for SVE_SIZE_BHS {
    fn definition(&self) -> &'static Insn {
        match self {
            SVE_SIZE_BHS::ASR_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_SIZE_BHS::ASR_SVE_Zd_S_B_SVE_Pg3_P_M_SVE_Zd_S_B_SVE_Zm_5_S_D(opcode) => {
                opcode.definition()
            }
            SVE_SIZE_BHS::CMPEQ_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_SIZE_BHS::CMPGE_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_SIZE_BHS::CMPGT_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_SIZE_BHS::CMPHI_SVE_Pd_S_B_SVE_Pg3_P_Z_SVE_Zn_S_B_SVE_Zm_16_S_D(opcode) => {
                opcode.definition()
            }
            SVE_SIZE_BHS::CMPHS_SVE_Pd_S_B_SVE_Pg3_P_Z_SVE_Zn_S_B_SVE_Zm_16_S_D(opcode) => {
                opcode.definition()
            }
            SVE_SIZE_BHS::CMPLE_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_SIZE_BHS::CMPLO_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_SIZE_BHS::CMPLS_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_SIZE_BHS::CMPLT_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_SIZE_BHS::CMPNE_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_SIZE_BHS::LSL_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_SIZE_BHS::LSL_SVE_Zd_S_B_SVE_Pg3_P_M_SVE_Zd_S_B_SVE_Zm_5_S_D(opcode) => {
                opcode.definition()
            }
            SVE_SIZE_BHS::LSR_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_SIZE_BHS::LSR_SVE_Zd_S_B_SVE_Pg3_P_M_SVE_Zd_S_B_SVE_Zm_5_S_D(opcode) => {
                opcode.definition()
            }
            SVE_SIZE_BHS::SADDV_SVE_Vd_SVE_Pg3_SVE_Zn(opcode) => opcode.definition(),
        }
    }
    fn bits(&self) -> u32 {
        match self {
            SVE_SIZE_BHS::ASR_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_SIZE_BHS::ASR_SVE_Zd_S_B_SVE_Pg3_P_M_SVE_Zd_S_B_SVE_Zm_5_S_D(opcode) => {
                opcode.bits()
            }
            SVE_SIZE_BHS::CMPEQ_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_SIZE_BHS::CMPGE_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_SIZE_BHS::CMPGT_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_SIZE_BHS::CMPHI_SVE_Pd_S_B_SVE_Pg3_P_Z_SVE_Zn_S_B_SVE_Zm_16_S_D(opcode) => {
                opcode.bits()
            }
            SVE_SIZE_BHS::CMPHS_SVE_Pd_S_B_SVE_Pg3_P_Z_SVE_Zn_S_B_SVE_Zm_16_S_D(opcode) => {
                opcode.bits()
            }
            SVE_SIZE_BHS::CMPLE_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_SIZE_BHS::CMPLO_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_SIZE_BHS::CMPLS_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_SIZE_BHS::CMPLT_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_SIZE_BHS::CMPNE_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_SIZE_BHS::LSL_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_SIZE_BHS::LSL_SVE_Zd_S_B_SVE_Pg3_P_M_SVE_Zd_S_B_SVE_Zm_5_S_D(opcode) => {
                opcode.bits()
            }
            SVE_SIZE_BHS::LSR_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_SIZE_BHS::LSR_SVE_Zd_S_B_SVE_Pg3_P_M_SVE_Zd_S_B_SVE_Zm_5_S_D(opcode) => {
                opcode.bits()
            }
            SVE_SIZE_BHS::SADDV_SVE_Vd_SVE_Pg3_SVE_Zn(opcode) => opcode.bits(),
        }
    }
}
impl InsnOpcode for FLOAT2INT {
    fn definition(&self) -> &'static Insn {
        match self {
            FLOAT2INT::FCVTAS_Rd_Fn(opcode) => opcode.definition(),
            FLOAT2INT::FCVTAS_Rd_W_Fn_S_D(opcode) => opcode.definition(),
            FLOAT2INT::FCVTAU_Rd_Fn(opcode) => opcode.definition(),
            FLOAT2INT::FCVTAU_Rd_W_Fn_S_D(opcode) => opcode.definition(),
            FLOAT2INT::FCVTMS_Rd_Fn(opcode) => opcode.definition(),
            FLOAT2INT::FCVTMS_Rd_W_Fn_S_D(opcode) => opcode.definition(),
            FLOAT2INT::FCVTMU_Rd_Fn(opcode) => opcode.definition(),
            FLOAT2INT::FCVTMU_Rd_W_Fn_S_D(opcode) => opcode.definition(),
            FLOAT2INT::FCVTNS_Rd_Fn(opcode) => opcode.definition(),
            FLOAT2INT::FCVTNS_Rd_W_Fn_S_D(opcode) => opcode.definition(),
            FLOAT2INT::FCVTNU_Rd_Fn(opcode) => opcode.definition(),
            FLOAT2INT::FCVTNU_Rd_W_Fn_S_D(opcode) => opcode.definition(),
            FLOAT2INT::FCVTPS_Rd_Fn(opcode) => opcode.definition(),
            FLOAT2INT::FCVTPS_Rd_W_Fn_S_D(opcode) => opcode.definition(),
            FLOAT2INT::FCVTPU_Rd_Fn(opcode) => opcode.definition(),
            FLOAT2INT::FCVTPU_Rd_W_Fn_S_D(opcode) => opcode.definition(),
            FLOAT2INT::FCVTZS_Rd_Fn(opcode) => opcode.definition(),
            FLOAT2INT::FCVTZS_Rd_W_Fn_S_D(opcode) => opcode.definition(),
            FLOAT2INT::FCVTZU_Rd_Fn(opcode) => opcode.definition(),
            FLOAT2INT::FCVTZU_Rd_W_Fn_S_D(opcode) => opcode.definition(),
            FLOAT2INT::FJCVTZS_Rd_Fn(opcode) => opcode.definition(),
            FLOAT2INT::FMOV_Fd_Rn(opcode) => opcode.definition(),
            FLOAT2INT::FMOV_Fd_S_S_Rn_W(opcode) => opcode.definition(),
            FLOAT2INT::FMOV_Rd_Fn(opcode) => opcode.definition(),
            FLOAT2INT::FMOV_Rd_VnD1(opcode) => opcode.definition(),
            FLOAT2INT::FMOV_Rd_W_Fn_S_S(opcode) => opcode.definition(),
            FLOAT2INT::FMOV_VdD1_Rn(opcode) => opcode.definition(),
            FLOAT2INT::SCVTF_Fd_Rn(opcode) => opcode.definition(),
            FLOAT2INT::SCVTF_Fd_S_D_Rn_W(opcode) => opcode.definition(),
            FLOAT2INT::UCVTF_Fd_Rn(opcode) => opcode.definition(),
            FLOAT2INT::UCVTF_Fd_S_D_Rn_W(opcode) => opcode.definition(),
        }
    }
    fn bits(&self) -> u32 {
        match self {
            FLOAT2INT::FCVTAS_Rd_Fn(opcode) => opcode.bits(),
            FLOAT2INT::FCVTAS_Rd_W_Fn_S_D(opcode) => opcode.bits(),
            FLOAT2INT::FCVTAU_Rd_Fn(opcode) => opcode.bits(),
            FLOAT2INT::FCVTAU_Rd_W_Fn_S_D(opcode) => opcode.bits(),
            FLOAT2INT::FCVTMS_Rd_Fn(opcode) => opcode.bits(),
            FLOAT2INT::FCVTMS_Rd_W_Fn_S_D(opcode) => opcode.bits(),
            FLOAT2INT::FCVTMU_Rd_Fn(opcode) => opcode.bits(),
            FLOAT2INT::FCVTMU_Rd_W_Fn_S_D(opcode) => opcode.bits(),
            FLOAT2INT::FCVTNS_Rd_Fn(opcode) => opcode.bits(),
            FLOAT2INT::FCVTNS_Rd_W_Fn_S_D(opcode) => opcode.bits(),
            FLOAT2INT::FCVTNU_Rd_Fn(opcode) => opcode.bits(),
            FLOAT2INT::FCVTNU_Rd_W_Fn_S_D(opcode) => opcode.bits(),
            FLOAT2INT::FCVTPS_Rd_Fn(opcode) => opcode.bits(),
            FLOAT2INT::FCVTPS_Rd_W_Fn_S_D(opcode) => opcode.bits(),
            FLOAT2INT::FCVTPU_Rd_Fn(opcode) => opcode.bits(),
            FLOAT2INT::FCVTPU_Rd_W_Fn_S_D(opcode) => opcode.bits(),
            FLOAT2INT::FCVTZS_Rd_Fn(opcode) => opcode.bits(),
            FLOAT2INT::FCVTZS_Rd_W_Fn_S_D(opcode) => opcode.bits(),
            FLOAT2INT::FCVTZU_Rd_Fn(opcode) => opcode.bits(),
            FLOAT2INT::FCVTZU_Rd_W_Fn_S_D(opcode) => opcode.bits(),
            FLOAT2INT::FJCVTZS_Rd_Fn(opcode) => opcode.bits(),
            FLOAT2INT::FMOV_Fd_Rn(opcode) => opcode.bits(),
            FLOAT2INT::FMOV_Fd_S_S_Rn_W(opcode) => opcode.bits(),
            FLOAT2INT::FMOV_Rd_Fn(opcode) => opcode.bits(),
            FLOAT2INT::FMOV_Rd_VnD1(opcode) => opcode.bits(),
            FLOAT2INT::FMOV_Rd_W_Fn_S_S(opcode) => opcode.bits(),
            FLOAT2INT::FMOV_VdD1_Rn(opcode) => opcode.bits(),
            FLOAT2INT::SCVTF_Fd_Rn(opcode) => opcode.bits(),
            FLOAT2INT::SCVTF_Fd_S_D_Rn_W(opcode) => opcode.bits(),
            FLOAT2INT::UCVTF_Fd_Rn(opcode) => opcode.bits(),
            FLOAT2INT::UCVTF_Fd_S_D_Rn_W(opcode) => opcode.bits(),
        }
    }
}
impl InsnOpcode for LDST_UNSCALED {
    fn definition(&self) -> &'static Insn {
        match self {
            LDST_UNSCALED::LDAPURB_Rt_ADDR_OFFSET(opcode) => opcode.definition(),
            LDST_UNSCALED::LDAPURH_Rt_ADDR_OFFSET(opcode) => opcode.definition(),
            LDST_UNSCALED::LDAPURSB_Rt_ADDR_OFFSET(opcode) => opcode.definition(),
            LDST_UNSCALED::LDAPURSB_Rt_W_ADDR_OFFSET(opcode) => opcode.definition(),
            LDST_UNSCALED::LDAPURSH_Rt_ADDR_OFFSET(opcode) => opcode.definition(),
            LDST_UNSCALED::LDAPURSH_Rt_W_ADDR_OFFSET(opcode) => opcode.definition(),
            LDST_UNSCALED::LDAPURSW_Rt_ADDR_OFFSET(opcode) => opcode.definition(),
            LDST_UNSCALED::LDAPUR_Rt_ADDR_OFFSET(opcode) => opcode.definition(),
            LDST_UNSCALED::LDAPUR_Rt_X_ADDR_OFFSET(opcode) => opcode.definition(),
            LDST_UNSCALED::LDG_Rt_ADDR_SIMM13(opcode) => opcode.definition(),
            LDST_UNSCALED::LDURB_Rt_ADDR_SIMM9(opcode) => opcode.definition(),
            LDST_UNSCALED::LDURH_Rt_ADDR_SIMM9(opcode) => opcode.definition(),
            LDST_UNSCALED::LDURSB_Rt_ADDR_SIMM9(opcode) => opcode.definition(),
            LDST_UNSCALED::LDURSH_Rt_ADDR_SIMM9(opcode) => opcode.definition(),
            LDST_UNSCALED::LDURSW_Rt_ADDR_SIMM9(opcode) => opcode.definition(),
            LDST_UNSCALED::LDUR_Ft_ADDR_SIMM9(opcode) => opcode.definition(),
            LDST_UNSCALED::LDUR_Rt_ADDR_SIMM9(opcode) => opcode.definition(),
            LDST_UNSCALED::PRFUM_PRFOP_ADDR_SIMM9(opcode) => opcode.definition(),
            LDST_UNSCALED::ST2G_Rt_SP_ADDR_SIMM13(opcode) => opcode.definition(),
            LDST_UNSCALED::STG_Rt_SP_ADDR_SIMM13(opcode) => opcode.definition(),
            LDST_UNSCALED::STLURB_Rt_ADDR_OFFSET(opcode) => opcode.definition(),
            LDST_UNSCALED::STLURH_Rt_ADDR_OFFSET(opcode) => opcode.definition(),
            LDST_UNSCALED::STLUR_Rt_ADDR_OFFSET(opcode) => opcode.definition(),
            LDST_UNSCALED::STLUR_Rt_X_ADDR_OFFSET(opcode) => opcode.definition(),
            LDST_UNSCALED::STURB_Rt_ADDR_SIMM9(opcode) => opcode.definition(),
            LDST_UNSCALED::STURH_Rt_ADDR_SIMM9(opcode) => opcode.definition(),
            LDST_UNSCALED::STUR_Ft_ADDR_SIMM9(opcode) => opcode.definition(),
            LDST_UNSCALED::STUR_Rt_ADDR_SIMM9(opcode) => opcode.definition(),
            LDST_UNSCALED::STZ2G_Rt_SP_ADDR_SIMM13(opcode) => opcode.definition(),
            LDST_UNSCALED::STZG_Rt_SP_ADDR_SIMM13(opcode) => opcode.definition(),
        }
    }
    fn bits(&self) -> u32 {
        match self {
            LDST_UNSCALED::LDAPURB_Rt_ADDR_OFFSET(opcode) => opcode.bits(),
            LDST_UNSCALED::LDAPURH_Rt_ADDR_OFFSET(opcode) => opcode.bits(),
            LDST_UNSCALED::LDAPURSB_Rt_ADDR_OFFSET(opcode) => opcode.bits(),
            LDST_UNSCALED::LDAPURSB_Rt_W_ADDR_OFFSET(opcode) => opcode.bits(),
            LDST_UNSCALED::LDAPURSH_Rt_ADDR_OFFSET(opcode) => opcode.bits(),
            LDST_UNSCALED::LDAPURSH_Rt_W_ADDR_OFFSET(opcode) => opcode.bits(),
            LDST_UNSCALED::LDAPURSW_Rt_ADDR_OFFSET(opcode) => opcode.bits(),
            LDST_UNSCALED::LDAPUR_Rt_ADDR_OFFSET(opcode) => opcode.bits(),
            LDST_UNSCALED::LDAPUR_Rt_X_ADDR_OFFSET(opcode) => opcode.bits(),
            LDST_UNSCALED::LDG_Rt_ADDR_SIMM13(opcode) => opcode.bits(),
            LDST_UNSCALED::LDURB_Rt_ADDR_SIMM9(opcode) => opcode.bits(),
            LDST_UNSCALED::LDURH_Rt_ADDR_SIMM9(opcode) => opcode.bits(),
            LDST_UNSCALED::LDURSB_Rt_ADDR_SIMM9(opcode) => opcode.bits(),
            LDST_UNSCALED::LDURSH_Rt_ADDR_SIMM9(opcode) => opcode.bits(),
            LDST_UNSCALED::LDURSW_Rt_ADDR_SIMM9(opcode) => opcode.bits(),
            LDST_UNSCALED::LDUR_Ft_ADDR_SIMM9(opcode) => opcode.bits(),
            LDST_UNSCALED::LDUR_Rt_ADDR_SIMM9(opcode) => opcode.bits(),
            LDST_UNSCALED::PRFUM_PRFOP_ADDR_SIMM9(opcode) => opcode.bits(),
            LDST_UNSCALED::ST2G_Rt_SP_ADDR_SIMM13(opcode) => opcode.bits(),
            LDST_UNSCALED::STG_Rt_SP_ADDR_SIMM13(opcode) => opcode.bits(),
            LDST_UNSCALED::STLURB_Rt_ADDR_OFFSET(opcode) => opcode.bits(),
            LDST_UNSCALED::STLURH_Rt_ADDR_OFFSET(opcode) => opcode.bits(),
            LDST_UNSCALED::STLUR_Rt_ADDR_OFFSET(opcode) => opcode.bits(),
            LDST_UNSCALED::STLUR_Rt_X_ADDR_OFFSET(opcode) => opcode.bits(),
            LDST_UNSCALED::STURB_Rt_ADDR_SIMM9(opcode) => opcode.bits(),
            LDST_UNSCALED::STURH_Rt_ADDR_SIMM9(opcode) => opcode.bits(),
            LDST_UNSCALED::STUR_Ft_ADDR_SIMM9(opcode) => opcode.bits(),
            LDST_UNSCALED::STUR_Rt_ADDR_SIMM9(opcode) => opcode.bits(),
            LDST_UNSCALED::STZ2G_Rt_SP_ADDR_SIMM13(opcode) => opcode.bits(),
            LDST_UNSCALED::STZG_Rt_SP_ADDR_SIMM13(opcode) => opcode.bits(),
        }
    }
}
impl InsnOpcode for ASISDSAME {
    fn definition(&self) -> &'static Insn {
        match self {
            ASISDSAME::ADD_Sd_Sn_Sm(opcode) => opcode.definition(),
            ASISDSAME::CMEQ_Sd_Sn_Sm(opcode) => opcode.definition(),
            ASISDSAME::CMGE_Sd_Sn_Sm(opcode) => opcode.definition(),
            ASISDSAME::CMGT_Sd_Sn_Sm(opcode) => opcode.definition(),
            ASISDSAME::CMHI_Sd_Sn_Sm(opcode) => opcode.definition(),
            ASISDSAME::CMHS_Sd_Sn_Sm(opcode) => opcode.definition(),
            ASISDSAME::CMTST_Sd_Sn_Sm(opcode) => opcode.definition(),
            ASISDSAME::FABD_Sd_S_S_Sn_S_S_Sm_S_S(opcode) => opcode.definition(),
            ASISDSAME::FABD_Sd_Sn_Sm(opcode) => opcode.definition(),
            ASISDSAME::FACGE_Sd_S_S_Sn_S_S_Sm_S_S(opcode) => opcode.definition(),
            ASISDSAME::FACGE_Sd_Sn_Sm(opcode) => opcode.definition(),
            ASISDSAME::FACGT_Sd_S_S_Sn_S_S_Sm_S_S(opcode) => opcode.definition(),
            ASISDSAME::FACGT_Sd_Sn_Sm(opcode) => opcode.definition(),
            ASISDSAME::FCMEQ_Sd_S_S_Sn_S_S_Sm_S_S(opcode) => opcode.definition(),
            ASISDSAME::FCMEQ_Sd_Sn_Sm(opcode) => opcode.definition(),
            ASISDSAME::FCMGE_Sd_S_S_Sn_S_S_Sm_S_S(opcode) => opcode.definition(),
            ASISDSAME::FCMGE_Sd_Sn_Sm(opcode) => opcode.definition(),
            ASISDSAME::FCMGT_Sd_S_S_Sn_S_S_Sm_S_S(opcode) => opcode.definition(),
            ASISDSAME::FCMGT_Sd_Sn_Sm(opcode) => opcode.definition(),
            ASISDSAME::FMULX_Sd_S_S_Sn_S_S_Sm_S_S(opcode) => opcode.definition(),
            ASISDSAME::FMULX_Sd_Sn_Sm(opcode) => opcode.definition(),
            ASISDSAME::FRECPS_Sd_S_S_Sn_S_S_Sm_S_S(opcode) => opcode.definition(),
            ASISDSAME::FRECPS_Sd_Sn_Sm(opcode) => opcode.definition(),
            ASISDSAME::FRSQRTS_Sd_S_S_Sn_S_S_Sm_S_S(opcode) => opcode.definition(),
            ASISDSAME::FRSQRTS_Sd_Sn_Sm(opcode) => opcode.definition(),
            ASISDSAME::SQADD_Sd_Sn_Sm(opcode) => opcode.definition(),
            ASISDSAME::SQDMULH_Sd_Sn_Sm(opcode) => opcode.definition(),
            ASISDSAME::SQRDMULH_Sd_Sn_Sm(opcode) => opcode.definition(),
            ASISDSAME::SQRSHL_Sd_Sn_Sm(opcode) => opcode.definition(),
            ASISDSAME::SQSHL_Sd_Sn_Sm(opcode) => opcode.definition(),
            ASISDSAME::SQSUB_Sd_Sn_Sm(opcode) => opcode.definition(),
            ASISDSAME::SRSHL_Sd_Sn_Sm(opcode) => opcode.definition(),
            ASISDSAME::SSHL_Sd_Sn_Sm(opcode) => opcode.definition(),
            ASISDSAME::SUB_Sd_Sn_Sm(opcode) => opcode.definition(),
            ASISDSAME::UQADD_Sd_Sn_Sm(opcode) => opcode.definition(),
            ASISDSAME::UQRSHL_Sd_Sn_Sm(opcode) => opcode.definition(),
            ASISDSAME::UQSHL_Sd_Sn_Sm(opcode) => opcode.definition(),
            ASISDSAME::UQSUB_Sd_Sn_Sm(opcode) => opcode.definition(),
            ASISDSAME::URSHL_Sd_Sn_Sm(opcode) => opcode.definition(),
            ASISDSAME::USHL_Sd_Sn_Sm(opcode) => opcode.definition(),
        }
    }
    fn bits(&self) -> u32 {
        match self {
            ASISDSAME::ADD_Sd_Sn_Sm(opcode) => opcode.bits(),
            ASISDSAME::CMEQ_Sd_Sn_Sm(opcode) => opcode.bits(),
            ASISDSAME::CMGE_Sd_Sn_Sm(opcode) => opcode.bits(),
            ASISDSAME::CMGT_Sd_Sn_Sm(opcode) => opcode.bits(),
            ASISDSAME::CMHI_Sd_Sn_Sm(opcode) => opcode.bits(),
            ASISDSAME::CMHS_Sd_Sn_Sm(opcode) => opcode.bits(),
            ASISDSAME::CMTST_Sd_Sn_Sm(opcode) => opcode.bits(),
            ASISDSAME::FABD_Sd_S_S_Sn_S_S_Sm_S_S(opcode) => opcode.bits(),
            ASISDSAME::FABD_Sd_Sn_Sm(opcode) => opcode.bits(),
            ASISDSAME::FACGE_Sd_S_S_Sn_S_S_Sm_S_S(opcode) => opcode.bits(),
            ASISDSAME::FACGE_Sd_Sn_Sm(opcode) => opcode.bits(),
            ASISDSAME::FACGT_Sd_S_S_Sn_S_S_Sm_S_S(opcode) => opcode.bits(),
            ASISDSAME::FACGT_Sd_Sn_Sm(opcode) => opcode.bits(),
            ASISDSAME::FCMEQ_Sd_S_S_Sn_S_S_Sm_S_S(opcode) => opcode.bits(),
            ASISDSAME::FCMEQ_Sd_Sn_Sm(opcode) => opcode.bits(),
            ASISDSAME::FCMGE_Sd_S_S_Sn_S_S_Sm_S_S(opcode) => opcode.bits(),
            ASISDSAME::FCMGE_Sd_Sn_Sm(opcode) => opcode.bits(),
            ASISDSAME::FCMGT_Sd_S_S_Sn_S_S_Sm_S_S(opcode) => opcode.bits(),
            ASISDSAME::FCMGT_Sd_Sn_Sm(opcode) => opcode.bits(),
            ASISDSAME::FMULX_Sd_S_S_Sn_S_S_Sm_S_S(opcode) => opcode.bits(),
            ASISDSAME::FMULX_Sd_Sn_Sm(opcode) => opcode.bits(),
            ASISDSAME::FRECPS_Sd_S_S_Sn_S_S_Sm_S_S(opcode) => opcode.bits(),
            ASISDSAME::FRECPS_Sd_Sn_Sm(opcode) => opcode.bits(),
            ASISDSAME::FRSQRTS_Sd_S_S_Sn_S_S_Sm_S_S(opcode) => opcode.bits(),
            ASISDSAME::FRSQRTS_Sd_Sn_Sm(opcode) => opcode.bits(),
            ASISDSAME::SQADD_Sd_Sn_Sm(opcode) => opcode.bits(),
            ASISDSAME::SQDMULH_Sd_Sn_Sm(opcode) => opcode.bits(),
            ASISDSAME::SQRDMULH_Sd_Sn_Sm(opcode) => opcode.bits(),
            ASISDSAME::SQRSHL_Sd_Sn_Sm(opcode) => opcode.bits(),
            ASISDSAME::SQSHL_Sd_Sn_Sm(opcode) => opcode.bits(),
            ASISDSAME::SQSUB_Sd_Sn_Sm(opcode) => opcode.bits(),
            ASISDSAME::SRSHL_Sd_Sn_Sm(opcode) => opcode.bits(),
            ASISDSAME::SSHL_Sd_Sn_Sm(opcode) => opcode.bits(),
            ASISDSAME::SUB_Sd_Sn_Sm(opcode) => opcode.bits(),
            ASISDSAME::UQADD_Sd_Sn_Sm(opcode) => opcode.bits(),
            ASISDSAME::UQRSHL_Sd_Sn_Sm(opcode) => opcode.bits(),
            ASISDSAME::UQSHL_Sd_Sn_Sm(opcode) => opcode.bits(),
            ASISDSAME::UQSUB_Sd_Sn_Sm(opcode) => opcode.bits(),
            ASISDSAME::URSHL_Sd_Sn_Sm(opcode) => opcode.bits(),
            ASISDSAME::USHL_Sd_Sn_Sm(opcode) => opcode.bits(),
        }
    }
}
impl InsnOpcode for ASIMDDIFF {
    fn definition(&self) -> &'static Insn {
        match self {
            ASIMDDIFF::ADDHN2_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDDIFF::ADDHN_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDDIFF::PMULL2_Vd_V_1Q_Vn_V_2D_Vm_V_2D(opcode) => opcode.definition(),
            ASIMDDIFF::PMULL2_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDDIFF::PMULL_Vd_V_1Q_Vn_V_1D_Vm_V_1D(opcode) => opcode.definition(),
            ASIMDDIFF::PMULL_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDDIFF::RADDHN2_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDDIFF::RADDHN_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDDIFF::RSUBHN2_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDDIFF::RSUBHN_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDDIFF::SABAL2_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDDIFF::SABAL_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDDIFF::SABDL2_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDDIFF::SABDL_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDDIFF::SADDL2_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDDIFF::SADDL_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDDIFF::SADDW2_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDDIFF::SADDW_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDDIFF::SMLAL2_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDDIFF::SMLAL_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDDIFF::SMLSL2_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDDIFF::SMLSL_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDDIFF::SMULL2_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDDIFF::SMULL_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDDIFF::SQDMLAL2_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDDIFF::SQDMLAL_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDDIFF::SQDMLSL2_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDDIFF::SQDMLSL_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDDIFF::SQDMULL2_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDDIFF::SQDMULL_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDDIFF::SSUBL2_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDDIFF::SSUBL_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDDIFF::SSUBW2_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDDIFF::SSUBW_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDDIFF::SUBHN2_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDDIFF::SUBHN_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDDIFF::UABAL2_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDDIFF::UABAL_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDDIFF::UABDL2_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDDIFF::UABDL_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDDIFF::UADDL2_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDDIFF::UADDL_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDDIFF::UADDW2_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDDIFF::UADDW_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDDIFF::UMLAL2_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDDIFF::UMLAL_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDDIFF::UMLSL2_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDDIFF::UMLSL_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDDIFF::UMULL2_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDDIFF::UMULL_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDDIFF::USUBL2_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDDIFF::USUBL_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDDIFF::USUBW2_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDDIFF::USUBW_Vd_Vn_Vm(opcode) => opcode.definition(),
        }
    }
    fn bits(&self) -> u32 {
        match self {
            ASIMDDIFF::ADDHN2_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDDIFF::ADDHN_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDDIFF::PMULL2_Vd_V_1Q_Vn_V_2D_Vm_V_2D(opcode) => opcode.bits(),
            ASIMDDIFF::PMULL2_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDDIFF::PMULL_Vd_V_1Q_Vn_V_1D_Vm_V_1D(opcode) => opcode.bits(),
            ASIMDDIFF::PMULL_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDDIFF::RADDHN2_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDDIFF::RADDHN_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDDIFF::RSUBHN2_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDDIFF::RSUBHN_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDDIFF::SABAL2_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDDIFF::SABAL_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDDIFF::SABDL2_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDDIFF::SABDL_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDDIFF::SADDL2_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDDIFF::SADDL_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDDIFF::SADDW2_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDDIFF::SADDW_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDDIFF::SMLAL2_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDDIFF::SMLAL_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDDIFF::SMLSL2_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDDIFF::SMLSL_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDDIFF::SMULL2_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDDIFF::SMULL_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDDIFF::SQDMLAL2_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDDIFF::SQDMLAL_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDDIFF::SQDMLSL2_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDDIFF::SQDMLSL_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDDIFF::SQDMULL2_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDDIFF::SQDMULL_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDDIFF::SSUBL2_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDDIFF::SSUBL_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDDIFF::SSUBW2_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDDIFF::SSUBW_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDDIFF::SUBHN2_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDDIFF::SUBHN_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDDIFF::UABAL2_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDDIFF::UABAL_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDDIFF::UABDL2_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDDIFF::UABDL_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDDIFF::UADDL2_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDDIFF::UADDL_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDDIFF::UADDW2_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDDIFF::UADDW_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDDIFF::UMLAL2_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDDIFF::UMLAL_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDDIFF::UMLSL2_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDDIFF::UMLSL_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDDIFF::UMULL2_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDDIFF::UMULL_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDDIFF::USUBL2_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDDIFF::USUBL_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDDIFF::USUBW2_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDDIFF::USUBW_Vd_Vn_Vm(opcode) => opcode.bits(),
        }
    }
}
impl InsnOpcode for CONDCMP_IMM {
    fn definition(&self) -> &'static Insn {
        match self {
            CONDCMP_IMM::CCMN_Rn_CCMP_IMM_NZCV_COND(opcode) => opcode.definition(),
            CONDCMP_IMM::CCMP_Rn_CCMP_IMM_NZCV_COND(opcode) => opcode.definition(),
        }
    }
    fn bits(&self) -> u32 {
        match self {
            CONDCMP_IMM::CCMN_Rn_CCMP_IMM_NZCV_COND(opcode) => opcode.bits(),
            CONDCMP_IMM::CCMP_Rn_CCMP_IMM_NZCV_COND(opcode) => opcode.bits(),
        }
    }
}
impl InsnOpcode for SME_FP_SD {
    fn definition(&self) -> &'static Insn {
        match self {
            SME_FP_SD::FADD_SME_ZA_array_off3_0_SME_Znx2(opcode) => opcode.definition(),
            SME_FP_SD::FADD_SME_ZA_array_off3_0_SME_Znx4(opcode) => opcode.definition(),
            SME_FP_SD::FMLA_SME_ZA_array_off3_0_SME_Znx2_SME_Zmx2(opcode) => opcode.definition(),
            SME_FP_SD::FMLA_SME_ZA_array_off3_0_SME_Znx4_SME_Zmx4(opcode) => opcode.definition(),
            SME_FP_SD::FMLA_SME_ZA_array_off3_0_SVE_ZnxN_SME_Zm(opcode) => opcode.definition(),
            SME_FP_SD::FMLA_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_S_SME_Zm_S_S(opcode) => {
                opcode.definition()
            }
            SME_FP_SD::FMLS_SME_ZA_array_off3_0_SME_Znx2_SME_Zmx2(opcode) => opcode.definition(),
            SME_FP_SD::FMLS_SME_ZA_array_off3_0_SME_Znx4_SME_Zmx4(opcode) => opcode.definition(),
            SME_FP_SD::FMLS_SME_ZA_array_off3_0_SVE_ZnxN_SME_Zm(opcode) => opcode.definition(),
            SME_FP_SD::FMLS_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_S_SME_Zm_S_S(opcode) => {
                opcode.definition()
            }
            SME_FP_SD::FSUB_SME_ZA_array_off3_0_SME_Znx2(opcode) => opcode.definition(),
            SME_FP_SD::FSUB_SME_ZA_array_off3_0_SME_Znx4(opcode) => opcode.definition(),
        }
    }
    fn bits(&self) -> u32 {
        match self {
            SME_FP_SD::FADD_SME_ZA_array_off3_0_SME_Znx2(opcode) => opcode.bits(),
            SME_FP_SD::FADD_SME_ZA_array_off3_0_SME_Znx4(opcode) => opcode.bits(),
            SME_FP_SD::FMLA_SME_ZA_array_off3_0_SME_Znx2_SME_Zmx2(opcode) => opcode.bits(),
            SME_FP_SD::FMLA_SME_ZA_array_off3_0_SME_Znx4_SME_Zmx4(opcode) => opcode.bits(),
            SME_FP_SD::FMLA_SME_ZA_array_off3_0_SVE_ZnxN_SME_Zm(opcode) => opcode.bits(),
            SME_FP_SD::FMLA_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_S_SME_Zm_S_S(opcode) => {
                opcode.bits()
            }
            SME_FP_SD::FMLS_SME_ZA_array_off3_0_SME_Znx2_SME_Zmx2(opcode) => opcode.bits(),
            SME_FP_SD::FMLS_SME_ZA_array_off3_0_SME_Znx4_SME_Zmx4(opcode) => opcode.bits(),
            SME_FP_SD::FMLS_SME_ZA_array_off3_0_SVE_ZnxN_SME_Zm(opcode) => opcode.bits(),
            SME_FP_SD::FMLS_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_S_SME_Zm_S_S(opcode) => {
                opcode.bits()
            }
            SME_FP_SD::FSUB_SME_ZA_array_off3_0_SME_Znx2(opcode) => opcode.bits(),
            SME_FP_SD::FSUB_SME_ZA_array_off3_0_SME_Znx4(opcode) => opcode.bits(),
        }
    }
}
impl InsnOpcode for SVE_SIZE_HSD {
    fn definition(&self) -> &'static Insn {
        match self {
            SVE_SIZE_HSD::ADDHNB_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_SIZE_HSD::ADDHNT_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_SIZE_HSD::DECP_SVE_Zd_SVE_Pg4_5(opcode) => opcode.definition(),
            SVE_SIZE_HSD::FABD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(opcode) => opcode.definition(),
            SVE_SIZE_HSD::FABS_SVE_Zd_SVE_Pg3_SVE_Zn(opcode) => opcode.definition(),
            SVE_SIZE_HSD::FACGE_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_SIZE_HSD::FACGT_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_SIZE_HSD::FADDA_SVE_Vd_SVE_Pg3_SVE_Vd_SVE_Zm_5(opcode) => opcode.definition(),
            SVE_SIZE_HSD::FADDP_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(opcode) => opcode.definition(),
            SVE_SIZE_HSD::FADDV_SVE_Vd_SVE_Pg3_SVE_Zn(opcode) => opcode.definition(),
            SVE_SIZE_HSD::FADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_I1_HALF_ONE(opcode) => opcode.definition(),
            SVE_SIZE_HSD::FADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(opcode) => opcode.definition(),
            SVE_SIZE_HSD::FADD_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_SIZE_HSD::FCADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5_SVE_IMM_ROT1(opcode) => {
                opcode.definition()
            }
            SVE_SIZE_HSD::FCMEQ_SVE_Pd_SVE_Pg3_SVE_Zn_FPIMM0(opcode) => opcode.definition(),
            SVE_SIZE_HSD::FCMEQ_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_SIZE_HSD::FCMGE_SVE_Pd_SVE_Pg3_SVE_Zn_FPIMM0(opcode) => opcode.definition(),
            SVE_SIZE_HSD::FCMGE_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_SIZE_HSD::FCMGT_SVE_Pd_SVE_Pg3_SVE_Zn_FPIMM0(opcode) => opcode.definition(),
            SVE_SIZE_HSD::FCMGT_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_SIZE_HSD::FCMLA_SVE_Zd_SVE_Pg3_SVE_Zn_SVE_Zm_16_IMM_ROT2(opcode) => {
                opcode.definition()
            }
            SVE_SIZE_HSD::FCMLE_SVE_Pd_SVE_Pg3_SVE_Zn_FPIMM0(opcode) => opcode.definition(),
            SVE_SIZE_HSD::FCMLT_SVE_Pd_SVE_Pg3_SVE_Zn_FPIMM0(opcode) => opcode.definition(),
            SVE_SIZE_HSD::FCMNE_SVE_Pd_SVE_Pg3_SVE_Zn_FPIMM0(opcode) => opcode.definition(),
            SVE_SIZE_HSD::FCMNE_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_SIZE_HSD::FCMUO_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_SIZE_HSD::FCPY_SVE_Zd_SVE_Pg4_16_SVE_FPIMM8(opcode) => opcode.definition(),
            SVE_SIZE_HSD::FDIVR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(opcode) => opcode.definition(),
            SVE_SIZE_HSD::FDIV_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(opcode) => opcode.definition(),
            SVE_SIZE_HSD::FDUP_SVE_Zd_SVE_FPIMM8(opcode) => opcode.definition(),
            SVE_SIZE_HSD::FEXPA_SVE_Zd_SVE_Zn(opcode) => opcode.definition(),
            SVE_SIZE_HSD::FMAD_SVE_Zd_SVE_Pg3_SVE_Zm_5_SVE_Za_16(opcode) => opcode.definition(),
            SVE_SIZE_HSD::FMAXNMP_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(opcode) => opcode.definition(),
            SVE_SIZE_HSD::FMAXNMV_SVE_Vd_SVE_Pg3_SVE_Zn(opcode) => opcode.definition(),
            SVE_SIZE_HSD::FMAXNM_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_I1_ZERO_ONE(opcode) => {
                opcode.definition()
            }
            SVE_SIZE_HSD::FMAXNM_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(opcode) => opcode.definition(),
            SVE_SIZE_HSD::FMAXP_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(opcode) => opcode.definition(),
            SVE_SIZE_HSD::FMAXV_SVE_Vd_SVE_Pg3_SVE_Zn(opcode) => opcode.definition(),
            SVE_SIZE_HSD::FMAX_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_I1_ZERO_ONE(opcode) => opcode.definition(),
            SVE_SIZE_HSD::FMAX_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(opcode) => opcode.definition(),
            SVE_SIZE_HSD::FMINNMP_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(opcode) => opcode.definition(),
            SVE_SIZE_HSD::FMINNMV_SVE_Vd_SVE_Pg3_SVE_Zn(opcode) => opcode.definition(),
            SVE_SIZE_HSD::FMINNM_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_I1_ZERO_ONE(opcode) => {
                opcode.definition()
            }
            SVE_SIZE_HSD::FMINNM_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(opcode) => opcode.definition(),
            SVE_SIZE_HSD::FMINP_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(opcode) => opcode.definition(),
            SVE_SIZE_HSD::FMINV_SVE_Vd_SVE_Pg3_SVE_Zn(opcode) => opcode.definition(),
            SVE_SIZE_HSD::FMIN_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_I1_ZERO_ONE(opcode) => opcode.definition(),
            SVE_SIZE_HSD::FMIN_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(opcode) => opcode.definition(),
            SVE_SIZE_HSD::FMLA_SVE_Zd_SVE_Pg3_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_SIZE_HSD::FMLS_SVE_Zd_SVE_Pg3_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_SIZE_HSD::FMSB_SVE_Zd_SVE_Pg3_SVE_Zm_5_SVE_Za_16(opcode) => opcode.definition(),
            SVE_SIZE_HSD::FMULX_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(opcode) => opcode.definition(),
            SVE_SIZE_HSD::FMUL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_I1_HALF_TWO(opcode) => opcode.definition(),
            SVE_SIZE_HSD::FMUL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(opcode) => opcode.definition(),
            SVE_SIZE_HSD::FMUL_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_SIZE_HSD::FNEG_SVE_Zd_SVE_Pg3_SVE_Zn(opcode) => opcode.definition(),
            SVE_SIZE_HSD::FNMAD_SVE_Zd_SVE_Pg3_SVE_Zm_5_SVE_Za_16(opcode) => opcode.definition(),
            SVE_SIZE_HSD::FNMLA_SVE_Zd_SVE_Pg3_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_SIZE_HSD::FNMLS_SVE_Zd_SVE_Pg3_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_SIZE_HSD::FNMSB_SVE_Zd_SVE_Pg3_SVE_Zm_5_SVE_Za_16(opcode) => opcode.definition(),
            SVE_SIZE_HSD::FRECPE_SVE_Zd_SVE_Zn(opcode) => opcode.definition(),
            SVE_SIZE_HSD::FRECPS_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_SIZE_HSD::FRECPX_SVE_Zd_SVE_Pg3_SVE_Zn(opcode) => opcode.definition(),
            SVE_SIZE_HSD::FRINTA_SVE_Zd_SVE_Pg3_SVE_Zn(opcode) => opcode.definition(),
            SVE_SIZE_HSD::FRINTI_SVE_Zd_SVE_Pg3_SVE_Zn(opcode) => opcode.definition(),
            SVE_SIZE_HSD::FRINTM_SVE_Zd_SVE_Pg3_SVE_Zn(opcode) => opcode.definition(),
            SVE_SIZE_HSD::FRINTN_SVE_Zd_SVE_Pg3_SVE_Zn(opcode) => opcode.definition(),
            SVE_SIZE_HSD::FRINTP_SVE_Zd_SVE_Pg3_SVE_Zn(opcode) => opcode.definition(),
            SVE_SIZE_HSD::FRINTX_SVE_Zd_SVE_Pg3_SVE_Zn(opcode) => opcode.definition(),
            SVE_SIZE_HSD::FRINTZ_SVE_Zd_SVE_Pg3_SVE_Zn(opcode) => opcode.definition(),
            SVE_SIZE_HSD::FRSQRTE_SVE_Zd_SVE_Zn(opcode) => opcode.definition(),
            SVE_SIZE_HSD::FRSQRTS_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_SIZE_HSD::FSCALE_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(opcode) => opcode.definition(),
            SVE_SIZE_HSD::FSQRT_SVE_Zd_SVE_Pg3_SVE_Zn(opcode) => opcode.definition(),
            SVE_SIZE_HSD::FSUBR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_I1_HALF_ONE(opcode) => {
                opcode.definition()
            }
            SVE_SIZE_HSD::FSUBR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(opcode) => opcode.definition(),
            SVE_SIZE_HSD::FSUB_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_I1_HALF_ONE(opcode) => opcode.definition(),
            SVE_SIZE_HSD::FSUB_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(opcode) => opcode.definition(),
            SVE_SIZE_HSD::FSUB_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_SIZE_HSD::FTMAD_SVE_Zd_SVE_Zd_SVE_Zm_5_SVE_UIMM3(opcode) => opcode.definition(),
            SVE_SIZE_HSD::FTSMUL_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_SIZE_HSD::FTSSEL_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_SIZE_HSD::INCP_SVE_Zd_SVE_Pg4_5(opcode) => opcode.definition(),
            SVE_SIZE_HSD::RADDHNB_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_SIZE_HSD::RADDHNT_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_SIZE_HSD::REVB_SVE_Zd_SVE_Pg3_SVE_Zn(opcode) => opcode.definition(),
            SVE_SIZE_HSD::RSUBHNB_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_SIZE_HSD::RSUBHNT_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_SIZE_HSD::SABALB_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_SIZE_HSD::SABALT_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_SIZE_HSD::SABDLB_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_SIZE_HSD::SABDLT_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_SIZE_HSD::SADALP_SVE_Zd_SVE_Pg3_SVE_Zn(opcode) => opcode.definition(),
            SVE_SIZE_HSD::SADDLBT_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_SIZE_HSD::SADDLB_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_SIZE_HSD::SADDLT_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_SIZE_HSD::SADDWB_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_SIZE_HSD::SADDWT_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_SIZE_HSD::SMLALB_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_SIZE_HSD::SMLALT_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_SIZE_HSD::SMLSLB_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_SIZE_HSD::SMLSLT_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_SIZE_HSD::SMULLB_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_SIZE_HSD::SMULLT_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_SIZE_HSD::SQDECP_SVE_Zd_SVE_Pg4_5(opcode) => opcode.definition(),
            SVE_SIZE_HSD::SQDMLALBT_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_SIZE_HSD::SQDMLALB_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_SIZE_HSD::SQDMLALT_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_SIZE_HSD::SQDMLSLBT_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_SIZE_HSD::SQDMLSLB_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_SIZE_HSD::SQDMLSLT_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_SIZE_HSD::SQDMULLB_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_SIZE_HSD::SQDMULLT_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_SIZE_HSD::SQINCP_SVE_Zd_SVE_Pg4_5(opcode) => opcode.definition(),
            SVE_SIZE_HSD::SSUBLBT_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_SIZE_HSD::SSUBLB_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_SIZE_HSD::SSUBLTB_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_SIZE_HSD::SSUBLT_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_SIZE_HSD::SSUBWB_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_SIZE_HSD::SSUBWT_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_SIZE_HSD::SUBHNB_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_SIZE_HSD::SUBHNT_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_SIZE_HSD::SUNPKHI_SVE_Zd_SVE_Zn(opcode) => opcode.definition(),
            SVE_SIZE_HSD::SUNPKLO_SVE_Zd_SVE_Zn(opcode) => opcode.definition(),
            SVE_SIZE_HSD::SXTB_SVE_Zd_SVE_Pg3_SVE_Zn(opcode) => opcode.definition(),
            SVE_SIZE_HSD::UABALB_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_SIZE_HSD::UABALT_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_SIZE_HSD::UABDLB_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_SIZE_HSD::UABDLT_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_SIZE_HSD::UADALP_SVE_Zd_SVE_Pg3_SVE_Zn(opcode) => opcode.definition(),
            SVE_SIZE_HSD::UADDLB_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_SIZE_HSD::UADDLT_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_SIZE_HSD::UADDWB_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_SIZE_HSD::UADDWT_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_SIZE_HSD::UMLALB_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_SIZE_HSD::UMLALT_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_SIZE_HSD::UMLSLB_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_SIZE_HSD::UMLSLT_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_SIZE_HSD::UMULLB_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_SIZE_HSD::UMULLT_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_SIZE_HSD::UQDECP_SVE_Zd_SVE_Pg4_5(opcode) => opcode.definition(),
            SVE_SIZE_HSD::UQINCP_SVE_Zd_SVE_Pg4_5(opcode) => opcode.definition(),
            SVE_SIZE_HSD::USUBLB_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_SIZE_HSD::USUBLT_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_SIZE_HSD::USUBWB_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_SIZE_HSD::USUBWT_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_SIZE_HSD::UUNPKHI_SVE_Zd_SVE_Zn(opcode) => opcode.definition(),
            SVE_SIZE_HSD::UUNPKLO_SVE_Zd_SVE_Zn(opcode) => opcode.definition(),
            SVE_SIZE_HSD::UXTB_SVE_Zd_SVE_Pg3_SVE_Zn(opcode) => opcode.definition(),
        }
    }
    fn bits(&self) -> u32 {
        match self {
            SVE_SIZE_HSD::ADDHNB_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_SIZE_HSD::ADDHNT_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_SIZE_HSD::DECP_SVE_Zd_SVE_Pg4_5(opcode) => opcode.bits(),
            SVE_SIZE_HSD::FABD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(opcode) => opcode.bits(),
            SVE_SIZE_HSD::FABS_SVE_Zd_SVE_Pg3_SVE_Zn(opcode) => opcode.bits(),
            SVE_SIZE_HSD::FACGE_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_SIZE_HSD::FACGT_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_SIZE_HSD::FADDA_SVE_Vd_SVE_Pg3_SVE_Vd_SVE_Zm_5(opcode) => opcode.bits(),
            SVE_SIZE_HSD::FADDP_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(opcode) => opcode.bits(),
            SVE_SIZE_HSD::FADDV_SVE_Vd_SVE_Pg3_SVE_Zn(opcode) => opcode.bits(),
            SVE_SIZE_HSD::FADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_I1_HALF_ONE(opcode) => opcode.bits(),
            SVE_SIZE_HSD::FADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(opcode) => opcode.bits(),
            SVE_SIZE_HSD::FADD_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_SIZE_HSD::FCADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5_SVE_IMM_ROT1(opcode) => {
                opcode.bits()
            }
            SVE_SIZE_HSD::FCMEQ_SVE_Pd_SVE_Pg3_SVE_Zn_FPIMM0(opcode) => opcode.bits(),
            SVE_SIZE_HSD::FCMEQ_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_SIZE_HSD::FCMGE_SVE_Pd_SVE_Pg3_SVE_Zn_FPIMM0(opcode) => opcode.bits(),
            SVE_SIZE_HSD::FCMGE_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_SIZE_HSD::FCMGT_SVE_Pd_SVE_Pg3_SVE_Zn_FPIMM0(opcode) => opcode.bits(),
            SVE_SIZE_HSD::FCMGT_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_SIZE_HSD::FCMLA_SVE_Zd_SVE_Pg3_SVE_Zn_SVE_Zm_16_IMM_ROT2(opcode) => opcode.bits(),
            SVE_SIZE_HSD::FCMLE_SVE_Pd_SVE_Pg3_SVE_Zn_FPIMM0(opcode) => opcode.bits(),
            SVE_SIZE_HSD::FCMLT_SVE_Pd_SVE_Pg3_SVE_Zn_FPIMM0(opcode) => opcode.bits(),
            SVE_SIZE_HSD::FCMNE_SVE_Pd_SVE_Pg3_SVE_Zn_FPIMM0(opcode) => opcode.bits(),
            SVE_SIZE_HSD::FCMNE_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_SIZE_HSD::FCMUO_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_SIZE_HSD::FCPY_SVE_Zd_SVE_Pg4_16_SVE_FPIMM8(opcode) => opcode.bits(),
            SVE_SIZE_HSD::FDIVR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(opcode) => opcode.bits(),
            SVE_SIZE_HSD::FDIV_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(opcode) => opcode.bits(),
            SVE_SIZE_HSD::FDUP_SVE_Zd_SVE_FPIMM8(opcode) => opcode.bits(),
            SVE_SIZE_HSD::FEXPA_SVE_Zd_SVE_Zn(opcode) => opcode.bits(),
            SVE_SIZE_HSD::FMAD_SVE_Zd_SVE_Pg3_SVE_Zm_5_SVE_Za_16(opcode) => opcode.bits(),
            SVE_SIZE_HSD::FMAXNMP_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(opcode) => opcode.bits(),
            SVE_SIZE_HSD::FMAXNMV_SVE_Vd_SVE_Pg3_SVE_Zn(opcode) => opcode.bits(),
            SVE_SIZE_HSD::FMAXNM_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_I1_ZERO_ONE(opcode) => opcode.bits(),
            SVE_SIZE_HSD::FMAXNM_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(opcode) => opcode.bits(),
            SVE_SIZE_HSD::FMAXP_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(opcode) => opcode.bits(),
            SVE_SIZE_HSD::FMAXV_SVE_Vd_SVE_Pg3_SVE_Zn(opcode) => opcode.bits(),
            SVE_SIZE_HSD::FMAX_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_I1_ZERO_ONE(opcode) => opcode.bits(),
            SVE_SIZE_HSD::FMAX_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(opcode) => opcode.bits(),
            SVE_SIZE_HSD::FMINNMP_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(opcode) => opcode.bits(),
            SVE_SIZE_HSD::FMINNMV_SVE_Vd_SVE_Pg3_SVE_Zn(opcode) => opcode.bits(),
            SVE_SIZE_HSD::FMINNM_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_I1_ZERO_ONE(opcode) => opcode.bits(),
            SVE_SIZE_HSD::FMINNM_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(opcode) => opcode.bits(),
            SVE_SIZE_HSD::FMINP_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(opcode) => opcode.bits(),
            SVE_SIZE_HSD::FMINV_SVE_Vd_SVE_Pg3_SVE_Zn(opcode) => opcode.bits(),
            SVE_SIZE_HSD::FMIN_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_I1_ZERO_ONE(opcode) => opcode.bits(),
            SVE_SIZE_HSD::FMIN_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(opcode) => opcode.bits(),
            SVE_SIZE_HSD::FMLA_SVE_Zd_SVE_Pg3_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_SIZE_HSD::FMLS_SVE_Zd_SVE_Pg3_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_SIZE_HSD::FMSB_SVE_Zd_SVE_Pg3_SVE_Zm_5_SVE_Za_16(opcode) => opcode.bits(),
            SVE_SIZE_HSD::FMULX_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(opcode) => opcode.bits(),
            SVE_SIZE_HSD::FMUL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_I1_HALF_TWO(opcode) => opcode.bits(),
            SVE_SIZE_HSD::FMUL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(opcode) => opcode.bits(),
            SVE_SIZE_HSD::FMUL_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_SIZE_HSD::FNEG_SVE_Zd_SVE_Pg3_SVE_Zn(opcode) => opcode.bits(),
            SVE_SIZE_HSD::FNMAD_SVE_Zd_SVE_Pg3_SVE_Zm_5_SVE_Za_16(opcode) => opcode.bits(),
            SVE_SIZE_HSD::FNMLA_SVE_Zd_SVE_Pg3_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_SIZE_HSD::FNMLS_SVE_Zd_SVE_Pg3_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_SIZE_HSD::FNMSB_SVE_Zd_SVE_Pg3_SVE_Zm_5_SVE_Za_16(opcode) => opcode.bits(),
            SVE_SIZE_HSD::FRECPE_SVE_Zd_SVE_Zn(opcode) => opcode.bits(),
            SVE_SIZE_HSD::FRECPS_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_SIZE_HSD::FRECPX_SVE_Zd_SVE_Pg3_SVE_Zn(opcode) => opcode.bits(),
            SVE_SIZE_HSD::FRINTA_SVE_Zd_SVE_Pg3_SVE_Zn(opcode) => opcode.bits(),
            SVE_SIZE_HSD::FRINTI_SVE_Zd_SVE_Pg3_SVE_Zn(opcode) => opcode.bits(),
            SVE_SIZE_HSD::FRINTM_SVE_Zd_SVE_Pg3_SVE_Zn(opcode) => opcode.bits(),
            SVE_SIZE_HSD::FRINTN_SVE_Zd_SVE_Pg3_SVE_Zn(opcode) => opcode.bits(),
            SVE_SIZE_HSD::FRINTP_SVE_Zd_SVE_Pg3_SVE_Zn(opcode) => opcode.bits(),
            SVE_SIZE_HSD::FRINTX_SVE_Zd_SVE_Pg3_SVE_Zn(opcode) => opcode.bits(),
            SVE_SIZE_HSD::FRINTZ_SVE_Zd_SVE_Pg3_SVE_Zn(opcode) => opcode.bits(),
            SVE_SIZE_HSD::FRSQRTE_SVE_Zd_SVE_Zn(opcode) => opcode.bits(),
            SVE_SIZE_HSD::FRSQRTS_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_SIZE_HSD::FSCALE_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(opcode) => opcode.bits(),
            SVE_SIZE_HSD::FSQRT_SVE_Zd_SVE_Pg3_SVE_Zn(opcode) => opcode.bits(),
            SVE_SIZE_HSD::FSUBR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_I1_HALF_ONE(opcode) => opcode.bits(),
            SVE_SIZE_HSD::FSUBR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(opcode) => opcode.bits(),
            SVE_SIZE_HSD::FSUB_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_I1_HALF_ONE(opcode) => opcode.bits(),
            SVE_SIZE_HSD::FSUB_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(opcode) => opcode.bits(),
            SVE_SIZE_HSD::FSUB_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_SIZE_HSD::FTMAD_SVE_Zd_SVE_Zd_SVE_Zm_5_SVE_UIMM3(opcode) => opcode.bits(),
            SVE_SIZE_HSD::FTSMUL_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_SIZE_HSD::FTSSEL_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_SIZE_HSD::INCP_SVE_Zd_SVE_Pg4_5(opcode) => opcode.bits(),
            SVE_SIZE_HSD::RADDHNB_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_SIZE_HSD::RADDHNT_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_SIZE_HSD::REVB_SVE_Zd_SVE_Pg3_SVE_Zn(opcode) => opcode.bits(),
            SVE_SIZE_HSD::RSUBHNB_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_SIZE_HSD::RSUBHNT_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_SIZE_HSD::SABALB_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_SIZE_HSD::SABALT_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_SIZE_HSD::SABDLB_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_SIZE_HSD::SABDLT_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_SIZE_HSD::SADALP_SVE_Zd_SVE_Pg3_SVE_Zn(opcode) => opcode.bits(),
            SVE_SIZE_HSD::SADDLBT_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_SIZE_HSD::SADDLB_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_SIZE_HSD::SADDLT_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_SIZE_HSD::SADDWB_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_SIZE_HSD::SADDWT_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_SIZE_HSD::SMLALB_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_SIZE_HSD::SMLALT_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_SIZE_HSD::SMLSLB_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_SIZE_HSD::SMLSLT_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_SIZE_HSD::SMULLB_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_SIZE_HSD::SMULLT_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_SIZE_HSD::SQDECP_SVE_Zd_SVE_Pg4_5(opcode) => opcode.bits(),
            SVE_SIZE_HSD::SQDMLALBT_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_SIZE_HSD::SQDMLALB_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_SIZE_HSD::SQDMLALT_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_SIZE_HSD::SQDMLSLBT_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_SIZE_HSD::SQDMLSLB_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_SIZE_HSD::SQDMLSLT_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_SIZE_HSD::SQDMULLB_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_SIZE_HSD::SQDMULLT_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_SIZE_HSD::SQINCP_SVE_Zd_SVE_Pg4_5(opcode) => opcode.bits(),
            SVE_SIZE_HSD::SSUBLBT_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_SIZE_HSD::SSUBLB_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_SIZE_HSD::SSUBLTB_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_SIZE_HSD::SSUBLT_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_SIZE_HSD::SSUBWB_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_SIZE_HSD::SSUBWT_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_SIZE_HSD::SUBHNB_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_SIZE_HSD::SUBHNT_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_SIZE_HSD::SUNPKHI_SVE_Zd_SVE_Zn(opcode) => opcode.bits(),
            SVE_SIZE_HSD::SUNPKLO_SVE_Zd_SVE_Zn(opcode) => opcode.bits(),
            SVE_SIZE_HSD::SXTB_SVE_Zd_SVE_Pg3_SVE_Zn(opcode) => opcode.bits(),
            SVE_SIZE_HSD::UABALB_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_SIZE_HSD::UABALT_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_SIZE_HSD::UABDLB_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_SIZE_HSD::UABDLT_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_SIZE_HSD::UADALP_SVE_Zd_SVE_Pg3_SVE_Zn(opcode) => opcode.bits(),
            SVE_SIZE_HSD::UADDLB_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_SIZE_HSD::UADDLT_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_SIZE_HSD::UADDWB_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_SIZE_HSD::UADDWT_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_SIZE_HSD::UMLALB_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_SIZE_HSD::UMLALT_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_SIZE_HSD::UMLSLB_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_SIZE_HSD::UMLSLT_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_SIZE_HSD::UMULLB_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_SIZE_HSD::UMULLT_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_SIZE_HSD::UQDECP_SVE_Zd_SVE_Pg4_5(opcode) => opcode.bits(),
            SVE_SIZE_HSD::UQINCP_SVE_Zd_SVE_Pg4_5(opcode) => opcode.bits(),
            SVE_SIZE_HSD::USUBLB_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_SIZE_HSD::USUBLT_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_SIZE_HSD::USUBWB_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_SIZE_HSD::USUBWT_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_SIZE_HSD::UUNPKHI_SVE_Zd_SVE_Zn(opcode) => opcode.bits(),
            SVE_SIZE_HSD::UUNPKLO_SVE_Zd_SVE_Zn(opcode) => opcode.bits(),
            SVE_SIZE_HSD::UXTB_SVE_Zd_SVE_Pg3_SVE_Zn(opcode) => opcode.bits(),
        }
    }
}
impl InsnOpcode for FLOATCMP {
    fn definition(&self) -> &'static Insn {
        match self {
            FLOATCMP::FCMPE_Fn_FPIMM0(opcode) => opcode.definition(),
            FLOATCMP::FCMPE_Fn_Fm(opcode) => opcode.definition(),
            FLOATCMP::FCMPE_Fn_S_S_FPIMM0(opcode) => opcode.definition(),
            FLOATCMP::FCMPE_Fn_S_S_Fm_S_S(opcode) => opcode.definition(),
            FLOATCMP::FCMP_Fn_FPIMM0(opcode) => opcode.definition(),
            FLOATCMP::FCMP_Fn_Fm(opcode) => opcode.definition(),
            FLOATCMP::FCMP_Fn_S_S_FPIMM0(opcode) => opcode.definition(),
            FLOATCMP::FCMP_Fn_S_S_Fm_S_S(opcode) => opcode.definition(),
        }
    }
    fn bits(&self) -> u32 {
        match self {
            FLOATCMP::FCMPE_Fn_FPIMM0(opcode) => opcode.bits(),
            FLOATCMP::FCMPE_Fn_Fm(opcode) => opcode.bits(),
            FLOATCMP::FCMPE_Fn_S_S_FPIMM0(opcode) => opcode.bits(),
            FLOATCMP::FCMPE_Fn_S_S_Fm_S_S(opcode) => opcode.bits(),
            FLOATCMP::FCMP_Fn_FPIMM0(opcode) => opcode.bits(),
            FLOATCMP::FCMP_Fn_Fm(opcode) => opcode.bits(),
            FLOATCMP::FCMP_Fn_S_S_FPIMM0(opcode) => opcode.bits(),
            FLOATCMP::FCMP_Fn_S_S_Fm_S_S(opcode) => opcode.bits(),
        }
    }
}
impl InsnOpcode for LSE128_ATOMIC {
    fn definition(&self) -> &'static Insn {
        match self {
            LSE128_ATOMIC::LDCLRPAL_LSE128_Rt_LSE128_Rt2_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE128_ATOMIC::LDCLRPA_LSE128_Rt_LSE128_Rt2_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE128_ATOMIC::LDCLRPL_LSE128_Rt_LSE128_Rt2_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE128_ATOMIC::LDCLRP_LSE128_Rt_LSE128_Rt2_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE128_ATOMIC::LDSETPAL_LSE128_Rt_LSE128_Rt2_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE128_ATOMIC::LDSETPA_LSE128_Rt_LSE128_Rt2_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE128_ATOMIC::LDSETPL_LSE128_Rt_LSE128_Rt2_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE128_ATOMIC::LDSETP_LSE128_Rt_LSE128_Rt2_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE128_ATOMIC::SWPPAL_LSE128_Rt_LSE128_Rt2_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE128_ATOMIC::SWPPA_LSE128_Rt_LSE128_Rt2_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE128_ATOMIC::SWPPL_LSE128_Rt_LSE128_Rt2_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE128_ATOMIC::SWPP_LSE128_Rt_LSE128_Rt2_ADDR_SIMPLE(opcode) => opcode.definition(),
        }
    }
    fn bits(&self) -> u32 {
        match self {
            LSE128_ATOMIC::LDCLRPAL_LSE128_Rt_LSE128_Rt2_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE128_ATOMIC::LDCLRPA_LSE128_Rt_LSE128_Rt2_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE128_ATOMIC::LDCLRPL_LSE128_Rt_LSE128_Rt2_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE128_ATOMIC::LDCLRP_LSE128_Rt_LSE128_Rt2_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE128_ATOMIC::LDSETPAL_LSE128_Rt_LSE128_Rt2_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE128_ATOMIC::LDSETPA_LSE128_Rt_LSE128_Rt2_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE128_ATOMIC::LDSETPL_LSE128_Rt_LSE128_Rt2_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE128_ATOMIC::LDSETP_LSE128_Rt_LSE128_Rt2_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE128_ATOMIC::SWPPAL_LSE128_Rt_LSE128_Rt2_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE128_ATOMIC::SWPPA_LSE128_Rt_LSE128_Rt2_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE128_ATOMIC::SWPPL_LSE128_Rt_LSE128_Rt2_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE128_ATOMIC::SWPP_LSE128_Rt_LSE128_Rt2_ADDR_SIMPLE(opcode) => opcode.bits(),
        }
    }
}
impl InsnOpcode for CONDBRANCH {
    fn definition(&self) -> &'static Insn {
        match self {
            CONDBRANCH::BC__ADDR_PCREL19(opcode) => opcode.definition(),
            CONDBRANCH::B__ADDR_PCREL19(opcode) => opcode.definition(),
        }
    }
    fn bits(&self) -> u32 {
        match self {
            CONDBRANCH::BC__ADDR_PCREL19(opcode) => opcode.bits(),
            CONDBRANCH::B__ADDR_PCREL19(opcode) => opcode.bits(),
        }
    }
}
impl InsnOpcode for SVE_SIZE_SD2 {
    fn definition(&self) -> &'static Insn {
        match self {
            SVE_SIZE_SD2::LDNT1SB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZX(opcode) => opcode.definition(),
            SVE_SIZE_SD2::LDNT1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZX(opcode) => opcode.definition(),
        }
    }
    fn bits(&self) -> u32 {
        match self {
            SVE_SIZE_SD2::LDNT1SB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZX(opcode) => opcode.bits(),
            SVE_SIZE_SD2::LDNT1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZX(opcode) => opcode.bits(),
        }
    }
}
impl InsnOpcode for FLOATDP1 {
    fn definition(&self) -> &'static Insn {
        match self {
            FLOATDP1::FABS_Fd_Fn(opcode) => opcode.definition(),
            FLOATDP1::FABS_Fd_S_S_Fn_S_S(opcode) => opcode.definition(),
            FLOATDP1::FCVT_Fd_Fn(opcode) => opcode.definition(),
            FLOATDP1::FMOV_Fd_Fn(opcode) => opcode.definition(),
            FLOATDP1::FMOV_Fd_S_S_Fn_S_S(opcode) => opcode.definition(),
            FLOATDP1::FNEG_Fd_Fn(opcode) => opcode.definition(),
            FLOATDP1::FNEG_Fd_S_S_Fn_S_S(opcode) => opcode.definition(),
            FLOATDP1::FRINT32X_Fd_Fn(opcode) => opcode.definition(),
            FLOATDP1::FRINT32Z_Fd_Fn(opcode) => opcode.definition(),
            FLOATDP1::FRINT64X_Fd_Fn(opcode) => opcode.definition(),
            FLOATDP1::FRINT64Z_Fd_Fn(opcode) => opcode.definition(),
            FLOATDP1::FRINTA_Fd_Fn(opcode) => opcode.definition(),
            FLOATDP1::FRINTA_Fd_S_S_Fn_S_S(opcode) => opcode.definition(),
            FLOATDP1::FRINTI_Fd_Fn(opcode) => opcode.definition(),
            FLOATDP1::FRINTI_Fd_S_S_Fn_S_S(opcode) => opcode.definition(),
            FLOATDP1::FRINTM_Fd_Fn(opcode) => opcode.definition(),
            FLOATDP1::FRINTM_Fd_S_S_Fn_S_S(opcode) => opcode.definition(),
            FLOATDP1::FRINTN_Fd_Fn(opcode) => opcode.definition(),
            FLOATDP1::FRINTN_Fd_S_S_Fn_S_S(opcode) => opcode.definition(),
            FLOATDP1::FRINTP_Fd_Fn(opcode) => opcode.definition(),
            FLOATDP1::FRINTP_Fd_S_S_Fn_S_S(opcode) => opcode.definition(),
            FLOATDP1::FRINTX_Fd_Fn(opcode) => opcode.definition(),
            FLOATDP1::FRINTX_Fd_S_S_Fn_S_S(opcode) => opcode.definition(),
            FLOATDP1::FRINTZ_Fd_Fn(opcode) => opcode.definition(),
            FLOATDP1::FRINTZ_Fd_S_S_Fn_S_S(opcode) => opcode.definition(),
            FLOATDP1::FSQRT_Fd_Fn(opcode) => opcode.definition(),
            FLOATDP1::FSQRT_Fd_S_S_Fn_S_S(opcode) => opcode.definition(),
        }
    }
    fn bits(&self) -> u32 {
        match self {
            FLOATDP1::FABS_Fd_Fn(opcode) => opcode.bits(),
            FLOATDP1::FABS_Fd_S_S_Fn_S_S(opcode) => opcode.bits(),
            FLOATDP1::FCVT_Fd_Fn(opcode) => opcode.bits(),
            FLOATDP1::FMOV_Fd_Fn(opcode) => opcode.bits(),
            FLOATDP1::FMOV_Fd_S_S_Fn_S_S(opcode) => opcode.bits(),
            FLOATDP1::FNEG_Fd_Fn(opcode) => opcode.bits(),
            FLOATDP1::FNEG_Fd_S_S_Fn_S_S(opcode) => opcode.bits(),
            FLOATDP1::FRINT32X_Fd_Fn(opcode) => opcode.bits(),
            FLOATDP1::FRINT32Z_Fd_Fn(opcode) => opcode.bits(),
            FLOATDP1::FRINT64X_Fd_Fn(opcode) => opcode.bits(),
            FLOATDP1::FRINT64Z_Fd_Fn(opcode) => opcode.bits(),
            FLOATDP1::FRINTA_Fd_Fn(opcode) => opcode.bits(),
            FLOATDP1::FRINTA_Fd_S_S_Fn_S_S(opcode) => opcode.bits(),
            FLOATDP1::FRINTI_Fd_Fn(opcode) => opcode.bits(),
            FLOATDP1::FRINTI_Fd_S_S_Fn_S_S(opcode) => opcode.bits(),
            FLOATDP1::FRINTM_Fd_Fn(opcode) => opcode.bits(),
            FLOATDP1::FRINTM_Fd_S_S_Fn_S_S(opcode) => opcode.bits(),
            FLOATDP1::FRINTN_Fd_Fn(opcode) => opcode.bits(),
            FLOATDP1::FRINTN_Fd_S_S_Fn_S_S(opcode) => opcode.bits(),
            FLOATDP1::FRINTP_Fd_Fn(opcode) => opcode.bits(),
            FLOATDP1::FRINTP_Fd_S_S_Fn_S_S(opcode) => opcode.bits(),
            FLOATDP1::FRINTX_Fd_Fn(opcode) => opcode.bits(),
            FLOATDP1::FRINTX_Fd_S_S_Fn_S_S(opcode) => opcode.bits(),
            FLOATDP1::FRINTZ_Fd_Fn(opcode) => opcode.bits(),
            FLOATDP1::FRINTZ_Fd_S_S_Fn_S_S(opcode) => opcode.bits(),
            FLOATDP1::FSQRT_Fd_Fn(opcode) => opcode.bits(),
            FLOATDP1::FSQRT_Fd_S_S_Fn_S_S(opcode) => opcode.bits(),
        }
    }
}
impl InsnOpcode for PCRELADDR {
    fn definition(&self) -> &'static Insn {
        match self {
            PCRELADDR::ADRP_Rd_ADDR_ADRP(opcode) => opcode.definition(),
            PCRELADDR::ADR_Rd_ADDR_PCREL21(opcode) => opcode.definition(),
        }
    }
    fn bits(&self) -> u32 {
        match self {
            PCRELADDR::ADRP_Rd_ADDR_ADRP(opcode) => opcode.bits(),
            PCRELADDR::ADR_Rd_ADDR_PCREL21(opcode) => opcode.bits(),
        }
    }
}
impl InsnOpcode for BITFIELD {
    fn definition(&self) -> &'static Insn {
        match self {
            BITFIELD::BFM_Rd_Rn_IMMR_IMMS(opcode) => opcode.definition(),
            BITFIELD::SBFM_Rd_Rn_IMMR_IMMS(opcode) => opcode.definition(),
            BITFIELD::UBFM_Rd_Rn_IMMR_IMMS(opcode) => opcode.definition(),
        }
    }
    fn bits(&self) -> u32 {
        match self {
            BITFIELD::BFM_Rd_Rn_IMMR_IMMS(opcode) => opcode.bits(),
            BITFIELD::SBFM_Rd_Rn_IMMR_IMMS(opcode) => opcode.bits(),
            BITFIELD::UBFM_Rd_Rn_IMMR_IMMS(opcode) => opcode.bits(),
        }
    }
}
impl InsnOpcode for LOG_IMM {
    fn definition(&self) -> &'static Insn {
        match self {
            LOG_IMM::ANDS_Rd_Rn_LIMM(opcode) => opcode.definition(),
            LOG_IMM::AND_Rd_SP_Rn_LIMM(opcode) => opcode.definition(),
            LOG_IMM::EOR_Rd_SP_Rn_LIMM(opcode) => opcode.definition(),
            LOG_IMM::ORR_Rd_SP_Rn_LIMM(opcode) => opcode.definition(),
        }
    }
    fn bits(&self) -> u32 {
        match self {
            LOG_IMM::ANDS_Rd_Rn_LIMM(opcode) => opcode.bits(),
            LOG_IMM::AND_Rd_SP_Rn_LIMM(opcode) => opcode.bits(),
            LOG_IMM::EOR_Rd_SP_Rn_LIMM(opcode) => opcode.bits(),
            LOG_IMM::ORR_Rd_SP_Rn_LIMM(opcode) => opcode.bits(),
        }
    }
}
impl InsnOpcode for ASISDONE {
    fn definition(&self) -> &'static Insn {
        match self {
            ASISDONE::DUP_Sd_En(opcode) => opcode.definition(),
        }
    }
    fn bits(&self) -> u32 {
        match self {
            ASISDONE::DUP_Sd_En(opcode) => opcode.bits(),
        }
    }
}
impl InsnOpcode for CONDSEL {
    fn definition(&self) -> &'static Insn {
        match self {
            CONDSEL::CSEL_Rd_Rn_Rm_COND(opcode) => opcode.definition(),
            CONDSEL::CSINC_Rd_Rn_Rm_COND(opcode) => opcode.definition(),
            CONDSEL::CSINV_Rd_Rn_Rm_COND(opcode) => opcode.definition(),
            CONDSEL::CSNEG_Rd_Rn_Rm_COND(opcode) => opcode.definition(),
        }
    }
    fn bits(&self) -> u32 {
        match self {
            CONDSEL::CSEL_Rd_Rn_Rm_COND(opcode) => opcode.bits(),
            CONDSEL::CSINC_Rd_Rn_Rm_COND(opcode) => opcode.bits(),
            CONDSEL::CSINV_Rd_Rn_Rm_COND(opcode) => opcode.bits(),
            CONDSEL::CSNEG_Rd_Rn_Rm_COND(opcode) => opcode.bits(),
        }
    }
}
impl InsnOpcode for CONDCMP_REG {
    fn definition(&self) -> &'static Insn {
        match self {
            CONDCMP_REG::CCMN_Rn_Rm_NZCV_COND(opcode) => opcode.definition(),
            CONDCMP_REG::CCMP_Rn_Rm_NZCV_COND(opcode) => opcode.definition(),
        }
    }
    fn bits(&self) -> u32 {
        match self {
            CONDCMP_REG::CCMN_Rn_Rm_NZCV_COND(opcode) => opcode.bits(),
            CONDCMP_REG::CCMP_Rn_Rm_NZCV_COND(opcode) => opcode.bits(),
        }
    }
}
impl InsnOpcode for ASIMDELEM {
    fn definition(&self) -> &'static Insn {
        match self {
            ASIMDELEM::FCMLA_Vd_Vn_Em_IMM_ROT2(opcode) => opcode.definition(),
            ASIMDELEM::FMLAL2_Vd_V_4S_Vn_V_4H_Em16_S_H(opcode) => opcode.definition(),
            ASIMDELEM::FMLAL2_Vd_Vn_Em16(opcode) => opcode.definition(),
            ASIMDELEM::FMLAL_Vd_V_4S_Vn_V_4H_Em16_S_H(opcode) => opcode.definition(),
            ASIMDELEM::FMLAL_Vd_Vn_Em16(opcode) => opcode.definition(),
            ASIMDELEM::FMLA_Vd_Vn_Em(opcode) => opcode.definition(),
            ASIMDELEM::FMLA_Vd_Vn_Em16(opcode) => opcode.definition(),
            ASIMDELEM::FMLSL2_Vd_V_4S_Vn_V_4H_Em16_S_H(opcode) => opcode.definition(),
            ASIMDELEM::FMLSL2_Vd_Vn_Em16(opcode) => opcode.definition(),
            ASIMDELEM::FMLSL_Vd_V_4S_Vn_V_4H_Em16_S_H(opcode) => opcode.definition(),
            ASIMDELEM::FMLSL_Vd_Vn_Em16(opcode) => opcode.definition(),
            ASIMDELEM::FMLS_Vd_Vn_Em(opcode) => opcode.definition(),
            ASIMDELEM::FMLS_Vd_Vn_Em16(opcode) => opcode.definition(),
            ASIMDELEM::FMULX_Vd_Vn_Em(opcode) => opcode.definition(),
            ASIMDELEM::FMULX_Vd_Vn_Em16(opcode) => opcode.definition(),
            ASIMDELEM::FMUL_Vd_Vn_Em(opcode) => opcode.definition(),
            ASIMDELEM::FMUL_Vd_Vn_Em16(opcode) => opcode.definition(),
            ASIMDELEM::MLA_Vd_Vn_Em16(opcode) => opcode.definition(),
            ASIMDELEM::MLS_Vd_Vn_Em16(opcode) => opcode.definition(),
            ASIMDELEM::MUL_Vd_Vn_Em16(opcode) => opcode.definition(),
            ASIMDELEM::SMLAL2_Vd_Vn_Em16(opcode) => opcode.definition(),
            ASIMDELEM::SMLAL_Vd_Vn_Em16(opcode) => opcode.definition(),
            ASIMDELEM::SMLSL2_Vd_Vn_Em16(opcode) => opcode.definition(),
            ASIMDELEM::SMLSL_Vd_Vn_Em16(opcode) => opcode.definition(),
            ASIMDELEM::SMULL2_Vd_Vn_Em16(opcode) => opcode.definition(),
            ASIMDELEM::SMULL_Vd_Vn_Em16(opcode) => opcode.definition(),
            ASIMDELEM::SQDMLAL2_Vd_Vn_Em16(opcode) => opcode.definition(),
            ASIMDELEM::SQDMLAL_Vd_Vn_Em16(opcode) => opcode.definition(),
            ASIMDELEM::SQDMLSL2_Vd_Vn_Em16(opcode) => opcode.definition(),
            ASIMDELEM::SQDMLSL_Vd_Vn_Em16(opcode) => opcode.definition(),
            ASIMDELEM::SQDMULH_Vd_Vn_Em16(opcode) => opcode.definition(),
            ASIMDELEM::SQDMULL2_Vd_Vn_Em16(opcode) => opcode.definition(),
            ASIMDELEM::SQDMULL_Vd_Vn_Em16(opcode) => opcode.definition(),
            ASIMDELEM::SQRDMLAH_Vd_Vn_Em16(opcode) => opcode.definition(),
            ASIMDELEM::SQRDMLSH_Vd_Vn_Em16(opcode) => opcode.definition(),
            ASIMDELEM::SQRDMULH_Vd_Vn_Em16(opcode) => opcode.definition(),
            ASIMDELEM::UMLAL2_Vd_Vn_Em16(opcode) => opcode.definition(),
            ASIMDELEM::UMLAL_Vd_Vn_Em16(opcode) => opcode.definition(),
            ASIMDELEM::UMLSL2_Vd_Vn_Em16(opcode) => opcode.definition(),
            ASIMDELEM::UMLSL_Vd_Vn_Em16(opcode) => opcode.definition(),
            ASIMDELEM::UMULL2_Vd_Vn_Em16(opcode) => opcode.definition(),
            ASIMDELEM::UMULL_Vd_Vn_Em16(opcode) => opcode.definition(),
        }
    }
    fn bits(&self) -> u32 {
        match self {
            ASIMDELEM::FCMLA_Vd_Vn_Em_IMM_ROT2(opcode) => opcode.bits(),
            ASIMDELEM::FMLAL2_Vd_V_4S_Vn_V_4H_Em16_S_H(opcode) => opcode.bits(),
            ASIMDELEM::FMLAL2_Vd_Vn_Em16(opcode) => opcode.bits(),
            ASIMDELEM::FMLAL_Vd_V_4S_Vn_V_4H_Em16_S_H(opcode) => opcode.bits(),
            ASIMDELEM::FMLAL_Vd_Vn_Em16(opcode) => opcode.bits(),
            ASIMDELEM::FMLA_Vd_Vn_Em(opcode) => opcode.bits(),
            ASIMDELEM::FMLA_Vd_Vn_Em16(opcode) => opcode.bits(),
            ASIMDELEM::FMLSL2_Vd_V_4S_Vn_V_4H_Em16_S_H(opcode) => opcode.bits(),
            ASIMDELEM::FMLSL2_Vd_Vn_Em16(opcode) => opcode.bits(),
            ASIMDELEM::FMLSL_Vd_V_4S_Vn_V_4H_Em16_S_H(opcode) => opcode.bits(),
            ASIMDELEM::FMLSL_Vd_Vn_Em16(opcode) => opcode.bits(),
            ASIMDELEM::FMLS_Vd_Vn_Em(opcode) => opcode.bits(),
            ASIMDELEM::FMLS_Vd_Vn_Em16(opcode) => opcode.bits(),
            ASIMDELEM::FMULX_Vd_Vn_Em(opcode) => opcode.bits(),
            ASIMDELEM::FMULX_Vd_Vn_Em16(opcode) => opcode.bits(),
            ASIMDELEM::FMUL_Vd_Vn_Em(opcode) => opcode.bits(),
            ASIMDELEM::FMUL_Vd_Vn_Em16(opcode) => opcode.bits(),
            ASIMDELEM::MLA_Vd_Vn_Em16(opcode) => opcode.bits(),
            ASIMDELEM::MLS_Vd_Vn_Em16(opcode) => opcode.bits(),
            ASIMDELEM::MUL_Vd_Vn_Em16(opcode) => opcode.bits(),
            ASIMDELEM::SMLAL2_Vd_Vn_Em16(opcode) => opcode.bits(),
            ASIMDELEM::SMLAL_Vd_Vn_Em16(opcode) => opcode.bits(),
            ASIMDELEM::SMLSL2_Vd_Vn_Em16(opcode) => opcode.bits(),
            ASIMDELEM::SMLSL_Vd_Vn_Em16(opcode) => opcode.bits(),
            ASIMDELEM::SMULL2_Vd_Vn_Em16(opcode) => opcode.bits(),
            ASIMDELEM::SMULL_Vd_Vn_Em16(opcode) => opcode.bits(),
            ASIMDELEM::SQDMLAL2_Vd_Vn_Em16(opcode) => opcode.bits(),
            ASIMDELEM::SQDMLAL_Vd_Vn_Em16(opcode) => opcode.bits(),
            ASIMDELEM::SQDMLSL2_Vd_Vn_Em16(opcode) => opcode.bits(),
            ASIMDELEM::SQDMLSL_Vd_Vn_Em16(opcode) => opcode.bits(),
            ASIMDELEM::SQDMULH_Vd_Vn_Em16(opcode) => opcode.bits(),
            ASIMDELEM::SQDMULL2_Vd_Vn_Em16(opcode) => opcode.bits(),
            ASIMDELEM::SQDMULL_Vd_Vn_Em16(opcode) => opcode.bits(),
            ASIMDELEM::SQRDMLAH_Vd_Vn_Em16(opcode) => opcode.bits(),
            ASIMDELEM::SQRDMLSH_Vd_Vn_Em16(opcode) => opcode.bits(),
            ASIMDELEM::SQRDMULH_Vd_Vn_Em16(opcode) => opcode.bits(),
            ASIMDELEM::UMLAL2_Vd_Vn_Em16(opcode) => opcode.bits(),
            ASIMDELEM::UMLAL_Vd_Vn_Em16(opcode) => opcode.bits(),
            ASIMDELEM::UMLSL2_Vd_Vn_Em16(opcode) => opcode.bits(),
            ASIMDELEM::UMLSL_Vd_Vn_Em16(opcode) => opcode.bits(),
            ASIMDELEM::UMULL2_Vd_Vn_Em16(opcode) => opcode.bits(),
            ASIMDELEM::UMULL_Vd_Vn_Em16(opcode) => opcode.bits(),
        }
    }
}
impl InsnOpcode for ADDSUB_CARRY {
    fn definition(&self) -> &'static Insn {
        match self {
            ADDSUB_CARRY::ADCS_Rd_Rn_Rm(opcode) => opcode.definition(),
            ADDSUB_CARRY::ADC_Rd_Rn_Rm(opcode) => opcode.definition(),
            ADDSUB_CARRY::SBCS_Rd_Rn_Rm(opcode) => opcode.definition(),
            ADDSUB_CARRY::SBC_Rd_Rn_Rm(opcode) => opcode.definition(),
        }
    }
    fn bits(&self) -> u32 {
        match self {
            ADDSUB_CARRY::ADCS_Rd_Rn_Rm(opcode) => opcode.bits(),
            ADDSUB_CARRY::ADC_Rd_Rn_Rm(opcode) => opcode.bits(),
            ADDSUB_CARRY::SBCS_Rd_Rn_Rm(opcode) => opcode.bits(),
            ADDSUB_CARRY::SBC_Rd_Rn_Rm(opcode) => opcode.bits(),
        }
    }
}
impl InsnOpcode for SVE_SHIFT_TSZ_BHSD {
    fn definition(&self) -> &'static Insn {
        match self {
            SVE_SHIFT_TSZ_BHSD::SLI_SVE_Zd_SVE_Zn_SVE_SHLIMM_UNPRED(opcode) => opcode.definition(),
            SVE_SHIFT_TSZ_BHSD::SRI_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED(opcode) => opcode.definition(),
            SVE_SHIFT_TSZ_BHSD::SRSRA_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED(opcode) => {
                opcode.definition()
            }
            SVE_SHIFT_TSZ_BHSD::SSRA_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED(opcode) => opcode.definition(),
            SVE_SHIFT_TSZ_BHSD::URSRA_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED(opcode) => {
                opcode.definition()
            }
            SVE_SHIFT_TSZ_BHSD::USRA_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED(opcode) => opcode.definition(),
            SVE_SHIFT_TSZ_BHSD::XAR_SVE_Zd_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED(opcode) => {
                opcode.definition()
            }
        }
    }
    fn bits(&self) -> u32 {
        match self {
            SVE_SHIFT_TSZ_BHSD::SLI_SVE_Zd_SVE_Zn_SVE_SHLIMM_UNPRED(opcode) => opcode.bits(),
            SVE_SHIFT_TSZ_BHSD::SRI_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED(opcode) => opcode.bits(),
            SVE_SHIFT_TSZ_BHSD::SRSRA_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED(opcode) => opcode.bits(),
            SVE_SHIFT_TSZ_BHSD::SSRA_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED(opcode) => opcode.bits(),
            SVE_SHIFT_TSZ_BHSD::URSRA_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED(opcode) => opcode.bits(),
            SVE_SHIFT_TSZ_BHSD::USRA_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED(opcode) => opcode.bits(),
            SVE_SHIFT_TSZ_BHSD::XAR_SVE_Zd_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED(opcode) => opcode.bits(),
        }
    }
}
impl InsnOpcode for CRYPTOSM4 {
    fn definition(&self) -> &'static Insn {
        match self {
            CRYPTOSM4::SM4EKEY_Vd_Vn_Vm(opcode) => opcode.definition(),
            CRYPTOSM4::SM4E_Vd_Vn(opcode) => opcode.definition(),
        }
    }
    fn bits(&self) -> u32 {
        match self {
            CRYPTOSM4::SM4EKEY_Vd_Vn_Vm(opcode) => opcode.bits(),
            CRYPTOSM4::SM4E_Vd_Vn(opcode) => opcode.bits(),
        }
    }
}
impl InsnOpcode for SME_SHIFT {
    fn definition(&self) -> &'static Insn {
        match self {
            SME_SHIFT::SQRSHRN_SVE_Zd_SME_Znx4_SME_SHRIMM5(opcode) => opcode.definition(),
            SME_SHIFT::SQRSHRUN_SVE_Zd_SME_Znx4_SME_SHRIMM5(opcode) => opcode.definition(),
            SME_SHIFT::SQRSHRU_SVE_Zd_SME_Znx4_SME_SHRIMM5(opcode) => opcode.definition(),
            SME_SHIFT::SQRSHR_SVE_Zd_SME_Znx4_SME_SHRIMM5(opcode) => opcode.definition(),
            SME_SHIFT::UQRSHRN_SVE_Zd_SME_Znx4_SME_SHRIMM5(opcode) => opcode.definition(),
            SME_SHIFT::UQRSHR_SVE_Zd_SME_Znx4_SME_SHRIMM5(opcode) => opcode.definition(),
        }
    }
    fn bits(&self) -> u32 {
        match self {
            SME_SHIFT::SQRSHRN_SVE_Zd_SME_Znx4_SME_SHRIMM5(opcode) => opcode.bits(),
            SME_SHIFT::SQRSHRUN_SVE_Zd_SME_Znx4_SME_SHRIMM5(opcode) => opcode.bits(),
            SME_SHIFT::SQRSHRU_SVE_Zd_SME_Znx4_SME_SHRIMM5(opcode) => opcode.bits(),
            SME_SHIFT::SQRSHR_SVE_Zd_SME_Znx4_SME_SHRIMM5(opcode) => opcode.bits(),
            SME_SHIFT::UQRSHRN_SVE_Zd_SME_Znx4_SME_SHRIMM5(opcode) => opcode.bits(),
            SME_SHIFT::UQRSHR_SVE_Zd_SME_Znx4_SME_SHRIMM5(opcode) => opcode.bits(),
        }
    }
}
impl InsnOpcode for ASIMDEXT {
    fn definition(&self) -> &'static Insn {
        match self {
            ASIMDEXT::EXT_Vd_Vn_Vm_IDX(opcode) => opcode.definition(),
        }
    }
    fn bits(&self) -> u32 {
        match self {
            ASIMDEXT::EXT_Vd_Vn_Vm_IDX(opcode) => opcode.bits(),
        }
    }
}
impl InsnOpcode for CRYPTOSM3 {
    fn definition(&self) -> &'static Insn {
        match self {
            CRYPTOSM3::SM3PARTW1_Vd_Vn_Vm(opcode) => opcode.definition(),
            CRYPTOSM3::SM3PARTW2_Vd_Vn_Vm(opcode) => opcode.definition(),
            CRYPTOSM3::SM3SS1_Vd_Vn_Vm_Va(opcode) => opcode.definition(),
            CRYPTOSM3::SM3TT1A_Vd_Vn_Em(opcode) => opcode.definition(),
            CRYPTOSM3::SM3TT1B_Vd_Vn_Em(opcode) => opcode.definition(),
            CRYPTOSM3::SM3TT2A_Vd_Vn_Em(opcode) => opcode.definition(),
            CRYPTOSM3::SM3TT2B_Vd_Vn_Em(opcode) => opcode.definition(),
        }
    }
    fn bits(&self) -> u32 {
        match self {
            CRYPTOSM3::SM3PARTW1_Vd_Vn_Vm(opcode) => opcode.bits(),
            CRYPTOSM3::SM3PARTW2_Vd_Vn_Vm(opcode) => opcode.bits(),
            CRYPTOSM3::SM3SS1_Vd_Vn_Vm_Va(opcode) => opcode.bits(),
            CRYPTOSM3::SM3TT1A_Vd_Vn_Em(opcode) => opcode.bits(),
            CRYPTOSM3::SM3TT1B_Vd_Vn_Em(opcode) => opcode.bits(),
            CRYPTOSM3::SM3TT2A_Vd_Vn_Em(opcode) => opcode.bits(),
            CRYPTOSM3::SM3TT2B_Vd_Vn_Em(opcode) => opcode.bits(),
        }
    }
}
impl InsnOpcode for ASISDELEM {
    fn definition(&self) -> &'static Insn {
        match self {
            ASISDELEM::FMLA_Sd_Sn_Em(opcode) => opcode.definition(),
            ASISDELEM::FMLA_Sd_Sn_Em16(opcode) => opcode.definition(),
            ASISDELEM::FMLS_Sd_Sn_Em(opcode) => opcode.definition(),
            ASISDELEM::FMLS_Sd_Sn_Em16(opcode) => opcode.definition(),
            ASISDELEM::FMULX_Sd_Sn_Em(opcode) => opcode.definition(),
            ASISDELEM::FMULX_Sd_Sn_Em16(opcode) => opcode.definition(),
            ASISDELEM::FMUL_Sd_Sn_Em(opcode) => opcode.definition(),
            ASISDELEM::FMUL_Sd_Sn_Em16(opcode) => opcode.definition(),
            ASISDELEM::SQDMLAL_Sd_Sn_Em16(opcode) => opcode.definition(),
            ASISDELEM::SQDMLSL_Sd_Sn_Em16(opcode) => opcode.definition(),
            ASISDELEM::SQDMULH_Sd_Sn_Em16(opcode) => opcode.definition(),
            ASISDELEM::SQDMULL_Sd_Sn_Em16(opcode) => opcode.definition(),
            ASISDELEM::SQRDMLAH_Sd_Sn_Em16(opcode) => opcode.definition(),
            ASISDELEM::SQRDMLSH_Sd_Sn_Em16(opcode) => opcode.definition(),
            ASISDELEM::SQRDMULH_Sd_Sn_Em16(opcode) => opcode.definition(),
        }
    }
    fn bits(&self) -> u32 {
        match self {
            ASISDELEM::FMLA_Sd_Sn_Em(opcode) => opcode.bits(),
            ASISDELEM::FMLA_Sd_Sn_Em16(opcode) => opcode.bits(),
            ASISDELEM::FMLS_Sd_Sn_Em(opcode) => opcode.bits(),
            ASISDELEM::FMLS_Sd_Sn_Em16(opcode) => opcode.bits(),
            ASISDELEM::FMULX_Sd_Sn_Em(opcode) => opcode.bits(),
            ASISDELEM::FMULX_Sd_Sn_Em16(opcode) => opcode.bits(),
            ASISDELEM::FMUL_Sd_Sn_Em(opcode) => opcode.bits(),
            ASISDELEM::FMUL_Sd_Sn_Em16(opcode) => opcode.bits(),
            ASISDELEM::SQDMLAL_Sd_Sn_Em16(opcode) => opcode.bits(),
            ASISDELEM::SQDMLSL_Sd_Sn_Em16(opcode) => opcode.bits(),
            ASISDELEM::SQDMULH_Sd_Sn_Em16(opcode) => opcode.bits(),
            ASISDELEM::SQDMULL_Sd_Sn_Em16(opcode) => opcode.bits(),
            ASISDELEM::SQRDMLAH_Sd_Sn_Em16(opcode) => opcode.bits(),
            ASISDELEM::SQRDMLSH_Sd_Sn_Em16(opcode) => opcode.bits(),
            ASISDELEM::SQRDMULH_Sd_Sn_Em16(opcode) => opcode.bits(),
        }
    }
}
impl InsnOpcode for LSE_ATOMIC {
    fn definition(&self) -> &'static Insn {
        match self {
            LSE_ATOMIC::CASAB_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE_ATOMIC::CASAH_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE_ATOMIC::CASALB_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE_ATOMIC::CASALH_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE_ATOMIC::CASAL_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE_ATOMIC::CASA_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE_ATOMIC::CASB_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE_ATOMIC::CASH_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE_ATOMIC::CASLB_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE_ATOMIC::CASLH_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE_ATOMIC::CASL_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE_ATOMIC::CASPAL_Rs_PAIRREG_Rt_PAIRREG_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE_ATOMIC::CASPA_Rs_PAIRREG_Rt_PAIRREG_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE_ATOMIC::CASPL_Rs_PAIRREG_Rt_PAIRREG_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE_ATOMIC::CASP_Rs_PAIRREG_Rt_PAIRREG_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE_ATOMIC::CAS_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE_ATOMIC::LD64B_Rt_LS64_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE_ATOMIC::LDADDAB_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE_ATOMIC::LDADDAH_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE_ATOMIC::LDADDALB_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE_ATOMIC::LDADDALH_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE_ATOMIC::LDADDAL_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE_ATOMIC::LDADDA_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE_ATOMIC::LDADDB_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE_ATOMIC::LDADDH_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE_ATOMIC::LDADDLB_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE_ATOMIC::LDADDLH_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE_ATOMIC::LDADDL_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE_ATOMIC::LDADD_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE_ATOMIC::LDCLRAB_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE_ATOMIC::LDCLRAH_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE_ATOMIC::LDCLRALB_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE_ATOMIC::LDCLRALH_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE_ATOMIC::LDCLRAL_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE_ATOMIC::LDCLRA_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE_ATOMIC::LDCLRB_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE_ATOMIC::LDCLRH_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE_ATOMIC::LDCLRLB_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE_ATOMIC::LDCLRLH_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE_ATOMIC::LDCLRL_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE_ATOMIC::LDCLR_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE_ATOMIC::LDEORAB_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE_ATOMIC::LDEORAH_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE_ATOMIC::LDEORALB_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE_ATOMIC::LDEORALH_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE_ATOMIC::LDEORAL_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE_ATOMIC::LDEORA_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE_ATOMIC::LDEORB_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE_ATOMIC::LDEORH_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE_ATOMIC::LDEORLB_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE_ATOMIC::LDEORLH_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE_ATOMIC::LDEORL_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE_ATOMIC::LDEOR_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE_ATOMIC::LDSETAB_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE_ATOMIC::LDSETAH_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE_ATOMIC::LDSETALB_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE_ATOMIC::LDSETALH_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE_ATOMIC::LDSETAL_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE_ATOMIC::LDSETA_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE_ATOMIC::LDSETB_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE_ATOMIC::LDSETH_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE_ATOMIC::LDSETLB_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE_ATOMIC::LDSETLH_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE_ATOMIC::LDSETL_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE_ATOMIC::LDSET_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE_ATOMIC::LDSMAXAB_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE_ATOMIC::LDSMAXAH_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE_ATOMIC::LDSMAXALB_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE_ATOMIC::LDSMAXALH_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE_ATOMIC::LDSMAXAL_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE_ATOMIC::LDSMAXA_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE_ATOMIC::LDSMAXB_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE_ATOMIC::LDSMAXH_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE_ATOMIC::LDSMAXLB_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE_ATOMIC::LDSMAXLH_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE_ATOMIC::LDSMAXL_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE_ATOMIC::LDSMAX_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE_ATOMIC::LDSMINAB_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE_ATOMIC::LDSMINAH_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE_ATOMIC::LDSMINALB_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE_ATOMIC::LDSMINALH_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE_ATOMIC::LDSMINAL_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE_ATOMIC::LDSMINA_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE_ATOMIC::LDSMINB_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE_ATOMIC::LDSMINH_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE_ATOMIC::LDSMINLB_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE_ATOMIC::LDSMINLH_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE_ATOMIC::LDSMINL_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE_ATOMIC::LDSMIN_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE_ATOMIC::LDUMAXAB_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE_ATOMIC::LDUMAXAH_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE_ATOMIC::LDUMAXALB_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE_ATOMIC::LDUMAXALH_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE_ATOMIC::LDUMAXAL_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE_ATOMIC::LDUMAXA_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE_ATOMIC::LDUMAXB_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE_ATOMIC::LDUMAXH_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE_ATOMIC::LDUMAXLB_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE_ATOMIC::LDUMAXLH_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE_ATOMIC::LDUMAXL_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE_ATOMIC::LDUMAX_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE_ATOMIC::LDUMINAB_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE_ATOMIC::LDUMINAH_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE_ATOMIC::LDUMINALB_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE_ATOMIC::LDUMINALH_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE_ATOMIC::LDUMINAL_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE_ATOMIC::LDUMINA_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE_ATOMIC::LDUMINB_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE_ATOMIC::LDUMINH_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE_ATOMIC::LDUMINLB_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE_ATOMIC::LDUMINLH_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE_ATOMIC::LDUMINL_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE_ATOMIC::LDUMIN_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE_ATOMIC::ST64BV0_Rs_Rt_LS64_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE_ATOMIC::ST64BV_Rs_Rt_LS64_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE_ATOMIC::ST64B_Rt_LS64_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE_ATOMIC::SWPAB_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE_ATOMIC::SWPAH_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE_ATOMIC::SWPALB_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE_ATOMIC::SWPALH_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE_ATOMIC::SWPAL_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE_ATOMIC::SWPA_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE_ATOMIC::SWPB_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE_ATOMIC::SWPH_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE_ATOMIC::SWPLB_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE_ATOMIC::SWPLH_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE_ATOMIC::SWPL_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LSE_ATOMIC::SWP_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
        }
    }
    fn bits(&self) -> u32 {
        match self {
            LSE_ATOMIC::CASAB_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE_ATOMIC::CASAH_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE_ATOMIC::CASALB_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE_ATOMIC::CASALH_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE_ATOMIC::CASAL_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE_ATOMIC::CASA_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE_ATOMIC::CASB_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE_ATOMIC::CASH_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE_ATOMIC::CASLB_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE_ATOMIC::CASLH_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE_ATOMIC::CASL_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE_ATOMIC::CASPAL_Rs_PAIRREG_Rt_PAIRREG_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE_ATOMIC::CASPA_Rs_PAIRREG_Rt_PAIRREG_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE_ATOMIC::CASPL_Rs_PAIRREG_Rt_PAIRREG_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE_ATOMIC::CASP_Rs_PAIRREG_Rt_PAIRREG_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE_ATOMIC::CAS_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE_ATOMIC::LD64B_Rt_LS64_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE_ATOMIC::LDADDAB_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE_ATOMIC::LDADDAH_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE_ATOMIC::LDADDALB_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE_ATOMIC::LDADDALH_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE_ATOMIC::LDADDAL_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE_ATOMIC::LDADDA_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE_ATOMIC::LDADDB_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE_ATOMIC::LDADDH_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE_ATOMIC::LDADDLB_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE_ATOMIC::LDADDLH_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE_ATOMIC::LDADDL_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE_ATOMIC::LDADD_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE_ATOMIC::LDCLRAB_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE_ATOMIC::LDCLRAH_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE_ATOMIC::LDCLRALB_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE_ATOMIC::LDCLRALH_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE_ATOMIC::LDCLRAL_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE_ATOMIC::LDCLRA_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE_ATOMIC::LDCLRB_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE_ATOMIC::LDCLRH_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE_ATOMIC::LDCLRLB_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE_ATOMIC::LDCLRLH_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE_ATOMIC::LDCLRL_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE_ATOMIC::LDCLR_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE_ATOMIC::LDEORAB_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE_ATOMIC::LDEORAH_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE_ATOMIC::LDEORALB_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE_ATOMIC::LDEORALH_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE_ATOMIC::LDEORAL_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE_ATOMIC::LDEORA_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE_ATOMIC::LDEORB_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE_ATOMIC::LDEORH_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE_ATOMIC::LDEORLB_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE_ATOMIC::LDEORLH_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE_ATOMIC::LDEORL_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE_ATOMIC::LDEOR_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE_ATOMIC::LDSETAB_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE_ATOMIC::LDSETAH_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE_ATOMIC::LDSETALB_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE_ATOMIC::LDSETALH_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE_ATOMIC::LDSETAL_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE_ATOMIC::LDSETA_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE_ATOMIC::LDSETB_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE_ATOMIC::LDSETH_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE_ATOMIC::LDSETLB_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE_ATOMIC::LDSETLH_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE_ATOMIC::LDSETL_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE_ATOMIC::LDSET_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE_ATOMIC::LDSMAXAB_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE_ATOMIC::LDSMAXAH_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE_ATOMIC::LDSMAXALB_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE_ATOMIC::LDSMAXALH_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE_ATOMIC::LDSMAXAL_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE_ATOMIC::LDSMAXA_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE_ATOMIC::LDSMAXB_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE_ATOMIC::LDSMAXH_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE_ATOMIC::LDSMAXLB_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE_ATOMIC::LDSMAXLH_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE_ATOMIC::LDSMAXL_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE_ATOMIC::LDSMAX_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE_ATOMIC::LDSMINAB_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE_ATOMIC::LDSMINAH_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE_ATOMIC::LDSMINALB_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE_ATOMIC::LDSMINALH_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE_ATOMIC::LDSMINAL_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE_ATOMIC::LDSMINA_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE_ATOMIC::LDSMINB_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE_ATOMIC::LDSMINH_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE_ATOMIC::LDSMINLB_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE_ATOMIC::LDSMINLH_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE_ATOMIC::LDSMINL_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE_ATOMIC::LDSMIN_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE_ATOMIC::LDUMAXAB_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE_ATOMIC::LDUMAXAH_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE_ATOMIC::LDUMAXALB_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE_ATOMIC::LDUMAXALH_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE_ATOMIC::LDUMAXAL_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE_ATOMIC::LDUMAXA_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE_ATOMIC::LDUMAXB_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE_ATOMIC::LDUMAXH_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE_ATOMIC::LDUMAXLB_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE_ATOMIC::LDUMAXLH_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE_ATOMIC::LDUMAXL_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE_ATOMIC::LDUMAX_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE_ATOMIC::LDUMINAB_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE_ATOMIC::LDUMINAH_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE_ATOMIC::LDUMINALB_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE_ATOMIC::LDUMINALH_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE_ATOMIC::LDUMINAL_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE_ATOMIC::LDUMINA_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE_ATOMIC::LDUMINB_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE_ATOMIC::LDUMINH_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE_ATOMIC::LDUMINLB_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE_ATOMIC::LDUMINLH_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE_ATOMIC::LDUMINL_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE_ATOMIC::LDUMIN_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE_ATOMIC::ST64BV0_Rs_Rt_LS64_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE_ATOMIC::ST64BV_Rs_Rt_LS64_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE_ATOMIC::ST64B_Rt_LS64_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE_ATOMIC::SWPAB_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE_ATOMIC::SWPAH_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE_ATOMIC::SWPALB_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE_ATOMIC::SWPALH_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE_ATOMIC::SWPAL_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE_ATOMIC::SWPA_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE_ATOMIC::SWPB_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE_ATOMIC::SWPH_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE_ATOMIC::SWPLB_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE_ATOMIC::SWPLH_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE_ATOMIC::SWPL_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LSE_ATOMIC::SWP_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
        }
    }
}
impl InsnOpcode for ASIMDPERM {
    fn definition(&self) -> &'static Insn {
        match self {
            ASIMDPERM::TRN1_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDPERM::TRN2_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDPERM::UZP1_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDPERM::UZP2_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDPERM::ZIP1_Vd_Vn_Vm(opcode) => opcode.definition(),
            ASIMDPERM::ZIP2_Vd_Vn_Vm(opcode) => opcode.definition(),
        }
    }
    fn bits(&self) -> u32 {
        match self {
            ASIMDPERM::TRN1_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDPERM::TRN2_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDPERM::UZP1_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDPERM::UZP2_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDPERM::ZIP1_Vd_Vn_Vm(opcode) => opcode.bits(),
            ASIMDPERM::ZIP2_Vd_Vn_Vm(opcode) => opcode.bits(),
        }
    }
}
impl InsnOpcode for LDSTNAPAIR_OFFS {
    fn definition(&self) -> &'static Insn {
        match self {
            LDSTNAPAIR_OFFS::LDNP_Ft_Ft2_ADDR_SIMM7(opcode) => opcode.definition(),
            LDSTNAPAIR_OFFS::LDNP_Rt_Rt2_ADDR_SIMM7(opcode) => opcode.definition(),
            LDSTNAPAIR_OFFS::STNP_Ft_Ft2_ADDR_SIMM7(opcode) => opcode.definition(),
            LDSTNAPAIR_OFFS::STNP_Rt_Rt2_ADDR_SIMM7(opcode) => opcode.definition(),
        }
    }
    fn bits(&self) -> u32 {
        match self {
            LDSTNAPAIR_OFFS::LDNP_Ft_Ft2_ADDR_SIMM7(opcode) => opcode.bits(),
            LDSTNAPAIR_OFFS::LDNP_Rt_Rt2_ADDR_SIMM7(opcode) => opcode.bits(),
            LDSTNAPAIR_OFFS::STNP_Ft_Ft2_ADDR_SIMM7(opcode) => opcode.bits(),
            LDSTNAPAIR_OFFS::STNP_Rt_Rt2_ADDR_SIMM7(opcode) => opcode.bits(),
        }
    }
}
impl InsnOpcode for CSSC {
    fn definition(&self) -> &'static Insn {
        match self {
            CSSC::ABS_Rd_Rn(opcode) => opcode.definition(),
            CSSC::CNT_Rd_Rn(opcode) => opcode.definition(),
            CSSC::CTZ_Rd_Rn(opcode) => opcode.definition(),
            CSSC::SMAX_Rd_Rn_CSSC_SIMM8(opcode) => opcode.definition(),
            CSSC::SMAX_Rd_Rn_Rm(opcode) => opcode.definition(),
            CSSC::SMIN_Rd_Rn_CSSC_SIMM8(opcode) => opcode.definition(),
            CSSC::SMIN_Rd_Rn_Rm(opcode) => opcode.definition(),
            CSSC::UMAX_Rd_Rn_CSSC_UIMM8(opcode) => opcode.definition(),
            CSSC::UMAX_Rd_Rn_Rm(opcode) => opcode.definition(),
            CSSC::UMIN_Rd_Rn_CSSC_UIMM8(opcode) => opcode.definition(),
            CSSC::UMIN_Rd_Rn_Rm(opcode) => opcode.definition(),
        }
    }
    fn bits(&self) -> u32 {
        match self {
            CSSC::ABS_Rd_Rn(opcode) => opcode.bits(),
            CSSC::CNT_Rd_Rn(opcode) => opcode.bits(),
            CSSC::CTZ_Rd_Rn(opcode) => opcode.bits(),
            CSSC::SMAX_Rd_Rn_CSSC_SIMM8(opcode) => opcode.bits(),
            CSSC::SMAX_Rd_Rn_Rm(opcode) => opcode.bits(),
            CSSC::SMIN_Rd_Rn_CSSC_SIMM8(opcode) => opcode.bits(),
            CSSC::SMIN_Rd_Rn_Rm(opcode) => opcode.bits(),
            CSSC::UMAX_Rd_Rn_CSSC_UIMM8(opcode) => opcode.bits(),
            CSSC::UMAX_Rd_Rn_Rm(opcode) => opcode.bits(),
            CSSC::UMIN_Rd_Rn_CSSC_UIMM8(opcode) => opcode.bits(),
            CSSC::UMIN_Rd_Rn_Rm(opcode) => opcode.bits(),
        }
    }
}
impl InsnOpcode for CRYPTOSHA2 {
    fn definition(&self) -> &'static Insn {
        match self {
            CRYPTOSHA2::SHA1H_Fd_Fn(opcode) => opcode.definition(),
            CRYPTOSHA2::SHA1SU1_Vd_Vn(opcode) => opcode.definition(),
            CRYPTOSHA2::SHA256SU0_Vd_Vn(opcode) => opcode.definition(),
            CRYPTOSHA2::SHA512H2_Fd_Fn_Vm(opcode) => opcode.definition(),
            CRYPTOSHA2::SHA512H_Fd_Fn_Vm(opcode) => opcode.definition(),
            CRYPTOSHA2::SHA512SU0_Vd_Vn(opcode) => opcode.definition(),
            CRYPTOSHA2::SHA512SU1_Vd_Vn_Vm(opcode) => opcode.definition(),
        }
    }
    fn bits(&self) -> u32 {
        match self {
            CRYPTOSHA2::SHA1H_Fd_Fn(opcode) => opcode.bits(),
            CRYPTOSHA2::SHA1SU1_Vd_Vn(opcode) => opcode.bits(),
            CRYPTOSHA2::SHA256SU0_Vd_Vn(opcode) => opcode.bits(),
            CRYPTOSHA2::SHA512H2_Fd_Fn_Vm(opcode) => opcode.bits(),
            CRYPTOSHA2::SHA512H_Fd_Fn_Vm(opcode) => opcode.bits(),
            CRYPTOSHA2::SHA512SU0_Vd_Vn(opcode) => opcode.bits(),
            CRYPTOSHA2::SHA512SU1_Vd_Vn_Vm(opcode) => opcode.bits(),
        }
    }
}
impl InsnOpcode for MOVEWIDE {
    fn definition(&self) -> &'static Insn {
        match self {
            MOVEWIDE::MOVK_Rd_HALF(opcode) => opcode.definition(),
            MOVEWIDE::MOVN_Rd_HALF(opcode) => opcode.definition(),
            MOVEWIDE::MOVZ_Rd_HALF(opcode) => opcode.definition(),
        }
    }
    fn bits(&self) -> u32 {
        match self {
            MOVEWIDE::MOVK_Rd_HALF(opcode) => opcode.bits(),
            MOVEWIDE::MOVN_Rd_HALF(opcode) => opcode.bits(),
            MOVEWIDE::MOVZ_Rd_HALF(opcode) => opcode.bits(),
        }
    }
}
impl InsnOpcode for ASISDLSOP {
    fn definition(&self) -> &'static Insn {
        match self {
            ASISDLSOP::LD1R_LVt_AL_SIMD_ADDR_POST(opcode) => opcode.definition(),
            ASISDLSOP::LD1_LEt_SIMD_ADDR_POST(opcode) => opcode.definition(),
            ASISDLSOP::LD2R_LVt_AL_SIMD_ADDR_POST(opcode) => opcode.definition(),
            ASISDLSOP::LD2_LEt_SIMD_ADDR_POST(opcode) => opcode.definition(),
            ASISDLSOP::LD3R_LVt_AL_SIMD_ADDR_POST(opcode) => opcode.definition(),
            ASISDLSOP::LD3_LEt_SIMD_ADDR_POST(opcode) => opcode.definition(),
            ASISDLSOP::LD4R_LVt_AL_SIMD_ADDR_POST(opcode) => opcode.definition(),
            ASISDLSOP::LD4_LEt_SIMD_ADDR_POST(opcode) => opcode.definition(),
            ASISDLSOP::ST1_LEt_SIMD_ADDR_POST(opcode) => opcode.definition(),
            ASISDLSOP::ST2_LEt_SIMD_ADDR_POST(opcode) => opcode.definition(),
            ASISDLSOP::ST3_LEt_SIMD_ADDR_POST(opcode) => opcode.definition(),
            ASISDLSOP::ST4_LEt_SIMD_ADDR_POST(opcode) => opcode.definition(),
        }
    }
    fn bits(&self) -> u32 {
        match self {
            ASISDLSOP::LD1R_LVt_AL_SIMD_ADDR_POST(opcode) => opcode.bits(),
            ASISDLSOP::LD1_LEt_SIMD_ADDR_POST(opcode) => opcode.bits(),
            ASISDLSOP::LD2R_LVt_AL_SIMD_ADDR_POST(opcode) => opcode.bits(),
            ASISDLSOP::LD2_LEt_SIMD_ADDR_POST(opcode) => opcode.bits(),
            ASISDLSOP::LD3R_LVt_AL_SIMD_ADDR_POST(opcode) => opcode.bits(),
            ASISDLSOP::LD3_LEt_SIMD_ADDR_POST(opcode) => opcode.bits(),
            ASISDLSOP::LD4R_LVt_AL_SIMD_ADDR_POST(opcode) => opcode.bits(),
            ASISDLSOP::LD4_LEt_SIMD_ADDR_POST(opcode) => opcode.bits(),
            ASISDLSOP::ST1_LEt_SIMD_ADDR_POST(opcode) => opcode.bits(),
            ASISDLSOP::ST2_LEt_SIMD_ADDR_POST(opcode) => opcode.bits(),
            ASISDLSOP::ST3_LEt_SIMD_ADDR_POST(opcode) => opcode.bits(),
            ASISDLSOP::ST4_LEt_SIMD_ADDR_POST(opcode) => opcode.bits(),
        }
    }
}
impl InsnOpcode for ASIMDALL {
    fn definition(&self) -> &'static Insn {
        match self {
            ASIMDALL::ADDV_Fd_Vn(opcode) => opcode.definition(),
            ASIMDALL::FMAXNMV_Fd_S_S_Vn_V_4S(opcode) => opcode.definition(),
            ASIMDALL::FMAXNMV_Fd_Vn(opcode) => opcode.definition(),
            ASIMDALL::FMAXV_Fd_S_S_Vn_V_4S(opcode) => opcode.definition(),
            ASIMDALL::FMAXV_Fd_Vn(opcode) => opcode.definition(),
            ASIMDALL::FMINNMV_Fd_S_S_Vn_V_4S(opcode) => opcode.definition(),
            ASIMDALL::FMINNMV_Fd_Vn(opcode) => opcode.definition(),
            ASIMDALL::FMINV_Fd_S_S_Vn_V_4S(opcode) => opcode.definition(),
            ASIMDALL::FMINV_Fd_Vn(opcode) => opcode.definition(),
            ASIMDALL::SADDLV_Fd_Vn(opcode) => opcode.definition(),
            ASIMDALL::SMAXV_Fd_Vn(opcode) => opcode.definition(),
            ASIMDALL::SMINV_Fd_Vn(opcode) => opcode.definition(),
            ASIMDALL::UADDLV_Fd_Vn(opcode) => opcode.definition(),
            ASIMDALL::UMAXV_Fd_Vn(opcode) => opcode.definition(),
            ASIMDALL::UMINV_Fd_Vn(opcode) => opcode.definition(),
        }
    }
    fn bits(&self) -> u32 {
        match self {
            ASIMDALL::ADDV_Fd_Vn(opcode) => opcode.bits(),
            ASIMDALL::FMAXNMV_Fd_S_S_Vn_V_4S(opcode) => opcode.bits(),
            ASIMDALL::FMAXNMV_Fd_Vn(opcode) => opcode.bits(),
            ASIMDALL::FMAXV_Fd_S_S_Vn_V_4S(opcode) => opcode.bits(),
            ASIMDALL::FMAXV_Fd_Vn(opcode) => opcode.bits(),
            ASIMDALL::FMINNMV_Fd_S_S_Vn_V_4S(opcode) => opcode.bits(),
            ASIMDALL::FMINNMV_Fd_Vn(opcode) => opcode.bits(),
            ASIMDALL::FMINV_Fd_S_S_Vn_V_4S(opcode) => opcode.bits(),
            ASIMDALL::FMINV_Fd_Vn(opcode) => opcode.bits(),
            ASIMDALL::SADDLV_Fd_Vn(opcode) => opcode.bits(),
            ASIMDALL::SMAXV_Fd_Vn(opcode) => opcode.bits(),
            ASIMDALL::SMINV_Fd_Vn(opcode) => opcode.bits(),
            ASIMDALL::UADDLV_Fd_Vn(opcode) => opcode.bits(),
            ASIMDALL::UMAXV_Fd_Vn(opcode) => opcode.bits(),
            ASIMDALL::UMINV_Fd_Vn(opcode) => opcode.bits(),
        }
    }
}
impl InsnOpcode for SVE_SHIFT_PRED {
    fn definition(&self) -> &'static Insn {
        match self {
            SVE_SHIFT_PRED::ASRD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_SHRIMM_PRED(opcode) => {
                opcode.definition()
            }
            SVE_SHIFT_PRED::ASR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_SHRIMM_PRED(opcode) => {
                opcode.definition()
            }
            SVE_SHIFT_PRED::LSL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_SHLIMM_PRED(opcode) => {
                opcode.definition()
            }
            SVE_SHIFT_PRED::LSR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_SHRIMM_PRED(opcode) => {
                opcode.definition()
            }
            SVE_SHIFT_PRED::SQSHLU_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_SHLIMM_PRED(opcode) => {
                opcode.definition()
            }
            SVE_SHIFT_PRED::SQSHL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_SHLIMM_PRED(opcode) => {
                opcode.definition()
            }
            SVE_SHIFT_PRED::SRSHR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_SHRIMM_PRED(opcode) => {
                opcode.definition()
            }
            SVE_SHIFT_PRED::UQSHL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_SHLIMM_PRED(opcode) => {
                opcode.definition()
            }
            SVE_SHIFT_PRED::URSHR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_SHRIMM_PRED(opcode) => {
                opcode.definition()
            }
        }
    }
    fn bits(&self) -> u32 {
        match self {
            SVE_SHIFT_PRED::ASRD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_SHRIMM_PRED(opcode) => opcode.bits(),
            SVE_SHIFT_PRED::ASR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_SHRIMM_PRED(opcode) => opcode.bits(),
            SVE_SHIFT_PRED::LSL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_SHLIMM_PRED(opcode) => opcode.bits(),
            SVE_SHIFT_PRED::LSR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_SHRIMM_PRED(opcode) => opcode.bits(),
            SVE_SHIFT_PRED::SQSHLU_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_SHLIMM_PRED(opcode) => opcode.bits(),
            SVE_SHIFT_PRED::SQSHL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_SHLIMM_PRED(opcode) => opcode.bits(),
            SVE_SHIFT_PRED::SRSHR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_SHRIMM_PRED(opcode) => opcode.bits(),
            SVE_SHIFT_PRED::UQSHL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_SHLIMM_PRED(opcode) => opcode.bits(),
            SVE_SHIFT_PRED::URSHR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_SHRIMM_PRED(opcode) => opcode.bits(),
        }
    }
}
impl InsnOpcode for SVE_SHIFT_UNPRED {
    fn definition(&self) -> &'static Insn {
        match self {
            SVE_SHIFT_UNPRED::ASR_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED(opcode) => opcode.definition(),
            SVE_SHIFT_UNPRED::LSL_SVE_Zd_SVE_Zn_SVE_SHLIMM_UNPRED(opcode) => opcode.definition(),
            SVE_SHIFT_UNPRED::LSR_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED(opcode) => opcode.definition(),
        }
    }
    fn bits(&self) -> u32 {
        match self {
            SVE_SHIFT_UNPRED::ASR_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED(opcode) => opcode.bits(),
            SVE_SHIFT_UNPRED::LSL_SVE_Zd_SVE_Zn_SVE_SHLIMM_UNPRED(opcode) => opcode.bits(),
            SVE_SHIFT_UNPRED::LSR_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED(opcode) => opcode.bits(),
        }
    }
}
impl InsnOpcode for SME_LDR {
    fn definition(&self) -> &'static Insn {
        match self {
            SME_LDR::LDR_SME_ZA_array_off4_SME_ADDR_RI_U4xVL(opcode) => opcode.definition(),
        }
    }
    fn bits(&self) -> u32 {
        match self {
            SME_LDR::LDR_SME_ZA_array_off4_SME_ADDR_RI_U4xVL(opcode) => opcode.bits(),
        }
    }
}
impl InsnOpcode for SVE_SHIFT_TSZ_HSD {
    fn definition(&self) -> &'static Insn {
        match self {
            SVE_SHIFT_TSZ_HSD::RSHRNB_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22(opcode) => {
                opcode.definition()
            }
            SVE_SHIFT_TSZ_HSD::RSHRNT_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22(opcode) => {
                opcode.definition()
            }
            SVE_SHIFT_TSZ_HSD::SHRNB_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22(opcode) => {
                opcode.definition()
            }
            SVE_SHIFT_TSZ_HSD::SHRNT_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22(opcode) => {
                opcode.definition()
            }
            SVE_SHIFT_TSZ_HSD::SQRSHRNB_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22(opcode) => {
                opcode.definition()
            }
            SVE_SHIFT_TSZ_HSD::SQRSHRNT_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22(opcode) => {
                opcode.definition()
            }
            SVE_SHIFT_TSZ_HSD::SQRSHRUNB_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22(opcode) => {
                opcode.definition()
            }
            SVE_SHIFT_TSZ_HSD::SQRSHRUNT_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22(opcode) => {
                opcode.definition()
            }
            SVE_SHIFT_TSZ_HSD::SQSHRNB_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22(opcode) => {
                opcode.definition()
            }
            SVE_SHIFT_TSZ_HSD::SQSHRNT_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22(opcode) => {
                opcode.definition()
            }
            SVE_SHIFT_TSZ_HSD::SQSHRUNB_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22(opcode) => {
                opcode.definition()
            }
            SVE_SHIFT_TSZ_HSD::SQSHRUNT_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22(opcode) => {
                opcode.definition()
            }
            SVE_SHIFT_TSZ_HSD::SSHLLB_SVE_Zd_SVE_Zn_SVE_SHLIMM_UNPRED_22(opcode) => {
                opcode.definition()
            }
            SVE_SHIFT_TSZ_HSD::SSHLLT_SVE_Zd_SVE_Zn_SVE_SHLIMM_UNPRED_22(opcode) => {
                opcode.definition()
            }
            SVE_SHIFT_TSZ_HSD::UQRSHRNB_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22(opcode) => {
                opcode.definition()
            }
            SVE_SHIFT_TSZ_HSD::UQRSHRNT_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22(opcode) => {
                opcode.definition()
            }
            SVE_SHIFT_TSZ_HSD::UQSHRNB_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22(opcode) => {
                opcode.definition()
            }
            SVE_SHIFT_TSZ_HSD::UQSHRNT_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22(opcode) => {
                opcode.definition()
            }
            SVE_SHIFT_TSZ_HSD::USHLLB_SVE_Zd_SVE_Zn_SVE_SHLIMM_UNPRED_22(opcode) => {
                opcode.definition()
            }
            SVE_SHIFT_TSZ_HSD::USHLLT_SVE_Zd_SVE_Zn_SVE_SHLIMM_UNPRED_22(opcode) => {
                opcode.definition()
            }
        }
    }
    fn bits(&self) -> u32 {
        match self {
            SVE_SHIFT_TSZ_HSD::RSHRNB_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22(opcode) => opcode.bits(),
            SVE_SHIFT_TSZ_HSD::RSHRNT_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22(opcode) => opcode.bits(),
            SVE_SHIFT_TSZ_HSD::SHRNB_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22(opcode) => opcode.bits(),
            SVE_SHIFT_TSZ_HSD::SHRNT_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22(opcode) => opcode.bits(),
            SVE_SHIFT_TSZ_HSD::SQRSHRNB_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22(opcode) => opcode.bits(),
            SVE_SHIFT_TSZ_HSD::SQRSHRNT_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22(opcode) => opcode.bits(),
            SVE_SHIFT_TSZ_HSD::SQRSHRUNB_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22(opcode) => {
                opcode.bits()
            }
            SVE_SHIFT_TSZ_HSD::SQRSHRUNT_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22(opcode) => {
                opcode.bits()
            }
            SVE_SHIFT_TSZ_HSD::SQSHRNB_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22(opcode) => opcode.bits(),
            SVE_SHIFT_TSZ_HSD::SQSHRNT_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22(opcode) => opcode.bits(),
            SVE_SHIFT_TSZ_HSD::SQSHRUNB_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22(opcode) => opcode.bits(),
            SVE_SHIFT_TSZ_HSD::SQSHRUNT_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22(opcode) => opcode.bits(),
            SVE_SHIFT_TSZ_HSD::SSHLLB_SVE_Zd_SVE_Zn_SVE_SHLIMM_UNPRED_22(opcode) => opcode.bits(),
            SVE_SHIFT_TSZ_HSD::SSHLLT_SVE_Zd_SVE_Zn_SVE_SHLIMM_UNPRED_22(opcode) => opcode.bits(),
            SVE_SHIFT_TSZ_HSD::UQRSHRNB_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22(opcode) => opcode.bits(),
            SVE_SHIFT_TSZ_HSD::UQRSHRNT_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22(opcode) => opcode.bits(),
            SVE_SHIFT_TSZ_HSD::UQSHRNB_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22(opcode) => opcode.bits(),
            SVE_SHIFT_TSZ_HSD::UQSHRNT_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22(opcode) => opcode.bits(),
            SVE_SHIFT_TSZ_HSD::USHLLB_SVE_Zd_SVE_Zn_SVE_SHLIMM_UNPRED_22(opcode) => opcode.bits(),
            SVE_SHIFT_TSZ_HSD::USHLLT_SVE_Zd_SVE_Zn_SVE_SHLIMM_UNPRED_22(opcode) => opcode.bits(),
        }
    }
}
impl InsnOpcode for CRYPTOSHA3 {
    fn definition(&self) -> &'static Insn {
        match self {
            CRYPTOSHA3::BCAX_Vd_Vn_Vm_Va(opcode) => opcode.definition(),
            CRYPTOSHA3::EOR3_Vd_Vn_Vm_Va(opcode) => opcode.definition(),
            CRYPTOSHA3::RAX1_Vd_Vn_Vm(opcode) => opcode.definition(),
            CRYPTOSHA3::SHA1C_Fd_Fn_Vm(opcode) => opcode.definition(),
            CRYPTOSHA3::SHA1M_Fd_Fn_Vm(opcode) => opcode.definition(),
            CRYPTOSHA3::SHA1P_Fd_Fn_Vm(opcode) => opcode.definition(),
            CRYPTOSHA3::SHA1SU0_Vd_Vn_Vm(opcode) => opcode.definition(),
            CRYPTOSHA3::SHA256H2_Fd_Fn_Vm(opcode) => opcode.definition(),
            CRYPTOSHA3::SHA256H_Fd_Fn_Vm(opcode) => opcode.definition(),
            CRYPTOSHA3::SHA256SU1_Vd_Vn_Vm(opcode) => opcode.definition(),
            CRYPTOSHA3::XAR_Vd_Vn_Vm_IMM(opcode) => opcode.definition(),
        }
    }
    fn bits(&self) -> u32 {
        match self {
            CRYPTOSHA3::BCAX_Vd_Vn_Vm_Va(opcode) => opcode.bits(),
            CRYPTOSHA3::EOR3_Vd_Vn_Vm_Va(opcode) => opcode.bits(),
            CRYPTOSHA3::RAX1_Vd_Vn_Vm(opcode) => opcode.bits(),
            CRYPTOSHA3::SHA1C_Fd_Fn_Vm(opcode) => opcode.bits(),
            CRYPTOSHA3::SHA1M_Fd_Fn_Vm(opcode) => opcode.bits(),
            CRYPTOSHA3::SHA1P_Fd_Fn_Vm(opcode) => opcode.bits(),
            CRYPTOSHA3::SHA1SU0_Vd_Vn_Vm(opcode) => opcode.bits(),
            CRYPTOSHA3::SHA256H2_Fd_Fn_Vm(opcode) => opcode.bits(),
            CRYPTOSHA3::SHA256H_Fd_Fn_Vm(opcode) => opcode.bits(),
            CRYPTOSHA3::SHA256SU1_Vd_Vn_Vm(opcode) => opcode.bits(),
            CRYPTOSHA3::XAR_Vd_Vn_Vm_IMM(opcode) => opcode.bits(),
        }
    }
}
impl InsnOpcode for AARCH64_MISC {
    fn definition(&self) -> &'static Insn {
        match self {
            AARCH64_MISC::AXFLAG(opcode) => opcode.definition(),
            AARCH64_MISC::CPYEN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => opcode.definition(),
            AARCH64_MISC::CPYERN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => {
                opcode.definition()
            }
            AARCH64_MISC::CPYERTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => {
                opcode.definition()
            }
            AARCH64_MISC::CPYERTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => {
                opcode.definition()
            }
            AARCH64_MISC::CPYERTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => {
                opcode.definition()
            }
            AARCH64_MISC::CPYERT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => {
                opcode.definition()
            }
            AARCH64_MISC::CPYETN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => {
                opcode.definition()
            }
            AARCH64_MISC::CPYETRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => {
                opcode.definition()
            }
            AARCH64_MISC::CPYETWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => {
                opcode.definition()
            }
            AARCH64_MISC::CPYET_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => opcode.definition(),
            AARCH64_MISC::CPYEWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => {
                opcode.definition()
            }
            AARCH64_MISC::CPYEWTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => {
                opcode.definition()
            }
            AARCH64_MISC::CPYEWTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => {
                opcode.definition()
            }
            AARCH64_MISC::CPYEWTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => {
                opcode.definition()
            }
            AARCH64_MISC::CPYEWT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => {
                opcode.definition()
            }
            AARCH64_MISC::CPYE_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => opcode.definition(),
            AARCH64_MISC::CPYFEN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => {
                opcode.definition()
            }
            AARCH64_MISC::CPYFERN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => {
                opcode.definition()
            }
            AARCH64_MISC::CPYFERTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => {
                opcode.definition()
            }
            AARCH64_MISC::CPYFERTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => {
                opcode.definition()
            }
            AARCH64_MISC::CPYFERTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => {
                opcode.definition()
            }
            AARCH64_MISC::CPYFERT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => {
                opcode.definition()
            }
            AARCH64_MISC::CPYFETN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => {
                opcode.definition()
            }
            AARCH64_MISC::CPYFETRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => {
                opcode.definition()
            }
            AARCH64_MISC::CPYFETWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => {
                opcode.definition()
            }
            AARCH64_MISC::CPYFET_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => {
                opcode.definition()
            }
            AARCH64_MISC::CPYFEWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => {
                opcode.definition()
            }
            AARCH64_MISC::CPYFEWTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => {
                opcode.definition()
            }
            AARCH64_MISC::CPYFEWTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => {
                opcode.definition()
            }
            AARCH64_MISC::CPYFEWTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => {
                opcode.definition()
            }
            AARCH64_MISC::CPYFEWT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => {
                opcode.definition()
            }
            AARCH64_MISC::CPYFE_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => opcode.definition(),
            AARCH64_MISC::CPYFMN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => {
                opcode.definition()
            }
            AARCH64_MISC::CPYFMRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => {
                opcode.definition()
            }
            AARCH64_MISC::CPYFMRTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => {
                opcode.definition()
            }
            AARCH64_MISC::CPYFMRTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => {
                opcode.definition()
            }
            AARCH64_MISC::CPYFMRTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => {
                opcode.definition()
            }
            AARCH64_MISC::CPYFMRT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => {
                opcode.definition()
            }
            AARCH64_MISC::CPYFMTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => {
                opcode.definition()
            }
            AARCH64_MISC::CPYFMTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => {
                opcode.definition()
            }
            AARCH64_MISC::CPYFMTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => {
                opcode.definition()
            }
            AARCH64_MISC::CPYFMT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => {
                opcode.definition()
            }
            AARCH64_MISC::CPYFMWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => {
                opcode.definition()
            }
            AARCH64_MISC::CPYFMWTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => {
                opcode.definition()
            }
            AARCH64_MISC::CPYFMWTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => {
                opcode.definition()
            }
            AARCH64_MISC::CPYFMWTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => {
                opcode.definition()
            }
            AARCH64_MISC::CPYFMWT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => {
                opcode.definition()
            }
            AARCH64_MISC::CPYFM_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => opcode.definition(),
            AARCH64_MISC::CPYFPN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => {
                opcode.definition()
            }
            AARCH64_MISC::CPYFPRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => {
                opcode.definition()
            }
            AARCH64_MISC::CPYFPRTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => {
                opcode.definition()
            }
            AARCH64_MISC::CPYFPRTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => {
                opcode.definition()
            }
            AARCH64_MISC::CPYFPRTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => {
                opcode.definition()
            }
            AARCH64_MISC::CPYFPRT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => {
                opcode.definition()
            }
            AARCH64_MISC::CPYFPTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => {
                opcode.definition()
            }
            AARCH64_MISC::CPYFPTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => {
                opcode.definition()
            }
            AARCH64_MISC::CPYFPTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => {
                opcode.definition()
            }
            AARCH64_MISC::CPYFPT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => {
                opcode.definition()
            }
            AARCH64_MISC::CPYFPWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => {
                opcode.definition()
            }
            AARCH64_MISC::CPYFPWTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => {
                opcode.definition()
            }
            AARCH64_MISC::CPYFPWTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => {
                opcode.definition()
            }
            AARCH64_MISC::CPYFPWTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => {
                opcode.definition()
            }
            AARCH64_MISC::CPYFPWT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => {
                opcode.definition()
            }
            AARCH64_MISC::CPYFP_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => opcode.definition(),
            AARCH64_MISC::CPYMN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => opcode.definition(),
            AARCH64_MISC::CPYMRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => {
                opcode.definition()
            }
            AARCH64_MISC::CPYMRTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => {
                opcode.definition()
            }
            AARCH64_MISC::CPYMRTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => {
                opcode.definition()
            }
            AARCH64_MISC::CPYMRTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => {
                opcode.definition()
            }
            AARCH64_MISC::CPYMRT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => {
                opcode.definition()
            }
            AARCH64_MISC::CPYMTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => {
                opcode.definition()
            }
            AARCH64_MISC::CPYMTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => {
                opcode.definition()
            }
            AARCH64_MISC::CPYMTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => {
                opcode.definition()
            }
            AARCH64_MISC::CPYMT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => opcode.definition(),
            AARCH64_MISC::CPYMWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => {
                opcode.definition()
            }
            AARCH64_MISC::CPYMWTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => {
                opcode.definition()
            }
            AARCH64_MISC::CPYMWTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => {
                opcode.definition()
            }
            AARCH64_MISC::CPYMWTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => {
                opcode.definition()
            }
            AARCH64_MISC::CPYMWT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => {
                opcode.definition()
            }
            AARCH64_MISC::CPYM_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => opcode.definition(),
            AARCH64_MISC::CPYPN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => opcode.definition(),
            AARCH64_MISC::CPYPRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => {
                opcode.definition()
            }
            AARCH64_MISC::CPYPRTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => {
                opcode.definition()
            }
            AARCH64_MISC::CPYPRTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => {
                opcode.definition()
            }
            AARCH64_MISC::CPYPRTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => {
                opcode.definition()
            }
            AARCH64_MISC::CPYPRT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => {
                opcode.definition()
            }
            AARCH64_MISC::CPYPTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => {
                opcode.definition()
            }
            AARCH64_MISC::CPYPTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => {
                opcode.definition()
            }
            AARCH64_MISC::CPYPTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => {
                opcode.definition()
            }
            AARCH64_MISC::CPYPT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => opcode.definition(),
            AARCH64_MISC::CPYPWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => {
                opcode.definition()
            }
            AARCH64_MISC::CPYPWTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => {
                opcode.definition()
            }
            AARCH64_MISC::CPYPWTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => {
                opcode.definition()
            }
            AARCH64_MISC::CPYPWTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => {
                opcode.definition()
            }
            AARCH64_MISC::CPYPWT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => {
                opcode.definition()
            }
            AARCH64_MISC::CPYP_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => opcode.definition(),
            AARCH64_MISC::SETEN_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm(opcode) => opcode.definition(),
            AARCH64_MISC::SETETN_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm(opcode) => opcode.definition(),
            AARCH64_MISC::SETET_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm(opcode) => opcode.definition(),
            AARCH64_MISC::SETE_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm(opcode) => opcode.definition(),
            AARCH64_MISC::SETGEN_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm(opcode) => opcode.definition(),
            AARCH64_MISC::SETGETN_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm(opcode) => opcode.definition(),
            AARCH64_MISC::SETGET_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm(opcode) => opcode.definition(),
            AARCH64_MISC::SETGE_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm(opcode) => opcode.definition(),
            AARCH64_MISC::SETGMN_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm(opcode) => opcode.definition(),
            AARCH64_MISC::SETGMTN_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm(opcode) => opcode.definition(),
            AARCH64_MISC::SETGMT_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm(opcode) => opcode.definition(),
            AARCH64_MISC::SETGM_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm(opcode) => opcode.definition(),
            AARCH64_MISC::SETGPN_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm(opcode) => opcode.definition(),
            AARCH64_MISC::SETGPTN_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm(opcode) => opcode.definition(),
            AARCH64_MISC::SETGPT_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm(opcode) => opcode.definition(),
            AARCH64_MISC::SETGP_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm(opcode) => opcode.definition(),
            AARCH64_MISC::SETMN_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm(opcode) => opcode.definition(),
            AARCH64_MISC::SETMTN_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm(opcode) => opcode.definition(),
            AARCH64_MISC::SETMT_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm(opcode) => opcode.definition(),
            AARCH64_MISC::SETM_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm(opcode) => opcode.definition(),
            AARCH64_MISC::SETPN_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm(opcode) => opcode.definition(),
            AARCH64_MISC::SETPTN_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm(opcode) => opcode.definition(),
            AARCH64_MISC::SETPT_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm(opcode) => opcode.definition(),
            AARCH64_MISC::SETP_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm(opcode) => opcode.definition(),
            AARCH64_MISC::SMMLA_Vd_Vn_Vm(opcode) => opcode.definition(),
            AARCH64_MISC::TCANCEL_TME_UIMM16(opcode) => opcode.definition(),
            AARCH64_MISC::TCOMMIT(opcode) => opcode.definition(),
            AARCH64_MISC::TSTART_Rd(opcode) => opcode.definition(),
            AARCH64_MISC::TTEST_Rd(opcode) => opcode.definition(),
            AARCH64_MISC::UMMLA_Vd_Vn_Vm(opcode) => opcode.definition(),
            AARCH64_MISC::USDOT_Vd_Vn_Vm(opcode) => opcode.definition(),
            AARCH64_MISC::USMMLA_Vd_Vn_Vm(opcode) => opcode.definition(),
            AARCH64_MISC::XAFLAG(opcode) => opcode.definition(),
        }
    }
    fn bits(&self) -> u32 {
        match self {
            AARCH64_MISC::AXFLAG(opcode) => opcode.bits(),
            AARCH64_MISC::CPYEN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => opcode.bits(),
            AARCH64_MISC::CPYERN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => opcode.bits(),
            AARCH64_MISC::CPYERTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => opcode.bits(),
            AARCH64_MISC::CPYERTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => opcode.bits(),
            AARCH64_MISC::CPYERTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => opcode.bits(),
            AARCH64_MISC::CPYERT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => opcode.bits(),
            AARCH64_MISC::CPYETN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => opcode.bits(),
            AARCH64_MISC::CPYETRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => opcode.bits(),
            AARCH64_MISC::CPYETWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => opcode.bits(),
            AARCH64_MISC::CPYET_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => opcode.bits(),
            AARCH64_MISC::CPYEWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => opcode.bits(),
            AARCH64_MISC::CPYEWTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => opcode.bits(),
            AARCH64_MISC::CPYEWTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => opcode.bits(),
            AARCH64_MISC::CPYEWTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => opcode.bits(),
            AARCH64_MISC::CPYEWT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => opcode.bits(),
            AARCH64_MISC::CPYE_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => opcode.bits(),
            AARCH64_MISC::CPYFEN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => opcode.bits(),
            AARCH64_MISC::CPYFERN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => opcode.bits(),
            AARCH64_MISC::CPYFERTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => opcode.bits(),
            AARCH64_MISC::CPYFERTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => opcode.bits(),
            AARCH64_MISC::CPYFERTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => opcode.bits(),
            AARCH64_MISC::CPYFERT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => opcode.bits(),
            AARCH64_MISC::CPYFETN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => opcode.bits(),
            AARCH64_MISC::CPYFETRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => opcode.bits(),
            AARCH64_MISC::CPYFETWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => opcode.bits(),
            AARCH64_MISC::CPYFET_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => opcode.bits(),
            AARCH64_MISC::CPYFEWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => opcode.bits(),
            AARCH64_MISC::CPYFEWTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => opcode.bits(),
            AARCH64_MISC::CPYFEWTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => opcode.bits(),
            AARCH64_MISC::CPYFEWTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => opcode.bits(),
            AARCH64_MISC::CPYFEWT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => opcode.bits(),
            AARCH64_MISC::CPYFE_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => opcode.bits(),
            AARCH64_MISC::CPYFMN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => opcode.bits(),
            AARCH64_MISC::CPYFMRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => opcode.bits(),
            AARCH64_MISC::CPYFMRTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => opcode.bits(),
            AARCH64_MISC::CPYFMRTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => opcode.bits(),
            AARCH64_MISC::CPYFMRTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => opcode.bits(),
            AARCH64_MISC::CPYFMRT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => opcode.bits(),
            AARCH64_MISC::CPYFMTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => opcode.bits(),
            AARCH64_MISC::CPYFMTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => opcode.bits(),
            AARCH64_MISC::CPYFMTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => opcode.bits(),
            AARCH64_MISC::CPYFMT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => opcode.bits(),
            AARCH64_MISC::CPYFMWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => opcode.bits(),
            AARCH64_MISC::CPYFMWTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => opcode.bits(),
            AARCH64_MISC::CPYFMWTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => opcode.bits(),
            AARCH64_MISC::CPYFMWTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => opcode.bits(),
            AARCH64_MISC::CPYFMWT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => opcode.bits(),
            AARCH64_MISC::CPYFM_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => opcode.bits(),
            AARCH64_MISC::CPYFPN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => opcode.bits(),
            AARCH64_MISC::CPYFPRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => opcode.bits(),
            AARCH64_MISC::CPYFPRTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => opcode.bits(),
            AARCH64_MISC::CPYFPRTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => opcode.bits(),
            AARCH64_MISC::CPYFPRTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => opcode.bits(),
            AARCH64_MISC::CPYFPRT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => opcode.bits(),
            AARCH64_MISC::CPYFPTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => opcode.bits(),
            AARCH64_MISC::CPYFPTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => opcode.bits(),
            AARCH64_MISC::CPYFPTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => opcode.bits(),
            AARCH64_MISC::CPYFPT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => opcode.bits(),
            AARCH64_MISC::CPYFPWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => opcode.bits(),
            AARCH64_MISC::CPYFPWTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => opcode.bits(),
            AARCH64_MISC::CPYFPWTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => opcode.bits(),
            AARCH64_MISC::CPYFPWTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => opcode.bits(),
            AARCH64_MISC::CPYFPWT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => opcode.bits(),
            AARCH64_MISC::CPYFP_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => opcode.bits(),
            AARCH64_MISC::CPYMN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => opcode.bits(),
            AARCH64_MISC::CPYMRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => opcode.bits(),
            AARCH64_MISC::CPYMRTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => opcode.bits(),
            AARCH64_MISC::CPYMRTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => opcode.bits(),
            AARCH64_MISC::CPYMRTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => opcode.bits(),
            AARCH64_MISC::CPYMRT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => opcode.bits(),
            AARCH64_MISC::CPYMTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => opcode.bits(),
            AARCH64_MISC::CPYMTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => opcode.bits(),
            AARCH64_MISC::CPYMTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => opcode.bits(),
            AARCH64_MISC::CPYMT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => opcode.bits(),
            AARCH64_MISC::CPYMWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => opcode.bits(),
            AARCH64_MISC::CPYMWTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => opcode.bits(),
            AARCH64_MISC::CPYMWTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => opcode.bits(),
            AARCH64_MISC::CPYMWTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => opcode.bits(),
            AARCH64_MISC::CPYMWT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => opcode.bits(),
            AARCH64_MISC::CPYM_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => opcode.bits(),
            AARCH64_MISC::CPYPN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => opcode.bits(),
            AARCH64_MISC::CPYPRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => opcode.bits(),
            AARCH64_MISC::CPYPRTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => opcode.bits(),
            AARCH64_MISC::CPYPRTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => opcode.bits(),
            AARCH64_MISC::CPYPRTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => opcode.bits(),
            AARCH64_MISC::CPYPRT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => opcode.bits(),
            AARCH64_MISC::CPYPTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => opcode.bits(),
            AARCH64_MISC::CPYPTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => opcode.bits(),
            AARCH64_MISC::CPYPTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => opcode.bits(),
            AARCH64_MISC::CPYPT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => opcode.bits(),
            AARCH64_MISC::CPYPWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => opcode.bits(),
            AARCH64_MISC::CPYPWTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => opcode.bits(),
            AARCH64_MISC::CPYPWTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => opcode.bits(),
            AARCH64_MISC::CPYPWTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => opcode.bits(),
            AARCH64_MISC::CPYPWT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => opcode.bits(),
            AARCH64_MISC::CPYP_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn(opcode) => opcode.bits(),
            AARCH64_MISC::SETEN_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm(opcode) => opcode.bits(),
            AARCH64_MISC::SETETN_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm(opcode) => opcode.bits(),
            AARCH64_MISC::SETET_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm(opcode) => opcode.bits(),
            AARCH64_MISC::SETE_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm(opcode) => opcode.bits(),
            AARCH64_MISC::SETGEN_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm(opcode) => opcode.bits(),
            AARCH64_MISC::SETGETN_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm(opcode) => opcode.bits(),
            AARCH64_MISC::SETGET_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm(opcode) => opcode.bits(),
            AARCH64_MISC::SETGE_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm(opcode) => opcode.bits(),
            AARCH64_MISC::SETGMN_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm(opcode) => opcode.bits(),
            AARCH64_MISC::SETGMTN_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm(opcode) => opcode.bits(),
            AARCH64_MISC::SETGMT_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm(opcode) => opcode.bits(),
            AARCH64_MISC::SETGM_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm(opcode) => opcode.bits(),
            AARCH64_MISC::SETGPN_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm(opcode) => opcode.bits(),
            AARCH64_MISC::SETGPTN_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm(opcode) => opcode.bits(),
            AARCH64_MISC::SETGPT_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm(opcode) => opcode.bits(),
            AARCH64_MISC::SETGP_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm(opcode) => opcode.bits(),
            AARCH64_MISC::SETMN_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm(opcode) => opcode.bits(),
            AARCH64_MISC::SETMTN_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm(opcode) => opcode.bits(),
            AARCH64_MISC::SETMT_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm(opcode) => opcode.bits(),
            AARCH64_MISC::SETM_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm(opcode) => opcode.bits(),
            AARCH64_MISC::SETPN_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm(opcode) => opcode.bits(),
            AARCH64_MISC::SETPTN_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm(opcode) => opcode.bits(),
            AARCH64_MISC::SETPT_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm(opcode) => opcode.bits(),
            AARCH64_MISC::SETP_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm(opcode) => opcode.bits(),
            AARCH64_MISC::SMMLA_Vd_Vn_Vm(opcode) => opcode.bits(),
            AARCH64_MISC::TCANCEL_TME_UIMM16(opcode) => opcode.bits(),
            AARCH64_MISC::TCOMMIT(opcode) => opcode.bits(),
            AARCH64_MISC::TSTART_Rd(opcode) => opcode.bits(),
            AARCH64_MISC::TTEST_Rd(opcode) => opcode.bits(),
            AARCH64_MISC::UMMLA_Vd_Vn_Vm(opcode) => opcode.bits(),
            AARCH64_MISC::USDOT_Vd_Vn_Vm(opcode) => opcode.bits(),
            AARCH64_MISC::USMMLA_Vd_Vn_Vm(opcode) => opcode.bits(),
            AARCH64_MISC::XAFLAG(opcode) => opcode.bits(),
        }
    }
}
impl InsnOpcode for THE {
    fn definition(&self) -> &'static Insn {
        match self {
            THE::RCWCASAL_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            THE::RCWCASA_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            THE::RCWCASL_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            THE::RCWCASPAL_Rs_PAIRREG_Rt_PAIRREG_ADDR_SIMPLE(opcode) => opcode.definition(),
            THE::RCWCASPA_Rs_PAIRREG_Rt_PAIRREG_ADDR_SIMPLE(opcode) => opcode.definition(),
            THE::RCWCASPL_Rs_PAIRREG_Rt_PAIRREG_ADDR_SIMPLE(opcode) => opcode.definition(),
            THE::RCWCASP_Rs_PAIRREG_Rt_PAIRREG_ADDR_SIMPLE(opcode) => opcode.definition(),
            THE::RCWCAS_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            THE::RCWCLRAL_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            THE::RCWCLRA_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            THE::RCWCLRL_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            THE::RCWCLRPAL_Rt_Rs_ADDR_SIMPLE(opcode) => opcode.definition(),
            THE::RCWCLRPA_Rt_Rs_ADDR_SIMPLE(opcode) => opcode.definition(),
            THE::RCWCLRPL_Rt_Rs_ADDR_SIMPLE(opcode) => opcode.definition(),
            THE::RCWCLRP_Rt_Rs_ADDR_SIMPLE(opcode) => opcode.definition(),
            THE::RCWCLR_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            THE::RCWSCASAL_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            THE::RCWSCASA_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            THE::RCWSCASL_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            THE::RCWSCASPAL_Rs_PAIRREG_Rt_PAIRREG_ADDR_SIMPLE(opcode) => opcode.definition(),
            THE::RCWSCASPA_Rs_PAIRREG_Rt_PAIRREG_ADDR_SIMPLE(opcode) => opcode.definition(),
            THE::RCWSCASPL_Rs_PAIRREG_Rt_PAIRREG_ADDR_SIMPLE(opcode) => opcode.definition(),
            THE::RCWSCASP_Rs_PAIRREG_Rt_PAIRREG_ADDR_SIMPLE(opcode) => opcode.definition(),
            THE::RCWSCAS_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            THE::RCWSCLRAL_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            THE::RCWSCLRA_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            THE::RCWSCLRL_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            THE::RCWSCLRPAL_Rt_Rs_ADDR_SIMPLE(opcode) => opcode.definition(),
            THE::RCWSCLRPA_Rt_Rs_ADDR_SIMPLE(opcode) => opcode.definition(),
            THE::RCWSCLRPL_Rt_Rs_ADDR_SIMPLE(opcode) => opcode.definition(),
            THE::RCWSCLRP_Rt_Rs_ADDR_SIMPLE(opcode) => opcode.definition(),
            THE::RCWSCLR_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            THE::RCWSETAL_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            THE::RCWSETA_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            THE::RCWSETL_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            THE::RCWSETPAL_Rt_Rs_ADDR_SIMPLE(opcode) => opcode.definition(),
            THE::RCWSETPA_Rt_Rs_ADDR_SIMPLE(opcode) => opcode.definition(),
            THE::RCWSETPL_Rt_Rs_ADDR_SIMPLE(opcode) => opcode.definition(),
            THE::RCWSETP_Rt_Rs_ADDR_SIMPLE(opcode) => opcode.definition(),
            THE::RCWSET_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            THE::RCWSSETAL_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            THE::RCWSSETA_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            THE::RCWSSETL_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            THE::RCWSSETPAL_Rt_Rs_ADDR_SIMPLE(opcode) => opcode.definition(),
            THE::RCWSSETPA_Rt_Rs_ADDR_SIMPLE(opcode) => opcode.definition(),
            THE::RCWSSETPL_Rt_Rs_ADDR_SIMPLE(opcode) => opcode.definition(),
            THE::RCWSSETP_Rt_Rs_ADDR_SIMPLE(opcode) => opcode.definition(),
            THE::RCWSSET_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            THE::RCWSSWPAL_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            THE::RCWSSWPA_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            THE::RCWSSWPL_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            THE::RCWSSWPPAL_Rt_Rs_ADDR_SIMPLE(opcode) => opcode.definition(),
            THE::RCWSSWPPA_Rt_Rs_ADDR_SIMPLE(opcode) => opcode.definition(),
            THE::RCWSSWPPL_Rt_Rs_ADDR_SIMPLE(opcode) => opcode.definition(),
            THE::RCWSSWPP_Rt_Rs_ADDR_SIMPLE(opcode) => opcode.definition(),
            THE::RCWSSWP_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            THE::RCWSWPAL_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            THE::RCWSWPA_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            THE::RCWSWPL_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            THE::RCWSWPPAL_Rt_Rs_ADDR_SIMPLE(opcode) => opcode.definition(),
            THE::RCWSWPPA_Rt_Rs_ADDR_SIMPLE(opcode) => opcode.definition(),
            THE::RCWSWPPL_Rt_Rs_ADDR_SIMPLE(opcode) => opcode.definition(),
            THE::RCWSWPP_Rt_Rs_ADDR_SIMPLE(opcode) => opcode.definition(),
            THE::RCWSWP_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
        }
    }
    fn bits(&self) -> u32 {
        match self {
            THE::RCWCASAL_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            THE::RCWCASA_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            THE::RCWCASL_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            THE::RCWCASPAL_Rs_PAIRREG_Rt_PAIRREG_ADDR_SIMPLE(opcode) => opcode.bits(),
            THE::RCWCASPA_Rs_PAIRREG_Rt_PAIRREG_ADDR_SIMPLE(opcode) => opcode.bits(),
            THE::RCWCASPL_Rs_PAIRREG_Rt_PAIRREG_ADDR_SIMPLE(opcode) => opcode.bits(),
            THE::RCWCASP_Rs_PAIRREG_Rt_PAIRREG_ADDR_SIMPLE(opcode) => opcode.bits(),
            THE::RCWCAS_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            THE::RCWCLRAL_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            THE::RCWCLRA_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            THE::RCWCLRL_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            THE::RCWCLRPAL_Rt_Rs_ADDR_SIMPLE(opcode) => opcode.bits(),
            THE::RCWCLRPA_Rt_Rs_ADDR_SIMPLE(opcode) => opcode.bits(),
            THE::RCWCLRPL_Rt_Rs_ADDR_SIMPLE(opcode) => opcode.bits(),
            THE::RCWCLRP_Rt_Rs_ADDR_SIMPLE(opcode) => opcode.bits(),
            THE::RCWCLR_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            THE::RCWSCASAL_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            THE::RCWSCASA_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            THE::RCWSCASL_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            THE::RCWSCASPAL_Rs_PAIRREG_Rt_PAIRREG_ADDR_SIMPLE(opcode) => opcode.bits(),
            THE::RCWSCASPA_Rs_PAIRREG_Rt_PAIRREG_ADDR_SIMPLE(opcode) => opcode.bits(),
            THE::RCWSCASPL_Rs_PAIRREG_Rt_PAIRREG_ADDR_SIMPLE(opcode) => opcode.bits(),
            THE::RCWSCASP_Rs_PAIRREG_Rt_PAIRREG_ADDR_SIMPLE(opcode) => opcode.bits(),
            THE::RCWSCAS_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            THE::RCWSCLRAL_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            THE::RCWSCLRA_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            THE::RCWSCLRL_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            THE::RCWSCLRPAL_Rt_Rs_ADDR_SIMPLE(opcode) => opcode.bits(),
            THE::RCWSCLRPA_Rt_Rs_ADDR_SIMPLE(opcode) => opcode.bits(),
            THE::RCWSCLRPL_Rt_Rs_ADDR_SIMPLE(opcode) => opcode.bits(),
            THE::RCWSCLRP_Rt_Rs_ADDR_SIMPLE(opcode) => opcode.bits(),
            THE::RCWSCLR_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            THE::RCWSETAL_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            THE::RCWSETA_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            THE::RCWSETL_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            THE::RCWSETPAL_Rt_Rs_ADDR_SIMPLE(opcode) => opcode.bits(),
            THE::RCWSETPA_Rt_Rs_ADDR_SIMPLE(opcode) => opcode.bits(),
            THE::RCWSETPL_Rt_Rs_ADDR_SIMPLE(opcode) => opcode.bits(),
            THE::RCWSETP_Rt_Rs_ADDR_SIMPLE(opcode) => opcode.bits(),
            THE::RCWSET_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            THE::RCWSSETAL_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            THE::RCWSSETA_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            THE::RCWSSETL_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            THE::RCWSSETPAL_Rt_Rs_ADDR_SIMPLE(opcode) => opcode.bits(),
            THE::RCWSSETPA_Rt_Rs_ADDR_SIMPLE(opcode) => opcode.bits(),
            THE::RCWSSETPL_Rt_Rs_ADDR_SIMPLE(opcode) => opcode.bits(),
            THE::RCWSSETP_Rt_Rs_ADDR_SIMPLE(opcode) => opcode.bits(),
            THE::RCWSSET_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            THE::RCWSSWPAL_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            THE::RCWSSWPA_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            THE::RCWSSWPL_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            THE::RCWSSWPPAL_Rt_Rs_ADDR_SIMPLE(opcode) => opcode.bits(),
            THE::RCWSSWPPA_Rt_Rs_ADDR_SIMPLE(opcode) => opcode.bits(),
            THE::RCWSSWPPL_Rt_Rs_ADDR_SIMPLE(opcode) => opcode.bits(),
            THE::RCWSSWPP_Rt_Rs_ADDR_SIMPLE(opcode) => opcode.bits(),
            THE::RCWSSWP_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            THE::RCWSWPAL_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            THE::RCWSWPA_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            THE::RCWSWPL_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            THE::RCWSWPPAL_Rt_Rs_ADDR_SIMPLE(opcode) => opcode.bits(),
            THE::RCWSWPPA_Rt_Rs_ADDR_SIMPLE(opcode) => opcode.bits(),
            THE::RCWSWPPL_Rt_Rs_ADDR_SIMPLE(opcode) => opcode.bits(),
            THE::RCWSWPP_Rt_Rs_ADDR_SIMPLE(opcode) => opcode.bits(),
            THE::RCWSWP_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
        }
    }
}
impl InsnOpcode for SVE_SIZE_BH {
    fn definition(&self) -> &'static Insn {
        match self {
            SVE_SIZE_BH::MATCH_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_SIZE_BH::NMATCH_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
        }
    }
    fn bits(&self) -> u32 {
        match self {
            SVE_SIZE_BH::MATCH_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_SIZE_BH::NMATCH_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
        }
    }
}
impl InsnOpcode for SVE_CPY {
    fn definition(&self) -> &'static Insn {
        match self {
            SVE_CPY::CPY_SVE_Zd_SVE_Pg4_16_SVE_ASIMM(opcode) => opcode.definition(),
        }
    }
    fn bits(&self) -> u32 {
        match self {
            SVE_CPY::CPY_SVE_Zd_SVE_Pg4_16_SVE_ASIMM(opcode) => opcode.bits(),
        }
    }
}
impl InsnOpcode for SME2_MOV {
    fn definition(&self) -> &'static Insn {
        match self {
            SME2_MOV::MOVA_SME_ZA_array_off3_0_SME_Znx2(opcode) => opcode.definition(),
            SME2_MOV::MOVA_SME_ZA_array_off3_0_SME_Znx4(opcode) => opcode.definition(),
            SME2_MOV::MOVA_SME_Zdnx2_SME_ZA_array_off3_5(opcode) => opcode.definition(),
            SME2_MOV::MOVA_SME_Zdnx4_SME_ZA_array_off3_5(opcode) => opcode.definition(),
            SME2_MOV::MOV_SME_ZA_array_off3_0_SME_Znx2(opcode) => opcode.definition(),
            SME2_MOV::MOV_SME_ZA_array_off3_0_SME_Znx4(opcode) => opcode.definition(),
            SME2_MOV::MOV_SME_Zdnx2_SME_ZA_array_off3_5(opcode) => opcode.definition(),
            SME2_MOV::MOV_SME_Zdnx4_SME_ZA_array_off3_5(opcode) => opcode.definition(),
        }
    }
    fn bits(&self) -> u32 {
        match self {
            SME2_MOV::MOVA_SME_ZA_array_off3_0_SME_Znx2(opcode) => opcode.bits(),
            SME2_MOV::MOVA_SME_ZA_array_off3_0_SME_Znx4(opcode) => opcode.bits(),
            SME2_MOV::MOVA_SME_Zdnx2_SME_ZA_array_off3_5(opcode) => opcode.bits(),
            SME2_MOV::MOVA_SME_Zdnx4_SME_ZA_array_off3_5(opcode) => opcode.bits(),
            SME2_MOV::MOV_SME_ZA_array_off3_0_SME_Znx2(opcode) => opcode.bits(),
            SME2_MOV::MOV_SME_ZA_array_off3_0_SME_Znx4(opcode) => opcode.bits(),
            SME2_MOV::MOV_SME_Zdnx2_SME_ZA_array_off3_5(opcode) => opcode.bits(),
            SME2_MOV::MOV_SME_Zdnx4_SME_ZA_array_off3_5(opcode) => opcode.bits(),
        }
    }
}
impl InsnOpcode for LOG_SHIFT {
    fn definition(&self) -> &'static Insn {
        match self {
            LOG_SHIFT::ANDS_Rd_Rn_Rm_SFT(opcode) => opcode.definition(),
            LOG_SHIFT::AND_Rd_Rn_Rm_SFT(opcode) => opcode.definition(),
            LOG_SHIFT::BICS_Rd_Rn_Rm_SFT(opcode) => opcode.definition(),
            LOG_SHIFT::BIC_Rd_Rn_Rm_SFT(opcode) => opcode.definition(),
            LOG_SHIFT::EON_Rd_Rn_Rm_SFT(opcode) => opcode.definition(),
            LOG_SHIFT::EOR_Rd_Rn_Rm_SFT(opcode) => opcode.definition(),
            LOG_SHIFT::ORN_Rd_Rn_Rm_SFT(opcode) => opcode.definition(),
            LOG_SHIFT::ORR_Rd_Rn_Rm_SFT(opcode) => opcode.definition(),
        }
    }
    fn bits(&self) -> u32 {
        match self {
            LOG_SHIFT::ANDS_Rd_Rn_Rm_SFT(opcode) => opcode.bits(),
            LOG_SHIFT::AND_Rd_Rn_Rm_SFT(opcode) => opcode.bits(),
            LOG_SHIFT::BICS_Rd_Rn_Rm_SFT(opcode) => opcode.bits(),
            LOG_SHIFT::BIC_Rd_Rn_Rm_SFT(opcode) => opcode.bits(),
            LOG_SHIFT::EON_Rd_Rn_Rm_SFT(opcode) => opcode.bits(),
            LOG_SHIFT::EOR_Rd_Rn_Rm_SFT(opcode) => opcode.bits(),
            LOG_SHIFT::ORN_Rd_Rn_Rm_SFT(opcode) => opcode.bits(),
            LOG_SHIFT::ORR_Rd_Rn_Rm_SFT(opcode) => opcode.bits(),
        }
    }
}
impl InsnOpcode for SME_PSEL {
    fn definition(&self) -> &'static Insn {
        match self {
            SME_PSEL::PSEL_SVE_PNd_SVE_PNg4_10_SME_PnT_Wm_imm(opcode) => opcode.definition(),
            SME_PSEL::PSEL_SVE_Pd_SVE_Pg4_10_SME_PnT_Wm_imm(opcode) => opcode.definition(),
        }
    }
    fn bits(&self) -> u32 {
        match self {
            SME_PSEL::PSEL_SVE_PNd_SVE_PNg4_10_SME_PnT_Wm_imm(opcode) => opcode.bits(),
            SME_PSEL::PSEL_SVE_Pd_SVE_Pg4_10_SME_PnT_Wm_imm(opcode) => opcode.bits(),
        }
    }
}
impl InsnOpcode for SME_SIZE_22 {
    fn definition(&self) -> &'static Insn {
        match self {
            SME_SIZE_22::ADD_SME_Zdnx2_SME_Zdnx2_SME_Zm(opcode) => opcode.definition(),
            SME_SIZE_22::ADD_SME_Zdnx4_SME_Zdnx4_SME_Zm(opcode) => opcode.definition(),
            SME_SIZE_22::CNTP_Rd_SME_PNn_SME_VLxN_10(opcode) => opcode.definition(),
            SME_SIZE_22::MOVA_SME_ZA_HV_idx_destxN_SME_Znx2(opcode) => opcode.definition(),
            SME_SIZE_22::MOVA_SME_ZA_HV_idx_destxN_SME_Znx4(opcode) => opcode.definition(),
            SME_SIZE_22::MOVA_SME_Zdnx2_SME_ZA_HV_idx_srcxN(opcode) => opcode.definition(),
            SME_SIZE_22::MOVA_SME_Zdnx4_SME_ZA_HV_idx_srcxN(opcode) => opcode.definition(),
            SME_SIZE_22::MOV_SME_ZA_HV_idx_destxN_SME_Znx2(opcode) => opcode.definition(),
            SME_SIZE_22::MOV_SME_ZA_HV_idx_destxN_SME_Znx4(opcode) => opcode.definition(),
            SME_SIZE_22::MOV_SME_Zdnx2_SME_ZA_HV_idx_srcxN(opcode) => opcode.definition(),
            SME_SIZE_22::MOV_SME_Zdnx4_SME_ZA_HV_idx_srcxN(opcode) => opcode.definition(),
            SME_SIZE_22::PEXT_SME_PdxN_SME_PNn3_INDEX1(opcode) => opcode.definition(),
            SME_SIZE_22::PEXT_SVE_Pd_SME_PNn3_INDEX2(opcode) => opcode.definition(),
            SME_SIZE_22::PTRUE_SME_PNd3(opcode) => opcode.definition(),
            SME_SIZE_22::SCLAMP_SME_Zdnx2_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SME_SIZE_22::SCLAMP_SME_Zdnx4_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SME_SIZE_22::SEL_SME_Zdnx2_SME_PNg3_SME_Znx2_SME_Zmx2(opcode) => opcode.definition(),
            SME_SIZE_22::SEL_SME_Zdnx4_SME_PNg3_SME_Znx4_SME_Zmx4(opcode) => opcode.definition(),
            SME_SIZE_22::SMAX_SME_Zdnx2_SME_Zdnx2_SME_Zm(opcode) => opcode.definition(),
            SME_SIZE_22::SMAX_SME_Zdnx2_SME_Zdnx2_SME_Zmx2(opcode) => opcode.definition(),
            SME_SIZE_22::SMAX_SME_Zdnx4_SME_Zdnx4_SME_Zm(opcode) => opcode.definition(),
            SME_SIZE_22::SMAX_SME_Zdnx4_SME_Zdnx4_SME_Zmx4(opcode) => opcode.definition(),
            SME_SIZE_22::SMIN_SME_Zdnx2_SME_Zdnx2_SME_Zm(opcode) => opcode.definition(),
            SME_SIZE_22::SMIN_SME_Zdnx2_SME_Zdnx2_SME_Zmx2(opcode) => opcode.definition(),
            SME_SIZE_22::SMIN_SME_Zdnx4_SME_Zdnx4_SME_Zm(opcode) => opcode.definition(),
            SME_SIZE_22::SMIN_SME_Zdnx4_SME_Zdnx4_SME_Zmx4(opcode) => opcode.definition(),
            SME_SIZE_22::SQDMULH_SME_Zdnx2_SME_Zdnx2_SME_Zm(opcode) => opcode.definition(),
            SME_SIZE_22::SQDMULH_SME_Zdnx2_SME_Zdnx2_SME_Zmx2(opcode) => opcode.definition(),
            SME_SIZE_22::SQDMULH_SME_Zdnx4_SME_Zdnx4_SME_Zm(opcode) => opcode.definition(),
            SME_SIZE_22::SQDMULH_SME_Zdnx4_SME_Zdnx4_SME_Zmx4(opcode) => opcode.definition(),
            SME_SIZE_22::SRSHL_SME_Zdnx2_SME_Zdnx2_SME_Zm(opcode) => opcode.definition(),
            SME_SIZE_22::SRSHL_SME_Zdnx2_SME_Zdnx2_SME_Zmx2(opcode) => opcode.definition(),
            SME_SIZE_22::SRSHL_SME_Zdnx4_SME_Zdnx4_SME_Zm(opcode) => opcode.definition(),
            SME_SIZE_22::SRSHL_SME_Zdnx4_SME_Zdnx4_SME_Zmx4(opcode) => opcode.definition(),
            SME_SIZE_22::UCLAMP_SME_Zdnx2_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SME_SIZE_22::UCLAMP_SME_Zdnx4_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SME_SIZE_22::UMAX_SME_Zdnx2_SME_Zdnx2_SME_Zm(opcode) => opcode.definition(),
            SME_SIZE_22::UMAX_SME_Zdnx2_SME_Zdnx2_SME_Zmx2(opcode) => opcode.definition(),
            SME_SIZE_22::UMAX_SME_Zdnx4_SME_Zdnx4_SME_Zm(opcode) => opcode.definition(),
            SME_SIZE_22::UMAX_SME_Zdnx4_SME_Zdnx4_SME_Zmx4(opcode) => opcode.definition(),
            SME_SIZE_22::UMIN_SME_Zdnx2_SME_Zdnx2_SME_Zm(opcode) => opcode.definition(),
            SME_SIZE_22::UMIN_SME_Zdnx2_SME_Zdnx2_SME_Zmx2(opcode) => opcode.definition(),
            SME_SIZE_22::UMIN_SME_Zdnx4_SME_Zdnx4_SME_Zm(opcode) => opcode.definition(),
            SME_SIZE_22::UMIN_SME_Zdnx4_SME_Zdnx4_SME_Zmx4(opcode) => opcode.definition(),
            SME_SIZE_22::URSHL_SME_Zdnx2_SME_Zdnx2_SME_Zm(opcode) => opcode.definition(),
            SME_SIZE_22::URSHL_SME_Zdnx2_SME_Zdnx2_SME_Zmx2(opcode) => opcode.definition(),
            SME_SIZE_22::URSHL_SME_Zdnx4_SME_Zdnx4_SME_Zm(opcode) => opcode.definition(),
            SME_SIZE_22::URSHL_SME_Zdnx4_SME_Zdnx4_SME_Zmx4(opcode) => opcode.definition(),
            SME_SIZE_22::UZP_SME_Zdnx2_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SME_SIZE_22::UZP_SME_Zdnx4_SME_Znx4(opcode) => opcode.definition(),
            SME_SIZE_22::WHILEGE_SME_PNd3_Rn_Rm_SME_VLxN_13(opcode) => opcode.definition(),
            SME_SIZE_22::WHILEGE_SME_Pdx2_Rn_Rm(opcode) => opcode.definition(),
            SME_SIZE_22::WHILEGT_SME_PNd3_Rn_Rm_SME_VLxN_13(opcode) => opcode.definition(),
            SME_SIZE_22::WHILEGT_SME_Pdx2_Rn_Rm(opcode) => opcode.definition(),
            SME_SIZE_22::WHILEHI_SME_PNd3_Rn_Rm_SME_VLxN_13(opcode) => opcode.definition(),
            SME_SIZE_22::WHILEHI_SME_Pdx2_Rn_Rm(opcode) => opcode.definition(),
            SME_SIZE_22::WHILEHS_SME_PNd3_Rn_Rm_SME_VLxN_13(opcode) => opcode.definition(),
            SME_SIZE_22::WHILEHS_SME_Pdx2_Rn_Rm(opcode) => opcode.definition(),
            SME_SIZE_22::WHILELE_SME_PNd3_Rn_Rm_SME_VLxN_13(opcode) => opcode.definition(),
            SME_SIZE_22::WHILELE_SME_Pdx2_Rn_Rm(opcode) => opcode.definition(),
            SME_SIZE_22::WHILELO_SME_PNd3_Rn_Rm_SME_VLxN_13(opcode) => opcode.definition(),
            SME_SIZE_22::WHILELO_SME_Pdx2_Rn_Rm(opcode) => opcode.definition(),
            SME_SIZE_22::WHILELS_SME_PNd3_Rn_Rm_SME_VLxN_13(opcode) => opcode.definition(),
            SME_SIZE_22::WHILELS_SME_Pdx2_Rn_Rm(opcode) => opcode.definition(),
            SME_SIZE_22::WHILELT_SME_PNd3_Rn_Rm_SME_VLxN_13(opcode) => opcode.definition(),
            SME_SIZE_22::WHILELT_SME_Pdx2_Rn_Rm(opcode) => opcode.definition(),
            SME_SIZE_22::ZIP_SME_Zdnx2_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SME_SIZE_22::ZIP_SME_Zdnx4_SME_Znx4(opcode) => opcode.definition(),
        }
    }
    fn bits(&self) -> u32 {
        match self {
            SME_SIZE_22::ADD_SME_Zdnx2_SME_Zdnx2_SME_Zm(opcode) => opcode.bits(),
            SME_SIZE_22::ADD_SME_Zdnx4_SME_Zdnx4_SME_Zm(opcode) => opcode.bits(),
            SME_SIZE_22::CNTP_Rd_SME_PNn_SME_VLxN_10(opcode) => opcode.bits(),
            SME_SIZE_22::MOVA_SME_ZA_HV_idx_destxN_SME_Znx2(opcode) => opcode.bits(),
            SME_SIZE_22::MOVA_SME_ZA_HV_idx_destxN_SME_Znx4(opcode) => opcode.bits(),
            SME_SIZE_22::MOVA_SME_Zdnx2_SME_ZA_HV_idx_srcxN(opcode) => opcode.bits(),
            SME_SIZE_22::MOVA_SME_Zdnx4_SME_ZA_HV_idx_srcxN(opcode) => opcode.bits(),
            SME_SIZE_22::MOV_SME_ZA_HV_idx_destxN_SME_Znx2(opcode) => opcode.bits(),
            SME_SIZE_22::MOV_SME_ZA_HV_idx_destxN_SME_Znx4(opcode) => opcode.bits(),
            SME_SIZE_22::MOV_SME_Zdnx2_SME_ZA_HV_idx_srcxN(opcode) => opcode.bits(),
            SME_SIZE_22::MOV_SME_Zdnx4_SME_ZA_HV_idx_srcxN(opcode) => opcode.bits(),
            SME_SIZE_22::PEXT_SME_PdxN_SME_PNn3_INDEX1(opcode) => opcode.bits(),
            SME_SIZE_22::PEXT_SVE_Pd_SME_PNn3_INDEX2(opcode) => opcode.bits(),
            SME_SIZE_22::PTRUE_SME_PNd3(opcode) => opcode.bits(),
            SME_SIZE_22::SCLAMP_SME_Zdnx2_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SME_SIZE_22::SCLAMP_SME_Zdnx4_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SME_SIZE_22::SEL_SME_Zdnx2_SME_PNg3_SME_Znx2_SME_Zmx2(opcode) => opcode.bits(),
            SME_SIZE_22::SEL_SME_Zdnx4_SME_PNg3_SME_Znx4_SME_Zmx4(opcode) => opcode.bits(),
            SME_SIZE_22::SMAX_SME_Zdnx2_SME_Zdnx2_SME_Zm(opcode) => opcode.bits(),
            SME_SIZE_22::SMAX_SME_Zdnx2_SME_Zdnx2_SME_Zmx2(opcode) => opcode.bits(),
            SME_SIZE_22::SMAX_SME_Zdnx4_SME_Zdnx4_SME_Zm(opcode) => opcode.bits(),
            SME_SIZE_22::SMAX_SME_Zdnx4_SME_Zdnx4_SME_Zmx4(opcode) => opcode.bits(),
            SME_SIZE_22::SMIN_SME_Zdnx2_SME_Zdnx2_SME_Zm(opcode) => opcode.bits(),
            SME_SIZE_22::SMIN_SME_Zdnx2_SME_Zdnx2_SME_Zmx2(opcode) => opcode.bits(),
            SME_SIZE_22::SMIN_SME_Zdnx4_SME_Zdnx4_SME_Zm(opcode) => opcode.bits(),
            SME_SIZE_22::SMIN_SME_Zdnx4_SME_Zdnx4_SME_Zmx4(opcode) => opcode.bits(),
            SME_SIZE_22::SQDMULH_SME_Zdnx2_SME_Zdnx2_SME_Zm(opcode) => opcode.bits(),
            SME_SIZE_22::SQDMULH_SME_Zdnx2_SME_Zdnx2_SME_Zmx2(opcode) => opcode.bits(),
            SME_SIZE_22::SQDMULH_SME_Zdnx4_SME_Zdnx4_SME_Zm(opcode) => opcode.bits(),
            SME_SIZE_22::SQDMULH_SME_Zdnx4_SME_Zdnx4_SME_Zmx4(opcode) => opcode.bits(),
            SME_SIZE_22::SRSHL_SME_Zdnx2_SME_Zdnx2_SME_Zm(opcode) => opcode.bits(),
            SME_SIZE_22::SRSHL_SME_Zdnx2_SME_Zdnx2_SME_Zmx2(opcode) => opcode.bits(),
            SME_SIZE_22::SRSHL_SME_Zdnx4_SME_Zdnx4_SME_Zm(opcode) => opcode.bits(),
            SME_SIZE_22::SRSHL_SME_Zdnx4_SME_Zdnx4_SME_Zmx4(opcode) => opcode.bits(),
            SME_SIZE_22::UCLAMP_SME_Zdnx2_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SME_SIZE_22::UCLAMP_SME_Zdnx4_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SME_SIZE_22::UMAX_SME_Zdnx2_SME_Zdnx2_SME_Zm(opcode) => opcode.bits(),
            SME_SIZE_22::UMAX_SME_Zdnx2_SME_Zdnx2_SME_Zmx2(opcode) => opcode.bits(),
            SME_SIZE_22::UMAX_SME_Zdnx4_SME_Zdnx4_SME_Zm(opcode) => opcode.bits(),
            SME_SIZE_22::UMAX_SME_Zdnx4_SME_Zdnx4_SME_Zmx4(opcode) => opcode.bits(),
            SME_SIZE_22::UMIN_SME_Zdnx2_SME_Zdnx2_SME_Zm(opcode) => opcode.bits(),
            SME_SIZE_22::UMIN_SME_Zdnx2_SME_Zdnx2_SME_Zmx2(opcode) => opcode.bits(),
            SME_SIZE_22::UMIN_SME_Zdnx4_SME_Zdnx4_SME_Zm(opcode) => opcode.bits(),
            SME_SIZE_22::UMIN_SME_Zdnx4_SME_Zdnx4_SME_Zmx4(opcode) => opcode.bits(),
            SME_SIZE_22::URSHL_SME_Zdnx2_SME_Zdnx2_SME_Zm(opcode) => opcode.bits(),
            SME_SIZE_22::URSHL_SME_Zdnx2_SME_Zdnx2_SME_Zmx2(opcode) => opcode.bits(),
            SME_SIZE_22::URSHL_SME_Zdnx4_SME_Zdnx4_SME_Zm(opcode) => opcode.bits(),
            SME_SIZE_22::URSHL_SME_Zdnx4_SME_Zdnx4_SME_Zmx4(opcode) => opcode.bits(),
            SME_SIZE_22::UZP_SME_Zdnx2_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SME_SIZE_22::UZP_SME_Zdnx4_SME_Znx4(opcode) => opcode.bits(),
            SME_SIZE_22::WHILEGE_SME_PNd3_Rn_Rm_SME_VLxN_13(opcode) => opcode.bits(),
            SME_SIZE_22::WHILEGE_SME_Pdx2_Rn_Rm(opcode) => opcode.bits(),
            SME_SIZE_22::WHILEGT_SME_PNd3_Rn_Rm_SME_VLxN_13(opcode) => opcode.bits(),
            SME_SIZE_22::WHILEGT_SME_Pdx2_Rn_Rm(opcode) => opcode.bits(),
            SME_SIZE_22::WHILEHI_SME_PNd3_Rn_Rm_SME_VLxN_13(opcode) => opcode.bits(),
            SME_SIZE_22::WHILEHI_SME_Pdx2_Rn_Rm(opcode) => opcode.bits(),
            SME_SIZE_22::WHILEHS_SME_PNd3_Rn_Rm_SME_VLxN_13(opcode) => opcode.bits(),
            SME_SIZE_22::WHILEHS_SME_Pdx2_Rn_Rm(opcode) => opcode.bits(),
            SME_SIZE_22::WHILELE_SME_PNd3_Rn_Rm_SME_VLxN_13(opcode) => opcode.bits(),
            SME_SIZE_22::WHILELE_SME_Pdx2_Rn_Rm(opcode) => opcode.bits(),
            SME_SIZE_22::WHILELO_SME_PNd3_Rn_Rm_SME_VLxN_13(opcode) => opcode.bits(),
            SME_SIZE_22::WHILELO_SME_Pdx2_Rn_Rm(opcode) => opcode.bits(),
            SME_SIZE_22::WHILELS_SME_PNd3_Rn_Rm_SME_VLxN_13(opcode) => opcode.bits(),
            SME_SIZE_22::WHILELS_SME_Pdx2_Rn_Rm(opcode) => opcode.bits(),
            SME_SIZE_22::WHILELT_SME_PNd3_Rn_Rm_SME_VLxN_13(opcode) => opcode.bits(),
            SME_SIZE_22::WHILELT_SME_Pdx2_Rn_Rm(opcode) => opcode.bits(),
            SME_SIZE_22::ZIP_SME_Zdnx2_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SME_SIZE_22::ZIP_SME_Zdnx4_SME_Znx4(opcode) => opcode.bits(),
        }
    }
}
impl InsnOpcode for SME_STOP {
    fn definition(&self) -> &'static Insn {
        match self {
            SME_STOP::SMSTOP(opcode) => opcode.definition(),
            SME_STOP::SMSTOP_SME_SM_ZA(opcode) => opcode.definition(),
        }
    }
    fn bits(&self) -> u32 {
        match self {
            SME_STOP::SMSTOP(opcode) => opcode.bits(),
            SME_STOP::SMSTOP_SME_SM_ZA(opcode) => opcode.bits(),
        }
    }
}
impl InsnOpcode for BFLOAT16 {
    fn definition(&self) -> &'static Insn {
        match self {
            BFLOAT16::BFCVTN2_Vd_Vn(opcode) => opcode.definition(),
            BFLOAT16::BFCVTN_Vd_Vn(opcode) => opcode.definition(),
            BFLOAT16::BFCVT_Fd_Fn(opcode) => opcode.definition(),
            BFLOAT16::BFDOT_Vd_Vn_Vm(opcode) => opcode.definition(),
            BFLOAT16::BFMLALB_Vd_Vn_Em16(opcode) => opcode.definition(),
            BFLOAT16::BFMLALB_Vd_Vn_Vm(opcode) => opcode.definition(),
            BFLOAT16::BFMLALT_Vd_Vn_Em16(opcode) => opcode.definition(),
            BFLOAT16::BFMLALT_Vd_Vn_Vm(opcode) => opcode.definition(),
            BFLOAT16::BFMMLA_Vd_Vn_Vm(opcode) => opcode.definition(),
        }
    }
    fn bits(&self) -> u32 {
        match self {
            BFLOAT16::BFCVTN2_Vd_Vn(opcode) => opcode.bits(),
            BFLOAT16::BFCVTN_Vd_Vn(opcode) => opcode.bits(),
            BFLOAT16::BFCVT_Fd_Fn(opcode) => opcode.bits(),
            BFLOAT16::BFDOT_Vd_Vn_Vm(opcode) => opcode.bits(),
            BFLOAT16::BFMLALB_Vd_Vn_Em16(opcode) => opcode.bits(),
            BFLOAT16::BFMLALB_Vd_Vn_Vm(opcode) => opcode.bits(),
            BFLOAT16::BFMLALT_Vd_Vn_Em16(opcode) => opcode.bits(),
            BFLOAT16::BFMLALT_Vd_Vn_Vm(opcode) => opcode.bits(),
            BFLOAT16::BFMMLA_Vd_Vn_Vm(opcode) => opcode.bits(),
        }
    }
}
impl InsnOpcode for ADDSUB_EXT {
    fn definition(&self) -> &'static Insn {
        match self {
            ADDSUB_EXT::ADDS_Rd_Rn_SP_Rm_EXT(opcode) => opcode.definition(),
            ADDSUB_EXT::ADD_Rd_SP_Rn_SP_Rm_EXT(opcode) => opcode.definition(),
            ADDSUB_EXT::SUBS_Rd_Rn_SP_Rm_EXT(opcode) => opcode.definition(),
            ADDSUB_EXT::SUB_Rd_SP_Rn_SP_Rm_EXT(opcode) => opcode.definition(),
        }
    }
    fn bits(&self) -> u32 {
        match self {
            ADDSUB_EXT::ADDS_Rd_Rn_SP_Rm_EXT(opcode) => opcode.bits(),
            ADDSUB_EXT::ADD_Rd_SP_Rn_SP_Rm_EXT(opcode) => opcode.bits(),
            ADDSUB_EXT::SUBS_Rd_Rn_SP_Rm_EXT(opcode) => opcode.bits(),
            ADDSUB_EXT::SUB_Rd_SP_Rn_SP_Rm_EXT(opcode) => opcode.bits(),
        }
    }
}
impl InsnOpcode for ASISDLSO {
    fn definition(&self) -> &'static Insn {
        match self {
            ASISDLSO::LD1R_LVt_AL_SIMD_ADDR_SIMPLE(opcode) => opcode.definition(),
            ASISDLSO::LD1_LEt_SIMD_ADDR_SIMPLE(opcode) => opcode.definition(),
            ASISDLSO::LD2R_LVt_AL_SIMD_ADDR_SIMPLE(opcode) => opcode.definition(),
            ASISDLSO::LD2_LEt_SIMD_ADDR_SIMPLE(opcode) => opcode.definition(),
            ASISDLSO::LD3R_LVt_AL_SIMD_ADDR_SIMPLE(opcode) => opcode.definition(),
            ASISDLSO::LD3_LEt_SIMD_ADDR_SIMPLE(opcode) => opcode.definition(),
            ASISDLSO::LD4R_LVt_AL_SIMD_ADDR_SIMPLE(opcode) => opcode.definition(),
            ASISDLSO::LD4_LEt_SIMD_ADDR_SIMPLE(opcode) => opcode.definition(),
            ASISDLSO::ST1_LEt_SIMD_ADDR_SIMPLE(opcode) => opcode.definition(),
            ASISDLSO::ST2_LEt_SIMD_ADDR_SIMPLE(opcode) => opcode.definition(),
            ASISDLSO::ST3_LEt_SIMD_ADDR_SIMPLE(opcode) => opcode.definition(),
            ASISDLSO::ST4_LEt_SIMD_ADDR_SIMPLE(opcode) => opcode.definition(),
        }
    }
    fn bits(&self) -> u32 {
        match self {
            ASISDLSO::LD1R_LVt_AL_SIMD_ADDR_SIMPLE(opcode) => opcode.bits(),
            ASISDLSO::LD1_LEt_SIMD_ADDR_SIMPLE(opcode) => opcode.bits(),
            ASISDLSO::LD2R_LVt_AL_SIMD_ADDR_SIMPLE(opcode) => opcode.bits(),
            ASISDLSO::LD2_LEt_SIMD_ADDR_SIMPLE(opcode) => opcode.bits(),
            ASISDLSO::LD3R_LVt_AL_SIMD_ADDR_SIMPLE(opcode) => opcode.bits(),
            ASISDLSO::LD3_LEt_SIMD_ADDR_SIMPLE(opcode) => opcode.bits(),
            ASISDLSO::LD4R_LVt_AL_SIMD_ADDR_SIMPLE(opcode) => opcode.bits(),
            ASISDLSO::LD4_LEt_SIMD_ADDR_SIMPLE(opcode) => opcode.bits(),
            ASISDLSO::ST1_LEt_SIMD_ADDR_SIMPLE(opcode) => opcode.bits(),
            ASISDLSO::ST2_LEt_SIMD_ADDR_SIMPLE(opcode) => opcode.bits(),
            ASISDLSO::ST3_LEt_SIMD_ADDR_SIMPLE(opcode) => opcode.bits(),
            ASISDLSO::ST4_LEt_SIMD_ADDR_SIMPLE(opcode) => opcode.bits(),
        }
    }
}
impl InsnOpcode for LDSTPAIR_OFF {
    fn definition(&self) -> &'static Insn {
        match self {
            LDSTPAIR_OFF::LDPSW_Rt_Rt2_ADDR_SIMM7(opcode) => opcode.definition(),
            LDSTPAIR_OFF::LDP_Ft_Ft2_ADDR_SIMM7(opcode) => opcode.definition(),
            LDSTPAIR_OFF::LDP_Rt_Rt2_ADDR_SIMM7(opcode) => opcode.definition(),
            LDSTPAIR_OFF::STGP_Rt_Rt2_ADDR_SIMM11(opcode) => opcode.definition(),
            LDSTPAIR_OFF::STP_Ft_Ft2_ADDR_SIMM7(opcode) => opcode.definition(),
            LDSTPAIR_OFF::STP_Rt_Rt2_ADDR_SIMM7(opcode) => opcode.definition(),
        }
    }
    fn bits(&self) -> u32 {
        match self {
            LDSTPAIR_OFF::LDPSW_Rt_Rt2_ADDR_SIMM7(opcode) => opcode.bits(),
            LDSTPAIR_OFF::LDP_Ft_Ft2_ADDR_SIMM7(opcode) => opcode.bits(),
            LDSTPAIR_OFF::LDP_Rt_Rt2_ADDR_SIMM7(opcode) => opcode.bits(),
            LDSTPAIR_OFF::STGP_Rt_Rt2_ADDR_SIMM11(opcode) => opcode.bits(),
            LDSTPAIR_OFF::STP_Ft_Ft2_ADDR_SIMM7(opcode) => opcode.bits(),
            LDSTPAIR_OFF::STP_Rt_Rt2_ADDR_SIMM7(opcode) => opcode.bits(),
        }
    }
}
impl InsnOpcode for FLOATDP2 {
    fn definition(&self) -> &'static Insn {
        match self {
            FLOATDP2::FADD_Fd_Fn_Fm(opcode) => opcode.definition(),
            FLOATDP2::FADD_Fd_S_S_Fn_S_S_Fm_S_S(opcode) => opcode.definition(),
            FLOATDP2::FDIV_Fd_Fn_Fm(opcode) => opcode.definition(),
            FLOATDP2::FDIV_Fd_S_S_Fn_S_S_Fm_S_S(opcode) => opcode.definition(),
            FLOATDP2::FMAXNM_Fd_Fn_Fm(opcode) => opcode.definition(),
            FLOATDP2::FMAXNM_Fd_S_S_Fn_S_S_Fm_S_S(opcode) => opcode.definition(),
            FLOATDP2::FMAX_Fd_Fn_Fm(opcode) => opcode.definition(),
            FLOATDP2::FMAX_Fd_S_S_Fn_S_S_Fm_S_S(opcode) => opcode.definition(),
            FLOATDP2::FMINNM_Fd_Fn_Fm(opcode) => opcode.definition(),
            FLOATDP2::FMINNM_Fd_S_S_Fn_S_S_Fm_S_S(opcode) => opcode.definition(),
            FLOATDP2::FMIN_Fd_Fn_Fm(opcode) => opcode.definition(),
            FLOATDP2::FMIN_Fd_S_S_Fn_S_S_Fm_S_S(opcode) => opcode.definition(),
            FLOATDP2::FMUL_Fd_Fn_Fm(opcode) => opcode.definition(),
            FLOATDP2::FMUL_Fd_S_S_Fn_S_S_Fm_S_S(opcode) => opcode.definition(),
            FLOATDP2::FNMUL_Fd_Fn_Fm(opcode) => opcode.definition(),
            FLOATDP2::FNMUL_Fd_S_S_Fn_S_S_Fm_S_S(opcode) => opcode.definition(),
            FLOATDP2::FSUB_Fd_Fn_Fm(opcode) => opcode.definition(),
            FLOATDP2::FSUB_Fd_S_S_Fn_S_S_Fm_S_S(opcode) => opcode.definition(),
        }
    }
    fn bits(&self) -> u32 {
        match self {
            FLOATDP2::FADD_Fd_Fn_Fm(opcode) => opcode.bits(),
            FLOATDP2::FADD_Fd_S_S_Fn_S_S_Fm_S_S(opcode) => opcode.bits(),
            FLOATDP2::FDIV_Fd_Fn_Fm(opcode) => opcode.bits(),
            FLOATDP2::FDIV_Fd_S_S_Fn_S_S_Fm_S_S(opcode) => opcode.bits(),
            FLOATDP2::FMAXNM_Fd_Fn_Fm(opcode) => opcode.bits(),
            FLOATDP2::FMAXNM_Fd_S_S_Fn_S_S_Fm_S_S(opcode) => opcode.bits(),
            FLOATDP2::FMAX_Fd_Fn_Fm(opcode) => opcode.bits(),
            FLOATDP2::FMAX_Fd_S_S_Fn_S_S_Fm_S_S(opcode) => opcode.bits(),
            FLOATDP2::FMINNM_Fd_Fn_Fm(opcode) => opcode.bits(),
            FLOATDP2::FMINNM_Fd_S_S_Fn_S_S_Fm_S_S(opcode) => opcode.bits(),
            FLOATDP2::FMIN_Fd_Fn_Fm(opcode) => opcode.bits(),
            FLOATDP2::FMIN_Fd_S_S_Fn_S_S_Fm_S_S(opcode) => opcode.bits(),
            FLOATDP2::FMUL_Fd_Fn_Fm(opcode) => opcode.bits(),
            FLOATDP2::FMUL_Fd_S_S_Fn_S_S_Fm_S_S(opcode) => opcode.bits(),
            FLOATDP2::FNMUL_Fd_Fn_Fm(opcode) => opcode.bits(),
            FLOATDP2::FNMUL_Fd_S_S_Fn_S_S_Fm_S_S(opcode) => opcode.bits(),
            FLOATDP2::FSUB_Fd_Fn_Fm(opcode) => opcode.bits(),
            FLOATDP2::FSUB_Fd_S_S_Fn_S_S_Fm_S_S(opcode) => opcode.bits(),
        }
    }
}
impl InsnOpcode for ASIMDMISC {
    fn definition(&self) -> &'static Insn {
        match self {
            ASIMDMISC::ABS_Vd_Vn(opcode) => opcode.definition(),
            ASIMDMISC::CLS_Vd_Vn(opcode) => opcode.definition(),
            ASIMDMISC::CLZ_Vd_Vn(opcode) => opcode.definition(),
            ASIMDMISC::CMEQ_Vd_Vn_IMM0(opcode) => opcode.definition(),
            ASIMDMISC::CMGE_Vd_Vn_IMM0(opcode) => opcode.definition(),
            ASIMDMISC::CMGT_Vd_Vn_IMM0(opcode) => opcode.definition(),
            ASIMDMISC::CMLE_Vd_Vn_IMM0(opcode) => opcode.definition(),
            ASIMDMISC::CMLT_Vd_Vn_IMM0(opcode) => opcode.definition(),
            ASIMDMISC::CNT_Vd_Vn(opcode) => opcode.definition(),
            ASIMDMISC::FABS_Vd_V_4H_Vn_V_4H(opcode) => opcode.definition(),
            ASIMDMISC::FABS_Vd_Vn(opcode) => opcode.definition(),
            ASIMDMISC::FCMEQ_Vd_V_4H_Vn_V_4H_FPIMM0(opcode) => opcode.definition(),
            ASIMDMISC::FCMEQ_Vd_Vn_FPIMM0(opcode) => opcode.definition(),
            ASIMDMISC::FCMGE_Vd_V_4H_Vn_V_4H_FPIMM0(opcode) => opcode.definition(),
            ASIMDMISC::FCMGE_Vd_Vn_FPIMM0(opcode) => opcode.definition(),
            ASIMDMISC::FCMGT_Vd_V_4H_Vn_V_4H_FPIMM0(opcode) => opcode.definition(),
            ASIMDMISC::FCMGT_Vd_Vn_FPIMM0(opcode) => opcode.definition(),
            ASIMDMISC::FCMLE_Vd_V_4H_Vn_V_4H_FPIMM0(opcode) => opcode.definition(),
            ASIMDMISC::FCMLE_Vd_Vn_FPIMM0(opcode) => opcode.definition(),
            ASIMDMISC::FCMLT_Vd_V_4H_Vn_V_4H_FPIMM0(opcode) => opcode.definition(),
            ASIMDMISC::FCMLT_Vd_Vn_FPIMM0(opcode) => opcode.definition(),
            ASIMDMISC::FCVTAS_Vd_V_4H_Vn_V_4H(opcode) => opcode.definition(),
            ASIMDMISC::FCVTAS_Vd_Vn(opcode) => opcode.definition(),
            ASIMDMISC::FCVTAU_Vd_V_4H_Vn_V_4H(opcode) => opcode.definition(),
            ASIMDMISC::FCVTAU_Vd_Vn(opcode) => opcode.definition(),
            ASIMDMISC::FCVTL2_Vd_Vn(opcode) => opcode.definition(),
            ASIMDMISC::FCVTL_Vd_Vn(opcode) => opcode.definition(),
            ASIMDMISC::FCVTMS_Vd_V_4H_Vn_V_4H(opcode) => opcode.definition(),
            ASIMDMISC::FCVTMS_Vd_Vn(opcode) => opcode.definition(),
            ASIMDMISC::FCVTMU_Vd_V_4H_Vn_V_4H(opcode) => opcode.definition(),
            ASIMDMISC::FCVTMU_Vd_Vn(opcode) => opcode.definition(),
            ASIMDMISC::FCVTN2_Vd_Vn(opcode) => opcode.definition(),
            ASIMDMISC::FCVTNS_Vd_V_4H_Vn_V_4H(opcode) => opcode.definition(),
            ASIMDMISC::FCVTNS_Vd_Vn(opcode) => opcode.definition(),
            ASIMDMISC::FCVTNU_Vd_V_4H_Vn_V_4H(opcode) => opcode.definition(),
            ASIMDMISC::FCVTNU_Vd_Vn(opcode) => opcode.definition(),
            ASIMDMISC::FCVTN_Vd_Vn(opcode) => opcode.definition(),
            ASIMDMISC::FCVTPS_Vd_V_4H_Vn_V_4H(opcode) => opcode.definition(),
            ASIMDMISC::FCVTPS_Vd_Vn(opcode) => opcode.definition(),
            ASIMDMISC::FCVTPU_Vd_V_4H_Vn_V_4H(opcode) => opcode.definition(),
            ASIMDMISC::FCVTPU_Vd_Vn(opcode) => opcode.definition(),
            ASIMDMISC::FCVTXN2_Vd_Vn(opcode) => opcode.definition(),
            ASIMDMISC::FCVTXN_Vd_Vn(opcode) => opcode.definition(),
            ASIMDMISC::FCVTZS_Vd_V_4H_Vn_V_4H(opcode) => opcode.definition(),
            ASIMDMISC::FCVTZS_Vd_Vn(opcode) => opcode.definition(),
            ASIMDMISC::FCVTZU_Vd_V_4H_Vn_V_4H(opcode) => opcode.definition(),
            ASIMDMISC::FCVTZU_Vd_Vn(opcode) => opcode.definition(),
            ASIMDMISC::FNEG_Vd_V_4H_Vn_V_4H(opcode) => opcode.definition(),
            ASIMDMISC::FNEG_Vd_Vn(opcode) => opcode.definition(),
            ASIMDMISC::FRECPE_Vd_V_4H_Vn_V_4H(opcode) => opcode.definition(),
            ASIMDMISC::FRECPE_Vd_Vn(opcode) => opcode.definition(),
            ASIMDMISC::FRINT32X_Vd_Vn(opcode) => opcode.definition(),
            ASIMDMISC::FRINT32Z_Vd_Vn(opcode) => opcode.definition(),
            ASIMDMISC::FRINT64X_Vd_Vn(opcode) => opcode.definition(),
            ASIMDMISC::FRINT64Z_Vd_Vn(opcode) => opcode.definition(),
            ASIMDMISC::FRINTA_Vd_V_4H_Vn_V_4H(opcode) => opcode.definition(),
            ASIMDMISC::FRINTA_Vd_Vn(opcode) => opcode.definition(),
            ASIMDMISC::FRINTI_Vd_V_4H_Vn_V_4H(opcode) => opcode.definition(),
            ASIMDMISC::FRINTI_Vd_Vn(opcode) => opcode.definition(),
            ASIMDMISC::FRINTM_Vd_V_4H_Vn_V_4H(opcode) => opcode.definition(),
            ASIMDMISC::FRINTM_Vd_Vn(opcode) => opcode.definition(),
            ASIMDMISC::FRINTN_Vd_V_4H_Vn_V_4H(opcode) => opcode.definition(),
            ASIMDMISC::FRINTN_Vd_Vn(opcode) => opcode.definition(),
            ASIMDMISC::FRINTP_Vd_V_4H_Vn_V_4H(opcode) => opcode.definition(),
            ASIMDMISC::FRINTP_Vd_Vn(opcode) => opcode.definition(),
            ASIMDMISC::FRINTX_Vd_V_4H_Vn_V_4H(opcode) => opcode.definition(),
            ASIMDMISC::FRINTX_Vd_Vn(opcode) => opcode.definition(),
            ASIMDMISC::FRINTZ_Vd_V_4H_Vn_V_4H(opcode) => opcode.definition(),
            ASIMDMISC::FRINTZ_Vd_Vn(opcode) => opcode.definition(),
            ASIMDMISC::FRSQRTE_Vd_V_4H_Vn_V_4H(opcode) => opcode.definition(),
            ASIMDMISC::FRSQRTE_Vd_Vn(opcode) => opcode.definition(),
            ASIMDMISC::FSQRT_Vd_V_4H_Vn_V_4H(opcode) => opcode.definition(),
            ASIMDMISC::FSQRT_Vd_Vn(opcode) => opcode.definition(),
            ASIMDMISC::NEG_Vd_Vn(opcode) => opcode.definition(),
            ASIMDMISC::NOT_Vd_Vn(opcode) => opcode.definition(),
            ASIMDMISC::RBIT_Vd_Vn(opcode) => opcode.definition(),
            ASIMDMISC::REV16_Vd_Vn(opcode) => opcode.definition(),
            ASIMDMISC::REV32_Vd_Vn(opcode) => opcode.definition(),
            ASIMDMISC::REV64_Vd_Vn(opcode) => opcode.definition(),
            ASIMDMISC::SADALP_Vd_Vn(opcode) => opcode.definition(),
            ASIMDMISC::SADDLP_Vd_Vn(opcode) => opcode.definition(),
            ASIMDMISC::SCVTF_Vd_V_4H_Vn_V_4H(opcode) => opcode.definition(),
            ASIMDMISC::SCVTF_Vd_Vn(opcode) => opcode.definition(),
            ASIMDMISC::SHLL2_Vd_Vn_SHLL_IMM(opcode) => opcode.definition(),
            ASIMDMISC::SHLL_Vd_Vn_SHLL_IMM(opcode) => opcode.definition(),
            ASIMDMISC::SQABS_Vd_Vn(opcode) => opcode.definition(),
            ASIMDMISC::SQNEG_Vd_Vn(opcode) => opcode.definition(),
            ASIMDMISC::SQXTN2_Vd_Vn(opcode) => opcode.definition(),
            ASIMDMISC::SQXTN_Vd_Vn(opcode) => opcode.definition(),
            ASIMDMISC::SQXTUN2_Vd_Vn(opcode) => opcode.definition(),
            ASIMDMISC::SQXTUN_Vd_Vn(opcode) => opcode.definition(),
            ASIMDMISC::SUQADD_Vd_Vn(opcode) => opcode.definition(),
            ASIMDMISC::UADALP_Vd_Vn(opcode) => opcode.definition(),
            ASIMDMISC::UADDLP_Vd_Vn(opcode) => opcode.definition(),
            ASIMDMISC::UCVTF_Vd_V_4H_Vn_V_4H(opcode) => opcode.definition(),
            ASIMDMISC::UCVTF_Vd_Vn(opcode) => opcode.definition(),
            ASIMDMISC::UQXTN2_Vd_Vn(opcode) => opcode.definition(),
            ASIMDMISC::UQXTN_Vd_Vn(opcode) => opcode.definition(),
            ASIMDMISC::URECPE_Vd_Vn(opcode) => opcode.definition(),
            ASIMDMISC::URSQRTE_Vd_Vn(opcode) => opcode.definition(),
            ASIMDMISC::USQADD_Vd_Vn(opcode) => opcode.definition(),
            ASIMDMISC::XTN2_Vd_Vn(opcode) => opcode.definition(),
            ASIMDMISC::XTN_Vd_Vn(opcode) => opcode.definition(),
        }
    }
    fn bits(&self) -> u32 {
        match self {
            ASIMDMISC::ABS_Vd_Vn(opcode) => opcode.bits(),
            ASIMDMISC::CLS_Vd_Vn(opcode) => opcode.bits(),
            ASIMDMISC::CLZ_Vd_Vn(opcode) => opcode.bits(),
            ASIMDMISC::CMEQ_Vd_Vn_IMM0(opcode) => opcode.bits(),
            ASIMDMISC::CMGE_Vd_Vn_IMM0(opcode) => opcode.bits(),
            ASIMDMISC::CMGT_Vd_Vn_IMM0(opcode) => opcode.bits(),
            ASIMDMISC::CMLE_Vd_Vn_IMM0(opcode) => opcode.bits(),
            ASIMDMISC::CMLT_Vd_Vn_IMM0(opcode) => opcode.bits(),
            ASIMDMISC::CNT_Vd_Vn(opcode) => opcode.bits(),
            ASIMDMISC::FABS_Vd_V_4H_Vn_V_4H(opcode) => opcode.bits(),
            ASIMDMISC::FABS_Vd_Vn(opcode) => opcode.bits(),
            ASIMDMISC::FCMEQ_Vd_V_4H_Vn_V_4H_FPIMM0(opcode) => opcode.bits(),
            ASIMDMISC::FCMEQ_Vd_Vn_FPIMM0(opcode) => opcode.bits(),
            ASIMDMISC::FCMGE_Vd_V_4H_Vn_V_4H_FPIMM0(opcode) => opcode.bits(),
            ASIMDMISC::FCMGE_Vd_Vn_FPIMM0(opcode) => opcode.bits(),
            ASIMDMISC::FCMGT_Vd_V_4H_Vn_V_4H_FPIMM0(opcode) => opcode.bits(),
            ASIMDMISC::FCMGT_Vd_Vn_FPIMM0(opcode) => opcode.bits(),
            ASIMDMISC::FCMLE_Vd_V_4H_Vn_V_4H_FPIMM0(opcode) => opcode.bits(),
            ASIMDMISC::FCMLE_Vd_Vn_FPIMM0(opcode) => opcode.bits(),
            ASIMDMISC::FCMLT_Vd_V_4H_Vn_V_4H_FPIMM0(opcode) => opcode.bits(),
            ASIMDMISC::FCMLT_Vd_Vn_FPIMM0(opcode) => opcode.bits(),
            ASIMDMISC::FCVTAS_Vd_V_4H_Vn_V_4H(opcode) => opcode.bits(),
            ASIMDMISC::FCVTAS_Vd_Vn(opcode) => opcode.bits(),
            ASIMDMISC::FCVTAU_Vd_V_4H_Vn_V_4H(opcode) => opcode.bits(),
            ASIMDMISC::FCVTAU_Vd_Vn(opcode) => opcode.bits(),
            ASIMDMISC::FCVTL2_Vd_Vn(opcode) => opcode.bits(),
            ASIMDMISC::FCVTL_Vd_Vn(opcode) => opcode.bits(),
            ASIMDMISC::FCVTMS_Vd_V_4H_Vn_V_4H(opcode) => opcode.bits(),
            ASIMDMISC::FCVTMS_Vd_Vn(opcode) => opcode.bits(),
            ASIMDMISC::FCVTMU_Vd_V_4H_Vn_V_4H(opcode) => opcode.bits(),
            ASIMDMISC::FCVTMU_Vd_Vn(opcode) => opcode.bits(),
            ASIMDMISC::FCVTN2_Vd_Vn(opcode) => opcode.bits(),
            ASIMDMISC::FCVTNS_Vd_V_4H_Vn_V_4H(opcode) => opcode.bits(),
            ASIMDMISC::FCVTNS_Vd_Vn(opcode) => opcode.bits(),
            ASIMDMISC::FCVTNU_Vd_V_4H_Vn_V_4H(opcode) => opcode.bits(),
            ASIMDMISC::FCVTNU_Vd_Vn(opcode) => opcode.bits(),
            ASIMDMISC::FCVTN_Vd_Vn(opcode) => opcode.bits(),
            ASIMDMISC::FCVTPS_Vd_V_4H_Vn_V_4H(opcode) => opcode.bits(),
            ASIMDMISC::FCVTPS_Vd_Vn(opcode) => opcode.bits(),
            ASIMDMISC::FCVTPU_Vd_V_4H_Vn_V_4H(opcode) => opcode.bits(),
            ASIMDMISC::FCVTPU_Vd_Vn(opcode) => opcode.bits(),
            ASIMDMISC::FCVTXN2_Vd_Vn(opcode) => opcode.bits(),
            ASIMDMISC::FCVTXN_Vd_Vn(opcode) => opcode.bits(),
            ASIMDMISC::FCVTZS_Vd_V_4H_Vn_V_4H(opcode) => opcode.bits(),
            ASIMDMISC::FCVTZS_Vd_Vn(opcode) => opcode.bits(),
            ASIMDMISC::FCVTZU_Vd_V_4H_Vn_V_4H(opcode) => opcode.bits(),
            ASIMDMISC::FCVTZU_Vd_Vn(opcode) => opcode.bits(),
            ASIMDMISC::FNEG_Vd_V_4H_Vn_V_4H(opcode) => opcode.bits(),
            ASIMDMISC::FNEG_Vd_Vn(opcode) => opcode.bits(),
            ASIMDMISC::FRECPE_Vd_V_4H_Vn_V_4H(opcode) => opcode.bits(),
            ASIMDMISC::FRECPE_Vd_Vn(opcode) => opcode.bits(),
            ASIMDMISC::FRINT32X_Vd_Vn(opcode) => opcode.bits(),
            ASIMDMISC::FRINT32Z_Vd_Vn(opcode) => opcode.bits(),
            ASIMDMISC::FRINT64X_Vd_Vn(opcode) => opcode.bits(),
            ASIMDMISC::FRINT64Z_Vd_Vn(opcode) => opcode.bits(),
            ASIMDMISC::FRINTA_Vd_V_4H_Vn_V_4H(opcode) => opcode.bits(),
            ASIMDMISC::FRINTA_Vd_Vn(opcode) => opcode.bits(),
            ASIMDMISC::FRINTI_Vd_V_4H_Vn_V_4H(opcode) => opcode.bits(),
            ASIMDMISC::FRINTI_Vd_Vn(opcode) => opcode.bits(),
            ASIMDMISC::FRINTM_Vd_V_4H_Vn_V_4H(opcode) => opcode.bits(),
            ASIMDMISC::FRINTM_Vd_Vn(opcode) => opcode.bits(),
            ASIMDMISC::FRINTN_Vd_V_4H_Vn_V_4H(opcode) => opcode.bits(),
            ASIMDMISC::FRINTN_Vd_Vn(opcode) => opcode.bits(),
            ASIMDMISC::FRINTP_Vd_V_4H_Vn_V_4H(opcode) => opcode.bits(),
            ASIMDMISC::FRINTP_Vd_Vn(opcode) => opcode.bits(),
            ASIMDMISC::FRINTX_Vd_V_4H_Vn_V_4H(opcode) => opcode.bits(),
            ASIMDMISC::FRINTX_Vd_Vn(opcode) => opcode.bits(),
            ASIMDMISC::FRINTZ_Vd_V_4H_Vn_V_4H(opcode) => opcode.bits(),
            ASIMDMISC::FRINTZ_Vd_Vn(opcode) => opcode.bits(),
            ASIMDMISC::FRSQRTE_Vd_V_4H_Vn_V_4H(opcode) => opcode.bits(),
            ASIMDMISC::FRSQRTE_Vd_Vn(opcode) => opcode.bits(),
            ASIMDMISC::FSQRT_Vd_V_4H_Vn_V_4H(opcode) => opcode.bits(),
            ASIMDMISC::FSQRT_Vd_Vn(opcode) => opcode.bits(),
            ASIMDMISC::NEG_Vd_Vn(opcode) => opcode.bits(),
            ASIMDMISC::NOT_Vd_Vn(opcode) => opcode.bits(),
            ASIMDMISC::RBIT_Vd_Vn(opcode) => opcode.bits(),
            ASIMDMISC::REV16_Vd_Vn(opcode) => opcode.bits(),
            ASIMDMISC::REV32_Vd_Vn(opcode) => opcode.bits(),
            ASIMDMISC::REV64_Vd_Vn(opcode) => opcode.bits(),
            ASIMDMISC::SADALP_Vd_Vn(opcode) => opcode.bits(),
            ASIMDMISC::SADDLP_Vd_Vn(opcode) => opcode.bits(),
            ASIMDMISC::SCVTF_Vd_V_4H_Vn_V_4H(opcode) => opcode.bits(),
            ASIMDMISC::SCVTF_Vd_Vn(opcode) => opcode.bits(),
            ASIMDMISC::SHLL2_Vd_Vn_SHLL_IMM(opcode) => opcode.bits(),
            ASIMDMISC::SHLL_Vd_Vn_SHLL_IMM(opcode) => opcode.bits(),
            ASIMDMISC::SQABS_Vd_Vn(opcode) => opcode.bits(),
            ASIMDMISC::SQNEG_Vd_Vn(opcode) => opcode.bits(),
            ASIMDMISC::SQXTN2_Vd_Vn(opcode) => opcode.bits(),
            ASIMDMISC::SQXTN_Vd_Vn(opcode) => opcode.bits(),
            ASIMDMISC::SQXTUN2_Vd_Vn(opcode) => opcode.bits(),
            ASIMDMISC::SQXTUN_Vd_Vn(opcode) => opcode.bits(),
            ASIMDMISC::SUQADD_Vd_Vn(opcode) => opcode.bits(),
            ASIMDMISC::UADALP_Vd_Vn(opcode) => opcode.bits(),
            ASIMDMISC::UADDLP_Vd_Vn(opcode) => opcode.bits(),
            ASIMDMISC::UCVTF_Vd_V_4H_Vn_V_4H(opcode) => opcode.bits(),
            ASIMDMISC::UCVTF_Vd_Vn(opcode) => opcode.bits(),
            ASIMDMISC::UQXTN2_Vd_Vn(opcode) => opcode.bits(),
            ASIMDMISC::UQXTN_Vd_Vn(opcode) => opcode.bits(),
            ASIMDMISC::URECPE_Vd_Vn(opcode) => opcode.bits(),
            ASIMDMISC::URSQRTE_Vd_Vn(opcode) => opcode.bits(),
            ASIMDMISC::USQADD_Vd_Vn(opcode) => opcode.bits(),
            ASIMDMISC::XTN2_Vd_Vn(opcode) => opcode.bits(),
            ASIMDMISC::XTN_Vd_Vn(opcode) => opcode.bits(),
        }
    }
}
impl InsnOpcode for EXTRACT {
    fn definition(&self) -> &'static Insn {
        match self {
            EXTRACT::EXTR_Rd_Rn_Rm_IMMS(opcode) => opcode.definition(),
        }
    }
    fn bits(&self) -> u32 {
        match self {
            EXTRACT::EXTR_Rd_Rn_Rm_IMMS(opcode) => opcode.bits(),
        }
    }
}
impl InsnOpcode for SVE_SIZE_SD {
    fn definition(&self) -> &'static Insn {
        match self {
            SVE_SIZE_SD::ADCLB_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_SIZE_SD::ADCLT_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_SIZE_SD::ADR_SVE_Zd_SVE_ADDR_ZZ_LSL(opcode) => opcode.definition(),
            SVE_SIZE_SD::CDOT_SVE_Zd_SVE_Zn_SVE_Zm_16_SVE_IMM_ROT2(opcode) => opcode.definition(),
            SVE_SIZE_SD::COMPACT_SVE_Zd_SVE_Pg3_SVE_Zn(opcode) => opcode.definition(),
            SVE_SIZE_SD::CTERMEQ_Rn_Rm(opcode) => opcode.definition(),
            SVE_SIZE_SD::CTERMNE_Rn_Rm(opcode) => opcode.definition(),
            SVE_SIZE_SD::HISTCNT_SVE_Zd_SVE_Pg3_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_SIZE_SD::REVH_SVE_Zd_SVE_Pg3_SVE_Zn(opcode) => opcode.definition(),
            SVE_SIZE_SD::SBCLB_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_SIZE_SD::SBCLT_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_SIZE_SD::SDIVR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(opcode) => opcode.definition(),
            SVE_SIZE_SD::SDIV_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(opcode) => opcode.definition(),
            SVE_SIZE_SD::SDOT_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_SIZE_SD::SXTH_SVE_Zd_SVE_Pg3_SVE_Zn(opcode) => opcode.definition(),
            SVE_SIZE_SD::UDIVR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(opcode) => opcode.definition(),
            SVE_SIZE_SD::UDIV_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(opcode) => opcode.definition(),
            SVE_SIZE_SD::UDOT_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_SIZE_SD::UXTH_SVE_Zd_SVE_Pg3_SVE_Zn(opcode) => opcode.definition(),
        }
    }
    fn bits(&self) -> u32 {
        match self {
            SVE_SIZE_SD::ADCLB_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_SIZE_SD::ADCLT_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_SIZE_SD::ADR_SVE_Zd_SVE_ADDR_ZZ_LSL(opcode) => opcode.bits(),
            SVE_SIZE_SD::CDOT_SVE_Zd_SVE_Zn_SVE_Zm_16_SVE_IMM_ROT2(opcode) => opcode.bits(),
            SVE_SIZE_SD::COMPACT_SVE_Zd_SVE_Pg3_SVE_Zn(opcode) => opcode.bits(),
            SVE_SIZE_SD::CTERMEQ_Rn_Rm(opcode) => opcode.bits(),
            SVE_SIZE_SD::CTERMNE_Rn_Rm(opcode) => opcode.bits(),
            SVE_SIZE_SD::HISTCNT_SVE_Zd_SVE_Pg3_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_SIZE_SD::REVH_SVE_Zd_SVE_Pg3_SVE_Zn(opcode) => opcode.bits(),
            SVE_SIZE_SD::SBCLB_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_SIZE_SD::SBCLT_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_SIZE_SD::SDIVR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(opcode) => opcode.bits(),
            SVE_SIZE_SD::SDIV_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(opcode) => opcode.bits(),
            SVE_SIZE_SD::SDOT_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_SIZE_SD::SXTH_SVE_Zd_SVE_Pg3_SVE_Zn(opcode) => opcode.bits(),
            SVE_SIZE_SD::UDIVR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(opcode) => opcode.bits(),
            SVE_SIZE_SD::UDIV_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(opcode) => opcode.bits(),
            SVE_SIZE_SD::UDOT_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_SIZE_SD::UXTH_SVE_Zd_SVE_Pg3_SVE_Zn(opcode) => opcode.bits(),
        }
    }
}
impl InsnOpcode for SVE_SIZE_BHSD {
    fn definition(&self) -> &'static Insn {
        match self {
            SVE_SIZE_BHSD::ABS_SVE_Zd_SVE_Pg3_SVE_Zn(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::ADDP_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::ADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::ADD_SVE_Zd_SVE_Zd_SVE_AIMM(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::ADD_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::ANDV_SVE_Vd_SVE_Pg3_SVE_Zn(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::AND_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::ASRR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::ASR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::BDEP_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::BEXT_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::BGRP_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::BIC_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::CADD_SVE_Zd_SVE_Zd_SVE_Zn_SVE_IMM_ROT3(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::CLASTA_Rd_SVE_Pg3_Rd_SVE_Zm_5(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::CLASTA_SVE_Vd_SVE_Pg3_SVE_Vd_SVE_Zm_5(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::CLASTA_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::CLASTB_Rd_SVE_Pg3_Rd_SVE_Zm_5(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::CLASTB_SVE_Vd_SVE_Pg3_SVE_Vd_SVE_Zm_5(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::CLASTB_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::CLS_SVE_Zd_SVE_Pg3_SVE_Zn(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::CLZ_SVE_Zd_SVE_Pg3_SVE_Zn(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::CMLA_SVE_Zd_SVE_Zn_SVE_Zm_16_SVE_IMM_ROT2(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::CMPEQ_SVE_Pd_SVE_Pg3_SVE_Zn_SIMM5(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::CMPEQ_SVE_Pd_S_B_SVE_Pg3_P_Z_SVE_Zn_S_B_SVE_Zm_16_S_B(opcode) => {
                opcode.definition()
            }
            SVE_SIZE_BHSD::CMPGE_SVE_Pd_SVE_Pg3_SVE_Zn_SIMM5(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::CMPGE_SVE_Pd_S_B_SVE_Pg3_P_Z_SVE_Zn_S_B_SVE_Zm_16_S_B(opcode) => {
                opcode.definition()
            }
            SVE_SIZE_BHSD::CMPGT_SVE_Pd_SVE_Pg3_SVE_Zn_SIMM5(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::CMPGT_SVE_Pd_S_B_SVE_Pg3_P_Z_SVE_Zn_S_B_SVE_Zm_16_S_B(opcode) => {
                opcode.definition()
            }
            SVE_SIZE_BHSD::CMPHI_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_UIMM7(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::CMPHI_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::CMPHS_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_UIMM7(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::CMPHS_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::CMPLE_SVE_Pd_SVE_Pg3_SVE_Zn_SIMM5(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::CMPLO_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_UIMM7(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::CMPLS_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_UIMM7(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::CMPLT_SVE_Pd_SVE_Pg3_SVE_Zn_SIMM5(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::CMPNE_SVE_Pd_SVE_Pg3_SVE_Zn_SIMM5(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::CMPNE_SVE_Pd_S_B_SVE_Pg3_P_Z_SVE_Zn_S_B_SVE_Zm_16_S_B(opcode) => {
                opcode.definition()
            }
            SVE_SIZE_BHSD::CNOT_SVE_Zd_SVE_Pg3_SVE_Zn(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::CNTP_Rd_SVE_Pg4_10_SVE_Pn(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::CNT_SVE_Zd_SVE_Pg3_SVE_Zn(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::CPY_SVE_Zd_SVE_Pg3_Rn_SP(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::CPY_SVE_Zd_SVE_Pg3_SVE_Vn(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::DECP_Rd_SVE_Pg4_5(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::DUP_SVE_Zd_Rn_SP(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::DUP_SVE_Zd_SVE_ASIMM(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::EORBT_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::EORTB_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::EORV_SVE_Vd_SVE_Pg3_SVE_Zn(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::EOR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::INCP_Rd_SVE_Pg4_5(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::INDEX_SVE_Zd_Rn_Rm(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::INDEX_SVE_Zd_Rn_SIMM5(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::INDEX_SVE_Zd_SVE_SIMM5_Rm(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::INDEX_SVE_Zd_SVE_SIMM5_SVE_SIMM5B(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::INSR_SVE_Zd_SVE_Rm(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::INSR_SVE_Zd_SVE_Vm(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::LASTA_Rd_SVE_Pg3_SVE_Zn(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::LASTA_SVE_Vd_SVE_Pg3_SVE_Zn(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::LASTB_Rd_SVE_Pg3_SVE_Zn(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::LASTB_SVE_Vd_SVE_Pg3_SVE_Zn(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::LSLR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::LSL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::LSRR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::LSR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::MAD_SVE_Zd_SVE_Pg3_SVE_Zm_16_SVE_Za_5(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::MLA_SVE_Zd_SVE_Pg3_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::MLS_SVE_Zd_SVE_Pg3_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::MSB_SVE_Zd_SVE_Pg3_SVE_Zm_16_SVE_Za_5(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::MUL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::MUL_SVE_Zd_SVE_Zd_SVE_SIMM8(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::MUL_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::NEG_SVE_Zd_SVE_Pg3_SVE_Zn(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::NOT_SVE_Zd_SVE_Pg3_SVE_Zn(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::ORR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::ORV_SVE_Vd_SVE_Pg3_SVE_Zn(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::PNEXT_SVE_Pd_SVE_Pg4_5_SVE_Pd(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::PTRUES_SVE_Pd_SVE_PATTERN(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::PTRUE_SVE_Pd_SVE_PATTERN(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::RBIT_SVE_Zd_SVE_Pg3_SVE_Zn(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::REV_SVE_Pd_SVE_Pn(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::REV_SVE_Zd_SVE_Zn(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::SABA_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::SABD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::SCLAMP_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::SEL_SVE_Zd_SVE_Pg4_10_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::SHADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::SHSUBR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::SHSUB_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::SMAXP_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::SMAXV_SVE_Vd_SVE_Pg3_SVE_Zn(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::SMAX_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::SMAX_SVE_Zd_SVE_Zd_SVE_SIMM8(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::SMINP_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::SMINV_SVE_Vd_SVE_Pg3_SVE_Zn(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::SMIN_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::SMIN_SVE_Zd_SVE_Zd_SVE_SIMM8(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::SMULH_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::SMULH_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::SPLICE_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::SPLICE_SVE_Zd_SVE_Pg3_SVE_ZnxN(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::SQABS_SVE_Zd_SVE_Pg3_SVE_Zn(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::SQADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::SQADD_SVE_Zd_SVE_Zd_SVE_AIMM(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::SQADD_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::SQCADD_SVE_Zd_SVE_Zd_SVE_Zn_SVE_IMM_ROT3(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::SQDECP_Rd_SVE_Pg4_5(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::SQDECP_Rd_SVE_Pg4_5_Rd(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::SQDMULH_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::SQINCP_Rd_SVE_Pg4_5(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::SQINCP_Rd_SVE_Pg4_5_Rd(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::SQNEG_SVE_Zd_SVE_Pg3_SVE_Zn(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::SQRDCMLAH_SVE_Zd_SVE_Zn_SVE_Zm_16_SVE_IMM_ROT2(opcode) => {
                opcode.definition()
            }
            SVE_SIZE_BHSD::SQRDMLAH_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::SQRDMLSH_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::SQRDMULH_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::SQRSHLR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::SQRSHL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::SQSHLR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::SQSHL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::SQSUBR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::SQSUB_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::SQSUB_SVE_Zd_SVE_Zd_SVE_AIMM(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::SQSUB_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::SRHADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::SRSHLR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::SRSHL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::SUBR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::SUBR_SVE_Zd_SVE_Zd_SVE_AIMM(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::SUB_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::SUB_SVE_Zd_SVE_Zd_SVE_AIMM(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::SUB_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::SUQADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::TBL_SVE_Zd_SVE_ZnxN_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::TBL_SVE_Zd_S_B_SVE_ZnxN_S_B_SVE_Zm_16_S_B(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::TBX_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::TRN1_SVE_Pd_SVE_Pn_SVE_Pm(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::TRN1_SVE_Zd_S_B_SVE_Zn_S_B_SVE_Zm_16_S_B(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::TRN2_SVE_Pd_SVE_Pn_SVE_Pm(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::TRN2_SVE_Zd_S_B_SVE_Zn_S_B_SVE_Zm_16_S_B(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::UABA_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::UABD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::UADDV_SVE_Vd_SVE_Pg3_SVE_Zn(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::UCLAMP_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::UHADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::UHSUBR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::UHSUB_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::UMAXP_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::UMAXV_SVE_Vd_SVE_Pg3_SVE_Zn(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::UMAX_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::UMAX_SVE_Zd_SVE_Zd_SVE_UIMM8(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::UMINP_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::UMINV_SVE_Vd_SVE_Pg3_SVE_Zn(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::UMIN_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::UMIN_SVE_Zd_SVE_Zd_SVE_UIMM8(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::UMULH_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::UMULH_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::UQADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::UQADD_SVE_Zd_SVE_Zd_SVE_AIMM(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::UQADD_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::UQDECP_Rd_SVE_Pg4_5(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::UQDECP_Rd_X_SVE_Pg4_5_S_B(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::UQINCP_Rd_SVE_Pg4_5(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::UQINCP_Rd_X_SVE_Pg4_5_S_B(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::UQRSHLR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::UQRSHL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::UQSHLR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::UQSHL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::UQSUBR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::UQSUB_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::UQSUB_SVE_Zd_SVE_Zd_SVE_AIMM(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::UQSUB_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::URHADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::URSHLR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::URSHL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::USQADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::UZP1_SVE_Pd_SVE_Pn_SVE_Pm(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::UZP1_SVE_Zd_S_B_SVE_Zn_S_B_SVE_Zm_16_S_B(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::UZP2_SVE_Pd_SVE_Pn_SVE_Pm(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::UZP2_SVE_Zd_S_B_SVE_Zn_S_B_SVE_Zm_16_S_B(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::WHILEGE_SVE_Pd_Rn_Rm(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::WHILEGE_SVE_Pd_S_B_Rn_X_Rm_X(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::WHILEGT_SVE_Pd_Rn_Rm(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::WHILEGT_SVE_Pd_S_B_Rn_X_Rm_X(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::WHILEHI_SVE_Pd_Rn_Rm(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::WHILEHI_SVE_Pd_S_B_Rn_X_Rm_X(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::WHILEHS_SVE_Pd_Rn_Rm(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::WHILEHS_SVE_Pd_S_B_Rn_X_Rm_X(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::WHILELE_SVE_Pd_Rn_Rm(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::WHILELE_SVE_Pd_S_B_Rn_X_Rm_X(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::WHILELO_SVE_Pd_Rn_Rm(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::WHILELO_SVE_Pd_S_B_Rn_X_Rm_X(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::WHILELS_SVE_Pd_Rn_Rm(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::WHILELS_SVE_Pd_S_B_Rn_X_Rm_X(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::WHILELT_SVE_Pd_Rn_Rm(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::WHILELT_SVE_Pd_S_B_Rn_X_Rm_X(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::WHILERW_SVE_Pd_Rn_Rm(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::WHILEWR_SVE_Pd_Rn_Rm(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::ZIP1_SVE_Pd_SVE_Pn_SVE_Pm(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::ZIP1_SVE_Zd_S_B_SVE_Zn_S_B_SVE_Zm_16_S_B(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::ZIP2_SVE_Pd_SVE_Pn_SVE_Pm(opcode) => opcode.definition(),
            SVE_SIZE_BHSD::ZIP2_SVE_Zd_S_B_SVE_Zn_S_B_SVE_Zm_16_S_B(opcode) => opcode.definition(),
        }
    }
    fn bits(&self) -> u32 {
        match self {
            SVE_SIZE_BHSD::ABS_SVE_Zd_SVE_Pg3_SVE_Zn(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::ADDP_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::ADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::ADD_SVE_Zd_SVE_Zd_SVE_AIMM(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::ADD_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::ANDV_SVE_Vd_SVE_Pg3_SVE_Zn(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::AND_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::ASRR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::ASR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::BDEP_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::BEXT_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::BGRP_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::BIC_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::CADD_SVE_Zd_SVE_Zd_SVE_Zn_SVE_IMM_ROT3(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::CLASTA_Rd_SVE_Pg3_Rd_SVE_Zm_5(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::CLASTA_SVE_Vd_SVE_Pg3_SVE_Vd_SVE_Zm_5(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::CLASTA_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::CLASTB_Rd_SVE_Pg3_Rd_SVE_Zm_5(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::CLASTB_SVE_Vd_SVE_Pg3_SVE_Vd_SVE_Zm_5(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::CLASTB_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::CLS_SVE_Zd_SVE_Pg3_SVE_Zn(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::CLZ_SVE_Zd_SVE_Pg3_SVE_Zn(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::CMLA_SVE_Zd_SVE_Zn_SVE_Zm_16_SVE_IMM_ROT2(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::CMPEQ_SVE_Pd_SVE_Pg3_SVE_Zn_SIMM5(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::CMPEQ_SVE_Pd_S_B_SVE_Pg3_P_Z_SVE_Zn_S_B_SVE_Zm_16_S_B(opcode) => {
                opcode.bits()
            }
            SVE_SIZE_BHSD::CMPGE_SVE_Pd_SVE_Pg3_SVE_Zn_SIMM5(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::CMPGE_SVE_Pd_S_B_SVE_Pg3_P_Z_SVE_Zn_S_B_SVE_Zm_16_S_B(opcode) => {
                opcode.bits()
            }
            SVE_SIZE_BHSD::CMPGT_SVE_Pd_SVE_Pg3_SVE_Zn_SIMM5(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::CMPGT_SVE_Pd_S_B_SVE_Pg3_P_Z_SVE_Zn_S_B_SVE_Zm_16_S_B(opcode) => {
                opcode.bits()
            }
            SVE_SIZE_BHSD::CMPHI_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_UIMM7(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::CMPHI_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::CMPHS_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_UIMM7(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::CMPHS_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::CMPLE_SVE_Pd_SVE_Pg3_SVE_Zn_SIMM5(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::CMPLO_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_UIMM7(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::CMPLS_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_UIMM7(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::CMPLT_SVE_Pd_SVE_Pg3_SVE_Zn_SIMM5(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::CMPNE_SVE_Pd_SVE_Pg3_SVE_Zn_SIMM5(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::CMPNE_SVE_Pd_S_B_SVE_Pg3_P_Z_SVE_Zn_S_B_SVE_Zm_16_S_B(opcode) => {
                opcode.bits()
            }
            SVE_SIZE_BHSD::CNOT_SVE_Zd_SVE_Pg3_SVE_Zn(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::CNTP_Rd_SVE_Pg4_10_SVE_Pn(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::CNT_SVE_Zd_SVE_Pg3_SVE_Zn(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::CPY_SVE_Zd_SVE_Pg3_Rn_SP(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::CPY_SVE_Zd_SVE_Pg3_SVE_Vn(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::DECP_Rd_SVE_Pg4_5(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::DUP_SVE_Zd_Rn_SP(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::DUP_SVE_Zd_SVE_ASIMM(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::EORBT_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::EORTB_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::EORV_SVE_Vd_SVE_Pg3_SVE_Zn(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::EOR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::INCP_Rd_SVE_Pg4_5(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::INDEX_SVE_Zd_Rn_Rm(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::INDEX_SVE_Zd_Rn_SIMM5(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::INDEX_SVE_Zd_SVE_SIMM5_Rm(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::INDEX_SVE_Zd_SVE_SIMM5_SVE_SIMM5B(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::INSR_SVE_Zd_SVE_Rm(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::INSR_SVE_Zd_SVE_Vm(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::LASTA_Rd_SVE_Pg3_SVE_Zn(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::LASTA_SVE_Vd_SVE_Pg3_SVE_Zn(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::LASTB_Rd_SVE_Pg3_SVE_Zn(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::LASTB_SVE_Vd_SVE_Pg3_SVE_Zn(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::LSLR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::LSL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::LSRR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::LSR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::MAD_SVE_Zd_SVE_Pg3_SVE_Zm_16_SVE_Za_5(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::MLA_SVE_Zd_SVE_Pg3_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::MLS_SVE_Zd_SVE_Pg3_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::MSB_SVE_Zd_SVE_Pg3_SVE_Zm_16_SVE_Za_5(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::MUL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::MUL_SVE_Zd_SVE_Zd_SVE_SIMM8(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::MUL_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::NEG_SVE_Zd_SVE_Pg3_SVE_Zn(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::NOT_SVE_Zd_SVE_Pg3_SVE_Zn(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::ORR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::ORV_SVE_Vd_SVE_Pg3_SVE_Zn(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::PNEXT_SVE_Pd_SVE_Pg4_5_SVE_Pd(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::PTRUES_SVE_Pd_SVE_PATTERN(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::PTRUE_SVE_Pd_SVE_PATTERN(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::RBIT_SVE_Zd_SVE_Pg3_SVE_Zn(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::REV_SVE_Pd_SVE_Pn(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::REV_SVE_Zd_SVE_Zn(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::SABA_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::SABD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::SCLAMP_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::SEL_SVE_Zd_SVE_Pg4_10_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::SHADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::SHSUBR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::SHSUB_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::SMAXP_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::SMAXV_SVE_Vd_SVE_Pg3_SVE_Zn(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::SMAX_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::SMAX_SVE_Zd_SVE_Zd_SVE_SIMM8(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::SMINP_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::SMINV_SVE_Vd_SVE_Pg3_SVE_Zn(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::SMIN_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::SMIN_SVE_Zd_SVE_Zd_SVE_SIMM8(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::SMULH_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::SMULH_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::SPLICE_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::SPLICE_SVE_Zd_SVE_Pg3_SVE_ZnxN(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::SQABS_SVE_Zd_SVE_Pg3_SVE_Zn(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::SQADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::SQADD_SVE_Zd_SVE_Zd_SVE_AIMM(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::SQADD_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::SQCADD_SVE_Zd_SVE_Zd_SVE_Zn_SVE_IMM_ROT3(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::SQDECP_Rd_SVE_Pg4_5(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::SQDECP_Rd_SVE_Pg4_5_Rd(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::SQDMULH_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::SQINCP_Rd_SVE_Pg4_5(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::SQINCP_Rd_SVE_Pg4_5_Rd(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::SQNEG_SVE_Zd_SVE_Pg3_SVE_Zn(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::SQRDCMLAH_SVE_Zd_SVE_Zn_SVE_Zm_16_SVE_IMM_ROT2(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::SQRDMLAH_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::SQRDMLSH_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::SQRDMULH_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::SQRSHLR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::SQRSHL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::SQSHLR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::SQSHL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::SQSUBR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::SQSUB_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::SQSUB_SVE_Zd_SVE_Zd_SVE_AIMM(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::SQSUB_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::SRHADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::SRSHLR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::SRSHL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::SUBR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::SUBR_SVE_Zd_SVE_Zd_SVE_AIMM(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::SUB_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::SUB_SVE_Zd_SVE_Zd_SVE_AIMM(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::SUB_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::SUQADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::TBL_SVE_Zd_SVE_ZnxN_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::TBL_SVE_Zd_S_B_SVE_ZnxN_S_B_SVE_Zm_16_S_B(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::TBX_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::TRN1_SVE_Pd_SVE_Pn_SVE_Pm(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::TRN1_SVE_Zd_S_B_SVE_Zn_S_B_SVE_Zm_16_S_B(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::TRN2_SVE_Pd_SVE_Pn_SVE_Pm(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::TRN2_SVE_Zd_S_B_SVE_Zn_S_B_SVE_Zm_16_S_B(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::UABA_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::UABD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::UADDV_SVE_Vd_SVE_Pg3_SVE_Zn(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::UCLAMP_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::UHADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::UHSUBR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::UHSUB_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::UMAXP_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::UMAXV_SVE_Vd_SVE_Pg3_SVE_Zn(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::UMAX_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::UMAX_SVE_Zd_SVE_Zd_SVE_UIMM8(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::UMINP_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::UMINV_SVE_Vd_SVE_Pg3_SVE_Zn(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::UMIN_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::UMIN_SVE_Zd_SVE_Zd_SVE_UIMM8(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::UMULH_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::UMULH_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::UQADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::UQADD_SVE_Zd_SVE_Zd_SVE_AIMM(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::UQADD_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::UQDECP_Rd_SVE_Pg4_5(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::UQDECP_Rd_X_SVE_Pg4_5_S_B(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::UQINCP_Rd_SVE_Pg4_5(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::UQINCP_Rd_X_SVE_Pg4_5_S_B(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::UQRSHLR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::UQRSHL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::UQSHLR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::UQSHL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::UQSUBR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::UQSUB_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::UQSUB_SVE_Zd_SVE_Zd_SVE_AIMM(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::UQSUB_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::URHADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::URSHLR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::URSHL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::USQADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::UZP1_SVE_Pd_SVE_Pn_SVE_Pm(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::UZP1_SVE_Zd_S_B_SVE_Zn_S_B_SVE_Zm_16_S_B(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::UZP2_SVE_Pd_SVE_Pn_SVE_Pm(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::UZP2_SVE_Zd_S_B_SVE_Zn_S_B_SVE_Zm_16_S_B(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::WHILEGE_SVE_Pd_Rn_Rm(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::WHILEGE_SVE_Pd_S_B_Rn_X_Rm_X(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::WHILEGT_SVE_Pd_Rn_Rm(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::WHILEGT_SVE_Pd_S_B_Rn_X_Rm_X(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::WHILEHI_SVE_Pd_Rn_Rm(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::WHILEHI_SVE_Pd_S_B_Rn_X_Rm_X(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::WHILEHS_SVE_Pd_Rn_Rm(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::WHILEHS_SVE_Pd_S_B_Rn_X_Rm_X(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::WHILELE_SVE_Pd_Rn_Rm(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::WHILELE_SVE_Pd_S_B_Rn_X_Rm_X(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::WHILELO_SVE_Pd_Rn_Rm(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::WHILELO_SVE_Pd_S_B_Rn_X_Rm_X(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::WHILELS_SVE_Pd_Rn_Rm(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::WHILELS_SVE_Pd_S_B_Rn_X_Rm_X(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::WHILELT_SVE_Pd_Rn_Rm(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::WHILELT_SVE_Pd_S_B_Rn_X_Rm_X(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::WHILERW_SVE_Pd_Rn_Rm(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::WHILEWR_SVE_Pd_Rn_Rm(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::ZIP1_SVE_Pd_SVE_Pn_SVE_Pm(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::ZIP1_SVE_Zd_S_B_SVE_Zn_S_B_SVE_Zm_16_S_B(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::ZIP2_SVE_Pd_SVE_Pn_SVE_Pm(opcode) => opcode.bits(),
            SVE_SIZE_BHSD::ZIP2_SVE_Zd_S_B_SVE_Zn_S_B_SVE_Zm_16_S_B(opcode) => opcode.bits(),
        }
    }
}
impl InsnOpcode for SVE_SIZE_HSD2 {
    fn definition(&self) -> &'static Insn {
        match self {
            SVE_SIZE_HSD2::FLOGB_SVE_Zd_SVE_Pg3_SVE_Zn(opcode) => opcode.definition(),
        }
    }
    fn bits(&self) -> u32 {
        match self {
            SVE_SIZE_HSD2::FLOGB_SVE_Zd_SVE_Pg3_SVE_Zn(opcode) => opcode.bits(),
        }
    }
}
impl InsnOpcode for ADDSUB_IMM {
    fn definition(&self) -> &'static Insn {
        match self {
            ADDSUB_IMM::ADDG_Rd_SP_Rn_SP_UIMM10_UIMM4_ADDG(opcode) => opcode.definition(),
            ADDSUB_IMM::ADDS_Rd_Rn_SP_AIMM(opcode) => opcode.definition(),
            ADDSUB_IMM::ADD_Rd_SP_Rn_SP_AIMM(opcode) => opcode.definition(),
            ADDSUB_IMM::SUBG_Rd_SP_Rn_SP_UIMM10_UIMM4_ADDG(opcode) => opcode.definition(),
            ADDSUB_IMM::SUBS_Rd_Rn_SP_AIMM(opcode) => opcode.definition(),
            ADDSUB_IMM::SUB_Rd_SP_Rn_SP_AIMM(opcode) => opcode.definition(),
        }
    }
    fn bits(&self) -> u32 {
        match self {
            ADDSUB_IMM::ADDG_Rd_SP_Rn_SP_UIMM10_UIMM4_ADDG(opcode) => opcode.bits(),
            ADDSUB_IMM::ADDS_Rd_Rn_SP_AIMM(opcode) => opcode.bits(),
            ADDSUB_IMM::ADD_Rd_SP_Rn_SP_AIMM(opcode) => opcode.bits(),
            ADDSUB_IMM::SUBG_Rd_SP_Rn_SP_UIMM10_UIMM4_ADDG(opcode) => opcode.bits(),
            ADDSUB_IMM::SUBS_Rd_Rn_SP_AIMM(opcode) => opcode.bits(),
            ADDSUB_IMM::SUB_Rd_SP_Rn_SP_AIMM(opcode) => opcode.bits(),
        }
    }
}
impl InsnOpcode for ASISDPAIR {
    fn definition(&self) -> &'static Insn {
        match self {
            ASISDPAIR::ADDP_Sd_Vn(opcode) => opcode.definition(),
            ASISDPAIR::FADDP_Sd_S_S_Vn_V_2S(opcode) => opcode.definition(),
            ASISDPAIR::FADDP_Sd_Vn(opcode) => opcode.definition(),
            ASISDPAIR::FMAXNMP_Sd_S_S_Vn_V_2S(opcode) => opcode.definition(),
            ASISDPAIR::FMAXNMP_Sd_Vn(opcode) => opcode.definition(),
            ASISDPAIR::FMAXP_Sd_S_S_Vn_V_2S(opcode) => opcode.definition(),
            ASISDPAIR::FMAXP_Sd_Vn(opcode) => opcode.definition(),
            ASISDPAIR::FMINNMP_Sd_S_S_Vn_V_2S(opcode) => opcode.definition(),
            ASISDPAIR::FMINNMP_Sd_Vn(opcode) => opcode.definition(),
            ASISDPAIR::FMINP_Sd_S_S_Vn_V_2S(opcode) => opcode.definition(),
            ASISDPAIR::FMINP_Sd_Vn(opcode) => opcode.definition(),
        }
    }
    fn bits(&self) -> u32 {
        match self {
            ASISDPAIR::ADDP_Sd_Vn(opcode) => opcode.bits(),
            ASISDPAIR::FADDP_Sd_S_S_Vn_V_2S(opcode) => opcode.bits(),
            ASISDPAIR::FADDP_Sd_Vn(opcode) => opcode.bits(),
            ASISDPAIR::FMAXNMP_Sd_S_S_Vn_V_2S(opcode) => opcode.bits(),
            ASISDPAIR::FMAXNMP_Sd_Vn(opcode) => opcode.bits(),
            ASISDPAIR::FMAXP_Sd_S_S_Vn_V_2S(opcode) => opcode.bits(),
            ASISDPAIR::FMAXP_Sd_Vn(opcode) => opcode.bits(),
            ASISDPAIR::FMINNMP_Sd_S_S_Vn_V_2S(opcode) => opcode.bits(),
            ASISDPAIR::FMINNMP_Sd_Vn(opcode) => opcode.bits(),
            ASISDPAIR::FMINP_Sd_S_S_Vn_V_2S(opcode) => opcode.bits(),
            ASISDPAIR::FMINP_Sd_Vn(opcode) => opcode.bits(),
        }
    }
}
impl InsnOpcode for SME_SZ_23 {
    fn definition(&self) -> &'static Insn {
        match self {
            SME_SZ_23::SQCVTN_SVE_Zd_SME_Znx4(opcode) => opcode.definition(),
            SME_SZ_23::SQCVTUN_SVE_Zd_SME_Znx4(opcode) => opcode.definition(),
            SME_SZ_23::SQCVTU_SVE_Zd_SME_Znx4(opcode) => opcode.definition(),
            SME_SZ_23::SQCVT_SVE_Zd_SME_Znx4(opcode) => opcode.definition(),
            SME_SZ_23::UQCVTN_SVE_Zd_SME_Znx4(opcode) => opcode.definition(),
            SME_SZ_23::UQCVT_SVE_Zd_SME_Znx4(opcode) => opcode.definition(),
        }
    }
    fn bits(&self) -> u32 {
        match self {
            SME_SZ_23::SQCVTN_SVE_Zd_SME_Znx4(opcode) => opcode.bits(),
            SME_SZ_23::SQCVTUN_SVE_Zd_SME_Znx4(opcode) => opcode.bits(),
            SME_SZ_23::SQCVTU_SVE_Zd_SME_Znx4(opcode) => opcode.bits(),
            SME_SZ_23::SQCVT_SVE_Zd_SME_Znx4(opcode) => opcode.bits(),
            SME_SZ_23::UQCVTN_SVE_Zd_SME_Znx4(opcode) => opcode.bits(),
            SME_SZ_23::UQCVT_SVE_Zd_SME_Znx4(opcode) => opcode.bits(),
        }
    }
}
impl InsnOpcode for SME_MISC {
    fn definition(&self) -> &'static Insn {
        match self {
            SME_MISC::ADDHA_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn(opcode) => opcode.definition(),
            SME_MISC::ADDHA_SME_ZAda_3b_SVE_Pg3_SME_Pm_SVE_Zn(opcode) => opcode.definition(),
            SME_MISC::ADDSPL_Rd_SP_SVE_Rn_SP_SVE_SIMM6(opcode) => opcode.definition(),
            SME_MISC::ADDSVL_Rd_SP_SVE_Rn_SP_SVE_SIMM6(opcode) => opcode.definition(),
            SME_MISC::ADDVA_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn(opcode) => opcode.definition(),
            SME_MISC::ADDVA_SME_ZAda_3b_SVE_Pg3_SME_Pm_SVE_Zn(opcode) => opcode.definition(),
            SME_MISC::BFCVTN_SVE_Zd_SME_Znx2(opcode) => opcode.definition(),
            SME_MISC::BFCVT_SVE_Zd_SME_Znx2(opcode) => opcode.definition(),
            SME_MISC::BFDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2(opcode) => {
                opcode.definition()
            }
            SME_MISC::BFDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zmx2(opcode) => opcode.definition(),
            SME_MISC::BFDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2(opcode) => {
                opcode.definition()
            }
            SME_MISC::BFDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zmx4(opcode) => opcode.definition(),
            SME_MISC::BFDOT_SME_ZA_array_off3_0_SVE_ZnxN_SME_Zm(opcode) => opcode.definition(),
            SME_MISC::BFDOT_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_H_SME_Zm_S_H(opcode) => {
                opcode.definition()
            }
            SME_MISC::BFMLAL_SME_ZA_array_off2x2_SME_Znx2_SME_Zm_INDEX3_2(opcode) => {
                opcode.definition()
            }
            SME_MISC::BFMLAL_SME_ZA_array_off2x2_SME_Znx2_SME_Zmx2(opcode) => opcode.definition(),
            SME_MISC::BFMLAL_SME_ZA_array_off2x2_SME_Znx4_SME_Zm_INDEX3_2(opcode) => {
                opcode.definition()
            }
            SME_MISC::BFMLAL_SME_ZA_array_off2x2_SME_Znx4_SME_Zmx4(opcode) => opcode.definition(),
            SME_MISC::BFMLAL_SME_ZA_array_off2x2_SVE_ZnxN_SME_Zm(opcode) => opcode.definition(),
            SME_MISC::BFMLAL_SME_ZA_array_off2x2_S_S_SVE_ZnxN_S_H_SME_Zm_S_H(opcode) => {
                opcode.definition()
            }
            SME_MISC::BFMLAL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm(opcode) => opcode.definition(),
            SME_MISC::BFMLAL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm_INDEX3_10(opcode) => {
                opcode.definition()
            }
            SME_MISC::BFMLSL_SME_ZA_array_off2x2_SME_Znx2_SME_Zm_INDEX3_2(opcode) => {
                opcode.definition()
            }
            SME_MISC::BFMLSL_SME_ZA_array_off2x2_SME_Znx2_SME_Zmx2(opcode) => opcode.definition(),
            SME_MISC::BFMLSL_SME_ZA_array_off2x2_SME_Znx4_SME_Zm_INDEX3_2(opcode) => {
                opcode.definition()
            }
            SME_MISC::BFMLSL_SME_ZA_array_off2x2_SME_Znx4_SME_Zmx4(opcode) => opcode.definition(),
            SME_MISC::BFMLSL_SME_ZA_array_off2x2_SVE_ZnxN_SME_Zm(opcode) => opcode.definition(),
            SME_MISC::BFMLSL_SME_ZA_array_off2x2_S_S_SVE_ZnxN_S_H_SME_Zm_S_H(opcode) => {
                opcode.definition()
            }
            SME_MISC::BFMLSL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm(opcode) => opcode.definition(),
            SME_MISC::BFMLSL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm_INDEX3_10(opcode) => {
                opcode.definition()
            }
            SME_MISC::BFMOPA_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16(opcode) => {
                opcode.definition()
            }
            SME_MISC::BFMOPS_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16(opcode) => {
                opcode.definition()
            }
            SME_MISC::BFVDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2(opcode) => {
                opcode.definition()
            }
            SME_MISC::BMOPA_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16(opcode) => {
                opcode.definition()
            }
            SME_MISC::BMOPS_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16(opcode) => {
                opcode.definition()
            }
            SME_MISC::FDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2(opcode) => {
                opcode.definition()
            }
            SME_MISC::FDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zmx2(opcode) => opcode.definition(),
            SME_MISC::FDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2(opcode) => {
                opcode.definition()
            }
            SME_MISC::FDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zmx4(opcode) => opcode.definition(),
            SME_MISC::FDOT_SME_ZA_array_off3_0_SVE_ZnxN_SME_Zm(opcode) => opcode.definition(),
            SME_MISC::FDOT_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_H_SME_Zm_S_H(opcode) => {
                opcode.definition()
            }
            SME_MISC::FMLAL_SME_ZA_array_off2x2_SME_Znx2_SME_Zm_INDEX3_2(opcode) => {
                opcode.definition()
            }
            SME_MISC::FMLAL_SME_ZA_array_off2x2_SME_Znx2_SME_Zmx2(opcode) => opcode.definition(),
            SME_MISC::FMLAL_SME_ZA_array_off2x2_SME_Znx4_SME_Zm_INDEX3_2(opcode) => {
                opcode.definition()
            }
            SME_MISC::FMLAL_SME_ZA_array_off2x2_SME_Znx4_SME_Zmx4(opcode) => opcode.definition(),
            SME_MISC::FMLAL_SME_ZA_array_off2x2_SVE_ZnxN_SME_Zm(opcode) => opcode.definition(),
            SME_MISC::FMLAL_SME_ZA_array_off2x2_S_S_SVE_ZnxN_S_H_SME_Zm_S_H(opcode) => {
                opcode.definition()
            }
            SME_MISC::FMLAL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm(opcode) => opcode.definition(),
            SME_MISC::FMLAL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm_INDEX3_10(opcode) => {
                opcode.definition()
            }
            SME_MISC::FMLA_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX1(opcode) => {
                opcode.definition()
            }
            SME_MISC::FMLA_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2(opcode) => {
                opcode.definition()
            }
            SME_MISC::FMLA_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX1(opcode) => {
                opcode.definition()
            }
            SME_MISC::FMLA_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2(opcode) => {
                opcode.definition()
            }
            SME_MISC::FMLSL_SME_ZA_array_off2x2_SME_Znx2_SME_Zm_INDEX3_2(opcode) => {
                opcode.definition()
            }
            SME_MISC::FMLSL_SME_ZA_array_off2x2_SME_Znx2_SME_Zmx2(opcode) => opcode.definition(),
            SME_MISC::FMLSL_SME_ZA_array_off2x2_SME_Znx4_SME_Zm_INDEX3_2(opcode) => {
                opcode.definition()
            }
            SME_MISC::FMLSL_SME_ZA_array_off2x2_SME_Znx4_SME_Zmx4(opcode) => opcode.definition(),
            SME_MISC::FMLSL_SME_ZA_array_off2x2_SVE_ZnxN_SME_Zm(opcode) => opcode.definition(),
            SME_MISC::FMLSL_SME_ZA_array_off2x2_S_S_SVE_ZnxN_S_H_SME_Zm_S_H(opcode) => {
                opcode.definition()
            }
            SME_MISC::FMLSL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm(opcode) => opcode.definition(),
            SME_MISC::FMLSL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm_INDEX3_10(opcode) => {
                opcode.definition()
            }
            SME_MISC::FMLS_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX1(opcode) => {
                opcode.definition()
            }
            SME_MISC::FMLS_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2(opcode) => {
                opcode.definition()
            }
            SME_MISC::FMLS_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX1(opcode) => {
                opcode.definition()
            }
            SME_MISC::FMLS_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2(opcode) => {
                opcode.definition()
            }
            SME_MISC::FMOPA_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16(opcode) => {
                opcode.definition()
            }
            SME_MISC::FMOPA_SME_ZAda_2b_S_S_SVE_Pg3_P_M_SME_Pm_P_M_SVE_Zn_S_H_SVE_Zm_16_S_H(
                opcode,
            ) => opcode.definition(),
            SME_MISC::FMOPA_SME_ZAda_3b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16(opcode) => {
                opcode.definition()
            }
            SME_MISC::FMOPS_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16(opcode) => {
                opcode.definition()
            }
            SME_MISC::FMOPS_SME_ZAda_2b_S_S_SVE_Pg3_P_M_SME_Pm_P_M_SVE_Zn_S_H_SVE_Zm_16_S_H(
                opcode,
            ) => opcode.definition(),
            SME_MISC::FMOPS_SME_ZAda_3b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16(opcode) => {
                opcode.definition()
            }
            SME_MISC::FVDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2(opcode) => {
                opcode.definition()
            }
            SME_MISC::LDR_SME_ZT0_SIMD_ADDR_SIMPLE(opcode) => opcode.definition(),
            SME_MISC::MOVT_Rt_SME_ZT0_INDEX(opcode) => opcode.definition(),
            SME_MISC::MOVT_SME_ZT0_INDEX_Rt(opcode) => opcode.definition(),
            SME_MISC::RDSVL_Rd_SVE_SIMM6(opcode) => opcode.definition(),
            SME_MISC::REVD_SVE_Zd_SVE_Pg3_SVE_Zn(opcode) => opcode.definition(),
            SME_MISC::RPRFM_RPRFMOP_Rm_SIMD_ADDR_SIMPLE(opcode) => opcode.definition(),
            SME_MISC::SDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX1(opcode) => {
                opcode.definition()
            }
            SME_MISC::SDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2(opcode) => {
                opcode.definition()
            }
            SME_MISC::SDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX1(opcode) => {
                opcode.definition()
            }
            SME_MISC::SDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2(opcode) => {
                opcode.definition()
            }
            SME_MISC::SDOT_SME_ZA_array_off3_0_S_S_SME_Znx2_S_B_SME_Zm_INDEX2_S_B(opcode) => {
                opcode.definition()
            }
            SME_MISC::SDOT_SME_ZA_array_off3_0_S_S_SME_Znx2_S_H_SME_Zmx2_S_H(opcode) => {
                opcode.definition()
            }
            SME_MISC::SDOT_SME_ZA_array_off3_0_S_S_SME_Znx4_S_B_SME_Zm_INDEX2_S_B(opcode) => {
                opcode.definition()
            }
            SME_MISC::SDOT_SME_ZA_array_off3_0_S_S_SME_Znx4_S_H_SME_Zmx4_S_H(opcode) => {
                opcode.definition()
            }
            SME_MISC::SDOT_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_H_SME_Zm_S_H(opcode) => {
                opcode.definition()
            }
            SME_MISC::SDOT_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_H_SME_Zm_S_H_c1701408(opcode) => {
                opcode.definition()
            }
            SME_MISC::SMLALL_SME_ZA_array_off1x4_SME_Znx2_SME_Zm_INDEX3_1(opcode) => {
                opcode.definition()
            }
            SME_MISC::SMLALL_SME_ZA_array_off1x4_SME_Znx2_SME_Zm_INDEX4_1(opcode) => {
                opcode.definition()
            }
            SME_MISC::SMLALL_SME_ZA_array_off1x4_SME_Znx4_SME_Zm_INDEX3_1(opcode) => {
                opcode.definition()
            }
            SME_MISC::SMLALL_SME_ZA_array_off1x4_SME_Znx4_SME_Zm_INDEX4_1(opcode) => {
                opcode.definition()
            }
            SME_MISC::SMLALL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm_INDEX3_10(opcode) => {
                opcode.definition()
            }
            SME_MISC::SMLALL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm_INDEX4_10(opcode) => {
                opcode.definition()
            }
            SME_MISC::SMLAL_SME_ZA_array_off2x2_SME_Znx2_SME_Zm_INDEX3_2(opcode) => {
                opcode.definition()
            }
            SME_MISC::SMLAL_SME_ZA_array_off2x2_SME_Znx2_SME_Zmx2(opcode) => opcode.definition(),
            SME_MISC::SMLAL_SME_ZA_array_off2x2_SME_Znx4_SME_Zm_INDEX3_2(opcode) => {
                opcode.definition()
            }
            SME_MISC::SMLAL_SME_ZA_array_off2x2_SME_Znx4_SME_Zmx4(opcode) => opcode.definition(),
            SME_MISC::SMLAL_SME_ZA_array_off2x2_SVE_ZnxN_SME_Zm(opcode) => opcode.definition(),
            SME_MISC::SMLAL_SME_ZA_array_off2x2_S_S_SVE_ZnxN_S_H_SME_Zm_S_H(opcode) => {
                opcode.definition()
            }
            SME_MISC::SMLAL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm(opcode) => opcode.definition(),
            SME_MISC::SMLAL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm_INDEX3_10(opcode) => {
                opcode.definition()
            }
            SME_MISC::SMLSLL_SME_ZA_array_off1x4_SME_Znx2_SME_Zm_INDEX3_1(opcode) => {
                opcode.definition()
            }
            SME_MISC::SMLSLL_SME_ZA_array_off1x4_SME_Znx2_SME_Zm_INDEX4_1(opcode) => {
                opcode.definition()
            }
            SME_MISC::SMLSLL_SME_ZA_array_off1x4_SME_Znx4_SME_Zm_INDEX3_1(opcode) => {
                opcode.definition()
            }
            SME_MISC::SMLSLL_SME_ZA_array_off1x4_SME_Znx4_SME_Zm_INDEX4_1(opcode) => {
                opcode.definition()
            }
            SME_MISC::SMLSLL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm_INDEX3_10(opcode) => {
                opcode.definition()
            }
            SME_MISC::SMLSLL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm_INDEX4_10(opcode) => {
                opcode.definition()
            }
            SME_MISC::SMLSL_SME_ZA_array_off2x2_SME_Znx2_SME_Zm_INDEX3_2(opcode) => {
                opcode.definition()
            }
            SME_MISC::SMLSL_SME_ZA_array_off2x2_SME_Znx2_SME_Zmx2(opcode) => opcode.definition(),
            SME_MISC::SMLSL_SME_ZA_array_off2x2_SME_Znx4_SME_Zm_INDEX3_2(opcode) => {
                opcode.definition()
            }
            SME_MISC::SMLSL_SME_ZA_array_off2x2_SME_Znx4_SME_Zmx4(opcode) => opcode.definition(),
            SME_MISC::SMLSL_SME_ZA_array_off2x2_SVE_ZnxN_SME_Zm(opcode) => opcode.definition(),
            SME_MISC::SMLSL_SME_ZA_array_off2x2_S_S_SVE_ZnxN_S_H_SME_Zm_S_H(opcode) => {
                opcode.definition()
            }
            SME_MISC::SMLSL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm(opcode) => opcode.definition(),
            SME_MISC::SMLSL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm_INDEX3_10(opcode) => {
                opcode.definition()
            }
            SME_MISC::SMOPA_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16(opcode) => {
                opcode.definition()
            }
            SME_MISC::SMOPA_SME_ZAda_2b_S_S_SVE_Pg3_P_M_SME_Pm_P_M_SVE_Zn_S_H_SVE_Zm_16_S_H(
                opcode,
            ) => opcode.definition(),
            SME_MISC::SMOPA_SME_ZAda_3b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16(opcode) => {
                opcode.definition()
            }
            SME_MISC::SMOPS_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16(opcode) => {
                opcode.definition()
            }
            SME_MISC::SMOPS_SME_ZAda_2b_S_S_SVE_Pg3_P_M_SME_Pm_P_M_SVE_Zn_S_H_SVE_Zm_16_S_H(
                opcode,
            ) => opcode.definition(),
            SME_MISC::SMOPS_SME_ZAda_3b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16(opcode) => {
                opcode.definition()
            }
            SME_MISC::SQCVTU_SVE_Zd_SME_Znx2(opcode) => opcode.definition(),
            SME_MISC::SQCVT_SVE_Zd_SME_Znx2(opcode) => opcode.definition(),
            SME_MISC::SQRSHRN_SVE_Zd_SME_Znx2_SME_SHRIMM4(opcode) => opcode.definition(),
            SME_MISC::SQRSHRUN_SVE_Zd_SME_Znx2_SME_SHRIMM4(opcode) => opcode.definition(),
            SME_MISC::SQRSHRU_SVE_Zd_SME_Znx2_SME_SHRIMM4(opcode) => opcode.definition(),
            SME_MISC::SQRSHR_SVE_Zd_SME_Znx2_SME_SHRIMM4(opcode) => opcode.definition(),
            SME_MISC::STR_SME_ZT0_SIMD_ADDR_SIMPLE(opcode) => opcode.definition(),
            SME_MISC::SUDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2(opcode) => {
                opcode.definition()
            }
            SME_MISC::SUDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2(opcode) => {
                opcode.definition()
            }
            SME_MISC::SUDOT_SME_ZA_array_off3_0_SVE_ZnxN_SME_Zm(opcode) => opcode.definition(),
            SME_MISC::SUDOT_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_B_SME_Zm_S_B(opcode) => {
                opcode.definition()
            }
            SME_MISC::SUMLALL_SME_ZA_array_off1x4_SME_Znx2_SME_Zm_INDEX4_1(opcode) => {
                opcode.definition()
            }
            SME_MISC::SUMLALL_SME_ZA_array_off1x4_SME_Znx4_SME_Zm_INDEX4_1(opcode) => {
                opcode.definition()
            }
            SME_MISC::SUMLALL_SME_ZA_array_off1x4_SVE_ZnxN_SME_Zm(opcode) => opcode.definition(),
            SME_MISC::SUMLALL_SME_ZA_array_off1x4_S_S_SVE_ZnxN_S_B_SME_Zm_S_B(opcode) => {
                opcode.definition()
            }
            SME_MISC::SUMLALL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm_INDEX4_10(opcode) => {
                opcode.definition()
            }
            SME_MISC::SUMOPA_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16(opcode) => {
                opcode.definition()
            }
            SME_MISC::SUMOPA_SME_ZAda_3b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16(opcode) => {
                opcode.definition()
            }
            SME_MISC::SUMOPS_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16(opcode) => {
                opcode.definition()
            }
            SME_MISC::SUMOPS_SME_ZAda_3b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16(opcode) => {
                opcode.definition()
            }
            SME_MISC::SUVDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2(opcode) => {
                opcode.definition()
            }
            SME_MISC::SVDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2(opcode) => {
                opcode.definition()
            }
            SME_MISC::SVDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX1(opcode) => {
                opcode.definition()
            }
            SME_MISC::SVDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2(opcode) => {
                opcode.definition()
            }
            SME_MISC::UDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX1(opcode) => {
                opcode.definition()
            }
            SME_MISC::UDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2(opcode) => {
                opcode.definition()
            }
            SME_MISC::UDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX1(opcode) => {
                opcode.definition()
            }
            SME_MISC::UDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2(opcode) => {
                opcode.definition()
            }
            SME_MISC::UDOT_SME_ZA_array_off3_0_S_S_SME_Znx2_S_B_SME_Zm_INDEX2_S_B(opcode) => {
                opcode.definition()
            }
            SME_MISC::UDOT_SME_ZA_array_off3_0_S_S_SME_Znx2_S_H_SME_Zmx2_S_H(opcode) => {
                opcode.definition()
            }
            SME_MISC::UDOT_SME_ZA_array_off3_0_S_S_SME_Znx4_S_B_SME_Zm_INDEX2_S_B(opcode) => {
                opcode.definition()
            }
            SME_MISC::UDOT_SME_ZA_array_off3_0_S_S_SME_Znx4_S_H_SME_Zmx4_S_H(opcode) => {
                opcode.definition()
            }
            SME_MISC::UDOT_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_H_SME_Zm_S_H(opcode) => {
                opcode.definition()
            }
            SME_MISC::UDOT_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_H_SME_Zm_S_H_c1701418(opcode) => {
                opcode.definition()
            }
            SME_MISC::UMLALL_SME_ZA_array_off1x4_SME_Znx2_SME_Zm_INDEX3_1(opcode) => {
                opcode.definition()
            }
            SME_MISC::UMLALL_SME_ZA_array_off1x4_SME_Znx2_SME_Zm_INDEX4_1(opcode) => {
                opcode.definition()
            }
            SME_MISC::UMLALL_SME_ZA_array_off1x4_SME_Znx4_SME_Zm_INDEX3_1(opcode) => {
                opcode.definition()
            }
            SME_MISC::UMLALL_SME_ZA_array_off1x4_SME_Znx4_SME_Zm_INDEX4_1(opcode) => {
                opcode.definition()
            }
            SME_MISC::UMLALL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm_INDEX3_10(opcode) => {
                opcode.definition()
            }
            SME_MISC::UMLALL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm_INDEX4_10(opcode) => {
                opcode.definition()
            }
            SME_MISC::UMLAL_SME_ZA_array_off2x2_SME_Znx2_SME_Zm_INDEX3_2(opcode) => {
                opcode.definition()
            }
            SME_MISC::UMLAL_SME_ZA_array_off2x2_SME_Znx2_SME_Zmx2(opcode) => opcode.definition(),
            SME_MISC::UMLAL_SME_ZA_array_off2x2_SME_Znx4_SME_Zm_INDEX3_2(opcode) => {
                opcode.definition()
            }
            SME_MISC::UMLAL_SME_ZA_array_off2x2_SME_Znx4_SME_Zmx4(opcode) => opcode.definition(),
            SME_MISC::UMLAL_SME_ZA_array_off2x2_SVE_ZnxN_SME_Zm(opcode) => opcode.definition(),
            SME_MISC::UMLAL_SME_ZA_array_off2x2_S_S_SVE_ZnxN_S_H_SME_Zm_S_H(opcode) => {
                opcode.definition()
            }
            SME_MISC::UMLAL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm(opcode) => opcode.definition(),
            SME_MISC::UMLAL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm_INDEX3_10(opcode) => {
                opcode.definition()
            }
            SME_MISC::UMLSLL_SME_ZA_array_off1x4_SME_Znx2_SME_Zm_INDEX3_1(opcode) => {
                opcode.definition()
            }
            SME_MISC::UMLSLL_SME_ZA_array_off1x4_SME_Znx2_SME_Zm_INDEX4_1(opcode) => {
                opcode.definition()
            }
            SME_MISC::UMLSLL_SME_ZA_array_off1x4_SME_Znx4_SME_Zm_INDEX3_1(opcode) => {
                opcode.definition()
            }
            SME_MISC::UMLSLL_SME_ZA_array_off1x4_SME_Znx4_SME_Zm_INDEX4_1(opcode) => {
                opcode.definition()
            }
            SME_MISC::UMLSLL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm_INDEX3_10(opcode) => {
                opcode.definition()
            }
            SME_MISC::UMLSLL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm_INDEX4_10(opcode) => {
                opcode.definition()
            }
            SME_MISC::UMLSL_SME_ZA_array_off2x2_SME_Znx2_SME_Zm_INDEX3_2(opcode) => {
                opcode.definition()
            }
            SME_MISC::UMLSL_SME_ZA_array_off2x2_SME_Znx2_SME_Zmx2(opcode) => opcode.definition(),
            SME_MISC::UMLSL_SME_ZA_array_off2x2_SME_Znx4_SME_Zm_INDEX3_2(opcode) => {
                opcode.definition()
            }
            SME_MISC::UMLSL_SME_ZA_array_off2x2_SME_Znx4_SME_Zmx4(opcode) => opcode.definition(),
            SME_MISC::UMLSL_SME_ZA_array_off2x2_SVE_ZnxN_SME_Zm(opcode) => opcode.definition(),
            SME_MISC::UMLSL_SME_ZA_array_off2x2_S_S_SVE_ZnxN_S_H_SME_Zm_S_H(opcode) => {
                opcode.definition()
            }
            SME_MISC::UMLSL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm(opcode) => opcode.definition(),
            SME_MISC::UMLSL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm_INDEX3_10(opcode) => {
                opcode.definition()
            }
            SME_MISC::UMOPA_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16(opcode) => {
                opcode.definition()
            }
            SME_MISC::UMOPA_SME_ZAda_2b_S_S_SVE_Pg3_P_M_SME_Pm_P_M_SVE_Zn_S_B_SVE_Zm_16_S_B(
                opcode,
            ) => opcode.definition(),
            SME_MISC::UMOPA_SME_ZAda_3b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16(opcode) => {
                opcode.definition()
            }
            SME_MISC::UMOPS_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16(opcode) => {
                opcode.definition()
            }
            SME_MISC::UMOPS_SME_ZAda_2b_S_S_SVE_Pg3_P_M_SME_Pm_P_M_SVE_Zn_S_B_SVE_Zm_16_S_B(
                opcode,
            ) => opcode.definition(),
            SME_MISC::UMOPS_SME_ZAda_3b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16(opcode) => {
                opcode.definition()
            }
            SME_MISC::UQCVT_SVE_Zd_SME_Znx2(opcode) => opcode.definition(),
            SME_MISC::UQRSHRN_SVE_Zd_SME_Znx2_SME_SHRIMM4(opcode) => opcode.definition(),
            SME_MISC::UQRSHR_SVE_Zd_SME_Znx2_SME_SHRIMM4(opcode) => opcode.definition(),
            SME_MISC::USDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2(opcode) => {
                opcode.definition()
            }
            SME_MISC::USDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zmx2(opcode) => opcode.definition(),
            SME_MISC::USDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2(opcode) => {
                opcode.definition()
            }
            SME_MISC::USDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zmx4(opcode) => opcode.definition(),
            SME_MISC::USDOT_SME_ZA_array_off3_0_SVE_ZnxN_SME_Zm(opcode) => opcode.definition(),
            SME_MISC::USDOT_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_B_SME_Zm_S_B(opcode) => {
                opcode.definition()
            }
            SME_MISC::USMLALL_SME_ZA_array_off1x4_SME_Znx2_SME_Zm_INDEX4_1(opcode) => {
                opcode.definition()
            }
            SME_MISC::USMLALL_SME_ZA_array_off1x4_SME_Znx2_SME_Zmx2(opcode) => opcode.definition(),
            SME_MISC::USMLALL_SME_ZA_array_off1x4_SME_Znx4_SME_Zm_INDEX4_1(opcode) => {
                opcode.definition()
            }
            SME_MISC::USMLALL_SME_ZA_array_off1x4_SME_Znx4_SME_Zmx4(opcode) => opcode.definition(),
            SME_MISC::USMLALL_SME_ZA_array_off1x4_SVE_ZnxN_SME_Zm(opcode) => opcode.definition(),
            SME_MISC::USMLALL_SME_ZA_array_off1x4_S_S_SVE_ZnxN_S_B_SME_Zm_S_B(opcode) => {
                opcode.definition()
            }
            SME_MISC::USMLALL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm(opcode) => opcode.definition(),
            SME_MISC::USMLALL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm_INDEX4_10(opcode) => {
                opcode.definition()
            }
            SME_MISC::USMOPA_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16(opcode) => {
                opcode.definition()
            }
            SME_MISC::USMOPA_SME_ZAda_3b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16(opcode) => {
                opcode.definition()
            }
            SME_MISC::USMOPS_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16(opcode) => {
                opcode.definition()
            }
            SME_MISC::USMOPS_SME_ZAda_3b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16(opcode) => {
                opcode.definition()
            }
            SME_MISC::USVDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2(opcode) => {
                opcode.definition()
            }
            SME_MISC::UVDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2(opcode) => {
                opcode.definition()
            }
            SME_MISC::UVDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX1(opcode) => {
                opcode.definition()
            }
            SME_MISC::UVDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2(opcode) => {
                opcode.definition()
            }
            SME_MISC::UZP_SME_Zdnx2_S_Q_SVE_Zn_S_Q_SVE_Zm_16_S_Q(opcode) => opcode.definition(),
            SME_MISC::UZP_SME_Zdnx4_S_Q_SME_Znx4_S_Q(opcode) => opcode.definition(),
            SME_MISC::ZERO_SME_ZT0_LIST(opcode) => opcode.definition(),
            SME_MISC::ZERO_SME_list_of_64bit_tiles(opcode) => opcode.definition(),
            SME_MISC::ZIP_SME_Zdnx2_S_Q_SVE_Zn_S_Q_SVE_Zm_16_S_Q(opcode) => opcode.definition(),
            SME_MISC::ZIP_SME_Zdnx4_S_Q_SME_Znx4_S_Q(opcode) => opcode.definition(),
        }
    }
    fn bits(&self) -> u32 {
        match self {
            SME_MISC::ADDHA_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn(opcode) => opcode.bits(),
            SME_MISC::ADDHA_SME_ZAda_3b_SVE_Pg3_SME_Pm_SVE_Zn(opcode) => opcode.bits(),
            SME_MISC::ADDSPL_Rd_SP_SVE_Rn_SP_SVE_SIMM6(opcode) => opcode.bits(),
            SME_MISC::ADDSVL_Rd_SP_SVE_Rn_SP_SVE_SIMM6(opcode) => opcode.bits(),
            SME_MISC::ADDVA_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn(opcode) => opcode.bits(),
            SME_MISC::ADDVA_SME_ZAda_3b_SVE_Pg3_SME_Pm_SVE_Zn(opcode) => opcode.bits(),
            SME_MISC::BFCVTN_SVE_Zd_SME_Znx2(opcode) => opcode.bits(),
            SME_MISC::BFCVT_SVE_Zd_SME_Znx2(opcode) => opcode.bits(),
            SME_MISC::BFDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2(opcode) => opcode.bits(),
            SME_MISC::BFDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zmx2(opcode) => opcode.bits(),
            SME_MISC::BFDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2(opcode) => opcode.bits(),
            SME_MISC::BFDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zmx4(opcode) => opcode.bits(),
            SME_MISC::BFDOT_SME_ZA_array_off3_0_SVE_ZnxN_SME_Zm(opcode) => opcode.bits(),
            SME_MISC::BFDOT_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_H_SME_Zm_S_H(opcode) => {
                opcode.bits()
            }
            SME_MISC::BFMLAL_SME_ZA_array_off2x2_SME_Znx2_SME_Zm_INDEX3_2(opcode) => opcode.bits(),
            SME_MISC::BFMLAL_SME_ZA_array_off2x2_SME_Znx2_SME_Zmx2(opcode) => opcode.bits(),
            SME_MISC::BFMLAL_SME_ZA_array_off2x2_SME_Znx4_SME_Zm_INDEX3_2(opcode) => opcode.bits(),
            SME_MISC::BFMLAL_SME_ZA_array_off2x2_SME_Znx4_SME_Zmx4(opcode) => opcode.bits(),
            SME_MISC::BFMLAL_SME_ZA_array_off2x2_SVE_ZnxN_SME_Zm(opcode) => opcode.bits(),
            SME_MISC::BFMLAL_SME_ZA_array_off2x2_S_S_SVE_ZnxN_S_H_SME_Zm_S_H(opcode) => {
                opcode.bits()
            }
            SME_MISC::BFMLAL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm(opcode) => opcode.bits(),
            SME_MISC::BFMLAL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm_INDEX3_10(opcode) => opcode.bits(),
            SME_MISC::BFMLSL_SME_ZA_array_off2x2_SME_Znx2_SME_Zm_INDEX3_2(opcode) => opcode.bits(),
            SME_MISC::BFMLSL_SME_ZA_array_off2x2_SME_Znx2_SME_Zmx2(opcode) => opcode.bits(),
            SME_MISC::BFMLSL_SME_ZA_array_off2x2_SME_Znx4_SME_Zm_INDEX3_2(opcode) => opcode.bits(),
            SME_MISC::BFMLSL_SME_ZA_array_off2x2_SME_Znx4_SME_Zmx4(opcode) => opcode.bits(),
            SME_MISC::BFMLSL_SME_ZA_array_off2x2_SVE_ZnxN_SME_Zm(opcode) => opcode.bits(),
            SME_MISC::BFMLSL_SME_ZA_array_off2x2_S_S_SVE_ZnxN_S_H_SME_Zm_S_H(opcode) => {
                opcode.bits()
            }
            SME_MISC::BFMLSL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm(opcode) => opcode.bits(),
            SME_MISC::BFMLSL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm_INDEX3_10(opcode) => opcode.bits(),
            SME_MISC::BFMOPA_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SME_MISC::BFMOPS_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SME_MISC::BFVDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2(opcode) => opcode.bits(),
            SME_MISC::BMOPA_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SME_MISC::BMOPS_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SME_MISC::FDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2(opcode) => opcode.bits(),
            SME_MISC::FDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zmx2(opcode) => opcode.bits(),
            SME_MISC::FDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2(opcode) => opcode.bits(),
            SME_MISC::FDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zmx4(opcode) => opcode.bits(),
            SME_MISC::FDOT_SME_ZA_array_off3_0_SVE_ZnxN_SME_Zm(opcode) => opcode.bits(),
            SME_MISC::FDOT_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_H_SME_Zm_S_H(opcode) => opcode.bits(),
            SME_MISC::FMLAL_SME_ZA_array_off2x2_SME_Znx2_SME_Zm_INDEX3_2(opcode) => opcode.bits(),
            SME_MISC::FMLAL_SME_ZA_array_off2x2_SME_Znx2_SME_Zmx2(opcode) => opcode.bits(),
            SME_MISC::FMLAL_SME_ZA_array_off2x2_SME_Znx4_SME_Zm_INDEX3_2(opcode) => opcode.bits(),
            SME_MISC::FMLAL_SME_ZA_array_off2x2_SME_Znx4_SME_Zmx4(opcode) => opcode.bits(),
            SME_MISC::FMLAL_SME_ZA_array_off2x2_SVE_ZnxN_SME_Zm(opcode) => opcode.bits(),
            SME_MISC::FMLAL_SME_ZA_array_off2x2_S_S_SVE_ZnxN_S_H_SME_Zm_S_H(opcode) => {
                opcode.bits()
            }
            SME_MISC::FMLAL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm(opcode) => opcode.bits(),
            SME_MISC::FMLAL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm_INDEX3_10(opcode) => opcode.bits(),
            SME_MISC::FMLA_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX1(opcode) => opcode.bits(),
            SME_MISC::FMLA_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2(opcode) => opcode.bits(),
            SME_MISC::FMLA_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX1(opcode) => opcode.bits(),
            SME_MISC::FMLA_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2(opcode) => opcode.bits(),
            SME_MISC::FMLSL_SME_ZA_array_off2x2_SME_Znx2_SME_Zm_INDEX3_2(opcode) => opcode.bits(),
            SME_MISC::FMLSL_SME_ZA_array_off2x2_SME_Znx2_SME_Zmx2(opcode) => opcode.bits(),
            SME_MISC::FMLSL_SME_ZA_array_off2x2_SME_Znx4_SME_Zm_INDEX3_2(opcode) => opcode.bits(),
            SME_MISC::FMLSL_SME_ZA_array_off2x2_SME_Znx4_SME_Zmx4(opcode) => opcode.bits(),
            SME_MISC::FMLSL_SME_ZA_array_off2x2_SVE_ZnxN_SME_Zm(opcode) => opcode.bits(),
            SME_MISC::FMLSL_SME_ZA_array_off2x2_S_S_SVE_ZnxN_S_H_SME_Zm_S_H(opcode) => {
                opcode.bits()
            }
            SME_MISC::FMLSL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm(opcode) => opcode.bits(),
            SME_MISC::FMLSL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm_INDEX3_10(opcode) => opcode.bits(),
            SME_MISC::FMLS_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX1(opcode) => opcode.bits(),
            SME_MISC::FMLS_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2(opcode) => opcode.bits(),
            SME_MISC::FMLS_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX1(opcode) => opcode.bits(),
            SME_MISC::FMLS_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2(opcode) => opcode.bits(),
            SME_MISC::FMOPA_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SME_MISC::FMOPA_SME_ZAda_2b_S_S_SVE_Pg3_P_M_SME_Pm_P_M_SVE_Zn_S_H_SVE_Zm_16_S_H(
                opcode,
            ) => opcode.bits(),
            SME_MISC::FMOPA_SME_ZAda_3b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SME_MISC::FMOPS_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SME_MISC::FMOPS_SME_ZAda_2b_S_S_SVE_Pg3_P_M_SME_Pm_P_M_SVE_Zn_S_H_SVE_Zm_16_S_H(
                opcode,
            ) => opcode.bits(),
            SME_MISC::FMOPS_SME_ZAda_3b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SME_MISC::FVDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2(opcode) => opcode.bits(),
            SME_MISC::LDR_SME_ZT0_SIMD_ADDR_SIMPLE(opcode) => opcode.bits(),
            SME_MISC::MOVT_Rt_SME_ZT0_INDEX(opcode) => opcode.bits(),
            SME_MISC::MOVT_SME_ZT0_INDEX_Rt(opcode) => opcode.bits(),
            SME_MISC::RDSVL_Rd_SVE_SIMM6(opcode) => opcode.bits(),
            SME_MISC::REVD_SVE_Zd_SVE_Pg3_SVE_Zn(opcode) => opcode.bits(),
            SME_MISC::RPRFM_RPRFMOP_Rm_SIMD_ADDR_SIMPLE(opcode) => opcode.bits(),
            SME_MISC::SDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX1(opcode) => opcode.bits(),
            SME_MISC::SDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2(opcode) => opcode.bits(),
            SME_MISC::SDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX1(opcode) => opcode.bits(),
            SME_MISC::SDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2(opcode) => opcode.bits(),
            SME_MISC::SDOT_SME_ZA_array_off3_0_S_S_SME_Znx2_S_B_SME_Zm_INDEX2_S_B(opcode) => {
                opcode.bits()
            }
            SME_MISC::SDOT_SME_ZA_array_off3_0_S_S_SME_Znx2_S_H_SME_Zmx2_S_H(opcode) => {
                opcode.bits()
            }
            SME_MISC::SDOT_SME_ZA_array_off3_0_S_S_SME_Znx4_S_B_SME_Zm_INDEX2_S_B(opcode) => {
                opcode.bits()
            }
            SME_MISC::SDOT_SME_ZA_array_off3_0_S_S_SME_Znx4_S_H_SME_Zmx4_S_H(opcode) => {
                opcode.bits()
            }
            SME_MISC::SDOT_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_H_SME_Zm_S_H(opcode) => opcode.bits(),
            SME_MISC::SDOT_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_H_SME_Zm_S_H_c1701408(opcode) => {
                opcode.bits()
            }
            SME_MISC::SMLALL_SME_ZA_array_off1x4_SME_Znx2_SME_Zm_INDEX3_1(opcode) => opcode.bits(),
            SME_MISC::SMLALL_SME_ZA_array_off1x4_SME_Znx2_SME_Zm_INDEX4_1(opcode) => opcode.bits(),
            SME_MISC::SMLALL_SME_ZA_array_off1x4_SME_Znx4_SME_Zm_INDEX3_1(opcode) => opcode.bits(),
            SME_MISC::SMLALL_SME_ZA_array_off1x4_SME_Znx4_SME_Zm_INDEX4_1(opcode) => opcode.bits(),
            SME_MISC::SMLALL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm_INDEX3_10(opcode) => opcode.bits(),
            SME_MISC::SMLALL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm_INDEX4_10(opcode) => opcode.bits(),
            SME_MISC::SMLAL_SME_ZA_array_off2x2_SME_Znx2_SME_Zm_INDEX3_2(opcode) => opcode.bits(),
            SME_MISC::SMLAL_SME_ZA_array_off2x2_SME_Znx2_SME_Zmx2(opcode) => opcode.bits(),
            SME_MISC::SMLAL_SME_ZA_array_off2x2_SME_Znx4_SME_Zm_INDEX3_2(opcode) => opcode.bits(),
            SME_MISC::SMLAL_SME_ZA_array_off2x2_SME_Znx4_SME_Zmx4(opcode) => opcode.bits(),
            SME_MISC::SMLAL_SME_ZA_array_off2x2_SVE_ZnxN_SME_Zm(opcode) => opcode.bits(),
            SME_MISC::SMLAL_SME_ZA_array_off2x2_S_S_SVE_ZnxN_S_H_SME_Zm_S_H(opcode) => {
                opcode.bits()
            }
            SME_MISC::SMLAL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm(opcode) => opcode.bits(),
            SME_MISC::SMLAL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm_INDEX3_10(opcode) => opcode.bits(),
            SME_MISC::SMLSLL_SME_ZA_array_off1x4_SME_Znx2_SME_Zm_INDEX3_1(opcode) => opcode.bits(),
            SME_MISC::SMLSLL_SME_ZA_array_off1x4_SME_Znx2_SME_Zm_INDEX4_1(opcode) => opcode.bits(),
            SME_MISC::SMLSLL_SME_ZA_array_off1x4_SME_Znx4_SME_Zm_INDEX3_1(opcode) => opcode.bits(),
            SME_MISC::SMLSLL_SME_ZA_array_off1x4_SME_Znx4_SME_Zm_INDEX4_1(opcode) => opcode.bits(),
            SME_MISC::SMLSLL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm_INDEX3_10(opcode) => opcode.bits(),
            SME_MISC::SMLSLL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm_INDEX4_10(opcode) => opcode.bits(),
            SME_MISC::SMLSL_SME_ZA_array_off2x2_SME_Znx2_SME_Zm_INDEX3_2(opcode) => opcode.bits(),
            SME_MISC::SMLSL_SME_ZA_array_off2x2_SME_Znx2_SME_Zmx2(opcode) => opcode.bits(),
            SME_MISC::SMLSL_SME_ZA_array_off2x2_SME_Znx4_SME_Zm_INDEX3_2(opcode) => opcode.bits(),
            SME_MISC::SMLSL_SME_ZA_array_off2x2_SME_Znx4_SME_Zmx4(opcode) => opcode.bits(),
            SME_MISC::SMLSL_SME_ZA_array_off2x2_SVE_ZnxN_SME_Zm(opcode) => opcode.bits(),
            SME_MISC::SMLSL_SME_ZA_array_off2x2_S_S_SVE_ZnxN_S_H_SME_Zm_S_H(opcode) => {
                opcode.bits()
            }
            SME_MISC::SMLSL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm(opcode) => opcode.bits(),
            SME_MISC::SMLSL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm_INDEX3_10(opcode) => opcode.bits(),
            SME_MISC::SMOPA_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SME_MISC::SMOPA_SME_ZAda_2b_S_S_SVE_Pg3_P_M_SME_Pm_P_M_SVE_Zn_S_H_SVE_Zm_16_S_H(
                opcode,
            ) => opcode.bits(),
            SME_MISC::SMOPA_SME_ZAda_3b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SME_MISC::SMOPS_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SME_MISC::SMOPS_SME_ZAda_2b_S_S_SVE_Pg3_P_M_SME_Pm_P_M_SVE_Zn_S_H_SVE_Zm_16_S_H(
                opcode,
            ) => opcode.bits(),
            SME_MISC::SMOPS_SME_ZAda_3b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SME_MISC::SQCVTU_SVE_Zd_SME_Znx2(opcode) => opcode.bits(),
            SME_MISC::SQCVT_SVE_Zd_SME_Znx2(opcode) => opcode.bits(),
            SME_MISC::SQRSHRN_SVE_Zd_SME_Znx2_SME_SHRIMM4(opcode) => opcode.bits(),
            SME_MISC::SQRSHRUN_SVE_Zd_SME_Znx2_SME_SHRIMM4(opcode) => opcode.bits(),
            SME_MISC::SQRSHRU_SVE_Zd_SME_Znx2_SME_SHRIMM4(opcode) => opcode.bits(),
            SME_MISC::SQRSHR_SVE_Zd_SME_Znx2_SME_SHRIMM4(opcode) => opcode.bits(),
            SME_MISC::STR_SME_ZT0_SIMD_ADDR_SIMPLE(opcode) => opcode.bits(),
            SME_MISC::SUDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2(opcode) => opcode.bits(),
            SME_MISC::SUDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2(opcode) => opcode.bits(),
            SME_MISC::SUDOT_SME_ZA_array_off3_0_SVE_ZnxN_SME_Zm(opcode) => opcode.bits(),
            SME_MISC::SUDOT_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_B_SME_Zm_S_B(opcode) => {
                opcode.bits()
            }
            SME_MISC::SUMLALL_SME_ZA_array_off1x4_SME_Znx2_SME_Zm_INDEX4_1(opcode) => opcode.bits(),
            SME_MISC::SUMLALL_SME_ZA_array_off1x4_SME_Znx4_SME_Zm_INDEX4_1(opcode) => opcode.bits(),
            SME_MISC::SUMLALL_SME_ZA_array_off1x4_SVE_ZnxN_SME_Zm(opcode) => opcode.bits(),
            SME_MISC::SUMLALL_SME_ZA_array_off1x4_S_S_SVE_ZnxN_S_B_SME_Zm_S_B(opcode) => {
                opcode.bits()
            }
            SME_MISC::SUMLALL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm_INDEX4_10(opcode) => opcode.bits(),
            SME_MISC::SUMOPA_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SME_MISC::SUMOPA_SME_ZAda_3b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SME_MISC::SUMOPS_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SME_MISC::SUMOPS_SME_ZAda_3b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SME_MISC::SUVDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2(opcode) => opcode.bits(),
            SME_MISC::SVDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2(opcode) => opcode.bits(),
            SME_MISC::SVDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX1(opcode) => opcode.bits(),
            SME_MISC::SVDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2(opcode) => opcode.bits(),
            SME_MISC::UDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX1(opcode) => opcode.bits(),
            SME_MISC::UDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2(opcode) => opcode.bits(),
            SME_MISC::UDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX1(opcode) => opcode.bits(),
            SME_MISC::UDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2(opcode) => opcode.bits(),
            SME_MISC::UDOT_SME_ZA_array_off3_0_S_S_SME_Znx2_S_B_SME_Zm_INDEX2_S_B(opcode) => {
                opcode.bits()
            }
            SME_MISC::UDOT_SME_ZA_array_off3_0_S_S_SME_Znx2_S_H_SME_Zmx2_S_H(opcode) => {
                opcode.bits()
            }
            SME_MISC::UDOT_SME_ZA_array_off3_0_S_S_SME_Znx4_S_B_SME_Zm_INDEX2_S_B(opcode) => {
                opcode.bits()
            }
            SME_MISC::UDOT_SME_ZA_array_off3_0_S_S_SME_Znx4_S_H_SME_Zmx4_S_H(opcode) => {
                opcode.bits()
            }
            SME_MISC::UDOT_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_H_SME_Zm_S_H(opcode) => opcode.bits(),
            SME_MISC::UDOT_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_H_SME_Zm_S_H_c1701418(opcode) => {
                opcode.bits()
            }
            SME_MISC::UMLALL_SME_ZA_array_off1x4_SME_Znx2_SME_Zm_INDEX3_1(opcode) => opcode.bits(),
            SME_MISC::UMLALL_SME_ZA_array_off1x4_SME_Znx2_SME_Zm_INDEX4_1(opcode) => opcode.bits(),
            SME_MISC::UMLALL_SME_ZA_array_off1x4_SME_Znx4_SME_Zm_INDEX3_1(opcode) => opcode.bits(),
            SME_MISC::UMLALL_SME_ZA_array_off1x4_SME_Znx4_SME_Zm_INDEX4_1(opcode) => opcode.bits(),
            SME_MISC::UMLALL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm_INDEX3_10(opcode) => opcode.bits(),
            SME_MISC::UMLALL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm_INDEX4_10(opcode) => opcode.bits(),
            SME_MISC::UMLAL_SME_ZA_array_off2x2_SME_Znx2_SME_Zm_INDEX3_2(opcode) => opcode.bits(),
            SME_MISC::UMLAL_SME_ZA_array_off2x2_SME_Znx2_SME_Zmx2(opcode) => opcode.bits(),
            SME_MISC::UMLAL_SME_ZA_array_off2x2_SME_Znx4_SME_Zm_INDEX3_2(opcode) => opcode.bits(),
            SME_MISC::UMLAL_SME_ZA_array_off2x2_SME_Znx4_SME_Zmx4(opcode) => opcode.bits(),
            SME_MISC::UMLAL_SME_ZA_array_off2x2_SVE_ZnxN_SME_Zm(opcode) => opcode.bits(),
            SME_MISC::UMLAL_SME_ZA_array_off2x2_S_S_SVE_ZnxN_S_H_SME_Zm_S_H(opcode) => {
                opcode.bits()
            }
            SME_MISC::UMLAL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm(opcode) => opcode.bits(),
            SME_MISC::UMLAL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm_INDEX3_10(opcode) => opcode.bits(),
            SME_MISC::UMLSLL_SME_ZA_array_off1x4_SME_Znx2_SME_Zm_INDEX3_1(opcode) => opcode.bits(),
            SME_MISC::UMLSLL_SME_ZA_array_off1x4_SME_Znx2_SME_Zm_INDEX4_1(opcode) => opcode.bits(),
            SME_MISC::UMLSLL_SME_ZA_array_off1x4_SME_Znx4_SME_Zm_INDEX3_1(opcode) => opcode.bits(),
            SME_MISC::UMLSLL_SME_ZA_array_off1x4_SME_Znx4_SME_Zm_INDEX4_1(opcode) => opcode.bits(),
            SME_MISC::UMLSLL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm_INDEX3_10(opcode) => opcode.bits(),
            SME_MISC::UMLSLL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm_INDEX4_10(opcode) => opcode.bits(),
            SME_MISC::UMLSL_SME_ZA_array_off2x2_SME_Znx2_SME_Zm_INDEX3_2(opcode) => opcode.bits(),
            SME_MISC::UMLSL_SME_ZA_array_off2x2_SME_Znx2_SME_Zmx2(opcode) => opcode.bits(),
            SME_MISC::UMLSL_SME_ZA_array_off2x2_SME_Znx4_SME_Zm_INDEX3_2(opcode) => opcode.bits(),
            SME_MISC::UMLSL_SME_ZA_array_off2x2_SME_Znx4_SME_Zmx4(opcode) => opcode.bits(),
            SME_MISC::UMLSL_SME_ZA_array_off2x2_SVE_ZnxN_SME_Zm(opcode) => opcode.bits(),
            SME_MISC::UMLSL_SME_ZA_array_off2x2_S_S_SVE_ZnxN_S_H_SME_Zm_S_H(opcode) => {
                opcode.bits()
            }
            SME_MISC::UMLSL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm(opcode) => opcode.bits(),
            SME_MISC::UMLSL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm_INDEX3_10(opcode) => opcode.bits(),
            SME_MISC::UMOPA_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SME_MISC::UMOPA_SME_ZAda_2b_S_S_SVE_Pg3_P_M_SME_Pm_P_M_SVE_Zn_S_B_SVE_Zm_16_S_B(
                opcode,
            ) => opcode.bits(),
            SME_MISC::UMOPA_SME_ZAda_3b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SME_MISC::UMOPS_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SME_MISC::UMOPS_SME_ZAda_2b_S_S_SVE_Pg3_P_M_SME_Pm_P_M_SVE_Zn_S_B_SVE_Zm_16_S_B(
                opcode,
            ) => opcode.bits(),
            SME_MISC::UMOPS_SME_ZAda_3b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SME_MISC::UQCVT_SVE_Zd_SME_Znx2(opcode) => opcode.bits(),
            SME_MISC::UQRSHRN_SVE_Zd_SME_Znx2_SME_SHRIMM4(opcode) => opcode.bits(),
            SME_MISC::UQRSHR_SVE_Zd_SME_Znx2_SME_SHRIMM4(opcode) => opcode.bits(),
            SME_MISC::USDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2(opcode) => opcode.bits(),
            SME_MISC::USDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zmx2(opcode) => opcode.bits(),
            SME_MISC::USDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2(opcode) => opcode.bits(),
            SME_MISC::USDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zmx4(opcode) => opcode.bits(),
            SME_MISC::USDOT_SME_ZA_array_off3_0_SVE_ZnxN_SME_Zm(opcode) => opcode.bits(),
            SME_MISC::USDOT_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_B_SME_Zm_S_B(opcode) => {
                opcode.bits()
            }
            SME_MISC::USMLALL_SME_ZA_array_off1x4_SME_Znx2_SME_Zm_INDEX4_1(opcode) => opcode.bits(),
            SME_MISC::USMLALL_SME_ZA_array_off1x4_SME_Znx2_SME_Zmx2(opcode) => opcode.bits(),
            SME_MISC::USMLALL_SME_ZA_array_off1x4_SME_Znx4_SME_Zm_INDEX4_1(opcode) => opcode.bits(),
            SME_MISC::USMLALL_SME_ZA_array_off1x4_SME_Znx4_SME_Zmx4(opcode) => opcode.bits(),
            SME_MISC::USMLALL_SME_ZA_array_off1x4_SVE_ZnxN_SME_Zm(opcode) => opcode.bits(),
            SME_MISC::USMLALL_SME_ZA_array_off1x4_S_S_SVE_ZnxN_S_B_SME_Zm_S_B(opcode) => {
                opcode.bits()
            }
            SME_MISC::USMLALL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm(opcode) => opcode.bits(),
            SME_MISC::USMLALL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm_INDEX4_10(opcode) => opcode.bits(),
            SME_MISC::USMOPA_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SME_MISC::USMOPA_SME_ZAda_3b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SME_MISC::USMOPS_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SME_MISC::USMOPS_SME_ZAda_3b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SME_MISC::USVDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2(opcode) => opcode.bits(),
            SME_MISC::UVDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2(opcode) => opcode.bits(),
            SME_MISC::UVDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX1(opcode) => opcode.bits(),
            SME_MISC::UVDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2(opcode) => opcode.bits(),
            SME_MISC::UZP_SME_Zdnx2_S_Q_SVE_Zn_S_Q_SVE_Zm_16_S_Q(opcode) => opcode.bits(),
            SME_MISC::UZP_SME_Zdnx4_S_Q_SME_Znx4_S_Q(opcode) => opcode.bits(),
            SME_MISC::ZERO_SME_ZT0_LIST(opcode) => opcode.bits(),
            SME_MISC::ZERO_SME_list_of_64bit_tiles(opcode) => opcode.bits(),
            SME_MISC::ZIP_SME_Zdnx2_S_Q_SVE_Zn_S_Q_SVE_Zm_16_S_Q(opcode) => opcode.bits(),
            SME_MISC::ZIP_SME_Zdnx4_S_Q_SME_Znx4_S_Q(opcode) => opcode.bits(),
        }
    }
}
impl InsnOpcode for DP_1SRC {
    fn definition(&self) -> &'static Insn {
        match self {
            DP_1SRC::AUTDA_Rd_Rn_SP(opcode) => opcode.definition(),
            DP_1SRC::AUTDB_Rd_Rn_SP(opcode) => opcode.definition(),
            DP_1SRC::AUTDZA_Rd(opcode) => opcode.definition(),
            DP_1SRC::AUTDZB_Rd(opcode) => opcode.definition(),
            DP_1SRC::AUTIA_Rd_Rn_SP(opcode) => opcode.definition(),
            DP_1SRC::AUTIB_Rd_Rn_SP(opcode) => opcode.definition(),
            DP_1SRC::AUTIZA_Rd(opcode) => opcode.definition(),
            DP_1SRC::AUTIZB_Rd(opcode) => opcode.definition(),
            DP_1SRC::CLS_Rd_Rn(opcode) => opcode.definition(),
            DP_1SRC::CLZ_Rd_Rn(opcode) => opcode.definition(),
            DP_1SRC::PACDA_Rd_Rn_SP(opcode) => opcode.definition(),
            DP_1SRC::PACDB_Rd_Rn_SP(opcode) => opcode.definition(),
            DP_1SRC::PACDZA_Rd(opcode) => opcode.definition(),
            DP_1SRC::PACDZB_Rd(opcode) => opcode.definition(),
            DP_1SRC::PACIA_Rd_Rn_SP(opcode) => opcode.definition(),
            DP_1SRC::PACIB_Rd_Rn_SP(opcode) => opcode.definition(),
            DP_1SRC::PACIZA_Rd(opcode) => opcode.definition(),
            DP_1SRC::PACIZB_Rd(opcode) => opcode.definition(),
            DP_1SRC::RBIT_Rd_Rn(opcode) => opcode.definition(),
            DP_1SRC::REV16_Rd_Rn(opcode) => opcode.definition(),
            DP_1SRC::REV32_Rd_Rn(opcode) => opcode.definition(),
            DP_1SRC::REV_Rd_Rn(opcode) => opcode.definition(),
            DP_1SRC::REV_Rd_X_Rn_X(opcode) => opcode.definition(),
            DP_1SRC::XPACD_Rd(opcode) => opcode.definition(),
            DP_1SRC::XPACI_Rd(opcode) => opcode.definition(),
        }
    }
    fn bits(&self) -> u32 {
        match self {
            DP_1SRC::AUTDA_Rd_Rn_SP(opcode) => opcode.bits(),
            DP_1SRC::AUTDB_Rd_Rn_SP(opcode) => opcode.bits(),
            DP_1SRC::AUTDZA_Rd(opcode) => opcode.bits(),
            DP_1SRC::AUTDZB_Rd(opcode) => opcode.bits(),
            DP_1SRC::AUTIA_Rd_Rn_SP(opcode) => opcode.bits(),
            DP_1SRC::AUTIB_Rd_Rn_SP(opcode) => opcode.bits(),
            DP_1SRC::AUTIZA_Rd(opcode) => opcode.bits(),
            DP_1SRC::AUTIZB_Rd(opcode) => opcode.bits(),
            DP_1SRC::CLS_Rd_Rn(opcode) => opcode.bits(),
            DP_1SRC::CLZ_Rd_Rn(opcode) => opcode.bits(),
            DP_1SRC::PACDA_Rd_Rn_SP(opcode) => opcode.bits(),
            DP_1SRC::PACDB_Rd_Rn_SP(opcode) => opcode.bits(),
            DP_1SRC::PACDZA_Rd(opcode) => opcode.bits(),
            DP_1SRC::PACDZB_Rd(opcode) => opcode.bits(),
            DP_1SRC::PACIA_Rd_Rn_SP(opcode) => opcode.bits(),
            DP_1SRC::PACIB_Rd_Rn_SP(opcode) => opcode.bits(),
            DP_1SRC::PACIZA_Rd(opcode) => opcode.bits(),
            DP_1SRC::PACIZB_Rd(opcode) => opcode.bits(),
            DP_1SRC::RBIT_Rd_Rn(opcode) => opcode.bits(),
            DP_1SRC::REV16_Rd_Rn(opcode) => opcode.bits(),
            DP_1SRC::REV32_Rd_Rn(opcode) => opcode.bits(),
            DP_1SRC::REV_Rd_Rn(opcode) => opcode.bits(),
            DP_1SRC::REV_Rd_X_Rn_X(opcode) => opcode.bits(),
            DP_1SRC::XPACD_Rd(opcode) => opcode.bits(),
            DP_1SRC::XPACI_Rd(opcode) => opcode.bits(),
        }
    }
}
impl InsnOpcode for CRYPTOAES {
    fn definition(&self) -> &'static Insn {
        match self {
            CRYPTOAES::AESD_Vd_Vn(opcode) => opcode.definition(),
            CRYPTOAES::AESE_Vd_Vn(opcode) => opcode.definition(),
            CRYPTOAES::AESIMC_Vd_Vn(opcode) => opcode.definition(),
            CRYPTOAES::AESMC_Vd_Vn(opcode) => opcode.definition(),
        }
    }
    fn bits(&self) -> u32 {
        match self {
            CRYPTOAES::AESD_Vd_Vn(opcode) => opcode.bits(),
            CRYPTOAES::AESE_Vd_Vn(opcode) => opcode.bits(),
            CRYPTOAES::AESIMC_Vd_Vn(opcode) => opcode.bits(),
            CRYPTOAES::AESMC_Vd_Vn(opcode) => opcode.bits(),
        }
    }
}
impl InsnOpcode for SVE_MISC {
    fn definition(&self) -> &'static Insn {
        match self {
            SVE_MISC::ADDPL_Rd_SP_SVE_Rn_SP_SVE_SIMM6(opcode) => opcode.definition(),
            SVE_MISC::ADDVL_Rd_SP_SVE_Rn_SP_SVE_SIMM6(opcode) => opcode.definition(),
            SVE_MISC::ADR_SVE_Zd_SVE_ADDR_ZZ_SXTW(opcode) => opcode.definition(),
            SVE_MISC::ADR_SVE_Zd_SVE_ADDR_ZZ_UXTW(opcode) => opcode.definition(),
            SVE_MISC::AESD_SVE_Zd_SVE_Zd_SVE_Zn(opcode) => opcode.definition(),
            SVE_MISC::AESE_SVE_Zd_SVE_Zd_SVE_Zn(opcode) => opcode.definition(),
            SVE_MISC::AESIMC_SVE_Zd_SVE_Zd(opcode) => opcode.definition(),
            SVE_MISC::AESMC_SVE_Zd_SVE_Zd(opcode) => opcode.definition(),
            SVE_MISC::ANDS_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm(opcode) => opcode.definition(),
            SVE_MISC::AND_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm(opcode) => opcode.definition(),
            SVE_MISC::AND_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_MISC::BCAX_SVE_Zd_SVE_Zd_SVE_Zm_16_SVE_Zn(opcode) => opcode.definition(),
            SVE_MISC::BFADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(opcode) => opcode.definition(),
            SVE_MISC::BFADD_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_MISC::BFCLAMP_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_MISC::BFCVTNT_SVE_Zd_SVE_Pg3_SVE_Zn(opcode) => opcode.definition(),
            SVE_MISC::BFCVT_SVE_Zd_SVE_Pg3_SVE_Zn(opcode) => opcode.definition(),
            SVE_MISC::BFDOT_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX(opcode) => opcode.definition(),
            SVE_MISC::BFDOT_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_MISC::BFMAXNM_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(opcode) => opcode.definition(),
            SVE_MISC::BFMAX_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(opcode) => opcode.definition(),
            SVE_MISC::BFMINNM_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(opcode) => opcode.definition(),
            SVE_MISC::BFMIN_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(opcode) => opcode.definition(),
            SVE_MISC::BFMLALB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX(opcode) => opcode.definition(),
            SVE_MISC::BFMLALB_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_MISC::BFMLALT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX(opcode) => opcode.definition(),
            SVE_MISC::BFMLALT_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_MISC::BFMLA_SVE_Zd_SVE_Pg3_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_MISC::BFMLA_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX(opcode) => opcode.definition(),
            SVE_MISC::BFMLSLB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX(opcode) => opcode.definition(),
            SVE_MISC::BFMLSLB_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_MISC::BFMLSLT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX(opcode) => opcode.definition(),
            SVE_MISC::BFMLSLT_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_MISC::BFMLS_SVE_Zd_SVE_Pg3_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_MISC::BFMLS_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX(opcode) => opcode.definition(),
            SVE_MISC::BFMMLA_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_MISC::BFMUL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(opcode) => opcode.definition(),
            SVE_MISC::BFMUL_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX(opcode) => opcode.definition(),
            SVE_MISC::BFMUL_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_MISC::BFSUB_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(opcode) => opcode.definition(),
            SVE_MISC::BFSUB_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_MISC::BICS_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm(opcode) => opcode.definition(),
            SVE_MISC::BIC_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm(opcode) => opcode.definition(),
            SVE_MISC::BIC_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_MISC::BRKAS_SVE_Pd_SVE_Pg4_10_SVE_Pn(opcode) => opcode.definition(),
            SVE_MISC::BRKBS_SVE_Pd_SVE_Pg4_10_SVE_Pn(opcode) => opcode.definition(),
            SVE_MISC::BRKNS_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pd(opcode) => opcode.definition(),
            SVE_MISC::BRKN_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pd(opcode) => opcode.definition(),
            SVE_MISC::BRKPAS_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm(opcode) => opcode.definition(),
            SVE_MISC::BRKPA_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm(opcode) => opcode.definition(),
            SVE_MISC::BRKPBS_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm(opcode) => opcode.definition(),
            SVE_MISC::BRKPB_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm(opcode) => opcode.definition(),
            SVE_MISC::BSL1N_SVE_Zd_SVE_Zd_SVE_Zm_16_SVE_Zn(opcode) => opcode.definition(),
            SVE_MISC::BSL2N_SVE_Zd_SVE_Zd_SVE_Zm_16_SVE_Zn(opcode) => opcode.definition(),
            SVE_MISC::BSL_SVE_Zd_SVE_Zd_SVE_Zm_16_SVE_Zn(opcode) => opcode.definition(),
            SVE_MISC::CDOT_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX_SVE_IMM_ROT2(opcode) => opcode.definition(),
            SVE_MISC::CDOT_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX_SVE_IMM_ROT2(opcode) => opcode.definition(),
            SVE_MISC::CMLA_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX_SVE_IMM_ROT2(opcode) => opcode.definition(),
            SVE_MISC::CMLA_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX_SVE_IMM_ROT2(opcode) => opcode.definition(),
            SVE_MISC::CNTB_Rd_SVE_PATTERN_SCALED(opcode) => opcode.definition(),
            SVE_MISC::CNTD_Rd_SVE_PATTERN_SCALED(opcode) => opcode.definition(),
            SVE_MISC::CNTH_Rd_SVE_PATTERN_SCALED(opcode) => opcode.definition(),
            SVE_MISC::CNTW_Rd_SVE_PATTERN_SCALED(opcode) => opcode.definition(),
            SVE_MISC::DECB_Rd_SVE_PATTERN_SCALED(opcode) => opcode.definition(),
            SVE_MISC::DECD_Rd_SVE_PATTERN_SCALED(opcode) => opcode.definition(),
            SVE_MISC::DECD_SVE_Zd_SVE_PATTERN_SCALED(opcode) => opcode.definition(),
            SVE_MISC::DECH_Rd_SVE_PATTERN_SCALED(opcode) => opcode.definition(),
            SVE_MISC::DECH_SVE_Zd_SVE_PATTERN_SCALED(opcode) => opcode.definition(),
            SVE_MISC::DECW_Rd_SVE_PATTERN_SCALED(opcode) => opcode.definition(),
            SVE_MISC::DECW_SVE_Zd_SVE_PATTERN_SCALED(opcode) => opcode.definition(),
            SVE_MISC::EOR3_SVE_Zd_SVE_Zd_SVE_Zm_16_SVE_Zn(opcode) => opcode.definition(),
            SVE_MISC::EORS_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm(opcode) => opcode.definition(),
            SVE_MISC::EOR_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm(opcode) => opcode.definition(),
            SVE_MISC::EOR_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_MISC::EXTQ_SVE_Zd_SVE_Zd_SVE_Zm_imm4(opcode) => opcode.definition(),
            SVE_MISC::EXT_SVE_Zd_SVE_Zd_SVE_Zm_5_SVE_UIMM8_53(opcode) => opcode.definition(),
            SVE_MISC::EXT_SVE_Zd_SVE_ZnxN_SVE_UIMM8_53(opcode) => opcode.definition(),
            SVE_MISC::FCMLA_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX_SVE_IMM_ROT2(opcode) => opcode.definition(),
            SVE_MISC::FCMLA_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX_SVE_IMM_ROT2(opcode) => opcode.definition(),
            SVE_MISC::FCVTLT_SVE_Zd_SVE_Pg3_SVE_Zn(opcode) => opcode.definition(),
            SVE_MISC::FCVTLT_SVE_Zd_S_D_SVE_Pg3_P_M_SVE_Zn_S_S(opcode) => opcode.definition(),
            SVE_MISC::FCVTNT_SVE_Zd_SVE_Pg3_SVE_Zn(opcode) => opcode.definition(),
            SVE_MISC::FCVTNT_SVE_Zd_S_S_SVE_Pg3_P_M_SVE_Zn_S_D(opcode) => opcode.definition(),
            SVE_MISC::FCVTN_SVE_Zd_SME_Znx2(opcode) => opcode.definition(),
            SVE_MISC::FCVTXNT_SVE_Zd_SVE_Pg3_SVE_Zn(opcode) => opcode.definition(),
            SVE_MISC::FCVTX_SVE_Zd_SVE_Pg3_SVE_Zn(opcode) => opcode.definition(),
            SVE_MISC::FCVTZS_SME_Zdnx2_SME_Znx2(opcode) => opcode.definition(),
            SVE_MISC::FCVTZS_SME_Zdnx4_SME_Znx4(opcode) => opcode.definition(),
            SVE_MISC::FCVTZS_SVE_Zd_SVE_Pg3_SVE_Zn(opcode) => opcode.definition(),
            SVE_MISC::FCVTZS_SVE_Zd_S_D_SVE_Pg3_P_M_SVE_Zn_S_D(opcode) => opcode.definition(),
            SVE_MISC::FCVTZS_SVE_Zd_S_D_SVE_Pg3_P_M_SVE_Zn_S_H(opcode) => opcode.definition(),
            SVE_MISC::FCVTZS_SVE_Zd_S_D_SVE_Pg3_P_M_SVE_Zn_S_S(opcode) => opcode.definition(),
            SVE_MISC::FCVTZS_SVE_Zd_S_H_SVE_Pg3_P_M_SVE_Zn_S_H(opcode) => opcode.definition(),
            SVE_MISC::FCVTZS_SVE_Zd_S_S_SVE_Pg3_P_M_SVE_Zn_S_D(opcode) => opcode.definition(),
            SVE_MISC::FCVTZS_SVE_Zd_S_S_SVE_Pg3_P_M_SVE_Zn_S_H(opcode) => opcode.definition(),
            SVE_MISC::FCVTZU_SME_Zdnx2_SME_Znx2(opcode) => opcode.definition(),
            SVE_MISC::FCVTZU_SME_Zdnx4_SME_Znx4(opcode) => opcode.definition(),
            SVE_MISC::FCVTZU_SVE_Zd_SVE_Pg3_SVE_Zn(opcode) => opcode.definition(),
            SVE_MISC::FCVTZU_SVE_Zd_S_D_SVE_Pg3_P_M_SVE_Zn_S_D(opcode) => opcode.definition(),
            SVE_MISC::FCVTZU_SVE_Zd_S_D_SVE_Pg3_P_M_SVE_Zn_S_H(opcode) => opcode.definition(),
            SVE_MISC::FCVTZU_SVE_Zd_S_D_SVE_Pg3_P_M_SVE_Zn_S_S(opcode) => opcode.definition(),
            SVE_MISC::FCVTZU_SVE_Zd_S_H_SVE_Pg3_P_M_SVE_Zn_S_H(opcode) => opcode.definition(),
            SVE_MISC::FCVTZU_SVE_Zd_S_S_SVE_Pg3_P_M_SVE_Zn_S_H(opcode) => opcode.definition(),
            SVE_MISC::FCVTZU_SVE_Zd_S_S_SVE_Pg3_P_M_SVE_Zn_S_S(opcode) => opcode.definition(),
            SVE_MISC::FCVT_SVE_Zd_SME_Znx2(opcode) => opcode.definition(),
            SVE_MISC::FCVT_SVE_Zd_SVE_Pg3_SVE_Zn(opcode) => opcode.definition(),
            SVE_MISC::FCVT_SVE_Zd_S_D_SVE_Pg3_P_M_SVE_Zn_S_H(opcode) => opcode.definition(),
            SVE_MISC::FCVT_SVE_Zd_S_D_SVE_Pg3_P_M_SVE_Zn_S_S(opcode) => opcode.definition(),
            SVE_MISC::FCVT_SVE_Zd_S_H_SVE_Pg3_P_M_SVE_Zn_S_D(opcode) => opcode.definition(),
            SVE_MISC::FCVT_SVE_Zd_S_S_SVE_Pg3_P_M_SVE_Zn_S_D(opcode) => opcode.definition(),
            SVE_MISC::FCVT_SVE_Zd_S_S_SVE_Pg3_P_M_SVE_Zn_S_H(opcode) => opcode.definition(),
            SVE_MISC::FDOT_SVE_Zd_SVE_Zn_SVE_Zm3_19_INDEX(opcode) => opcode.definition(),
            SVE_MISC::FDOT_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_MISC::FMLALB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX(opcode) => opcode.definition(),
            SVE_MISC::FMLALB_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_MISC::FMLALT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX(opcode) => opcode.definition(),
            SVE_MISC::FMLALT_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_MISC::FMLA_SVE_Zd_SVE_Zn_SVE_Zm3_22_INDEX(opcode) => opcode.definition(),
            SVE_MISC::FMLA_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX(opcode) => opcode.definition(),
            SVE_MISC::FMLA_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX(opcode) => opcode.definition(),
            SVE_MISC::FMLSLB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX(opcode) => opcode.definition(),
            SVE_MISC::FMLSLB_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_MISC::FMLSLT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX(opcode) => opcode.definition(),
            SVE_MISC::FMLSLT_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_MISC::FMLS_SVE_Zd_SVE_Zn_SVE_Zm3_22_INDEX(opcode) => opcode.definition(),
            SVE_MISC::FMLS_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX(opcode) => opcode.definition(),
            SVE_MISC::FMLS_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX(opcode) => opcode.definition(),
            SVE_MISC::FMMLA_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_MISC::FMMLA_SVE_Zd_S_D_SVE_Zn_S_D_SVE_Zm_16_S_D(opcode) => opcode.definition(),
            SVE_MISC::FMUL_SVE_Zd_SVE_Zn_SVE_Zm3_22_INDEX(opcode) => opcode.definition(),
            SVE_MISC::FMUL_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX(opcode) => opcode.definition(),
            SVE_MISC::FMUL_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX(opcode) => opcode.definition(),
            SVE_MISC::FRINTA_SME_Zdnx2_SME_Znx2(opcode) => opcode.definition(),
            SVE_MISC::FRINTA_SME_Zdnx4_SME_Znx4(opcode) => opcode.definition(),
            SVE_MISC::FRINTM_SME_Zdnx2_SME_Znx2(opcode) => opcode.definition(),
            SVE_MISC::FRINTM_SME_Zdnx4_SME_Znx4(opcode) => opcode.definition(),
            SVE_MISC::FRINTN_SME_Zdnx2_SME_Znx2(opcode) => opcode.definition(),
            SVE_MISC::FRINTN_SME_Zdnx4_SME_Znx4(opcode) => opcode.definition(),
            SVE_MISC::FRINTP_SME_Zdnx2_SME_Znx2(opcode) => opcode.definition(),
            SVE_MISC::FRINTP_SME_Zdnx4_SME_Znx4(opcode) => opcode.definition(),
            SVE_MISC::HISTSEG_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_MISC::INCB_Rd_SVE_PATTERN_SCALED(opcode) => opcode.definition(),
            SVE_MISC::INCD_Rd_SVE_PATTERN_SCALED(opcode) => opcode.definition(),
            SVE_MISC::INCD_SVE_Zd_SVE_PATTERN_SCALED(opcode) => opcode.definition(),
            SVE_MISC::INCH_Rd_SVE_PATTERN_SCALED(opcode) => opcode.definition(),
            SVE_MISC::INCH_SVE_Zd_SVE_PATTERN_SCALED(opcode) => opcode.definition(),
            SVE_MISC::INCW_Rd_SVE_PATTERN_SCALED(opcode) => opcode.definition(),
            SVE_MISC::INCW_SVE_Zd_SVE_PATTERN_SCALED(opcode) => opcode.definition(),
            SVE_MISC::LD1B_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_R(opcode) => opcode.definition(),
            SVE_MISC::LD1B_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_RR(opcode) => opcode.definition(),
            SVE_MISC::LD1B_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL(opcode) => opcode.definition(),
            SVE_MISC::LD1B_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR(opcode) => opcode.definition(),
            SVE_MISC::LD1B_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL(opcode) => opcode.definition(),
            SVE_MISC::LD1B_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR(opcode) => opcode.definition(),
            SVE_MISC::LD1B_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL(opcode) => {
                opcode.definition()
            }
            SVE_MISC::LD1B_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR(opcode) => opcode.definition(),
            SVE_MISC::LD1B_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL(opcode) => {
                opcode.definition()
            }
            SVE_MISC::LD1B_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR(opcode) => opcode.definition(),
            SVE_MISC::LD1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL(opcode) => opcode.definition(),
            SVE_MISC::LD1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX(opcode) => opcode.definition(),
            SVE_MISC::LD1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ(opcode) => opcode.definition(),
            SVE_MISC::LD1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22(opcode) => opcode.definition(),
            SVE_MISC::LD1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5(opcode) => opcode.definition(),
            SVE_MISC::LD1B_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL(opcode) => {
                opcode.definition()
            }
            SVE_MISC::LD1B_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RX(opcode) => opcode.definition(),
            SVE_MISC::LD1B_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW_22_S_D(opcode) => {
                opcode.definition()
            }
            SVE_MISC::LD1B_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_ZI_U5_S_D(opcode) => {
                opcode.definition()
            }
            SVE_MISC::LD1B_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL(opcode) => {
                opcode.definition()
            }
            SVE_MISC::LD1B_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RX(opcode) => opcode.definition(),
            SVE_MISC::LD1B_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL(opcode) => {
                opcode.definition()
            }
            SVE_MISC::LD1B_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RX(opcode) => opcode.definition(),
            SVE_MISC::LD1D_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_R(opcode) => opcode.definition(),
            SVE_MISC::LD1D_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_RR_LSL3(opcode) => {
                opcode.definition()
            }
            SVE_MISC::LD1D_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL(opcode) => opcode.definition(),
            SVE_MISC::LD1D_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR_LSL3(opcode) => opcode.definition(),
            SVE_MISC::LD1D_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL(opcode) => opcode.definition(),
            SVE_MISC::LD1D_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR_LSL3(opcode) => opcode.definition(),
            SVE_MISC::LD1D_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL(opcode) => {
                opcode.definition()
            }
            SVE_MISC::LD1D_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL3(opcode) => {
                opcode.definition()
            }
            SVE_MISC::LD1D_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL(opcode) => {
                opcode.definition()
            }
            SVE_MISC::LD1D_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL3(opcode) => {
                opcode.definition()
            }
            SVE_MISC::LD1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL(opcode) => opcode.definition(),
            SVE_MISC::LD1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL3(opcode) => opcode.definition(),
            SVE_MISC::LD1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ(opcode) => opcode.definition(),
            SVE_MISC::LD1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL3(opcode) => opcode.definition(),
            SVE_MISC::LD1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW3_22(opcode) => opcode.definition(),
            SVE_MISC::LD1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22(opcode) => opcode.definition(),
            SVE_MISC::LD1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x8(opcode) => opcode.definition(),
            SVE_MISC::LD1H_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_R(opcode) => opcode.definition(),
            SVE_MISC::LD1H_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_RR_LSL1(opcode) => {
                opcode.definition()
            }
            SVE_MISC::LD1H_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL(opcode) => opcode.definition(),
            SVE_MISC::LD1H_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR_LSL1(opcode) => opcode.definition(),
            SVE_MISC::LD1H_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL(opcode) => opcode.definition(),
            SVE_MISC::LD1H_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR_LSL1(opcode) => opcode.definition(),
            SVE_MISC::LD1H_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL(opcode) => {
                opcode.definition()
            }
            SVE_MISC::LD1H_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL1(opcode) => {
                opcode.definition()
            }
            SVE_MISC::LD1H_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL(opcode) => {
                opcode.definition()
            }
            SVE_MISC::LD1H_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL1(opcode) => {
                opcode.definition()
            }
            SVE_MISC::LD1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL(opcode) => opcode.definition(),
            SVE_MISC::LD1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1(opcode) => opcode.definition(),
            SVE_MISC::LD1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ(opcode) => opcode.definition(),
            SVE_MISC::LD1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL1(opcode) => opcode.definition(),
            SVE_MISC::LD1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW1_22(opcode) => opcode.definition(),
            SVE_MISC::LD1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22(opcode) => opcode.definition(),
            SVE_MISC::LD1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x2(opcode) => opcode.definition(),
            SVE_MISC::LD1H_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL(opcode) => {
                opcode.definition()
            }
            SVE_MISC::LD1H_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RX_LSL1(opcode) => opcode.definition(),
            SVE_MISC::LD1H_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW1_22_S_D(opcode) => {
                opcode.definition()
            }
            SVE_MISC::LD1H_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW_22_S_D(opcode) => {
                opcode.definition()
            }
            SVE_MISC::LD1H_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_ZI_U5x2_S_D(opcode) => {
                opcode.definition()
            }
            SVE_MISC::LD1H_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL(opcode) => {
                opcode.definition()
            }
            SVE_MISC::LD1H_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RX_LSL1(opcode) => opcode.definition(),
            SVE_MISC::LD1Q_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_R(opcode) => opcode.definition(),
            SVE_MISC::LD1Q_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_RR_LSL4(opcode) => {
                opcode.definition()
            }
            SVE_MISC::LD1Q_SVE_Zt_SVE_Pg3_SVE_ADDR_ZX(opcode) => opcode.definition(),
            SVE_MISC::LD1RB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_U6(opcode) => opcode.definition(),
            SVE_MISC::LD1RB_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RI_U6(opcode) => opcode.definition(),
            SVE_MISC::LD1RB_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RI_U6(opcode) => opcode.definition(),
            SVE_MISC::LD1RB_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RI_U6(opcode) => opcode.definition(),
            SVE_MISC::LD1RD_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_U6x8(opcode) => opcode.definition(),
            SVE_MISC::LD1RH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_U6x2(opcode) => opcode.definition(),
            SVE_MISC::LD1RH_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RI_U6x2(opcode) => {
                opcode.definition()
            }
            SVE_MISC::LD1RH_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RI_U6x2(opcode) => {
                opcode.definition()
            }
            SVE_MISC::LD1ROB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x32(opcode) => opcode.definition(),
            SVE_MISC::LD1ROB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX(opcode) => opcode.definition(),
            SVE_MISC::LD1ROD_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x32(opcode) => opcode.definition(),
            SVE_MISC::LD1ROD_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL3(opcode) => opcode.definition(),
            SVE_MISC::LD1ROH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x32(opcode) => opcode.definition(),
            SVE_MISC::LD1ROH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1(opcode) => opcode.definition(),
            SVE_MISC::LD1ROW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x32(opcode) => opcode.definition(),
            SVE_MISC::LD1ROW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2(opcode) => opcode.definition(),
            SVE_MISC::LD1RQB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x16(opcode) => opcode.definition(),
            SVE_MISC::LD1RQB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX(opcode) => opcode.definition(),
            SVE_MISC::LD1RQD_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x16(opcode) => opcode.definition(),
            SVE_MISC::LD1RQD_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL3(opcode) => opcode.definition(),
            SVE_MISC::LD1RQH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x16(opcode) => opcode.definition(),
            SVE_MISC::LD1RQH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1(opcode) => opcode.definition(),
            SVE_MISC::LD1RQW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x16(opcode) => opcode.definition(),
            SVE_MISC::LD1RQW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2(opcode) => opcode.definition(),
            SVE_MISC::LD1RSB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_U6(opcode) => opcode.definition(),
            SVE_MISC::LD1RSB_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RI_U6(opcode) => opcode.definition(),
            SVE_MISC::LD1RSB_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RI_U6(opcode) => opcode.definition(),
            SVE_MISC::LD1RSH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_U6x2(opcode) => opcode.definition(),
            SVE_MISC::LD1RSH_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RI_U6x2(opcode) => {
                opcode.definition()
            }
            SVE_MISC::LD1RSW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_U6x4(opcode) => opcode.definition(),
            SVE_MISC::LD1RW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_U6x4(opcode) => opcode.definition(),
            SVE_MISC::LD1RW_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RI_U6x4(opcode) => {
                opcode.definition()
            }
            SVE_MISC::LD1SB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL(opcode) => opcode.definition(),
            SVE_MISC::LD1SB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX(opcode) => opcode.definition(),
            SVE_MISC::LD1SB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ(opcode) => opcode.definition(),
            SVE_MISC::LD1SB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22(opcode) => opcode.definition(),
            SVE_MISC::LD1SB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5(opcode) => opcode.definition(),
            SVE_MISC::LD1SB_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW_22_S_D(opcode) => {
                opcode.definition()
            }
            SVE_MISC::LD1SB_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_ZI_U5_S_D(opcode) => {
                opcode.definition()
            }
            SVE_MISC::LD1SB_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL(opcode) => {
                opcode.definition()
            }
            SVE_MISC::LD1SB_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RX(opcode) => opcode.definition(),
            SVE_MISC::LD1SB_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL(opcode) => {
                opcode.definition()
            }
            SVE_MISC::LD1SB_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RX(opcode) => opcode.definition(),
            SVE_MISC::LD1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL(opcode) => opcode.definition(),
            SVE_MISC::LD1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1(opcode) => opcode.definition(),
            SVE_MISC::LD1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ(opcode) => opcode.definition(),
            SVE_MISC::LD1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL1(opcode) => opcode.definition(),
            SVE_MISC::LD1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW1_22(opcode) => opcode.definition(),
            SVE_MISC::LD1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22(opcode) => opcode.definition(),
            SVE_MISC::LD1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x2(opcode) => opcode.definition(),
            SVE_MISC::LD1SH_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW1_22_S_D(opcode) => {
                opcode.definition()
            }
            SVE_MISC::LD1SH_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW_22_S_D(opcode) => {
                opcode.definition()
            }
            SVE_MISC::LD1SH_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_ZI_U5x2_S_D(opcode) => {
                opcode.definition()
            }
            SVE_MISC::LD1SH_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL(opcode) => {
                opcode.definition()
            }
            SVE_MISC::LD1SH_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RX_LSL1(opcode) => {
                opcode.definition()
            }
            SVE_MISC::LD1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL(opcode) => opcode.definition(),
            SVE_MISC::LD1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2(opcode) => opcode.definition(),
            SVE_MISC::LD1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ(opcode) => opcode.definition(),
            SVE_MISC::LD1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL2(opcode) => opcode.definition(),
            SVE_MISC::LD1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW2_22(opcode) => opcode.definition(),
            SVE_MISC::LD1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22(opcode) => opcode.definition(),
            SVE_MISC::LD1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x4(opcode) => opcode.definition(),
            SVE_MISC::LD1W_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_R(opcode) => opcode.definition(),
            SVE_MISC::LD1W_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_RR_LSL2(opcode) => {
                opcode.definition()
            }
            SVE_MISC::LD1W_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL(opcode) => opcode.definition(),
            SVE_MISC::LD1W_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR_LSL2(opcode) => opcode.definition(),
            SVE_MISC::LD1W_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL(opcode) => opcode.definition(),
            SVE_MISC::LD1W_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR_LSL2(opcode) => opcode.definition(),
            SVE_MISC::LD1W_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL(opcode) => {
                opcode.definition()
            }
            SVE_MISC::LD1W_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL2(opcode) => {
                opcode.definition()
            }
            SVE_MISC::LD1W_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL(opcode) => {
                opcode.definition()
            }
            SVE_MISC::LD1W_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL2(opcode) => {
                opcode.definition()
            }
            SVE_MISC::LD1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL(opcode) => opcode.definition(),
            SVE_MISC::LD1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2(opcode) => opcode.definition(),
            SVE_MISC::LD1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ(opcode) => opcode.definition(),
            SVE_MISC::LD1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL2(opcode) => opcode.definition(),
            SVE_MISC::LD1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW2_22(opcode) => opcode.definition(),
            SVE_MISC::LD1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22(opcode) => opcode.definition(),
            SVE_MISC::LD1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x4(opcode) => opcode.definition(),
            SVE_MISC::LD1W_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL(opcode) => {
                opcode.definition()
            }
            SVE_MISC::LD1W_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RX_LSL2(opcode) => opcode.definition(),
            SVE_MISC::LD1W_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW2_22_S_D(opcode) => {
                opcode.definition()
            }
            SVE_MISC::LD1W_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW_22_S_D(opcode) => {
                opcode.definition()
            }
            SVE_MISC::LD1W_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_ZI_U5x4_S_D(opcode) => {
                opcode.definition()
            }
            SVE_MISC::LD2B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x2xVL(opcode) => opcode.definition(),
            SVE_MISC::LD2B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX(opcode) => opcode.definition(),
            SVE_MISC::LD2D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x2xVL(opcode) => opcode.definition(),
            SVE_MISC::LD2D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL3(opcode) => opcode.definition(),
            SVE_MISC::LD2H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x2xVL(opcode) => opcode.definition(),
            SVE_MISC::LD2H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1(opcode) => opcode.definition(),
            SVE_MISC::LD2Q_SME_Zt2_SVE_Pg3_SVE_ADDR_RI_S4x2xVL(opcode) => opcode.definition(),
            SVE_MISC::LD2Q_SME_Zt2_SVE_Pg3_SVE_ADDR_RR_LSL4(opcode) => opcode.definition(),
            SVE_MISC::LD2W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x2xVL(opcode) => opcode.definition(),
            SVE_MISC::LD2W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2(opcode) => opcode.definition(),
            SVE_MISC::LD3B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x3xVL(opcode) => opcode.definition(),
            SVE_MISC::LD3B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX(opcode) => opcode.definition(),
            SVE_MISC::LD3D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x3xVL(opcode) => opcode.definition(),
            SVE_MISC::LD3D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL3(opcode) => opcode.definition(),
            SVE_MISC::LD3H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x3xVL(opcode) => opcode.definition(),
            SVE_MISC::LD3H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1(opcode) => opcode.definition(),
            SVE_MISC::LD3Q_SME_Zt3_SVE_Pg3_SVE_ADDR_RI_S4x2xVL(opcode) => opcode.definition(),
            SVE_MISC::LD3Q_SME_Zt3_SVE_Pg3_SVE_ADDR_RR_LSL4(opcode) => opcode.definition(),
            SVE_MISC::LD3W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x3xVL(opcode) => opcode.definition(),
            SVE_MISC::LD3W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2(opcode) => opcode.definition(),
            SVE_MISC::LD4B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x4xVL(opcode) => opcode.definition(),
            SVE_MISC::LD4B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX(opcode) => opcode.definition(),
            SVE_MISC::LD4D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x4xVL(opcode) => opcode.definition(),
            SVE_MISC::LD4D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL3(opcode) => opcode.definition(),
            SVE_MISC::LD4H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x4xVL(opcode) => opcode.definition(),
            SVE_MISC::LD4H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1(opcode) => opcode.definition(),
            SVE_MISC::LD4Q_SME_Zt4_SVE_Pg3_SVE_ADDR_RI_S4x2xVL(opcode) => opcode.definition(),
            SVE_MISC::LD4Q_SME_Zt4_SVE_Pg3_SVE_ADDR_RR_LSL4(opcode) => opcode.definition(),
            SVE_MISC::LD4W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x4xVL(opcode) => opcode.definition(),
            SVE_MISC::LD4W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2(opcode) => opcode.definition(),
            SVE_MISC::LDFF1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_R(opcode) => opcode.definition(),
            SVE_MISC::LDFF1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RR(opcode) => opcode.definition(),
            SVE_MISC::LDFF1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ(opcode) => opcode.definition(),
            SVE_MISC::LDFF1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22(opcode) => opcode.definition(),
            SVE_MISC::LDFF1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5(opcode) => opcode.definition(),
            SVE_MISC::LDFF1B_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_R(opcode) => opcode.definition(),
            SVE_MISC::LDFF1B_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RR(opcode) => opcode.definition(),
            SVE_MISC::LDFF1B_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW_22_S_D(opcode) => {
                opcode.definition()
            }
            SVE_MISC::LDFF1B_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_ZI_U5_S_D(opcode) => {
                opcode.definition()
            }
            SVE_MISC::LDFF1B_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_R(opcode) => opcode.definition(),
            SVE_MISC::LDFF1B_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RR(opcode) => opcode.definition(),
            SVE_MISC::LDFF1B_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_R(opcode) => opcode.definition(),
            SVE_MISC::LDFF1B_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RR(opcode) => opcode.definition(),
            SVE_MISC::LDFF1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_R(opcode) => opcode.definition(),
            SVE_MISC::LDFF1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RR_LSL3(opcode) => opcode.definition(),
            SVE_MISC::LDFF1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ(opcode) => opcode.definition(),
            SVE_MISC::LDFF1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL3(opcode) => opcode.definition(),
            SVE_MISC::LDFF1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW3_22(opcode) => opcode.definition(),
            SVE_MISC::LDFF1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22(opcode) => opcode.definition(),
            SVE_MISC::LDFF1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x8(opcode) => opcode.definition(),
            SVE_MISC::LDFF1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_R(opcode) => opcode.definition(),
            SVE_MISC::LDFF1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RR_LSL1(opcode) => opcode.definition(),
            SVE_MISC::LDFF1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ(opcode) => opcode.definition(),
            SVE_MISC::LDFF1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL1(opcode) => opcode.definition(),
            SVE_MISC::LDFF1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW1_22(opcode) => opcode.definition(),
            SVE_MISC::LDFF1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22(opcode) => opcode.definition(),
            SVE_MISC::LDFF1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x2(opcode) => opcode.definition(),
            SVE_MISC::LDFF1H_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_R(opcode) => opcode.definition(),
            SVE_MISC::LDFF1H_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RR_LSL1(opcode) => {
                opcode.definition()
            }
            SVE_MISC::LDFF1H_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW1_22_S_D(opcode) => {
                opcode.definition()
            }
            SVE_MISC::LDFF1H_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW_22_S_D(opcode) => {
                opcode.definition()
            }
            SVE_MISC::LDFF1H_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_ZI_U5x2_S_D(opcode) => {
                opcode.definition()
            }
            SVE_MISC::LDFF1H_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_R(opcode) => opcode.definition(),
            SVE_MISC::LDFF1H_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RR_LSL1(opcode) => {
                opcode.definition()
            }
            SVE_MISC::LDFF1SB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_R(opcode) => opcode.definition(),
            SVE_MISC::LDFF1SB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RR(opcode) => opcode.definition(),
            SVE_MISC::LDFF1SB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ(opcode) => opcode.definition(),
            SVE_MISC::LDFF1SB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22(opcode) => opcode.definition(),
            SVE_MISC::LDFF1SB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5(opcode) => opcode.definition(),
            SVE_MISC::LDFF1SB_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW_22_S_D(opcode) => {
                opcode.definition()
            }
            SVE_MISC::LDFF1SB_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_ZI_U5_S_D(opcode) => {
                opcode.definition()
            }
            SVE_MISC::LDFF1SB_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_R(opcode) => opcode.definition(),
            SVE_MISC::LDFF1SB_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RR(opcode) => opcode.definition(),
            SVE_MISC::LDFF1SB_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_R(opcode) => opcode.definition(),
            SVE_MISC::LDFF1SB_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RR(opcode) => opcode.definition(),
            SVE_MISC::LDFF1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_R(opcode) => opcode.definition(),
            SVE_MISC::LDFF1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RR_LSL1(opcode) => opcode.definition(),
            SVE_MISC::LDFF1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ(opcode) => opcode.definition(),
            SVE_MISC::LDFF1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL1(opcode) => opcode.definition(),
            SVE_MISC::LDFF1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW1_22(opcode) => opcode.definition(),
            SVE_MISC::LDFF1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22(opcode) => opcode.definition(),
            SVE_MISC::LDFF1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x2(opcode) => opcode.definition(),
            SVE_MISC::LDFF1SH_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW1_22_S_D(opcode) => {
                opcode.definition()
            }
            SVE_MISC::LDFF1SH_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW_22_S_D(opcode) => {
                opcode.definition()
            }
            SVE_MISC::LDFF1SH_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_ZI_U5x2_S_D(opcode) => {
                opcode.definition()
            }
            SVE_MISC::LDFF1SH_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_R(opcode) => opcode.definition(),
            SVE_MISC::LDFF1SH_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RR_LSL1(opcode) => {
                opcode.definition()
            }
            SVE_MISC::LDFF1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_R(opcode) => opcode.definition(),
            SVE_MISC::LDFF1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RR_LSL2(opcode) => opcode.definition(),
            SVE_MISC::LDFF1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ(opcode) => opcode.definition(),
            SVE_MISC::LDFF1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL2(opcode) => opcode.definition(),
            SVE_MISC::LDFF1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW2_22(opcode) => opcode.definition(),
            SVE_MISC::LDFF1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22(opcode) => opcode.definition(),
            SVE_MISC::LDFF1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x4(opcode) => opcode.definition(),
            SVE_MISC::LDFF1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_R(opcode) => opcode.definition(),
            SVE_MISC::LDFF1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RR_LSL2(opcode) => opcode.definition(),
            SVE_MISC::LDFF1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ(opcode) => opcode.definition(),
            SVE_MISC::LDFF1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL2(opcode) => opcode.definition(),
            SVE_MISC::LDFF1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW2_22(opcode) => opcode.definition(),
            SVE_MISC::LDFF1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22(opcode) => opcode.definition(),
            SVE_MISC::LDFF1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x4(opcode) => opcode.definition(),
            SVE_MISC::LDFF1W_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_R(opcode) => opcode.definition(),
            SVE_MISC::LDFF1W_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RR_LSL2(opcode) => {
                opcode.definition()
            }
            SVE_MISC::LDFF1W_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW2_22_S_D(opcode) => {
                opcode.definition()
            }
            SVE_MISC::LDFF1W_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW_22_S_D(opcode) => {
                opcode.definition()
            }
            SVE_MISC::LDFF1W_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_ZI_U5x4_S_D(opcode) => {
                opcode.definition()
            }
            SVE_MISC::LDNF1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL(opcode) => opcode.definition(),
            SVE_MISC::LDNF1B_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL(opcode) => {
                opcode.definition()
            }
            SVE_MISC::LDNF1B_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL(opcode) => {
                opcode.definition()
            }
            SVE_MISC::LDNF1B_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL(opcode) => {
                opcode.definition()
            }
            SVE_MISC::LDNF1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL(opcode) => opcode.definition(),
            SVE_MISC::LDNF1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL(opcode) => opcode.definition(),
            SVE_MISC::LDNF1H_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL(opcode) => {
                opcode.definition()
            }
            SVE_MISC::LDNF1H_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL(opcode) => {
                opcode.definition()
            }
            SVE_MISC::LDNF1SB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL(opcode) => opcode.definition(),
            SVE_MISC::LDNF1SB_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL(opcode) => {
                opcode.definition()
            }
            SVE_MISC::LDNF1SB_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL(opcode) => {
                opcode.definition()
            }
            SVE_MISC::LDNF1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL(opcode) => opcode.definition(),
            SVE_MISC::LDNF1SH_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL(opcode) => {
                opcode.definition()
            }
            SVE_MISC::LDNF1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL(opcode) => opcode.definition(),
            SVE_MISC::LDNF1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL(opcode) => opcode.definition(),
            SVE_MISC::LDNF1W_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL(opcode) => {
                opcode.definition()
            }
            SVE_MISC::LDNT1B_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL(opcode) => opcode.definition(),
            SVE_MISC::LDNT1B_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR(opcode) => opcode.definition(),
            SVE_MISC::LDNT1B_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL(opcode) => opcode.definition(),
            SVE_MISC::LDNT1B_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR(opcode) => opcode.definition(),
            SVE_MISC::LDNT1B_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL(opcode) => {
                opcode.definition()
            }
            SVE_MISC::LDNT1B_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR(opcode) => opcode.definition(),
            SVE_MISC::LDNT1B_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL(opcode) => {
                opcode.definition()
            }
            SVE_MISC::LDNT1B_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR(opcode) => opcode.definition(),
            SVE_MISC::LDNT1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL(opcode) => opcode.definition(),
            SVE_MISC::LDNT1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX(opcode) => opcode.definition(),
            SVE_MISC::LDNT1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZX(opcode) => opcode.definition(),
            SVE_MISC::LDNT1B_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_ZX_S_S(opcode) => {
                opcode.definition()
            }
            SVE_MISC::LDNT1D_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL(opcode) => opcode.definition(),
            SVE_MISC::LDNT1D_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR_LSL3(opcode) => opcode.definition(),
            SVE_MISC::LDNT1D_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL(opcode) => opcode.definition(),
            SVE_MISC::LDNT1D_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR_LSL3(opcode) => opcode.definition(),
            SVE_MISC::LDNT1D_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL(opcode) => {
                opcode.definition()
            }
            SVE_MISC::LDNT1D_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL3(opcode) => {
                opcode.definition()
            }
            SVE_MISC::LDNT1D_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL(opcode) => {
                opcode.definition()
            }
            SVE_MISC::LDNT1D_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL3(opcode) => {
                opcode.definition()
            }
            SVE_MISC::LDNT1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL(opcode) => opcode.definition(),
            SVE_MISC::LDNT1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL3(opcode) => opcode.definition(),
            SVE_MISC::LDNT1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZX(opcode) => opcode.definition(),
            SVE_MISC::LDNT1H_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL(opcode) => opcode.definition(),
            SVE_MISC::LDNT1H_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR_LSL1(opcode) => opcode.definition(),
            SVE_MISC::LDNT1H_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL(opcode) => opcode.definition(),
            SVE_MISC::LDNT1H_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR_LSL1(opcode) => opcode.definition(),
            SVE_MISC::LDNT1H_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL(opcode) => {
                opcode.definition()
            }
            SVE_MISC::LDNT1H_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL1(opcode) => {
                opcode.definition()
            }
            SVE_MISC::LDNT1H_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL(opcode) => {
                opcode.definition()
            }
            SVE_MISC::LDNT1H_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL1(opcode) => {
                opcode.definition()
            }
            SVE_MISC::LDNT1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL(opcode) => opcode.definition(),
            SVE_MISC::LDNT1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1(opcode) => opcode.definition(),
            SVE_MISC::LDNT1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZX(opcode) => opcode.definition(),
            SVE_MISC::LDNT1H_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_ZX_S_S(opcode) => {
                opcode.definition()
            }
            SVE_MISC::LDNT1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZX(opcode) => opcode.definition(),
            SVE_MISC::LDNT1W_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL(opcode) => opcode.definition(),
            SVE_MISC::LDNT1W_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR_LSL2(opcode) => opcode.definition(),
            SVE_MISC::LDNT1W_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL(opcode) => opcode.definition(),
            SVE_MISC::LDNT1W_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR_LSL2(opcode) => opcode.definition(),
            SVE_MISC::LDNT1W_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL(opcode) => {
                opcode.definition()
            }
            SVE_MISC::LDNT1W_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL2(opcode) => {
                opcode.definition()
            }
            SVE_MISC::LDNT1W_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL(opcode) => {
                opcode.definition()
            }
            SVE_MISC::LDNT1W_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL2(opcode) => {
                opcode.definition()
            }
            SVE_MISC::LDNT1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL(opcode) => opcode.definition(),
            SVE_MISC::LDNT1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2(opcode) => opcode.definition(),
            SVE_MISC::LDNT1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZX(opcode) => opcode.definition(),
            SVE_MISC::LDNT1W_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_ZX_S_D(opcode) => {
                opcode.definition()
            }
            SVE_MISC::LDR_SVE_PNt_SVE_ADDR_RI_S9xVL(opcode) => opcode.definition(),
            SVE_MISC::LDR_SVE_Pt_SVE_ADDR_RI_S9xVL(opcode) => opcode.definition(),
            SVE_MISC::LDR_SVE_Zt_SVE_ADDR_RI_S9xVL(opcode) => opcode.definition(),
            SVE_MISC::MLA_SVE_Zd_SVE_Zn_SVE_Zm3_22_INDEX(opcode) => opcode.definition(),
            SVE_MISC::MLA_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX(opcode) => opcode.definition(),
            SVE_MISC::MLA_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX(opcode) => opcode.definition(),
            SVE_MISC::MLS_SVE_Zd_SVE_Zn_SVE_Zm3_22_INDEX(opcode) => opcode.definition(),
            SVE_MISC::MLS_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX(opcode) => opcode.definition(),
            SVE_MISC::MLS_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX(opcode) => opcode.definition(),
            SVE_MISC::MOVPRFX_SVE_Zd_SVE_Zn(opcode) => opcode.definition(),
            SVE_MISC::MUL_SVE_Zd_SVE_Zn_SVE_Zm3_22_INDEX(opcode) => opcode.definition(),
            SVE_MISC::MUL_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX(opcode) => opcode.definition(),
            SVE_MISC::MUL_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX(opcode) => opcode.definition(),
            SVE_MISC::NANDS_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm(opcode) => opcode.definition(),
            SVE_MISC::NAND_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm(opcode) => opcode.definition(),
            SVE_MISC::NBSL_SVE_Zd_SVE_Zd_SVE_Zm_16_SVE_Zn(opcode) => opcode.definition(),
            SVE_MISC::NORS_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm(opcode) => opcode.definition(),
            SVE_MISC::NOR_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm(opcode) => opcode.definition(),
            SVE_MISC::ORNS_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm(opcode) => opcode.definition(),
            SVE_MISC::ORN_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm(opcode) => opcode.definition(),
            SVE_MISC::ORRS_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm(opcode) => opcode.definition(),
            SVE_MISC::ORR_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm(opcode) => opcode.definition(),
            SVE_MISC::ORR_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_MISC::PFALSE_SVE_PNd(opcode) => opcode.definition(),
            SVE_MISC::PFALSE_SVE_Pd(opcode) => opcode.definition(),
            SVE_MISC::PFIRST_SVE_Pd_SVE_Pg4_5_SVE_Pd(opcode) => opcode.definition(),
            SVE_MISC::PMULLB_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_MISC::PMULLT_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_MISC::PMUL_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_MISC::PRFB_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RI_S6xVL(opcode) => opcode.definition(),
            SVE_MISC::PRFB_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RX(opcode) => opcode.definition(),
            SVE_MISC::PRFB_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RZ(opcode) => opcode.definition(),
            SVE_MISC::PRFB_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RZ_XTW_22(opcode) => opcode.definition(),
            SVE_MISC::PRFB_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RZ_XTW_22_c4200000(opcode) => {
                opcode.definition()
            }
            SVE_MISC::PRFB_SVE_PRFOP_SVE_Pg3_SVE_ADDR_ZI_U5(opcode) => opcode.definition(),
            SVE_MISC::PRFB_SVE_PRFOP_SVE_Pg3_SVE_ADDR_ZI_U5_c400e000(opcode) => opcode.definition(),
            SVE_MISC::PRFD_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RI_S6xVL(opcode) => opcode.definition(),
            SVE_MISC::PRFD_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RX_LSL3(opcode) => opcode.definition(),
            SVE_MISC::PRFD_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RZ_LSL3(opcode) => opcode.definition(),
            SVE_MISC::PRFD_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RZ_XTW3_22(opcode) => opcode.definition(),
            SVE_MISC::PRFD_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RZ_XTW3_22_c4206000(opcode) => {
                opcode.definition()
            }
            SVE_MISC::PRFD_SVE_PRFOP_SVE_Pg3_SVE_ADDR_ZI_U5x8(opcode) => opcode.definition(),
            SVE_MISC::PRFD_SVE_PRFOP_SVE_Pg3_SVE_ADDR_ZI_U5x8_c580e000(opcode) => {
                opcode.definition()
            }
            SVE_MISC::PRFH_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RI_S6xVL(opcode) => opcode.definition(),
            SVE_MISC::PRFH_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RX_LSL1(opcode) => opcode.definition(),
            SVE_MISC::PRFH_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RZ_LSL1(opcode) => opcode.definition(),
            SVE_MISC::PRFH_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RZ_XTW1_22(opcode) => opcode.definition(),
            SVE_MISC::PRFH_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RZ_XTW1_22_c4202000(opcode) => {
                opcode.definition()
            }
            SVE_MISC::PRFH_SVE_PRFOP_SVE_Pg3_SVE_ADDR_ZI_U5x2(opcode) => opcode.definition(),
            SVE_MISC::PRFH_SVE_PRFOP_SVE_Pg3_SVE_ADDR_ZI_U5x2_c480e000(opcode) => {
                opcode.definition()
            }
            SVE_MISC::PRFW_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RI_S6xVL(opcode) => opcode.definition(),
            SVE_MISC::PRFW_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RX_LSL2(opcode) => opcode.definition(),
            SVE_MISC::PRFW_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RZ_LSL2(opcode) => opcode.definition(),
            SVE_MISC::PRFW_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RZ_XTW2_22(opcode) => opcode.definition(),
            SVE_MISC::PRFW_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RZ_XTW2_22_c4204000(opcode) => {
                opcode.definition()
            }
            SVE_MISC::PRFW_SVE_PRFOP_SVE_Pg3_SVE_ADDR_ZI_U5x4(opcode) => opcode.definition(),
            SVE_MISC::PRFW_SVE_PRFOP_SVE_Pg3_SVE_ADDR_ZI_U5x4_c500e000(opcode) => {
                opcode.definition()
            }
            SVE_MISC::PTEST_SVE_Pg4_10_SVE_Pn(opcode) => opcode.definition(),
            SVE_MISC::PUNPKHI_SVE_Pd_SVE_Pn(opcode) => opcode.definition(),
            SVE_MISC::PUNPKLO_SVE_Pd_SVE_Pn(opcode) => opcode.definition(),
            SVE_MISC::RAX1_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_MISC::RDFFRS_SVE_Pd_SVE_Pg4_5(opcode) => opcode.definition(),
            SVE_MISC::RDFFR_SVE_Pd(opcode) => opcode.definition(),
            SVE_MISC::RDFFR_SVE_Pd_SVE_Pg4_5(opcode) => opcode.definition(),
            SVE_MISC::RDVL_Rd_SVE_SIMM6(opcode) => opcode.definition(),
            SVE_MISC::REVW_SVE_Zd_SVE_Pg3_SVE_Zn(opcode) => opcode.definition(),
            SVE_MISC::SCVTF_SME_Zdnx2_SME_Znx2(opcode) => opcode.definition(),
            SVE_MISC::SCVTF_SME_Zdnx4_SME_Znx4(opcode) => opcode.definition(),
            SVE_MISC::SCVTF_SVE_Zd_SVE_Pg3_SVE_Zn(opcode) => opcode.definition(),
            SVE_MISC::SCVTF_SVE_Zd_S_D_SVE_Pg3_P_M_SVE_Zn_S_D(opcode) => opcode.definition(),
            SVE_MISC::SCVTF_SVE_Zd_S_H_SVE_Pg3_P_M_SVE_Zn_S_D(opcode) => opcode.definition(),
            SVE_MISC::SCVTF_SVE_Zd_S_H_SVE_Pg3_P_M_SVE_Zn_S_H(opcode) => opcode.definition(),
            SVE_MISC::SCVTF_SVE_Zd_S_H_SVE_Pg3_P_M_SVE_Zn_S_S(opcode) => opcode.definition(),
            SVE_MISC::SCVTF_SVE_Zd_S_S_SVE_Pg3_P_M_SVE_Zn_S_D(opcode) => opcode.definition(),
            SVE_MISC::SCVTF_SVE_Zd_S_S_SVE_Pg3_P_M_SVE_Zn_S_S(opcode) => opcode.definition(),
            SVE_MISC::SDOT_SVE_Zd_SVE_Zn_SVE_Zm3_19_INDEX(opcode) => opcode.definition(),
            SVE_MISC::SDOT_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX(opcode) => opcode.definition(),
            SVE_MISC::SDOT_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX(opcode) => opcode.definition(),
            SVE_MISC::SDOT_SVE_Zd_S_S_SVE_Zn_S_H_SVE_Zm_16_S_H(opcode) => opcode.definition(),
            SVE_MISC::SEL_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm(opcode) => opcode.definition(),
            SVE_MISC::SETFFR(opcode) => opcode.definition(),
            SVE_MISC::SM4EKEY_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_MISC::SM4E_SVE_Zd_SVE_Zd_SVE_Zn(opcode) => opcode.definition(),
            SVE_MISC::SMLALB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX(opcode) => opcode.definition(),
            SVE_MISC::SMLALB_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX(opcode) => opcode.definition(),
            SVE_MISC::SMLALT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX(opcode) => opcode.definition(),
            SVE_MISC::SMLALT_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX(opcode) => opcode.definition(),
            SVE_MISC::SMLSLB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX(opcode) => opcode.definition(),
            SVE_MISC::SMLSLB_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX(opcode) => opcode.definition(),
            SVE_MISC::SMLSLT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX(opcode) => opcode.definition(),
            SVE_MISC::SMLSLT_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX(opcode) => opcode.definition(),
            SVE_MISC::SMMLA_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_MISC::SMULLB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX(opcode) => opcode.definition(),
            SVE_MISC::SMULLB_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX(opcode) => opcode.definition(),
            SVE_MISC::SMULLT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX(opcode) => opcode.definition(),
            SVE_MISC::SMULLT_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX(opcode) => opcode.definition(),
            SVE_MISC::SQCVTN_SVE_Zd_SME_Znx2(opcode) => opcode.definition(),
            SVE_MISC::SQCVTUN_SVE_Zd_SME_Znx2(opcode) => opcode.definition(),
            SVE_MISC::SQDECB_Rd_Rd_SVE_PATTERN_SCALED(opcode) => opcode.definition(),
            SVE_MISC::SQDECB_Rd_SVE_PATTERN_SCALED(opcode) => opcode.definition(),
            SVE_MISC::SQDECD_Rd_Rd_SVE_PATTERN_SCALED(opcode) => opcode.definition(),
            SVE_MISC::SQDECD_Rd_SVE_PATTERN_SCALED(opcode) => opcode.definition(),
            SVE_MISC::SQDECD_SVE_Zd_SVE_PATTERN_SCALED(opcode) => opcode.definition(),
            SVE_MISC::SQDECH_Rd_Rd_SVE_PATTERN_SCALED(opcode) => opcode.definition(),
            SVE_MISC::SQDECH_Rd_SVE_PATTERN_SCALED(opcode) => opcode.definition(),
            SVE_MISC::SQDECH_SVE_Zd_SVE_PATTERN_SCALED(opcode) => opcode.definition(),
            SVE_MISC::SQDECW_Rd_Rd_SVE_PATTERN_SCALED(opcode) => opcode.definition(),
            SVE_MISC::SQDECW_Rd_SVE_PATTERN_SCALED(opcode) => opcode.definition(),
            SVE_MISC::SQDECW_SVE_Zd_SVE_PATTERN_SCALED(opcode) => opcode.definition(),
            SVE_MISC::SQDMLALB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX(opcode) => opcode.definition(),
            SVE_MISC::SQDMLALB_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX(opcode) => opcode.definition(),
            SVE_MISC::SQDMLALT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX(opcode) => opcode.definition(),
            SVE_MISC::SQDMLALT_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX(opcode) => opcode.definition(),
            SVE_MISC::SQDMLSLB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX(opcode) => opcode.definition(),
            SVE_MISC::SQDMLSLB_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX(opcode) => opcode.definition(),
            SVE_MISC::SQDMLSLT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX(opcode) => opcode.definition(),
            SVE_MISC::SQDMLSLT_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX(opcode) => opcode.definition(),
            SVE_MISC::SQDMULH_SVE_Zd_SVE_Zn_SVE_Zm3_22_INDEX(opcode) => opcode.definition(),
            SVE_MISC::SQDMULH_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX(opcode) => opcode.definition(),
            SVE_MISC::SQDMULH_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX(opcode) => opcode.definition(),
            SVE_MISC::SQDMULLB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX(opcode) => opcode.definition(),
            SVE_MISC::SQDMULLB_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX(opcode) => opcode.definition(),
            SVE_MISC::SQDMULLT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX(opcode) => opcode.definition(),
            SVE_MISC::SQDMULLT_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX(opcode) => opcode.definition(),
            SVE_MISC::SQINCB_Rd_Rd_SVE_PATTERN_SCALED(opcode) => opcode.definition(),
            SVE_MISC::SQINCB_Rd_SVE_PATTERN_SCALED(opcode) => opcode.definition(),
            SVE_MISC::SQINCD_Rd_Rd_SVE_PATTERN_SCALED(opcode) => opcode.definition(),
            SVE_MISC::SQINCD_Rd_SVE_PATTERN_SCALED(opcode) => opcode.definition(),
            SVE_MISC::SQINCD_SVE_Zd_SVE_PATTERN_SCALED(opcode) => opcode.definition(),
            SVE_MISC::SQINCH_Rd_Rd_SVE_PATTERN_SCALED(opcode) => opcode.definition(),
            SVE_MISC::SQINCH_Rd_SVE_PATTERN_SCALED(opcode) => opcode.definition(),
            SVE_MISC::SQINCH_SVE_Zd_SVE_PATTERN_SCALED(opcode) => opcode.definition(),
            SVE_MISC::SQINCW_Rd_Rd_SVE_PATTERN_SCALED(opcode) => opcode.definition(),
            SVE_MISC::SQINCW_Rd_SVE_PATTERN_SCALED(opcode) => opcode.definition(),
            SVE_MISC::SQINCW_SVE_Zd_SVE_PATTERN_SCALED(opcode) => opcode.definition(),
            SVE_MISC::SQRDCMLAH_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX_SVE_IMM_ROT2(opcode) => {
                opcode.definition()
            }
            SVE_MISC::SQRDCMLAH_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX_SVE_IMM_ROT2(opcode) => {
                opcode.definition()
            }
            SVE_MISC::SQRDMLAH_SVE_Zd_SVE_Zn_SVE_Zm3_22_INDEX(opcode) => opcode.definition(),
            SVE_MISC::SQRDMLAH_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX(opcode) => opcode.definition(),
            SVE_MISC::SQRDMLAH_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX(opcode) => opcode.definition(),
            SVE_MISC::SQRDMLSH_SVE_Zd_SVE_Zn_SVE_Zm3_22_INDEX(opcode) => opcode.definition(),
            SVE_MISC::SQRDMLSH_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX(opcode) => opcode.definition(),
            SVE_MISC::SQRDMLSH_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX(opcode) => opcode.definition(),
            SVE_MISC::SQRDMULH_SVE_Zd_SVE_Zn_SVE_Zm3_22_INDEX(opcode) => opcode.definition(),
            SVE_MISC::SQRDMULH_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX(opcode) => opcode.definition(),
            SVE_MISC::SQRDMULH_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX(opcode) => opcode.definition(),
            SVE_MISC::ST1B_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_R(opcode) => opcode.definition(),
            SVE_MISC::ST1B_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_RR(opcode) => opcode.definition(),
            SVE_MISC::ST1B_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL(opcode) => opcode.definition(),
            SVE_MISC::ST1B_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR(opcode) => opcode.definition(),
            SVE_MISC::ST1B_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL(opcode) => opcode.definition(),
            SVE_MISC::ST1B_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR(opcode) => opcode.definition(),
            SVE_MISC::ST1B_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL(opcode) => {
                opcode.definition()
            }
            SVE_MISC::ST1B_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR(opcode) => opcode.definition(),
            SVE_MISC::ST1B_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL(opcode) => {
                opcode.definition()
            }
            SVE_MISC::ST1B_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR(opcode) => opcode.definition(),
            SVE_MISC::ST1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL(opcode) => opcode.definition(),
            SVE_MISC::ST1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX(opcode) => opcode.definition(),
            SVE_MISC::ST1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ(opcode) => opcode.definition(),
            SVE_MISC::ST1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_14(opcode) => opcode.definition(),
            SVE_MISC::ST1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5(opcode) => opcode.definition(),
            SVE_MISC::ST1B_SVE_ZtxN_S_D_SVE_Pg3_SVE_ADDR_RI_S4xVL(opcode) => opcode.definition(),
            SVE_MISC::ST1B_SVE_ZtxN_S_D_SVE_Pg3_SVE_ADDR_RX(opcode) => opcode.definition(),
            SVE_MISC::ST1B_SVE_ZtxN_S_H_SVE_Pg3_SVE_ADDR_RI_S4xVL(opcode) => opcode.definition(),
            SVE_MISC::ST1B_SVE_ZtxN_S_H_SVE_Pg3_SVE_ADDR_RX(opcode) => opcode.definition(),
            SVE_MISC::ST1B_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_RI_S4xVL(opcode) => opcode.definition(),
            SVE_MISC::ST1B_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_RX(opcode) => opcode.definition(),
            SVE_MISC::ST1B_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_RZ_XTW_14(opcode) => opcode.definition(),
            SVE_MISC::ST1B_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_ZI_U5(opcode) => opcode.definition(),
            SVE_MISC::ST1D_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_R(opcode) => opcode.definition(),
            SVE_MISC::ST1D_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_RR_LSL3(opcode) => {
                opcode.definition()
            }
            SVE_MISC::ST1D_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL(opcode) => opcode.definition(),
            SVE_MISC::ST1D_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR_LSL3(opcode) => opcode.definition(),
            SVE_MISC::ST1D_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL(opcode) => opcode.definition(),
            SVE_MISC::ST1D_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR_LSL3(opcode) => opcode.definition(),
            SVE_MISC::ST1D_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL(opcode) => {
                opcode.definition()
            }
            SVE_MISC::ST1D_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL3(opcode) => {
                opcode.definition()
            }
            SVE_MISC::ST1D_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL(opcode) => {
                opcode.definition()
            }
            SVE_MISC::ST1D_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL3(opcode) => {
                opcode.definition()
            }
            SVE_MISC::ST1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL(opcode) => opcode.definition(),
            SVE_MISC::ST1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL3(opcode) => opcode.definition(),
            SVE_MISC::ST1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ(opcode) => opcode.definition(),
            SVE_MISC::ST1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL3(opcode) => opcode.definition(),
            SVE_MISC::ST1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW3_14(opcode) => opcode.definition(),
            SVE_MISC::ST1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_14(opcode) => opcode.definition(),
            SVE_MISC::ST1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x8(opcode) => opcode.definition(),
            SVE_MISC::ST1H_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_R(opcode) => opcode.definition(),
            SVE_MISC::ST1H_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_RR_LSL1(opcode) => {
                opcode.definition()
            }
            SVE_MISC::ST1H_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL(opcode) => opcode.definition(),
            SVE_MISC::ST1H_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR_LSL1(opcode) => opcode.definition(),
            SVE_MISC::ST1H_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL(opcode) => opcode.definition(),
            SVE_MISC::ST1H_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR_LSL1(opcode) => opcode.definition(),
            SVE_MISC::ST1H_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL(opcode) => {
                opcode.definition()
            }
            SVE_MISC::ST1H_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL1(opcode) => {
                opcode.definition()
            }
            SVE_MISC::ST1H_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL(opcode) => {
                opcode.definition()
            }
            SVE_MISC::ST1H_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL1(opcode) => {
                opcode.definition()
            }
            SVE_MISC::ST1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL(opcode) => opcode.definition(),
            SVE_MISC::ST1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1(opcode) => opcode.definition(),
            SVE_MISC::ST1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ(opcode) => opcode.definition(),
            SVE_MISC::ST1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL1(opcode) => opcode.definition(),
            SVE_MISC::ST1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW1_14(opcode) => opcode.definition(),
            SVE_MISC::ST1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_14(opcode) => opcode.definition(),
            SVE_MISC::ST1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x2(opcode) => opcode.definition(),
            SVE_MISC::ST1H_SVE_ZtxN_S_D_SVE_Pg3_SVE_ADDR_RI_S4xVL(opcode) => opcode.definition(),
            SVE_MISC::ST1H_SVE_ZtxN_S_D_SVE_Pg3_SVE_ADDR_RX_LSL1(opcode) => opcode.definition(),
            SVE_MISC::ST1H_SVE_ZtxN_S_H_SVE_Pg3_SVE_ADDR_RI_S4xVL(opcode) => opcode.definition(),
            SVE_MISC::ST1H_SVE_ZtxN_S_H_SVE_Pg3_SVE_ADDR_RX_LSL1(opcode) => opcode.definition(),
            SVE_MISC::ST1H_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_RZ_XTW1_14(opcode) => opcode.definition(),
            SVE_MISC::ST1H_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_RZ_XTW_14(opcode) => opcode.definition(),
            SVE_MISC::ST1H_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_ZI_U5x2(opcode) => opcode.definition(),
            SVE_MISC::ST1Q_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_R(opcode) => opcode.definition(),
            SVE_MISC::ST1Q_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_RR_LSL4(opcode) => {
                opcode.definition()
            }
            SVE_MISC::ST1Q_SVE_Zt_SVE_Pg3_SVE_ADDR_ZX(opcode) => opcode.definition(),
            SVE_MISC::ST1W_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_R(opcode) => opcode.definition(),
            SVE_MISC::ST1W_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_RR_LSL2(opcode) => {
                opcode.definition()
            }
            SVE_MISC::ST1W_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL(opcode) => opcode.definition(),
            SVE_MISC::ST1W_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR_LSL2(opcode) => opcode.definition(),
            SVE_MISC::ST1W_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL(opcode) => opcode.definition(),
            SVE_MISC::ST1W_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR_LSL2(opcode) => opcode.definition(),
            SVE_MISC::ST1W_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL(opcode) => {
                opcode.definition()
            }
            SVE_MISC::ST1W_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL2(opcode) => {
                opcode.definition()
            }
            SVE_MISC::ST1W_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL(opcode) => {
                opcode.definition()
            }
            SVE_MISC::ST1W_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL2(opcode) => {
                opcode.definition()
            }
            SVE_MISC::ST1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL(opcode) => opcode.definition(),
            SVE_MISC::ST1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2(opcode) => opcode.definition(),
            SVE_MISC::ST1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ(opcode) => opcode.definition(),
            SVE_MISC::ST1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL2(opcode) => opcode.definition(),
            SVE_MISC::ST1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW2_14(opcode) => opcode.definition(),
            SVE_MISC::ST1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_14(opcode) => opcode.definition(),
            SVE_MISC::ST1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x4(opcode) => opcode.definition(),
            SVE_MISC::ST1W_SVE_ZtxN_S_D_SVE_Pg3_SVE_ADDR_RI_S4xVL(opcode) => opcode.definition(),
            SVE_MISC::ST1W_SVE_ZtxN_S_D_SVE_Pg3_SVE_ADDR_RX_LSL2(opcode) => opcode.definition(),
            SVE_MISC::ST1W_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_RZ_XTW2_14(opcode) => opcode.definition(),
            SVE_MISC::ST1W_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_RZ_XTW_14(opcode) => opcode.definition(),
            SVE_MISC::ST1W_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_ZI_U5x4(opcode) => opcode.definition(),
            SVE_MISC::ST2B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x2xVL(opcode) => opcode.definition(),
            SVE_MISC::ST2B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX(opcode) => opcode.definition(),
            SVE_MISC::ST2D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x2xVL(opcode) => opcode.definition(),
            SVE_MISC::ST2D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL3(opcode) => opcode.definition(),
            SVE_MISC::ST2H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x2xVL(opcode) => opcode.definition(),
            SVE_MISC::ST2H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1(opcode) => opcode.definition(),
            SVE_MISC::ST2Q_SME_Zt2_SVE_Pg3_SVE_ADDR_RI_S4x2xVL(opcode) => opcode.definition(),
            SVE_MISC::ST2Q_SME_Zt2_SVE_Pg3_SVE_ADDR_RR_LSL4(opcode) => opcode.definition(),
            SVE_MISC::ST2W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x2xVL(opcode) => opcode.definition(),
            SVE_MISC::ST2W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2(opcode) => opcode.definition(),
            SVE_MISC::ST3B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x3xVL(opcode) => opcode.definition(),
            SVE_MISC::ST3B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX(opcode) => opcode.definition(),
            SVE_MISC::ST3D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x3xVL(opcode) => opcode.definition(),
            SVE_MISC::ST3D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL3(opcode) => opcode.definition(),
            SVE_MISC::ST3H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x3xVL(opcode) => opcode.definition(),
            SVE_MISC::ST3H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1(opcode) => opcode.definition(),
            SVE_MISC::ST3Q_SME_Zt3_SVE_Pg3_SVE_ADDR_RI_S4x2xVL(opcode) => opcode.definition(),
            SVE_MISC::ST3Q_SME_Zt3_SVE_Pg3_SVE_ADDR_RR_LSL4(opcode) => opcode.definition(),
            SVE_MISC::ST3W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x3xVL(opcode) => opcode.definition(),
            SVE_MISC::ST3W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2(opcode) => opcode.definition(),
            SVE_MISC::ST4B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x4xVL(opcode) => opcode.definition(),
            SVE_MISC::ST4B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX(opcode) => opcode.definition(),
            SVE_MISC::ST4D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x4xVL(opcode) => opcode.definition(),
            SVE_MISC::ST4D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL3(opcode) => opcode.definition(),
            SVE_MISC::ST4H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x4xVL(opcode) => opcode.definition(),
            SVE_MISC::ST4H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1(opcode) => opcode.definition(),
            SVE_MISC::ST4Q_SME_Zt4_SVE_Pg3_SVE_ADDR_RI_S4x2xVL(opcode) => opcode.definition(),
            SVE_MISC::ST4Q_SME_Zt4_SVE_Pg3_SVE_ADDR_RR_LSL4(opcode) => opcode.definition(),
            SVE_MISC::ST4W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x4xVL(opcode) => opcode.definition(),
            SVE_MISC::ST4W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2(opcode) => opcode.definition(),
            SVE_MISC::STNT1B_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL(opcode) => opcode.definition(),
            SVE_MISC::STNT1B_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR(opcode) => opcode.definition(),
            SVE_MISC::STNT1B_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL(opcode) => opcode.definition(),
            SVE_MISC::STNT1B_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR(opcode) => opcode.definition(),
            SVE_MISC::STNT1B_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL(opcode) => {
                opcode.definition()
            }
            SVE_MISC::STNT1B_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR(opcode) => opcode.definition(),
            SVE_MISC::STNT1B_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL(opcode) => {
                opcode.definition()
            }
            SVE_MISC::STNT1B_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR(opcode) => opcode.definition(),
            SVE_MISC::STNT1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL(opcode) => opcode.definition(),
            SVE_MISC::STNT1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX(opcode) => opcode.definition(),
            SVE_MISC::STNT1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZX(opcode) => opcode.definition(),
            SVE_MISC::STNT1B_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_ZX(opcode) => opcode.definition(),
            SVE_MISC::STNT1D_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL(opcode) => opcode.definition(),
            SVE_MISC::STNT1D_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR_LSL3(opcode) => opcode.definition(),
            SVE_MISC::STNT1D_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL(opcode) => opcode.definition(),
            SVE_MISC::STNT1D_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR_LSL3(opcode) => opcode.definition(),
            SVE_MISC::STNT1D_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL(opcode) => {
                opcode.definition()
            }
            SVE_MISC::STNT1D_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL3(opcode) => {
                opcode.definition()
            }
            SVE_MISC::STNT1D_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL(opcode) => {
                opcode.definition()
            }
            SVE_MISC::STNT1D_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL3(opcode) => {
                opcode.definition()
            }
            SVE_MISC::STNT1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL(opcode) => opcode.definition(),
            SVE_MISC::STNT1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL3(opcode) => opcode.definition(),
            SVE_MISC::STNT1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZX(opcode) => opcode.definition(),
            SVE_MISC::STNT1H_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL(opcode) => opcode.definition(),
            SVE_MISC::STNT1H_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR_LSL1(opcode) => opcode.definition(),
            SVE_MISC::STNT1H_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL(opcode) => opcode.definition(),
            SVE_MISC::STNT1H_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR_LSL1(opcode) => opcode.definition(),
            SVE_MISC::STNT1H_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL(opcode) => {
                opcode.definition()
            }
            SVE_MISC::STNT1H_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL1(opcode) => {
                opcode.definition()
            }
            SVE_MISC::STNT1H_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL(opcode) => {
                opcode.definition()
            }
            SVE_MISC::STNT1H_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL1(opcode) => {
                opcode.definition()
            }
            SVE_MISC::STNT1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL(opcode) => opcode.definition(),
            SVE_MISC::STNT1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1(opcode) => opcode.definition(),
            SVE_MISC::STNT1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZX(opcode) => opcode.definition(),
            SVE_MISC::STNT1H_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_ZX(opcode) => opcode.definition(),
            SVE_MISC::STNT1W_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL(opcode) => opcode.definition(),
            SVE_MISC::STNT1W_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR_LSL2(opcode) => opcode.definition(),
            SVE_MISC::STNT1W_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL(opcode) => opcode.definition(),
            SVE_MISC::STNT1W_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR_LSL2(opcode) => opcode.definition(),
            SVE_MISC::STNT1W_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL(opcode) => {
                opcode.definition()
            }
            SVE_MISC::STNT1W_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL2(opcode) => {
                opcode.definition()
            }
            SVE_MISC::STNT1W_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL(opcode) => {
                opcode.definition()
            }
            SVE_MISC::STNT1W_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL2(opcode) => {
                opcode.definition()
            }
            SVE_MISC::STNT1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL(opcode) => opcode.definition(),
            SVE_MISC::STNT1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2(opcode) => opcode.definition(),
            SVE_MISC::STNT1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZX(opcode) => opcode.definition(),
            SVE_MISC::STNT1W_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_ZX(opcode) => opcode.definition(),
            SVE_MISC::STR_SVE_PNt_SVE_ADDR_RI_S9xVL(opcode) => opcode.definition(),
            SVE_MISC::STR_SVE_Pt_SVE_ADDR_RI_S9xVL(opcode) => opcode.definition(),
            SVE_MISC::STR_SVE_Zt_SVE_ADDR_RI_S9xVL(opcode) => opcode.definition(),
            SVE_MISC::SUDOT_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX(opcode) => opcode.definition(),
            SVE_MISC::SXTW_SVE_Zd_SVE_Pg3_SVE_Zn(opcode) => opcode.definition(),
            SVE_MISC::TRN1_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_MISC::TRN2_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_MISC::UCVTF_SME_Zdnx2_SME_Znx2(opcode) => opcode.definition(),
            SVE_MISC::UCVTF_SME_Zdnx4_SME_Znx4(opcode) => opcode.definition(),
            SVE_MISC::UCVTF_SVE_Zd_SVE_Pg3_SVE_Zn(opcode) => opcode.definition(),
            SVE_MISC::UCVTF_SVE_Zd_S_D_SVE_Pg3_P_M_SVE_Zn_S_D(opcode) => opcode.definition(),
            SVE_MISC::UCVTF_SVE_Zd_S_H_SVE_Pg3_P_M_SVE_Zn_S_D(opcode) => opcode.definition(),
            SVE_MISC::UCVTF_SVE_Zd_S_H_SVE_Pg3_P_M_SVE_Zn_S_H(opcode) => opcode.definition(),
            SVE_MISC::UCVTF_SVE_Zd_S_H_SVE_Pg3_P_M_SVE_Zn_S_S(opcode) => opcode.definition(),
            SVE_MISC::UCVTF_SVE_Zd_S_S_SVE_Pg3_P_M_SVE_Zn_S_D(opcode) => opcode.definition(),
            SVE_MISC::UCVTF_SVE_Zd_S_S_SVE_Pg3_P_M_SVE_Zn_S_S(opcode) => opcode.definition(),
            SVE_MISC::UDOT_SVE_Zd_SVE_Zn_SVE_Zm3_19_INDEX(opcode) => opcode.definition(),
            SVE_MISC::UDOT_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX(opcode) => opcode.definition(),
            SVE_MISC::UDOT_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX(opcode) => opcode.definition(),
            SVE_MISC::UDOT_SVE_Zd_S_S_SVE_Zn_S_H_SVE_Zm_16_S_H(opcode) => opcode.definition(),
            SVE_MISC::UMLALB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX(opcode) => opcode.definition(),
            SVE_MISC::UMLALB_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX(opcode) => opcode.definition(),
            SVE_MISC::UMLALT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX(opcode) => opcode.definition(),
            SVE_MISC::UMLALT_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX(opcode) => opcode.definition(),
            SVE_MISC::UMLSLB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX(opcode) => opcode.definition(),
            SVE_MISC::UMLSLB_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX(opcode) => opcode.definition(),
            SVE_MISC::UMLSLT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX(opcode) => opcode.definition(),
            SVE_MISC::UMLSLT_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX(opcode) => opcode.definition(),
            SVE_MISC::UMMLA_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_MISC::UMULLB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX(opcode) => opcode.definition(),
            SVE_MISC::UMULLB_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX(opcode) => opcode.definition(),
            SVE_MISC::UMULLT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX(opcode) => opcode.definition(),
            SVE_MISC::UMULLT_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX(opcode) => opcode.definition(),
            SVE_MISC::UQCVTN_SVE_Zd_SME_Znx2(opcode) => opcode.definition(),
            SVE_MISC::UQDECB_Rd_SVE_PATTERN_SCALED(opcode) => opcode.definition(),
            SVE_MISC::UQDECB_Rd_X_SVE_PATTERN_SCALED(opcode) => opcode.definition(),
            SVE_MISC::UQDECD_Rd_SVE_PATTERN_SCALED(opcode) => opcode.definition(),
            SVE_MISC::UQDECD_Rd_X_SVE_PATTERN_SCALED(opcode) => opcode.definition(),
            SVE_MISC::UQDECD_SVE_Zd_SVE_PATTERN_SCALED(opcode) => opcode.definition(),
            SVE_MISC::UQDECH_Rd_SVE_PATTERN_SCALED(opcode) => opcode.definition(),
            SVE_MISC::UQDECH_Rd_X_SVE_PATTERN_SCALED(opcode) => opcode.definition(),
            SVE_MISC::UQDECH_SVE_Zd_SVE_PATTERN_SCALED(opcode) => opcode.definition(),
            SVE_MISC::UQDECW_Rd_SVE_PATTERN_SCALED(opcode) => opcode.definition(),
            SVE_MISC::UQDECW_Rd_X_SVE_PATTERN_SCALED(opcode) => opcode.definition(),
            SVE_MISC::UQDECW_SVE_Zd_SVE_PATTERN_SCALED(opcode) => opcode.definition(),
            SVE_MISC::UQINCB_Rd_SVE_PATTERN_SCALED(opcode) => opcode.definition(),
            SVE_MISC::UQINCB_Rd_X_SVE_PATTERN_SCALED(opcode) => opcode.definition(),
            SVE_MISC::UQINCD_Rd_SVE_PATTERN_SCALED(opcode) => opcode.definition(),
            SVE_MISC::UQINCD_Rd_X_SVE_PATTERN_SCALED(opcode) => opcode.definition(),
            SVE_MISC::UQINCD_SVE_Zd_SVE_PATTERN_SCALED(opcode) => opcode.definition(),
            SVE_MISC::UQINCH_Rd_SVE_PATTERN_SCALED(opcode) => opcode.definition(),
            SVE_MISC::UQINCH_Rd_X_SVE_PATTERN_SCALED(opcode) => opcode.definition(),
            SVE_MISC::UQINCH_SVE_Zd_SVE_PATTERN_SCALED(opcode) => opcode.definition(),
            SVE_MISC::UQINCW_Rd_SVE_PATTERN_SCALED(opcode) => opcode.definition(),
            SVE_MISC::UQINCW_Rd_X_SVE_PATTERN_SCALED(opcode) => opcode.definition(),
            SVE_MISC::UQINCW_SVE_Zd_SVE_PATTERN_SCALED(opcode) => opcode.definition(),
            SVE_MISC::URECPE_SVE_Zd_SVE_Pg3_SVE_Zn(opcode) => opcode.definition(),
            SVE_MISC::URSQRTE_SVE_Zd_SVE_Pg3_SVE_Zn(opcode) => opcode.definition(),
            SVE_MISC::USDOT_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX(opcode) => opcode.definition(),
            SVE_MISC::USDOT_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_MISC::USMMLA_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_MISC::UXTW_SVE_Zd_SVE_Pg3_SVE_Zn(opcode) => opcode.definition(),
            SVE_MISC::UZP1_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_MISC::UZP2_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_MISC::WRFFR_SVE_Pn(opcode) => opcode.definition(),
            SVE_MISC::ZIP1_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
            SVE_MISC::ZIP2_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.definition(),
        }
    }
    fn bits(&self) -> u32 {
        match self {
            SVE_MISC::ADDPL_Rd_SP_SVE_Rn_SP_SVE_SIMM6(opcode) => opcode.bits(),
            SVE_MISC::ADDVL_Rd_SP_SVE_Rn_SP_SVE_SIMM6(opcode) => opcode.bits(),
            SVE_MISC::ADR_SVE_Zd_SVE_ADDR_ZZ_SXTW(opcode) => opcode.bits(),
            SVE_MISC::ADR_SVE_Zd_SVE_ADDR_ZZ_UXTW(opcode) => opcode.bits(),
            SVE_MISC::AESD_SVE_Zd_SVE_Zd_SVE_Zn(opcode) => opcode.bits(),
            SVE_MISC::AESE_SVE_Zd_SVE_Zd_SVE_Zn(opcode) => opcode.bits(),
            SVE_MISC::AESIMC_SVE_Zd_SVE_Zd(opcode) => opcode.bits(),
            SVE_MISC::AESMC_SVE_Zd_SVE_Zd(opcode) => opcode.bits(),
            SVE_MISC::ANDS_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm(opcode) => opcode.bits(),
            SVE_MISC::AND_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm(opcode) => opcode.bits(),
            SVE_MISC::AND_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_MISC::BCAX_SVE_Zd_SVE_Zd_SVE_Zm_16_SVE_Zn(opcode) => opcode.bits(),
            SVE_MISC::BFADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(opcode) => opcode.bits(),
            SVE_MISC::BFADD_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_MISC::BFCLAMP_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_MISC::BFCVTNT_SVE_Zd_SVE_Pg3_SVE_Zn(opcode) => opcode.bits(),
            SVE_MISC::BFCVT_SVE_Zd_SVE_Pg3_SVE_Zn(opcode) => opcode.bits(),
            SVE_MISC::BFDOT_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX(opcode) => opcode.bits(),
            SVE_MISC::BFDOT_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_MISC::BFMAXNM_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(opcode) => opcode.bits(),
            SVE_MISC::BFMAX_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(opcode) => opcode.bits(),
            SVE_MISC::BFMINNM_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(opcode) => opcode.bits(),
            SVE_MISC::BFMIN_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(opcode) => opcode.bits(),
            SVE_MISC::BFMLALB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX(opcode) => opcode.bits(),
            SVE_MISC::BFMLALB_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_MISC::BFMLALT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX(opcode) => opcode.bits(),
            SVE_MISC::BFMLALT_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_MISC::BFMLA_SVE_Zd_SVE_Pg3_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_MISC::BFMLA_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX(opcode) => opcode.bits(),
            SVE_MISC::BFMLSLB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX(opcode) => opcode.bits(),
            SVE_MISC::BFMLSLB_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_MISC::BFMLSLT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX(opcode) => opcode.bits(),
            SVE_MISC::BFMLSLT_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_MISC::BFMLS_SVE_Zd_SVE_Pg3_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_MISC::BFMLS_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX(opcode) => opcode.bits(),
            SVE_MISC::BFMMLA_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_MISC::BFMUL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(opcode) => opcode.bits(),
            SVE_MISC::BFMUL_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX(opcode) => opcode.bits(),
            SVE_MISC::BFMUL_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_MISC::BFSUB_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5(opcode) => opcode.bits(),
            SVE_MISC::BFSUB_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_MISC::BICS_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm(opcode) => opcode.bits(),
            SVE_MISC::BIC_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm(opcode) => opcode.bits(),
            SVE_MISC::BIC_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_MISC::BRKAS_SVE_Pd_SVE_Pg4_10_SVE_Pn(opcode) => opcode.bits(),
            SVE_MISC::BRKBS_SVE_Pd_SVE_Pg4_10_SVE_Pn(opcode) => opcode.bits(),
            SVE_MISC::BRKNS_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pd(opcode) => opcode.bits(),
            SVE_MISC::BRKN_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pd(opcode) => opcode.bits(),
            SVE_MISC::BRKPAS_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm(opcode) => opcode.bits(),
            SVE_MISC::BRKPA_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm(opcode) => opcode.bits(),
            SVE_MISC::BRKPBS_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm(opcode) => opcode.bits(),
            SVE_MISC::BRKPB_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm(opcode) => opcode.bits(),
            SVE_MISC::BSL1N_SVE_Zd_SVE_Zd_SVE_Zm_16_SVE_Zn(opcode) => opcode.bits(),
            SVE_MISC::BSL2N_SVE_Zd_SVE_Zd_SVE_Zm_16_SVE_Zn(opcode) => opcode.bits(),
            SVE_MISC::BSL_SVE_Zd_SVE_Zd_SVE_Zm_16_SVE_Zn(opcode) => opcode.bits(),
            SVE_MISC::CDOT_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX_SVE_IMM_ROT2(opcode) => opcode.bits(),
            SVE_MISC::CDOT_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX_SVE_IMM_ROT2(opcode) => opcode.bits(),
            SVE_MISC::CMLA_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX_SVE_IMM_ROT2(opcode) => opcode.bits(),
            SVE_MISC::CMLA_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX_SVE_IMM_ROT2(opcode) => opcode.bits(),
            SVE_MISC::CNTB_Rd_SVE_PATTERN_SCALED(opcode) => opcode.bits(),
            SVE_MISC::CNTD_Rd_SVE_PATTERN_SCALED(opcode) => opcode.bits(),
            SVE_MISC::CNTH_Rd_SVE_PATTERN_SCALED(opcode) => opcode.bits(),
            SVE_MISC::CNTW_Rd_SVE_PATTERN_SCALED(opcode) => opcode.bits(),
            SVE_MISC::DECB_Rd_SVE_PATTERN_SCALED(opcode) => opcode.bits(),
            SVE_MISC::DECD_Rd_SVE_PATTERN_SCALED(opcode) => opcode.bits(),
            SVE_MISC::DECD_SVE_Zd_SVE_PATTERN_SCALED(opcode) => opcode.bits(),
            SVE_MISC::DECH_Rd_SVE_PATTERN_SCALED(opcode) => opcode.bits(),
            SVE_MISC::DECH_SVE_Zd_SVE_PATTERN_SCALED(opcode) => opcode.bits(),
            SVE_MISC::DECW_Rd_SVE_PATTERN_SCALED(opcode) => opcode.bits(),
            SVE_MISC::DECW_SVE_Zd_SVE_PATTERN_SCALED(opcode) => opcode.bits(),
            SVE_MISC::EOR3_SVE_Zd_SVE_Zd_SVE_Zm_16_SVE_Zn(opcode) => opcode.bits(),
            SVE_MISC::EORS_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm(opcode) => opcode.bits(),
            SVE_MISC::EOR_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm(opcode) => opcode.bits(),
            SVE_MISC::EOR_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_MISC::EXTQ_SVE_Zd_SVE_Zd_SVE_Zm_imm4(opcode) => opcode.bits(),
            SVE_MISC::EXT_SVE_Zd_SVE_Zd_SVE_Zm_5_SVE_UIMM8_53(opcode) => opcode.bits(),
            SVE_MISC::EXT_SVE_Zd_SVE_ZnxN_SVE_UIMM8_53(opcode) => opcode.bits(),
            SVE_MISC::FCMLA_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX_SVE_IMM_ROT2(opcode) => opcode.bits(),
            SVE_MISC::FCMLA_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX_SVE_IMM_ROT2(opcode) => opcode.bits(),
            SVE_MISC::FCVTLT_SVE_Zd_SVE_Pg3_SVE_Zn(opcode) => opcode.bits(),
            SVE_MISC::FCVTLT_SVE_Zd_S_D_SVE_Pg3_P_M_SVE_Zn_S_S(opcode) => opcode.bits(),
            SVE_MISC::FCVTNT_SVE_Zd_SVE_Pg3_SVE_Zn(opcode) => opcode.bits(),
            SVE_MISC::FCVTNT_SVE_Zd_S_S_SVE_Pg3_P_M_SVE_Zn_S_D(opcode) => opcode.bits(),
            SVE_MISC::FCVTN_SVE_Zd_SME_Znx2(opcode) => opcode.bits(),
            SVE_MISC::FCVTXNT_SVE_Zd_SVE_Pg3_SVE_Zn(opcode) => opcode.bits(),
            SVE_MISC::FCVTX_SVE_Zd_SVE_Pg3_SVE_Zn(opcode) => opcode.bits(),
            SVE_MISC::FCVTZS_SME_Zdnx2_SME_Znx2(opcode) => opcode.bits(),
            SVE_MISC::FCVTZS_SME_Zdnx4_SME_Znx4(opcode) => opcode.bits(),
            SVE_MISC::FCVTZS_SVE_Zd_SVE_Pg3_SVE_Zn(opcode) => opcode.bits(),
            SVE_MISC::FCVTZS_SVE_Zd_S_D_SVE_Pg3_P_M_SVE_Zn_S_D(opcode) => opcode.bits(),
            SVE_MISC::FCVTZS_SVE_Zd_S_D_SVE_Pg3_P_M_SVE_Zn_S_H(opcode) => opcode.bits(),
            SVE_MISC::FCVTZS_SVE_Zd_S_D_SVE_Pg3_P_M_SVE_Zn_S_S(opcode) => opcode.bits(),
            SVE_MISC::FCVTZS_SVE_Zd_S_H_SVE_Pg3_P_M_SVE_Zn_S_H(opcode) => opcode.bits(),
            SVE_MISC::FCVTZS_SVE_Zd_S_S_SVE_Pg3_P_M_SVE_Zn_S_D(opcode) => opcode.bits(),
            SVE_MISC::FCVTZS_SVE_Zd_S_S_SVE_Pg3_P_M_SVE_Zn_S_H(opcode) => opcode.bits(),
            SVE_MISC::FCVTZU_SME_Zdnx2_SME_Znx2(opcode) => opcode.bits(),
            SVE_MISC::FCVTZU_SME_Zdnx4_SME_Znx4(opcode) => opcode.bits(),
            SVE_MISC::FCVTZU_SVE_Zd_SVE_Pg3_SVE_Zn(opcode) => opcode.bits(),
            SVE_MISC::FCVTZU_SVE_Zd_S_D_SVE_Pg3_P_M_SVE_Zn_S_D(opcode) => opcode.bits(),
            SVE_MISC::FCVTZU_SVE_Zd_S_D_SVE_Pg3_P_M_SVE_Zn_S_H(opcode) => opcode.bits(),
            SVE_MISC::FCVTZU_SVE_Zd_S_D_SVE_Pg3_P_M_SVE_Zn_S_S(opcode) => opcode.bits(),
            SVE_MISC::FCVTZU_SVE_Zd_S_H_SVE_Pg3_P_M_SVE_Zn_S_H(opcode) => opcode.bits(),
            SVE_MISC::FCVTZU_SVE_Zd_S_S_SVE_Pg3_P_M_SVE_Zn_S_H(opcode) => opcode.bits(),
            SVE_MISC::FCVTZU_SVE_Zd_S_S_SVE_Pg3_P_M_SVE_Zn_S_S(opcode) => opcode.bits(),
            SVE_MISC::FCVT_SVE_Zd_SME_Znx2(opcode) => opcode.bits(),
            SVE_MISC::FCVT_SVE_Zd_SVE_Pg3_SVE_Zn(opcode) => opcode.bits(),
            SVE_MISC::FCVT_SVE_Zd_S_D_SVE_Pg3_P_M_SVE_Zn_S_H(opcode) => opcode.bits(),
            SVE_MISC::FCVT_SVE_Zd_S_D_SVE_Pg3_P_M_SVE_Zn_S_S(opcode) => opcode.bits(),
            SVE_MISC::FCVT_SVE_Zd_S_H_SVE_Pg3_P_M_SVE_Zn_S_D(opcode) => opcode.bits(),
            SVE_MISC::FCVT_SVE_Zd_S_S_SVE_Pg3_P_M_SVE_Zn_S_D(opcode) => opcode.bits(),
            SVE_MISC::FCVT_SVE_Zd_S_S_SVE_Pg3_P_M_SVE_Zn_S_H(opcode) => opcode.bits(),
            SVE_MISC::FDOT_SVE_Zd_SVE_Zn_SVE_Zm3_19_INDEX(opcode) => opcode.bits(),
            SVE_MISC::FDOT_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_MISC::FMLALB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX(opcode) => opcode.bits(),
            SVE_MISC::FMLALB_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_MISC::FMLALT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX(opcode) => opcode.bits(),
            SVE_MISC::FMLALT_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_MISC::FMLA_SVE_Zd_SVE_Zn_SVE_Zm3_22_INDEX(opcode) => opcode.bits(),
            SVE_MISC::FMLA_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX(opcode) => opcode.bits(),
            SVE_MISC::FMLA_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX(opcode) => opcode.bits(),
            SVE_MISC::FMLSLB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX(opcode) => opcode.bits(),
            SVE_MISC::FMLSLB_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_MISC::FMLSLT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX(opcode) => opcode.bits(),
            SVE_MISC::FMLSLT_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_MISC::FMLS_SVE_Zd_SVE_Zn_SVE_Zm3_22_INDEX(opcode) => opcode.bits(),
            SVE_MISC::FMLS_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX(opcode) => opcode.bits(),
            SVE_MISC::FMLS_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX(opcode) => opcode.bits(),
            SVE_MISC::FMMLA_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_MISC::FMMLA_SVE_Zd_S_D_SVE_Zn_S_D_SVE_Zm_16_S_D(opcode) => opcode.bits(),
            SVE_MISC::FMUL_SVE_Zd_SVE_Zn_SVE_Zm3_22_INDEX(opcode) => opcode.bits(),
            SVE_MISC::FMUL_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX(opcode) => opcode.bits(),
            SVE_MISC::FMUL_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX(opcode) => opcode.bits(),
            SVE_MISC::FRINTA_SME_Zdnx2_SME_Znx2(opcode) => opcode.bits(),
            SVE_MISC::FRINTA_SME_Zdnx4_SME_Znx4(opcode) => opcode.bits(),
            SVE_MISC::FRINTM_SME_Zdnx2_SME_Znx2(opcode) => opcode.bits(),
            SVE_MISC::FRINTM_SME_Zdnx4_SME_Znx4(opcode) => opcode.bits(),
            SVE_MISC::FRINTN_SME_Zdnx2_SME_Znx2(opcode) => opcode.bits(),
            SVE_MISC::FRINTN_SME_Zdnx4_SME_Znx4(opcode) => opcode.bits(),
            SVE_MISC::FRINTP_SME_Zdnx2_SME_Znx2(opcode) => opcode.bits(),
            SVE_MISC::FRINTP_SME_Zdnx4_SME_Znx4(opcode) => opcode.bits(),
            SVE_MISC::HISTSEG_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_MISC::INCB_Rd_SVE_PATTERN_SCALED(opcode) => opcode.bits(),
            SVE_MISC::INCD_Rd_SVE_PATTERN_SCALED(opcode) => opcode.bits(),
            SVE_MISC::INCD_SVE_Zd_SVE_PATTERN_SCALED(opcode) => opcode.bits(),
            SVE_MISC::INCH_Rd_SVE_PATTERN_SCALED(opcode) => opcode.bits(),
            SVE_MISC::INCH_SVE_Zd_SVE_PATTERN_SCALED(opcode) => opcode.bits(),
            SVE_MISC::INCW_Rd_SVE_PATTERN_SCALED(opcode) => opcode.bits(),
            SVE_MISC::INCW_SVE_Zd_SVE_PATTERN_SCALED(opcode) => opcode.bits(),
            SVE_MISC::LD1B_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_R(opcode) => opcode.bits(),
            SVE_MISC::LD1B_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_RR(opcode) => opcode.bits(),
            SVE_MISC::LD1B_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL(opcode) => opcode.bits(),
            SVE_MISC::LD1B_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR(opcode) => opcode.bits(),
            SVE_MISC::LD1B_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL(opcode) => opcode.bits(),
            SVE_MISC::LD1B_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR(opcode) => opcode.bits(),
            SVE_MISC::LD1B_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL(opcode) => opcode.bits(),
            SVE_MISC::LD1B_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR(opcode) => opcode.bits(),
            SVE_MISC::LD1B_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL(opcode) => opcode.bits(),
            SVE_MISC::LD1B_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR(opcode) => opcode.bits(),
            SVE_MISC::LD1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL(opcode) => opcode.bits(),
            SVE_MISC::LD1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX(opcode) => opcode.bits(),
            SVE_MISC::LD1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ(opcode) => opcode.bits(),
            SVE_MISC::LD1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22(opcode) => opcode.bits(),
            SVE_MISC::LD1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5(opcode) => opcode.bits(),
            SVE_MISC::LD1B_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL(opcode) => opcode.bits(),
            SVE_MISC::LD1B_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RX(opcode) => opcode.bits(),
            SVE_MISC::LD1B_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW_22_S_D(opcode) => opcode.bits(),
            SVE_MISC::LD1B_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_ZI_U5_S_D(opcode) => opcode.bits(),
            SVE_MISC::LD1B_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL(opcode) => opcode.bits(),
            SVE_MISC::LD1B_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RX(opcode) => opcode.bits(),
            SVE_MISC::LD1B_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL(opcode) => opcode.bits(),
            SVE_MISC::LD1B_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RX(opcode) => opcode.bits(),
            SVE_MISC::LD1D_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_R(opcode) => opcode.bits(),
            SVE_MISC::LD1D_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_RR_LSL3(opcode) => opcode.bits(),
            SVE_MISC::LD1D_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL(opcode) => opcode.bits(),
            SVE_MISC::LD1D_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR_LSL3(opcode) => opcode.bits(),
            SVE_MISC::LD1D_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL(opcode) => opcode.bits(),
            SVE_MISC::LD1D_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR_LSL3(opcode) => opcode.bits(),
            SVE_MISC::LD1D_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL(opcode) => opcode.bits(),
            SVE_MISC::LD1D_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL3(opcode) => opcode.bits(),
            SVE_MISC::LD1D_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL(opcode) => opcode.bits(),
            SVE_MISC::LD1D_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL3(opcode) => opcode.bits(),
            SVE_MISC::LD1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL(opcode) => opcode.bits(),
            SVE_MISC::LD1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL3(opcode) => opcode.bits(),
            SVE_MISC::LD1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ(opcode) => opcode.bits(),
            SVE_MISC::LD1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL3(opcode) => opcode.bits(),
            SVE_MISC::LD1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW3_22(opcode) => opcode.bits(),
            SVE_MISC::LD1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22(opcode) => opcode.bits(),
            SVE_MISC::LD1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x8(opcode) => opcode.bits(),
            SVE_MISC::LD1H_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_R(opcode) => opcode.bits(),
            SVE_MISC::LD1H_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_RR_LSL1(opcode) => opcode.bits(),
            SVE_MISC::LD1H_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL(opcode) => opcode.bits(),
            SVE_MISC::LD1H_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR_LSL1(opcode) => opcode.bits(),
            SVE_MISC::LD1H_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL(opcode) => opcode.bits(),
            SVE_MISC::LD1H_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR_LSL1(opcode) => opcode.bits(),
            SVE_MISC::LD1H_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL(opcode) => opcode.bits(),
            SVE_MISC::LD1H_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL1(opcode) => opcode.bits(),
            SVE_MISC::LD1H_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL(opcode) => opcode.bits(),
            SVE_MISC::LD1H_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL1(opcode) => opcode.bits(),
            SVE_MISC::LD1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL(opcode) => opcode.bits(),
            SVE_MISC::LD1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1(opcode) => opcode.bits(),
            SVE_MISC::LD1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ(opcode) => opcode.bits(),
            SVE_MISC::LD1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL1(opcode) => opcode.bits(),
            SVE_MISC::LD1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW1_22(opcode) => opcode.bits(),
            SVE_MISC::LD1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22(opcode) => opcode.bits(),
            SVE_MISC::LD1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x2(opcode) => opcode.bits(),
            SVE_MISC::LD1H_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL(opcode) => opcode.bits(),
            SVE_MISC::LD1H_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RX_LSL1(opcode) => opcode.bits(),
            SVE_MISC::LD1H_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW1_22_S_D(opcode) => {
                opcode.bits()
            }
            SVE_MISC::LD1H_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW_22_S_D(opcode) => opcode.bits(),
            SVE_MISC::LD1H_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_ZI_U5x2_S_D(opcode) => opcode.bits(),
            SVE_MISC::LD1H_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL(opcode) => opcode.bits(),
            SVE_MISC::LD1H_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RX_LSL1(opcode) => opcode.bits(),
            SVE_MISC::LD1Q_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_R(opcode) => opcode.bits(),
            SVE_MISC::LD1Q_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_RR_LSL4(opcode) => opcode.bits(),
            SVE_MISC::LD1Q_SVE_Zt_SVE_Pg3_SVE_ADDR_ZX(opcode) => opcode.bits(),
            SVE_MISC::LD1RB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_U6(opcode) => opcode.bits(),
            SVE_MISC::LD1RB_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RI_U6(opcode) => opcode.bits(),
            SVE_MISC::LD1RB_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RI_U6(opcode) => opcode.bits(),
            SVE_MISC::LD1RB_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RI_U6(opcode) => opcode.bits(),
            SVE_MISC::LD1RD_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_U6x8(opcode) => opcode.bits(),
            SVE_MISC::LD1RH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_U6x2(opcode) => opcode.bits(),
            SVE_MISC::LD1RH_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RI_U6x2(opcode) => opcode.bits(),
            SVE_MISC::LD1RH_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RI_U6x2(opcode) => opcode.bits(),
            SVE_MISC::LD1ROB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x32(opcode) => opcode.bits(),
            SVE_MISC::LD1ROB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX(opcode) => opcode.bits(),
            SVE_MISC::LD1ROD_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x32(opcode) => opcode.bits(),
            SVE_MISC::LD1ROD_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL3(opcode) => opcode.bits(),
            SVE_MISC::LD1ROH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x32(opcode) => opcode.bits(),
            SVE_MISC::LD1ROH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1(opcode) => opcode.bits(),
            SVE_MISC::LD1ROW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x32(opcode) => opcode.bits(),
            SVE_MISC::LD1ROW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2(opcode) => opcode.bits(),
            SVE_MISC::LD1RQB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x16(opcode) => opcode.bits(),
            SVE_MISC::LD1RQB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX(opcode) => opcode.bits(),
            SVE_MISC::LD1RQD_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x16(opcode) => opcode.bits(),
            SVE_MISC::LD1RQD_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL3(opcode) => opcode.bits(),
            SVE_MISC::LD1RQH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x16(opcode) => opcode.bits(),
            SVE_MISC::LD1RQH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1(opcode) => opcode.bits(),
            SVE_MISC::LD1RQW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x16(opcode) => opcode.bits(),
            SVE_MISC::LD1RQW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2(opcode) => opcode.bits(),
            SVE_MISC::LD1RSB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_U6(opcode) => opcode.bits(),
            SVE_MISC::LD1RSB_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RI_U6(opcode) => opcode.bits(),
            SVE_MISC::LD1RSB_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RI_U6(opcode) => opcode.bits(),
            SVE_MISC::LD1RSH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_U6x2(opcode) => opcode.bits(),
            SVE_MISC::LD1RSH_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RI_U6x2(opcode) => opcode.bits(),
            SVE_MISC::LD1RSW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_U6x4(opcode) => opcode.bits(),
            SVE_MISC::LD1RW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_U6x4(opcode) => opcode.bits(),
            SVE_MISC::LD1RW_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RI_U6x4(opcode) => opcode.bits(),
            SVE_MISC::LD1SB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL(opcode) => opcode.bits(),
            SVE_MISC::LD1SB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX(opcode) => opcode.bits(),
            SVE_MISC::LD1SB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ(opcode) => opcode.bits(),
            SVE_MISC::LD1SB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22(opcode) => opcode.bits(),
            SVE_MISC::LD1SB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5(opcode) => opcode.bits(),
            SVE_MISC::LD1SB_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW_22_S_D(opcode) => {
                opcode.bits()
            }
            SVE_MISC::LD1SB_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_ZI_U5_S_D(opcode) => opcode.bits(),
            SVE_MISC::LD1SB_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL(opcode) => opcode.bits(),
            SVE_MISC::LD1SB_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RX(opcode) => opcode.bits(),
            SVE_MISC::LD1SB_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL(opcode) => opcode.bits(),
            SVE_MISC::LD1SB_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RX(opcode) => opcode.bits(),
            SVE_MISC::LD1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL(opcode) => opcode.bits(),
            SVE_MISC::LD1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1(opcode) => opcode.bits(),
            SVE_MISC::LD1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ(opcode) => opcode.bits(),
            SVE_MISC::LD1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL1(opcode) => opcode.bits(),
            SVE_MISC::LD1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW1_22(opcode) => opcode.bits(),
            SVE_MISC::LD1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22(opcode) => opcode.bits(),
            SVE_MISC::LD1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x2(opcode) => opcode.bits(),
            SVE_MISC::LD1SH_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW1_22_S_D(opcode) => {
                opcode.bits()
            }
            SVE_MISC::LD1SH_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW_22_S_D(opcode) => {
                opcode.bits()
            }
            SVE_MISC::LD1SH_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_ZI_U5x2_S_D(opcode) => opcode.bits(),
            SVE_MISC::LD1SH_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL(opcode) => opcode.bits(),
            SVE_MISC::LD1SH_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RX_LSL1(opcode) => opcode.bits(),
            SVE_MISC::LD1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL(opcode) => opcode.bits(),
            SVE_MISC::LD1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2(opcode) => opcode.bits(),
            SVE_MISC::LD1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ(opcode) => opcode.bits(),
            SVE_MISC::LD1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL2(opcode) => opcode.bits(),
            SVE_MISC::LD1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW2_22(opcode) => opcode.bits(),
            SVE_MISC::LD1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22(opcode) => opcode.bits(),
            SVE_MISC::LD1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x4(opcode) => opcode.bits(),
            SVE_MISC::LD1W_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_R(opcode) => opcode.bits(),
            SVE_MISC::LD1W_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_RR_LSL2(opcode) => opcode.bits(),
            SVE_MISC::LD1W_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL(opcode) => opcode.bits(),
            SVE_MISC::LD1W_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR_LSL2(opcode) => opcode.bits(),
            SVE_MISC::LD1W_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL(opcode) => opcode.bits(),
            SVE_MISC::LD1W_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR_LSL2(opcode) => opcode.bits(),
            SVE_MISC::LD1W_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL(opcode) => opcode.bits(),
            SVE_MISC::LD1W_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL2(opcode) => opcode.bits(),
            SVE_MISC::LD1W_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL(opcode) => opcode.bits(),
            SVE_MISC::LD1W_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL2(opcode) => opcode.bits(),
            SVE_MISC::LD1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL(opcode) => opcode.bits(),
            SVE_MISC::LD1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2(opcode) => opcode.bits(),
            SVE_MISC::LD1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ(opcode) => opcode.bits(),
            SVE_MISC::LD1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL2(opcode) => opcode.bits(),
            SVE_MISC::LD1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW2_22(opcode) => opcode.bits(),
            SVE_MISC::LD1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22(opcode) => opcode.bits(),
            SVE_MISC::LD1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x4(opcode) => opcode.bits(),
            SVE_MISC::LD1W_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL(opcode) => opcode.bits(),
            SVE_MISC::LD1W_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RX_LSL2(opcode) => opcode.bits(),
            SVE_MISC::LD1W_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW2_22_S_D(opcode) => {
                opcode.bits()
            }
            SVE_MISC::LD1W_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW_22_S_D(opcode) => opcode.bits(),
            SVE_MISC::LD1W_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_ZI_U5x4_S_D(opcode) => opcode.bits(),
            SVE_MISC::LD2B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x2xVL(opcode) => opcode.bits(),
            SVE_MISC::LD2B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX(opcode) => opcode.bits(),
            SVE_MISC::LD2D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x2xVL(opcode) => opcode.bits(),
            SVE_MISC::LD2D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL3(opcode) => opcode.bits(),
            SVE_MISC::LD2H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x2xVL(opcode) => opcode.bits(),
            SVE_MISC::LD2H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1(opcode) => opcode.bits(),
            SVE_MISC::LD2Q_SME_Zt2_SVE_Pg3_SVE_ADDR_RI_S4x2xVL(opcode) => opcode.bits(),
            SVE_MISC::LD2Q_SME_Zt2_SVE_Pg3_SVE_ADDR_RR_LSL4(opcode) => opcode.bits(),
            SVE_MISC::LD2W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x2xVL(opcode) => opcode.bits(),
            SVE_MISC::LD2W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2(opcode) => opcode.bits(),
            SVE_MISC::LD3B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x3xVL(opcode) => opcode.bits(),
            SVE_MISC::LD3B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX(opcode) => opcode.bits(),
            SVE_MISC::LD3D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x3xVL(opcode) => opcode.bits(),
            SVE_MISC::LD3D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL3(opcode) => opcode.bits(),
            SVE_MISC::LD3H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x3xVL(opcode) => opcode.bits(),
            SVE_MISC::LD3H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1(opcode) => opcode.bits(),
            SVE_MISC::LD3Q_SME_Zt3_SVE_Pg3_SVE_ADDR_RI_S4x2xVL(opcode) => opcode.bits(),
            SVE_MISC::LD3Q_SME_Zt3_SVE_Pg3_SVE_ADDR_RR_LSL4(opcode) => opcode.bits(),
            SVE_MISC::LD3W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x3xVL(opcode) => opcode.bits(),
            SVE_MISC::LD3W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2(opcode) => opcode.bits(),
            SVE_MISC::LD4B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x4xVL(opcode) => opcode.bits(),
            SVE_MISC::LD4B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX(opcode) => opcode.bits(),
            SVE_MISC::LD4D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x4xVL(opcode) => opcode.bits(),
            SVE_MISC::LD4D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL3(opcode) => opcode.bits(),
            SVE_MISC::LD4H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x4xVL(opcode) => opcode.bits(),
            SVE_MISC::LD4H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1(opcode) => opcode.bits(),
            SVE_MISC::LD4Q_SME_Zt4_SVE_Pg3_SVE_ADDR_RI_S4x2xVL(opcode) => opcode.bits(),
            SVE_MISC::LD4Q_SME_Zt4_SVE_Pg3_SVE_ADDR_RR_LSL4(opcode) => opcode.bits(),
            SVE_MISC::LD4W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x4xVL(opcode) => opcode.bits(),
            SVE_MISC::LD4W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2(opcode) => opcode.bits(),
            SVE_MISC::LDFF1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_R(opcode) => opcode.bits(),
            SVE_MISC::LDFF1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RR(opcode) => opcode.bits(),
            SVE_MISC::LDFF1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ(opcode) => opcode.bits(),
            SVE_MISC::LDFF1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22(opcode) => opcode.bits(),
            SVE_MISC::LDFF1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5(opcode) => opcode.bits(),
            SVE_MISC::LDFF1B_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_R(opcode) => opcode.bits(),
            SVE_MISC::LDFF1B_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RR(opcode) => opcode.bits(),
            SVE_MISC::LDFF1B_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW_22_S_D(opcode) => {
                opcode.bits()
            }
            SVE_MISC::LDFF1B_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_ZI_U5_S_D(opcode) => opcode.bits(),
            SVE_MISC::LDFF1B_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_R(opcode) => opcode.bits(),
            SVE_MISC::LDFF1B_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RR(opcode) => opcode.bits(),
            SVE_MISC::LDFF1B_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_R(opcode) => opcode.bits(),
            SVE_MISC::LDFF1B_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RR(opcode) => opcode.bits(),
            SVE_MISC::LDFF1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_R(opcode) => opcode.bits(),
            SVE_MISC::LDFF1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RR_LSL3(opcode) => opcode.bits(),
            SVE_MISC::LDFF1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ(opcode) => opcode.bits(),
            SVE_MISC::LDFF1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL3(opcode) => opcode.bits(),
            SVE_MISC::LDFF1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW3_22(opcode) => opcode.bits(),
            SVE_MISC::LDFF1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22(opcode) => opcode.bits(),
            SVE_MISC::LDFF1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x8(opcode) => opcode.bits(),
            SVE_MISC::LDFF1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_R(opcode) => opcode.bits(),
            SVE_MISC::LDFF1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RR_LSL1(opcode) => opcode.bits(),
            SVE_MISC::LDFF1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ(opcode) => opcode.bits(),
            SVE_MISC::LDFF1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL1(opcode) => opcode.bits(),
            SVE_MISC::LDFF1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW1_22(opcode) => opcode.bits(),
            SVE_MISC::LDFF1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22(opcode) => opcode.bits(),
            SVE_MISC::LDFF1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x2(opcode) => opcode.bits(),
            SVE_MISC::LDFF1H_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_R(opcode) => opcode.bits(),
            SVE_MISC::LDFF1H_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RR_LSL1(opcode) => opcode.bits(),
            SVE_MISC::LDFF1H_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW1_22_S_D(opcode) => {
                opcode.bits()
            }
            SVE_MISC::LDFF1H_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW_22_S_D(opcode) => {
                opcode.bits()
            }
            SVE_MISC::LDFF1H_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_ZI_U5x2_S_D(opcode) => opcode.bits(),
            SVE_MISC::LDFF1H_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_R(opcode) => opcode.bits(),
            SVE_MISC::LDFF1H_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RR_LSL1(opcode) => opcode.bits(),
            SVE_MISC::LDFF1SB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_R(opcode) => opcode.bits(),
            SVE_MISC::LDFF1SB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RR(opcode) => opcode.bits(),
            SVE_MISC::LDFF1SB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ(opcode) => opcode.bits(),
            SVE_MISC::LDFF1SB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22(opcode) => opcode.bits(),
            SVE_MISC::LDFF1SB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5(opcode) => opcode.bits(),
            SVE_MISC::LDFF1SB_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW_22_S_D(opcode) => {
                opcode.bits()
            }
            SVE_MISC::LDFF1SB_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_ZI_U5_S_D(opcode) => opcode.bits(),
            SVE_MISC::LDFF1SB_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_R(opcode) => opcode.bits(),
            SVE_MISC::LDFF1SB_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RR(opcode) => opcode.bits(),
            SVE_MISC::LDFF1SB_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_R(opcode) => opcode.bits(),
            SVE_MISC::LDFF1SB_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RR(opcode) => opcode.bits(),
            SVE_MISC::LDFF1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_R(opcode) => opcode.bits(),
            SVE_MISC::LDFF1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RR_LSL1(opcode) => opcode.bits(),
            SVE_MISC::LDFF1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ(opcode) => opcode.bits(),
            SVE_MISC::LDFF1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL1(opcode) => opcode.bits(),
            SVE_MISC::LDFF1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW1_22(opcode) => opcode.bits(),
            SVE_MISC::LDFF1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22(opcode) => opcode.bits(),
            SVE_MISC::LDFF1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x2(opcode) => opcode.bits(),
            SVE_MISC::LDFF1SH_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW1_22_S_D(opcode) => {
                opcode.bits()
            }
            SVE_MISC::LDFF1SH_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW_22_S_D(opcode) => {
                opcode.bits()
            }
            SVE_MISC::LDFF1SH_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_ZI_U5x2_S_D(opcode) => {
                opcode.bits()
            }
            SVE_MISC::LDFF1SH_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_R(opcode) => opcode.bits(),
            SVE_MISC::LDFF1SH_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RR_LSL1(opcode) => opcode.bits(),
            SVE_MISC::LDFF1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_R(opcode) => opcode.bits(),
            SVE_MISC::LDFF1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RR_LSL2(opcode) => opcode.bits(),
            SVE_MISC::LDFF1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ(opcode) => opcode.bits(),
            SVE_MISC::LDFF1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL2(opcode) => opcode.bits(),
            SVE_MISC::LDFF1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW2_22(opcode) => opcode.bits(),
            SVE_MISC::LDFF1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22(opcode) => opcode.bits(),
            SVE_MISC::LDFF1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x4(opcode) => opcode.bits(),
            SVE_MISC::LDFF1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_R(opcode) => opcode.bits(),
            SVE_MISC::LDFF1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RR_LSL2(opcode) => opcode.bits(),
            SVE_MISC::LDFF1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ(opcode) => opcode.bits(),
            SVE_MISC::LDFF1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL2(opcode) => opcode.bits(),
            SVE_MISC::LDFF1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW2_22(opcode) => opcode.bits(),
            SVE_MISC::LDFF1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22(opcode) => opcode.bits(),
            SVE_MISC::LDFF1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x4(opcode) => opcode.bits(),
            SVE_MISC::LDFF1W_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_R(opcode) => opcode.bits(),
            SVE_MISC::LDFF1W_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RR_LSL2(opcode) => opcode.bits(),
            SVE_MISC::LDFF1W_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW2_22_S_D(opcode) => {
                opcode.bits()
            }
            SVE_MISC::LDFF1W_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW_22_S_D(opcode) => {
                opcode.bits()
            }
            SVE_MISC::LDFF1W_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_ZI_U5x4_S_D(opcode) => opcode.bits(),
            SVE_MISC::LDNF1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL(opcode) => opcode.bits(),
            SVE_MISC::LDNF1B_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL(opcode) => opcode.bits(),
            SVE_MISC::LDNF1B_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL(opcode) => opcode.bits(),
            SVE_MISC::LDNF1B_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL(opcode) => opcode.bits(),
            SVE_MISC::LDNF1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL(opcode) => opcode.bits(),
            SVE_MISC::LDNF1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL(opcode) => opcode.bits(),
            SVE_MISC::LDNF1H_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL(opcode) => opcode.bits(),
            SVE_MISC::LDNF1H_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL(opcode) => opcode.bits(),
            SVE_MISC::LDNF1SB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL(opcode) => opcode.bits(),
            SVE_MISC::LDNF1SB_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL(opcode) => opcode.bits(),
            SVE_MISC::LDNF1SB_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL(opcode) => opcode.bits(),
            SVE_MISC::LDNF1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL(opcode) => opcode.bits(),
            SVE_MISC::LDNF1SH_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL(opcode) => opcode.bits(),
            SVE_MISC::LDNF1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL(opcode) => opcode.bits(),
            SVE_MISC::LDNF1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL(opcode) => opcode.bits(),
            SVE_MISC::LDNF1W_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL(opcode) => opcode.bits(),
            SVE_MISC::LDNT1B_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL(opcode) => opcode.bits(),
            SVE_MISC::LDNT1B_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR(opcode) => opcode.bits(),
            SVE_MISC::LDNT1B_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL(opcode) => opcode.bits(),
            SVE_MISC::LDNT1B_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR(opcode) => opcode.bits(),
            SVE_MISC::LDNT1B_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL(opcode) => opcode.bits(),
            SVE_MISC::LDNT1B_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR(opcode) => opcode.bits(),
            SVE_MISC::LDNT1B_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL(opcode) => opcode.bits(),
            SVE_MISC::LDNT1B_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR(opcode) => opcode.bits(),
            SVE_MISC::LDNT1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL(opcode) => opcode.bits(),
            SVE_MISC::LDNT1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX(opcode) => opcode.bits(),
            SVE_MISC::LDNT1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZX(opcode) => opcode.bits(),
            SVE_MISC::LDNT1B_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_ZX_S_S(opcode) => opcode.bits(),
            SVE_MISC::LDNT1D_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL(opcode) => opcode.bits(),
            SVE_MISC::LDNT1D_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR_LSL3(opcode) => opcode.bits(),
            SVE_MISC::LDNT1D_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL(opcode) => opcode.bits(),
            SVE_MISC::LDNT1D_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR_LSL3(opcode) => opcode.bits(),
            SVE_MISC::LDNT1D_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL(opcode) => opcode.bits(),
            SVE_MISC::LDNT1D_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL3(opcode) => opcode.bits(),
            SVE_MISC::LDNT1D_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL(opcode) => opcode.bits(),
            SVE_MISC::LDNT1D_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL3(opcode) => opcode.bits(),
            SVE_MISC::LDNT1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL(opcode) => opcode.bits(),
            SVE_MISC::LDNT1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL3(opcode) => opcode.bits(),
            SVE_MISC::LDNT1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZX(opcode) => opcode.bits(),
            SVE_MISC::LDNT1H_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL(opcode) => opcode.bits(),
            SVE_MISC::LDNT1H_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR_LSL1(opcode) => opcode.bits(),
            SVE_MISC::LDNT1H_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL(opcode) => opcode.bits(),
            SVE_MISC::LDNT1H_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR_LSL1(opcode) => opcode.bits(),
            SVE_MISC::LDNT1H_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL(opcode) => opcode.bits(),
            SVE_MISC::LDNT1H_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL1(opcode) => opcode.bits(),
            SVE_MISC::LDNT1H_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL(opcode) => opcode.bits(),
            SVE_MISC::LDNT1H_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL1(opcode) => opcode.bits(),
            SVE_MISC::LDNT1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL(opcode) => opcode.bits(),
            SVE_MISC::LDNT1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1(opcode) => opcode.bits(),
            SVE_MISC::LDNT1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZX(opcode) => opcode.bits(),
            SVE_MISC::LDNT1H_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_ZX_S_S(opcode) => opcode.bits(),
            SVE_MISC::LDNT1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZX(opcode) => opcode.bits(),
            SVE_MISC::LDNT1W_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL(opcode) => opcode.bits(),
            SVE_MISC::LDNT1W_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR_LSL2(opcode) => opcode.bits(),
            SVE_MISC::LDNT1W_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL(opcode) => opcode.bits(),
            SVE_MISC::LDNT1W_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR_LSL2(opcode) => opcode.bits(),
            SVE_MISC::LDNT1W_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL(opcode) => opcode.bits(),
            SVE_MISC::LDNT1W_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL2(opcode) => opcode.bits(),
            SVE_MISC::LDNT1W_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL(opcode) => opcode.bits(),
            SVE_MISC::LDNT1W_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL2(opcode) => opcode.bits(),
            SVE_MISC::LDNT1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL(opcode) => opcode.bits(),
            SVE_MISC::LDNT1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2(opcode) => opcode.bits(),
            SVE_MISC::LDNT1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZX(opcode) => opcode.bits(),
            SVE_MISC::LDNT1W_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_ZX_S_D(opcode) => opcode.bits(),
            SVE_MISC::LDR_SVE_PNt_SVE_ADDR_RI_S9xVL(opcode) => opcode.bits(),
            SVE_MISC::LDR_SVE_Pt_SVE_ADDR_RI_S9xVL(opcode) => opcode.bits(),
            SVE_MISC::LDR_SVE_Zt_SVE_ADDR_RI_S9xVL(opcode) => opcode.bits(),
            SVE_MISC::MLA_SVE_Zd_SVE_Zn_SVE_Zm3_22_INDEX(opcode) => opcode.bits(),
            SVE_MISC::MLA_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX(opcode) => opcode.bits(),
            SVE_MISC::MLA_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX(opcode) => opcode.bits(),
            SVE_MISC::MLS_SVE_Zd_SVE_Zn_SVE_Zm3_22_INDEX(opcode) => opcode.bits(),
            SVE_MISC::MLS_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX(opcode) => opcode.bits(),
            SVE_MISC::MLS_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX(opcode) => opcode.bits(),
            SVE_MISC::MOVPRFX_SVE_Zd_SVE_Zn(opcode) => opcode.bits(),
            SVE_MISC::MUL_SVE_Zd_SVE_Zn_SVE_Zm3_22_INDEX(opcode) => opcode.bits(),
            SVE_MISC::MUL_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX(opcode) => opcode.bits(),
            SVE_MISC::MUL_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX(opcode) => opcode.bits(),
            SVE_MISC::NANDS_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm(opcode) => opcode.bits(),
            SVE_MISC::NAND_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm(opcode) => opcode.bits(),
            SVE_MISC::NBSL_SVE_Zd_SVE_Zd_SVE_Zm_16_SVE_Zn(opcode) => opcode.bits(),
            SVE_MISC::NORS_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm(opcode) => opcode.bits(),
            SVE_MISC::NOR_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm(opcode) => opcode.bits(),
            SVE_MISC::ORNS_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm(opcode) => opcode.bits(),
            SVE_MISC::ORN_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm(opcode) => opcode.bits(),
            SVE_MISC::ORRS_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm(opcode) => opcode.bits(),
            SVE_MISC::ORR_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm(opcode) => opcode.bits(),
            SVE_MISC::ORR_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_MISC::PFALSE_SVE_PNd(opcode) => opcode.bits(),
            SVE_MISC::PFALSE_SVE_Pd(opcode) => opcode.bits(),
            SVE_MISC::PFIRST_SVE_Pd_SVE_Pg4_5_SVE_Pd(opcode) => opcode.bits(),
            SVE_MISC::PMULLB_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_MISC::PMULLT_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_MISC::PMUL_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_MISC::PRFB_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RI_S6xVL(opcode) => opcode.bits(),
            SVE_MISC::PRFB_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RX(opcode) => opcode.bits(),
            SVE_MISC::PRFB_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RZ(opcode) => opcode.bits(),
            SVE_MISC::PRFB_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RZ_XTW_22(opcode) => opcode.bits(),
            SVE_MISC::PRFB_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RZ_XTW_22_c4200000(opcode) => opcode.bits(),
            SVE_MISC::PRFB_SVE_PRFOP_SVE_Pg3_SVE_ADDR_ZI_U5(opcode) => opcode.bits(),
            SVE_MISC::PRFB_SVE_PRFOP_SVE_Pg3_SVE_ADDR_ZI_U5_c400e000(opcode) => opcode.bits(),
            SVE_MISC::PRFD_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RI_S6xVL(opcode) => opcode.bits(),
            SVE_MISC::PRFD_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RX_LSL3(opcode) => opcode.bits(),
            SVE_MISC::PRFD_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RZ_LSL3(opcode) => opcode.bits(),
            SVE_MISC::PRFD_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RZ_XTW3_22(opcode) => opcode.bits(),
            SVE_MISC::PRFD_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RZ_XTW3_22_c4206000(opcode) => opcode.bits(),
            SVE_MISC::PRFD_SVE_PRFOP_SVE_Pg3_SVE_ADDR_ZI_U5x8(opcode) => opcode.bits(),
            SVE_MISC::PRFD_SVE_PRFOP_SVE_Pg3_SVE_ADDR_ZI_U5x8_c580e000(opcode) => opcode.bits(),
            SVE_MISC::PRFH_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RI_S6xVL(opcode) => opcode.bits(),
            SVE_MISC::PRFH_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RX_LSL1(opcode) => opcode.bits(),
            SVE_MISC::PRFH_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RZ_LSL1(opcode) => opcode.bits(),
            SVE_MISC::PRFH_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RZ_XTW1_22(opcode) => opcode.bits(),
            SVE_MISC::PRFH_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RZ_XTW1_22_c4202000(opcode) => opcode.bits(),
            SVE_MISC::PRFH_SVE_PRFOP_SVE_Pg3_SVE_ADDR_ZI_U5x2(opcode) => opcode.bits(),
            SVE_MISC::PRFH_SVE_PRFOP_SVE_Pg3_SVE_ADDR_ZI_U5x2_c480e000(opcode) => opcode.bits(),
            SVE_MISC::PRFW_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RI_S6xVL(opcode) => opcode.bits(),
            SVE_MISC::PRFW_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RX_LSL2(opcode) => opcode.bits(),
            SVE_MISC::PRFW_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RZ_LSL2(opcode) => opcode.bits(),
            SVE_MISC::PRFW_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RZ_XTW2_22(opcode) => opcode.bits(),
            SVE_MISC::PRFW_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RZ_XTW2_22_c4204000(opcode) => opcode.bits(),
            SVE_MISC::PRFW_SVE_PRFOP_SVE_Pg3_SVE_ADDR_ZI_U5x4(opcode) => opcode.bits(),
            SVE_MISC::PRFW_SVE_PRFOP_SVE_Pg3_SVE_ADDR_ZI_U5x4_c500e000(opcode) => opcode.bits(),
            SVE_MISC::PTEST_SVE_Pg4_10_SVE_Pn(opcode) => opcode.bits(),
            SVE_MISC::PUNPKHI_SVE_Pd_SVE_Pn(opcode) => opcode.bits(),
            SVE_MISC::PUNPKLO_SVE_Pd_SVE_Pn(opcode) => opcode.bits(),
            SVE_MISC::RAX1_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_MISC::RDFFRS_SVE_Pd_SVE_Pg4_5(opcode) => opcode.bits(),
            SVE_MISC::RDFFR_SVE_Pd(opcode) => opcode.bits(),
            SVE_MISC::RDFFR_SVE_Pd_SVE_Pg4_5(opcode) => opcode.bits(),
            SVE_MISC::RDVL_Rd_SVE_SIMM6(opcode) => opcode.bits(),
            SVE_MISC::REVW_SVE_Zd_SVE_Pg3_SVE_Zn(opcode) => opcode.bits(),
            SVE_MISC::SCVTF_SME_Zdnx2_SME_Znx2(opcode) => opcode.bits(),
            SVE_MISC::SCVTF_SME_Zdnx4_SME_Znx4(opcode) => opcode.bits(),
            SVE_MISC::SCVTF_SVE_Zd_SVE_Pg3_SVE_Zn(opcode) => opcode.bits(),
            SVE_MISC::SCVTF_SVE_Zd_S_D_SVE_Pg3_P_M_SVE_Zn_S_D(opcode) => opcode.bits(),
            SVE_MISC::SCVTF_SVE_Zd_S_H_SVE_Pg3_P_M_SVE_Zn_S_D(opcode) => opcode.bits(),
            SVE_MISC::SCVTF_SVE_Zd_S_H_SVE_Pg3_P_M_SVE_Zn_S_H(opcode) => opcode.bits(),
            SVE_MISC::SCVTF_SVE_Zd_S_H_SVE_Pg3_P_M_SVE_Zn_S_S(opcode) => opcode.bits(),
            SVE_MISC::SCVTF_SVE_Zd_S_S_SVE_Pg3_P_M_SVE_Zn_S_D(opcode) => opcode.bits(),
            SVE_MISC::SCVTF_SVE_Zd_S_S_SVE_Pg3_P_M_SVE_Zn_S_S(opcode) => opcode.bits(),
            SVE_MISC::SDOT_SVE_Zd_SVE_Zn_SVE_Zm3_19_INDEX(opcode) => opcode.bits(),
            SVE_MISC::SDOT_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX(opcode) => opcode.bits(),
            SVE_MISC::SDOT_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX(opcode) => opcode.bits(),
            SVE_MISC::SDOT_SVE_Zd_S_S_SVE_Zn_S_H_SVE_Zm_16_S_H(opcode) => opcode.bits(),
            SVE_MISC::SEL_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm(opcode) => opcode.bits(),
            SVE_MISC::SETFFR(opcode) => opcode.bits(),
            SVE_MISC::SM4EKEY_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_MISC::SM4E_SVE_Zd_SVE_Zd_SVE_Zn(opcode) => opcode.bits(),
            SVE_MISC::SMLALB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX(opcode) => opcode.bits(),
            SVE_MISC::SMLALB_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX(opcode) => opcode.bits(),
            SVE_MISC::SMLALT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX(opcode) => opcode.bits(),
            SVE_MISC::SMLALT_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX(opcode) => opcode.bits(),
            SVE_MISC::SMLSLB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX(opcode) => opcode.bits(),
            SVE_MISC::SMLSLB_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX(opcode) => opcode.bits(),
            SVE_MISC::SMLSLT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX(opcode) => opcode.bits(),
            SVE_MISC::SMLSLT_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX(opcode) => opcode.bits(),
            SVE_MISC::SMMLA_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_MISC::SMULLB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX(opcode) => opcode.bits(),
            SVE_MISC::SMULLB_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX(opcode) => opcode.bits(),
            SVE_MISC::SMULLT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX(opcode) => opcode.bits(),
            SVE_MISC::SMULLT_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX(opcode) => opcode.bits(),
            SVE_MISC::SQCVTN_SVE_Zd_SME_Znx2(opcode) => opcode.bits(),
            SVE_MISC::SQCVTUN_SVE_Zd_SME_Znx2(opcode) => opcode.bits(),
            SVE_MISC::SQDECB_Rd_Rd_SVE_PATTERN_SCALED(opcode) => opcode.bits(),
            SVE_MISC::SQDECB_Rd_SVE_PATTERN_SCALED(opcode) => opcode.bits(),
            SVE_MISC::SQDECD_Rd_Rd_SVE_PATTERN_SCALED(opcode) => opcode.bits(),
            SVE_MISC::SQDECD_Rd_SVE_PATTERN_SCALED(opcode) => opcode.bits(),
            SVE_MISC::SQDECD_SVE_Zd_SVE_PATTERN_SCALED(opcode) => opcode.bits(),
            SVE_MISC::SQDECH_Rd_Rd_SVE_PATTERN_SCALED(opcode) => opcode.bits(),
            SVE_MISC::SQDECH_Rd_SVE_PATTERN_SCALED(opcode) => opcode.bits(),
            SVE_MISC::SQDECH_SVE_Zd_SVE_PATTERN_SCALED(opcode) => opcode.bits(),
            SVE_MISC::SQDECW_Rd_Rd_SVE_PATTERN_SCALED(opcode) => opcode.bits(),
            SVE_MISC::SQDECW_Rd_SVE_PATTERN_SCALED(opcode) => opcode.bits(),
            SVE_MISC::SQDECW_SVE_Zd_SVE_PATTERN_SCALED(opcode) => opcode.bits(),
            SVE_MISC::SQDMLALB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX(opcode) => opcode.bits(),
            SVE_MISC::SQDMLALB_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX(opcode) => opcode.bits(),
            SVE_MISC::SQDMLALT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX(opcode) => opcode.bits(),
            SVE_MISC::SQDMLALT_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX(opcode) => opcode.bits(),
            SVE_MISC::SQDMLSLB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX(opcode) => opcode.bits(),
            SVE_MISC::SQDMLSLB_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX(opcode) => opcode.bits(),
            SVE_MISC::SQDMLSLT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX(opcode) => opcode.bits(),
            SVE_MISC::SQDMLSLT_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX(opcode) => opcode.bits(),
            SVE_MISC::SQDMULH_SVE_Zd_SVE_Zn_SVE_Zm3_22_INDEX(opcode) => opcode.bits(),
            SVE_MISC::SQDMULH_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX(opcode) => opcode.bits(),
            SVE_MISC::SQDMULH_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX(opcode) => opcode.bits(),
            SVE_MISC::SQDMULLB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX(opcode) => opcode.bits(),
            SVE_MISC::SQDMULLB_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX(opcode) => opcode.bits(),
            SVE_MISC::SQDMULLT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX(opcode) => opcode.bits(),
            SVE_MISC::SQDMULLT_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX(opcode) => opcode.bits(),
            SVE_MISC::SQINCB_Rd_Rd_SVE_PATTERN_SCALED(opcode) => opcode.bits(),
            SVE_MISC::SQINCB_Rd_SVE_PATTERN_SCALED(opcode) => opcode.bits(),
            SVE_MISC::SQINCD_Rd_Rd_SVE_PATTERN_SCALED(opcode) => opcode.bits(),
            SVE_MISC::SQINCD_Rd_SVE_PATTERN_SCALED(opcode) => opcode.bits(),
            SVE_MISC::SQINCD_SVE_Zd_SVE_PATTERN_SCALED(opcode) => opcode.bits(),
            SVE_MISC::SQINCH_Rd_Rd_SVE_PATTERN_SCALED(opcode) => opcode.bits(),
            SVE_MISC::SQINCH_Rd_SVE_PATTERN_SCALED(opcode) => opcode.bits(),
            SVE_MISC::SQINCH_SVE_Zd_SVE_PATTERN_SCALED(opcode) => opcode.bits(),
            SVE_MISC::SQINCW_Rd_Rd_SVE_PATTERN_SCALED(opcode) => opcode.bits(),
            SVE_MISC::SQINCW_Rd_SVE_PATTERN_SCALED(opcode) => opcode.bits(),
            SVE_MISC::SQINCW_SVE_Zd_SVE_PATTERN_SCALED(opcode) => opcode.bits(),
            SVE_MISC::SQRDCMLAH_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX_SVE_IMM_ROT2(opcode) => opcode.bits(),
            SVE_MISC::SQRDCMLAH_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX_SVE_IMM_ROT2(opcode) => opcode.bits(),
            SVE_MISC::SQRDMLAH_SVE_Zd_SVE_Zn_SVE_Zm3_22_INDEX(opcode) => opcode.bits(),
            SVE_MISC::SQRDMLAH_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX(opcode) => opcode.bits(),
            SVE_MISC::SQRDMLAH_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX(opcode) => opcode.bits(),
            SVE_MISC::SQRDMLSH_SVE_Zd_SVE_Zn_SVE_Zm3_22_INDEX(opcode) => opcode.bits(),
            SVE_MISC::SQRDMLSH_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX(opcode) => opcode.bits(),
            SVE_MISC::SQRDMLSH_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX(opcode) => opcode.bits(),
            SVE_MISC::SQRDMULH_SVE_Zd_SVE_Zn_SVE_Zm3_22_INDEX(opcode) => opcode.bits(),
            SVE_MISC::SQRDMULH_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX(opcode) => opcode.bits(),
            SVE_MISC::SQRDMULH_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX(opcode) => opcode.bits(),
            SVE_MISC::ST1B_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_R(opcode) => opcode.bits(),
            SVE_MISC::ST1B_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_RR(opcode) => opcode.bits(),
            SVE_MISC::ST1B_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL(opcode) => opcode.bits(),
            SVE_MISC::ST1B_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR(opcode) => opcode.bits(),
            SVE_MISC::ST1B_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL(opcode) => opcode.bits(),
            SVE_MISC::ST1B_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR(opcode) => opcode.bits(),
            SVE_MISC::ST1B_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL(opcode) => opcode.bits(),
            SVE_MISC::ST1B_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR(opcode) => opcode.bits(),
            SVE_MISC::ST1B_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL(opcode) => opcode.bits(),
            SVE_MISC::ST1B_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR(opcode) => opcode.bits(),
            SVE_MISC::ST1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL(opcode) => opcode.bits(),
            SVE_MISC::ST1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX(opcode) => opcode.bits(),
            SVE_MISC::ST1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ(opcode) => opcode.bits(),
            SVE_MISC::ST1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_14(opcode) => opcode.bits(),
            SVE_MISC::ST1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5(opcode) => opcode.bits(),
            SVE_MISC::ST1B_SVE_ZtxN_S_D_SVE_Pg3_SVE_ADDR_RI_S4xVL(opcode) => opcode.bits(),
            SVE_MISC::ST1B_SVE_ZtxN_S_D_SVE_Pg3_SVE_ADDR_RX(opcode) => opcode.bits(),
            SVE_MISC::ST1B_SVE_ZtxN_S_H_SVE_Pg3_SVE_ADDR_RI_S4xVL(opcode) => opcode.bits(),
            SVE_MISC::ST1B_SVE_ZtxN_S_H_SVE_Pg3_SVE_ADDR_RX(opcode) => opcode.bits(),
            SVE_MISC::ST1B_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_RI_S4xVL(opcode) => opcode.bits(),
            SVE_MISC::ST1B_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_RX(opcode) => opcode.bits(),
            SVE_MISC::ST1B_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_RZ_XTW_14(opcode) => opcode.bits(),
            SVE_MISC::ST1B_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_ZI_U5(opcode) => opcode.bits(),
            SVE_MISC::ST1D_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_R(opcode) => opcode.bits(),
            SVE_MISC::ST1D_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_RR_LSL3(opcode) => opcode.bits(),
            SVE_MISC::ST1D_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL(opcode) => opcode.bits(),
            SVE_MISC::ST1D_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR_LSL3(opcode) => opcode.bits(),
            SVE_MISC::ST1D_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL(opcode) => opcode.bits(),
            SVE_MISC::ST1D_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR_LSL3(opcode) => opcode.bits(),
            SVE_MISC::ST1D_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL(opcode) => opcode.bits(),
            SVE_MISC::ST1D_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL3(opcode) => opcode.bits(),
            SVE_MISC::ST1D_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL(opcode) => opcode.bits(),
            SVE_MISC::ST1D_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL3(opcode) => opcode.bits(),
            SVE_MISC::ST1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL(opcode) => opcode.bits(),
            SVE_MISC::ST1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL3(opcode) => opcode.bits(),
            SVE_MISC::ST1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ(opcode) => opcode.bits(),
            SVE_MISC::ST1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL3(opcode) => opcode.bits(),
            SVE_MISC::ST1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW3_14(opcode) => opcode.bits(),
            SVE_MISC::ST1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_14(opcode) => opcode.bits(),
            SVE_MISC::ST1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x8(opcode) => opcode.bits(),
            SVE_MISC::ST1H_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_R(opcode) => opcode.bits(),
            SVE_MISC::ST1H_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_RR_LSL1(opcode) => opcode.bits(),
            SVE_MISC::ST1H_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL(opcode) => opcode.bits(),
            SVE_MISC::ST1H_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR_LSL1(opcode) => opcode.bits(),
            SVE_MISC::ST1H_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL(opcode) => opcode.bits(),
            SVE_MISC::ST1H_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR_LSL1(opcode) => opcode.bits(),
            SVE_MISC::ST1H_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL(opcode) => opcode.bits(),
            SVE_MISC::ST1H_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL1(opcode) => opcode.bits(),
            SVE_MISC::ST1H_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL(opcode) => opcode.bits(),
            SVE_MISC::ST1H_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL1(opcode) => opcode.bits(),
            SVE_MISC::ST1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL(opcode) => opcode.bits(),
            SVE_MISC::ST1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1(opcode) => opcode.bits(),
            SVE_MISC::ST1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ(opcode) => opcode.bits(),
            SVE_MISC::ST1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL1(opcode) => opcode.bits(),
            SVE_MISC::ST1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW1_14(opcode) => opcode.bits(),
            SVE_MISC::ST1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_14(opcode) => opcode.bits(),
            SVE_MISC::ST1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x2(opcode) => opcode.bits(),
            SVE_MISC::ST1H_SVE_ZtxN_S_D_SVE_Pg3_SVE_ADDR_RI_S4xVL(opcode) => opcode.bits(),
            SVE_MISC::ST1H_SVE_ZtxN_S_D_SVE_Pg3_SVE_ADDR_RX_LSL1(opcode) => opcode.bits(),
            SVE_MISC::ST1H_SVE_ZtxN_S_H_SVE_Pg3_SVE_ADDR_RI_S4xVL(opcode) => opcode.bits(),
            SVE_MISC::ST1H_SVE_ZtxN_S_H_SVE_Pg3_SVE_ADDR_RX_LSL1(opcode) => opcode.bits(),
            SVE_MISC::ST1H_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_RZ_XTW1_14(opcode) => opcode.bits(),
            SVE_MISC::ST1H_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_RZ_XTW_14(opcode) => opcode.bits(),
            SVE_MISC::ST1H_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_ZI_U5x2(opcode) => opcode.bits(),
            SVE_MISC::ST1Q_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_R(opcode) => opcode.bits(),
            SVE_MISC::ST1Q_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_RR_LSL4(opcode) => opcode.bits(),
            SVE_MISC::ST1Q_SVE_Zt_SVE_Pg3_SVE_ADDR_ZX(opcode) => opcode.bits(),
            SVE_MISC::ST1W_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_R(opcode) => opcode.bits(),
            SVE_MISC::ST1W_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_RR_LSL2(opcode) => opcode.bits(),
            SVE_MISC::ST1W_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL(opcode) => opcode.bits(),
            SVE_MISC::ST1W_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR_LSL2(opcode) => opcode.bits(),
            SVE_MISC::ST1W_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL(opcode) => opcode.bits(),
            SVE_MISC::ST1W_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR_LSL2(opcode) => opcode.bits(),
            SVE_MISC::ST1W_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL(opcode) => opcode.bits(),
            SVE_MISC::ST1W_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL2(opcode) => opcode.bits(),
            SVE_MISC::ST1W_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL(opcode) => opcode.bits(),
            SVE_MISC::ST1W_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL2(opcode) => opcode.bits(),
            SVE_MISC::ST1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL(opcode) => opcode.bits(),
            SVE_MISC::ST1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2(opcode) => opcode.bits(),
            SVE_MISC::ST1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ(opcode) => opcode.bits(),
            SVE_MISC::ST1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL2(opcode) => opcode.bits(),
            SVE_MISC::ST1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW2_14(opcode) => opcode.bits(),
            SVE_MISC::ST1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_14(opcode) => opcode.bits(),
            SVE_MISC::ST1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x4(opcode) => opcode.bits(),
            SVE_MISC::ST1W_SVE_ZtxN_S_D_SVE_Pg3_SVE_ADDR_RI_S4xVL(opcode) => opcode.bits(),
            SVE_MISC::ST1W_SVE_ZtxN_S_D_SVE_Pg3_SVE_ADDR_RX_LSL2(opcode) => opcode.bits(),
            SVE_MISC::ST1W_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_RZ_XTW2_14(opcode) => opcode.bits(),
            SVE_MISC::ST1W_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_RZ_XTW_14(opcode) => opcode.bits(),
            SVE_MISC::ST1W_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_ZI_U5x4(opcode) => opcode.bits(),
            SVE_MISC::ST2B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x2xVL(opcode) => opcode.bits(),
            SVE_MISC::ST2B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX(opcode) => opcode.bits(),
            SVE_MISC::ST2D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x2xVL(opcode) => opcode.bits(),
            SVE_MISC::ST2D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL3(opcode) => opcode.bits(),
            SVE_MISC::ST2H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x2xVL(opcode) => opcode.bits(),
            SVE_MISC::ST2H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1(opcode) => opcode.bits(),
            SVE_MISC::ST2Q_SME_Zt2_SVE_Pg3_SVE_ADDR_RI_S4x2xVL(opcode) => opcode.bits(),
            SVE_MISC::ST2Q_SME_Zt2_SVE_Pg3_SVE_ADDR_RR_LSL4(opcode) => opcode.bits(),
            SVE_MISC::ST2W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x2xVL(opcode) => opcode.bits(),
            SVE_MISC::ST2W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2(opcode) => opcode.bits(),
            SVE_MISC::ST3B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x3xVL(opcode) => opcode.bits(),
            SVE_MISC::ST3B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX(opcode) => opcode.bits(),
            SVE_MISC::ST3D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x3xVL(opcode) => opcode.bits(),
            SVE_MISC::ST3D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL3(opcode) => opcode.bits(),
            SVE_MISC::ST3H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x3xVL(opcode) => opcode.bits(),
            SVE_MISC::ST3H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1(opcode) => opcode.bits(),
            SVE_MISC::ST3Q_SME_Zt3_SVE_Pg3_SVE_ADDR_RI_S4x2xVL(opcode) => opcode.bits(),
            SVE_MISC::ST3Q_SME_Zt3_SVE_Pg3_SVE_ADDR_RR_LSL4(opcode) => opcode.bits(),
            SVE_MISC::ST3W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x3xVL(opcode) => opcode.bits(),
            SVE_MISC::ST3W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2(opcode) => opcode.bits(),
            SVE_MISC::ST4B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x4xVL(opcode) => opcode.bits(),
            SVE_MISC::ST4B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX(opcode) => opcode.bits(),
            SVE_MISC::ST4D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x4xVL(opcode) => opcode.bits(),
            SVE_MISC::ST4D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL3(opcode) => opcode.bits(),
            SVE_MISC::ST4H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x4xVL(opcode) => opcode.bits(),
            SVE_MISC::ST4H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1(opcode) => opcode.bits(),
            SVE_MISC::ST4Q_SME_Zt4_SVE_Pg3_SVE_ADDR_RI_S4x2xVL(opcode) => opcode.bits(),
            SVE_MISC::ST4Q_SME_Zt4_SVE_Pg3_SVE_ADDR_RR_LSL4(opcode) => opcode.bits(),
            SVE_MISC::ST4W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x4xVL(opcode) => opcode.bits(),
            SVE_MISC::ST4W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2(opcode) => opcode.bits(),
            SVE_MISC::STNT1B_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL(opcode) => opcode.bits(),
            SVE_MISC::STNT1B_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR(opcode) => opcode.bits(),
            SVE_MISC::STNT1B_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL(opcode) => opcode.bits(),
            SVE_MISC::STNT1B_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR(opcode) => opcode.bits(),
            SVE_MISC::STNT1B_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL(opcode) => opcode.bits(),
            SVE_MISC::STNT1B_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR(opcode) => opcode.bits(),
            SVE_MISC::STNT1B_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL(opcode) => opcode.bits(),
            SVE_MISC::STNT1B_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR(opcode) => opcode.bits(),
            SVE_MISC::STNT1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL(opcode) => opcode.bits(),
            SVE_MISC::STNT1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX(opcode) => opcode.bits(),
            SVE_MISC::STNT1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZX(opcode) => opcode.bits(),
            SVE_MISC::STNT1B_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_ZX(opcode) => opcode.bits(),
            SVE_MISC::STNT1D_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL(opcode) => opcode.bits(),
            SVE_MISC::STNT1D_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR_LSL3(opcode) => opcode.bits(),
            SVE_MISC::STNT1D_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL(opcode) => opcode.bits(),
            SVE_MISC::STNT1D_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR_LSL3(opcode) => opcode.bits(),
            SVE_MISC::STNT1D_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL(opcode) => opcode.bits(),
            SVE_MISC::STNT1D_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL3(opcode) => opcode.bits(),
            SVE_MISC::STNT1D_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL(opcode) => opcode.bits(),
            SVE_MISC::STNT1D_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL3(opcode) => opcode.bits(),
            SVE_MISC::STNT1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL(opcode) => opcode.bits(),
            SVE_MISC::STNT1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL3(opcode) => opcode.bits(),
            SVE_MISC::STNT1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZX(opcode) => opcode.bits(),
            SVE_MISC::STNT1H_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL(opcode) => opcode.bits(),
            SVE_MISC::STNT1H_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR_LSL1(opcode) => opcode.bits(),
            SVE_MISC::STNT1H_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL(opcode) => opcode.bits(),
            SVE_MISC::STNT1H_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR_LSL1(opcode) => opcode.bits(),
            SVE_MISC::STNT1H_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL(opcode) => opcode.bits(),
            SVE_MISC::STNT1H_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL1(opcode) => opcode.bits(),
            SVE_MISC::STNT1H_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL(opcode) => opcode.bits(),
            SVE_MISC::STNT1H_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL1(opcode) => opcode.bits(),
            SVE_MISC::STNT1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL(opcode) => opcode.bits(),
            SVE_MISC::STNT1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1(opcode) => opcode.bits(),
            SVE_MISC::STNT1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZX(opcode) => opcode.bits(),
            SVE_MISC::STNT1H_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_ZX(opcode) => opcode.bits(),
            SVE_MISC::STNT1W_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL(opcode) => opcode.bits(),
            SVE_MISC::STNT1W_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR_LSL2(opcode) => opcode.bits(),
            SVE_MISC::STNT1W_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL(opcode) => opcode.bits(),
            SVE_MISC::STNT1W_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR_LSL2(opcode) => opcode.bits(),
            SVE_MISC::STNT1W_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL(opcode) => opcode.bits(),
            SVE_MISC::STNT1W_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL2(opcode) => opcode.bits(),
            SVE_MISC::STNT1W_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL(opcode) => opcode.bits(),
            SVE_MISC::STNT1W_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL2(opcode) => opcode.bits(),
            SVE_MISC::STNT1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL(opcode) => opcode.bits(),
            SVE_MISC::STNT1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2(opcode) => opcode.bits(),
            SVE_MISC::STNT1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZX(opcode) => opcode.bits(),
            SVE_MISC::STNT1W_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_ZX(opcode) => opcode.bits(),
            SVE_MISC::STR_SVE_PNt_SVE_ADDR_RI_S9xVL(opcode) => opcode.bits(),
            SVE_MISC::STR_SVE_Pt_SVE_ADDR_RI_S9xVL(opcode) => opcode.bits(),
            SVE_MISC::STR_SVE_Zt_SVE_ADDR_RI_S9xVL(opcode) => opcode.bits(),
            SVE_MISC::SUDOT_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX(opcode) => opcode.bits(),
            SVE_MISC::SXTW_SVE_Zd_SVE_Pg3_SVE_Zn(opcode) => opcode.bits(),
            SVE_MISC::TRN1_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_MISC::TRN2_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_MISC::UCVTF_SME_Zdnx2_SME_Znx2(opcode) => opcode.bits(),
            SVE_MISC::UCVTF_SME_Zdnx4_SME_Znx4(opcode) => opcode.bits(),
            SVE_MISC::UCVTF_SVE_Zd_SVE_Pg3_SVE_Zn(opcode) => opcode.bits(),
            SVE_MISC::UCVTF_SVE_Zd_S_D_SVE_Pg3_P_M_SVE_Zn_S_D(opcode) => opcode.bits(),
            SVE_MISC::UCVTF_SVE_Zd_S_H_SVE_Pg3_P_M_SVE_Zn_S_D(opcode) => opcode.bits(),
            SVE_MISC::UCVTF_SVE_Zd_S_H_SVE_Pg3_P_M_SVE_Zn_S_H(opcode) => opcode.bits(),
            SVE_MISC::UCVTF_SVE_Zd_S_H_SVE_Pg3_P_M_SVE_Zn_S_S(opcode) => opcode.bits(),
            SVE_MISC::UCVTF_SVE_Zd_S_S_SVE_Pg3_P_M_SVE_Zn_S_D(opcode) => opcode.bits(),
            SVE_MISC::UCVTF_SVE_Zd_S_S_SVE_Pg3_P_M_SVE_Zn_S_S(opcode) => opcode.bits(),
            SVE_MISC::UDOT_SVE_Zd_SVE_Zn_SVE_Zm3_19_INDEX(opcode) => opcode.bits(),
            SVE_MISC::UDOT_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX(opcode) => opcode.bits(),
            SVE_MISC::UDOT_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX(opcode) => opcode.bits(),
            SVE_MISC::UDOT_SVE_Zd_S_S_SVE_Zn_S_H_SVE_Zm_16_S_H(opcode) => opcode.bits(),
            SVE_MISC::UMLALB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX(opcode) => opcode.bits(),
            SVE_MISC::UMLALB_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX(opcode) => opcode.bits(),
            SVE_MISC::UMLALT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX(opcode) => opcode.bits(),
            SVE_MISC::UMLALT_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX(opcode) => opcode.bits(),
            SVE_MISC::UMLSLB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX(opcode) => opcode.bits(),
            SVE_MISC::UMLSLB_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX(opcode) => opcode.bits(),
            SVE_MISC::UMLSLT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX(opcode) => opcode.bits(),
            SVE_MISC::UMLSLT_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX(opcode) => opcode.bits(),
            SVE_MISC::UMMLA_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_MISC::UMULLB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX(opcode) => opcode.bits(),
            SVE_MISC::UMULLB_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX(opcode) => opcode.bits(),
            SVE_MISC::UMULLT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX(opcode) => opcode.bits(),
            SVE_MISC::UMULLT_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX(opcode) => opcode.bits(),
            SVE_MISC::UQCVTN_SVE_Zd_SME_Znx2(opcode) => opcode.bits(),
            SVE_MISC::UQDECB_Rd_SVE_PATTERN_SCALED(opcode) => opcode.bits(),
            SVE_MISC::UQDECB_Rd_X_SVE_PATTERN_SCALED(opcode) => opcode.bits(),
            SVE_MISC::UQDECD_Rd_SVE_PATTERN_SCALED(opcode) => opcode.bits(),
            SVE_MISC::UQDECD_Rd_X_SVE_PATTERN_SCALED(opcode) => opcode.bits(),
            SVE_MISC::UQDECD_SVE_Zd_SVE_PATTERN_SCALED(opcode) => opcode.bits(),
            SVE_MISC::UQDECH_Rd_SVE_PATTERN_SCALED(opcode) => opcode.bits(),
            SVE_MISC::UQDECH_Rd_X_SVE_PATTERN_SCALED(opcode) => opcode.bits(),
            SVE_MISC::UQDECH_SVE_Zd_SVE_PATTERN_SCALED(opcode) => opcode.bits(),
            SVE_MISC::UQDECW_Rd_SVE_PATTERN_SCALED(opcode) => opcode.bits(),
            SVE_MISC::UQDECW_Rd_X_SVE_PATTERN_SCALED(opcode) => opcode.bits(),
            SVE_MISC::UQDECW_SVE_Zd_SVE_PATTERN_SCALED(opcode) => opcode.bits(),
            SVE_MISC::UQINCB_Rd_SVE_PATTERN_SCALED(opcode) => opcode.bits(),
            SVE_MISC::UQINCB_Rd_X_SVE_PATTERN_SCALED(opcode) => opcode.bits(),
            SVE_MISC::UQINCD_Rd_SVE_PATTERN_SCALED(opcode) => opcode.bits(),
            SVE_MISC::UQINCD_Rd_X_SVE_PATTERN_SCALED(opcode) => opcode.bits(),
            SVE_MISC::UQINCD_SVE_Zd_SVE_PATTERN_SCALED(opcode) => opcode.bits(),
            SVE_MISC::UQINCH_Rd_SVE_PATTERN_SCALED(opcode) => opcode.bits(),
            SVE_MISC::UQINCH_Rd_X_SVE_PATTERN_SCALED(opcode) => opcode.bits(),
            SVE_MISC::UQINCH_SVE_Zd_SVE_PATTERN_SCALED(opcode) => opcode.bits(),
            SVE_MISC::UQINCW_Rd_SVE_PATTERN_SCALED(opcode) => opcode.bits(),
            SVE_MISC::UQINCW_Rd_X_SVE_PATTERN_SCALED(opcode) => opcode.bits(),
            SVE_MISC::UQINCW_SVE_Zd_SVE_PATTERN_SCALED(opcode) => opcode.bits(),
            SVE_MISC::URECPE_SVE_Zd_SVE_Pg3_SVE_Zn(opcode) => opcode.bits(),
            SVE_MISC::URSQRTE_SVE_Zd_SVE_Pg3_SVE_Zn(opcode) => opcode.bits(),
            SVE_MISC::USDOT_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX(opcode) => opcode.bits(),
            SVE_MISC::USDOT_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_MISC::USMMLA_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_MISC::UXTW_SVE_Zd_SVE_Pg3_SVE_Zn(opcode) => opcode.bits(),
            SVE_MISC::UZP1_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_MISC::UZP2_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_MISC::WRFFR_SVE_Pn(opcode) => opcode.bits(),
            SVE_MISC::ZIP1_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
            SVE_MISC::ZIP2_SVE_Zd_SVE_Zn_SVE_Zm_16(opcode) => opcode.bits(),
        }
    }
}
impl InsnOpcode for SME_INT_SD {
    fn definition(&self) -> &'static Insn {
        match self {
            SME_INT_SD::ADD_SME_ZA_array_off3_0_SME_Znx2(opcode) => opcode.definition(),
            SME_INT_SD::ADD_SME_ZA_array_off3_0_SME_Znx2_SME_Zmx2(opcode) => opcode.definition(),
            SME_INT_SD::ADD_SME_ZA_array_off3_0_SME_Znx4(opcode) => opcode.definition(),
            SME_INT_SD::ADD_SME_ZA_array_off3_0_SME_Znx4_SME_Zmx4(opcode) => opcode.definition(),
            SME_INT_SD::ADD_SME_ZA_array_off3_0_SVE_ZnxN_SME_Zm(opcode) => opcode.definition(),
            SME_INT_SD::ADD_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_S_SME_Zm_S_S(opcode) => {
                opcode.definition()
            }
            SME_INT_SD::SDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zmx2(opcode) => opcode.definition(),
            SME_INT_SD::SDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zmx4(opcode) => opcode.definition(),
            SME_INT_SD::SDOT_SME_ZA_array_off3_0_SVE_ZnxN_SME_Zm(opcode) => opcode.definition(),
            SME_INT_SD::SDOT_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_B_SME_Zm_S_B(opcode) => {
                opcode.definition()
            }
            SME_INT_SD::SMLALL_SME_ZA_array_off1x4_SME_Znx2_SME_Zmx2(opcode) => opcode.definition(),
            SME_INT_SD::SMLALL_SME_ZA_array_off1x4_SME_Znx4_SME_Zmx4(opcode) => opcode.definition(),
            SME_INT_SD::SMLALL_SME_ZA_array_off1x4_SVE_ZnxN_SME_Zm(opcode) => opcode.definition(),
            SME_INT_SD::SMLALL_SME_ZA_array_off1x4_S_S_SVE_ZnxN_S_B_SME_Zm_S_B(opcode) => {
                opcode.definition()
            }
            SME_INT_SD::SMLALL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm(opcode) => opcode.definition(),
            SME_INT_SD::SMLSLL_SME_ZA_array_off1x4_SME_Znx2_SME_Zmx2(opcode) => opcode.definition(),
            SME_INT_SD::SMLSLL_SME_ZA_array_off1x4_SME_Znx4_SME_Zmx4(opcode) => opcode.definition(),
            SME_INT_SD::SMLSLL_SME_ZA_array_off1x4_SVE_ZnxN_SME_Zm(opcode) => opcode.definition(),
            SME_INT_SD::SMLSLL_SME_ZA_array_off1x4_S_S_SVE_ZnxN_S_B_SME_Zm_S_B(opcode) => {
                opcode.definition()
            }
            SME_INT_SD::SMLSLL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm(opcode) => opcode.definition(),
            SME_INT_SD::SUB_SME_ZA_array_off3_0_SME_Znx2(opcode) => opcode.definition(),
            SME_INT_SD::SUB_SME_ZA_array_off3_0_SME_Znx2_SME_Zmx2(opcode) => opcode.definition(),
            SME_INT_SD::SUB_SME_ZA_array_off3_0_SME_Znx4(opcode) => opcode.definition(),
            SME_INT_SD::SUB_SME_ZA_array_off3_0_SME_Znx4_SME_Zmx4(opcode) => opcode.definition(),
            SME_INT_SD::SUB_SME_ZA_array_off3_0_SVE_ZnxN_SME_Zm(opcode) => opcode.definition(),
            SME_INT_SD::SUB_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_S_SME_Zm_S_S(opcode) => {
                opcode.definition()
            }
            SME_INT_SD::UDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zmx2(opcode) => opcode.definition(),
            SME_INT_SD::UDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zmx4(opcode) => opcode.definition(),
            SME_INT_SD::UDOT_SME_ZA_array_off3_0_SVE_ZnxN_SME_Zm(opcode) => opcode.definition(),
            SME_INT_SD::UDOT_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_B_SME_Zm_S_B(opcode) => {
                opcode.definition()
            }
            SME_INT_SD::UMLALL_SME_ZA_array_off1x4_SME_Znx2_SME_Zmx2(opcode) => opcode.definition(),
            SME_INT_SD::UMLALL_SME_ZA_array_off1x4_SME_Znx4_SME_Zmx4(opcode) => opcode.definition(),
            SME_INT_SD::UMLALL_SME_ZA_array_off1x4_SVE_ZnxN_SME_Zm(opcode) => opcode.definition(),
            SME_INT_SD::UMLALL_SME_ZA_array_off1x4_S_S_SVE_ZnxN_S_B_SME_Zm_S_B(opcode) => {
                opcode.definition()
            }
            SME_INT_SD::UMLALL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm(opcode) => opcode.definition(),
            SME_INT_SD::UMLSLL_SME_ZA_array_off1x4_SME_Znx2_SME_Zmx2(opcode) => opcode.definition(),
            SME_INT_SD::UMLSLL_SME_ZA_array_off1x4_SME_Znx4_SME_Zmx4(opcode) => opcode.definition(),
            SME_INT_SD::UMLSLL_SME_ZA_array_off1x4_SVE_ZnxN_SME_Zm(opcode) => opcode.definition(),
            SME_INT_SD::UMLSLL_SME_ZA_array_off1x4_S_S_SVE_ZnxN_S_B_SME_Zm_S_B(opcode) => {
                opcode.definition()
            }
            SME_INT_SD::UMLSLL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm(opcode) => opcode.definition(),
        }
    }
    fn bits(&self) -> u32 {
        match self {
            SME_INT_SD::ADD_SME_ZA_array_off3_0_SME_Znx2(opcode) => opcode.bits(),
            SME_INT_SD::ADD_SME_ZA_array_off3_0_SME_Znx2_SME_Zmx2(opcode) => opcode.bits(),
            SME_INT_SD::ADD_SME_ZA_array_off3_0_SME_Znx4(opcode) => opcode.bits(),
            SME_INT_SD::ADD_SME_ZA_array_off3_0_SME_Znx4_SME_Zmx4(opcode) => opcode.bits(),
            SME_INT_SD::ADD_SME_ZA_array_off3_0_SVE_ZnxN_SME_Zm(opcode) => opcode.bits(),
            SME_INT_SD::ADD_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_S_SME_Zm_S_S(opcode) => {
                opcode.bits()
            }
            SME_INT_SD::SDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zmx2(opcode) => opcode.bits(),
            SME_INT_SD::SDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zmx4(opcode) => opcode.bits(),
            SME_INT_SD::SDOT_SME_ZA_array_off3_0_SVE_ZnxN_SME_Zm(opcode) => opcode.bits(),
            SME_INT_SD::SDOT_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_B_SME_Zm_S_B(opcode) => {
                opcode.bits()
            }
            SME_INT_SD::SMLALL_SME_ZA_array_off1x4_SME_Znx2_SME_Zmx2(opcode) => opcode.bits(),
            SME_INT_SD::SMLALL_SME_ZA_array_off1x4_SME_Znx4_SME_Zmx4(opcode) => opcode.bits(),
            SME_INT_SD::SMLALL_SME_ZA_array_off1x4_SVE_ZnxN_SME_Zm(opcode) => opcode.bits(),
            SME_INT_SD::SMLALL_SME_ZA_array_off1x4_S_S_SVE_ZnxN_S_B_SME_Zm_S_B(opcode) => {
                opcode.bits()
            }
            SME_INT_SD::SMLALL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm(opcode) => opcode.bits(),
            SME_INT_SD::SMLSLL_SME_ZA_array_off1x4_SME_Znx2_SME_Zmx2(opcode) => opcode.bits(),
            SME_INT_SD::SMLSLL_SME_ZA_array_off1x4_SME_Znx4_SME_Zmx4(opcode) => opcode.bits(),
            SME_INT_SD::SMLSLL_SME_ZA_array_off1x4_SVE_ZnxN_SME_Zm(opcode) => opcode.bits(),
            SME_INT_SD::SMLSLL_SME_ZA_array_off1x4_S_S_SVE_ZnxN_S_B_SME_Zm_S_B(opcode) => {
                opcode.bits()
            }
            SME_INT_SD::SMLSLL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm(opcode) => opcode.bits(),
            SME_INT_SD::SUB_SME_ZA_array_off3_0_SME_Znx2(opcode) => opcode.bits(),
            SME_INT_SD::SUB_SME_ZA_array_off3_0_SME_Znx2_SME_Zmx2(opcode) => opcode.bits(),
            SME_INT_SD::SUB_SME_ZA_array_off3_0_SME_Znx4(opcode) => opcode.bits(),
            SME_INT_SD::SUB_SME_ZA_array_off3_0_SME_Znx4_SME_Zmx4(opcode) => opcode.bits(),
            SME_INT_SD::SUB_SME_ZA_array_off3_0_SVE_ZnxN_SME_Zm(opcode) => opcode.bits(),
            SME_INT_SD::SUB_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_S_SME_Zm_S_S(opcode) => {
                opcode.bits()
            }
            SME_INT_SD::UDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zmx2(opcode) => opcode.bits(),
            SME_INT_SD::UDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zmx4(opcode) => opcode.bits(),
            SME_INT_SD::UDOT_SME_ZA_array_off3_0_SVE_ZnxN_SME_Zm(opcode) => opcode.bits(),
            SME_INT_SD::UDOT_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_B_SME_Zm_S_B(opcode) => {
                opcode.bits()
            }
            SME_INT_SD::UMLALL_SME_ZA_array_off1x4_SME_Znx2_SME_Zmx2(opcode) => opcode.bits(),
            SME_INT_SD::UMLALL_SME_ZA_array_off1x4_SME_Znx4_SME_Zmx4(opcode) => opcode.bits(),
            SME_INT_SD::UMLALL_SME_ZA_array_off1x4_SVE_ZnxN_SME_Zm(opcode) => opcode.bits(),
            SME_INT_SD::UMLALL_SME_ZA_array_off1x4_S_S_SVE_ZnxN_S_B_SME_Zm_S_B(opcode) => {
                opcode.bits()
            }
            SME_INT_SD::UMLALL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm(opcode) => opcode.bits(),
            SME_INT_SD::UMLSLL_SME_ZA_array_off1x4_SME_Znx2_SME_Zmx2(opcode) => opcode.bits(),
            SME_INT_SD::UMLSLL_SME_ZA_array_off1x4_SME_Znx4_SME_Zmx4(opcode) => opcode.bits(),
            SME_INT_SD::UMLSLL_SME_ZA_array_off1x4_SVE_ZnxN_SME_Zm(opcode) => opcode.bits(),
            SME_INT_SD::UMLSLL_SME_ZA_array_off1x4_S_S_SVE_ZnxN_S_B_SME_Zm_S_B(opcode) => {
                opcode.bits()
            }
            SME_INT_SD::UMLSLL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm(opcode) => opcode.bits(),
        }
    }
}
impl InsnOpcode for FLOATCCMP {
    fn definition(&self) -> &'static Insn {
        match self {
            FLOATCCMP::FCCMPE_Fn_Fm_NZCV_COND(opcode) => opcode.definition(),
            FLOATCCMP::FCCMPE_Fn_S_S_Fm_S_S_NZCV_COND(opcode) => opcode.definition(),
            FLOATCCMP::FCCMP_Fn_Fm_NZCV_COND(opcode) => opcode.definition(),
            FLOATCCMP::FCCMP_Fn_S_S_Fm_S_S_NZCV_COND(opcode) => opcode.definition(),
        }
    }
    fn bits(&self) -> u32 {
        match self {
            FLOATCCMP::FCCMPE_Fn_Fm_NZCV_COND(opcode) => opcode.bits(),
            FLOATCCMP::FCCMPE_Fn_S_S_Fm_S_S_NZCV_COND(opcode) => opcode.bits(),
            FLOATCCMP::FCCMP_Fn_Fm_NZCV_COND(opcode) => opcode.bits(),
            FLOATCCMP::FCCMP_Fn_S_S_Fm_S_S_NZCV_COND(opcode) => opcode.bits(),
        }
    }
}
impl InsnOpcode for SME2_MOVAZ {
    fn definition(&self) -> &'static Insn {
        match self {
            SME2_MOVAZ::MOVAZ_SME_Zdnx2_SME_ZA_array_vrsb_1(opcode) => opcode.definition(),
            SME2_MOVAZ::MOVAZ_SME_Zdnx2_SME_ZA_array_vrsd_1(opcode) => opcode.definition(),
            SME2_MOVAZ::MOVAZ_SME_Zdnx2_SME_ZA_array_vrsh_1(opcode) => opcode.definition(),
            SME2_MOVAZ::MOVAZ_SME_Zdnx2_SME_ZA_array_vrss_1(opcode) => opcode.definition(),
            SME2_MOVAZ::MOVAZ_SME_Zdnx4_SME_ZA_array_vrsb_2(opcode) => opcode.definition(),
            SME2_MOVAZ::MOVAZ_SME_Zdnx4_SME_ZA_array_vrsd_2(opcode) => opcode.definition(),
            SME2_MOVAZ::MOVAZ_SME_Zdnx4_SME_ZA_array_vrsh_2(opcode) => opcode.definition(),
            SME2_MOVAZ::MOVAZ_SME_Zdnx4_SME_ZA_array_vrss_2(opcode) => opcode.definition(),
        }
    }
    fn bits(&self) -> u32 {
        match self {
            SME2_MOVAZ::MOVAZ_SME_Zdnx2_SME_ZA_array_vrsb_1(opcode) => opcode.bits(),
            SME2_MOVAZ::MOVAZ_SME_Zdnx2_SME_ZA_array_vrsd_1(opcode) => opcode.bits(),
            SME2_MOVAZ::MOVAZ_SME_Zdnx2_SME_ZA_array_vrsh_1(opcode) => opcode.bits(),
            SME2_MOVAZ::MOVAZ_SME_Zdnx2_SME_ZA_array_vrss_1(opcode) => opcode.bits(),
            SME2_MOVAZ::MOVAZ_SME_Zdnx4_SME_ZA_array_vrsb_2(opcode) => opcode.bits(),
            SME2_MOVAZ::MOVAZ_SME_Zdnx4_SME_ZA_array_vrsd_2(opcode) => opcode.bits(),
            SME2_MOVAZ::MOVAZ_SME_Zdnx4_SME_ZA_array_vrsh_2(opcode) => opcode.bits(),
            SME2_MOVAZ::MOVAZ_SME_Zdnx4_SME_ZA_array_vrss_2(opcode) => opcode.bits(),
        }
    }
}
impl InsnOpcode for TESTBRANCH {
    fn definition(&self) -> &'static Insn {
        match self {
            TESTBRANCH::TBNZ_Rt_BIT_NUM_ADDR_PCREL14(opcode) => opcode.definition(),
            TESTBRANCH::TBZ_Rt_BIT_NUM_ADDR_PCREL14(opcode) => opcode.definition(),
        }
    }
    fn bits(&self) -> u32 {
        match self {
            TESTBRANCH::TBNZ_Rt_BIT_NUM_ADDR_PCREL14(opcode) => opcode.bits(),
            TESTBRANCH::TBZ_Rt_BIT_NUM_ADDR_PCREL14(opcode) => opcode.bits(),
        }
    }
}
impl InsnOpcode for LDST_REGOFF {
    fn definition(&self) -> &'static Insn {
        match self {
            LDST_REGOFF::LDRB_Rt_ADDR_REGOFF(opcode) => opcode.definition(),
            LDST_REGOFF::LDRH_Rt_ADDR_REGOFF(opcode) => opcode.definition(),
            LDST_REGOFF::LDRSB_Rt_ADDR_REGOFF(opcode) => opcode.definition(),
            LDST_REGOFF::LDRSH_Rt_ADDR_REGOFF(opcode) => opcode.definition(),
            LDST_REGOFF::LDRSW_Rt_ADDR_REGOFF(opcode) => opcode.definition(),
            LDST_REGOFF::LDR_Ft_ADDR_REGOFF(opcode) => opcode.definition(),
            LDST_REGOFF::LDR_Rt_ADDR_REGOFF(opcode) => opcode.definition(),
            LDST_REGOFF::PRFM_PRFOP_ADDR_REGOFF(opcode) => opcode.definition(),
            LDST_REGOFF::STRB_Rt_ADDR_REGOFF(opcode) => opcode.definition(),
            LDST_REGOFF::STRH_Rt_ADDR_REGOFF(opcode) => opcode.definition(),
            LDST_REGOFF::STR_Ft_ADDR_REGOFF(opcode) => opcode.definition(),
            LDST_REGOFF::STR_Rt_ADDR_REGOFF(opcode) => opcode.definition(),
        }
    }
    fn bits(&self) -> u32 {
        match self {
            LDST_REGOFF::LDRB_Rt_ADDR_REGOFF(opcode) => opcode.bits(),
            LDST_REGOFF::LDRH_Rt_ADDR_REGOFF(opcode) => opcode.bits(),
            LDST_REGOFF::LDRSB_Rt_ADDR_REGOFF(opcode) => opcode.bits(),
            LDST_REGOFF::LDRSH_Rt_ADDR_REGOFF(opcode) => opcode.bits(),
            LDST_REGOFF::LDRSW_Rt_ADDR_REGOFF(opcode) => opcode.bits(),
            LDST_REGOFF::LDR_Ft_ADDR_REGOFF(opcode) => opcode.bits(),
            LDST_REGOFF::LDR_Rt_ADDR_REGOFF(opcode) => opcode.bits(),
            LDST_REGOFF::PRFM_PRFOP_ADDR_REGOFF(opcode) => opcode.bits(),
            LDST_REGOFF::STRB_Rt_ADDR_REGOFF(opcode) => opcode.bits(),
            LDST_REGOFF::STRH_Rt_ADDR_REGOFF(opcode) => opcode.bits(),
            LDST_REGOFF::STR_Ft_ADDR_REGOFF(opcode) => opcode.bits(),
            LDST_REGOFF::STR_Rt_ADDR_REGOFF(opcode) => opcode.bits(),
        }
    }
}
impl InsnOpcode for SVE_SIZE_TSZ_BHS {
    fn definition(&self) -> &'static Insn {
        match self {
            SVE_SIZE_TSZ_BHS::SQXTNB_SVE_Zd_SVE_Zn(opcode) => opcode.definition(),
            SVE_SIZE_TSZ_BHS::SQXTNT_SVE_Zd_SVE_Zn(opcode) => opcode.definition(),
            SVE_SIZE_TSZ_BHS::SQXTUNB_SVE_Zd_SVE_Zn(opcode) => opcode.definition(),
            SVE_SIZE_TSZ_BHS::SQXTUNT_SVE_Zd_SVE_Zn(opcode) => opcode.definition(),
            SVE_SIZE_TSZ_BHS::UQXTNB_SVE_Zd_SVE_Zn(opcode) => opcode.definition(),
            SVE_SIZE_TSZ_BHS::UQXTNT_SVE_Zd_SVE_Zn(opcode) => opcode.definition(),
        }
    }
    fn bits(&self) -> u32 {
        match self {
            SVE_SIZE_TSZ_BHS::SQXTNB_SVE_Zd_SVE_Zn(opcode) => opcode.bits(),
            SVE_SIZE_TSZ_BHS::SQXTNT_SVE_Zd_SVE_Zn(opcode) => opcode.bits(),
            SVE_SIZE_TSZ_BHS::SQXTUNB_SVE_Zd_SVE_Zn(opcode) => opcode.bits(),
            SVE_SIZE_TSZ_BHS::SQXTUNT_SVE_Zd_SVE_Zn(opcode) => opcode.bits(),
            SVE_SIZE_TSZ_BHS::UQXTNB_SVE_Zd_SVE_Zn(opcode) => opcode.bits(),
            SVE_SIZE_TSZ_BHS::UQXTNT_SVE_Zd_SVE_Zn(opcode) => opcode.bits(),
        }
    }
}
impl InsnOpcode for ASIMDSHF {
    fn definition(&self) -> &'static Insn {
        match self {
            ASIMDSHF::FCVTZS_Vd_V_2S_Vn_V_2S_IMM_VLSR_V_2S(opcode) => opcode.definition(),
            ASIMDSHF::FCVTZS_Vd_Vn_IMM_VLSR(opcode) => opcode.definition(),
            ASIMDSHF::FCVTZU_Vd_V_2S_Vn_V_2S_IMM_VLSR_V_2S(opcode) => opcode.definition(),
            ASIMDSHF::FCVTZU_Vd_Vn_IMM_VLSR(opcode) => opcode.definition(),
            ASIMDSHF::RSHRN2_Vd_Vn_IMM_VLSR(opcode) => opcode.definition(),
            ASIMDSHF::RSHRN_Vd_Vn_IMM_VLSR(opcode) => opcode.definition(),
            ASIMDSHF::SCVTF_Vd_V_2S_Vn_V_2S_IMM_VLSR_V_2S(opcode) => opcode.definition(),
            ASIMDSHF::SCVTF_Vd_Vn_IMM_VLSR(opcode) => opcode.definition(),
            ASIMDSHF::SHL_Vd_Vn_IMM_VLSL(opcode) => opcode.definition(),
            ASIMDSHF::SHRN2_Vd_Vn_IMM_VLSR(opcode) => opcode.definition(),
            ASIMDSHF::SHRN_Vd_Vn_IMM_VLSR(opcode) => opcode.definition(),
            ASIMDSHF::SLI_Vd_Vn_IMM_VLSL(opcode) => opcode.definition(),
            ASIMDSHF::SQRSHRN2_Vd_Vn_IMM_VLSR(opcode) => opcode.definition(),
            ASIMDSHF::SQRSHRN_Vd_Vn_IMM_VLSR(opcode) => opcode.definition(),
            ASIMDSHF::SQRSHRUN2_Vd_Vn_IMM_VLSR(opcode) => opcode.definition(),
            ASIMDSHF::SQRSHRUN_Vd_Vn_IMM_VLSR(opcode) => opcode.definition(),
            ASIMDSHF::SQSHLU_Vd_Vn_IMM_VLSL(opcode) => opcode.definition(),
            ASIMDSHF::SQSHL_Vd_Vn_IMM_VLSL(opcode) => opcode.definition(),
            ASIMDSHF::SQSHRN2_Vd_Vn_IMM_VLSR(opcode) => opcode.definition(),
            ASIMDSHF::SQSHRN_Vd_Vn_IMM_VLSR(opcode) => opcode.definition(),
            ASIMDSHF::SQSHRUN2_Vd_Vn_IMM_VLSR(opcode) => opcode.definition(),
            ASIMDSHF::SQSHRUN_Vd_Vn_IMM_VLSR(opcode) => opcode.definition(),
            ASIMDSHF::SRI_Vd_Vn_IMM_VLSR(opcode) => opcode.definition(),
            ASIMDSHF::SRSHR_Vd_Vn_IMM_VLSR(opcode) => opcode.definition(),
            ASIMDSHF::SRSRA_Vd_Vn_IMM_VLSR(opcode) => opcode.definition(),
            ASIMDSHF::SSHLL2_Vd_Vn_IMM_VLSL(opcode) => opcode.definition(),
            ASIMDSHF::SSHLL_Vd_Vn_IMM_VLSL(opcode) => opcode.definition(),
            ASIMDSHF::SSHR_Vd_Vn_IMM_VLSR(opcode) => opcode.definition(),
            ASIMDSHF::SSRA_Vd_Vn_IMM_VLSR(opcode) => opcode.definition(),
            ASIMDSHF::UCVTF_Vd_V_2S_Vn_V_2S_IMM_VLSR_V_2S(opcode) => opcode.definition(),
            ASIMDSHF::UCVTF_Vd_Vn_IMM_VLSR(opcode) => opcode.definition(),
            ASIMDSHF::UQRSHRN2_Vd_Vn_IMM_VLSR(opcode) => opcode.definition(),
            ASIMDSHF::UQRSHRN_Vd_Vn_IMM_VLSR(opcode) => opcode.definition(),
            ASIMDSHF::UQSHL_Vd_Vn_IMM_VLSL(opcode) => opcode.definition(),
            ASIMDSHF::UQSHRN2_Vd_Vn_IMM_VLSR(opcode) => opcode.definition(),
            ASIMDSHF::UQSHRN_Vd_Vn_IMM_VLSR(opcode) => opcode.definition(),
            ASIMDSHF::URSHR_Vd_Vn_IMM_VLSR(opcode) => opcode.definition(),
            ASIMDSHF::URSRA_Vd_Vn_IMM_VLSR(opcode) => opcode.definition(),
            ASIMDSHF::USHLL2_Vd_Vn_IMM_VLSL(opcode) => opcode.definition(),
            ASIMDSHF::USHLL_Vd_Vn_IMM_VLSL(opcode) => opcode.definition(),
            ASIMDSHF::USHR_Vd_Vn_IMM_VLSR(opcode) => opcode.definition(),
            ASIMDSHF::USRA_Vd_Vn_IMM_VLSR(opcode) => opcode.definition(),
        }
    }
    fn bits(&self) -> u32 {
        match self {
            ASIMDSHF::FCVTZS_Vd_V_2S_Vn_V_2S_IMM_VLSR_V_2S(opcode) => opcode.bits(),
            ASIMDSHF::FCVTZS_Vd_Vn_IMM_VLSR(opcode) => opcode.bits(),
            ASIMDSHF::FCVTZU_Vd_V_2S_Vn_V_2S_IMM_VLSR_V_2S(opcode) => opcode.bits(),
            ASIMDSHF::FCVTZU_Vd_Vn_IMM_VLSR(opcode) => opcode.bits(),
            ASIMDSHF::RSHRN2_Vd_Vn_IMM_VLSR(opcode) => opcode.bits(),
            ASIMDSHF::RSHRN_Vd_Vn_IMM_VLSR(opcode) => opcode.bits(),
            ASIMDSHF::SCVTF_Vd_V_2S_Vn_V_2S_IMM_VLSR_V_2S(opcode) => opcode.bits(),
            ASIMDSHF::SCVTF_Vd_Vn_IMM_VLSR(opcode) => opcode.bits(),
            ASIMDSHF::SHL_Vd_Vn_IMM_VLSL(opcode) => opcode.bits(),
            ASIMDSHF::SHRN2_Vd_Vn_IMM_VLSR(opcode) => opcode.bits(),
            ASIMDSHF::SHRN_Vd_Vn_IMM_VLSR(opcode) => opcode.bits(),
            ASIMDSHF::SLI_Vd_Vn_IMM_VLSL(opcode) => opcode.bits(),
            ASIMDSHF::SQRSHRN2_Vd_Vn_IMM_VLSR(opcode) => opcode.bits(),
            ASIMDSHF::SQRSHRN_Vd_Vn_IMM_VLSR(opcode) => opcode.bits(),
            ASIMDSHF::SQRSHRUN2_Vd_Vn_IMM_VLSR(opcode) => opcode.bits(),
            ASIMDSHF::SQRSHRUN_Vd_Vn_IMM_VLSR(opcode) => opcode.bits(),
            ASIMDSHF::SQSHLU_Vd_Vn_IMM_VLSL(opcode) => opcode.bits(),
            ASIMDSHF::SQSHL_Vd_Vn_IMM_VLSL(opcode) => opcode.bits(),
            ASIMDSHF::SQSHRN2_Vd_Vn_IMM_VLSR(opcode) => opcode.bits(),
            ASIMDSHF::SQSHRN_Vd_Vn_IMM_VLSR(opcode) => opcode.bits(),
            ASIMDSHF::SQSHRUN2_Vd_Vn_IMM_VLSR(opcode) => opcode.bits(),
            ASIMDSHF::SQSHRUN_Vd_Vn_IMM_VLSR(opcode) => opcode.bits(),
            ASIMDSHF::SRI_Vd_Vn_IMM_VLSR(opcode) => opcode.bits(),
            ASIMDSHF::SRSHR_Vd_Vn_IMM_VLSR(opcode) => opcode.bits(),
            ASIMDSHF::SRSRA_Vd_Vn_IMM_VLSR(opcode) => opcode.bits(),
            ASIMDSHF::SSHLL2_Vd_Vn_IMM_VLSL(opcode) => opcode.bits(),
            ASIMDSHF::SSHLL_Vd_Vn_IMM_VLSL(opcode) => opcode.bits(),
            ASIMDSHF::SSHR_Vd_Vn_IMM_VLSR(opcode) => opcode.bits(),
            ASIMDSHF::SSRA_Vd_Vn_IMM_VLSR(opcode) => opcode.bits(),
            ASIMDSHF::UCVTF_Vd_V_2S_Vn_V_2S_IMM_VLSR_V_2S(opcode) => opcode.bits(),
            ASIMDSHF::UCVTF_Vd_Vn_IMM_VLSR(opcode) => opcode.bits(),
            ASIMDSHF::UQRSHRN2_Vd_Vn_IMM_VLSR(opcode) => opcode.bits(),
            ASIMDSHF::UQRSHRN_Vd_Vn_IMM_VLSR(opcode) => opcode.bits(),
            ASIMDSHF::UQSHL_Vd_Vn_IMM_VLSL(opcode) => opcode.bits(),
            ASIMDSHF::UQSHRN2_Vd_Vn_IMM_VLSR(opcode) => opcode.bits(),
            ASIMDSHF::UQSHRN_Vd_Vn_IMM_VLSR(opcode) => opcode.bits(),
            ASIMDSHF::URSHR_Vd_Vn_IMM_VLSR(opcode) => opcode.bits(),
            ASIMDSHF::URSRA_Vd_Vn_IMM_VLSR(opcode) => opcode.bits(),
            ASIMDSHF::USHLL2_Vd_Vn_IMM_VLSL(opcode) => opcode.bits(),
            ASIMDSHF::USHLL_Vd_Vn_IMM_VLSL(opcode) => opcode.bits(),
            ASIMDSHF::USHR_Vd_Vn_IMM_VLSR(opcode) => opcode.bits(),
            ASIMDSHF::USRA_Vd_Vn_IMM_VLSR(opcode) => opcode.bits(),
        }
    }
}
impl InsnOpcode for LDST_IMM10 {
    fn definition(&self) -> &'static Insn {
        match self {
            LDST_IMM10::LDRAA_Rt_ADDR_SIMM10(opcode) => opcode.definition(),
            LDST_IMM10::LDRAB_Rt_ADDR_SIMM10(opcode) => opcode.definition(),
        }
    }
    fn bits(&self) -> u32 {
        match self {
            LDST_IMM10::LDRAA_Rt_ADDR_SIMM10(opcode) => opcode.bits(),
            LDST_IMM10::LDRAB_Rt_ADDR_SIMM10(opcode) => opcode.bits(),
        }
    }
}
impl InsnOpcode for LOADLIT {
    fn definition(&self) -> &'static Insn {
        match self {
            LOADLIT::LDRSW_Rt_ADDR_PCREL19(opcode) => opcode.definition(),
            LOADLIT::LDR_Ft_ADDR_PCREL19(opcode) => opcode.definition(),
            LOADLIT::LDR_Rt_ADDR_PCREL19(opcode) => opcode.definition(),
            LOADLIT::PRFM_PRFOP_ADDR_PCREL19(opcode) => opcode.definition(),
        }
    }
    fn bits(&self) -> u32 {
        match self {
            LOADLIT::LDRSW_Rt_ADDR_PCREL19(opcode) => opcode.bits(),
            LOADLIT::LDR_Ft_ADDR_PCREL19(opcode) => opcode.bits(),
            LOADLIT::LDR_Rt_ADDR_PCREL19(opcode) => opcode.bits(),
            LOADLIT::PRFM_PRFOP_ADDR_PCREL19(opcode) => opcode.bits(),
        }
    }
}
impl InsnOpcode for ASIMDINS {
    fn definition(&self) -> &'static Insn {
        match self {
            ASIMDINS::DUP_Vd_En(opcode) => opcode.definition(),
            ASIMDINS::DUP_Vd_Rn(opcode) => opcode.definition(),
            ASIMDINS::INS_Ed_En(opcode) => opcode.definition(),
            ASIMDINS::INS_Ed_Rn(opcode) => opcode.definition(),
            ASIMDINS::SMOV_Rd_En(opcode) => opcode.definition(),
            ASIMDINS::UMOV_Rd_En(opcode) => opcode.definition(),
        }
    }
    fn bits(&self) -> u32 {
        match self {
            ASIMDINS::DUP_Vd_En(opcode) => opcode.bits(),
            ASIMDINS::DUP_Vd_Rn(opcode) => opcode.bits(),
            ASIMDINS::INS_Ed_En(opcode) => opcode.bits(),
            ASIMDINS::INS_Ed_Rn(opcode) => opcode.bits(),
            ASIMDINS::SMOV_Rd_En(opcode) => opcode.bits(),
            ASIMDINS::UMOV_Rd_En(opcode) => opcode.bits(),
        }
    }
}
impl InsnOpcode for LDSTPAIR_INDEXED {
    fn definition(&self) -> &'static Insn {
        match self {
            LDSTPAIR_INDEXED::LDPSW_Rt_X_Rt2_X_ADDR_SIMM7_S_S(opcode) => opcode.definition(),
            LDSTPAIR_INDEXED::LDP_Ft_S_S_Ft2_S_S_ADDR_SIMM7_S_S(opcode) => opcode.definition(),
            LDSTPAIR_INDEXED::LDP_Rt_W_Rt2_W_ADDR_SIMM7_S_S(opcode) => opcode.definition(),
            LDSTPAIR_INDEXED::STGP_Rt_X_Rt2_X_ADDR_SIMM11_imm_tag(opcode) => opcode.definition(),
            LDSTPAIR_INDEXED::STP_Ft_S_S_Ft2_S_S_ADDR_SIMM7_S_S(opcode) => opcode.definition(),
            LDSTPAIR_INDEXED::STP_Rt_W_Rt2_W_ADDR_SIMM7_S_S(opcode) => opcode.definition(),
        }
    }
    fn bits(&self) -> u32 {
        match self {
            LDSTPAIR_INDEXED::LDPSW_Rt_X_Rt2_X_ADDR_SIMM7_S_S(opcode) => opcode.bits(),
            LDSTPAIR_INDEXED::LDP_Ft_S_S_Ft2_S_S_ADDR_SIMM7_S_S(opcode) => opcode.bits(),
            LDSTPAIR_INDEXED::LDP_Rt_W_Rt2_W_ADDR_SIMM7_S_S(opcode) => opcode.bits(),
            LDSTPAIR_INDEXED::STGP_Rt_X_Rt2_X_ADDR_SIMM11_imm_tag(opcode) => opcode.bits(),
            LDSTPAIR_INDEXED::STP_Ft_S_S_Ft2_S_S_ADDR_SIMM7_S_S(opcode) => opcode.bits(),
            LDSTPAIR_INDEXED::STP_Rt_W_Rt2_W_ADDR_SIMM7_S_S(opcode) => opcode.bits(),
        }
    }
}
impl InsnOpcode for DP_2SRC {
    fn definition(&self) -> &'static Insn {
        match self {
            DP_2SRC::ASRV_Rd_Rn_Rm(opcode) => opcode.definition(),
            DP_2SRC::CRC32B_Rd_Rn_Rm(opcode) => opcode.definition(),
            DP_2SRC::CRC32CB_Rd_Rn_Rm(opcode) => opcode.definition(),
            DP_2SRC::CRC32CH_Rd_Rn_Rm(opcode) => opcode.definition(),
            DP_2SRC::CRC32CW_Rd_Rn_Rm(opcode) => opcode.definition(),
            DP_2SRC::CRC32CX_Rd_Rn_Rm(opcode) => opcode.definition(),
            DP_2SRC::CRC32H_Rd_Rn_Rm(opcode) => opcode.definition(),
            DP_2SRC::CRC32W_Rd_Rn_Rm(opcode) => opcode.definition(),
            DP_2SRC::CRC32X_Rd_Rn_Rm(opcode) => opcode.definition(),
            DP_2SRC::GMI_Rd_Rn_SP_Rm(opcode) => opcode.definition(),
            DP_2SRC::IRG_Rd_SP_Rn_SP_Rm(opcode) => opcode.definition(),
            DP_2SRC::LSLV_Rd_Rn_Rm(opcode) => opcode.definition(),
            DP_2SRC::LSRV_Rd_Rn_Rm(opcode) => opcode.definition(),
            DP_2SRC::PACGA_Rd_Rn_Rm_SP(opcode) => opcode.definition(),
            DP_2SRC::RORV_Rd_Rn_Rm(opcode) => opcode.definition(),
            DP_2SRC::SDIV_Rd_Rn_Rm(opcode) => opcode.definition(),
            DP_2SRC::SUBPS_Rd_Rn_SP_Rm_SP(opcode) => opcode.definition(),
            DP_2SRC::SUBP_Rd_Rn_SP_Rm_SP(opcode) => opcode.definition(),
            DP_2SRC::UDIV_Rd_Rn_Rm(opcode) => opcode.definition(),
        }
    }
    fn bits(&self) -> u32 {
        match self {
            DP_2SRC::ASRV_Rd_Rn_Rm(opcode) => opcode.bits(),
            DP_2SRC::CRC32B_Rd_Rn_Rm(opcode) => opcode.bits(),
            DP_2SRC::CRC32CB_Rd_Rn_Rm(opcode) => opcode.bits(),
            DP_2SRC::CRC32CH_Rd_Rn_Rm(opcode) => opcode.bits(),
            DP_2SRC::CRC32CW_Rd_Rn_Rm(opcode) => opcode.bits(),
            DP_2SRC::CRC32CX_Rd_Rn_Rm(opcode) => opcode.bits(),
            DP_2SRC::CRC32H_Rd_Rn_Rm(opcode) => opcode.bits(),
            DP_2SRC::CRC32W_Rd_Rn_Rm(opcode) => opcode.bits(),
            DP_2SRC::CRC32X_Rd_Rn_Rm(opcode) => opcode.bits(),
            DP_2SRC::GMI_Rd_Rn_SP_Rm(opcode) => opcode.bits(),
            DP_2SRC::IRG_Rd_SP_Rn_SP_Rm(opcode) => opcode.bits(),
            DP_2SRC::LSLV_Rd_Rn_Rm(opcode) => opcode.bits(),
            DP_2SRC::LSRV_Rd_Rn_Rm(opcode) => opcode.bits(),
            DP_2SRC::PACGA_Rd_Rn_Rm_SP(opcode) => opcode.bits(),
            DP_2SRC::RORV_Rd_Rn_Rm(opcode) => opcode.bits(),
            DP_2SRC::SDIV_Rd_Rn_Rm(opcode) => opcode.bits(),
            DP_2SRC::SUBPS_Rd_Rn_SP_Rm_SP(opcode) => opcode.bits(),
            DP_2SRC::SUBP_Rd_Rn_SP_Rm_SP(opcode) => opcode.bits(),
            DP_2SRC::UDIV_Rd_Rn_Rm(opcode) => opcode.bits(),
        }
    }
}
impl InsnOpcode for COMPBRANCH {
    fn definition(&self) -> &'static Insn {
        match self {
            COMPBRANCH::CBNZ_Rt_ADDR_PCREL19(opcode) => opcode.definition(),
            COMPBRANCH::CBZ_Rt_ADDR_PCREL19(opcode) => opcode.definition(),
        }
    }
    fn bits(&self) -> u32 {
        match self {
            COMPBRANCH::CBNZ_Rt_ADDR_PCREL19(opcode) => opcode.bits(),
            COMPBRANCH::CBZ_Rt_ADDR_PCREL19(opcode) => opcode.bits(),
        }
    }
}
impl InsnOpcode for ASISDSHF {
    fn definition(&self) -> &'static Insn {
        match self {
            ASISDSHF::FCVTZS_Sd_S_S_Sn_S_S_IMM_VLSR_S_S(opcode) => opcode.definition(),
            ASISDSHF::FCVTZS_Sd_Sn_IMM_VLSR(opcode) => opcode.definition(),
            ASISDSHF::FCVTZU_Sd_S_S_Sn_S_S_IMM_VLSR_S_S(opcode) => opcode.definition(),
            ASISDSHF::FCVTZU_Sd_Sn_IMM_VLSR(opcode) => opcode.definition(),
            ASISDSHF::SCVTF_Sd_S_S_Sn_S_S_IMM_VLSR_S_S(opcode) => opcode.definition(),
            ASISDSHF::SCVTF_Sd_Sn_IMM_VLSR(opcode) => opcode.definition(),
            ASISDSHF::SHL_Sd_Sn_IMM_VLSL(opcode) => opcode.definition(),
            ASISDSHF::SLI_Sd_Sn_IMM_VLSL(opcode) => opcode.definition(),
            ASISDSHF::SQRSHRN_Sd_Sn_IMM_VLSR(opcode) => opcode.definition(),
            ASISDSHF::SQRSHRUN_Sd_Sn_IMM_VLSR(opcode) => opcode.definition(),
            ASISDSHF::SQSHLU_Sd_Sn_IMM_VLSL(opcode) => opcode.definition(),
            ASISDSHF::SQSHL_Sd_Sn_IMM_VLSL(opcode) => opcode.definition(),
            ASISDSHF::SQSHRN_Sd_Sn_IMM_VLSR(opcode) => opcode.definition(),
            ASISDSHF::SQSHRUN_Sd_Sn_IMM_VLSR(opcode) => opcode.definition(),
            ASISDSHF::SRI_Sd_Sn_IMM_VLSR(opcode) => opcode.definition(),
            ASISDSHF::SRSHR_Sd_Sn_IMM_VLSR(opcode) => opcode.definition(),
            ASISDSHF::SRSRA_Sd_Sn_IMM_VLSR(opcode) => opcode.definition(),
            ASISDSHF::SSHR_Sd_Sn_IMM_VLSR(opcode) => opcode.definition(),
            ASISDSHF::SSRA_Sd_Sn_IMM_VLSR(opcode) => opcode.definition(),
            ASISDSHF::UCVTF_Sd_S_S_Sn_S_S_IMM_VLSR_S_S(opcode) => opcode.definition(),
            ASISDSHF::UCVTF_Sd_Sn_IMM_VLSR(opcode) => opcode.definition(),
            ASISDSHF::UQRSHRN_Sd_Sn_IMM_VLSR(opcode) => opcode.definition(),
            ASISDSHF::UQSHL_Sd_Sn_IMM_VLSL(opcode) => opcode.definition(),
            ASISDSHF::UQSHRN_Sd_Sn_IMM_VLSR(opcode) => opcode.definition(),
            ASISDSHF::URSHR_Sd_Sn_IMM_VLSR(opcode) => opcode.definition(),
            ASISDSHF::URSRA_Sd_Sn_IMM_VLSR(opcode) => opcode.definition(),
            ASISDSHF::USHR_Sd_Sn_IMM_VLSR(opcode) => opcode.definition(),
            ASISDSHF::USRA_Sd_Sn_IMM_VLSR(opcode) => opcode.definition(),
        }
    }
    fn bits(&self) -> u32 {
        match self {
            ASISDSHF::FCVTZS_Sd_S_S_Sn_S_S_IMM_VLSR_S_S(opcode) => opcode.bits(),
            ASISDSHF::FCVTZS_Sd_Sn_IMM_VLSR(opcode) => opcode.bits(),
            ASISDSHF::FCVTZU_Sd_S_S_Sn_S_S_IMM_VLSR_S_S(opcode) => opcode.bits(),
            ASISDSHF::FCVTZU_Sd_Sn_IMM_VLSR(opcode) => opcode.bits(),
            ASISDSHF::SCVTF_Sd_S_S_Sn_S_S_IMM_VLSR_S_S(opcode) => opcode.bits(),
            ASISDSHF::SCVTF_Sd_Sn_IMM_VLSR(opcode) => opcode.bits(),
            ASISDSHF::SHL_Sd_Sn_IMM_VLSL(opcode) => opcode.bits(),
            ASISDSHF::SLI_Sd_Sn_IMM_VLSL(opcode) => opcode.bits(),
            ASISDSHF::SQRSHRN_Sd_Sn_IMM_VLSR(opcode) => opcode.bits(),
            ASISDSHF::SQRSHRUN_Sd_Sn_IMM_VLSR(opcode) => opcode.bits(),
            ASISDSHF::SQSHLU_Sd_Sn_IMM_VLSL(opcode) => opcode.bits(),
            ASISDSHF::SQSHL_Sd_Sn_IMM_VLSL(opcode) => opcode.bits(),
            ASISDSHF::SQSHRN_Sd_Sn_IMM_VLSR(opcode) => opcode.bits(),
            ASISDSHF::SQSHRUN_Sd_Sn_IMM_VLSR(opcode) => opcode.bits(),
            ASISDSHF::SRI_Sd_Sn_IMM_VLSR(opcode) => opcode.bits(),
            ASISDSHF::SRSHR_Sd_Sn_IMM_VLSR(opcode) => opcode.bits(),
            ASISDSHF::SRSRA_Sd_Sn_IMM_VLSR(opcode) => opcode.bits(),
            ASISDSHF::SSHR_Sd_Sn_IMM_VLSR(opcode) => opcode.bits(),
            ASISDSHF::SSRA_Sd_Sn_IMM_VLSR(opcode) => opcode.bits(),
            ASISDSHF::UCVTF_Sd_S_S_Sn_S_S_IMM_VLSR_S_S(opcode) => opcode.bits(),
            ASISDSHF::UCVTF_Sd_Sn_IMM_VLSR(opcode) => opcode.bits(),
            ASISDSHF::UQRSHRN_Sd_Sn_IMM_VLSR(opcode) => opcode.bits(),
            ASISDSHF::UQSHL_Sd_Sn_IMM_VLSL(opcode) => opcode.bits(),
            ASISDSHF::UQSHRN_Sd_Sn_IMM_VLSR(opcode) => opcode.bits(),
            ASISDSHF::URSHR_Sd_Sn_IMM_VLSR(opcode) => opcode.bits(),
            ASISDSHF::URSRA_Sd_Sn_IMM_VLSR(opcode) => opcode.bits(),
            ASISDSHF::USHR_Sd_Sn_IMM_VLSR(opcode) => opcode.bits(),
            ASISDSHF::USRA_Sd_Sn_IMM_VLSR(opcode) => opcode.bits(),
        }
    }
}
impl InsnOpcode for SME_SIZE_12_HS {
    fn definition(&self) -> &'static Insn {
        match self {
            SME_SIZE_12_HS::LUTI4_SME_Zdnx4_SME_ZT0_SME_Zn_INDEX1_16(opcode) => opcode.definition(),
        }
    }
    fn bits(&self) -> u32 {
        match self {
            SME_SIZE_12_HS::LUTI4_SME_Zdnx4_SME_ZT0_SME_Zn_INDEX1_16(opcode) => opcode.bits(),
        }
    }
}
impl InsnOpcode for IC_SYSTEM {
    fn definition(&self) -> &'static Insn {
        match self {
            IC_SYSTEM::CFINV(opcode) => opcode.definition(),
            IC_SYSTEM::CHKFEAT_X16(opcode) => opcode.definition(),
            IC_SYSTEM::CLREX_UIMM4(opcode) => opcode.definition(),
            IC_SYSTEM::DGH(opcode) => opcode.definition(),
            IC_SYSTEM::DMB_BARRIER(opcode) => opcode.definition(),
            IC_SYSTEM::DSB_BARRIER(opcode) => opcode.definition(),
            IC_SYSTEM::DSB_BARRIER_DSB_NXS(opcode) => opcode.definition(),
            IC_SYSTEM::HINT_UIMM7(opcode) => opcode.definition(),
            IC_SYSTEM::ISB_BARRIER_ISB(opcode) => opcode.definition(),
            IC_SYSTEM::MRRS_Rt_PAIRREG_SYSREG128(opcode) => opcode.definition(),
            IC_SYSTEM::MRS_Rt_SYSREG(opcode) => opcode.definition(),
            IC_SYSTEM::MSRR_SYSREG128_Rt_PAIRREG(opcode) => opcode.definition(),
            IC_SYSTEM::MSR_PSTATEFIELD_UIMM4(opcode) => opcode.definition(),
            IC_SYSTEM::MSR_SYSREG_Rt(opcode) => opcode.definition(),
            IC_SYSTEM::RMIF_Rn_IMM_2_MASK(opcode) => opcode.definition(),
            IC_SYSTEM::SB(opcode) => opcode.definition(),
            IC_SYSTEM::SETF16_Rn(opcode) => opcode.definition(),
            IC_SYSTEM::SETF8_Rn(opcode) => opcode.definition(),
            IC_SYSTEM::SYSL_Rt_UIMM3_OP1_CRn_CRm_UIMM3_OP2(opcode) => opcode.definition(),
            IC_SYSTEM::SYSP_UIMM3_OP1_CRn_CRm_UIMM3_OP2_Rt_PAIRREG_OR_XZR(opcode) => {
                opcode.definition()
            }
            IC_SYSTEM::SYS_UIMM3_OP1_CRn_CRm_UIMM3_OP2_Rt(opcode) => opcode.definition(),
            IC_SYSTEM::WFET_Rd(opcode) => opcode.definition(),
            IC_SYSTEM::WFIT_Rd(opcode) => opcode.definition(),
        }
    }
    fn bits(&self) -> u32 {
        match self {
            IC_SYSTEM::CFINV(opcode) => opcode.bits(),
            IC_SYSTEM::CHKFEAT_X16(opcode) => opcode.bits(),
            IC_SYSTEM::CLREX_UIMM4(opcode) => opcode.bits(),
            IC_SYSTEM::DGH(opcode) => opcode.bits(),
            IC_SYSTEM::DMB_BARRIER(opcode) => opcode.bits(),
            IC_SYSTEM::DSB_BARRIER(opcode) => opcode.bits(),
            IC_SYSTEM::DSB_BARRIER_DSB_NXS(opcode) => opcode.bits(),
            IC_SYSTEM::HINT_UIMM7(opcode) => opcode.bits(),
            IC_SYSTEM::ISB_BARRIER_ISB(opcode) => opcode.bits(),
            IC_SYSTEM::MRRS_Rt_PAIRREG_SYSREG128(opcode) => opcode.bits(),
            IC_SYSTEM::MRS_Rt_SYSREG(opcode) => opcode.bits(),
            IC_SYSTEM::MSRR_SYSREG128_Rt_PAIRREG(opcode) => opcode.bits(),
            IC_SYSTEM::MSR_PSTATEFIELD_UIMM4(opcode) => opcode.bits(),
            IC_SYSTEM::MSR_SYSREG_Rt(opcode) => opcode.bits(),
            IC_SYSTEM::RMIF_Rn_IMM_2_MASK(opcode) => opcode.bits(),
            IC_SYSTEM::SB(opcode) => opcode.bits(),
            IC_SYSTEM::SETF16_Rn(opcode) => opcode.bits(),
            IC_SYSTEM::SETF8_Rn(opcode) => opcode.bits(),
            IC_SYSTEM::SYSL_Rt_UIMM3_OP1_CRn_CRm_UIMM3_OP2(opcode) => opcode.bits(),
            IC_SYSTEM::SYSP_UIMM3_OP1_CRn_CRm_UIMM3_OP2_Rt_PAIRREG_OR_XZR(opcode) => opcode.bits(),
            IC_SYSTEM::SYS_UIMM3_OP1_CRn_CRm_UIMM3_OP2_Rt(opcode) => opcode.bits(),
            IC_SYSTEM::WFET_Rd(opcode) => opcode.bits(),
            IC_SYSTEM::WFIT_Rd(opcode) => opcode.bits(),
        }
    }
}
impl InsnOpcode for FLOATDP3 {
    fn definition(&self) -> &'static Insn {
        match self {
            FLOATDP3::FMADD_Fd_Fn_Fm_Fa(opcode) => opcode.definition(),
            FLOATDP3::FMADD_Fd_S_S_Fn_S_S_Fm_S_S_Fa_S_S(opcode) => opcode.definition(),
            FLOATDP3::FMSUB_Fd_Fn_Fm_Fa(opcode) => opcode.definition(),
            FLOATDP3::FMSUB_Fd_S_S_Fn_S_S_Fm_S_S_Fa_S_S(opcode) => opcode.definition(),
            FLOATDP3::FNMADD_Fd_Fn_Fm_Fa(opcode) => opcode.definition(),
            FLOATDP3::FNMADD_Fd_S_S_Fn_S_S_Fm_S_S_Fa_S_S(opcode) => opcode.definition(),
            FLOATDP3::FNMSUB_Fd_Fn_Fm_Fa(opcode) => opcode.definition(),
            FLOATDP3::FNMSUB_Fd_S_S_Fn_S_S_Fm_S_S_Fa_S_S(opcode) => opcode.definition(),
        }
    }
    fn bits(&self) -> u32 {
        match self {
            FLOATDP3::FMADD_Fd_Fn_Fm_Fa(opcode) => opcode.bits(),
            FLOATDP3::FMADD_Fd_S_S_Fn_S_S_Fm_S_S_Fa_S_S(opcode) => opcode.bits(),
            FLOATDP3::FMSUB_Fd_Fn_Fm_Fa(opcode) => opcode.bits(),
            FLOATDP3::FMSUB_Fd_S_S_Fn_S_S_Fm_S_S_Fa_S_S(opcode) => opcode.bits(),
            FLOATDP3::FNMADD_Fd_Fn_Fm_Fa(opcode) => opcode.bits(),
            FLOATDP3::FNMADD_Fd_S_S_Fn_S_S_Fm_S_S_Fa_S_S(opcode) => opcode.bits(),
            FLOATDP3::FNMSUB_Fd_Fn_Fm_Fa(opcode) => opcode.bits(),
            FLOATDP3::FNMSUB_Fd_S_S_Fn_S_S_Fm_S_S_Fa_S_S(opcode) => opcode.bits(),
        }
    }
}
impl InsnOpcode for SVE2_URQVS {
    fn definition(&self) -> &'static Insn {
        match self {
            SVE2_URQVS::ADDQV_Vd_SVE_Pg3_SVE_Zn(opcode) => opcode.definition(),
            SVE2_URQVS::ANDQV_Vd_SVE_Pg3_SVE_Zn(opcode) => opcode.definition(),
            SVE2_URQVS::EORQV_Vd_SVE_Pg3_SVE_Zn(opcode) => opcode.definition(),
            SVE2_URQVS::FADDQV_Vd_SVE_Pg3_SVE_Zn(opcode) => opcode.definition(),
            SVE2_URQVS::FMAXNMQV_Vd_SVE_Pg3_SVE_Zn(opcode) => opcode.definition(),
            SVE2_URQVS::FMAXQV_Vd_SVE_Pg3_SVE_Zn(opcode) => opcode.definition(),
            SVE2_URQVS::FMINNMQV_Vd_SVE_Pg3_SVE_Zn(opcode) => opcode.definition(),
            SVE2_URQVS::FMINQV_Vd_SVE_Pg3_SVE_Zn(opcode) => opcode.definition(),
            SVE2_URQVS::SMAXQV_Vd_SVE_Pg3_SVE_Zn(opcode) => opcode.definition(),
            SVE2_URQVS::SMINQV_Vd_SVE_Pg3_SVE_Zn(opcode) => opcode.definition(),
            SVE2_URQVS::UMAXQV_Vd_SVE_Pg3_SVE_Zn(opcode) => opcode.definition(),
            SVE2_URQVS::UMINQV_Vd_SVE_Pg3_SVE_Zn(opcode) => opcode.definition(),
        }
    }
    fn bits(&self) -> u32 {
        match self {
            SVE2_URQVS::ADDQV_Vd_SVE_Pg3_SVE_Zn(opcode) => opcode.bits(),
            SVE2_URQVS::ANDQV_Vd_SVE_Pg3_SVE_Zn(opcode) => opcode.bits(),
            SVE2_URQVS::EORQV_Vd_SVE_Pg3_SVE_Zn(opcode) => opcode.bits(),
            SVE2_URQVS::FADDQV_Vd_SVE_Pg3_SVE_Zn(opcode) => opcode.bits(),
            SVE2_URQVS::FMAXNMQV_Vd_SVE_Pg3_SVE_Zn(opcode) => opcode.bits(),
            SVE2_URQVS::FMAXQV_Vd_SVE_Pg3_SVE_Zn(opcode) => opcode.bits(),
            SVE2_URQVS::FMINNMQV_Vd_SVE_Pg3_SVE_Zn(opcode) => opcode.bits(),
            SVE2_URQVS::FMINQV_Vd_SVE_Pg3_SVE_Zn(opcode) => opcode.bits(),
            SVE2_URQVS::SMAXQV_Vd_SVE_Pg3_SVE_Zn(opcode) => opcode.bits(),
            SVE2_URQVS::SMINQV_Vd_SVE_Pg3_SVE_Zn(opcode) => opcode.bits(),
            SVE2_URQVS::UMAXQV_Vd_SVE_Pg3_SVE_Zn(opcode) => opcode.bits(),
            SVE2_URQVS::UMINQV_Vd_SVE_Pg3_SVE_Zn(opcode) => opcode.bits(),
        }
    }
}
impl InsnOpcode for SVE_INDEX {
    fn definition(&self) -> &'static Insn {
        match self {
            SVE_INDEX::DUP_SVE_Zd_SVE_Zn_INDEX(opcode) => opcode.definition(),
        }
    }
    fn bits(&self) -> u32 {
        match self {
            SVE_INDEX::DUP_SVE_Zd_SVE_Zn_INDEX(opcode) => opcode.bits(),
        }
    }
}
impl InsnOpcode for LDST_IMM9 {
    fn definition(&self) -> &'static Insn {
        match self {
            LDST_IMM9::LDRB_Rt_ADDR_SIMM9(opcode) => opcode.definition(),
            LDST_IMM9::LDRH_Rt_ADDR_SIMM9(opcode) => opcode.definition(),
            LDST_IMM9::LDRSB_Rt_ADDR_SIMM9(opcode) => opcode.definition(),
            LDST_IMM9::LDRSH_Rt_ADDR_SIMM9(opcode) => opcode.definition(),
            LDST_IMM9::LDRSW_Rt_ADDR_SIMM9(opcode) => opcode.definition(),
            LDST_IMM9::LDR_Ft_ADDR_SIMM9(opcode) => opcode.definition(),
            LDST_IMM9::LDR_Rt_ADDR_SIMM9(opcode) => opcode.definition(),
            LDST_IMM9::ST2G_Rt_SP_X_ADDR_SIMM13_imm_tag(opcode) => opcode.definition(),
            LDST_IMM9::STG_Rt_SP_X_ADDR_SIMM13_imm_tag(opcode) => opcode.definition(),
            LDST_IMM9::STRB_Rt_ADDR_SIMM9(opcode) => opcode.definition(),
            LDST_IMM9::STRH_Rt_ADDR_SIMM9(opcode) => opcode.definition(),
            LDST_IMM9::STR_Ft_ADDR_SIMM9(opcode) => opcode.definition(),
            LDST_IMM9::STR_Rt_ADDR_SIMM9(opcode) => opcode.definition(),
            LDST_IMM9::STZ2G_Rt_SP_X_ADDR_SIMM13_imm_tag(opcode) => opcode.definition(),
            LDST_IMM9::STZG_Rt_SP_X_ADDR_SIMM13_imm_tag(opcode) => opcode.definition(),
        }
    }
    fn bits(&self) -> u32 {
        match self {
            LDST_IMM9::LDRB_Rt_ADDR_SIMM9(opcode) => opcode.bits(),
            LDST_IMM9::LDRH_Rt_ADDR_SIMM9(opcode) => opcode.bits(),
            LDST_IMM9::LDRSB_Rt_ADDR_SIMM9(opcode) => opcode.bits(),
            LDST_IMM9::LDRSH_Rt_ADDR_SIMM9(opcode) => opcode.bits(),
            LDST_IMM9::LDRSW_Rt_ADDR_SIMM9(opcode) => opcode.bits(),
            LDST_IMM9::LDR_Ft_ADDR_SIMM9(opcode) => opcode.bits(),
            LDST_IMM9::LDR_Rt_ADDR_SIMM9(opcode) => opcode.bits(),
            LDST_IMM9::ST2G_Rt_SP_X_ADDR_SIMM13_imm_tag(opcode) => opcode.bits(),
            LDST_IMM9::STG_Rt_SP_X_ADDR_SIMM13_imm_tag(opcode) => opcode.bits(),
            LDST_IMM9::STRB_Rt_ADDR_SIMM9(opcode) => opcode.bits(),
            LDST_IMM9::STRH_Rt_ADDR_SIMM9(opcode) => opcode.bits(),
            LDST_IMM9::STR_Ft_ADDR_SIMM9(opcode) => opcode.bits(),
            LDST_IMM9::STR_Rt_ADDR_SIMM9(opcode) => opcode.bits(),
            LDST_IMM9::STZ2G_Rt_SP_X_ADDR_SIMM13_imm_tag(opcode) => opcode.bits(),
            LDST_IMM9::STZG_Rt_SP_X_ADDR_SIMM13_imm_tag(opcode) => opcode.bits(),
        }
    }
}
impl InsnOpcode for SME_MOV {
    fn definition(&self) -> &'static Insn {
        match self {
            SME_MOV::MOVA_SME_ZA_HV_idx_dest_SVE_Pg3_SVE_Zn(opcode) => opcode.definition(),
            SME_MOV::MOVA_SVE_Zd_SVE_Pg3_SME_ZA_HV_idx_src(opcode) => opcode.definition(),
            SME_MOV::MOV_SME_ZA_HV_idx_dest_SVE_Pg3_SVE_Zn(opcode) => opcode.definition(),
            SME_MOV::MOV_SVE_Zd_SVE_Pg3_SME_ZA_HV_idx_src(opcode) => opcode.definition(),
        }
    }
    fn bits(&self) -> u32 {
        match self {
            SME_MOV::MOVA_SME_ZA_HV_idx_dest_SVE_Pg3_SVE_Zn(opcode) => opcode.bits(),
            SME_MOV::MOVA_SVE_Zd_SVE_Pg3_SME_ZA_HV_idx_src(opcode) => opcode.bits(),
            SME_MOV::MOV_SME_ZA_HV_idx_dest_SVE_Pg3_SVE_Zn(opcode) => opcode.bits(),
            SME_MOV::MOV_SVE_Zd_SVE_Pg3_SME_ZA_HV_idx_src(opcode) => opcode.bits(),
        }
    }
}
impl InsnOpcode for BRANCH_IMM {
    fn definition(&self) -> &'static Insn {
        match self {
            BRANCH_IMM::BL_ADDR_PCREL26(opcode) => opcode.definition(),
            BRANCH_IMM::B_ADDR_PCREL26(opcode) => opcode.definition(),
        }
    }
    fn bits(&self) -> u32 {
        match self {
            BRANCH_IMM::BL_ADDR_PCREL26(opcode) => opcode.bits(),
            BRANCH_IMM::B_ADDR_PCREL26(opcode) => opcode.bits(),
        }
    }
}
impl InsnOpcode for FLOAT2FIX {
    fn definition(&self) -> &'static Insn {
        match self {
            FLOAT2FIX::FCVTZS_Rd_Fn_FBITS(opcode) => opcode.definition(),
            FLOAT2FIX::FCVTZS_Rd_W_Fn_S_D_FBITS_imm_1_32(opcode) => opcode.definition(),
            FLOAT2FIX::FCVTZU_Rd_Fn_FBITS(opcode) => opcode.definition(),
            FLOAT2FIX::FCVTZU_Rd_W_Fn_S_D_FBITS_imm_1_32(opcode) => opcode.definition(),
            FLOAT2FIX::SCVTF_Fd_Rn_FBITS(opcode) => opcode.definition(),
            FLOAT2FIX::SCVTF_Fd_S_D_Rn_W_FBITS_imm_1_32(opcode) => opcode.definition(),
            FLOAT2FIX::UCVTF_Fd_Rn_FBITS(opcode) => opcode.definition(),
            FLOAT2FIX::UCVTF_Fd_S_D_Rn_W_FBITS_imm_1_32(opcode) => opcode.definition(),
        }
    }
    fn bits(&self) -> u32 {
        match self {
            FLOAT2FIX::FCVTZS_Rd_Fn_FBITS(opcode) => opcode.bits(),
            FLOAT2FIX::FCVTZS_Rd_W_Fn_S_D_FBITS_imm_1_32(opcode) => opcode.bits(),
            FLOAT2FIX::FCVTZU_Rd_Fn_FBITS(opcode) => opcode.bits(),
            FLOAT2FIX::FCVTZU_Rd_W_Fn_S_D_FBITS_imm_1_32(opcode) => opcode.bits(),
            FLOAT2FIX::SCVTF_Fd_Rn_FBITS(opcode) => opcode.bits(),
            FLOAT2FIX::SCVTF_Fd_S_D_Rn_W_FBITS_imm_1_32(opcode) => opcode.bits(),
            FLOAT2FIX::UCVTF_Fd_Rn_FBITS(opcode) => opcode.bits(),
            FLOAT2FIX::UCVTF_Fd_S_D_Rn_W_FBITS_imm_1_32(opcode) => opcode.bits(),
        }
    }
}
impl InsnOpcode for ASISDDIFF {
    fn definition(&self) -> &'static Insn {
        match self {
            ASISDDIFF::SQDMLAL_Sd_Sn_Sm(opcode) => opcode.definition(),
            ASISDDIFF::SQDMLSL_Sd_Sn_Sm(opcode) => opcode.definition(),
            ASISDDIFF::SQDMULL_Sd_Sn_Sm(opcode) => opcode.definition(),
        }
    }
    fn bits(&self) -> u32 {
        match self {
            ASISDDIFF::SQDMLAL_Sd_Sn_Sm(opcode) => opcode.bits(),
            ASISDDIFF::SQDMLSL_Sd_Sn_Sm(opcode) => opcode.bits(),
            ASISDDIFF::SQDMULL_Sd_Sn_Sm(opcode) => opcode.bits(),
        }
    }
}
impl InsnOpcode for ASISDLSE {
    fn definition(&self) -> &'static Insn {
        match self {
            ASISDLSE::LD1_LVt_SIMD_ADDR_SIMPLE(opcode) => opcode.definition(),
            ASISDLSE::LD2_LVt_SIMD_ADDR_SIMPLE(opcode) => opcode.definition(),
            ASISDLSE::LD3_LVt_SIMD_ADDR_SIMPLE(opcode) => opcode.definition(),
            ASISDLSE::LD4_LVt_SIMD_ADDR_SIMPLE(opcode) => opcode.definition(),
            ASISDLSE::ST1_LVt_SIMD_ADDR_SIMPLE(opcode) => opcode.definition(),
            ASISDLSE::ST2_LVt_SIMD_ADDR_SIMPLE(opcode) => opcode.definition(),
            ASISDLSE::ST3_LVt_SIMD_ADDR_SIMPLE(opcode) => opcode.definition(),
            ASISDLSE::ST4_LVt_SIMD_ADDR_SIMPLE(opcode) => opcode.definition(),
        }
    }
    fn bits(&self) -> u32 {
        match self {
            ASISDLSE::LD1_LVt_SIMD_ADDR_SIMPLE(opcode) => opcode.bits(),
            ASISDLSE::LD2_LVt_SIMD_ADDR_SIMPLE(opcode) => opcode.bits(),
            ASISDLSE::LD3_LVt_SIMD_ADDR_SIMPLE(opcode) => opcode.bits(),
            ASISDLSE::LD4_LVt_SIMD_ADDR_SIMPLE(opcode) => opcode.bits(),
            ASISDLSE::ST1_LVt_SIMD_ADDR_SIMPLE(opcode) => opcode.bits(),
            ASISDLSE::ST2_LVt_SIMD_ADDR_SIMPLE(opcode) => opcode.bits(),
            ASISDLSE::ST3_LVt_SIMD_ADDR_SIMPLE(opcode) => opcode.bits(),
            ASISDLSE::ST4_LVt_SIMD_ADDR_SIMPLE(opcode) => opcode.bits(),
        }
    }
}
impl InsnOpcode for SME_STR {
    fn definition(&self) -> &'static Insn {
        match self {
            SME_STR::STR_SME_ZA_array_off4_SME_ADDR_RI_U4xVL(opcode) => opcode.definition(),
        }
    }
    fn bits(&self) -> u32 {
        match self {
            SME_STR::STR_SME_ZA_array_off4_SME_ADDR_RI_U4xVL(opcode) => opcode.bits(),
        }
    }
}
impl InsnOpcode for GCS {
    fn definition(&self) -> &'static Insn {
        match self {
            GCS::GCSPOPCX(opcode) => opcode.definition(),
            GCS::GCSPOPM(opcode) => opcode.definition(),
            GCS::GCSPOPM_Rt(opcode) => opcode.definition(),
            GCS::GCSPOPX(opcode) => opcode.definition(),
            GCS::GCSPUSHM_Rt(opcode) => opcode.definition(),
            GCS::GCSPUSHX(opcode) => opcode.definition(),
            GCS::GCSSS1_Rt(opcode) => opcode.definition(),
            GCS::GCSSS2_Rt(opcode) => opcode.definition(),
            GCS::GCSSTR_Rt_Rn_SP(opcode) => opcode.definition(),
            GCS::GCSSTTR_Rt_Rn_SP(opcode) => opcode.definition(),
        }
    }
    fn bits(&self) -> u32 {
        match self {
            GCS::GCSPOPCX(opcode) => opcode.bits(),
            GCS::GCSPOPM(opcode) => opcode.bits(),
            GCS::GCSPOPM_Rt(opcode) => opcode.bits(),
            GCS::GCSPOPX(opcode) => opcode.bits(),
            GCS::GCSPUSHM_Rt(opcode) => opcode.bits(),
            GCS::GCSPUSHX(opcode) => opcode.bits(),
            GCS::GCSSS1_Rt(opcode) => opcode.bits(),
            GCS::GCSSS2_Rt(opcode) => opcode.bits(),
            GCS::GCSSTR_Rt_Rn_SP(opcode) => opcode.bits(),
            GCS::GCSSTTR_Rt_Rn_SP(opcode) => opcode.bits(),
        }
    }
}
impl InsnOpcode for EXCEPTION {
    fn definition(&self) -> &'static Insn {
        match self {
            EXCEPTION::BRK_EXCEPTION(opcode) => opcode.definition(),
            EXCEPTION::DCPS1_EXCEPTION(opcode) => opcode.definition(),
            EXCEPTION::DCPS2_EXCEPTION(opcode) => opcode.definition(),
            EXCEPTION::DCPS3_EXCEPTION(opcode) => opcode.definition(),
            EXCEPTION::HLT_EXCEPTION(opcode) => opcode.definition(),
            EXCEPTION::HVC_EXCEPTION(opcode) => opcode.definition(),
            EXCEPTION::SMC_EXCEPTION(opcode) => opcode.definition(),
            EXCEPTION::SVC_EXCEPTION(opcode) => opcode.definition(),
            EXCEPTION::UDF_UNDEFINED(opcode) => opcode.definition(),
        }
    }
    fn bits(&self) -> u32 {
        match self {
            EXCEPTION::BRK_EXCEPTION(opcode) => opcode.bits(),
            EXCEPTION::DCPS1_EXCEPTION(opcode) => opcode.bits(),
            EXCEPTION::DCPS2_EXCEPTION(opcode) => opcode.bits(),
            EXCEPTION::DCPS3_EXCEPTION(opcode) => opcode.bits(),
            EXCEPTION::HLT_EXCEPTION(opcode) => opcode.bits(),
            EXCEPTION::HVC_EXCEPTION(opcode) => opcode.bits(),
            EXCEPTION::SMC_EXCEPTION(opcode) => opcode.bits(),
            EXCEPTION::SVC_EXCEPTION(opcode) => opcode.bits(),
            EXCEPTION::UDF_UNDEFINED(opcode) => opcode.bits(),
        }
    }
}
impl InsnOpcode for DOTPRODUCT {
    fn definition(&self) -> &'static Insn {
        match self {
            DOTPRODUCT::BFDOT_Vd_Vn_Em(opcode) => opcode.definition(),
            DOTPRODUCT::SDOT_Vd_Vn_Em(opcode) => opcode.definition(),
            DOTPRODUCT::SDOT_Vd_Vn_Vm(opcode) => opcode.definition(),
            DOTPRODUCT::SUDOT_Vd_Vn_Em(opcode) => opcode.definition(),
            DOTPRODUCT::UDOT_Vd_Vn_Em(opcode) => opcode.definition(),
            DOTPRODUCT::UDOT_Vd_Vn_Vm(opcode) => opcode.definition(),
            DOTPRODUCT::USDOT_Vd_Vn_Em(opcode) => opcode.definition(),
        }
    }
    fn bits(&self) -> u32 {
        match self {
            DOTPRODUCT::BFDOT_Vd_Vn_Em(opcode) => opcode.bits(),
            DOTPRODUCT::SDOT_Vd_Vn_Em(opcode) => opcode.bits(),
            DOTPRODUCT::SDOT_Vd_Vn_Vm(opcode) => opcode.bits(),
            DOTPRODUCT::SUDOT_Vd_Vn_Em(opcode) => opcode.bits(),
            DOTPRODUCT::UDOT_Vd_Vn_Em(opcode) => opcode.bits(),
            DOTPRODUCT::UDOT_Vd_Vn_Vm(opcode) => opcode.bits(),
            DOTPRODUCT::USDOT_Vd_Vn_Em(opcode) => opcode.bits(),
        }
    }
}
impl InsnOpcode for BRANCH_REG {
    fn definition(&self) -> &'static Insn {
        match self {
            BRANCH_REG::BLRAAZ_Rn(opcode) => opcode.definition(),
            BRANCH_REG::BLRAA_Rn_Rd_SP(opcode) => opcode.definition(),
            BRANCH_REG::BLRABZ_Rn(opcode) => opcode.definition(),
            BRANCH_REG::BLRAB_Rn_Rd_SP(opcode) => opcode.definition(),
            BRANCH_REG::BLR_Rn(opcode) => opcode.definition(),
            BRANCH_REG::BRAAZ_Rn(opcode) => opcode.definition(),
            BRANCH_REG::BRAA_Rn_Rd_SP(opcode) => opcode.definition(),
            BRANCH_REG::BRABZ_Rn(opcode) => opcode.definition(),
            BRANCH_REG::BRAB_Rn_Rd_SP(opcode) => opcode.definition(),
            BRANCH_REG::BR_Rn(opcode) => opcode.definition(),
            BRANCH_REG::DRPS(opcode) => opcode.definition(),
            BRANCH_REG::ERET(opcode) => opcode.definition(),
            BRANCH_REG::ERETAA(opcode) => opcode.definition(),
            BRANCH_REG::ERETAB(opcode) => opcode.definition(),
            BRANCH_REG::RETAA(opcode) => opcode.definition(),
            BRANCH_REG::RETAB(opcode) => opcode.definition(),
            BRANCH_REG::RET_Rn(opcode) => opcode.definition(),
        }
    }
    fn bits(&self) -> u32 {
        match self {
            BRANCH_REG::BLRAAZ_Rn(opcode) => opcode.bits(),
            BRANCH_REG::BLRAA_Rn_Rd_SP(opcode) => opcode.bits(),
            BRANCH_REG::BLRABZ_Rn(opcode) => opcode.bits(),
            BRANCH_REG::BLRAB_Rn_Rd_SP(opcode) => opcode.bits(),
            BRANCH_REG::BLR_Rn(opcode) => opcode.bits(),
            BRANCH_REG::BRAAZ_Rn(opcode) => opcode.bits(),
            BRANCH_REG::BRAA_Rn_Rd_SP(opcode) => opcode.bits(),
            BRANCH_REG::BRABZ_Rn(opcode) => opcode.bits(),
            BRANCH_REG::BRAB_Rn_Rd_SP(opcode) => opcode.bits(),
            BRANCH_REG::BR_Rn(opcode) => opcode.bits(),
            BRANCH_REG::DRPS(opcode) => opcode.bits(),
            BRANCH_REG::ERET(opcode) => opcode.bits(),
            BRANCH_REG::ERETAA(opcode) => opcode.bits(),
            BRANCH_REG::ERETAB(opcode) => opcode.bits(),
            BRANCH_REG::RETAA(opcode) => opcode.bits(),
            BRANCH_REG::RETAB(opcode) => opcode.bits(),
            BRANCH_REG::RET_Rn(opcode) => opcode.bits(),
        }
    }
}
impl InsnOpcode for SVE_SIZE_13 {
    fn definition(&self) -> &'static Insn {
        match self {
            SVE_SIZE_13::PMULLB_SVE_Zd_S_H_SVE_Zn_S_B_SVE_Zm_16_S_B(opcode) => opcode.definition(),
            SVE_SIZE_13::PMULLT_SVE_Zd_S_H_SVE_Zn_S_B_SVE_Zm_16_S_B(opcode) => opcode.definition(),
        }
    }
    fn bits(&self) -> u32 {
        match self {
            SVE_SIZE_13::PMULLB_SVE_Zd_S_H_SVE_Zn_S_B_SVE_Zm_16_S_B(opcode) => opcode.bits(),
            SVE_SIZE_13::PMULLT_SVE_Zd_S_H_SVE_Zn_S_B_SVE_Zm_16_S_B(opcode) => opcode.bits(),
        }
    }
}
impl InsnOpcode for LDSTEXCL {
    fn definition(&self) -> &'static Insn {
        match self {
            LDSTEXCL::LDAPRB_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LDSTEXCL::LDAPRH_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LDSTEXCL::LDAPR_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LDSTEXCL::LDARB_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LDSTEXCL::LDARH_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LDSTEXCL::LDAR_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LDSTEXCL::LDAXP_Rt_Rt2_ADDR_SIMPLE(opcode) => opcode.definition(),
            LDSTEXCL::LDAXRB_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LDSTEXCL::LDAXRH_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LDSTEXCL::LDAXR_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LDSTEXCL::LDGM_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LDSTEXCL::LDLARB_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LDSTEXCL::LDLARH_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LDSTEXCL::LDLAR_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LDSTEXCL::LDXP_Rt_Rt2_ADDR_SIMPLE(opcode) => opcode.definition(),
            LDSTEXCL::LDXRB_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LDSTEXCL::LDXRH_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LDSTEXCL::LDXR_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LDSTEXCL::STGM_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LDSTEXCL::STLLRB_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LDSTEXCL::STLLRH_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LDSTEXCL::STLLR_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LDSTEXCL::STLRB_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LDSTEXCL::STLRH_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LDSTEXCL::STLR_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LDSTEXCL::STLXP_Rs_Rt_Rt2_ADDR_SIMPLE(opcode) => opcode.definition(),
            LDSTEXCL::STLXRB_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LDSTEXCL::STLXRH_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LDSTEXCL::STLXR_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LDSTEXCL::STXP_Rs_Rt_Rt2_ADDR_SIMPLE(opcode) => opcode.definition(),
            LDSTEXCL::STXRB_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LDSTEXCL::STXRH_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LDSTEXCL::STXR_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
            LDSTEXCL::STZGM_Rt_ADDR_SIMPLE(opcode) => opcode.definition(),
        }
    }
    fn bits(&self) -> u32 {
        match self {
            LDSTEXCL::LDAPRB_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LDSTEXCL::LDAPRH_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LDSTEXCL::LDAPR_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LDSTEXCL::LDARB_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LDSTEXCL::LDARH_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LDSTEXCL::LDAR_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LDSTEXCL::LDAXP_Rt_Rt2_ADDR_SIMPLE(opcode) => opcode.bits(),
            LDSTEXCL::LDAXRB_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LDSTEXCL::LDAXRH_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LDSTEXCL::LDAXR_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LDSTEXCL::LDGM_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LDSTEXCL::LDLARB_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LDSTEXCL::LDLARH_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LDSTEXCL::LDLAR_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LDSTEXCL::LDXP_Rt_Rt2_ADDR_SIMPLE(opcode) => opcode.bits(),
            LDSTEXCL::LDXRB_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LDSTEXCL::LDXRH_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LDSTEXCL::LDXR_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LDSTEXCL::STGM_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LDSTEXCL::STLLRB_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LDSTEXCL::STLLRH_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LDSTEXCL::STLLR_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LDSTEXCL::STLRB_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LDSTEXCL::STLRH_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LDSTEXCL::STLR_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LDSTEXCL::STLXP_Rs_Rt_Rt2_ADDR_SIMPLE(opcode) => opcode.bits(),
            LDSTEXCL::STLXRB_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LDSTEXCL::STLXRH_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LDSTEXCL::STLXR_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LDSTEXCL::STXP_Rs_Rt_Rt2_ADDR_SIMPLE(opcode) => opcode.bits(),
            LDSTEXCL::STXRB_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LDSTEXCL::STXRH_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LDSTEXCL::STXR_Rs_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
            LDSTEXCL::STZGM_Rt_ADDR_SIMPLE(opcode) => opcode.bits(),
        }
    }
}
impl InsnOpcode for LDST_UNPRIV {
    fn definition(&self) -> &'static Insn {
        match self {
            LDST_UNPRIV::LDTRB_Rt_ADDR_SIMM9(opcode) => opcode.definition(),
            LDST_UNPRIV::LDTRH_Rt_ADDR_SIMM9(opcode) => opcode.definition(),
            LDST_UNPRIV::LDTRSB_Rt_ADDR_SIMM9(opcode) => opcode.definition(),
            LDST_UNPRIV::LDTRSH_Rt_ADDR_SIMM9(opcode) => opcode.definition(),
            LDST_UNPRIV::LDTRSW_Rt_ADDR_SIMM9(opcode) => opcode.definition(),
            LDST_UNPRIV::LDTR_Rt_ADDR_SIMM9(opcode) => opcode.definition(),
            LDST_UNPRIV::STTRB_Rt_ADDR_SIMM9(opcode) => opcode.definition(),
            LDST_UNPRIV::STTRH_Rt_ADDR_SIMM9(opcode) => opcode.definition(),
            LDST_UNPRIV::STTR_Rt_ADDR_SIMM9(opcode) => opcode.definition(),
        }
    }
    fn bits(&self) -> u32 {
        match self {
            LDST_UNPRIV::LDTRB_Rt_ADDR_SIMM9(opcode) => opcode.bits(),
            LDST_UNPRIV::LDTRH_Rt_ADDR_SIMM9(opcode) => opcode.bits(),
            LDST_UNPRIV::LDTRSB_Rt_ADDR_SIMM9(opcode) => opcode.bits(),
            LDST_UNPRIV::LDTRSH_Rt_ADDR_SIMM9(opcode) => opcode.bits(),
            LDST_UNPRIV::LDTRSW_Rt_ADDR_SIMM9(opcode) => opcode.bits(),
            LDST_UNPRIV::LDTR_Rt_ADDR_SIMM9(opcode) => opcode.bits(),
            LDST_UNPRIV::STTRB_Rt_ADDR_SIMM9(opcode) => opcode.bits(),
            LDST_UNPRIV::STTRH_Rt_ADDR_SIMM9(opcode) => opcode.bits(),
            LDST_UNPRIV::STTR_Rt_ADDR_SIMM9(opcode) => opcode.bits(),
        }
    }
}
impl InsnOpcode for FLOATIMM {
    fn definition(&self) -> &'static Insn {
        match self {
            FLOATIMM::FMOV_Fd_FPIMM(opcode) => opcode.definition(),
            FLOATIMM::FMOV_Fd_S_S_FPIMM(opcode) => opcode.definition(),
        }
    }
    fn bits(&self) -> u32 {
        match self {
            FLOATIMM::FMOV_Fd_FPIMM(opcode) => opcode.bits(),
            FLOATIMM::FMOV_Fd_S_S_FPIMM(opcode) => opcode.bits(),
        }
    }
}
impl InsnOpcode for SVE_MOVPRFX {
    fn definition(&self) -> &'static Insn {
        match self {
            SVE_MOVPRFX::MOVPRFX_SVE_Zd_SVE_Pg3_SVE_Zn(opcode) => opcode.definition(),
        }
    }
    fn bits(&self) -> u32 {
        match self {
            SVE_MOVPRFX::MOVPRFX_SVE_Zd_SVE_Pg3_SVE_Zn(opcode) => opcode.bits(),
        }
    }
}
impl InsnOpcode for ASISDLSEP {
    fn definition(&self) -> &'static Insn {
        match self {
            ASISDLSEP::LD1_LVt_SIMD_ADDR_POST(opcode) => opcode.definition(),
            ASISDLSEP::LD2_LVt_SIMD_ADDR_POST(opcode) => opcode.definition(),
            ASISDLSEP::LD3_LVt_SIMD_ADDR_POST(opcode) => opcode.definition(),
            ASISDLSEP::LD4_LVt_SIMD_ADDR_POST(opcode) => opcode.definition(),
            ASISDLSEP::ST1_LVt_SIMD_ADDR_POST(opcode) => opcode.definition(),
            ASISDLSEP::ST2_LVt_SIMD_ADDR_POST(opcode) => opcode.definition(),
            ASISDLSEP::ST3_LVt_SIMD_ADDR_POST(opcode) => opcode.definition(),
            ASISDLSEP::ST4_LVt_SIMD_ADDR_POST(opcode) => opcode.definition(),
        }
    }
    fn bits(&self) -> u32 {
        match self {
            ASISDLSEP::LD1_LVt_SIMD_ADDR_POST(opcode) => opcode.bits(),
            ASISDLSEP::LD2_LVt_SIMD_ADDR_POST(opcode) => opcode.bits(),
            ASISDLSEP::LD3_LVt_SIMD_ADDR_POST(opcode) => opcode.bits(),
            ASISDLSEP::LD4_LVt_SIMD_ADDR_POST(opcode) => opcode.bits(),
            ASISDLSEP::ST1_LVt_SIMD_ADDR_POST(opcode) => opcode.bits(),
            ASISDLSEP::ST2_LVt_SIMD_ADDR_POST(opcode) => opcode.bits(),
            ASISDLSEP::ST3_LVt_SIMD_ADDR_POST(opcode) => opcode.bits(),
            ASISDLSEP::ST4_LVt_SIMD_ADDR_POST(opcode) => opcode.bits(),
        }
    }
}
impl InsnOpcode for RCPC3 {
    fn definition(&self) -> &'static Insn {
        match self {
            RCPC3::LDAP1_LEt_SIMD_ADDR_SIMPLE(opcode) => opcode.definition(),
            RCPC3::LDAPR_Rt_RCPC3_ADDR_POSTIND(opcode) => opcode.definition(),
            RCPC3::LDAPUR_Ft_RCPC3_ADDR_OFFSET(opcode) => opcode.definition(),
            RCPC3::LDIAPP_Rt_Rs_RCPC3_ADDR_OPT_POSTIND(opcode) => opcode.definition(),
            RCPC3::STILP_Rt_Rs_RCPC3_ADDR_OPT_PREIND_WB(opcode) => opcode.definition(),
            RCPC3::STL1_LEt_SIMD_ADDR_SIMPLE(opcode) => opcode.definition(),
            RCPC3::STLR_Rt_RCPC3_ADDR_PREIND_WB(opcode) => opcode.definition(),
            RCPC3::STLUR_Ft_RCPC3_ADDR_OFFSET(opcode) => opcode.definition(),
        }
    }
    fn bits(&self) -> u32 {
        match self {
            RCPC3::LDAP1_LEt_SIMD_ADDR_SIMPLE(opcode) => opcode.bits(),
            RCPC3::LDAPR_Rt_RCPC3_ADDR_POSTIND(opcode) => opcode.bits(),
            RCPC3::LDAPUR_Ft_RCPC3_ADDR_OFFSET(opcode) => opcode.bits(),
            RCPC3::LDIAPP_Rt_Rs_RCPC3_ADDR_OPT_POSTIND(opcode) => opcode.bits(),
            RCPC3::STILP_Rt_Rs_RCPC3_ADDR_OPT_PREIND_WB(opcode) => opcode.bits(),
            RCPC3::STL1_LEt_SIMD_ADDR_SIMPLE(opcode) => opcode.bits(),
            RCPC3::STLR_Rt_RCPC3_ADDR_PREIND_WB(opcode) => opcode.bits(),
            RCPC3::STLUR_Ft_RCPC3_ADDR_OFFSET(opcode) => opcode.bits(),
        }
    }
}
impl InsnOpcode for SVE_PRED_ZM {
    fn definition(&self) -> &'static Insn {
        match self {
            SVE_PRED_ZM::BRKA_SVE_Pd_SVE_Pg4_10_SVE_Pn(opcode) => opcode.definition(),
            SVE_PRED_ZM::BRKB_SVE_Pd_SVE_Pg4_10_SVE_Pn(opcode) => opcode.definition(),
        }
    }
    fn bits(&self) -> u32 {
        match self {
            SVE_PRED_ZM::BRKA_SVE_Pd_SVE_Pg4_10_SVE_Pn(opcode) => opcode.bits(),
            SVE_PRED_ZM::BRKB_SVE_Pd_SVE_Pg4_10_SVE_Pn(opcode) => opcode.bits(),
        }
    }
}
impl InsnOpcode for SME_SIZE_12_BHS {
    fn definition(&self) -> &'static Insn {
        match self {
            SME_SIZE_12_BHS::LUTI2_SME_Zdnx2_SME_ZT0_SME_Zn_INDEX3_15(opcode) => {
                opcode.definition()
            }
            SME_SIZE_12_BHS::LUTI2_SME_Zdnx4_SME_ZT0_SME_Zn_INDEX2_16(opcode) => {
                opcode.definition()
            }
            SME_SIZE_12_BHS::LUTI2_SVE_Zd_SME_ZT0_SME_Zn_INDEX4_14(opcode) => opcode.definition(),
            SME_SIZE_12_BHS::LUTI4_SME_Zdnx2_SME_ZT0_SME_Zn_INDEX2_15(opcode) => {
                opcode.definition()
            }
            SME_SIZE_12_BHS::LUTI4_SVE_Zd_SME_ZT0_SME_Zn_INDEX3_14(opcode) => opcode.definition(),
        }
    }
    fn bits(&self) -> u32 {
        match self {
            SME_SIZE_12_BHS::LUTI2_SME_Zdnx2_SME_ZT0_SME_Zn_INDEX3_15(opcode) => opcode.bits(),
            SME_SIZE_12_BHS::LUTI2_SME_Zdnx4_SME_ZT0_SME_Zn_INDEX2_16(opcode) => opcode.bits(),
            SME_SIZE_12_BHS::LUTI2_SVE_Zd_SME_ZT0_SME_Zn_INDEX4_14(opcode) => opcode.bits(),
            SME_SIZE_12_BHS::LUTI4_SME_Zdnx2_SME_ZT0_SME_Zn_INDEX2_15(opcode) => opcode.bits(),
            SME_SIZE_12_BHS::LUTI4_SVE_Zd_SME_ZT0_SME_Zn_INDEX3_14(opcode) => opcode.bits(),
        }
    }
}
impl InsnOpcode for FLOATSEL {
    fn definition(&self) -> &'static Insn {
        match self {
            FLOATSEL::FCSEL_Fd_Fn_Fm_COND(opcode) => opcode.definition(),
            FLOATSEL::FCSEL_Fd_S_S_Fn_S_S_Fm_S_S_COND(opcode) => opcode.definition(),
        }
    }
    fn bits(&self) -> u32 {
        match self {
            FLOATSEL::FCSEL_Fd_Fn_Fm_COND(opcode) => opcode.bits(),
            FLOATSEL::FCSEL_Fd_S_S_Fn_S_S_Fm_S_S_COND(opcode) => opcode.bits(),
        }
    }
}
impl InsnOpcode for SVE_INDEX1 {
    fn definition(&self) -> &'static Insn {
        match self {
            SVE_INDEX1::DUPQ_SVE_Zd_SVE_Zn_5_INDEX(opcode) => opcode.definition(),
        }
    }
    fn bits(&self) -> u32 {
        match self {
            SVE_INDEX1::DUPQ_SVE_Zd_SVE_Zn_5_INDEX(opcode) => opcode.bits(),
        }
    }
}
impl InsnOpcode for ASISDMISC {
    fn definition(&self) -> &'static Insn {
        match self {
            ASISDMISC::ABS_Sd_Sn(opcode) => opcode.definition(),
            ASISDMISC::CMEQ_Sd_Sn_IMM0(opcode) => opcode.definition(),
            ASISDMISC::CMGE_Sd_Sn_IMM0(opcode) => opcode.definition(),
            ASISDMISC::CMGT_Sd_Sn_IMM0(opcode) => opcode.definition(),
            ASISDMISC::CMLE_Sd_Sn_IMM0(opcode) => opcode.definition(),
            ASISDMISC::CMLT_Sd_Sn_IMM0(opcode) => opcode.definition(),
            ASISDMISC::FCMEQ_Sd_S_H_Sn_S_H_FPIMM0(opcode) => opcode.definition(),
            ASISDMISC::FCMEQ_Sd_Sn_FPIMM0(opcode) => opcode.definition(),
            ASISDMISC::FCMGE_Sd_S_H_Sn_S_H_FPIMM0(opcode) => opcode.definition(),
            ASISDMISC::FCMGE_Sd_Sn_FPIMM0(opcode) => opcode.definition(),
            ASISDMISC::FCMGT_Sd_S_H_Sn_S_H_FPIMM0(opcode) => opcode.definition(),
            ASISDMISC::FCMGT_Sd_Sn_FPIMM0(opcode) => opcode.definition(),
            ASISDMISC::FCMLE_Sd_S_H_Sn_S_H_FPIMM0(opcode) => opcode.definition(),
            ASISDMISC::FCMLE_Sd_Sn_FPIMM0(opcode) => opcode.definition(),
            ASISDMISC::FCMLT_Sd_S_H_Sn_S_H_FPIMM0(opcode) => opcode.definition(),
            ASISDMISC::FCMLT_Sd_Sn_FPIMM0(opcode) => opcode.definition(),
            ASISDMISC::FCVTAS_Sd_S_H_Sn_S_H(opcode) => opcode.definition(),
            ASISDMISC::FCVTAS_Sd_Sn(opcode) => opcode.definition(),
            ASISDMISC::FCVTAU_Sd_S_H_Sn_S_H(opcode) => opcode.definition(),
            ASISDMISC::FCVTAU_Sd_Sn(opcode) => opcode.definition(),
            ASISDMISC::FCVTMS_Sd_S_H_Sn_S_H(opcode) => opcode.definition(),
            ASISDMISC::FCVTMS_Sd_Sn(opcode) => opcode.definition(),
            ASISDMISC::FCVTMU_Sd_S_H_Sn_S_H(opcode) => opcode.definition(),
            ASISDMISC::FCVTMU_Sd_Sn(opcode) => opcode.definition(),
            ASISDMISC::FCVTNS_Sd_S_H_Sn_S_H(opcode) => opcode.definition(),
            ASISDMISC::FCVTNS_Sd_Sn(opcode) => opcode.definition(),
            ASISDMISC::FCVTNU_Sd_S_H_Sn_S_H(opcode) => opcode.definition(),
            ASISDMISC::FCVTNU_Sd_Sn(opcode) => opcode.definition(),
            ASISDMISC::FCVTPS_Sd_S_H_Sn_S_H(opcode) => opcode.definition(),
            ASISDMISC::FCVTPS_Sd_Sn(opcode) => opcode.definition(),
            ASISDMISC::FCVTPU_Sd_S_H_Sn_S_H(opcode) => opcode.definition(),
            ASISDMISC::FCVTPU_Sd_Sn(opcode) => opcode.definition(),
            ASISDMISC::FCVTXN_Sd_Sn(opcode) => opcode.definition(),
            ASISDMISC::FCVTZS_Sd_S_H_Sn_S_H(opcode) => opcode.definition(),
            ASISDMISC::FCVTZS_Sd_Sn(opcode) => opcode.definition(),
            ASISDMISC::FCVTZU_Sd_S_H_Sn_S_H(opcode) => opcode.definition(),
            ASISDMISC::FCVTZU_Sd_Sn(opcode) => opcode.definition(),
            ASISDMISC::FRECPE_Sd_S_H_Sn_S_H(opcode) => opcode.definition(),
            ASISDMISC::FRECPE_Sd_Sn(opcode) => opcode.definition(),
            ASISDMISC::FRECPX_Sd_S_H_Sn_S_H(opcode) => opcode.definition(),
            ASISDMISC::FRECPX_Sd_Sn(opcode) => opcode.definition(),
            ASISDMISC::FRSQRTE_Sd_S_H_Sn_S_H(opcode) => opcode.definition(),
            ASISDMISC::FRSQRTE_Sd_Sn(opcode) => opcode.definition(),
            ASISDMISC::NEG_Sd_Sn(opcode) => opcode.definition(),
            ASISDMISC::SCVTF_Sd_S_H_Sn_S_H(opcode) => opcode.definition(),
            ASISDMISC::SCVTF_Sd_Sn(opcode) => opcode.definition(),
            ASISDMISC::SQABS_Sd_Sn(opcode) => opcode.definition(),
            ASISDMISC::SQNEG_Sd_Sn(opcode) => opcode.definition(),
            ASISDMISC::SQXTN_Sd_Sn(opcode) => opcode.definition(),
            ASISDMISC::SQXTUN_Sd_Sn(opcode) => opcode.definition(),
            ASISDMISC::SUQADD_Sd_Sn(opcode) => opcode.definition(),
            ASISDMISC::UCVTF_Sd_S_H_Sn_S_H(opcode) => opcode.definition(),
            ASISDMISC::UCVTF_Sd_Sn(opcode) => opcode.definition(),
            ASISDMISC::UQXTN_Sd_Sn(opcode) => opcode.definition(),
            ASISDMISC::USQADD_Sd_Sn(opcode) => opcode.definition(),
        }
    }
    fn bits(&self) -> u32 {
        match self {
            ASISDMISC::ABS_Sd_Sn(opcode) => opcode.bits(),
            ASISDMISC::CMEQ_Sd_Sn_IMM0(opcode) => opcode.bits(),
            ASISDMISC::CMGE_Sd_Sn_IMM0(opcode) => opcode.bits(),
            ASISDMISC::CMGT_Sd_Sn_IMM0(opcode) => opcode.bits(),
            ASISDMISC::CMLE_Sd_Sn_IMM0(opcode) => opcode.bits(),
            ASISDMISC::CMLT_Sd_Sn_IMM0(opcode) => opcode.bits(),
            ASISDMISC::FCMEQ_Sd_S_H_Sn_S_H_FPIMM0(opcode) => opcode.bits(),
            ASISDMISC::FCMEQ_Sd_Sn_FPIMM0(opcode) => opcode.bits(),
            ASISDMISC::FCMGE_Sd_S_H_Sn_S_H_FPIMM0(opcode) => opcode.bits(),
            ASISDMISC::FCMGE_Sd_Sn_FPIMM0(opcode) => opcode.bits(),
            ASISDMISC::FCMGT_Sd_S_H_Sn_S_H_FPIMM0(opcode) => opcode.bits(),
            ASISDMISC::FCMGT_Sd_Sn_FPIMM0(opcode) => opcode.bits(),
            ASISDMISC::FCMLE_Sd_S_H_Sn_S_H_FPIMM0(opcode) => opcode.bits(),
            ASISDMISC::FCMLE_Sd_Sn_FPIMM0(opcode) => opcode.bits(),
            ASISDMISC::FCMLT_Sd_S_H_Sn_S_H_FPIMM0(opcode) => opcode.bits(),
            ASISDMISC::FCMLT_Sd_Sn_FPIMM0(opcode) => opcode.bits(),
            ASISDMISC::FCVTAS_Sd_S_H_Sn_S_H(opcode) => opcode.bits(),
            ASISDMISC::FCVTAS_Sd_Sn(opcode) => opcode.bits(),
            ASISDMISC::FCVTAU_Sd_S_H_Sn_S_H(opcode) => opcode.bits(),
            ASISDMISC::FCVTAU_Sd_Sn(opcode) => opcode.bits(),
            ASISDMISC::FCVTMS_Sd_S_H_Sn_S_H(opcode) => opcode.bits(),
            ASISDMISC::FCVTMS_Sd_Sn(opcode) => opcode.bits(),
            ASISDMISC::FCVTMU_Sd_S_H_Sn_S_H(opcode) => opcode.bits(),
            ASISDMISC::FCVTMU_Sd_Sn(opcode) => opcode.bits(),
            ASISDMISC::FCVTNS_Sd_S_H_Sn_S_H(opcode) => opcode.bits(),
            ASISDMISC::FCVTNS_Sd_Sn(opcode) => opcode.bits(),
            ASISDMISC::FCVTNU_Sd_S_H_Sn_S_H(opcode) => opcode.bits(),
            ASISDMISC::FCVTNU_Sd_Sn(opcode) => opcode.bits(),
            ASISDMISC::FCVTPS_Sd_S_H_Sn_S_H(opcode) => opcode.bits(),
            ASISDMISC::FCVTPS_Sd_Sn(opcode) => opcode.bits(),
            ASISDMISC::FCVTPU_Sd_S_H_Sn_S_H(opcode) => opcode.bits(),
            ASISDMISC::FCVTPU_Sd_Sn(opcode) => opcode.bits(),
            ASISDMISC::FCVTXN_Sd_Sn(opcode) => opcode.bits(),
            ASISDMISC::FCVTZS_Sd_S_H_Sn_S_H(opcode) => opcode.bits(),
            ASISDMISC::FCVTZS_Sd_Sn(opcode) => opcode.bits(),
            ASISDMISC::FCVTZU_Sd_S_H_Sn_S_H(opcode) => opcode.bits(),
            ASISDMISC::FCVTZU_Sd_Sn(opcode) => opcode.bits(),
            ASISDMISC::FRECPE_Sd_S_H_Sn_S_H(opcode) => opcode.bits(),
            ASISDMISC::FRECPE_Sd_Sn(opcode) => opcode.bits(),
            ASISDMISC::FRECPX_Sd_S_H_Sn_S_H(opcode) => opcode.bits(),
            ASISDMISC::FRECPX_Sd_Sn(opcode) => opcode.bits(),
            ASISDMISC::FRSQRTE_Sd_S_H_Sn_S_H(opcode) => opcode.bits(),
            ASISDMISC::FRSQRTE_Sd_Sn(opcode) => opcode.bits(),
            ASISDMISC::NEG_Sd_Sn(opcode) => opcode.bits(),
            ASISDMISC::SCVTF_Sd_S_H_Sn_S_H(opcode) => opcode.bits(),
            ASISDMISC::SCVTF_Sd_Sn(opcode) => opcode.bits(),
            ASISDMISC::SQABS_Sd_Sn(opcode) => opcode.bits(),
            ASISDMISC::SQNEG_Sd_Sn(opcode) => opcode.bits(),
            ASISDMISC::SQXTN_Sd_Sn(opcode) => opcode.bits(),
            ASISDMISC::SQXTUN_Sd_Sn(opcode) => opcode.bits(),
            ASISDMISC::SUQADD_Sd_Sn(opcode) => opcode.bits(),
            ASISDMISC::UCVTF_Sd_S_H_Sn_S_H(opcode) => opcode.bits(),
            ASISDMISC::UCVTF_Sd_Sn(opcode) => opcode.bits(),
            ASISDMISC::UQXTN_Sd_Sn(opcode) => opcode.bits(),
            ASISDMISC::USQADD_Sd_Sn(opcode) => opcode.bits(),
        }
    }
}
impl InsnOpcode for Opcode {
    fn definition(&self) -> &'static Insn {
        match self {
            Opcode::SME_SIZE_22_HSD(class) => class.definition(),
            Opcode::DP_3SRC(class) => class.definition(),
            Opcode::SME_START(class) => class.definition(),
            Opcode::ASIMDIMM(class) => class.definition(),
            Opcode::ASIMDTBL(class) => class.definition(),
            Opcode::SVE_LIMM(class) => class.definition(),
            Opcode::LDST_POS(class) => class.definition(),
            Opcode::ADDSUB_SHIFT(class) => class.definition(),
            Opcode::ASIMDSAME(class) => class.definition(),
            Opcode::SVE_SIZE_BHS(class) => class.definition(),
            Opcode::FLOAT2INT(class) => class.definition(),
            Opcode::LDST_UNSCALED(class) => class.definition(),
            Opcode::ASISDSAME(class) => class.definition(),
            Opcode::ASIMDDIFF(class) => class.definition(),
            Opcode::CONDCMP_IMM(class) => class.definition(),
            Opcode::SME_FP_SD(class) => class.definition(),
            Opcode::SVE_SIZE_HSD(class) => class.definition(),
            Opcode::FLOATCMP(class) => class.definition(),
            Opcode::LSE128_ATOMIC(class) => class.definition(),
            Opcode::CONDBRANCH(class) => class.definition(),
            Opcode::SVE_SIZE_SD2(class) => class.definition(),
            Opcode::FLOATDP1(class) => class.definition(),
            Opcode::PCRELADDR(class) => class.definition(),
            Opcode::BITFIELD(class) => class.definition(),
            Opcode::LOG_IMM(class) => class.definition(),
            Opcode::ASISDONE(class) => class.definition(),
            Opcode::CONDSEL(class) => class.definition(),
            Opcode::CONDCMP_REG(class) => class.definition(),
            Opcode::ASIMDELEM(class) => class.definition(),
            Opcode::ADDSUB_CARRY(class) => class.definition(),
            Opcode::SVE_SHIFT_TSZ_BHSD(class) => class.definition(),
            Opcode::CRYPTOSM4(class) => class.definition(),
            Opcode::SME_SHIFT(class) => class.definition(),
            Opcode::ASIMDEXT(class) => class.definition(),
            Opcode::CRYPTOSM3(class) => class.definition(),
            Opcode::ASISDELEM(class) => class.definition(),
            Opcode::LSE_ATOMIC(class) => class.definition(),
            Opcode::ASIMDPERM(class) => class.definition(),
            Opcode::LDSTNAPAIR_OFFS(class) => class.definition(),
            Opcode::CSSC(class) => class.definition(),
            Opcode::CRYPTOSHA2(class) => class.definition(),
            Opcode::MOVEWIDE(class) => class.definition(),
            Opcode::ASISDLSOP(class) => class.definition(),
            Opcode::ASIMDALL(class) => class.definition(),
            Opcode::SVE_SHIFT_PRED(class) => class.definition(),
            Opcode::SVE_SHIFT_UNPRED(class) => class.definition(),
            Opcode::SME_LDR(class) => class.definition(),
            Opcode::SVE_SHIFT_TSZ_HSD(class) => class.definition(),
            Opcode::CRYPTOSHA3(class) => class.definition(),
            Opcode::AARCH64_MISC(class) => class.definition(),
            Opcode::THE(class) => class.definition(),
            Opcode::SVE_SIZE_BH(class) => class.definition(),
            Opcode::SVE_CPY(class) => class.definition(),
            Opcode::SME2_MOV(class) => class.definition(),
            Opcode::LOG_SHIFT(class) => class.definition(),
            Opcode::SME_PSEL(class) => class.definition(),
            Opcode::SME_SIZE_22(class) => class.definition(),
            Opcode::SME_STOP(class) => class.definition(),
            Opcode::BFLOAT16(class) => class.definition(),
            Opcode::ADDSUB_EXT(class) => class.definition(),
            Opcode::ASISDLSO(class) => class.definition(),
            Opcode::LDSTPAIR_OFF(class) => class.definition(),
            Opcode::FLOATDP2(class) => class.definition(),
            Opcode::ASIMDMISC(class) => class.definition(),
            Opcode::EXTRACT(class) => class.definition(),
            Opcode::SVE_SIZE_SD(class) => class.definition(),
            Opcode::SVE_SIZE_BHSD(class) => class.definition(),
            Opcode::SVE_SIZE_HSD2(class) => class.definition(),
            Opcode::ADDSUB_IMM(class) => class.definition(),
            Opcode::ASISDPAIR(class) => class.definition(),
            Opcode::SME_SZ_23(class) => class.definition(),
            Opcode::SME_MISC(class) => class.definition(),
            Opcode::DP_1SRC(class) => class.definition(),
            Opcode::CRYPTOAES(class) => class.definition(),
            Opcode::SVE_MISC(class) => class.definition(),
            Opcode::SME_INT_SD(class) => class.definition(),
            Opcode::FLOATCCMP(class) => class.definition(),
            Opcode::SME2_MOVAZ(class) => class.definition(),
            Opcode::TESTBRANCH(class) => class.definition(),
            Opcode::LDST_REGOFF(class) => class.definition(),
            Opcode::SVE_SIZE_TSZ_BHS(class) => class.definition(),
            Opcode::ASIMDSHF(class) => class.definition(),
            Opcode::LDST_IMM10(class) => class.definition(),
            Opcode::LOADLIT(class) => class.definition(),
            Opcode::ASIMDINS(class) => class.definition(),
            Opcode::LDSTPAIR_INDEXED(class) => class.definition(),
            Opcode::DP_2SRC(class) => class.definition(),
            Opcode::COMPBRANCH(class) => class.definition(),
            Opcode::ASISDSHF(class) => class.definition(),
            Opcode::SME_SIZE_12_HS(class) => class.definition(),
            Opcode::IC_SYSTEM(class) => class.definition(),
            Opcode::FLOATDP3(class) => class.definition(),
            Opcode::SVE2_URQVS(class) => class.definition(),
            Opcode::SVE_INDEX(class) => class.definition(),
            Opcode::LDST_IMM9(class) => class.definition(),
            Opcode::SME_MOV(class) => class.definition(),
            Opcode::BRANCH_IMM(class) => class.definition(),
            Opcode::FLOAT2FIX(class) => class.definition(),
            Opcode::ASISDDIFF(class) => class.definition(),
            Opcode::ASISDLSE(class) => class.definition(),
            Opcode::SME_STR(class) => class.definition(),
            Opcode::GCS(class) => class.definition(),
            Opcode::EXCEPTION(class) => class.definition(),
            Opcode::DOTPRODUCT(class) => class.definition(),
            Opcode::BRANCH_REG(class) => class.definition(),
            Opcode::SVE_SIZE_13(class) => class.definition(),
            Opcode::LDSTEXCL(class) => class.definition(),
            Opcode::LDST_UNPRIV(class) => class.definition(),
            Opcode::FLOATIMM(class) => class.definition(),
            Opcode::SVE_MOVPRFX(class) => class.definition(),
            Opcode::ASISDLSEP(class) => class.definition(),
            Opcode::RCPC3(class) => class.definition(),
            Opcode::SVE_PRED_ZM(class) => class.definition(),
            Opcode::SME_SIZE_12_BHS(class) => class.definition(),
            Opcode::FLOATSEL(class) => class.definition(),
            Opcode::SVE_INDEX1(class) => class.definition(),
            Opcode::ASISDMISC(class) => class.definition(),
        }
    }
    fn bits(&self) -> u32 {
        match self {
            Opcode::SME_SIZE_22_HSD(class) => class.bits(),
            Opcode::DP_3SRC(class) => class.bits(),
            Opcode::SME_START(class) => class.bits(),
            Opcode::ASIMDIMM(class) => class.bits(),
            Opcode::ASIMDTBL(class) => class.bits(),
            Opcode::SVE_LIMM(class) => class.bits(),
            Opcode::LDST_POS(class) => class.bits(),
            Opcode::ADDSUB_SHIFT(class) => class.bits(),
            Opcode::ASIMDSAME(class) => class.bits(),
            Opcode::SVE_SIZE_BHS(class) => class.bits(),
            Opcode::FLOAT2INT(class) => class.bits(),
            Opcode::LDST_UNSCALED(class) => class.bits(),
            Opcode::ASISDSAME(class) => class.bits(),
            Opcode::ASIMDDIFF(class) => class.bits(),
            Opcode::CONDCMP_IMM(class) => class.bits(),
            Opcode::SME_FP_SD(class) => class.bits(),
            Opcode::SVE_SIZE_HSD(class) => class.bits(),
            Opcode::FLOATCMP(class) => class.bits(),
            Opcode::LSE128_ATOMIC(class) => class.bits(),
            Opcode::CONDBRANCH(class) => class.bits(),
            Opcode::SVE_SIZE_SD2(class) => class.bits(),
            Opcode::FLOATDP1(class) => class.bits(),
            Opcode::PCRELADDR(class) => class.bits(),
            Opcode::BITFIELD(class) => class.bits(),
            Opcode::LOG_IMM(class) => class.bits(),
            Opcode::ASISDONE(class) => class.bits(),
            Opcode::CONDSEL(class) => class.bits(),
            Opcode::CONDCMP_REG(class) => class.bits(),
            Opcode::ASIMDELEM(class) => class.bits(),
            Opcode::ADDSUB_CARRY(class) => class.bits(),
            Opcode::SVE_SHIFT_TSZ_BHSD(class) => class.bits(),
            Opcode::CRYPTOSM4(class) => class.bits(),
            Opcode::SME_SHIFT(class) => class.bits(),
            Opcode::ASIMDEXT(class) => class.bits(),
            Opcode::CRYPTOSM3(class) => class.bits(),
            Opcode::ASISDELEM(class) => class.bits(),
            Opcode::LSE_ATOMIC(class) => class.bits(),
            Opcode::ASIMDPERM(class) => class.bits(),
            Opcode::LDSTNAPAIR_OFFS(class) => class.bits(),
            Opcode::CSSC(class) => class.bits(),
            Opcode::CRYPTOSHA2(class) => class.bits(),
            Opcode::MOVEWIDE(class) => class.bits(),
            Opcode::ASISDLSOP(class) => class.bits(),
            Opcode::ASIMDALL(class) => class.bits(),
            Opcode::SVE_SHIFT_PRED(class) => class.bits(),
            Opcode::SVE_SHIFT_UNPRED(class) => class.bits(),
            Opcode::SME_LDR(class) => class.bits(),
            Opcode::SVE_SHIFT_TSZ_HSD(class) => class.bits(),
            Opcode::CRYPTOSHA3(class) => class.bits(),
            Opcode::AARCH64_MISC(class) => class.bits(),
            Opcode::THE(class) => class.bits(),
            Opcode::SVE_SIZE_BH(class) => class.bits(),
            Opcode::SVE_CPY(class) => class.bits(),
            Opcode::SME2_MOV(class) => class.bits(),
            Opcode::LOG_SHIFT(class) => class.bits(),
            Opcode::SME_PSEL(class) => class.bits(),
            Opcode::SME_SIZE_22(class) => class.bits(),
            Opcode::SME_STOP(class) => class.bits(),
            Opcode::BFLOAT16(class) => class.bits(),
            Opcode::ADDSUB_EXT(class) => class.bits(),
            Opcode::ASISDLSO(class) => class.bits(),
            Opcode::LDSTPAIR_OFF(class) => class.bits(),
            Opcode::FLOATDP2(class) => class.bits(),
            Opcode::ASIMDMISC(class) => class.bits(),
            Opcode::EXTRACT(class) => class.bits(),
            Opcode::SVE_SIZE_SD(class) => class.bits(),
            Opcode::SVE_SIZE_BHSD(class) => class.bits(),
            Opcode::SVE_SIZE_HSD2(class) => class.bits(),
            Opcode::ADDSUB_IMM(class) => class.bits(),
            Opcode::ASISDPAIR(class) => class.bits(),
            Opcode::SME_SZ_23(class) => class.bits(),
            Opcode::SME_MISC(class) => class.bits(),
            Opcode::DP_1SRC(class) => class.bits(),
            Opcode::CRYPTOAES(class) => class.bits(),
            Opcode::SVE_MISC(class) => class.bits(),
            Opcode::SME_INT_SD(class) => class.bits(),
            Opcode::FLOATCCMP(class) => class.bits(),
            Opcode::SME2_MOVAZ(class) => class.bits(),
            Opcode::TESTBRANCH(class) => class.bits(),
            Opcode::LDST_REGOFF(class) => class.bits(),
            Opcode::SVE_SIZE_TSZ_BHS(class) => class.bits(),
            Opcode::ASIMDSHF(class) => class.bits(),
            Opcode::LDST_IMM10(class) => class.bits(),
            Opcode::LOADLIT(class) => class.bits(),
            Opcode::ASIMDINS(class) => class.bits(),
            Opcode::LDSTPAIR_INDEXED(class) => class.bits(),
            Opcode::DP_2SRC(class) => class.bits(),
            Opcode::COMPBRANCH(class) => class.bits(),
            Opcode::ASISDSHF(class) => class.bits(),
            Opcode::SME_SIZE_12_HS(class) => class.bits(),
            Opcode::IC_SYSTEM(class) => class.bits(),
            Opcode::FLOATDP3(class) => class.bits(),
            Opcode::SVE2_URQVS(class) => class.bits(),
            Opcode::SVE_INDEX(class) => class.bits(),
            Opcode::LDST_IMM9(class) => class.bits(),
            Opcode::SME_MOV(class) => class.bits(),
            Opcode::BRANCH_IMM(class) => class.bits(),
            Opcode::FLOAT2FIX(class) => class.bits(),
            Opcode::ASISDDIFF(class) => class.bits(),
            Opcode::ASISDLSE(class) => class.bits(),
            Opcode::SME_STR(class) => class.bits(),
            Opcode::GCS(class) => class.bits(),
            Opcode::EXCEPTION(class) => class.bits(),
            Opcode::DOTPRODUCT(class) => class.bits(),
            Opcode::BRANCH_REG(class) => class.bits(),
            Opcode::SVE_SIZE_13(class) => class.bits(),
            Opcode::LDSTEXCL(class) => class.bits(),
            Opcode::LDST_UNPRIV(class) => class.bits(),
            Opcode::FLOATIMM(class) => class.bits(),
            Opcode::SVE_MOVPRFX(class) => class.bits(),
            Opcode::ASISDLSEP(class) => class.bits(),
            Opcode::RCPC3(class) => class.bits(),
            Opcode::SVE_PRED_ZM(class) => class.bits(),
            Opcode::SME_SIZE_12_BHS(class) => class.bits(),
            Opcode::FLOATSEL(class) => class.bits(),
            Opcode::SVE_INDEX1(class) => class.bits(),
            Opcode::ASISDMISC(class) => class.bits(),
        }
    }
}
pub fn decode(insn: u32) -> Option<Opcode> {
    if insn & 0x4000000 == 0 {
        if insn & 0x2000000 == 0 {
            if insn & 0x8000000 == 0 {
                if insn & 0x1000000 == 0 {
                    if insn & 0x10000000 == 0 {
                        if insn & 0x200000 == 0 {
                            if insn & 0x20000000 == 0 {
                                if insn & 0x40000000 == 0 {
                                    if insn & 0x400000 == 0 {
                                        if insn & 0x800000 == 0 {
                                            if insn & 0xffff0000 == 0x000000 {
                                                return Some(UDF_UNDEFINED::make_opcode(insn));
                                            }
                                        } else {
                                            if insn & 0x000008 == 0 {
                                                if insn & 0x000010 == 0 {
                                                    if insn & 0xffe0001c == 0x80800000 {
                                                        return Some (FMOPA_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                    }
                                                } else {
                                                    if insn & 0xffe0001c == 0x80800010 {
                                                        return Some (FMOPS_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                    }
                                                }
                                            } else {
                                                if insn & 0x000010 == 0 {
                                                    if insn & 0xffe0001c == 0x80800008 {
                                                        return Some (BMOPA_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                    }
                                                } else {
                                                    if insn & 0xffe0001c == 0x80800018 {
                                                        return Some (BMOPS_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                    }
                                                }
                                            }
                                        }
                                    } else {
                                        if insn & 0x000010 == 0 {
                                            if insn & 0xffe00018 == 0x80c00000 {
                                                return Some (FMOPA_SME_ZAda_3b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                            }
                                        } else {
                                            if insn & 0xffe00018 == 0x80c00010 {
                                                return Some (FMOPS_SME_ZAda_3b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                            }
                                        }
                                    }
                                } else {
                                    if insn & 0x040000 == 0 {
                                        if insn & 0x020000 == 0 {
                                            if insn & 0x080000 == 0 {
                                                if insn & 0x100000 == 0 {
                                                    if insn & 0xff3e0010 == 0xc0000000 {
                                                        return Some (MOVA_SME_ZA_HV_idx_dest_SVE_Pg3_SVE_Zn :: make_opcode (insn)) ;
                                                    }
                                                    if insn & 0xff3e0010 == 0xc0000000 {
                                                        return Some (MOVA_SME_ZA_HV_idx_dest_SVE_Pg3_SVE_Zn :: make_opcode (insn)) ;
                                                    }
                                                } else {
                                                    if insn & 0x010000 == 0 {
                                                        if insn & 0x400000 == 0 {
                                                            if insn & 0xffff001c == 0xc0900000 {
                                                                return Some (ADDHA_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xffff0018 == 0xc0d00000 {
                                                                return Some (ADDHA_SME_ZAda_3b_SVE_Pg3_SME_Pm_SVE_Zn :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x400000 == 0 {
                                                            if insn & 0xffff001c == 0xc0910000 {
                                                                return Some (ADDVA_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xffff0018 == 0xc0d10000 {
                                                                return Some (ADDVA_SME_ZAda_3b_SVE_Pg3_SME_Pm_SVE_Zn :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0x400000 == 0 {
                                                    if insn & 0xffffff00 == 0xc0080000 {
                                                        return Some (ZERO_SME_list_of_64bit_tiles :: make_opcode (insn)) ;
                                                    }
                                                } else {
                                                    if insn == 0xc0480001 {
                                                        return Some(
                                                            ZERO_SME_ZT0_LIST::make_opcode(insn),
                                                        );
                                                    }
                                                }
                                            }
                                        } else {
                                            if insn & 0x080000 == 0 {
                                                if insn & 0xff3e0200 == 0xc0020000 {
                                                    return Some (MOVA_SVE_Zd_SVE_Pg3_SME_ZA_HV_idx_src :: make_opcode (insn)) ;
                                                }
                                                if insn & 0xff3e0200 == 0xc0020000 {
                                                    return Some (MOVA_SVE_Zd_SVE_Pg3_SME_ZA_HV_idx_src :: make_opcode (insn)) ;
                                                }
                                            } else {
                                                if insn & 0x400000 == 0 {
                                                    if insn & 0x004000 == 0 {
                                                        if insn & 0xfffecc03 == 0xc08a8000 {
                                                            return Some (LUTI4_SME_Zdnx4_SME_ZT0_SME_Zn_INDEX1_16 :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xfffe4c01 == 0xc08a4000 {
                                                            return Some (LUTI4_SME_Zdnx2_SME_ZT0_SME_Zn_INDEX2_15 :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0xfffe0c00 == 0xc0ca0000 {
                                                        return Some (LUTI4_SVE_Zd_SME_ZT0_SME_Zn_INDEX3_14 :: make_opcode (insn)) ;
                                                    }
                                                }
                                            }
                                        }
                                    } else {
                                        if insn & 0x000400 == 0 {
                                            if insn & 0x000800 == 0 {
                                                if insn & 0x080000 == 0 {
                                                    if insn & 0x020000 == 0 {
                                                        if insn & 0xff3f1c38 == 0xc0040000 {
                                                            return Some (MOVA_SME_ZA_HV_idx_destxN_SME_Znx2 :: make_opcode (insn)) ;
                                                        }
                                                        if insn & 0xff3f1c38 == 0xc0040000 {
                                                            return Some (MOVA_SME_ZA_HV_idx_destxN_SME_Znx2 :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0x000200 == 0 {
                                                            if insn & 0xff3f1f01 == 0xc0060000 {
                                                                return Some (MOVA_SME_Zdnx2_SME_ZA_HV_idx_srcxN :: make_opcode (insn)) ;
                                                            }
                                                            if insn & 0xff3f1f01 == 0xc0060000 {
                                                                return Some (MOVA_SME_Zdnx2_SME_ZA_HV_idx_srcxN :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0x400000 == 0 {
                                                                if insn & 0x800000 == 0 {
                                                                    if insn & 0xffff1f01
                                                                        == 0xc0060200
                                                                    {
                                                                        return Some (MOVAZ_SME_Zdnx2_SME_ZA_array_vrsb_1 :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xffff1f01
                                                                        == 0xc0860200
                                                                    {
                                                                        return Some (MOVAZ_SME_Zdnx2_SME_ZA_array_vrss_1 :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0x800000 == 0 {
                                                                    if insn & 0xffff1f01
                                                                        == 0xc0460200
                                                                    {
                                                                        return Some (MOVAZ_SME_Zdnx2_SME_ZA_array_vrsh_1 :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xffff1f01
                                                                        == 0xc0c60200
                                                                    {
                                                                        return Some (MOVAZ_SME_Zdnx2_SME_ZA_array_vrsd_1 :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            }
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x400000 == 0 {
                                                        if insn & 0x004000 == 0 {
                                                            if insn & 0xfffccc03 == 0xc08c8000 {
                                                                return Some (LUTI2_SME_Zdnx4_SME_ZT0_SME_Zn_INDEX2_16 :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xfffc4c01 == 0xc08c4000 {
                                                                return Some (LUTI2_SME_Zdnx2_SME_ZT0_SME_Zn_INDEX3_15 :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x800000 == 0 {
                                                            if insn & 0x020000 == 0 {
                                                                if insn & 0xffff8fe0 == 0xc04c03e0 {
                                                                    return Some (MOVT_Rt_SME_ZT0_INDEX :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xffff8fe0 == 0xc04e03e0 {
                                                                    return Some (MOVT_SME_ZT0_INDEX_Rt :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0xfffc0c00 == 0xc0cc0000 {
                                                                return Some (LUTI2_SVE_Zd_SME_ZT0_SME_Zn_INDEX4_14 :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0x020000 == 0 {
                                                    if insn & 0xffff9c38 == 0xc0040800 {
                                                        return Some (MOVA_SME_ZA_array_off3_0_SME_Znx2 :: make_opcode (insn)) ;
                                                    }
                                                    if insn & 0xffff9c38 == 0xc0040800 {
                                                        return Some (MOVA_SME_ZA_array_off3_0_SME_Znx2 :: make_opcode (insn)) ;
                                                    }
                                                } else {
                                                    if insn & 0xffff9f01 == 0xc0060800 {
                                                        return Some (MOVA_SME_Zdnx2_SME_ZA_array_off3_5 :: make_opcode (insn)) ;
                                                    }
                                                    if insn & 0xffff9f01 == 0xc0060800 {
                                                        return Some (MOVA_SME_Zdnx2_SME_ZA_array_off3_5 :: make_opcode (insn)) ;
                                                    }
                                                }
                                            }
                                        } else {
                                            if insn & 0x000800 == 0 {
                                                if insn & 0x020000 == 0 {
                                                    if insn & 0xff3f1c78 == 0xc0040400 {
                                                        return Some (MOVA_SME_ZA_HV_idx_destxN_SME_Znx4 :: make_opcode (insn)) ;
                                                    }
                                                    if insn & 0xff3f1c78 == 0xc0040400 {
                                                        return Some (MOVA_SME_ZA_HV_idx_destxN_SME_Znx4 :: make_opcode (insn)) ;
                                                    }
                                                } else {
                                                    if insn & 0x000200 == 0 {
                                                        if insn & 0xff3f1f03 == 0xc0060400 {
                                                            return Some (MOVA_SME_Zdnx4_SME_ZA_HV_idx_srcxN :: make_opcode (insn)) ;
                                                        }
                                                        if insn & 0xff3f1f03 == 0xc0060400 {
                                                            return Some (MOVA_SME_Zdnx4_SME_ZA_HV_idx_srcxN :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0x400000 == 0 {
                                                            if insn & 0x800000 == 0 {
                                                                if insn & 0xffff1f83 == 0xc0060600 {
                                                                    return Some (MOVAZ_SME_Zdnx4_SME_ZA_array_vrsb_2 :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xffff1f83 == 0xc0860600 {
                                                                    return Some (MOVAZ_SME_Zdnx4_SME_ZA_array_vrss_2 :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x800000 == 0 {
                                                                if insn & 0xffff1f83 == 0xc0460600 {
                                                                    return Some (MOVAZ_SME_Zdnx4_SME_ZA_array_vrsh_2 :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xffff1f03 == 0xc0c60600 {
                                                                    return Some (MOVAZ_SME_Zdnx4_SME_ZA_array_vrsd_2 :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0x020000 == 0 {
                                                    if insn & 0xffff9c78 == 0xc0040c00 {
                                                        return Some (MOVA_SME_ZA_array_off3_0_SME_Znx4 :: make_opcode (insn)) ;
                                                    }
                                                    if insn & 0xffff9c78 == 0xc0040c00 {
                                                        return Some (MOVA_SME_ZA_array_off3_0_SME_Znx4 :: make_opcode (insn)) ;
                                                    }
                                                } else {
                                                    if insn & 0xffff9f03 == 0xc0060c00 {
                                                        return Some (MOVA_SME_Zdnx4_SME_ZA_array_off3_5 :: make_opcode (insn)) ;
                                                    }
                                                    if insn & 0xffff9f03 == 0xc0060c00 {
                                                        return Some (MOVA_SME_Zdnx4_SME_ZA_array_off3_5 :: make_opcode (insn)) ;
                                                    }
                                                }
                                            }
                                        }
                                    }
                                }
                            } else {
                                if insn & 0x400000 == 0 {
                                    if insn & 0x800000 == 0 {
                                        if insn & 0x40000000 == 0 {
                                            if insn & 0x000001 == 0 {
                                                if insn & 0x002000 == 0 {
                                                    if insn & 0x004000 == 0 {
                                                        if insn & 0x008000 == 0 {
                                                            if insn & 0xffe0e001 == 0xa0000000 {
                                                                return Some (LD1B_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xffe0e003 == 0xa0008000 {
                                                                return Some (LD1B_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x008000 == 0 {
                                                            if insn & 0xffe0e001 == 0xa0004000 {
                                                                return Some (LD1W_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR_LSL2 :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xffe0e003 == 0xa000c000 {
                                                                return Some (LD1W_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR_LSL2 :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x004000 == 0 {
                                                        if insn & 0x008000 == 0 {
                                                            if insn & 0xffe0e001 == 0xa0002000 {
                                                                return Some (LD1H_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR_LSL1 :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xffe0e003 == 0xa000a000 {
                                                                return Some (LD1H_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR_LSL1 :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x008000 == 0 {
                                                            if insn & 0xffe0e001 == 0xa0006000 {
                                                                return Some (LD1D_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR_LSL3 :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xffe0e003 == 0xa000e000 {
                                                                return Some (LD1D_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR_LSL3 :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0x002000 == 0 {
                                                    if insn & 0x004000 == 0 {
                                                        if insn & 0x008000 == 0 {
                                                            if insn & 0xffe0e001 == 0xa0000001 {
                                                                return Some (LDNT1B_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xffe0e003 == 0xa0008001 {
                                                                return Some (LDNT1B_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x008000 == 0 {
                                                            if insn & 0xffe0e001 == 0xa0004001 {
                                                                return Some (LDNT1W_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR_LSL2 :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xffe0e003 == 0xa000c001 {
                                                                return Some (LDNT1W_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR_LSL2 :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x004000 == 0 {
                                                        if insn & 0x008000 == 0 {
                                                            if insn & 0xffe0e001 == 0xa0002001 {
                                                                return Some (LDNT1H_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR_LSL1 :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xffe0e003 == 0xa000a001 {
                                                                return Some (LDNT1H_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR_LSL1 :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x008000 == 0 {
                                                            if insn & 0xffe0e001 == 0xa0006001 {
                                                                return Some (LDNT1D_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR_LSL3 :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xffe0e003 == 0xa000e001 {
                                                                return Some (LDNT1D_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR_LSL3 :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    }
                                                }
                                            }
                                        } else {
                                            if insn & 0xffe00010 == 0xe0000000 {
                                                return Some (LD1B_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_R :: make_opcode (insn)) ;
                                            }
                                            if insn & 0xffe00010 == 0xe0000000 {
                                                return Some (LD1B_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_R :: make_opcode (insn)) ;
                                            }
                                        }
                                    } else {
                                        if insn & 0x000010 == 0 {
                                            if insn & 0x40000000 == 0 {
                                                if insn & 0x000008 == 0 {
                                                    if insn & 0xffe0001c == 0xa0800000 {
                                                        return Some (SMOPA_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                    }
                                                } else {
                                                    if insn & 0xffe0001c == 0xa0800008 {
                                                        return Some (SMOPA_SME_ZAda_2b_S_S_SVE_Pg3_P_M_SME_Pm_P_M_SVE_Zn_S_H_SVE_Zm_16_S_H :: make_opcode (insn)) ;
                                                    }
                                                }
                                            } else {
                                                if insn & 0xffe00010 == 0xe0800000 {
                                                    return Some (LD1W_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_R :: make_opcode (insn)) ;
                                                }
                                                if insn & 0xffe00010 == 0xe0800000 {
                                                    return Some (LD1W_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_R :: make_opcode (insn)) ;
                                                }
                                            }
                                        } else {
                                            if insn & 0x000008 == 0 {
                                                if insn & 0xffe0001c == 0xa0800010 {
                                                    return Some (SMOPS_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                }
                                            } else {
                                                if insn & 0xffe0001c == 0xa0800018 {
                                                    return Some (SMOPS_SME_ZAda_2b_S_S_SVE_Pg3_P_M_SME_Pm_P_M_SVE_Zn_S_H_SVE_Zm_16_S_H :: make_opcode (insn)) ;
                                                }
                                            }
                                        }
                                    }
                                } else {
                                    if insn & 0x800000 == 0 {
                                        if insn & 0x40000000 == 0 {
                                            if insn & 0x000001 == 0 {
                                                if insn & 0x002000 == 0 {
                                                    if insn & 0x004000 == 0 {
                                                        if insn & 0x008000 == 0 {
                                                            if insn & 0xfff0e001 == 0xa0400000 {
                                                                return Some (LD1B_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xfff0e003 == 0xa0408000 {
                                                                return Some (LD1B_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x008000 == 0 {
                                                            if insn & 0xfff0e001 == 0xa0404000 {
                                                                return Some (LD1W_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xfff0e003 == 0xa040c000 {
                                                                return Some (LD1W_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x004000 == 0 {
                                                        if insn & 0x008000 == 0 {
                                                            if insn & 0xfff0e001 == 0xa0402000 {
                                                                return Some (LD1H_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xfff0e003 == 0xa040a000 {
                                                                return Some (LD1H_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x008000 == 0 {
                                                            if insn & 0xfff0e001 == 0xa0406000 {
                                                                return Some (LD1D_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xfff0e003 == 0xa040e000 {
                                                                return Some (LD1D_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0x002000 == 0 {
                                                    if insn & 0x004000 == 0 {
                                                        if insn & 0x008000 == 0 {
                                                            if insn & 0xfff0e001 == 0xa0400001 {
                                                                return Some (LDNT1B_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xfff0e003 == 0xa0408001 {
                                                                return Some (LDNT1B_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x008000 == 0 {
                                                            if insn & 0xfff0e001 == 0xa0404001 {
                                                                return Some (LDNT1W_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xfff0e003 == 0xa040c001 {
                                                                return Some (LDNT1W_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x004000 == 0 {
                                                        if insn & 0x008000 == 0 {
                                                            if insn & 0xfff0e001 == 0xa0402001 {
                                                                return Some (LDNT1H_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xfff0e003 == 0xa040a001 {
                                                                return Some (LDNT1H_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x008000 == 0 {
                                                            if insn & 0xfff0e001 == 0xa0406001 {
                                                                return Some (LDNT1D_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xfff0e003 == 0xa040e001 {
                                                                return Some (LDNT1D_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    }
                                                }
                                            }
                                        } else {
                                            if insn & 0xffe00010 == 0xe0400000 {
                                                return Some (LD1H_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_R :: make_opcode (insn)) ;
                                            }
                                            if insn & 0xffe00010 == 0xe0400000 {
                                                return Some (LD1H_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_R :: make_opcode (insn)) ;
                                            }
                                        }
                                    } else {
                                        if insn & 0x000010 == 0 {
                                            if insn & 0x40000000 == 0 {
                                                if insn & 0xffe00018 == 0xa0c00000 {
                                                    return Some (SMOPA_SME_ZAda_3b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                }
                                            } else {
                                                if insn & 0xffe00010 == 0xe0c00000 {
                                                    return Some (LD1D_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_R :: make_opcode (insn)) ;
                                                }
                                                if insn & 0xffe00010 == 0xe0c00000 {
                                                    return Some (LD1D_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_R :: make_opcode (insn)) ;
                                                }
                                            }
                                        } else {
                                            if insn & 0xffe00018 == 0xa0c00010 {
                                                return Some (SMOPS_SME_ZAda_3b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                            }
                                        }
                                    }
                                }
                            }
                        } else {
                            if insn & 0x400000 == 0 {
                                if insn & 0x800000 == 0 {
                                    if insn & 0x40000000 == 0 {
                                        if insn & 0x000001 == 0 {
                                            if insn & 0x002000 == 0 {
                                                if insn & 0x004000 == 0 {
                                                    if insn & 0x008000 == 0 {
                                                        if insn & 0xffe0e001 == 0xa0200000 {
                                                            return Some (ST1B_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xffe0e003 == 0xa0208000 {
                                                            return Some (ST1B_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x008000 == 0 {
                                                        if insn & 0xffe0e001 == 0xa0204000 {
                                                            return Some (ST1W_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR_LSL2 :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xffe0e003 == 0xa020c000 {
                                                            return Some (ST1W_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR_LSL2 :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0x004000 == 0 {
                                                    if insn & 0x008000 == 0 {
                                                        if insn & 0xffe0e001 == 0xa0202000 {
                                                            return Some (ST1H_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR_LSL1 :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xffe0e003 == 0xa020a000 {
                                                            return Some (ST1H_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR_LSL1 :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x008000 == 0 {
                                                        if insn & 0xffe0e001 == 0xa0206000 {
                                                            return Some (ST1D_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR_LSL3 :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xffe0e003 == 0xa020e000 {
                                                            return Some (ST1D_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR_LSL3 :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                }
                                            }
                                        } else {
                                            if insn & 0x002000 == 0 {
                                                if insn & 0x004000 == 0 {
                                                    if insn & 0x008000 == 0 {
                                                        if insn & 0xffe0e001 == 0xa0200001 {
                                                            return Some (STNT1B_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xffe0e003 == 0xa0208001 {
                                                            return Some (STNT1B_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x008000 == 0 {
                                                        if insn & 0xffe0e001 == 0xa0204001 {
                                                            return Some (STNT1W_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR_LSL2 :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xffe0e003 == 0xa020c001 {
                                                            return Some (STNT1W_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR_LSL2 :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0x004000 == 0 {
                                                    if insn & 0x008000 == 0 {
                                                        if insn & 0xffe0e001 == 0xa0202001 {
                                                            return Some (STNT1H_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR_LSL1 :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xffe0e003 == 0xa020a001 {
                                                            return Some (STNT1H_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR_LSL1 :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x008000 == 0 {
                                                        if insn & 0xffe0e001 == 0xa0206001 {
                                                            return Some (STNT1D_SME_Zdnx2_SME_PNg3_SVE_ADDR_RR_LSL3 :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xffe0e003 == 0xa020e001 {
                                                            return Some (STNT1D_SME_Zdnx4_SME_PNg3_SVE_ADDR_RR_LSL3 :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                }
                                            }
                                        }
                                    } else {
                                        if insn & 0xffe00010 == 0xe0200000 {
                                            return Some (ST1B_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_R :: make_opcode (insn)) ;
                                        }
                                        if insn & 0xffe00010 == 0xe0200000 {
                                            return Some (ST1B_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_R :: make_opcode (insn)) ;
                                        }
                                    }
                                } else {
                                    if insn & 0x000010 == 0 {
                                        if insn & 0x40000000 == 0 {
                                            if insn & 0xffe0001c == 0xa0a00000 {
                                                return Some (SUMOPA_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                            }
                                        } else {
                                            if insn & 0xffe00010 == 0xe0a00000 {
                                                return Some (ST1W_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_R :: make_opcode (insn)) ;
                                            }
                                            if insn & 0xffe00010 == 0xe0a00000 {
                                                return Some (ST1W_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_R :: make_opcode (insn)) ;
                                            }
                                        }
                                    } else {
                                        if insn & 0xffe0001c == 0xa0a00010 {
                                            return Some (SUMOPS_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                        }
                                    }
                                }
                            } else {
                                if insn & 0x800000 == 0 {
                                    if insn & 0x40000000 == 0 {
                                        if insn & 0x000001 == 0 {
                                            if insn & 0x002000 == 0 {
                                                if insn & 0x004000 == 0 {
                                                    if insn & 0x008000 == 0 {
                                                        if insn & 0xfff0e001 == 0xa0600000 {
                                                            return Some (ST1B_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xfff0e003 == 0xa0608000 {
                                                            return Some (ST1B_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x008000 == 0 {
                                                        if insn & 0xfff0e001 == 0xa0604000 {
                                                            return Some (ST1W_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xfff0e003 == 0xa060c000 {
                                                            return Some (ST1W_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0x004000 == 0 {
                                                    if insn & 0x008000 == 0 {
                                                        if insn & 0xfff0e001 == 0xa0602000 {
                                                            return Some (ST1H_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xfff0e003 == 0xa060a000 {
                                                            return Some (ST1H_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x008000 == 0 {
                                                        if insn & 0xfff0e001 == 0xa0606000 {
                                                            return Some (ST1D_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xfff0e003 == 0xa060e000 {
                                                            return Some (ST1D_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                }
                                            }
                                        } else {
                                            if insn & 0x002000 == 0 {
                                                if insn & 0x004000 == 0 {
                                                    if insn & 0x008000 == 0 {
                                                        if insn & 0xfff0e001 == 0xa0600001 {
                                                            return Some (STNT1B_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xfff0e003 == 0xa0608001 {
                                                            return Some (STNT1B_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x008000 == 0 {
                                                        if insn & 0xfff0e001 == 0xa0604001 {
                                                            return Some (STNT1W_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xfff0e003 == 0xa060c001 {
                                                            return Some (STNT1W_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0x004000 == 0 {
                                                    if insn & 0x008000 == 0 {
                                                        if insn & 0xfff0e001 == 0xa0602001 {
                                                            return Some (STNT1H_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xfff0e003 == 0xa060a001 {
                                                            return Some (STNT1H_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x008000 == 0 {
                                                        if insn & 0xfff0e001 == 0xa0606001 {
                                                            return Some (STNT1D_SME_Zdnx2_SME_PNg3_SVE_ADDR_RI_S4x2xVL :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xfff0e003 == 0xa060e001 {
                                                            return Some (STNT1D_SME_Zdnx4_SME_PNg3_SVE_ADDR_RI_S4x4xVL :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                }
                                            }
                                        }
                                    } else {
                                        if insn & 0xffe00010 == 0xe0600000 {
                                            return Some (ST1H_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_R :: make_opcode (insn)) ;
                                        }
                                        if insn & 0xffe00010 == 0xe0600000 {
                                            return Some (ST1H_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_R :: make_opcode (insn)) ;
                                        }
                                    }
                                } else {
                                    if insn & 0x000010 == 0 {
                                        if insn & 0x40000000 == 0 {
                                            if insn & 0xffe00018 == 0xa0e00000 {
                                                return Some (SUMOPA_SME_ZAda_3b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                            }
                                        } else {
                                            if insn & 0xffe00010 == 0xe0e00000 {
                                                return Some (ST1D_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_R :: make_opcode (insn)) ;
                                            }
                                            if insn & 0xffe00010 == 0xe0e00000 {
                                                return Some (ST1D_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_R :: make_opcode (insn)) ;
                                            }
                                        }
                                    } else {
                                        if insn & 0xffe00018 == 0xa0e00010 {
                                            return Some (SUMOPS_SME_ZAda_3b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                        }
                                    }
                                }
                            }
                        }
                    } else {
                        if insn & 0x80000000 == 0 {
                            if insn & 0x9f000000 == 0x10000000 {
                                return Some(ADR_Rd_ADDR_PCREL21::make_opcode(insn));
                            }
                        } else {
                            if insn & 0x9f000000 == 0x90000000 {
                                return Some(ADRP_Rd_ADDR_ADRP::make_opcode(insn));
                            }
                        }
                    }
                } else {
                    if insn & 0x10000000 == 0 {
                        if insn & 0x200000 == 0 {
                            if insn & 0x400000 == 0 {
                                if insn & 0x800000 == 0 {
                                    if insn & 0x20000000 == 0 {
                                        if insn & 0x000008 == 0 {
                                            if insn & 0x000010 == 0 {
                                                if insn & 0x100000 == 0 {
                                                    if insn & 0x000004 == 0 {
                                                        if insn & 0xfff0001c == 0xc1000000 {
                                                            return Some (SMLALL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm_INDEX4_10 :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xfff0001c == 0xc1000004 {
                                                            return Some (USMLALL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm_INDEX4_10 :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x000020 == 0 {
                                                        if insn & 0x008000 == 0 {
                                                            if insn & 0xfff09038 == 0xc1100000 {
                                                                return Some (SMLALL_SME_ZA_array_off1x4_SME_Znx2_SME_Zm_INDEX4_1 :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xfff09078 == 0xc1108000 {
                                                                return Some (SMLALL_SME_ZA_array_off1x4_SME_Znx4_SME_Zm_INDEX4_1 :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x008000 == 0 {
                                                            if insn & 0xfff09038 == 0xc1100020 {
                                                                return Some (USMLALL_SME_ZA_array_off1x4_SME_Znx2_SME_Zm_INDEX4_1 :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xfff09078 == 0xc1108020 {
                                                                return Some (USMLALL_SME_ZA_array_off1x4_SME_Znx4_SME_Zm_INDEX4_1 :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0x100000 == 0 {
                                                    if insn & 0x000004 == 0 {
                                                        if insn & 0xfff0001c == 0xc1000010 {
                                                            return Some (UMLALL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm_INDEX4_10 :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xfff0001c == 0xc1000014 {
                                                            return Some (SUMLALL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm_INDEX4_10 :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x000020 == 0 {
                                                        if insn & 0x008000 == 0 {
                                                            if insn & 0xfff09038 == 0xc1100010 {
                                                                return Some (UMLALL_SME_ZA_array_off1x4_SME_Znx2_SME_Zm_INDEX4_1 :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xfff09078 == 0xc1108010 {
                                                                return Some (UMLALL_SME_ZA_array_off1x4_SME_Znx4_SME_Zm_INDEX4_1 :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x008000 == 0 {
                                                            if insn & 0xfff09038 == 0xc1100030 {
                                                                return Some (SUMLALL_SME_ZA_array_off1x4_SME_Znx2_SME_Zm_INDEX4_1 :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xfff09078 == 0xc1108030 {
                                                                return Some (SUMLALL_SME_ZA_array_off1x4_SME_Znx4_SME_Zm_INDEX4_1 :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    }
                                                }
                                            }
                                        } else {
                                            if insn & 0x000010 == 0 {
                                                if insn & 0x100000 == 0 {
                                                    if insn & 0xfff0001c == 0xc1000008 {
                                                        return Some (SMLSLL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm_INDEX4_10 :: make_opcode (insn)) ;
                                                    }
                                                } else {
                                                    if insn & 0x008000 == 0 {
                                                        if insn & 0xfff09038 == 0xc1100008 {
                                                            return Some (SMLSLL_SME_ZA_array_off1x4_SME_Znx2_SME_Zm_INDEX4_1 :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xfff09078 == 0xc1108008 {
                                                            return Some (SMLSLL_SME_ZA_array_off1x4_SME_Znx4_SME_Zm_INDEX4_1 :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0x100000 == 0 {
                                                    if insn & 0xfff0001c == 0xc1000018 {
                                                        return Some (UMLSLL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm_INDEX4_10 :: make_opcode (insn)) ;
                                                    }
                                                } else {
                                                    if insn & 0x008000 == 0 {
                                                        if insn & 0xfff09038 == 0xc1100018 {
                                                            return Some (UMLSLL_SME_ZA_array_off1x4_SME_Znx2_SME_Zm_INDEX4_1 :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xfff09078 == 0xc1108018 {
                                                            return Some (UMLSLL_SME_ZA_array_off1x4_SME_Znx4_SME_Zm_INDEX4_1 :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                }
                                            }
                                        }
                                    } else {
                                        if insn & 0x008000 == 0 {
                                            if insn & 0x40000000 == 0 {
                                                if insn & 0x000008 == 0 {
                                                    if insn & 0x002000 == 0 {
                                                        if insn & 0x004000 == 0 {
                                                            if insn & 0xffe0e008 == 0xa1000000 {
                                                                return Some (LD1B_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xffe0e008 == 0xa1004000 {
                                                                return Some (LD1W_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL2 :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x004000 == 0 {
                                                            if insn & 0xffe0e008 == 0xa1002000 {
                                                                return Some (LD1H_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL1 :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xffe0e008 == 0xa1006000 {
                                                                return Some (LD1D_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL3 :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x002000 == 0 {
                                                        if insn & 0x004000 == 0 {
                                                            if insn & 0xffe0e008 == 0xa1000008 {
                                                                return Some (LDNT1B_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xffe0e008 == 0xa1004008 {
                                                                return Some (LDNT1W_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL2 :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x004000 == 0 {
                                                            if insn & 0xffe0e008 == 0xa1002008 {
                                                                return Some (LDNT1H_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL1 :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xffe0e008 == 0xa1006008 {
                                                                return Some (LDNT1D_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL3 :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0xffff9c10 == 0xe1000000 {
                                                    return Some (LDR_SME_ZA_array_off4_SME_ADDR_RI_U4xVL :: make_opcode (insn)) ;
                                                }
                                            }
                                        } else {
                                            if insn & 0x000008 == 0 {
                                                if insn & 0x002000 == 0 {
                                                    if insn & 0x004000 == 0 {
                                                        if insn & 0x40000000 == 0 {
                                                            if insn & 0xffe0e00c == 0xa1008000 {
                                                                return Some (LD1B_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xfffffc1f == 0xe11f8000 {
                                                                return Some (LDR_SME_ZT0_SIMD_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0xffe0e00c == 0xa100c000 {
                                                            return Some (LD1W_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL2 :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x004000 == 0 {
                                                        if insn & 0xffe0e00c == 0xa100a000 {
                                                            return Some (LD1H_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL1 :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xffe0e00c == 0xa100e000 {
                                                            return Some (LD1D_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL3 :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0x002000 == 0 {
                                                    if insn & 0x004000 == 0 {
                                                        if insn & 0xffe0e00c == 0xa1008008 {
                                                            return Some (LDNT1B_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xffe0e00c == 0xa100c008 {
                                                            return Some (LDNT1W_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL2 :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x004000 == 0 {
                                                        if insn & 0xffe0e00c == 0xa100a008 {
                                                            return Some (LDNT1H_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL1 :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xffe0e00c == 0xa100e008 {
                                                            return Some (LDNT1D_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL3 :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                }
                                            }
                                        }
                                    }
                                } else {
                                    if insn & 0x000008 == 0 {
                                        if insn & 0x000010 == 0 {
                                            if insn & 0x20000000 == 0 {
                                                if insn & 0x40000000 == 0 {
                                                    if insn & 0xffe0001c == 0x81800000 {
                                                        return Some (BFMOPA_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                    }
                                                } else {
                                                    if insn & 0x001000 == 0 {
                                                        if insn & 0x100000 == 0 {
                                                            if insn & 0xfff0101c == 0xc1800000 {
                                                                return Some (SMLALL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm_INDEX3_10 :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0x008000 == 0 {
                                                                if insn & 0xfff09838 == 0xc1900000 {
                                                                    return Some (SMLALL_SME_ZA_array_off1x4_SME_Znx2_SME_Zm_INDEX3_1 :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xfff09878 == 0xc1908000 {
                                                                    return Some (SMLALL_SME_ZA_array_off1x4_SME_Znx4_SME_Zm_INDEX3_1 :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x100000 == 0 {
                                                            if insn & 0xfff01018 == 0xc1801000 {
                                                                return Some (FMLAL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm_INDEX3_10 :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0x008000 == 0 {
                                                                if insn & 0xfff09038 == 0xc1901000 {
                                                                    return Some (FMLAL_SME_ZA_array_off2x2_SME_Znx2_SME_Zm_INDEX3_2 :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xfff09078 == 0xc1909000 {
                                                                    return Some (FMLAL_SME_ZA_array_off2x2_SME_Znx4_SME_Zm_INDEX3_2 :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0xffe0001c == 0xa1800000 {
                                                    return Some (USMOPA_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                }
                                            }
                                        } else {
                                            if insn & 0x20000000 == 0 {
                                                if insn & 0x40000000 == 0 {
                                                    if insn & 0xffe0001c == 0x81800010 {
                                                        return Some (BFMOPS_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                    }
                                                } else {
                                                    if insn & 0x001000 == 0 {
                                                        if insn & 0x100000 == 0 {
                                                            if insn & 0xfff0101c == 0xc1800010 {
                                                                return Some (UMLALL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm_INDEX3_10 :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0x008000 == 0 {
                                                                if insn & 0xfff09838 == 0xc1900010 {
                                                                    return Some (UMLALL_SME_ZA_array_off1x4_SME_Znx2_SME_Zm_INDEX3_1 :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xfff09878 == 0xc1908010 {
                                                                    return Some (UMLALL_SME_ZA_array_off1x4_SME_Znx4_SME_Zm_INDEX3_1 :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x100000 == 0 {
                                                            if insn & 0xfff01018 == 0xc1801010 {
                                                                return Some (BFMLAL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm_INDEX3_10 :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0x008000 == 0 {
                                                                if insn & 0xfff09038 == 0xc1901010 {
                                                                    return Some (BFMLAL_SME_ZA_array_off2x2_SME_Znx2_SME_Zm_INDEX3_2 :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xfff09078 == 0xc1909010 {
                                                                    return Some (BFMLAL_SME_ZA_array_off2x2_SME_Znx4_SME_Zm_INDEX3_2 :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0xffe0001c == 0xa1800010 {
                                                    return Some (USMOPS_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                }
                                            }
                                        }
                                    } else {
                                        if insn & 0x000010 == 0 {
                                            if insn & 0x20000000 == 0 {
                                                if insn & 0x001000 == 0 {
                                                    if insn & 0x100000 == 0 {
                                                        if insn & 0xfff0101c == 0xc1800008 {
                                                            return Some (SMLSLL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm_INDEX3_10 :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0x008000 == 0 {
                                                            if insn & 0xfff09838 == 0xc1900008 {
                                                                return Some (SMLSLL_SME_ZA_array_off1x4_SME_Znx2_SME_Zm_INDEX3_1 :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xfff09878 == 0xc1908008 {
                                                                return Some (SMLSLL_SME_ZA_array_off1x4_SME_Znx4_SME_Zm_INDEX3_1 :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x100000 == 0 {
                                                        if insn & 0xfff01018 == 0xc1801008 {
                                                            return Some (FMLSL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm_INDEX3_10 :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0x008000 == 0 {
                                                            if insn & 0xfff09038 == 0xc1901008 {
                                                                return Some (FMLSL_SME_ZA_array_off2x2_SME_Znx2_SME_Zm_INDEX3_2 :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xfff09078 == 0xc1909008 {
                                                                return Some (FMLSL_SME_ZA_array_off2x2_SME_Znx4_SME_Zm_INDEX3_2 :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0xffe0001c == 0xa1800008 {
                                                    return Some (UMOPA_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                }
                                            }
                                        } else {
                                            if insn & 0x20000000 == 0 {
                                                if insn & 0x001000 == 0 {
                                                    if insn & 0x100000 == 0 {
                                                        if insn & 0xfff0101c == 0xc1800018 {
                                                            return Some (UMLSLL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm_INDEX3_10 :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0x008000 == 0 {
                                                            if insn & 0xfff09838 == 0xc1900018 {
                                                                return Some (UMLSLL_SME_ZA_array_off1x4_SME_Znx2_SME_Zm_INDEX3_1 :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xfff09878 == 0xc1908018 {
                                                                return Some (UMLSLL_SME_ZA_array_off1x4_SME_Znx4_SME_Zm_INDEX3_1 :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x100000 == 0 {
                                                        if insn & 0xfff01018 == 0xc1801018 {
                                                            return Some (BFMLSL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm_INDEX3_10 :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0x008000 == 0 {
                                                            if insn & 0xfff09038 == 0xc1901018 {
                                                                return Some (BFMLSL_SME_ZA_array_off2x2_SME_Znx2_SME_Zm_INDEX3_2 :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xfff09078 == 0xc1909018 {
                                                                return Some (BFMLSL_SME_ZA_array_off2x2_SME_Znx4_SME_Zm_INDEX3_2 :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0xffe0001c == 0xa1800018 {
                                                    return Some (UMOPS_SME_ZAda_2b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                }
                                            }
                                        }
                                    }
                                }
                            } else {
                                if insn & 0x800000 == 0 {
                                    if insn & 0x000008 == 0 {
                                        if insn & 0x008000 == 0 {
                                            if insn & 0x100000 == 0 {
                                                if insn & 0x002000 == 0 {
                                                    if insn & 0x004000 == 0 {
                                                        if insn & 0xfff0e008 == 0xa1400000 {
                                                            return Some (LD1B_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xfff0e008 == 0xa1404000 {
                                                            return Some (LD1W_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x004000 == 0 {
                                                        if insn & 0xfff0e008 == 0xa1402000 {
                                                            return Some (LD1H_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xfff0e008 == 0xa1406000 {
                                                            return Some (LD1D_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0x000010 == 0 {
                                                    if insn & 0x000020 == 0 {
                                                        if insn & 0x001000 == 0 {
                                                            if insn & 0xfff09038 == 0xc1500000 {
                                                                return Some (FMLA_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2 :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xfff09038 == 0xc1501000 {
                                                                return Some (SDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2 :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x001000 == 0 {
                                                            if insn & 0xfff09038 == 0xc1500020 {
                                                                return Some (SVDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2 :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xfff09038 == 0xc1501020 {
                                                                return Some (SDOT_SME_ZA_array_off3_0_S_S_SME_Znx2_S_B_SME_Zm_INDEX2_S_B :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x000020 == 0 {
                                                        if insn & 0x001000 == 0 {
                                                            if insn & 0xfff09038 == 0xc1500010 {
                                                                return Some (FMLS_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2 :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xfff09038 == 0xc1501010 {
                                                                return Some (UDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2 :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x001000 == 0 {
                                                            if insn & 0xfff09038 == 0xc1500030 {
                                                                return Some (UVDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2 :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xfff09038 == 0xc1501030 {
                                                                return Some (UDOT_SME_ZA_array_off3_0_S_S_SME_Znx2_S_B_SME_Zm_INDEX2_S_B :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    }
                                                }
                                            }
                                        } else {
                                            if insn & 0x100000 == 0 {
                                                if insn & 0x002000 == 0 {
                                                    if insn & 0x004000 == 0 {
                                                        if insn & 0xfff0e00c == 0xa1408000 {
                                                            return Some (LD1B_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xfff0e00c == 0xa140c000 {
                                                            return Some (LD1W_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x004000 == 0 {
                                                        if insn & 0xfff0e00c == 0xa140a000 {
                                                            return Some (LD1H_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xfff0e00c == 0xa140e000 {
                                                            return Some (LD1D_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0x000010 == 0 {
                                                    if insn & 0x000020 == 0 {
                                                        if insn & 0x001000 == 0 {
                                                            if insn & 0xfff09078 == 0xc1508000 {
                                                                return Some (FMLA_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2 :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xfff09078 == 0xc1509000 {
                                                                return Some (SDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2 :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x001000 == 0 {
                                                            if insn & 0xfff09078 == 0xc1508020 {
                                                                return Some (SVDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2 :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xfff09078 == 0xc1509020 {
                                                                return Some (SDOT_SME_ZA_array_off3_0_S_S_SME_Znx4_S_B_SME_Zm_INDEX2_S_B :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x000020 == 0 {
                                                        if insn & 0x001000 == 0 {
                                                            if insn & 0xfff09078 == 0xc1508010 {
                                                                return Some (FMLS_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2 :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xfff09078 == 0xc1509010 {
                                                                return Some (UDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2 :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x001000 == 0 {
                                                            if insn & 0xfff09078 == 0xc1508030 {
                                                                return Some (UVDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2 :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xfff09078 == 0xc1509030 {
                                                                return Some (UDOT_SME_ZA_array_off3_0_S_S_SME_Znx4_S_B_SME_Zm_INDEX2_S_B :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    }
                                                }
                                            }
                                        }
                                    } else {
                                        if insn & 0x008000 == 0 {
                                            if insn & 0x100000 == 0 {
                                                if insn & 0x002000 == 0 {
                                                    if insn & 0x004000 == 0 {
                                                        if insn & 0xfff0e008 == 0xa1400008 {
                                                            return Some (LDNT1B_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xfff0e008 == 0xa1404008 {
                                                            return Some (LDNT1W_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x004000 == 0 {
                                                        if insn & 0xfff0e008 == 0xa1402008 {
                                                            return Some (LDNT1H_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xfff0e008 == 0xa1406008 {
                                                            return Some (LDNT1D_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0x000010 == 0 {
                                                    if insn & 0x000020 == 0 {
                                                        if insn & 0x001000 == 0 {
                                                            if insn & 0xfff09038 == 0xc1500008 {
                                                                return Some (FVDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2 :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xfff09038 == 0xc1501008 {
                                                                return Some (FDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2 :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0xfff09038 == 0xc1501028 {
                                                            return Some (USDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2 :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x000020 == 0 {
                                                        if insn & 0x001000 == 0 {
                                                            if insn & 0xfff09038 == 0xc1500018 {
                                                                return Some (BFVDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2 :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xfff09038 == 0xc1501018 {
                                                                return Some (BFDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2 :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0xfff09038 == 0xc1501038 {
                                                            return Some (SUDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX2 :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                }
                                            }
                                        } else {
                                            if insn & 0x100000 == 0 {
                                                if insn & 0x002000 == 0 {
                                                    if insn & 0x004000 == 0 {
                                                        if insn & 0xfff0e00c == 0xa1408008 {
                                                            return Some (LDNT1B_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xfff0e00c == 0xa140c008 {
                                                            return Some (LDNT1W_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x004000 == 0 {
                                                        if insn & 0xfff0e00c == 0xa140a008 {
                                                            return Some (LDNT1H_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xfff0e00c == 0xa140e008 {
                                                            return Some (LDNT1D_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0x000010 == 0 {
                                                    if insn & 0x000020 == 0 {
                                                        if insn & 0xfff09078 == 0xc1509008 {
                                                            return Some (FDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2 :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0x001000 == 0 {
                                                            if insn & 0xfff09078 == 0xc1508028 {
                                                                return Some (USVDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2 :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xfff09078 == 0xc1509028 {
                                                                return Some (USDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2 :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x000020 == 0 {
                                                        if insn & 0xfff09078 == 0xc1509018 {
                                                            return Some (BFDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2 :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0x001000 == 0 {
                                                            if insn & 0xfff09078 == 0xc1508038 {
                                                                return Some (SUVDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2 :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xfff09078 == 0xc1509038 {
                                                                return Some (SUDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX2 :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    }
                                                }
                                            }
                                        }
                                    }
                                } else {
                                    if insn & 0x000010 == 0 {
                                        if insn & 0x20000000 == 0 {
                                            if insn & 0x000008 == 0 {
                                                if insn & 0x001000 == 0 {
                                                    if insn & 0x008000 == 0 {
                                                        if insn & 0xfff09838 == 0xc1d00000 {
                                                            return Some (FMLA_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX1 :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xfff09878 == 0xc1d08000 {
                                                            return Some (FMLA_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX1 :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x100000 == 0 {
                                                        if insn & 0xfff01018 == 0xc1c01000 {
                                                            return Some (SMLAL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm_INDEX3_10 :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0x008000 == 0 {
                                                            if insn & 0xfff09038 == 0xc1d01000 {
                                                                return Some (SMLAL_SME_ZA_array_off2x2_SME_Znx2_SME_Zm_INDEX3_2 :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xfff09078 == 0xc1d09000 {
                                                                return Some (SMLAL_SME_ZA_array_off2x2_SME_Znx4_SME_Zm_INDEX3_2 :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0x001000 == 0 {
                                                    if insn & 0x000800 == 0 {
                                                        if insn & 0x008000 == 0 {
                                                            if insn & 0xfff09838 == 0xc1d00008 {
                                                                return Some (SDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX1 :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xfff09878 == 0xc1d08008 {
                                                                return Some (SDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX1 :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0xfff09878 == 0xc1d08808 {
                                                            return Some (SVDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX1 :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x100000 == 0 {
                                                        if insn & 0xfff01018 == 0xc1c01008 {
                                                            return Some (SMLSL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm_INDEX3_10 :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0x008000 == 0 {
                                                            if insn & 0xfff09038 == 0xc1d01008 {
                                                                return Some (SMLSL_SME_ZA_array_off2x2_SME_Znx2_SME_Zm_INDEX3_2 :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xfff09078 == 0xc1d09008 {
                                                                return Some (SMLSL_SME_ZA_array_off2x2_SME_Znx4_SME_Zm_INDEX3_2 :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    }
                                                }
                                            }
                                        } else {
                                            if insn & 0x40000000 == 0 {
                                                if insn & 0xffe00018 == 0xa1c00000 {
                                                    return Some (USMOPA_SME_ZAda_3b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                }
                                            } else {
                                                if insn & 0xffe00010 == 0xe1c00000 {
                                                    return Some (LD1Q_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_R :: make_opcode (insn)) ;
                                                }
                                                if insn & 0xffe00010 == 0xe1c00000 {
                                                    return Some (LD1Q_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_R :: make_opcode (insn)) ;
                                                }
                                            }
                                        }
                                    } else {
                                        if insn & 0x000008 == 0 {
                                            if insn & 0x20000000 == 0 {
                                                if insn & 0x001000 == 0 {
                                                    if insn & 0x008000 == 0 {
                                                        if insn & 0xfff09838 == 0xc1d00010 {
                                                            return Some (FMLS_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX1 :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xfff09878 == 0xc1d08010 {
                                                            return Some (FMLS_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX1 :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x100000 == 0 {
                                                        if insn & 0xfff01018 == 0xc1c01010 {
                                                            return Some (UMLAL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm_INDEX3_10 :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0x008000 == 0 {
                                                            if insn & 0xfff09038 == 0xc1d01010 {
                                                                return Some (UMLAL_SME_ZA_array_off2x2_SME_Znx2_SME_Zm_INDEX3_2 :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xfff09078 == 0xc1d09010 {
                                                                return Some (UMLAL_SME_ZA_array_off2x2_SME_Znx4_SME_Zm_INDEX3_2 :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0xffe00018 == 0xa1c00010 {
                                                    return Some (USMOPS_SME_ZAda_3b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                }
                                            }
                                        } else {
                                            if insn & 0x001000 == 0 {
                                                if insn & 0x000800 == 0 {
                                                    if insn & 0x008000 == 0 {
                                                        if insn & 0xfff09838 == 0xc1d00018 {
                                                            return Some (UDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zm_INDEX1 :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xfff09878 == 0xc1d08018 {
                                                            return Some (UDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX1 :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0xfff09878 == 0xc1d08818 {
                                                        return Some (UVDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zm_INDEX1 :: make_opcode (insn)) ;
                                                    }
                                                }
                                            } else {
                                                if insn & 0x100000 == 0 {
                                                    if insn & 0xfff01018 == 0xc1c01018 {
                                                        return Some (UMLSL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm_INDEX3_10 :: make_opcode (insn)) ;
                                                    }
                                                } else {
                                                    if insn & 0x008000 == 0 {
                                                        if insn & 0xfff09038 == 0xc1d01018 {
                                                            return Some (UMLSL_SME_ZA_array_off2x2_SME_Znx2_SME_Zm_INDEX3_2 :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xfff09078 == 0xc1d09018 {
                                                            return Some (UMLSL_SME_ZA_array_off2x2_SME_Znx4_SME_Zm_INDEX3_2 :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                }
                                            }
                                        }
                                    }
                                }
                            }
                        } else {
                            if insn & 0x20000000 == 0 {
                                if insn & 0x40000000 == 0 {
                                    if insn & 0x000010 == 0 {
                                        if insn & 0xffe0001c == 0x81a00000 {
                                            return Some (FMOPA_SME_ZAda_2b_S_S_SVE_Pg3_P_M_SME_Pm_P_M_SVE_Zn_S_H_SVE_Zm_16_S_H :: make_opcode (insn)) ;
                                        }
                                    } else {
                                        if insn & 0xffe0001c == 0x81a00010 {
                                            return Some (FMOPS_SME_ZAda_2b_S_S_SVE_Pg3_P_M_SME_Pm_P_M_SVE_Zn_S_H_SVE_Zm_16_S_H :: make_opcode (insn)) ;
                                        }
                                    }
                                } else {
                                    if insn & 0x008000 == 0 {
                                        if insn & 0x000008 == 0 {
                                            if insn & 0x000010 == 0 {
                                                if insn & 0x000400 == 0 {
                                                    if insn & 0x000800 == 0 {
                                                        if insn & 0x001000 == 0 {
                                                            if insn & 0x000004 == 0 {
                                                                if insn & 0x800000 == 0 {
                                                                    if insn & 0x100000 == 0 {
                                                                        if insn & 0xffb09c1e
                                                                            == 0xc1200000
                                                                        {
                                                                            return Some (SMLALL_SME_ZA_array_off1x4_SVE_ZnxN_SME_Zm :: make_opcode (insn)) ;
                                                                        }
                                                                    } else {
                                                                        if insn & 0xffb09c1e
                                                                            == 0xc1300000
                                                                        {
                                                                            return Some (SMLALL_SME_ZA_array_off1x4_S_S_SVE_ZnxN_S_B_SME_Zm_S_B :: make_opcode (insn)) ;
                                                                        }
                                                                    }
                                                                } else {
                                                                    if insn & 0x010000 == 0 {
                                                                        if insn & 0xffa19c3e
                                                                            == 0xc1a00000
                                                                        {
                                                                            return Some (SMLALL_SME_ZA_array_off1x4_SME_Znx2_SME_Zmx2 :: make_opcode (insn)) ;
                                                                        }
                                                                    } else {
                                                                        if insn & 0xffa39c7e
                                                                            == 0xc1a10000
                                                                        {
                                                                            return Some (SMLALL_SME_ZA_array_off1x4_SME_Znx4_SME_Zmx4 :: make_opcode (insn)) ;
                                                                        }
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0x800000 == 0 {
                                                                    if insn & 0x100000 == 0 {
                                                                        if insn & 0xfff09c1e
                                                                            == 0xc1200004
                                                                        {
                                                                            return Some (USMLALL_SME_ZA_array_off1x4_SVE_ZnxN_SME_Zm :: make_opcode (insn)) ;
                                                                        }
                                                                    } else {
                                                                        if insn & 0xfff09c1e
                                                                            == 0xc1300004
                                                                        {
                                                                            return Some (USMLALL_SME_ZA_array_off1x4_S_S_SVE_ZnxN_S_B_SME_Zm_S_B :: make_opcode (insn)) ;
                                                                        }
                                                                    }
                                                                } else {
                                                                    if insn & 0x010000 == 0 {
                                                                        if insn & 0xffe19c3e
                                                                            == 0xc1a00004
                                                                        {
                                                                            return Some (USMLALL_SME_ZA_array_off1x4_SME_Znx2_SME_Zmx2 :: make_opcode (insn)) ;
                                                                        }
                                                                    } else {
                                                                        if insn & 0xffe39c7e
                                                                            == 0xc1a10004
                                                                        {
                                                                            return Some (USMLALL_SME_ZA_array_off1x4_SME_Znx4_SME_Zmx4 :: make_opcode (insn)) ;
                                                                        }
                                                                    }
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x800000 == 0 {
                                                                if insn & 0x100000 == 0 {
                                                                    if insn & 0xfff09c18
                                                                        == 0xc1201000
                                                                    {
                                                                        return Some (FDOT_SME_ZA_array_off3_0_SVE_ZnxN_SME_Zm :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xfff09c18
                                                                        == 0xc1301000
                                                                    {
                                                                        return Some (FDOT_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_H_SME_Zm_S_H :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0x010000 == 0 {
                                                                    if insn & 0xffe19c38
                                                                        == 0xc1a01000
                                                                    {
                                                                        return Some (FDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zmx2 :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xffe39c78
                                                                        == 0xc1a11000
                                                                    {
                                                                        return Some (FDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zmx4 :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x001000 == 0 {
                                                            if insn & 0x400000 == 0 {
                                                                if insn & 0x800000 == 0 {
                                                                    if insn & 0x100000 == 0 {
                                                                        if insn & 0xfff09c1c
                                                                            == 0xc1200800
                                                                        {
                                                                            return Some (FMLAL_SME_ZA_array_off2x2_SVE_ZnxN_SME_Zm :: make_opcode (insn)) ;
                                                                        }
                                                                    } else {
                                                                        if insn & 0xfff09c1c
                                                                            == 0xc1300800
                                                                        {
                                                                            return Some (FMLAL_SME_ZA_array_off2x2_S_S_SVE_ZnxN_S_H_SME_Zm_S_H :: make_opcode (insn)) ;
                                                                        }
                                                                    }
                                                                } else {
                                                                    if insn & 0x010000 == 0 {
                                                                        if insn & 0xffe19c3c
                                                                            == 0xc1a00800
                                                                        {
                                                                            return Some (FMLAL_SME_ZA_array_off2x2_SME_Znx2_SME_Zmx2 :: make_opcode (insn)) ;
                                                                        }
                                                                    } else {
                                                                        if insn & 0xffe39c7c
                                                                            == 0xc1a10800
                                                                        {
                                                                            return Some (FMLAL_SME_ZA_array_off2x2_SME_Znx4_SME_Zmx4 :: make_opcode (insn)) ;
                                                                        }
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0x800000 == 0 {
                                                                    if insn & 0x100000 == 0 {
                                                                        if insn & 0xfff09c1c
                                                                            == 0xc1600800
                                                                        {
                                                                            return Some (SMLAL_SME_ZA_array_off2x2_SVE_ZnxN_SME_Zm :: make_opcode (insn)) ;
                                                                        }
                                                                    } else {
                                                                        if insn & 0xfff09c1c
                                                                            == 0xc1700800
                                                                        {
                                                                            return Some (SMLAL_SME_ZA_array_off2x2_S_S_SVE_ZnxN_S_H_SME_Zm_S_H :: make_opcode (insn)) ;
                                                                        }
                                                                    }
                                                                } else {
                                                                    if insn & 0x010000 == 0 {
                                                                        if insn & 0xffe19c3c
                                                                            == 0xc1e00800
                                                                        {
                                                                            return Some (SMLAL_SME_ZA_array_off2x2_SME_Znx2_SME_Zmx2 :: make_opcode (insn)) ;
                                                                        }
                                                                    } else {
                                                                        if insn & 0xffe39c7c
                                                                            == 0xc1e10800
                                                                        {
                                                                            return Some (SMLAL_SME_ZA_array_off2x2_SME_Znx4_SME_Zmx4 :: make_opcode (insn)) ;
                                                                        }
                                                                    }
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x800000 == 0 {
                                                                if insn & 0x100000 == 0 {
                                                                    if insn & 0xffb09c18
                                                                        == 0xc1201800
                                                                    {
                                                                        return Some (FMLA_SME_ZA_array_off3_0_SVE_ZnxN_SME_Zm :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xffb09c18
                                                                        == 0xc1301800
                                                                    {
                                                                        return Some (FMLA_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_S_SME_Zm_S_S :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0x010000 == 0 {
                                                                    if insn & 0xffa19c38
                                                                        == 0xc1a01800
                                                                    {
                                                                        return Some (FMLA_SME_ZA_array_off3_0_SME_Znx2_SME_Zmx2 :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xffa39c78
                                                                        == 0xc1a11800
                                                                    {
                                                                        return Some (FMLA_SME_ZA_array_off3_0_SME_Znx4_SME_Zmx4 :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            }
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x000800 == 0 {
                                                        if insn & 0x001000 == 0 {
                                                            if insn & 0x000004 == 0 {
                                                                if insn & 0xffb09c1c == 0xc1200400 {
                                                                    return Some (SMLALL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xfff09c1c == 0xc1200404 {
                                                                    return Some (USMLALL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x800000 == 0 {
                                                                if insn & 0x100000 == 0 {
                                                                    if insn & 0xffb09c18
                                                                        == 0xc1201400
                                                                    {
                                                                        return Some (SDOT_SME_ZA_array_off3_0_SVE_ZnxN_SME_Zm :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xffb09c18
                                                                        == 0xc1301400
                                                                    {
                                                                        return Some (SDOT_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_B_SME_Zm_S_B :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0x010000 == 0 {
                                                                    if insn & 0xffa19c38
                                                                        == 0xc1a01400
                                                                    {
                                                                        return Some (SDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zmx2 :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xffa39c78
                                                                        == 0xc1a11400
                                                                    {
                                                                        return Some (SDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zmx4 :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x001000 == 0 {
                                                            if insn & 0x400000 == 0 {
                                                                if insn & 0xfff09c18 == 0xc1200c00 {
                                                                    return Some (FMLAL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xfff09c18 == 0xc1600c00 {
                                                                    return Some (SMLAL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x010000 == 0 {
                                                                if insn & 0xffbf9c38 == 0xc1a01c00 {
                                                                    return Some (FADD_SME_ZA_array_off3_0_SME_Znx2 :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xffbf9c78 == 0xc1a11c00 {
                                                                    return Some (FADD_SME_ZA_array_off3_0_SME_Znx4 :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0x000400 == 0 {
                                                    if insn & 0x000800 == 0 {
                                                        if insn & 0x001000 == 0 {
                                                            if insn & 0x000004 == 0 {
                                                                if insn & 0x800000 == 0 {
                                                                    if insn & 0x100000 == 0 {
                                                                        if insn & 0xffb09c1e
                                                                            == 0xc1200010
                                                                        {
                                                                            return Some (UMLALL_SME_ZA_array_off1x4_SVE_ZnxN_SME_Zm :: make_opcode (insn)) ;
                                                                        }
                                                                    } else {
                                                                        if insn & 0xffb09c1e
                                                                            == 0xc1300010
                                                                        {
                                                                            return Some (UMLALL_SME_ZA_array_off1x4_S_S_SVE_ZnxN_S_B_SME_Zm_S_B :: make_opcode (insn)) ;
                                                                        }
                                                                    }
                                                                } else {
                                                                    if insn & 0x010000 == 0 {
                                                                        if insn & 0xffa19c3e
                                                                            == 0xc1a00010
                                                                        {
                                                                            return Some (UMLALL_SME_ZA_array_off1x4_SME_Znx2_SME_Zmx2 :: make_opcode (insn)) ;
                                                                        }
                                                                    } else {
                                                                        if insn & 0xffa39c7e
                                                                            == 0xc1a10010
                                                                        {
                                                                            return Some (UMLALL_SME_ZA_array_off1x4_SME_Znx4_SME_Zmx4 :: make_opcode (insn)) ;
                                                                        }
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0x100000 == 0 {
                                                                    if insn & 0xfff09c1e
                                                                        == 0xc1200014
                                                                    {
                                                                        return Some (SUMLALL_SME_ZA_array_off1x4_SVE_ZnxN_SME_Zm :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xfff09c1e
                                                                        == 0xc1300014
                                                                    {
                                                                        return Some (SUMLALL_SME_ZA_array_off1x4_S_S_SVE_ZnxN_S_B_SME_Zm_S_B :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x800000 == 0 {
                                                                if insn & 0x100000 == 0 {
                                                                    if insn & 0xfff09c18
                                                                        == 0xc1201010
                                                                    {
                                                                        return Some (BFDOT_SME_ZA_array_off3_0_SVE_ZnxN_SME_Zm :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xfff09c18
                                                                        == 0xc1301010
                                                                    {
                                                                        return Some (BFDOT_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_H_SME_Zm_S_H :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0x010000 == 0 {
                                                                    if insn & 0xffe19c38
                                                                        == 0xc1a01010
                                                                    {
                                                                        return Some (BFDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zmx2 :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xffe39c78
                                                                        == 0xc1a11010
                                                                    {
                                                                        return Some (BFDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zmx4 :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x001000 == 0 {
                                                            if insn & 0x400000 == 0 {
                                                                if insn & 0x800000 == 0 {
                                                                    if insn & 0x100000 == 0 {
                                                                        if insn & 0xfff09c1c
                                                                            == 0xc1200810
                                                                        {
                                                                            return Some (BFMLAL_SME_ZA_array_off2x2_SVE_ZnxN_SME_Zm :: make_opcode (insn)) ;
                                                                        }
                                                                    } else {
                                                                        if insn & 0xfff09c1c
                                                                            == 0xc1300810
                                                                        {
                                                                            return Some (BFMLAL_SME_ZA_array_off2x2_S_S_SVE_ZnxN_S_H_SME_Zm_S_H :: make_opcode (insn)) ;
                                                                        }
                                                                    }
                                                                } else {
                                                                    if insn & 0x010000 == 0 {
                                                                        if insn & 0xffe19c3c
                                                                            == 0xc1a00810
                                                                        {
                                                                            return Some (BFMLAL_SME_ZA_array_off2x2_SME_Znx2_SME_Zmx2 :: make_opcode (insn)) ;
                                                                        }
                                                                    } else {
                                                                        if insn & 0xffe39c7c
                                                                            == 0xc1a10810
                                                                        {
                                                                            return Some (BFMLAL_SME_ZA_array_off2x2_SME_Znx4_SME_Zmx4 :: make_opcode (insn)) ;
                                                                        }
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0x800000 == 0 {
                                                                    if insn & 0x100000 == 0 {
                                                                        if insn & 0xfff09c1c
                                                                            == 0xc1600810
                                                                        {
                                                                            return Some (UMLAL_SME_ZA_array_off2x2_SVE_ZnxN_SME_Zm :: make_opcode (insn)) ;
                                                                        }
                                                                    } else {
                                                                        if insn & 0xfff09c1c
                                                                            == 0xc1700810
                                                                        {
                                                                            return Some (UMLAL_SME_ZA_array_off2x2_S_S_SVE_ZnxN_S_H_SME_Zm_S_H :: make_opcode (insn)) ;
                                                                        }
                                                                    }
                                                                } else {
                                                                    if insn & 0x010000 == 0 {
                                                                        if insn & 0xffe19c3c
                                                                            == 0xc1e00810
                                                                        {
                                                                            return Some (UMLAL_SME_ZA_array_off2x2_SME_Znx2_SME_Zmx2 :: make_opcode (insn)) ;
                                                                        }
                                                                    } else {
                                                                        if insn & 0xffe39c7c
                                                                            == 0xc1e10810
                                                                        {
                                                                            return Some (UMLAL_SME_ZA_array_off2x2_SME_Znx4_SME_Zmx4 :: make_opcode (insn)) ;
                                                                        }
                                                                    }
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x800000 == 0 {
                                                                if insn & 0x100000 == 0 {
                                                                    if insn & 0xffb09c18
                                                                        == 0xc1201810
                                                                    {
                                                                        return Some (ADD_SME_ZA_array_off3_0_SVE_ZnxN_SME_Zm :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xffb09c18
                                                                        == 0xc1301810
                                                                    {
                                                                        return Some (ADD_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_S_SME_Zm_S_S :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0x010000 == 0 {
                                                                    if insn & 0xffa19c38
                                                                        == 0xc1a01810
                                                                    {
                                                                        return Some (ADD_SME_ZA_array_off3_0_SME_Znx2_SME_Zmx2 :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xffa39c78
                                                                        == 0xc1a11810
                                                                    {
                                                                        return Some (ADD_SME_ZA_array_off3_0_SME_Znx4_SME_Zmx4 :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            }
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x000800 == 0 {
                                                        if insn & 0x001000 == 0 {
                                                            if insn & 0xffb09c1c == 0xc1200410 {
                                                                return Some (UMLALL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0x800000 == 0 {
                                                                if insn & 0x100000 == 0 {
                                                                    if insn & 0xffb09c18
                                                                        == 0xc1201410
                                                                    {
                                                                        return Some (UDOT_SME_ZA_array_off3_0_SVE_ZnxN_SME_Zm :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xffb09c18
                                                                        == 0xc1301410
                                                                    {
                                                                        return Some (UDOT_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_B_SME_Zm_S_B :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0x010000 == 0 {
                                                                    if insn & 0xffa19c38
                                                                        == 0xc1a01410
                                                                    {
                                                                        return Some (UDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zmx2 :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xffa39c78
                                                                        == 0xc1a11410
                                                                    {
                                                                        return Some (UDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zmx4 :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x001000 == 0 {
                                                            if insn & 0x400000 == 0 {
                                                                if insn & 0xfff09c18 == 0xc1200c10 {
                                                                    return Some (BFMLAL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xfff09c18 == 0xc1600c10 {
                                                                    return Some (UMLAL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x010000 == 0 {
                                                                if insn & 0xffbf9c38 == 0xc1a01c10 {
                                                                    return Some (ADD_SME_ZA_array_off3_0_SME_Znx2 :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xffbf9c78 == 0xc1a11c10 {
                                                                    return Some (ADD_SME_ZA_array_off3_0_SME_Znx4 :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        }
                                                    }
                                                }
                                            }
                                        } else {
                                            if insn & 0x000010 == 0 {
                                                if insn & 0x000400 == 0 {
                                                    if insn & 0x000800 == 0 {
                                                        if insn & 0x800000 == 0 {
                                                            if insn & 0x100000 == 0 {
                                                                if insn & 0xffb09c1e == 0xc1200008 {
                                                                    return Some (SMLSLL_SME_ZA_array_off1x4_SVE_ZnxN_SME_Zm :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xffb09c1e == 0xc1300008 {
                                                                    return Some (SMLSLL_SME_ZA_array_off1x4_S_S_SVE_ZnxN_S_B_SME_Zm_S_B :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x010000 == 0 {
                                                                if insn & 0xffa19c3e == 0xc1a00008 {
                                                                    return Some (SMLSLL_SME_ZA_array_off1x4_SME_Znx2_SME_Zmx2 :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xffa39c7e == 0xc1a10008 {
                                                                    return Some (SMLSLL_SME_ZA_array_off1x4_SME_Znx4_SME_Zmx4 :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x001000 == 0 {
                                                            if insn & 0x400000 == 0 {
                                                                if insn & 0x800000 == 0 {
                                                                    if insn & 0x100000 == 0 {
                                                                        if insn & 0xfff09c1c
                                                                            == 0xc1200808
                                                                        {
                                                                            return Some (FMLSL_SME_ZA_array_off2x2_SVE_ZnxN_SME_Zm :: make_opcode (insn)) ;
                                                                        }
                                                                    } else {
                                                                        if insn & 0xfff09c1c
                                                                            == 0xc1300808
                                                                        {
                                                                            return Some (FMLSL_SME_ZA_array_off2x2_S_S_SVE_ZnxN_S_H_SME_Zm_S_H :: make_opcode (insn)) ;
                                                                        }
                                                                    }
                                                                } else {
                                                                    if insn & 0x010000 == 0 {
                                                                        if insn & 0xffe19c3c
                                                                            == 0xc1a00808
                                                                        {
                                                                            return Some (FMLSL_SME_ZA_array_off2x2_SME_Znx2_SME_Zmx2 :: make_opcode (insn)) ;
                                                                        }
                                                                    } else {
                                                                        if insn & 0xffe39c7c
                                                                            == 0xc1a10808
                                                                        {
                                                                            return Some (FMLSL_SME_ZA_array_off2x2_SME_Znx4_SME_Zmx4 :: make_opcode (insn)) ;
                                                                        }
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0x800000 == 0 {
                                                                    if insn & 0x100000 == 0 {
                                                                        if insn & 0xfff09c1c
                                                                            == 0xc1600808
                                                                        {
                                                                            return Some (SMLSL_SME_ZA_array_off2x2_SVE_ZnxN_SME_Zm :: make_opcode (insn)) ;
                                                                        }
                                                                    } else {
                                                                        if insn & 0xfff09c1c
                                                                            == 0xc1700808
                                                                        {
                                                                            return Some (SMLSL_SME_ZA_array_off2x2_S_S_SVE_ZnxN_S_H_SME_Zm_S_H :: make_opcode (insn)) ;
                                                                        }
                                                                    }
                                                                } else {
                                                                    if insn & 0x010000 == 0 {
                                                                        if insn & 0xffe19c3c
                                                                            == 0xc1e00808
                                                                        {
                                                                            return Some (SMLSL_SME_ZA_array_off2x2_SME_Znx2_SME_Zmx2 :: make_opcode (insn)) ;
                                                                        }
                                                                    } else {
                                                                        if insn & 0xffe39c7c
                                                                            == 0xc1e10808
                                                                        {
                                                                            return Some (SMLSL_SME_ZA_array_off2x2_SME_Znx4_SME_Zmx4 :: make_opcode (insn)) ;
                                                                        }
                                                                    }
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x800000 == 0 {
                                                                if insn & 0x100000 == 0 {
                                                                    if insn & 0xffb09c18
                                                                        == 0xc1201808
                                                                    {
                                                                        return Some (FMLS_SME_ZA_array_off3_0_SVE_ZnxN_SME_Zm :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xffb09c18
                                                                        == 0xc1301808
                                                                    {
                                                                        return Some (FMLS_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_S_SME_Zm_S_S :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0x010000 == 0 {
                                                                    if insn & 0xffa19c38
                                                                        == 0xc1a01808
                                                                    {
                                                                        return Some (FMLS_SME_ZA_array_off3_0_SME_Znx2_SME_Zmx2 :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xffa39c78
                                                                        == 0xc1a11808
                                                                    {
                                                                        return Some (FMLS_SME_ZA_array_off3_0_SME_Znx4_SME_Zmx4 :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            }
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x000800 == 0 {
                                                        if insn & 0x001000 == 0 {
                                                            if insn & 0xffb09c1c == 0xc1200408 {
                                                                return Some (SMLSLL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0x400000 == 0 {
                                                                if insn & 0x800000 == 0 {
                                                                    if insn & 0x100000 == 0 {
                                                                        if insn & 0xfff09c18
                                                                            == 0xc1201408
                                                                        {
                                                                            return Some (USDOT_SME_ZA_array_off3_0_SVE_ZnxN_SME_Zm :: make_opcode (insn)) ;
                                                                        }
                                                                    } else {
                                                                        if insn & 0xfff09c18
                                                                            == 0xc1301408
                                                                        {
                                                                            return Some (USDOT_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_B_SME_Zm_S_B :: make_opcode (insn)) ;
                                                                        }
                                                                    }
                                                                } else {
                                                                    if insn & 0x010000 == 0 {
                                                                        if insn & 0xffe19c38
                                                                            == 0xc1a01408
                                                                        {
                                                                            return Some (USDOT_SME_ZA_array_off3_0_SME_Znx2_SME_Zmx2 :: make_opcode (insn)) ;
                                                                        }
                                                                    } else {
                                                                        if insn & 0xffe39c78
                                                                            == 0xc1a11408
                                                                        {
                                                                            return Some (USDOT_SME_ZA_array_off3_0_SME_Znx4_SME_Zmx4 :: make_opcode (insn)) ;
                                                                        }
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0x800000 == 0 {
                                                                    if insn & 0x100000 == 0 {
                                                                        if insn & 0xfff09c18
                                                                            == 0xc1601408
                                                                        {
                                                                            return Some (SDOT_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_H_SME_Zm_S_H :: make_opcode (insn)) ;
                                                                        }
                                                                    } else {
                                                                        if insn & 0xfff09c18
                                                                            == 0xc1701408
                                                                        {
                                                                            return Some (SDOT_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_H_SME_Zm_S_H_c1701408 :: make_opcode (insn)) ;
                                                                        }
                                                                    }
                                                                } else {
                                                                    if insn & 0x010000 == 0 {
                                                                        if insn & 0xffe19c38
                                                                            == 0xc1e01408
                                                                        {
                                                                            return Some (SDOT_SME_ZA_array_off3_0_S_S_SME_Znx2_S_H_SME_Zmx2_S_H :: make_opcode (insn)) ;
                                                                        }
                                                                    } else {
                                                                        if insn & 0xffe39c78
                                                                            == 0xc1e11408
                                                                        {
                                                                            return Some (SDOT_SME_ZA_array_off3_0_S_S_SME_Znx4_S_H_SME_Zmx4_S_H :: make_opcode (insn)) ;
                                                                        }
                                                                    }
                                                                }
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x001000 == 0 {
                                                            if insn & 0x400000 == 0 {
                                                                if insn & 0xfff09c18 == 0xc1200c08 {
                                                                    return Some (FMLSL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xfff09c18 == 0xc1600c08 {
                                                                    return Some (SMLSL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x010000 == 0 {
                                                                if insn & 0xffbf9c38 == 0xc1a01c08 {
                                                                    return Some (FSUB_SME_ZA_array_off3_0_SME_Znx2 :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xffbf9c78 == 0xc1a11c08 {
                                                                    return Some (FSUB_SME_ZA_array_off3_0_SME_Znx4 :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0x000400 == 0 {
                                                    if insn & 0x000800 == 0 {
                                                        if insn & 0x800000 == 0 {
                                                            if insn & 0x100000 == 0 {
                                                                if insn & 0xffb09c1e == 0xc1200018 {
                                                                    return Some (UMLSLL_SME_ZA_array_off1x4_SVE_ZnxN_SME_Zm :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xffb09c1e == 0xc1300018 {
                                                                    return Some (UMLSLL_SME_ZA_array_off1x4_S_S_SVE_ZnxN_S_B_SME_Zm_S_B :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x010000 == 0 {
                                                                if insn & 0xffa19c3e == 0xc1a00018 {
                                                                    return Some (UMLSLL_SME_ZA_array_off1x4_SME_Znx2_SME_Zmx2 :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xffa39c7e == 0xc1a10018 {
                                                                    return Some (UMLSLL_SME_ZA_array_off1x4_SME_Znx4_SME_Zmx4 :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x001000 == 0 {
                                                            if insn & 0x400000 == 0 {
                                                                if insn & 0x800000 == 0 {
                                                                    if insn & 0x100000 == 0 {
                                                                        if insn & 0xfff09c1c
                                                                            == 0xc1200818
                                                                        {
                                                                            return Some (BFMLSL_SME_ZA_array_off2x2_SVE_ZnxN_SME_Zm :: make_opcode (insn)) ;
                                                                        }
                                                                    } else {
                                                                        if insn & 0xfff09c1c
                                                                            == 0xc1300818
                                                                        {
                                                                            return Some (BFMLSL_SME_ZA_array_off2x2_S_S_SVE_ZnxN_S_H_SME_Zm_S_H :: make_opcode (insn)) ;
                                                                        }
                                                                    }
                                                                } else {
                                                                    if insn & 0x010000 == 0 {
                                                                        if insn & 0xffe19c3c
                                                                            == 0xc1a00818
                                                                        {
                                                                            return Some (BFMLSL_SME_ZA_array_off2x2_SME_Znx2_SME_Zmx2 :: make_opcode (insn)) ;
                                                                        }
                                                                    } else {
                                                                        if insn & 0xffe39c7c
                                                                            == 0xc1a10818
                                                                        {
                                                                            return Some (BFMLSL_SME_ZA_array_off2x2_SME_Znx4_SME_Zmx4 :: make_opcode (insn)) ;
                                                                        }
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0x800000 == 0 {
                                                                    if insn & 0x100000 == 0 {
                                                                        if insn & 0xfff09c1c
                                                                            == 0xc1600818
                                                                        {
                                                                            return Some (UMLSL_SME_ZA_array_off2x2_SVE_ZnxN_SME_Zm :: make_opcode (insn)) ;
                                                                        }
                                                                    } else {
                                                                        if insn & 0xfff09c1c
                                                                            == 0xc1700818
                                                                        {
                                                                            return Some (UMLSL_SME_ZA_array_off2x2_S_S_SVE_ZnxN_S_H_SME_Zm_S_H :: make_opcode (insn)) ;
                                                                        }
                                                                    }
                                                                } else {
                                                                    if insn & 0x010000 == 0 {
                                                                        if insn & 0xffe19c3c
                                                                            == 0xc1e00818
                                                                        {
                                                                            return Some (UMLSL_SME_ZA_array_off2x2_SME_Znx2_SME_Zmx2 :: make_opcode (insn)) ;
                                                                        }
                                                                    } else {
                                                                        if insn & 0xffe39c7c
                                                                            == 0xc1e10818
                                                                        {
                                                                            return Some (UMLSL_SME_ZA_array_off2x2_SME_Znx4_SME_Zmx4 :: make_opcode (insn)) ;
                                                                        }
                                                                    }
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x800000 == 0 {
                                                                if insn & 0x100000 == 0 {
                                                                    if insn & 0xffb09c18
                                                                        == 0xc1201818
                                                                    {
                                                                        return Some (SUB_SME_ZA_array_off3_0_SVE_ZnxN_SME_Zm :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xffb09c18
                                                                        == 0xc1301818
                                                                    {
                                                                        return Some (SUB_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_S_SME_Zm_S_S :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0x010000 == 0 {
                                                                    if insn & 0xffa19c38
                                                                        == 0xc1a01818
                                                                    {
                                                                        return Some (SUB_SME_ZA_array_off3_0_SME_Znx2_SME_Zmx2 :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xffa39c78
                                                                        == 0xc1a11818
                                                                    {
                                                                        return Some (SUB_SME_ZA_array_off3_0_SME_Znx4_SME_Zmx4 :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            }
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x000800 == 0 {
                                                        if insn & 0x001000 == 0 {
                                                            if insn & 0xffb09c1c == 0xc1200418 {
                                                                return Some (UMLSLL_SME_ZA_array_off2x4_SVE_Zn_SME_Zm :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0x400000 == 0 {
                                                                if insn & 0x100000 == 0 {
                                                                    if insn & 0xfff09c18
                                                                        == 0xc1201418
                                                                    {
                                                                        return Some (SUDOT_SME_ZA_array_off3_0_SVE_ZnxN_SME_Zm :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xfff09c18
                                                                        == 0xc1301418
                                                                    {
                                                                        return Some (SUDOT_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_B_SME_Zm_S_B :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0x800000 == 0 {
                                                                    if insn & 0x100000 == 0 {
                                                                        if insn & 0xfff09c18
                                                                            == 0xc1601418
                                                                        {
                                                                            return Some (UDOT_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_H_SME_Zm_S_H :: make_opcode (insn)) ;
                                                                        }
                                                                    } else {
                                                                        if insn & 0xfff09c18
                                                                            == 0xc1701418
                                                                        {
                                                                            return Some (UDOT_SME_ZA_array_off3_0_S_S_SVE_ZnxN_S_H_SME_Zm_S_H_c1701418 :: make_opcode (insn)) ;
                                                                        }
                                                                    }
                                                                } else {
                                                                    if insn & 0x010000 == 0 {
                                                                        if insn & 0xffe19c38
                                                                            == 0xc1e01418
                                                                        {
                                                                            return Some (UDOT_SME_ZA_array_off3_0_S_S_SME_Znx2_S_H_SME_Zmx2_S_H :: make_opcode (insn)) ;
                                                                        }
                                                                    } else {
                                                                        if insn & 0xffe39c78
                                                                            == 0xc1e11418
                                                                        {
                                                                            return Some (UDOT_SME_ZA_array_off3_0_S_S_SME_Znx4_S_H_SME_Zmx4_S_H :: make_opcode (insn)) ;
                                                                        }
                                                                    }
                                                                }
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x001000 == 0 {
                                                            if insn & 0x400000 == 0 {
                                                                if insn & 0xfff09c18 == 0xc1200c18 {
                                                                    return Some (BFMLSL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xfff09c18 == 0xc1600c18 {
                                                                    return Some (UMLSL_SME_ZA_array_off3x2_SVE_Zn_SME_Zm :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x010000 == 0 {
                                                                if insn & 0xffbf9c38 == 0xc1a01c18 {
                                                                    return Some (SUB_SME_ZA_array_off3_0_SME_Znx2 :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xffbf9c78 == 0xc1a11c18 {
                                                                    return Some (SUB_SME_ZA_array_off3_0_SME_Znx4 :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        }
                                                    }
                                                }
                                            }
                                        }
                                    } else {
                                        if insn & 0x002000 == 0 {
                                            if insn & 0x004000 == 0 {
                                                if insn & 0x010000 == 0 {
                                                    if insn & 0xff21e021 == 0xc1208000 {
                                                        return Some (SEL_SME_Zdnx2_SME_PNg3_SME_Znx2_SME_Zmx2 :: make_opcode (insn)) ;
                                                    }
                                                } else {
                                                    if insn & 0xff23e063 == 0xc1218000 {
                                                        return Some (SEL_SME_Zdnx4_SME_PNg3_SME_Znx4_SME_Zmx4 :: make_opcode (insn)) ;
                                                    }
                                                }
                                            } else {
                                                if insn & 0x000400 == 0 {
                                                    if insn & 0x000800 == 0 {
                                                        if insn & 0x000001 == 0 {
                                                            if insn & 0x001000 == 0 {
                                                                if insn & 0xff20fc01 == 0xc120c000 {
                                                                    return Some (FCLAMP_SME_Zdnx2_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xff20fc01 == 0xc120d000 {
                                                                    return Some (ZIP_SME_Zdnx2_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0xff20fc01 == 0xc120d001 {
                                                                return Some (UZP_SME_Zdnx2_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x001000 == 0 {
                                                            if insn & 0xff20fc03 == 0xc120c800 {
                                                                return Some (FCLAMP_SME_Zdnx4_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0x000020 == 0 {
                                                                if insn & 0x000040 == 0 {
                                                                    if insn & 0xff20fc60
                                                                        == 0xc120d800
                                                                    {
                                                                        return Some (SQRSHR_SVE_Zd_SME_Znx4_SME_SHRIMM5 :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xff20fc60
                                                                        == 0xc120d840
                                                                    {
                                                                        return Some (SQRSHRU_SVE_Zd_SME_Znx4_SME_SHRIMM5 :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0xff20fc60 == 0xc120d820 {
                                                                    return Some (UQRSHR_SVE_Zd_SME_Znx4_SME_SHRIMM5 :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x000800 == 0 {
                                                        if insn & 0x001000 == 0 {
                                                            if insn & 0x000001 == 0 {
                                                                if insn & 0xff20fc01 == 0xc120c400 {
                                                                    return Some (SCLAMP_SME_Zdnx2_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xff20fc01 == 0xc120c401 {
                                                                    return Some (UCLAMP_SME_Zdnx2_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x400000 == 0 {
                                                                if insn & 0x000001 == 0 {
                                                                    if insn & 0xffe0fc01
                                                                        == 0xc120d400
                                                                    {
                                                                        return Some (ZIP_SME_Zdnx2_S_Q_SVE_Zn_S_Q_SVE_Zm_16_S_Q :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xffe0fc01
                                                                        == 0xc120d401
                                                                    {
                                                                        return Some (UZP_SME_Zdnx2_S_Q_SVE_Zn_S_Q_SVE_Zm_16_S_Q :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0x000020 == 0 {
                                                                    if insn & 0x100000 == 0 {
                                                                        if insn & 0xfff0fc20
                                                                            == 0xc1e0d400
                                                                        {
                                                                            return Some (SQRSHR_SVE_Zd_SME_Znx2_SME_SHRIMM4 :: make_opcode (insn)) ;
                                                                        }
                                                                    } else {
                                                                        if insn & 0xfff0fc20
                                                                            == 0xc1f0d400
                                                                        {
                                                                            return Some (SQRSHRU_SVE_Zd_SME_Znx2_SME_SHRIMM4 :: make_opcode (insn)) ;
                                                                        }
                                                                    }
                                                                } else {
                                                                    if insn & 0xfff0fc20
                                                                        == 0xc1e0d420
                                                                    {
                                                                        return Some (UQRSHR_SVE_Zd_SME_Znx2_SME_SHRIMM4 :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x001000 == 0 {
                                                            if insn & 0x000001 == 0 {
                                                                if insn & 0xff20fc03 == 0xc120cc00 {
                                                                    return Some (SCLAMP_SME_Zdnx4_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xff20fc03 == 0xc120cc01 {
                                                                    return Some (UCLAMP_SME_Zdnx4_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x000020 == 0 {
                                                                if insn & 0x000040 == 0 {
                                                                    if insn & 0xff20fc60
                                                                        == 0xc120dc00
                                                                    {
                                                                        return Some (SQRSHRN_SVE_Zd_SME_Znx4_SME_SHRIMM5 :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xff20fc60
                                                                        == 0xc120dc40
                                                                    {
                                                                        return Some (SQRSHRUN_SVE_Zd_SME_Znx4_SME_SHRIMM5 :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0xff20fc60 == 0xc120dc20 {
                                                                    return Some (UQRSHRN_SVE_Zd_SME_Znx4_SME_SHRIMM5 :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        }
                                                    }
                                                }
                                            }
                                        } else {
                                            if insn & 0x000400 == 0 {
                                                if insn & 0x000800 == 0 {
                                                    if insn & 0x001000 == 0 {
                                                        if insn & 0x004000 == 0 {
                                                            if insn & 0x000001 == 0 {
                                                                if insn & 0x000020 == 0 {
                                                                    if insn & 0x000100 == 0 {
                                                                        if insn & 0xff30ffe1
                                                                            == 0xc120a000
                                                                        {
                                                                            return Some (SMAX_SME_Zdnx2_SME_Zdnx2_SME_Zm :: make_opcode (insn)) ;
                                                                        }
                                                                    } else {
                                                                        if insn & 0x000200 == 0 {
                                                                            if insn & 0xff30ffe1
                                                                                == 0xc120a100
                                                                            {
                                                                                return Some (FMAX_SME_Zdnx2_SME_Zdnx2_SME_Zm :: make_opcode (insn)) ;
                                                                            }
                                                                        } else {
                                                                            if insn & 0xff30ffe1
                                                                                == 0xc120a300
                                                                            {
                                                                                return Some (ADD_SME_Zdnx2_SME_Zdnx2_SME_Zm :: make_opcode (insn)) ;
                                                                            }
                                                                        }
                                                                    }
                                                                } else {
                                                                    if insn & 0x000100 == 0 {
                                                                        if insn & 0x000200 == 0 {
                                                                            if insn & 0xff30ffe1
                                                                                == 0xc120a020
                                                                            {
                                                                                return Some (SMIN_SME_Zdnx2_SME_Zdnx2_SME_Zm :: make_opcode (insn)) ;
                                                                            }
                                                                        } else {
                                                                            if insn & 0xff30ffe1
                                                                                == 0xc120a220
                                                                            {
                                                                                return Some (SRSHL_SME_Zdnx2_SME_Zdnx2_SME_Zm :: make_opcode (insn)) ;
                                                                            }
                                                                        }
                                                                    } else {
                                                                        if insn & 0xff30ffe1
                                                                            == 0xc120a120
                                                                        {
                                                                            return Some (FMAXNM_SME_Zdnx2_SME_Zdnx2_SME_Zm :: make_opcode (insn)) ;
                                                                        }
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0x000020 == 0 {
                                                                    if insn & 0x000100 == 0 {
                                                                        if insn & 0xff30ffe1
                                                                            == 0xc120a001
                                                                        {
                                                                            return Some (UMAX_SME_Zdnx2_SME_Zdnx2_SME_Zm :: make_opcode (insn)) ;
                                                                        }
                                                                    } else {
                                                                        if insn & 0xff30ffe1
                                                                            == 0xc120a101
                                                                        {
                                                                            return Some (FMIN_SME_Zdnx2_SME_Zdnx2_SME_Zm :: make_opcode (insn)) ;
                                                                        }
                                                                    }
                                                                } else {
                                                                    if insn & 0x000100 == 0 {
                                                                        if insn & 0x000200 == 0 {
                                                                            if insn & 0xff30ffe1
                                                                                == 0xc120a021
                                                                            {
                                                                                return Some (UMIN_SME_Zdnx2_SME_Zdnx2_SME_Zm :: make_opcode (insn)) ;
                                                                            }
                                                                        } else {
                                                                            if insn & 0xff30ffe1
                                                                                == 0xc120a221
                                                                            {
                                                                                return Some (URSHL_SME_Zdnx2_SME_Zdnx2_SME_Zm :: make_opcode (insn)) ;
                                                                            }
                                                                        }
                                                                    } else {
                                                                        if insn & 0xff30ffe1
                                                                            == 0xc120a121
                                                                        {
                                                                            return Some (FMINNM_SME_Zdnx2_SME_Zdnx2_SME_Zm :: make_opcode (insn)) ;
                                                                        }
                                                                    }
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x010000 == 0 {
                                                                if insn & 0x000020 == 0 {
                                                                    if insn & 0x020000 == 0 {
                                                                        if insn & 0x040000 == 0 {
                                                                            if insn & 0x080000 == 0
                                                                            {
                                                                                if insn & 0x400000
                                                                                    == 0
                                                                                {
                                                                                    if insn & 0xfffffc20 == 0xc120e000 { return Some (FCVT_SVE_Zd_SME_Znx2 :: make_opcode (insn)) ; }
                                                                                } else {
                                                                                    if insn & 0xfffffc20 == 0xc160e000 { return Some (BFCVT_SVE_Zd_SME_Znx2 :: make_opcode (insn)) ; }
                                                                                }
                                                                            } else {
                                                                                if insn & 0x100000
                                                                                    == 0
                                                                                {
                                                                                    if insn & 0xfffffc21 == 0xc1a8e000 { return Some (FRINTN_SME_Zdnx2_SME_Znx2 :: make_opcode (insn)) ; }
                                                                                } else {
                                                                                    if insn & 0xfffffc63 == 0xc1b8e000 { return Some (FRINTN_SME_Zdnx4_SME_Znx4 :: make_opcode (insn)) ; }
                                                                                }
                                                                            }
                                                                        } else {
                                                                            if insn & 0x100000 == 0
                                                                            {
                                                                                if insn & 0xfffffc21
                                                                                    == 0xc1ace000
                                                                                {
                                                                                    return Some (FRINTA_SME_Zdnx2_SME_Znx2 :: make_opcode (insn)) ;
                                                                                }
                                                                            } else {
                                                                                if insn & 0xfffffc63
                                                                                    == 0xc1bce000
                                                                                {
                                                                                    return Some (FRINTA_SME_Zdnx4_SME_Znx4 :: make_opcode (insn)) ;
                                                                                }
                                                                            }
                                                                        }
                                                                    } else {
                                                                        if insn & 0x040000 == 0 {
                                                                            if insn & 0x080000 == 0
                                                                            {
                                                                                if insn & 0x100000
                                                                                    == 0
                                                                                {
                                                                                    if insn & 0xfffffc21 == 0xc122e000 { return Some (SCVTF_SME_Zdnx2_SME_Znx2 :: make_opcode (insn)) ; }
                                                                                } else {
                                                                                    if insn & 0xfffffc63 == 0xc132e000 { return Some (SCVTF_SME_Zdnx4_SME_Znx4 :: make_opcode (insn)) ; }
                                                                                }
                                                                            } else {
                                                                                if insn & 0x100000
                                                                                    == 0
                                                                                {
                                                                                    if insn & 0xfffffc21 == 0xc1aae000 { return Some (FRINTM_SME_Zdnx2_SME_Znx2 :: make_opcode (insn)) ; }
                                                                                } else {
                                                                                    if insn & 0xfffffc63 == 0xc1bae000 { return Some (FRINTM_SME_Zdnx4_SME_Znx4 :: make_opcode (insn)) ; }
                                                                                }
                                                                            }
                                                                        } else {
                                                                            if insn & 0x000002 == 0
                                                                            {
                                                                                if insn & 0xff3ffc63
                                                                                    == 0xc136e000
                                                                                {
                                                                                    return Some (ZIP_SME_Zdnx4_SME_Znx4 :: make_opcode (insn)) ;
                                                                                }
                                                                            } else {
                                                                                if insn & 0xff3ffc63
                                                                                    == 0xc136e002
                                                                                {
                                                                                    return Some (UZP_SME_Zdnx4_SME_Znx4 :: make_opcode (insn)) ;
                                                                                }
                                                                            }
                                                                        }
                                                                    }
                                                                } else {
                                                                    if insn & 0x020000 == 0 {
                                                                        if insn & 0x400000 == 0 {
                                                                            if insn & 0xfffffc20
                                                                                == 0xc120e020
                                                                            {
                                                                                return Some (FCVTN_SVE_Zd_SME_Znx2 :: make_opcode (insn)) ;
                                                                            }
                                                                        } else {
                                                                            if insn & 0xfffffc20
                                                                                == 0xc160e020
                                                                            {
                                                                                return Some (BFCVTN_SVE_Zd_SME_Znx2 :: make_opcode (insn)) ;
                                                                            }
                                                                        }
                                                                    } else {
                                                                        if insn & 0x100000 == 0 {
                                                                            if insn & 0xfffffc21
                                                                                == 0xc122e020
                                                                            {
                                                                                return Some (UCVTF_SME_Zdnx2_SME_Znx2 :: make_opcode (insn)) ;
                                                                            }
                                                                        } else {
                                                                            if insn & 0xfffffc63
                                                                                == 0xc132e020
                                                                            {
                                                                                return Some (UCVTF_SME_Zdnx4_SME_Znx4 :: make_opcode (insn)) ;
                                                                            }
                                                                        }
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0x020000 == 0 {
                                                                    if insn & 0x000001 == 0 {
                                                                        if insn & 0x040000 == 0 {
                                                                            if insn & 0x000020 == 0
                                                                            {
                                                                                if insn & 0x080000
                                                                                    == 0
                                                                                {
                                                                                    if insn
                                                                                        & 0x100000
                                                                                        == 0
                                                                                    {
                                                                                        if insn & 0xfffffc21 == 0xc121e000 { return Some (FCVTZS_SME_Zdnx2_SME_Znx2 :: make_opcode (insn)) ; }
                                                                                    } else {
                                                                                        if insn & 0xfffffc63 == 0xc131e000 { return Some (FCVTZS_SME_Zdnx4_SME_Znx4 :: make_opcode (insn)) ; }
                                                                                    }
                                                                                } else {
                                                                                    if insn
                                                                                        & 0x100000
                                                                                        == 0
                                                                                    {
                                                                                        if insn & 0xfffffc21 == 0xc1a9e000 { return Some (FRINTP_SME_Zdnx2_SME_Znx2 :: make_opcode (insn)) ; }
                                                                                    } else {
                                                                                        if insn & 0xfffffc63 == 0xc1b9e000 { return Some (FRINTP_SME_Zdnx4_SME_Znx4 :: make_opcode (insn)) ; }
                                                                                    }
                                                                                }
                                                                            } else {
                                                                                if insn & 0x100000
                                                                                    == 0
                                                                                {
                                                                                    if insn & 0xfffffc21 == 0xc121e020 { return Some (FCVTZU_SME_Zdnx2_SME_Znx2 :: make_opcode (insn)) ; }
                                                                                } else {
                                                                                    if insn & 0xfffffc63 == 0xc131e020 { return Some (FCVTZU_SME_Zdnx4_SME_Znx4 :: make_opcode (insn)) ; }
                                                                                }
                                                                            }
                                                                        } else {
                                                                            if insn & 0x100000 == 0
                                                                            {
                                                                                if insn & 0xff3ffc01
                                                                                    == 0xc125e000
                                                                                {
                                                                                    return Some (SUNPK_SME_Zdnx2_SVE_Zn :: make_opcode (insn)) ;
                                                                                }
                                                                            } else {
                                                                                if insn & 0xff3ffc23
                                                                                    == 0xc135e000
                                                                                {
                                                                                    return Some (SUNPK_SME_Zdnx4_SME_Znx2 :: make_opcode (insn)) ;
                                                                                }
                                                                            }
                                                                        }
                                                                    } else {
                                                                        if insn & 0x100000 == 0 {
                                                                            if insn & 0xff3ffc01
                                                                                == 0xc125e001
                                                                            {
                                                                                return Some (UUNPK_SME_Zdnx2_SVE_Zn :: make_opcode (insn)) ;
                                                                            }
                                                                        } else {
                                                                            if insn & 0xff3ffc23
                                                                                == 0xc135e001
                                                                            {
                                                                                return Some (UUNPK_SME_Zdnx4_SME_Znx2 :: make_opcode (insn)) ;
                                                                            }
                                                                        }
                                                                    }
                                                                } else {
                                                                    if insn & 0x000020 == 0 {
                                                                        if insn & 0x040000 == 0 {
                                                                            if insn & 0x100000 == 0
                                                                            {
                                                                                if insn & 0x400000
                                                                                    == 0
                                                                                {
                                                                                    if insn & 0xfffffc20 == 0xc123e000 { return Some (SQCVT_SVE_Zd_SME_Znx2 :: make_opcode (insn)) ; }
                                                                                } else {
                                                                                    if insn & 0xfffffc20 == 0xc163e000 { return Some (SQCVTU_SVE_Zd_SME_Znx2 :: make_opcode (insn)) ; }
                                                                                }
                                                                            } else {
                                                                                if insn & 0x000040
                                                                                    == 0
                                                                                {
                                                                                    if insn
                                                                                        & 0x400000
                                                                                        == 0
                                                                                    {
                                                                                        if insn & 0xff7ffc60 == 0xc133e000 { return Some (SQCVT_SVE_Zd_SME_Znx4 :: make_opcode (insn)) ; }
                                                                                    } else {
                                                                                        if insn & 0xff7ffc60 == 0xc173e000 { return Some (SQCVTU_SVE_Zd_SME_Znx4 :: make_opcode (insn)) ; }
                                                                                    }
                                                                                } else {
                                                                                    if insn
                                                                                        & 0x400000
                                                                                        == 0
                                                                                    {
                                                                                        if insn & 0xff7ffc60 == 0xc133e040 { return Some (SQCVTN_SVE_Zd_SME_Znx4 :: make_opcode (insn)) ; }
                                                                                    } else {
                                                                                        if insn & 0xff7ffc60 == 0xc173e040 { return Some (SQCVTUN_SVE_Zd_SME_Znx4 :: make_opcode (insn)) ; }
                                                                                    }
                                                                                }
                                                                            }
                                                                        } else {
                                                                            if insn & 0x000002 == 0
                                                                            {
                                                                                if insn & 0xfffffc63
                                                                                    == 0xc137e000
                                                                                {
                                                                                    return Some (ZIP_SME_Zdnx4_S_Q_SME_Znx4_S_Q :: make_opcode (insn)) ;
                                                                                }
                                                                            } else {
                                                                                if insn & 0xfffffc63
                                                                                    == 0xc137e002
                                                                                {
                                                                                    return Some (UZP_SME_Zdnx4_S_Q_SME_Znx4_S_Q :: make_opcode (insn)) ;
                                                                                }
                                                                            }
                                                                        }
                                                                    } else {
                                                                        if insn & 0x100000 == 0 {
                                                                            if insn & 0xfffffc20
                                                                                == 0xc123e020
                                                                            {
                                                                                return Some (UQCVT_SVE_Zd_SME_Znx2 :: make_opcode (insn)) ;
                                                                            }
                                                                        } else {
                                                                            if insn & 0x000040 == 0
                                                                            {
                                                                                if insn & 0xff7ffc60
                                                                                    == 0xc133e020
                                                                                {
                                                                                    return Some (UQCVT_SVE_Zd_SME_Znx4 :: make_opcode (insn)) ;
                                                                                }
                                                                            } else {
                                                                                if insn & 0xff7ffc60
                                                                                    == 0xc133e060
                                                                                {
                                                                                    return Some (UQCVTN_SVE_Zd_SME_Znx4 :: make_opcode (insn)) ;
                                                                                }
                                                                            }
                                                                        }
                                                                    }
                                                                }
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x000001 == 0 {
                                                            if insn & 0x000020 == 0 {
                                                                if insn & 0x000100 == 0 {
                                                                    if insn & 0xff21ffe1
                                                                        == 0xc120b000
                                                                    {
                                                                        return Some (SMAX_SME_Zdnx2_SME_Zdnx2_SME_Zmx2 :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xff21ffe1
                                                                        == 0xc120b100
                                                                    {
                                                                        return Some (FMAX_SME_Zdnx2_SME_Zdnx2_SME_Zmx2 :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0x000100 == 0 {
                                                                    if insn & 0x000200 == 0 {
                                                                        if insn & 0xff21ffe1
                                                                            == 0xc120b020
                                                                        {
                                                                            return Some (SMIN_SME_Zdnx2_SME_Zdnx2_SME_Zmx2 :: make_opcode (insn)) ;
                                                                        }
                                                                    } else {
                                                                        if insn & 0xff21ffe1
                                                                            == 0xc120b220
                                                                        {
                                                                            return Some (SRSHL_SME_Zdnx2_SME_Zdnx2_SME_Zmx2 :: make_opcode (insn)) ;
                                                                        }
                                                                    }
                                                                } else {
                                                                    if insn & 0xff21ffe1
                                                                        == 0xc120b120
                                                                    {
                                                                        return Some (FMAXNM_SME_Zdnx2_SME_Zdnx2_SME_Zmx2 :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x000020 == 0 {
                                                                if insn & 0x000100 == 0 {
                                                                    if insn & 0xff21ffe1
                                                                        == 0xc120b001
                                                                    {
                                                                        return Some (UMAX_SME_Zdnx2_SME_Zdnx2_SME_Zmx2 :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xff21ffe1
                                                                        == 0xc120b101
                                                                    {
                                                                        return Some (FMIN_SME_Zdnx2_SME_Zdnx2_SME_Zmx2 :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0x000100 == 0 {
                                                                    if insn & 0x000200 == 0 {
                                                                        if insn & 0xff21ffe1
                                                                            == 0xc120b021
                                                                        {
                                                                            return Some (UMIN_SME_Zdnx2_SME_Zdnx2_SME_Zmx2 :: make_opcode (insn)) ;
                                                                        }
                                                                    } else {
                                                                        if insn & 0xff21ffe1
                                                                            == 0xc120b221
                                                                        {
                                                                            return Some (URSHL_SME_Zdnx2_SME_Zdnx2_SME_Zmx2 :: make_opcode (insn)) ;
                                                                        }
                                                                    }
                                                                } else {
                                                                    if insn & 0xff21ffe1
                                                                        == 0xc120b121
                                                                    {
                                                                        return Some (FMINNM_SME_Zdnx2_SME_Zdnx2_SME_Zmx2 :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            }
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x000001 == 0 {
                                                        if insn & 0x000020 == 0 {
                                                            if insn & 0x000100 == 0 {
                                                                if insn & 0x001000 == 0 {
                                                                    if insn & 0xff30ffe3
                                                                        == 0xc120a800
                                                                    {
                                                                        return Some (SMAX_SME_Zdnx4_SME_Zdnx4_SME_Zm :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xff23ffe3
                                                                        == 0xc120b800
                                                                    {
                                                                        return Some (SMAX_SME_Zdnx4_SME_Zdnx4_SME_Zmx4 :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0x000200 == 0 {
                                                                    if insn & 0x001000 == 0 {
                                                                        if insn & 0xff30ffe3
                                                                            == 0xc120a900
                                                                        {
                                                                            return Some (FMAX_SME_Zdnx4_SME_Zdnx4_SME_Zm :: make_opcode (insn)) ;
                                                                        }
                                                                    } else {
                                                                        if insn & 0xff23ffe3
                                                                            == 0xc120b900
                                                                        {
                                                                            return Some (FMAX_SME_Zdnx4_SME_Zdnx4_SME_Zmx4 :: make_opcode (insn)) ;
                                                                        }
                                                                    }
                                                                } else {
                                                                    if insn & 0xff30ffe3
                                                                        == 0xc120ab00
                                                                    {
                                                                        return Some (ADD_SME_Zdnx4_SME_Zdnx4_SME_Zm :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x000100 == 0 {
                                                                if insn & 0x000200 == 0 {
                                                                    if insn & 0x001000 == 0 {
                                                                        if insn & 0xff30ffe3
                                                                            == 0xc120a820
                                                                        {
                                                                            return Some (SMIN_SME_Zdnx4_SME_Zdnx4_SME_Zm :: make_opcode (insn)) ;
                                                                        }
                                                                    } else {
                                                                        if insn & 0xff23ffe3
                                                                            == 0xc120b820
                                                                        {
                                                                            return Some (SMIN_SME_Zdnx4_SME_Zdnx4_SME_Zmx4 :: make_opcode (insn)) ;
                                                                        }
                                                                    }
                                                                } else {
                                                                    if insn & 0x001000 == 0 {
                                                                        if insn & 0xff30ffe3
                                                                            == 0xc120aa20
                                                                        {
                                                                            return Some (SRSHL_SME_Zdnx4_SME_Zdnx4_SME_Zm :: make_opcode (insn)) ;
                                                                        }
                                                                    } else {
                                                                        if insn & 0xff23ffe3
                                                                            == 0xc120ba20
                                                                        {
                                                                            return Some (SRSHL_SME_Zdnx4_SME_Zdnx4_SME_Zmx4 :: make_opcode (insn)) ;
                                                                        }
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0x001000 == 0 {
                                                                    if insn & 0xff30ffe3
                                                                        == 0xc120a920
                                                                    {
                                                                        return Some (FMAXNM_SME_Zdnx4_SME_Zdnx4_SME_Zm :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xff23ffe3
                                                                        == 0xc120b920
                                                                    {
                                                                        return Some (FMAXNM_SME_Zdnx4_SME_Zdnx4_SME_Zmx4 :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x000020 == 0 {
                                                            if insn & 0x000100 == 0 {
                                                                if insn & 0x001000 == 0 {
                                                                    if insn & 0xff30ffe3
                                                                        == 0xc120a801
                                                                    {
                                                                        return Some (UMAX_SME_Zdnx4_SME_Zdnx4_SME_Zm :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xff23ffe3
                                                                        == 0xc120b801
                                                                    {
                                                                        return Some (UMAX_SME_Zdnx4_SME_Zdnx4_SME_Zmx4 :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0x001000 == 0 {
                                                                    if insn & 0xff30ffe3
                                                                        == 0xc120a901
                                                                    {
                                                                        return Some (FMIN_SME_Zdnx4_SME_Zdnx4_SME_Zm :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xff23ffe3
                                                                        == 0xc120b901
                                                                    {
                                                                        return Some (FMIN_SME_Zdnx4_SME_Zdnx4_SME_Zmx4 :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x000100 == 0 {
                                                                if insn & 0x000200 == 0 {
                                                                    if insn & 0x001000 == 0 {
                                                                        if insn & 0xff30ffe3
                                                                            == 0xc120a821
                                                                        {
                                                                            return Some (UMIN_SME_Zdnx4_SME_Zdnx4_SME_Zm :: make_opcode (insn)) ;
                                                                        }
                                                                    } else {
                                                                        if insn & 0xff23ffe3
                                                                            == 0xc120b821
                                                                        {
                                                                            return Some (UMIN_SME_Zdnx4_SME_Zdnx4_SME_Zmx4 :: make_opcode (insn)) ;
                                                                        }
                                                                    }
                                                                } else {
                                                                    if insn & 0x001000 == 0 {
                                                                        if insn & 0xff30ffe3
                                                                            == 0xc120aa21
                                                                        {
                                                                            return Some (URSHL_SME_Zdnx4_SME_Zdnx4_SME_Zm :: make_opcode (insn)) ;
                                                                        }
                                                                    } else {
                                                                        if insn & 0xff23ffe3
                                                                            == 0xc120ba21
                                                                        {
                                                                            return Some (URSHL_SME_Zdnx4_SME_Zdnx4_SME_Zmx4 :: make_opcode (insn)) ;
                                                                        }
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0x001000 == 0 {
                                                                    if insn & 0xff30ffe3
                                                                        == 0xc120a921
                                                                    {
                                                                        return Some (FMINNM_SME_Zdnx4_SME_Zdnx4_SME_Zm :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xff23ffe3
                                                                        == 0xc120b921
                                                                    {
                                                                        return Some (FMINNM_SME_Zdnx4_SME_Zdnx4_SME_Zmx4 :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            }
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0x000800 == 0 {
                                                    if insn & 0x001000 == 0 {
                                                        if insn & 0xff30ffe1 == 0xc120a400 {
                                                            return Some (SQDMULH_SME_Zdnx2_SME_Zdnx2_SME_Zm :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xff21ffe1 == 0xc120b400 {
                                                            return Some (SQDMULH_SME_Zdnx2_SME_Zdnx2_SME_Zmx2 :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x001000 == 0 {
                                                        if insn & 0xff30ffe3 == 0xc120ac00 {
                                                            return Some (SQDMULH_SME_Zdnx4_SME_Zdnx4_SME_Zm :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xff23ffe3 == 0xc120bc00 {
                                                            return Some (SQDMULH_SME_Zdnx4_SME_Zdnx4_SME_Zmx4 :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                }
                                            }
                                        }
                                    }
                                }
                            } else {
                                if insn & 0x400000 == 0 {
                                    if insn & 0x800000 == 0 {
                                        if insn & 0x008000 == 0 {
                                            if insn & 0x40000000 == 0 {
                                                if insn & 0x000008 == 0 {
                                                    if insn & 0x002000 == 0 {
                                                        if insn & 0x004000 == 0 {
                                                            if insn & 0xffe0e008 == 0xa1200000 {
                                                                return Some (ST1B_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xffe0e008 == 0xa1204000 {
                                                                return Some (ST1W_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL2 :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x004000 == 0 {
                                                            if insn & 0xffe0e008 == 0xa1202000 {
                                                                return Some (ST1H_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL1 :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xffe0e008 == 0xa1206000 {
                                                                return Some (ST1D_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL3 :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x002000 == 0 {
                                                        if insn & 0x004000 == 0 {
                                                            if insn & 0xffe0e008 == 0xa1200008 {
                                                                return Some (STNT1B_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xffe0e008 == 0xa1204008 {
                                                                return Some (STNT1W_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL2 :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x004000 == 0 {
                                                            if insn & 0xffe0e008 == 0xa1202008 {
                                                                return Some (STNT1H_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL1 :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xffe0e008 == 0xa1206008 {
                                                                return Some (STNT1D_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL3 :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0xffff9c10 == 0xe1200000 {
                                                    return Some (STR_SME_ZA_array_off4_SME_ADDR_RI_U4xVL :: make_opcode (insn)) ;
                                                }
                                            }
                                        } else {
                                            if insn & 0x000008 == 0 {
                                                if insn & 0x002000 == 0 {
                                                    if insn & 0x004000 == 0 {
                                                        if insn & 0x40000000 == 0 {
                                                            if insn & 0xffe0e00c == 0xa1208000 {
                                                                return Some (ST1B_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xfffffc1f == 0xe13f8000 {
                                                                return Some (STR_SME_ZT0_SIMD_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0xffe0e00c == 0xa120c000 {
                                                            return Some (ST1W_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL2 :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x004000 == 0 {
                                                        if insn & 0xffe0e00c == 0xa120a000 {
                                                            return Some (ST1H_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL1 :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xffe0e00c == 0xa120e000 {
                                                            return Some (ST1D_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL3 :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0x002000 == 0 {
                                                    if insn & 0x004000 == 0 {
                                                        if insn & 0xffe0e00c == 0xa1208008 {
                                                            return Some (STNT1B_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xffe0e00c == 0xa120c008 {
                                                            return Some (STNT1W_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL2 :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x004000 == 0 {
                                                        if insn & 0xffe0e00c == 0xa120a008 {
                                                            return Some (STNT1H_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL1 :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xffe0e00c == 0xa120e008 {
                                                            return Some (STNT1D_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RR_LSL3 :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                }
                                            }
                                        }
                                    } else {
                                        if insn & 0x000010 == 0 {
                                            if insn & 0xffe0001c == 0xa1a00000 {
                                                return Some (UMOPA_SME_ZAda_2b_S_S_SVE_Pg3_P_M_SME_Pm_P_M_SVE_Zn_S_B_SVE_Zm_16_S_B :: make_opcode (insn)) ;
                                            }
                                        } else {
                                            if insn & 0xffe0001c == 0xa1a00010 {
                                                return Some (UMOPS_SME_ZAda_2b_S_S_SVE_Pg3_P_M_SME_Pm_P_M_SVE_Zn_S_B_SVE_Zm_16_S_B :: make_opcode (insn)) ;
                                            }
                                        }
                                    }
                                } else {
                                    if insn & 0x800000 == 0 {
                                        if insn & 0x000008 == 0 {
                                            if insn & 0x002000 == 0 {
                                                if insn & 0x004000 == 0 {
                                                    if insn & 0x008000 == 0 {
                                                        if insn & 0xfff0e008 == 0xa1600000 {
                                                            return Some (ST1B_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xfff0e00c == 0xa1608000 {
                                                            return Some (ST1B_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x008000 == 0 {
                                                        if insn & 0xfff0e008 == 0xa1604000 {
                                                            return Some (ST1W_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xfff0e00c == 0xa160c000 {
                                                            return Some (ST1W_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0x004000 == 0 {
                                                    if insn & 0x008000 == 0 {
                                                        if insn & 0xfff0e008 == 0xa1602000 {
                                                            return Some (ST1H_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xfff0e00c == 0xa160a000 {
                                                            return Some (ST1H_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x008000 == 0 {
                                                        if insn & 0xfff0e008 == 0xa1606000 {
                                                            return Some (ST1D_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xfff0e00c == 0xa160e000 {
                                                            return Some (ST1D_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                }
                                            }
                                        } else {
                                            if insn & 0x002000 == 0 {
                                                if insn & 0x004000 == 0 {
                                                    if insn & 0x008000 == 0 {
                                                        if insn & 0xfff0e008 == 0xa1600008 {
                                                            return Some (STNT1B_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xfff0e00c == 0xa1608008 {
                                                            return Some (STNT1B_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x008000 == 0 {
                                                        if insn & 0xfff0e008 == 0xa1604008 {
                                                            return Some (STNT1W_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xfff0e00c == 0xa160c008 {
                                                            return Some (STNT1W_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0x004000 == 0 {
                                                    if insn & 0x008000 == 0 {
                                                        if insn & 0xfff0e008 == 0xa1602008 {
                                                            return Some (STNT1H_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xfff0e00c == 0xa160a008 {
                                                            return Some (STNT1H_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x008000 == 0 {
                                                        if insn & 0xfff0e008 == 0xa1606008 {
                                                            return Some (STNT1D_SME_Ztx2_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x2xVL :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xfff0e00c == 0xa160e008 {
                                                            return Some (STNT1D_SME_Ztx4_STRIDED_SME_PNg3_SVE_ADDR_RI_S4x4xVL :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                }
                                            }
                                        }
                                    } else {
                                        if insn & 0x000010 == 0 {
                                            if insn & 0x40000000 == 0 {
                                                if insn & 0xffe00018 == 0xa1e00000 {
                                                    return Some (UMOPA_SME_ZAda_3b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                }
                                            } else {
                                                if insn & 0xffe00010 == 0xe1e00000 {
                                                    return Some (ST1Q_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_R :: make_opcode (insn)) ;
                                                }
                                                if insn & 0xffe00010 == 0xe1e00000 {
                                                    return Some (ST1Q_SME_ZA_HV_idx_ldstr_SVE_Pg3_SVE_ADDR_R :: make_opcode (insn)) ;
                                                }
                                            }
                                        } else {
                                            if insn & 0xffe00018 == 0xa1e00010 {
                                                return Some (UMOPS_SME_ZAda_3b_SVE_Pg3_SME_Pm_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                            }
                                        }
                                    }
                                }
                            }
                        }
                    } else {
                        if insn & 0x800000 == 0 {
                            if insn & 0x20000000 == 0 {
                                if insn & 0x40000000 == 0 {
                                    if insn & 0x7f800000 == 0x11000000 {
                                        return Some(ADD_Rd_SP_Rn_SP_AIMM::make_opcode(insn));
                                    }
                                } else {
                                    if insn & 0x7f800000 == 0x51000000 {
                                        return Some(SUB_Rd_SP_Rn_SP_AIMM::make_opcode(insn));
                                    }
                                }
                            } else {
                                if insn & 0x40000000 == 0 {
                                    if insn & 0x7f800000 == 0x31000000 {
                                        return Some(ADDS_Rd_Rn_SP_AIMM::make_opcode(insn));
                                    }
                                } else {
                                    if insn & 0x7f800000 == 0x71000000 {
                                        return Some(SUBS_Rd_Rn_SP_AIMM::make_opcode(insn));
                                    }
                                }
                            }
                        } else {
                            if insn & 0x400000 == 0 {
                                if insn & 0x40000000 == 0 {
                                    if insn & 0xffc0c000 == 0x91800000 {
                                        return Some(
                                            ADDG_Rd_SP_Rn_SP_UIMM10_UIMM4_ADDG::make_opcode(insn),
                                        );
                                    }
                                } else {
                                    if insn & 0xffc0c000 == 0xd1800000 {
                                        return Some(
                                            SUBG_Rd_SP_Rn_SP_UIMM10_UIMM4_ADDG::make_opcode(insn),
                                        );
                                    }
                                }
                            } else {
                                if insn & 0x040000 == 0 {
                                    if insn & 0x080000 == 0 {
                                        if insn & 0x7ffc0000 == 0x11c00000 {
                                            return Some(SMAX_Rd_Rn_CSSC_SIMM8::make_opcode(insn));
                                        }
                                    } else {
                                        if insn & 0x7ffc0000 == 0x11c80000 {
                                            return Some(SMIN_Rd_Rn_CSSC_SIMM8::make_opcode(insn));
                                        }
                                    }
                                } else {
                                    if insn & 0x080000 == 0 {
                                        if insn & 0x7ffc0000 == 0x11c40000 {
                                            return Some(UMAX_Rd_Rn_CSSC_UIMM8::make_opcode(insn));
                                        }
                                    } else {
                                        if insn & 0x7ffc0000 == 0x11cc0000 {
                                            return Some(UMIN_Rd_Rn_CSSC_UIMM8::make_opcode(insn));
                                        }
                                    }
                                }
                            }
                        }
                    }
                }
            } else {
                if insn & 0x10000000 == 0 {
                    if insn & 0x400000 == 0 {
                        if insn & 0x800000 == 0 {
                            if insn & 0x1000000 == 0 {
                                if insn & 0x20000000 == 0 {
                                    if insn & 0x008000 == 0 {
                                        if insn & 0x200000 == 0 {
                                            if insn & 0x80000000 == 0 {
                                                if insn & 0x40000000 == 0 {
                                                    if insn & 0xffe0fc00 == 0x8007c00 {
                                                        return Some(
                                                            STXRB_Rs_Rt_ADDR_SIMPLE::make_opcode(
                                                                insn,
                                                            ),
                                                        );
                                                    }
                                                } else {
                                                    if insn & 0xffe0fc00 == 0x48007c00 {
                                                        return Some(
                                                            STXRH_Rs_Rt_ADDR_SIMPLE::make_opcode(
                                                                insn,
                                                            ),
                                                        );
                                                    }
                                                }
                                            } else {
                                                if insn & 0xbfe0fc00 == 0x88007c00 {
                                                    return Some(
                                                        STXR_Rs_Rt_ADDR_SIMPLE::make_opcode(insn),
                                                    );
                                                }
                                            }
                                        } else {
                                            if insn & 0x80000000 == 0 {
                                                if insn & 0xbfe0fc00 == 0x8207c00 {
                                                    return Some (CASP_Rs_PAIRREG_Rt_PAIRREG_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                }
                                            } else {
                                                if insn & 0xbfe08000 == 0x88200000 {
                                                    return Some(
                                                        STXP_Rs_Rt_Rt2_ADDR_SIMPLE::make_opcode(
                                                            insn,
                                                        ),
                                                    );
                                                }
                                            }
                                        }
                                    } else {
                                        if insn & 0x200000 == 0 {
                                            if insn & 0x80000000 == 0 {
                                                if insn & 0x40000000 == 0 {
                                                    if insn & 0xffe0fc00 == 0x800fc00 {
                                                        return Some(
                                                            STLXRB_Rs_Rt_ADDR_SIMPLE::make_opcode(
                                                                insn,
                                                            ),
                                                        );
                                                    }
                                                } else {
                                                    if insn & 0xffe0fc00 == 0x4800fc00 {
                                                        return Some(
                                                            STLXRH_Rs_Rt_ADDR_SIMPLE::make_opcode(
                                                                insn,
                                                            ),
                                                        );
                                                    }
                                                }
                                            } else {
                                                if insn & 0xbfe0fc00 == 0x8800fc00 {
                                                    return Some(
                                                        STLXR_Rs_Rt_ADDR_SIMPLE::make_opcode(insn),
                                                    );
                                                }
                                            }
                                        } else {
                                            if insn & 0x80000000 == 0 {
                                                if insn & 0xbfe0fc00 == 0x820fc00 {
                                                    return Some (CASPL_Rs_PAIRREG_Rt_PAIRREG_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                }
                                            } else {
                                                if insn & 0xbfe08000 == 0x88208000 {
                                                    return Some(
                                                        STLXP_Rs_Rt_Rt2_ADDR_SIMPLE::make_opcode(
                                                            insn,
                                                        ),
                                                    );
                                                }
                                            }
                                        }
                                    }
                                } else {
                                    if insn & 0x7fc00000 == 0x28000000 {
                                        return Some(STNP_Rt_Rt2_ADDR_SIMM7::make_opcode(insn));
                                    }
                                }
                            } else {
                                if insn & 0x40000000 == 0 {
                                    if insn & 0x7fc00000 == 0x29000000 {
                                        return Some(STP_Rt_Rt2_ADDR_SIMM7::make_opcode(insn));
                                    }
                                } else {
                                    if insn & 0xffc00000 == 0x69000000 {
                                        return Some(STGP_Rt_Rt2_ADDR_SIMM11::make_opcode(insn));
                                    }
                                }
                            }
                        } else {
                            if insn & 0x20000000 == 0 {
                                if insn & 0x008000 == 0 {
                                    if insn & 0x200000 == 0 {
                                        if insn & 0x80000000 == 0 {
                                            if insn & 0x40000000 == 0 {
                                                if insn & 0xfffffc00 == 0x89f7c00 {
                                                    return Some(
                                                        STLLRB_Rt_ADDR_SIMPLE::make_opcode(insn),
                                                    );
                                                }
                                            } else {
                                                if insn & 0xfffffc00 == 0x489f7c00 {
                                                    return Some(
                                                        STLLRH_Rt_ADDR_SIMPLE::make_opcode(insn),
                                                    );
                                                }
                                            }
                                        } else {
                                            if insn & 0xbffffc00 == 0x889f7c00 {
                                                return Some(STLLR_Rt_ADDR_SIMPLE::make_opcode(
                                                    insn,
                                                ));
                                            }
                                        }
                                    } else {
                                        if insn & 0x80000000 == 0 {
                                            if insn & 0x40000000 == 0 {
                                                if insn & 0xffe0fc00 == 0x8a07c00 {
                                                    return Some(
                                                        CASB_Rs_Rt_ADDR_SIMPLE::make_opcode(insn),
                                                    );
                                                }
                                            } else {
                                                if insn & 0xffe0fc00 == 0x48a07c00 {
                                                    return Some(
                                                        CASH_Rs_Rt_ADDR_SIMPLE::make_opcode(insn),
                                                    );
                                                }
                                            }
                                        } else {
                                            if insn & 0xbfe0fc00 == 0x88a07c00 {
                                                return Some(CAS_Rs_Rt_ADDR_SIMPLE::make_opcode(
                                                    insn,
                                                ));
                                            }
                                        }
                                    }
                                } else {
                                    if insn & 0x200000 == 0 {
                                        if insn & 0x80000000 == 0 {
                                            if insn & 0x40000000 == 0 {
                                                if insn & 0xfffffc00 == 0x89ffc00 {
                                                    return Some(
                                                        STLRB_Rt_ADDR_SIMPLE::make_opcode(insn),
                                                    );
                                                }
                                            } else {
                                                if insn & 0xfffffc00 == 0x489ffc00 {
                                                    return Some(
                                                        STLRH_Rt_ADDR_SIMPLE::make_opcode(insn),
                                                    );
                                                }
                                            }
                                        } else {
                                            if insn & 0xbffffc00 == 0x889ffc00 {
                                                return Some(STLR_Rt_ADDR_SIMPLE::make_opcode(
                                                    insn,
                                                ));
                                            }
                                        }
                                    } else {
                                        if insn & 0x80000000 == 0 {
                                            if insn & 0x40000000 == 0 {
                                                if insn & 0xffe0fc00 == 0x8a0fc00 {
                                                    return Some(
                                                        CASLB_Rs_Rt_ADDR_SIMPLE::make_opcode(insn),
                                                    );
                                                }
                                            } else {
                                                if insn & 0xffe0fc00 == 0x48a0fc00 {
                                                    return Some(
                                                        CASLH_Rs_Rt_ADDR_SIMPLE::make_opcode(insn),
                                                    );
                                                }
                                            }
                                        } else {
                                            if insn & 0xbfe0fc00 == 0x88a0fc00 {
                                                return Some(CASL_Rs_Rt_ADDR_SIMPLE::make_opcode(
                                                    insn,
                                                ));
                                            }
                                        }
                                    }
                                }
                            } else {
                                if insn & 0x40000000 == 0 {
                                    if insn & 0x7ec00000 == 0x28800000 {
                                        return Some(STP_Rt_W_Rt2_W_ADDR_SIMM7_S_S::make_opcode(
                                            insn,
                                        ));
                                    }
                                } else {
                                    if insn & 0xfec00000 == 0x68800000 {
                                        return Some(
                                            STGP_Rt_X_Rt2_X_ADDR_SIMM11_imm_tag::make_opcode(insn),
                                        );
                                    }
                                }
                            }
                        }
                    } else {
                        if insn & 0x800000 == 0 {
                            if insn & 0x1000000 == 0 {
                                if insn & 0x20000000 == 0 {
                                    if insn & 0x008000 == 0 {
                                        if insn & 0x200000 == 0 {
                                            if insn & 0x80000000 == 0 {
                                                if insn & 0x40000000 == 0 {
                                                    if insn & 0xfffffc00 == 0x85f7c00 {
                                                        return Some(
                                                            LDXRB_Rt_ADDR_SIMPLE::make_opcode(insn),
                                                        );
                                                    }
                                                } else {
                                                    if insn & 0xfffffc00 == 0x485f7c00 {
                                                        return Some(
                                                            LDXRH_Rt_ADDR_SIMPLE::make_opcode(insn),
                                                        );
                                                    }
                                                }
                                            } else {
                                                if insn & 0xbffffc00 == 0x885f7c00 {
                                                    return Some(LDXR_Rt_ADDR_SIMPLE::make_opcode(
                                                        insn,
                                                    ));
                                                }
                                            }
                                        } else {
                                            if insn & 0x80000000 == 0 {
                                                if insn & 0xbfe0fc00 == 0x8607c00 {
                                                    return Some (CASPA_Rs_PAIRREG_Rt_PAIRREG_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                }
                                            } else {
                                                if insn & 0xbfff8000 == 0x887f0000 {
                                                    return Some(
                                                        LDXP_Rt_Rt2_ADDR_SIMPLE::make_opcode(insn),
                                                    );
                                                }
                                            }
                                        }
                                    } else {
                                        if insn & 0x200000 == 0 {
                                            if insn & 0x80000000 == 0 {
                                                if insn & 0x40000000 == 0 {
                                                    if insn & 0xfffffc00 == 0x85ffc00 {
                                                        return Some(
                                                            LDAXRB_Rt_ADDR_SIMPLE::make_opcode(
                                                                insn,
                                                            ),
                                                        );
                                                    }
                                                } else {
                                                    if insn & 0xfffffc00 == 0x485ffc00 {
                                                        return Some(
                                                            LDAXRH_Rt_ADDR_SIMPLE::make_opcode(
                                                                insn,
                                                            ),
                                                        );
                                                    }
                                                }
                                            } else {
                                                if insn & 0xbffffc00 == 0x885ffc00 {
                                                    return Some(
                                                        LDAXR_Rt_ADDR_SIMPLE::make_opcode(insn),
                                                    );
                                                }
                                            }
                                        } else {
                                            if insn & 0x80000000 == 0 {
                                                if insn & 0xbfe0fc00 == 0x860fc00 {
                                                    return Some (CASPAL_Rs_PAIRREG_Rt_PAIRREG_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                }
                                            } else {
                                                if insn & 0xbfff8000 == 0x887f8000 {
                                                    return Some(
                                                        LDAXP_Rt_Rt2_ADDR_SIMPLE::make_opcode(insn),
                                                    );
                                                }
                                            }
                                        }
                                    }
                                } else {
                                    if insn & 0x7fc00000 == 0x28400000 {
                                        return Some(LDNP_Rt_Rt2_ADDR_SIMM7::make_opcode(insn));
                                    }
                                }
                            } else {
                                if insn & 0x40000000 == 0 {
                                    if insn & 0x7fc00000 == 0x29400000 {
                                        return Some(LDP_Rt_Rt2_ADDR_SIMM7::make_opcode(insn));
                                    }
                                } else {
                                    if insn & 0xffc00000 == 0x69400000 {
                                        return Some(LDPSW_Rt_Rt2_ADDR_SIMM7::make_opcode(insn));
                                    }
                                }
                            }
                        } else {
                            if insn & 0x20000000 == 0 {
                                if insn & 0x008000 == 0 {
                                    if insn & 0x200000 == 0 {
                                        if insn & 0x80000000 == 0 {
                                            if insn & 0x40000000 == 0 {
                                                if insn & 0xfffffc00 == 0x8df7c00 {
                                                    return Some(
                                                        LDLARB_Rt_ADDR_SIMPLE::make_opcode(insn),
                                                    );
                                                }
                                            } else {
                                                if insn & 0xfffffc00 == 0x48df7c00 {
                                                    return Some(
                                                        LDLARH_Rt_ADDR_SIMPLE::make_opcode(insn),
                                                    );
                                                }
                                            }
                                        } else {
                                            if insn & 0xbffffc00 == 0x88df7c00 {
                                                return Some(LDLAR_Rt_ADDR_SIMPLE::make_opcode(
                                                    insn,
                                                ));
                                            }
                                        }
                                    } else {
                                        if insn & 0x80000000 == 0 {
                                            if insn & 0x40000000 == 0 {
                                                if insn & 0xffe0fc00 == 0x8e07c00 {
                                                    return Some(
                                                        CASAB_Rs_Rt_ADDR_SIMPLE::make_opcode(insn),
                                                    );
                                                }
                                            } else {
                                                if insn & 0xffe0fc00 == 0x48e07c00 {
                                                    return Some(
                                                        CASAH_Rs_Rt_ADDR_SIMPLE::make_opcode(insn),
                                                    );
                                                }
                                            }
                                        } else {
                                            if insn & 0xbfe0fc00 == 0x88e07c00 {
                                                return Some(CASA_Rs_Rt_ADDR_SIMPLE::make_opcode(
                                                    insn,
                                                ));
                                            }
                                        }
                                    }
                                } else {
                                    if insn & 0x200000 == 0 {
                                        if insn & 0x80000000 == 0 {
                                            if insn & 0x40000000 == 0 {
                                                if insn & 0xfffffc00 == 0x8dffc00 {
                                                    return Some(
                                                        LDARB_Rt_ADDR_SIMPLE::make_opcode(insn),
                                                    );
                                                }
                                            } else {
                                                if insn & 0xfffffc00 == 0x48dffc00 {
                                                    return Some(
                                                        LDARH_Rt_ADDR_SIMPLE::make_opcode(insn),
                                                    );
                                                }
                                            }
                                        } else {
                                            if insn & 0xbffffc00 == 0x88dffc00 {
                                                return Some(LDAR_Rt_ADDR_SIMPLE::make_opcode(
                                                    insn,
                                                ));
                                            }
                                        }
                                    } else {
                                        if insn & 0x80000000 == 0 {
                                            if insn & 0x40000000 == 0 {
                                                if insn & 0xffe0fc00 == 0x8e0fc00 {
                                                    return Some(
                                                        CASALB_Rs_Rt_ADDR_SIMPLE::make_opcode(insn),
                                                    );
                                                }
                                            } else {
                                                if insn & 0xffe0fc00 == 0x48e0fc00 {
                                                    return Some(
                                                        CASALH_Rs_Rt_ADDR_SIMPLE::make_opcode(insn),
                                                    );
                                                }
                                            }
                                        } else {
                                            if insn & 0xbfe0fc00 == 0x88e0fc00 {
                                                return Some(CASAL_Rs_Rt_ADDR_SIMPLE::make_opcode(
                                                    insn,
                                                ));
                                            }
                                        }
                                    }
                                }
                            } else {
                                if insn & 0x40000000 == 0 {
                                    if insn & 0x7ec00000 == 0x28c00000 {
                                        return Some(LDP_Rt_W_Rt2_W_ADDR_SIMM7_S_S::make_opcode(
                                            insn,
                                        ));
                                    }
                                } else {
                                    if insn & 0xfec00000 == 0x68c00000 {
                                        return Some(LDPSW_Rt_X_Rt2_X_ADDR_SIMM7_S_S::make_opcode(
                                            insn,
                                        ));
                                    }
                                }
                            }
                        }
                    }
                } else {
                    if insn & 0x1000000 == 0 {
                        if insn & 0x20000000 == 0 {
                            if insn & 0x80000000 == 0 {
                                if insn & 0xbf000000 == 0x18000000 {
                                    return Some(LDR_Rt_ADDR_PCREL19::make_opcode(insn));
                                }
                            } else {
                                if insn & 0x40000000 == 0 {
                                    if insn & 0xff000000 == 0x98000000 {
                                        return Some(LDRSW_Rt_ADDR_PCREL19::make_opcode(insn));
                                    }
                                } else {
                                    if insn & 0xff000000 == 0xd8000000 {
                                        return Some(PRFM_PRFOP_ADDR_PCREL19::make_opcode(insn));
                                    }
                                }
                            }
                        } else {
                            if insn & 0x000400 == 0 {
                                if insn & 0x000800 == 0 {
                                    if insn & 0x200000 == 0 {
                                        if insn & 0x800000 == 0 {
                                            if insn & 0x400000 == 0 {
                                                if insn & 0x80000000 == 0 {
                                                    if insn & 0x40000000 == 0 {
                                                        if insn & 0xffe00c00 == 0x38000000 {
                                                            return Some(
                                                                STURB_Rt_ADDR_SIMM9::make_opcode(
                                                                    insn,
                                                                ),
                                                            );
                                                        }
                                                    } else {
                                                        if insn & 0xffe00c00 == 0x78000000 {
                                                            return Some(
                                                                STURH_Rt_ADDR_SIMM9::make_opcode(
                                                                    insn,
                                                                ),
                                                            );
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0xbfe00c00 == 0xb8000000 {
                                                        return Some(
                                                            STUR_Rt_ADDR_SIMM9::make_opcode(insn),
                                                        );
                                                    }
                                                }
                                            } else {
                                                if insn & 0x80000000 == 0 {
                                                    if insn & 0x40000000 == 0 {
                                                        if insn & 0xffe00c00 == 0x38400000 {
                                                            return Some(
                                                                LDURB_Rt_ADDR_SIMM9::make_opcode(
                                                                    insn,
                                                                ),
                                                            );
                                                        }
                                                    } else {
                                                        if insn & 0xffe00c00 == 0x78400000 {
                                                            return Some(
                                                                LDURH_Rt_ADDR_SIMM9::make_opcode(
                                                                    insn,
                                                                ),
                                                            );
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0xbfe00c00 == 0xb8400000 {
                                                        return Some(
                                                            LDUR_Rt_ADDR_SIMM9::make_opcode(insn),
                                                        );
                                                    }
                                                }
                                            }
                                        } else {
                                            if insn & 0x40000000 == 0 {
                                                if insn & 0x80000000 == 0 {
                                                    if insn & 0xffa00c00 == 0x38800000 {
                                                        return Some(
                                                            LDURSB_Rt_ADDR_SIMM9::make_opcode(insn),
                                                        );
                                                    }
                                                } else {
                                                    if insn & 0xffe00c00 == 0xb8800000 {
                                                        return Some(
                                                            LDURSW_Rt_ADDR_SIMM9::make_opcode(insn),
                                                        );
                                                    }
                                                }
                                            } else {
                                                if insn & 0x80000000 == 0 {
                                                    if insn & 0xffa00c00 == 0x78800000 {
                                                        return Some(
                                                            LDURSH_Rt_ADDR_SIMM9::make_opcode(insn),
                                                        );
                                                    }
                                                } else {
                                                    if insn & 0xffe00c00 == 0xf8800000 {
                                                        return Some(
                                                            PRFUM_PRFOP_ADDR_SIMM9::make_opcode(
                                                                insn,
                                                            ),
                                                        );
                                                    }
                                                }
                                            }
                                        }
                                    } else {
                                        if insn & 0x001000 == 0 {
                                            if insn & 0x002000 == 0 {
                                                if insn & 0x004000 == 0 {
                                                    if insn & 0x008000 == 0 {
                                                        if insn & 0x400000 == 0 {
                                                            if insn & 0x800000 == 0 {
                                                                if insn & 0x80000000 == 0 {
                                                                    if insn & 0x40000000 == 0 {
                                                                        if insn & 0xffe0fc00
                                                                            == 0x38200000
                                                                        {
                                                                            return Some (LDADDB_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                        }
                                                                    } else {
                                                                        if insn & 0xffe0fc00
                                                                            == 0x78200000
                                                                        {
                                                                            return Some (LDADDH_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                        }
                                                                    }
                                                                } else {
                                                                    if insn & 0xbfe0fc00
                                                                        == 0xb8200000
                                                                    {
                                                                        return Some (LDADD_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0x80000000 == 0 {
                                                                    if insn & 0x40000000 == 0 {
                                                                        if insn & 0xffe0fc00
                                                                            == 0x38a00000
                                                                        {
                                                                            return Some (LDADDAB_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                        }
                                                                    } else {
                                                                        if insn & 0xffe0fc00
                                                                            == 0x78a00000
                                                                        {
                                                                            return Some (LDADDAH_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                        }
                                                                    }
                                                                } else {
                                                                    if insn & 0xbfe0fc00
                                                                        == 0xb8a00000
                                                                    {
                                                                        return Some (LDADDA_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x800000 == 0 {
                                                                if insn & 0x80000000 == 0 {
                                                                    if insn & 0x40000000 == 0 {
                                                                        if insn & 0xffe0fc00
                                                                            == 0x38600000
                                                                        {
                                                                            return Some (LDADDLB_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                        }
                                                                    } else {
                                                                        if insn & 0xffe0fc00
                                                                            == 0x78600000
                                                                        {
                                                                            return Some (LDADDLH_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                        }
                                                                    }
                                                                } else {
                                                                    if insn & 0xbfe0fc00
                                                                        == 0xb8600000
                                                                    {
                                                                        return Some (LDADDL_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0x80000000 == 0 {
                                                                    if insn & 0x40000000 == 0 {
                                                                        if insn & 0xffe0fc00
                                                                            == 0x38e00000
                                                                        {
                                                                            return Some (LDADDALB_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                        }
                                                                    } else {
                                                                        if insn & 0xffe0fc00
                                                                            == 0x78e00000
                                                                        {
                                                                            return Some (LDADDALH_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                        }
                                                                    }
                                                                } else {
                                                                    if insn & 0xbfe0fc00
                                                                        == 0xb8e00000
                                                                    {
                                                                        return Some (LDADDAL_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x400000 == 0 {
                                                            if insn & 0x800000 == 0 {
                                                                if insn & 0x80000000 == 0 {
                                                                    if insn & 0x40000000 == 0 {
                                                                        if insn & 0xffe0fc00
                                                                            == 0x38208000
                                                                        {
                                                                            return Some (SWPB_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                        }
                                                                    } else {
                                                                        if insn & 0xffe0fc00
                                                                            == 0x78208000
                                                                        {
                                                                            return Some (SWPH_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                        }
                                                                    }
                                                                } else {
                                                                    if insn & 0xbfe0fc00
                                                                        == 0xb8208000
                                                                    {
                                                                        return Some (SWP_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0x80000000 == 0 {
                                                                    if insn & 0x40000000 == 0 {
                                                                        if insn & 0xffe0fc00
                                                                            == 0x38a08000
                                                                        {
                                                                            return Some (SWPAB_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                        }
                                                                    } else {
                                                                        if insn & 0xffe0fc00
                                                                            == 0x78a08000
                                                                        {
                                                                            return Some (SWPAH_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                        }
                                                                    }
                                                                } else {
                                                                    if insn & 0xbfe0fc00
                                                                        == 0xb8a08000
                                                                    {
                                                                        return Some (SWPA_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x800000 == 0 {
                                                                if insn & 0x80000000 == 0 {
                                                                    if insn & 0x40000000 == 0 {
                                                                        if insn & 0xffe0fc00
                                                                            == 0x38608000
                                                                        {
                                                                            return Some (SWPLB_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                        }
                                                                    } else {
                                                                        if insn & 0xffe0fc00
                                                                            == 0x78608000
                                                                        {
                                                                            return Some (SWPLH_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                        }
                                                                    }
                                                                } else {
                                                                    if insn & 0xbfe0fc00
                                                                        == 0xb8608000
                                                                    {
                                                                        return Some (SWPL_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0x80000000 == 0 {
                                                                    if insn & 0x40000000 == 0 {
                                                                        if insn & 0xffe0fc00
                                                                            == 0x38e08000
                                                                        {
                                                                            return Some (SWPALB_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                        }
                                                                    } else {
                                                                        if insn & 0xffe0fc00
                                                                            == 0x78e08000
                                                                        {
                                                                            return Some (SWPALH_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                        }
                                                                    }
                                                                } else {
                                                                    if insn & 0xbfe0fc00
                                                                        == 0xb8e08000
                                                                    {
                                                                        return Some (SWPAL_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            }
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x008000 == 0 {
                                                        if insn & 0x400000 == 0 {
                                                            if insn & 0x800000 == 0 {
                                                                if insn & 0x80000000 == 0 {
                                                                    if insn & 0x40000000 == 0 {
                                                                        if insn & 0xffe0fc00
                                                                            == 0x38204000
                                                                        {
                                                                            return Some (LDSMAXB_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                        }
                                                                    } else {
                                                                        if insn & 0xffe0fc00
                                                                            == 0x78204000
                                                                        {
                                                                            return Some (LDSMAXH_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                        }
                                                                    }
                                                                } else {
                                                                    if insn & 0xbfe0fc00
                                                                        == 0xb8204000
                                                                    {
                                                                        return Some (LDSMAX_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0x80000000 == 0 {
                                                                    if insn & 0x40000000 == 0 {
                                                                        if insn & 0xffe0fc00
                                                                            == 0x38a04000
                                                                        {
                                                                            return Some (LDSMAXAB_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                        }
                                                                    } else {
                                                                        if insn & 0xffe0fc00
                                                                            == 0x78a04000
                                                                        {
                                                                            return Some (LDSMAXAH_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                        }
                                                                    }
                                                                } else {
                                                                    if insn & 0xbfe0fc00
                                                                        == 0xb8a04000
                                                                    {
                                                                        return Some (LDSMAXA_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x800000 == 0 {
                                                                if insn & 0x80000000 == 0 {
                                                                    if insn & 0x40000000 == 0 {
                                                                        if insn & 0xffe0fc00
                                                                            == 0x38604000
                                                                        {
                                                                            return Some (LDSMAXLB_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                        }
                                                                    } else {
                                                                        if insn & 0xffe0fc00
                                                                            == 0x78604000
                                                                        {
                                                                            return Some (LDSMAXLH_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                        }
                                                                    }
                                                                } else {
                                                                    if insn & 0xbfe0fc00
                                                                        == 0xb8604000
                                                                    {
                                                                        return Some (LDSMAXL_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0x80000000 == 0 {
                                                                    if insn & 0x40000000 == 0 {
                                                                        if insn & 0xffe0fc00
                                                                            == 0x38e04000
                                                                        {
                                                                            return Some (LDSMAXALB_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                        }
                                                                    } else {
                                                                        if insn & 0xffe0fc00
                                                                            == 0x78e04000
                                                                        {
                                                                            return Some (LDSMAXALH_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                        }
                                                                    }
                                                                } else {
                                                                    if insn & 0xbfe0fc00
                                                                        == 0xb8e04000
                                                                    {
                                                                        return Some (LDSMAXAL_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x80000000 == 0 {
                                                            if insn & 0x40000000 == 0 {
                                                                if insn & 0xfffffc00 == 0x38bfc000 {
                                                                    return Some (LDAPRB_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xfffffc00 == 0x78bfc000 {
                                                                    return Some (LDAPRH_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0xbffffc00 == 0xb8bfc000 {
                                                                return Some (LDAPR_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0x004000 == 0 {
                                                    if insn & 0x008000 == 0 {
                                                        if insn & 0x400000 == 0 {
                                                            if insn & 0x800000 == 0 {
                                                                if insn & 0x80000000 == 0 {
                                                                    if insn & 0x40000000 == 0 {
                                                                        if insn & 0xffe0fc00
                                                                            == 0x38202000
                                                                        {
                                                                            return Some (LDEORB_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                        }
                                                                    } else {
                                                                        if insn & 0xffe0fc00
                                                                            == 0x78202000
                                                                        {
                                                                            return Some (LDEORH_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                        }
                                                                    }
                                                                } else {
                                                                    if insn & 0xbfe0fc00
                                                                        == 0xb8202000
                                                                    {
                                                                        return Some (LDEOR_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0x80000000 == 0 {
                                                                    if insn & 0x40000000 == 0 {
                                                                        if insn & 0xffe0fc00
                                                                            == 0x38a02000
                                                                        {
                                                                            return Some (LDEORAB_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                        }
                                                                    } else {
                                                                        if insn & 0xffe0fc00
                                                                            == 0x78a02000
                                                                        {
                                                                            return Some (LDEORAH_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                        }
                                                                    }
                                                                } else {
                                                                    if insn & 0xbfe0fc00
                                                                        == 0xb8a02000
                                                                    {
                                                                        return Some (LDEORA_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x800000 == 0 {
                                                                if insn & 0x80000000 == 0 {
                                                                    if insn & 0x40000000 == 0 {
                                                                        if insn & 0xffe0fc00
                                                                            == 0x38602000
                                                                        {
                                                                            return Some (LDEORLB_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                        }
                                                                    } else {
                                                                        if insn & 0xffe0fc00
                                                                            == 0x78602000
                                                                        {
                                                                            return Some (LDEORLH_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                        }
                                                                    }
                                                                } else {
                                                                    if insn & 0xbfe0fc00
                                                                        == 0xb8602000
                                                                    {
                                                                        return Some (LDEORL_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0x80000000 == 0 {
                                                                    if insn & 0x40000000 == 0 {
                                                                        if insn & 0xffe0fc00
                                                                            == 0x38e02000
                                                                        {
                                                                            return Some (LDEORALB_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                        }
                                                                    } else {
                                                                        if insn & 0xffe0fc00
                                                                            == 0x78e02000
                                                                        {
                                                                            return Some (LDEORALH_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                        }
                                                                    }
                                                                } else {
                                                                    if insn & 0xbfe0fc00
                                                                        == 0xb8e02000
                                                                    {
                                                                        return Some (LDEORAL_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x400000 == 0 {
                                                            if insn & 0x800000 == 0 {
                                                                if insn & 0x40000000 == 0 {
                                                                    if insn & 0xffe0fc00
                                                                        == 0x3820a000
                                                                    {
                                                                        return Some (RCWSWP_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0x80000000 == 0 {
                                                                        if insn & 0xffe0fc00
                                                                            == 0x7820a000
                                                                        {
                                                                            return Some (RCWSSWP_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                        }
                                                                    } else {
                                                                        if insn & 0xffe0fc00
                                                                            == 0xf820a000
                                                                        {
                                                                            return Some (ST64BV0_Rs_Rt_LS64_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                        }
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0x40000000 == 0 {
                                                                    if insn & 0xffe0fc00
                                                                        == 0x38a0a000
                                                                    {
                                                                        return Some (RCWSWPA_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xffe0fc00
                                                                        == 0x78a0a000
                                                                    {
                                                                        return Some (RCWSSWPA_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x800000 == 0 {
                                                                if insn & 0x40000000 == 0 {
                                                                    if insn & 0xffe0fc00
                                                                        == 0x3860a000
                                                                    {
                                                                        return Some (RCWSWPL_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xffe0fc00
                                                                        == 0x7860a000
                                                                    {
                                                                        return Some (RCWSSWPL_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0x40000000 == 0 {
                                                                    if insn & 0xffe0fc00
                                                                        == 0x38e0a000
                                                                    {
                                                                        return Some (RCWSWPAL_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xffe0fc00
                                                                        == 0x78e0a000
                                                                    {
                                                                        return Some (RCWSSWPAL_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            }
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x400000 == 0 {
                                                        if insn & 0x800000 == 0 {
                                                            if insn & 0x80000000 == 0 {
                                                                if insn & 0x40000000 == 0 {
                                                                    if insn & 0xffe0fc00
                                                                        == 0x38206000
                                                                    {
                                                                        return Some (LDUMAXB_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xffe0fc00
                                                                        == 0x78206000
                                                                    {
                                                                        return Some (LDUMAXH_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0xbfe0fc00 == 0xb8206000 {
                                                                    return Some (LDUMAX_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x80000000 == 0 {
                                                                if insn & 0x40000000 == 0 {
                                                                    if insn & 0xffe0fc00
                                                                        == 0x38a06000
                                                                    {
                                                                        return Some (LDUMAXAB_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xffe0fc00
                                                                        == 0x78a06000
                                                                    {
                                                                        return Some (LDUMAXAH_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0xbfe0fc00 == 0xb8a06000 {
                                                                    return Some (LDUMAXA_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x800000 == 0 {
                                                            if insn & 0x80000000 == 0 {
                                                                if insn & 0x40000000 == 0 {
                                                                    if insn & 0xffe0fc00
                                                                        == 0x38606000
                                                                    {
                                                                        return Some (LDUMAXLB_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xffe0fc00
                                                                        == 0x78606000
                                                                    {
                                                                        return Some (LDUMAXLH_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0xbfe0fc00 == 0xb8606000 {
                                                                    return Some (LDUMAXL_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x80000000 == 0 {
                                                                if insn & 0x40000000 == 0 {
                                                                    if insn & 0xffe0fc00
                                                                        == 0x38e06000
                                                                    {
                                                                        return Some (LDUMAXALB_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xffe0fc00
                                                                        == 0x78e06000
                                                                    {
                                                                        return Some (LDUMAXALH_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0xbfe0fc00 == 0xb8e06000 {
                                                                    return Some (LDUMAXAL_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        }
                                                    }
                                                }
                                            }
                                        } else {
                                            if insn & 0x002000 == 0 {
                                                if insn & 0x004000 == 0 {
                                                    if insn & 0x008000 == 0 {
                                                        if insn & 0x400000 == 0 {
                                                            if insn & 0x800000 == 0 {
                                                                if insn & 0x80000000 == 0 {
                                                                    if insn & 0x40000000 == 0 {
                                                                        if insn & 0xffe0fc00
                                                                            == 0x38201000
                                                                        {
                                                                            return Some (LDCLRB_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                        }
                                                                    } else {
                                                                        if insn & 0xffe0fc00
                                                                            == 0x78201000
                                                                        {
                                                                            return Some (LDCLRH_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                        }
                                                                    }
                                                                } else {
                                                                    if insn & 0xbfe0fc00
                                                                        == 0xb8201000
                                                                    {
                                                                        return Some (LDCLR_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0x80000000 == 0 {
                                                                    if insn & 0x40000000 == 0 {
                                                                        if insn & 0xffe0fc00
                                                                            == 0x38a01000
                                                                        {
                                                                            return Some (LDCLRAB_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                        }
                                                                    } else {
                                                                        if insn & 0xffe0fc00
                                                                            == 0x78a01000
                                                                        {
                                                                            return Some (LDCLRAH_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                        }
                                                                    }
                                                                } else {
                                                                    if insn & 0xbfe0fc00
                                                                        == 0xb8a01000
                                                                    {
                                                                        return Some (LDCLRA_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x800000 == 0 {
                                                                if insn & 0x80000000 == 0 {
                                                                    if insn & 0x40000000 == 0 {
                                                                        if insn & 0xffe0fc00
                                                                            == 0x38601000
                                                                        {
                                                                            return Some (LDCLRLB_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                        }
                                                                    } else {
                                                                        if insn & 0xffe0fc00
                                                                            == 0x78601000
                                                                        {
                                                                            return Some (LDCLRLH_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                        }
                                                                    }
                                                                } else {
                                                                    if insn & 0xbfe0fc00
                                                                        == 0xb8601000
                                                                    {
                                                                        return Some (LDCLRL_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0x80000000 == 0 {
                                                                    if insn & 0x40000000 == 0 {
                                                                        if insn & 0xffe0fc00
                                                                            == 0x38e01000
                                                                        {
                                                                            return Some (LDCLRALB_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                        }
                                                                    } else {
                                                                        if insn & 0xffe0fc00
                                                                            == 0x78e01000
                                                                        {
                                                                            return Some (LDCLRALH_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                        }
                                                                    }
                                                                } else {
                                                                    if insn & 0xbfe0fc00
                                                                        == 0xb8e01000
                                                                    {
                                                                        return Some (LDCLRAL_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x400000 == 0 {
                                                            if insn & 0x800000 == 0 {
                                                                if insn & 0x40000000 == 0 {
                                                                    if insn & 0xffe0fc00
                                                                        == 0x38209000
                                                                    {
                                                                        return Some (RCWCLR_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0x80000000 == 0 {
                                                                        if insn & 0xffe0fc00
                                                                            == 0x78209000
                                                                        {
                                                                            return Some (RCWSCLR_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                        }
                                                                    } else {
                                                                        if insn & 0xfffffc00
                                                                            == 0xf83f9000
                                                                        {
                                                                            return Some (ST64B_Rt_LS64_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                        }
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0x40000000 == 0 {
                                                                    if insn & 0xffe0fc00
                                                                        == 0x38a09000
                                                                    {
                                                                        return Some (RCWCLRA_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xffe0fc00
                                                                        == 0x78a09000
                                                                    {
                                                                        return Some (RCWSCLRA_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x800000 == 0 {
                                                                if insn & 0x40000000 == 0 {
                                                                    if insn & 0xffe0fc00
                                                                        == 0x38609000
                                                                    {
                                                                        return Some (RCWCLRL_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xffe0fc00
                                                                        == 0x78609000
                                                                    {
                                                                        return Some (RCWSCLRL_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0x40000000 == 0 {
                                                                    if insn & 0xffe0fc00
                                                                        == 0x38e09000
                                                                    {
                                                                        return Some (RCWCLRAL_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xffe0fc00
                                                                        == 0x78e09000
                                                                    {
                                                                        return Some (RCWSCLRAL_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            }
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x008000 == 0 {
                                                        if insn & 0x400000 == 0 {
                                                            if insn & 0x800000 == 0 {
                                                                if insn & 0x80000000 == 0 {
                                                                    if insn & 0x40000000 == 0 {
                                                                        if insn & 0xffe0fc00
                                                                            == 0x38205000
                                                                        {
                                                                            return Some (LDSMINB_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                        }
                                                                    } else {
                                                                        if insn & 0xffe0fc00
                                                                            == 0x78205000
                                                                        {
                                                                            return Some (LDSMINH_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                        }
                                                                    }
                                                                } else {
                                                                    if insn & 0xbfe0fc00
                                                                        == 0xb8205000
                                                                    {
                                                                        return Some (LDSMIN_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0x80000000 == 0 {
                                                                    if insn & 0x40000000 == 0 {
                                                                        if insn & 0xffe0fc00
                                                                            == 0x38a05000
                                                                        {
                                                                            return Some (LDSMINAB_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                        }
                                                                    } else {
                                                                        if insn & 0xffe0fc00
                                                                            == 0x78a05000
                                                                        {
                                                                            return Some (LDSMINAH_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                        }
                                                                    }
                                                                } else {
                                                                    if insn & 0xbfe0fc00
                                                                        == 0xb8a05000
                                                                    {
                                                                        return Some (LDSMINA_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x800000 == 0 {
                                                                if insn & 0x80000000 == 0 {
                                                                    if insn & 0x40000000 == 0 {
                                                                        if insn & 0xffe0fc00
                                                                            == 0x38605000
                                                                        {
                                                                            return Some (LDSMINLB_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                        }
                                                                    } else {
                                                                        if insn & 0xffe0fc00
                                                                            == 0x78605000
                                                                        {
                                                                            return Some (LDSMINLH_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                        }
                                                                    }
                                                                } else {
                                                                    if insn & 0xbfe0fc00
                                                                        == 0xb8605000
                                                                    {
                                                                        return Some (LDSMINL_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0x80000000 == 0 {
                                                                    if insn & 0x40000000 == 0 {
                                                                        if insn & 0xffe0fc00
                                                                            == 0x38e05000
                                                                        {
                                                                            return Some (LDSMINALB_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                        }
                                                                    } else {
                                                                        if insn & 0xffe0fc00
                                                                            == 0x78e05000
                                                                        {
                                                                            return Some (LDSMINALH_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                        }
                                                                    }
                                                                } else {
                                                                    if insn & 0xbfe0fc00
                                                                        == 0xb8e05000
                                                                    {
                                                                        return Some (LDSMINAL_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0xfffffc00 == 0xf83fd000 {
                                                            return Some (LD64B_Rt_LS64_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0x004000 == 0 {
                                                    if insn & 0x008000 == 0 {
                                                        if insn & 0x400000 == 0 {
                                                            if insn & 0x800000 == 0 {
                                                                if insn & 0x80000000 == 0 {
                                                                    if insn & 0x40000000 == 0 {
                                                                        if insn & 0xffe0fc00
                                                                            == 0x38203000
                                                                        {
                                                                            return Some (LDSETB_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                        }
                                                                    } else {
                                                                        if insn & 0xffe0fc00
                                                                            == 0x78203000
                                                                        {
                                                                            return Some (LDSETH_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                        }
                                                                    }
                                                                } else {
                                                                    if insn & 0xbfe0fc00
                                                                        == 0xb8203000
                                                                    {
                                                                        return Some (LDSET_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0x80000000 == 0 {
                                                                    if insn & 0x40000000 == 0 {
                                                                        if insn & 0xffe0fc00
                                                                            == 0x38a03000
                                                                        {
                                                                            return Some (LDSETAB_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                        }
                                                                    } else {
                                                                        if insn & 0xffe0fc00
                                                                            == 0x78a03000
                                                                        {
                                                                            return Some (LDSETAH_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                        }
                                                                    }
                                                                } else {
                                                                    if insn & 0xbfe0fc00
                                                                        == 0xb8a03000
                                                                    {
                                                                        return Some (LDSETA_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x800000 == 0 {
                                                                if insn & 0x80000000 == 0 {
                                                                    if insn & 0x40000000 == 0 {
                                                                        if insn & 0xffe0fc00
                                                                            == 0x38603000
                                                                        {
                                                                            return Some (LDSETLB_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                        }
                                                                    } else {
                                                                        if insn & 0xffe0fc00
                                                                            == 0x78603000
                                                                        {
                                                                            return Some (LDSETLH_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                        }
                                                                    }
                                                                } else {
                                                                    if insn & 0xbfe0fc00
                                                                        == 0xb8603000
                                                                    {
                                                                        return Some (LDSETL_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0x80000000 == 0 {
                                                                    if insn & 0x40000000 == 0 {
                                                                        if insn & 0xffe0fc00
                                                                            == 0x38e03000
                                                                        {
                                                                            return Some (LDSETALB_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                        }
                                                                    } else {
                                                                        if insn & 0xffe0fc00
                                                                            == 0x78e03000
                                                                        {
                                                                            return Some (LDSETALH_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                        }
                                                                    }
                                                                } else {
                                                                    if insn & 0xbfe0fc00
                                                                        == 0xb8e03000
                                                                    {
                                                                        return Some (LDSETAL_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x400000 == 0 {
                                                            if insn & 0x800000 == 0 {
                                                                if insn & 0x40000000 == 0 {
                                                                    if insn & 0xffe0fc00
                                                                        == 0x3820b000
                                                                    {
                                                                        return Some (RCWSET_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0x80000000 == 0 {
                                                                        if insn & 0xffe0fc00
                                                                            == 0x7820b000
                                                                        {
                                                                            return Some (RCWSSET_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                        }
                                                                    } else {
                                                                        if insn & 0xffe0fc00
                                                                            == 0xf820b000
                                                                        {
                                                                            return Some (ST64BV_Rs_Rt_LS64_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                        }
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0x40000000 == 0 {
                                                                    if insn & 0xffe0fc00
                                                                        == 0x38a0b000
                                                                    {
                                                                        return Some (RCWSETA_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xffe0fc00
                                                                        == 0x78a0b000
                                                                    {
                                                                        return Some (RCWSSETA_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x800000 == 0 {
                                                                if insn & 0x40000000 == 0 {
                                                                    if insn & 0xffe0fc00
                                                                        == 0x3860b000
                                                                    {
                                                                        return Some (RCWSETL_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xffe0fc00
                                                                        == 0x7860b000
                                                                    {
                                                                        return Some (RCWSSETL_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0x40000000 == 0 {
                                                                    if insn & 0xffe0fc00
                                                                        == 0x38e0b000
                                                                    {
                                                                        return Some (RCWSETAL_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xffe0fc00
                                                                        == 0x78e0b000
                                                                    {
                                                                        return Some (RCWSSETAL_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            }
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x400000 == 0 {
                                                        if insn & 0x800000 == 0 {
                                                            if insn & 0x80000000 == 0 {
                                                                if insn & 0x40000000 == 0 {
                                                                    if insn & 0xffe0fc00
                                                                        == 0x38207000
                                                                    {
                                                                        return Some (LDUMINB_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xffe0fc00
                                                                        == 0x78207000
                                                                    {
                                                                        return Some (LDUMINH_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0xbfe0fc00 == 0xb8207000 {
                                                                    return Some (LDUMIN_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x80000000 == 0 {
                                                                if insn & 0x40000000 == 0 {
                                                                    if insn & 0xffe0fc00
                                                                        == 0x38a07000
                                                                    {
                                                                        return Some (LDUMINAB_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xffe0fc00
                                                                        == 0x78a07000
                                                                    {
                                                                        return Some (LDUMINAH_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0xbfe0fc00 == 0xb8a07000 {
                                                                    return Some (LDUMINA_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x800000 == 0 {
                                                            if insn & 0x80000000 == 0 {
                                                                if insn & 0x40000000 == 0 {
                                                                    if insn & 0xffe0fc00
                                                                        == 0x38607000
                                                                    {
                                                                        return Some (LDUMINLB_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xffe0fc00
                                                                        == 0x78607000
                                                                    {
                                                                        return Some (LDUMINLH_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0xbfe0fc00 == 0xb8607000 {
                                                                    return Some (LDUMINL_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x80000000 == 0 {
                                                                if insn & 0x40000000 == 0 {
                                                                    if insn & 0xffe0fc00
                                                                        == 0x38e07000
                                                                    {
                                                                        return Some (LDUMINALB_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xffe0fc00
                                                                        == 0x78e07000
                                                                    {
                                                                        return Some (LDUMINALH_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0xbfe0fc00 == 0xb8e07000 {
                                                                    return Some (LDUMINAL_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        }
                                                    }
                                                }
                                            }
                                        }
                                    }
                                } else {
                                    if insn & 0x200000 == 0 {
                                        if insn & 0x800000 == 0 {
                                            if insn & 0x400000 == 0 {
                                                if insn & 0x80000000 == 0 {
                                                    if insn & 0x40000000 == 0 {
                                                        if insn & 0xffe00c00 == 0x38000800 {
                                                            return Some(
                                                                STTRB_Rt_ADDR_SIMM9::make_opcode(
                                                                    insn,
                                                                ),
                                                            );
                                                        }
                                                    } else {
                                                        if insn & 0xffe00c00 == 0x78000800 {
                                                            return Some(
                                                                STTRH_Rt_ADDR_SIMM9::make_opcode(
                                                                    insn,
                                                                ),
                                                            );
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0xbfe00c00 == 0xb8000800 {
                                                        return Some(
                                                            STTR_Rt_ADDR_SIMM9::make_opcode(insn),
                                                        );
                                                    }
                                                }
                                            } else {
                                                if insn & 0x80000000 == 0 {
                                                    if insn & 0x40000000 == 0 {
                                                        if insn & 0xffe00c00 == 0x38400800 {
                                                            return Some(
                                                                LDTRB_Rt_ADDR_SIMM9::make_opcode(
                                                                    insn,
                                                                ),
                                                            );
                                                        }
                                                    } else {
                                                        if insn & 0xffe00c00 == 0x78400800 {
                                                            return Some(
                                                                LDTRH_Rt_ADDR_SIMM9::make_opcode(
                                                                    insn,
                                                                ),
                                                            );
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0xbfe00c00 == 0xb8400800 {
                                                        return Some(
                                                            LDTR_Rt_ADDR_SIMM9::make_opcode(insn),
                                                        );
                                                    }
                                                }
                                            }
                                        } else {
                                            if insn & 0x40000000 == 0 {
                                                if insn & 0x80000000 == 0 {
                                                    if insn & 0xffa00c00 == 0x38800800 {
                                                        return Some(
                                                            LDTRSB_Rt_ADDR_SIMM9::make_opcode(insn),
                                                        );
                                                    }
                                                } else {
                                                    if insn & 0xffe00c00 == 0xb8800800 {
                                                        return Some(
                                                            LDTRSW_Rt_ADDR_SIMM9::make_opcode(insn),
                                                        );
                                                    }
                                                }
                                            } else {
                                                if insn & 0xffa00c00 == 0x78800800 {
                                                    return Some(
                                                        LDTRSH_Rt_ADDR_SIMM9::make_opcode(insn),
                                                    );
                                                }
                                            }
                                        }
                                    } else {
                                        if insn & 0x800000 == 0 {
                                            if insn & 0x400000 == 0 {
                                                if insn & 0x80000000 == 0 {
                                                    if insn & 0x40000000 == 0 {
                                                        if insn & 0xffe00c00 == 0x38200800 {
                                                            return Some(
                                                                STRB_Rt_ADDR_REGOFF::make_opcode(
                                                                    insn,
                                                                ),
                                                            );
                                                        }
                                                    } else {
                                                        if insn & 0xffe00c00 == 0x78200800 {
                                                            return Some(
                                                                STRH_Rt_ADDR_REGOFF::make_opcode(
                                                                    insn,
                                                                ),
                                                            );
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0xbfe00c00 == 0xb8200800 {
                                                        return Some(
                                                            STR_Rt_ADDR_REGOFF::make_opcode(insn),
                                                        );
                                                    }
                                                }
                                            } else {
                                                if insn & 0x80000000 == 0 {
                                                    if insn & 0x40000000 == 0 {
                                                        if insn & 0xffe00c00 == 0x38600800 {
                                                            return Some(
                                                                LDRB_Rt_ADDR_REGOFF::make_opcode(
                                                                    insn,
                                                                ),
                                                            );
                                                        }
                                                    } else {
                                                        if insn & 0xffe00c00 == 0x78600800 {
                                                            return Some(
                                                                LDRH_Rt_ADDR_REGOFF::make_opcode(
                                                                    insn,
                                                                ),
                                                            );
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0xbfe00c00 == 0xb8600800 {
                                                        return Some(
                                                            LDR_Rt_ADDR_REGOFF::make_opcode(insn),
                                                        );
                                                    }
                                                }
                                            }
                                        } else {
                                            if insn & 0x40000000 == 0 {
                                                if insn & 0x80000000 == 0 {
                                                    if insn & 0xffa00c00 == 0x38a00800 {
                                                        return Some(
                                                            LDRSB_Rt_ADDR_REGOFF::make_opcode(insn),
                                                        );
                                                    }
                                                } else {
                                                    if insn & 0xffe00c00 == 0xb8a00800 {
                                                        return Some(
                                                            LDRSW_Rt_ADDR_REGOFF::make_opcode(insn),
                                                        );
                                                    }
                                                }
                                            } else {
                                                if insn & 0x80000000 == 0 {
                                                    if insn & 0xffa00c00 == 0x78a00800 {
                                                        return Some(
                                                            LDRSH_Rt_ADDR_REGOFF::make_opcode(insn),
                                                        );
                                                    }
                                                } else {
                                                    if insn & 0xffe04c18 == 0xf8a04818 {
                                                        return Some (RPRFM_RPRFMOP_Rm_SIMD_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                    }
                                                    if insn & 0xffe00c00 == 0xf8a00800 {
                                                        return Some(
                                                            PRFM_PRFOP_ADDR_REGOFF::make_opcode(
                                                                insn,
                                                            ),
                                                        );
                                                    }
                                                }
                                            }
                                        }
                                    }
                                }
                            } else {
                                if insn & 0x200000 == 0 {
                                    if insn & 0x800000 == 0 {
                                        if insn & 0x400000 == 0 {
                                            if insn & 0x80000000 == 0 {
                                                if insn & 0x40000000 == 0 {
                                                    if insn & 0xffe00400 == 0x38000400 {
                                                        return Some(
                                                            STRB_Rt_ADDR_SIMM9::make_opcode(insn),
                                                        );
                                                    }
                                                } else {
                                                    if insn & 0xffe00400 == 0x78000400 {
                                                        return Some(
                                                            STRH_Rt_ADDR_SIMM9::make_opcode(insn),
                                                        );
                                                    }
                                                }
                                            } else {
                                                if insn & 0xbfe00400 == 0xb8000400 {
                                                    return Some(STR_Rt_ADDR_SIMM9::make_opcode(
                                                        insn,
                                                    ));
                                                }
                                            }
                                        } else {
                                            if insn & 0x80000000 == 0 {
                                                if insn & 0x40000000 == 0 {
                                                    if insn & 0xffe00400 == 0x38400400 {
                                                        return Some(
                                                            LDRB_Rt_ADDR_SIMM9::make_opcode(insn),
                                                        );
                                                    }
                                                } else {
                                                    if insn & 0xffe00400 == 0x78400400 {
                                                        return Some(
                                                            LDRH_Rt_ADDR_SIMM9::make_opcode(insn),
                                                        );
                                                    }
                                                }
                                            } else {
                                                if insn & 0xbfe00400 == 0xb8400400 {
                                                    return Some(LDR_Rt_ADDR_SIMM9::make_opcode(
                                                        insn,
                                                    ));
                                                }
                                            }
                                        }
                                    } else {
                                        if insn & 0x40000000 == 0 {
                                            if insn & 0x80000000 == 0 {
                                                if insn & 0xffa00400 == 0x38800400 {
                                                    return Some(LDRSB_Rt_ADDR_SIMM9::make_opcode(
                                                        insn,
                                                    ));
                                                }
                                            } else {
                                                if insn & 0xffe00400 == 0xb8800400 {
                                                    return Some(LDRSW_Rt_ADDR_SIMM9::make_opcode(
                                                        insn,
                                                    ));
                                                }
                                            }
                                        } else {
                                            if insn & 0xffa00400 == 0x78800400 {
                                                return Some(LDRSH_Rt_ADDR_SIMM9::make_opcode(
                                                    insn,
                                                ));
                                            }
                                        }
                                    }
                                } else {
                                    if insn & 0x800000 == 0 {
                                        if insn & 0xffa00400 == 0xf8200400 {
                                            return Some(LDRAA_Rt_ADDR_SIMM10::make_opcode(insn));
                                        }
                                    } else {
                                        if insn & 0xffa00400 == 0xf8a00400 {
                                            return Some(LDRAB_Rt_ADDR_SIMM10::make_opcode(insn));
                                        }
                                    }
                                }
                            }
                        }
                    } else {
                        if insn & 0x800000 == 0 {
                            if insn & 0x400000 == 0 {
                                if insn & 0x20000000 == 0 {
                                    if insn & 0x000400 == 0 {
                                        if insn & 0x000800 == 0 {
                                            if insn & 0x200000 == 0 {
                                                if insn & 0x40000000 == 0 {
                                                    if insn & 0x80000000 == 0 {
                                                        if insn & 0xffe00c00 == 0x19000000 {
                                                            return Some(
                                                                STLURB_Rt_ADDR_OFFSET::make_opcode(
                                                                    insn,
                                                                ),
                                                            );
                                                        }
                                                    } else {
                                                        if insn & 0xffe00c00 == 0x99000000 {
                                                            return Some(
                                                                STLUR_Rt_ADDR_OFFSET::make_opcode(
                                                                    insn,
                                                                ),
                                                            );
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x80000000 == 0 {
                                                        if insn & 0xffe00c00 == 0x59000000 {
                                                            return Some(
                                                                STLURH_Rt_ADDR_OFFSET::make_opcode(
                                                                    insn,
                                                                ),
                                                            );
                                                        }
                                                    } else {
                                                        if insn & 0xffe00c00 == 0xd9000000 {
                                                            return Some(
                                                                STLUR_Rt_X_ADDR_OFFSET::make_opcode(
                                                                    insn,
                                                                ),
                                                            );
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0x001000 == 0 {
                                                    if insn & 0x002000 == 0 {
                                                        if insn & 0x008000 == 0 {
                                                            if insn & 0xfffffc00 == 0xd9200000 {
                                                                return Some (STZGM_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xffe0fc00 == 0x19208000 {
                                                                return Some (SWPP_LSE128_Rt_LSE128_Rt2_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x40000000 == 0 {
                                                            if insn & 0xffe0fc00 == 0x1920a000 {
                                                                return Some (RCWSWPP_Rt_Rs_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xffe0fc00 == 0x5920a000 {
                                                                return Some (RCWSSWPP_Rt_Rs_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x002000 == 0 {
                                                        if insn & 0x008000 == 0 {
                                                            if insn & 0xffe0fc00 == 0x19201000 {
                                                                return Some (LDCLRP_LSE128_Rt_LSE128_Rt2_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0x40000000 == 0 {
                                                                if insn & 0xffe0fc00 == 0x19209000 {
                                                                    return Some (RCWCLRP_Rt_Rs_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xffe0fc00 == 0x59209000 {
                                                                    return Some (RCWSCLRP_Rt_Rs_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x008000 == 0 {
                                                            if insn & 0xffe0fc00 == 0x19203000 {
                                                                return Some (LDSETP_LSE128_Rt_LSE128_Rt2_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0x40000000 == 0 {
                                                                if insn & 0xffe0fc00 == 0x1920b000 {
                                                                    return Some (RCWSETP_Rt_Rs_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xffe0fc00 == 0x5920b000 {
                                                                    return Some (RCWSSETP_Rt_Rs_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        }
                                                    }
                                                }
                                            }
                                        } else {
                                            if insn & 0x200000 == 0 {
                                                if insn & 0x3fe0ec00 == 0x19000800 {
                                                    return Some (STILP_Rt_Rs_RCPC3_ADDR_OPT_PREIND_WB :: make_opcode (insn)) ;
                                                }
                                            } else {
                                                if insn & 0x40000000 == 0 {
                                                    if insn & 0xffe0fc00 == 0x19200800 {
                                                        return Some(
                                                            RCWCAS_Rs_Rt_ADDR_SIMPLE::make_opcode(
                                                                insn,
                                                            ),
                                                        );
                                                    }
                                                } else {
                                                    if insn & 0x80000000 == 0 {
                                                        if insn & 0xffe0fc00 == 0x59200800 {
                                                            return Some (RCWSCAS_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xffe00c00 == 0xd9200800 {
                                                            return Some(
                                                                STG_Rt_SP_ADDR_SIMM13::make_opcode(
                                                                    insn,
                                                                ),
                                                            );
                                                        }
                                                    }
                                                }
                                            }
                                        }
                                    } else {
                                        if insn & 0x200000 == 0 {
                                            if insn & 0x000800 == 0 {
                                                if insn & 0x001000 == 0 {
                                                    if insn & 0x002000 == 0 {
                                                        if insn & 0x004000 == 0 {
                                                            if insn & 0x008000 == 0 {
                                                                if insn & 0xffe0fc00 == 0x19000400 {
                                                                    return Some (CPYFP_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xffe0fc00 == 0x19008400 {
                                                                    return Some (CPYFPRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x008000 == 0 {
                                                                if insn & 0xffe0fc00 == 0x19004400 {
                                                                    return Some (CPYFPWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xffe0fc00 == 0x1900c400 {
                                                                    return Some (CPYFPN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x004000 == 0 {
                                                            if insn & 0x008000 == 0 {
                                                                if insn & 0xffe0fc00 == 0x19002400 {
                                                                    return Some (CPYFPRT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xffe0fc00 == 0x1900a400 {
                                                                    return Some (CPYFPRTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x008000 == 0 {
                                                                if insn & 0xffe0fc00 == 0x19006400 {
                                                                    return Some (CPYFPRTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xffe0fc00 == 0x1900e400 {
                                                                    return Some (CPYFPRTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x002000 == 0 {
                                                        if insn & 0x004000 == 0 {
                                                            if insn & 0x008000 == 0 {
                                                                if insn & 0xffe0fc00 == 0x19001400 {
                                                                    return Some (CPYFPWT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xffe0fc00 == 0x19009400 {
                                                                    return Some (CPYFPWTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x008000 == 0 {
                                                                if insn & 0xffe0fc00 == 0x19005400 {
                                                                    return Some (CPYFPWTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xffe0fc00 == 0x1900d400 {
                                                                    return Some (CPYFPWTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x004000 == 0 {
                                                            if insn & 0x008000 == 0 {
                                                                if insn & 0xffe0fc00 == 0x19003400 {
                                                                    return Some (CPYFPT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xffe0fc00 == 0x1900b400 {
                                                                    return Some (CPYFPTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x008000 == 0 {
                                                                if insn & 0xffe0fc00 == 0x19007400 {
                                                                    return Some (CPYFPTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xffe0fc00 == 0x1900f400 {
                                                                    return Some (CPYFPTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0x001000 == 0 {
                                                    if insn & 0xfffffc00 == 0xd91f0c00 {
                                                        return Some(GCSSTR_Rt_Rn_SP::make_opcode(
                                                            insn,
                                                        ));
                                                    }
                                                } else {
                                                    if insn & 0xfffffc00 == 0xd91f1c00 {
                                                        return Some(
                                                            GCSSTTR_Rt_Rn_SP::make_opcode(insn),
                                                        );
                                                    }
                                                }
                                            }
                                        } else {
                                            if insn & 0x40000000 == 0 {
                                                if insn & 0xffe0fc00 == 0x19200c00 {
                                                    return Some (RCWCASP_Rs_PAIRREG_Rt_PAIRREG_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                }
                                            } else {
                                                if insn & 0x80000000 == 0 {
                                                    if insn & 0xffe0fc00 == 0x59200c00 {
                                                        return Some (RCWSCASP_Rs_PAIRREG_Rt_PAIRREG_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                    }
                                                } else {
                                                    if insn & 0xffe00400 == 0xd9200400 {
                                                        return Some (STG_Rt_SP_X_ADDR_SIMM13_imm_tag :: make_opcode (insn)) ;
                                                    }
                                                }
                                            }
                                        }
                                    }
                                } else {
                                    if insn & 0x80000000 == 0 {
                                        if insn & 0x40000000 == 0 {
                                            if insn & 0xffc00000 == 0x39000000 {
                                                return Some(STRB_Rt_ADDR_UIMM12::make_opcode(
                                                    insn,
                                                ));
                                            }
                                        } else {
                                            if insn & 0xffc00000 == 0x79000000 {
                                                return Some(STRH_Rt_ADDR_UIMM12::make_opcode(
                                                    insn,
                                                ));
                                            }
                                        }
                                    } else {
                                        if insn & 0xbfc00000 == 0xb9000000 {
                                            return Some(STR_Rt_ADDR_UIMM12::make_opcode(insn));
                                        }
                                    }
                                }
                            } else {
                                if insn & 0x20000000 == 0 {
                                    if insn & 0x000400 == 0 {
                                        if insn & 0x000800 == 0 {
                                            if insn & 0x200000 == 0 {
                                                if insn & 0x40000000 == 0 {
                                                    if insn & 0x80000000 == 0 {
                                                        if insn & 0xffe00c00 == 0x19400000 {
                                                            return Some(
                                                                LDAPURB_Rt_ADDR_OFFSET::make_opcode(
                                                                    insn,
                                                                ),
                                                            );
                                                        }
                                                    } else {
                                                        if insn & 0xffe00c00 == 0x99400000 {
                                                            return Some(
                                                                LDAPUR_Rt_ADDR_OFFSET::make_opcode(
                                                                    insn,
                                                                ),
                                                            );
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x80000000 == 0 {
                                                        if insn & 0xffe00c00 == 0x59400000 {
                                                            return Some(
                                                                LDAPURH_Rt_ADDR_OFFSET::make_opcode(
                                                                    insn,
                                                                ),
                                                            );
                                                        }
                                                    } else {
                                                        if insn & 0xffe00c00 == 0xd9400000 {
                                                            return Some (LDAPUR_Rt_X_ADDR_OFFSET :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0x40000000 == 0 {
                                                    if insn & 0x001000 == 0 {
                                                        if insn & 0x002000 == 0 {
                                                            if insn & 0xffe0fc00 == 0x19608000 {
                                                                return Some (SWPPL_LSE128_Rt_LSE128_Rt2_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xffe0fc00 == 0x1960a000 {
                                                                return Some (RCWSWPPL_Rt_Rs_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x002000 == 0 {
                                                            if insn & 0x008000 == 0 {
                                                                if insn & 0xffe0fc00 == 0x19601000 {
                                                                    return Some (LDCLRPL_LSE128_Rt_LSE128_Rt2_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xffe0fc00 == 0x19609000 {
                                                                    return Some (RCWCLRPL_Rt_Rs_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x008000 == 0 {
                                                                if insn & 0xffe0fc00 == 0x19603000 {
                                                                    return Some (LDSETPL_LSE128_Rt_LSE128_Rt2_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xffe0fc00 == 0x1960b000 {
                                                                    return Some (RCWSETPL_Rt_Rs_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x80000000 == 0 {
                                                        if insn & 0x001000 == 0 {
                                                            if insn & 0xffe0fc00 == 0x5960a000 {
                                                                return Some (RCWSSWPPL_Rt_Rs_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0x002000 == 0 {
                                                                if insn & 0xffe0fc00 == 0x59609000 {
                                                                    return Some (RCWSCLRPL_Rt_Rs_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xffe0fc00 == 0x5960b000 {
                                                                    return Some (RCWSSETPL_Rt_Rs_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0xffe00c00 == 0xd9600000 {
                                                            return Some(
                                                                LDG_Rt_ADDR_SIMM13::make_opcode(
                                                                    insn,
                                                                ),
                                                            );
                                                        }
                                                    }
                                                }
                                            }
                                        } else {
                                            if insn & 0x200000 == 0 {
                                                if insn & 0x3fe0ec00 == 0x19400800 {
                                                    return Some (LDIAPP_Rt_Rs_RCPC3_ADDR_OPT_POSTIND :: make_opcode (insn)) ;
                                                }
                                            } else {
                                                if insn & 0x40000000 == 0 {
                                                    if insn & 0xffe0fc00 == 0x19600800 {
                                                        return Some(
                                                            RCWCASL_Rs_Rt_ADDR_SIMPLE::make_opcode(
                                                                insn,
                                                            ),
                                                        );
                                                    }
                                                } else {
                                                    if insn & 0x80000000 == 0 {
                                                        if insn & 0xffe0fc00 == 0x59600800 {
                                                            return Some (RCWSCASL_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xffe00c00 == 0xd9600800 {
                                                            return Some(
                                                                STZG_Rt_SP_ADDR_SIMM13::make_opcode(
                                                                    insn,
                                                                ),
                                                            );
                                                        }
                                                    }
                                                }
                                            }
                                        }
                                    } else {
                                        if insn & 0x200000 == 0 {
                                            if insn & 0x001000 == 0 {
                                                if insn & 0x002000 == 0 {
                                                    if insn & 0x004000 == 0 {
                                                        if insn & 0x008000 == 0 {
                                                            if insn & 0xffe0fc00 == 0x19400400 {
                                                                return Some (CPYFM_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xffe0fc00 == 0x19408400 {
                                                                return Some (CPYFMRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x008000 == 0 {
                                                            if insn & 0xffe0fc00 == 0x19404400 {
                                                                return Some (CPYFMWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xffe0fc00 == 0x1940c400 {
                                                                return Some (CPYFMN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x004000 == 0 {
                                                        if insn & 0x008000 == 0 {
                                                            if insn & 0xffe0fc00 == 0x19402400 {
                                                                return Some (CPYFMRT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xffe0fc00 == 0x1940a400 {
                                                                return Some (CPYFMRTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x008000 == 0 {
                                                            if insn & 0xffe0fc00 == 0x19406400 {
                                                                return Some (CPYFMRTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xffe0fc00 == 0x1940e400 {
                                                                return Some (CPYFMRTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0x002000 == 0 {
                                                    if insn & 0x004000 == 0 {
                                                        if insn & 0x008000 == 0 {
                                                            if insn & 0xffe0fc00 == 0x19401400 {
                                                                return Some (CPYFMWT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xffe0fc00 == 0x19409400 {
                                                                return Some (CPYFMWTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x008000 == 0 {
                                                            if insn & 0xffe0fc00 == 0x19405400 {
                                                                return Some (CPYFMWTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xffe0fc00 == 0x1940d400 {
                                                                return Some (CPYFMWTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x004000 == 0 {
                                                        if insn & 0x008000 == 0 {
                                                            if insn & 0xffe0fc00 == 0x19403400 {
                                                                return Some (CPYFMT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xffe0fc00 == 0x1940b400 {
                                                                return Some (CPYFMTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x008000 == 0 {
                                                            if insn & 0xffe0fc00 == 0x19407400 {
                                                                return Some (CPYFMTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xffe0fc00 == 0x1940f400 {
                                                                return Some (CPYFMTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    }
                                                }
                                            }
                                        } else {
                                            if insn & 0x40000000 == 0 {
                                                if insn & 0xffe0fc00 == 0x19600c00 {
                                                    return Some (RCWCASPL_Rs_PAIRREG_Rt_PAIRREG_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                }
                                            } else {
                                                if insn & 0x80000000 == 0 {
                                                    if insn & 0xffe0fc00 == 0x59600c00 {
                                                        return Some (RCWSCASPL_Rs_PAIRREG_Rt_PAIRREG_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                    }
                                                } else {
                                                    if insn & 0xffe00400 == 0xd9600400 {
                                                        return Some (STZG_Rt_SP_X_ADDR_SIMM13_imm_tag :: make_opcode (insn)) ;
                                                    }
                                                }
                                            }
                                        }
                                    }
                                } else {
                                    if insn & 0x80000000 == 0 {
                                        if insn & 0x40000000 == 0 {
                                            if insn & 0xffc00000 == 0x39400000 {
                                                return Some(LDRB_Rt_ADDR_UIMM12::make_opcode(
                                                    insn,
                                                ));
                                            }
                                        } else {
                                            if insn & 0xffc00000 == 0x79400000 {
                                                return Some(LDRH_Rt_ADDR_UIMM12::make_opcode(
                                                    insn,
                                                ));
                                            }
                                        }
                                    } else {
                                        if insn & 0xbfc00000 == 0xb9400000 {
                                            return Some(LDR_Rt_ADDR_UIMM12::make_opcode(insn));
                                        }
                                    }
                                }
                            }
                        } else {
                            if insn & 0x20000000 == 0 {
                                if insn & 0x000400 == 0 {
                                    if insn & 0x000800 == 0 {
                                        if insn & 0x200000 == 0 {
                                            if insn & 0x400000 == 0 {
                                                if insn & 0x40000000 == 0 {
                                                    if insn & 0x80000000 == 0 {
                                                        if insn & 0xffe00c00 == 0x19800000 {
                                                            return Some (LDAPURSB_Rt_ADDR_OFFSET :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xffe00c00 == 0x99800000 {
                                                            return Some (LDAPURSW_Rt_ADDR_OFFSET :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0xffe00c00 == 0x59800000 {
                                                        return Some(
                                                            LDAPURSH_Rt_ADDR_OFFSET::make_opcode(
                                                                insn,
                                                            ),
                                                        );
                                                    }
                                                }
                                            } else {
                                                if insn & 0x40000000 == 0 {
                                                    if insn & 0xffe00c00 == 0x19c00000 {
                                                        return Some(
                                                            LDAPURSB_Rt_W_ADDR_OFFSET::make_opcode(
                                                                insn,
                                                            ),
                                                        );
                                                    }
                                                } else {
                                                    if insn & 0xffe00c00 == 0x59c00000 {
                                                        return Some(
                                                            LDAPURSH_Rt_W_ADDR_OFFSET::make_opcode(
                                                                insn,
                                                            ),
                                                        );
                                                    }
                                                }
                                            }
                                        } else {
                                            if insn & 0x001000 == 0 {
                                                if insn & 0x002000 == 0 {
                                                    if insn & 0x008000 == 0 {
                                                        if insn & 0x400000 == 0 {
                                                            if insn & 0xfffffc00 == 0xd9a00000 {
                                                                return Some (STGM_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xfffffc00 == 0xd9e00000 {
                                                                return Some (LDGM_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x400000 == 0 {
                                                            if insn & 0xffe0fc00 == 0x19a08000 {
                                                                return Some (SWPPA_LSE128_Rt_LSE128_Rt2_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xffe0fc00 == 0x19e08000 {
                                                                return Some (SWPPAL_LSE128_Rt_LSE128_Rt2_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x400000 == 0 {
                                                        if insn & 0x40000000 == 0 {
                                                            if insn & 0xffe0fc00 == 0x19a0a000 {
                                                                return Some (RCWSWPPA_Rt_Rs_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xffe0fc00 == 0x59a0a000 {
                                                                return Some (RCWSSWPPA_Rt_Rs_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x40000000 == 0 {
                                                            if insn & 0xffe0fc00 == 0x19e0a000 {
                                                                return Some (RCWSWPPAL_Rt_Rs_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xffe0fc00 == 0x59e0a000 {
                                                                return Some (RCWSSWPPAL_Rt_Rs_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0x002000 == 0 {
                                                    if insn & 0x008000 == 0 {
                                                        if insn & 0x400000 == 0 {
                                                            if insn & 0xffe0fc00 == 0x19a01000 {
                                                                return Some (LDCLRPA_LSE128_Rt_LSE128_Rt2_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xffe0fc00 == 0x19e01000 {
                                                                return Some (LDCLRPAL_LSE128_Rt_LSE128_Rt2_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x400000 == 0 {
                                                            if insn & 0x40000000 == 0 {
                                                                if insn & 0xffe0fc00 == 0x19a09000 {
                                                                    return Some (RCWCLRPA_Rt_Rs_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xffe0fc00 == 0x59a09000 {
                                                                    return Some (RCWSCLRPA_Rt_Rs_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x40000000 == 0 {
                                                                if insn & 0xffe0fc00 == 0x19e09000 {
                                                                    return Some (RCWCLRPAL_Rt_Rs_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xffe0fc00 == 0x59e09000 {
                                                                    return Some (RCWSCLRPAL_Rt_Rs_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x008000 == 0 {
                                                        if insn & 0x400000 == 0 {
                                                            if insn & 0xffe0fc00 == 0x19a03000 {
                                                                return Some (LDSETPA_LSE128_Rt_LSE128_Rt2_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xffe0fc00 == 0x19e03000 {
                                                                return Some (LDSETPAL_LSE128_Rt_LSE128_Rt2_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x400000 == 0 {
                                                            if insn & 0x40000000 == 0 {
                                                                if insn & 0xffe0fc00 == 0x19a0b000 {
                                                                    return Some (RCWSETPA_Rt_Rs_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xffe0fc00 == 0x59a0b000 {
                                                                    return Some (RCWSSETPA_Rt_Rs_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x40000000 == 0 {
                                                                if insn & 0xffe0fc00 == 0x19e0b000 {
                                                                    return Some (RCWSETPAL_Rt_Rs_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xffe0fc00 == 0x59e0b000 {
                                                                    return Some (RCWSSETPAL_Rt_Rs_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        }
                                                    }
                                                }
                                            }
                                        }
                                    } else {
                                        if insn & 0x200000 == 0 {
                                            if insn & 0x400000 == 0 {
                                                if insn & 0x3ffffc00 == 0x19800800 {
                                                    return Some(
                                                        STLR_Rt_RCPC3_ADDR_PREIND_WB::make_opcode(
                                                            insn,
                                                        ),
                                                    );
                                                }
                                            } else {
                                                if insn & 0x3ffffc00 == 0x19c00800 {
                                                    return Some(
                                                        LDAPR_Rt_RCPC3_ADDR_POSTIND::make_opcode(
                                                            insn,
                                                        ),
                                                    );
                                                }
                                            }
                                        } else {
                                            if insn & 0x400000 == 0 {
                                                if insn & 0x40000000 == 0 {
                                                    if insn & 0xffe0fc00 == 0x19a00800 {
                                                        return Some(
                                                            RCWCASA_Rs_Rt_ADDR_SIMPLE::make_opcode(
                                                                insn,
                                                            ),
                                                        );
                                                    }
                                                } else {
                                                    if insn & 0x80000000 == 0 {
                                                        if insn & 0xffe0fc00 == 0x59a00800 {
                                                            return Some (RCWSCASA_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xffe00c00 == 0xd9a00800 {
                                                            return Some(
                                                                ST2G_Rt_SP_ADDR_SIMM13::make_opcode(
                                                                    insn,
                                                                ),
                                                            );
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0x40000000 == 0 {
                                                    if insn & 0xffe0fc00 == 0x19e00800 {
                                                        return Some(
                                                            RCWCASAL_Rs_Rt_ADDR_SIMPLE::make_opcode(
                                                                insn,
                                                            ),
                                                        );
                                                    }
                                                } else {
                                                    if insn & 0x80000000 == 0 {
                                                        if insn & 0xffe0fc00 == 0x59e00800 {
                                                            return Some (RCWSCASAL_Rs_Rt_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xffe00c00 == 0xd9e00800 {
                                                            return Some (STZ2G_Rt_SP_ADDR_SIMM13 :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                }
                                            }
                                        }
                                    }
                                } else {
                                    if insn & 0x200000 == 0 {
                                        if insn & 0x001000 == 0 {
                                            if insn & 0x002000 == 0 {
                                                if insn & 0x004000 == 0 {
                                                    if insn & 0x008000 == 0 {
                                                        if insn & 0x400000 == 0 {
                                                            if insn & 0xffe0fc00 == 0x19800400 {
                                                                return Some (CPYFE_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xffe0fc00 == 0x19c00400 {
                                                                return Some (SETP_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x400000 == 0 {
                                                            if insn & 0xffe0fc00 == 0x19808400 {
                                                                return Some (CPYFERN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xffe0fc00 == 0x19c08400 {
                                                                return Some (SETE_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x008000 == 0 {
                                                        if insn & 0x400000 == 0 {
                                                            if insn & 0xffe0fc00 == 0x19804400 {
                                                                return Some (CPYFEWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xffe0fc00 == 0x19c04400 {
                                                                return Some (SETM_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0xffe0fc00 == 0x1980c400 {
                                                            return Some (CPYFEN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0x004000 == 0 {
                                                    if insn & 0x008000 == 0 {
                                                        if insn & 0x400000 == 0 {
                                                            if insn & 0xffe0fc00 == 0x19802400 {
                                                                return Some (CPYFERT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xffe0fc00 == 0x19c02400 {
                                                                return Some (SETPN_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x400000 == 0 {
                                                            if insn & 0xffe0fc00 == 0x1980a400 {
                                                                return Some (CPYFERTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xffe0fc00 == 0x19c0a400 {
                                                                return Some (SETEN_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x008000 == 0 {
                                                        if insn & 0x400000 == 0 {
                                                            if insn & 0xffe0fc00 == 0x19806400 {
                                                                return Some (CPYFERTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xffe0fc00 == 0x19c06400 {
                                                                return Some (SETMN_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0xffe0fc00 == 0x1980e400 {
                                                            return Some (CPYFERTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                }
                                            }
                                        } else {
                                            if insn & 0x002000 == 0 {
                                                if insn & 0x004000 == 0 {
                                                    if insn & 0x008000 == 0 {
                                                        if insn & 0x400000 == 0 {
                                                            if insn & 0xffe0fc00 == 0x19801400 {
                                                                return Some (CPYFEWT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xffe0fc00 == 0x19c01400 {
                                                                return Some (SETPT_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x400000 == 0 {
                                                            if insn & 0xffe0fc00 == 0x19809400 {
                                                                return Some (CPYFEWTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xffe0fc00 == 0x19c09400 {
                                                                return Some (SETET_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x008000 == 0 {
                                                        if insn & 0x400000 == 0 {
                                                            if insn & 0xffe0fc00 == 0x19805400 {
                                                                return Some (CPYFEWTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xffe0fc00 == 0x19c05400 {
                                                                return Some (SETMT_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0xffe0fc00 == 0x1980d400 {
                                                            return Some (CPYFEWTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0x004000 == 0 {
                                                    if insn & 0x008000 == 0 {
                                                        if insn & 0x400000 == 0 {
                                                            if insn & 0xffe0fc00 == 0x19803400 {
                                                                return Some (CPYFET_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xffe0fc00 == 0x19c03400 {
                                                                return Some (SETPTN_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x400000 == 0 {
                                                            if insn & 0xffe0fc00 == 0x1980b400 {
                                                                return Some (CPYFETRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xffe0fc00 == 0x19c0b400 {
                                                                return Some (SETETN_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x008000 == 0 {
                                                        if insn & 0x400000 == 0 {
                                                            if insn & 0xffe0fc00 == 0x19807400 {
                                                                return Some (CPYFETWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xffe0fc00 == 0x19c07400 {
                                                                return Some (SETMTN_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0xffe0fc00 == 0x1980f400 {
                                                            return Some (CPYFETN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                }
                                            }
                                        }
                                    } else {
                                        if insn & 0x400000 == 0 {
                                            if insn & 0x40000000 == 0 {
                                                if insn & 0xffe0fc00 == 0x19a00c00 {
                                                    return Some (RCWCASPA_Rs_PAIRREG_Rt_PAIRREG_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                }
                                            } else {
                                                if insn & 0x80000000 == 0 {
                                                    if insn & 0xffe0fc00 == 0x59a00c00 {
                                                        return Some (RCWSCASPA_Rs_PAIRREG_Rt_PAIRREG_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                    }
                                                } else {
                                                    if insn & 0xffe00400 == 0xd9a00400 {
                                                        return Some (ST2G_Rt_SP_X_ADDR_SIMM13_imm_tag :: make_opcode (insn)) ;
                                                    }
                                                }
                                            }
                                        } else {
                                            if insn & 0x40000000 == 0 {
                                                if insn & 0xffe0fc00 == 0x19e00c00 {
                                                    return Some (RCWCASPAL_Rs_PAIRREG_Rt_PAIRREG_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                }
                                            } else {
                                                if insn & 0x80000000 == 0 {
                                                    if insn & 0xffe0fc00 == 0x59e00c00 {
                                                        return Some (RCWSCASPAL_Rs_PAIRREG_Rt_PAIRREG_ADDR_SIMPLE :: make_opcode (insn)) ;
                                                    }
                                                } else {
                                                    if insn & 0xffe00400 == 0xd9e00400 {
                                                        return Some (STZ2G_Rt_SP_X_ADDR_SIMM13_imm_tag :: make_opcode (insn)) ;
                                                    }
                                                }
                                            }
                                        }
                                    }
                                }
                            } else {
                                if insn & 0x40000000 == 0 {
                                    if insn & 0x80000000 == 0 {
                                        if insn & 0xff800000 == 0x39800000 {
                                            return Some(LDRSB_Rt_ADDR_UIMM12::make_opcode(insn));
                                        }
                                    } else {
                                        if insn & 0xffc00000 == 0xb9800000 {
                                            return Some(LDRSW_Rt_ADDR_UIMM12::make_opcode(insn));
                                        }
                                    }
                                } else {
                                    if insn & 0x80000000 == 0 {
                                        if insn & 0xff800000 == 0x79800000 {
                                            return Some(LDRSH_Rt_ADDR_UIMM12::make_opcode(insn));
                                        }
                                    } else {
                                        if insn & 0xffc00000 == 0xf9800000 {
                                            return Some(PRFM_PRFOP_ADDR_UIMM12::make_opcode(insn));
                                        }
                                    }
                                }
                            }
                        }
                    }
                }
            }
        } else {
            if insn & 0x1000000 == 0 {
                if insn & 0x8000000 == 0 {
                    if insn & 0x800000 == 0 {
                        if insn & 0x20000000 == 0 {
                            if insn & 0x40000000 == 0 {
                                if insn & 0x7f800000 == 0x12000000 {
                                    return Some(AND_Rd_SP_Rn_LIMM::make_opcode(insn));
                                }
                            } else {
                                if insn & 0x7f800000 == 0x52000000 {
                                    return Some(EOR_Rd_SP_Rn_LIMM::make_opcode(insn));
                                }
                            }
                        } else {
                            if insn & 0x40000000 == 0 {
                                if insn & 0x7f800000 == 0x32000000 {
                                    return Some(ORR_Rd_SP_Rn_LIMM::make_opcode(insn));
                                }
                            } else {
                                if insn & 0x7f800000 == 0x72000000 {
                                    return Some(ANDS_Rd_Rn_LIMM::make_opcode(insn));
                                }
                            }
                        }
                    } else {
                        if insn & 0x20000000 == 0 {
                            if insn & 0x40000000 == 0 {
                                if insn & 0x7f800000 == 0x12800000 {
                                    return Some(MOVN_Rd_HALF::make_opcode(insn));
                                }
                            } else {
                                if insn & 0x7f800000 == 0x52800000 {
                                    return Some(MOVZ_Rd_HALF::make_opcode(insn));
                                }
                            }
                        } else {
                            if insn & 0x7f800000 == 0x72800000 {
                                return Some(MOVK_Rd_HALF::make_opcode(insn));
                            }
                        }
                    }
                } else {
                    if insn & 0x200000 == 0 {
                        if insn & 0x10000000 == 0 {
                            if insn & 0x20000000 == 0 {
                                if insn & 0x40000000 == 0 {
                                    if insn & 0x7f200000 == 0xa000000 {
                                        return Some(AND_Rd_Rn_Rm_SFT::make_opcode(insn));
                                    }
                                } else {
                                    if insn & 0x7f200000 == 0x4a000000 {
                                        return Some(EOR_Rd_Rn_Rm_SFT::make_opcode(insn));
                                    }
                                }
                            } else {
                                if insn & 0x40000000 == 0 {
                                    if insn & 0x7f200000 == 0x2a000000 {
                                        return Some(ORR_Rd_Rn_Rm_SFT::make_opcode(insn));
                                    }
                                } else {
                                    if insn & 0x7f200000 == 0x6a000000 {
                                        return Some(ANDS_Rd_Rn_Rm_SFT::make_opcode(insn));
                                    }
                                }
                            }
                        } else {
                            if insn & 0x000400 == 0 {
                                if insn & 0x000800 == 0 {
                                    if insn & 0x400000 == 0 {
                                        if insn & 0x800000 == 0 {
                                            if insn & 0x20000000 == 0 {
                                                if insn & 0x40000000 == 0 {
                                                    if insn & 0x7fe0fc00 == 0x1a000000 {
                                                        return Some(ADC_Rd_Rn_Rm::make_opcode(
                                                            insn,
                                                        ));
                                                    }
                                                } else {
                                                    if insn & 0x7fe0fc00 == 0x5a000000 {
                                                        return Some(SBC_Rd_Rn_Rm::make_opcode(
                                                            insn,
                                                        ));
                                                    }
                                                }
                                            } else {
                                                if insn & 0x40000000 == 0 {
                                                    if insn & 0x7fe0fc00 == 0x3a000000 {
                                                        return Some(ADCS_Rd_Rn_Rm::make_opcode(
                                                            insn,
                                                        ));
                                                    }
                                                } else {
                                                    if insn & 0x7fe0fc00 == 0x7a000000 {
                                                        return Some(SBCS_Rd_Rn_Rm::make_opcode(
                                                            insn,
                                                        ));
                                                    }
                                                }
                                            }
                                        } else {
                                            if insn & 0x40000000 == 0 {
                                                if insn & 0x7fe00c00 == 0x1a800000 {
                                                    return Some(CSEL_Rd_Rn_Rm_COND::make_opcode(
                                                        insn,
                                                    ));
                                                }
                                            } else {
                                                if insn & 0x7fe00c00 == 0x5a800000 {
                                                    return Some(CSINV_Rd_Rn_Rm_COND::make_opcode(
                                                        insn,
                                                    ));
                                                }
                                            }
                                        }
                                    } else {
                                        if insn & 0x800000 == 0 {
                                            if insn & 0x40000000 == 0 {
                                                if insn & 0x7fe00c10 == 0x3a400000 {
                                                    return Some(
                                                        CCMN_Rn_Rm_NZCV_COND::make_opcode(insn),
                                                    );
                                                }
                                            } else {
                                                if insn & 0x7fe00c10 == 0x7a400000 {
                                                    return Some(
                                                        CCMP_Rn_Rm_NZCV_COND::make_opcode(insn),
                                                    );
                                                }
                                            }
                                        } else {
                                            if insn & 0x001000 == 0 {
                                                if insn & 0x002000 == 0 {
                                                    if insn & 0x004000 == 0 {
                                                        if insn & 0x20000000 == 0 {
                                                            if insn & 0x40000000 == 0 {
                                                                if insn & 0xffe0fc00 == 0x9ac00000 {
                                                                    return Some (SUBP_Rd_Rn_SP_Rm_SP :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0x010000 == 0 {
                                                                    if insn & 0x7ffffc00
                                                                        == 0x5ac00000
                                                                    {
                                                                        return Some(
                                                                            RBIT_Rd_Rn::make_opcode(
                                                                                insn,
                                                                            ),
                                                                        );
                                                                    }
                                                                } else {
                                                                    if insn & 0xfffffc00
                                                                        == 0xdac10000
                                                                    {
                                                                        return Some (PACIA_Rd_Rn_SP :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0xffe0fc00 == 0xbac00000 {
                                                                return Some (SUBPS_Rd_Rn_SP_Rm_SP :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x40000000 == 0 {
                                                            if insn & 0xffe0fc00 == 0x1ac04000 {
                                                                return Some(
                                                                    CRC32B_Rd_Rn_Rm::make_opcode(
                                                                        insn,
                                                                    ),
                                                                );
                                                            }
                                                        } else {
                                                            if insn & 0xffffffe0 == 0xdac143e0 {
                                                                return Some(
                                                                    XPACI_Rd::make_opcode(insn),
                                                                );
                                                            }
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x004000 == 0 {
                                                        if insn & 0x40000000 == 0 {
                                                            if insn & 0x7fe0fc00 == 0x1ac02000 {
                                                                return Some(
                                                                    LSLV_Rd_Rn_Rm::make_opcode(
                                                                        insn,
                                                                    ),
                                                                );
                                                            }
                                                        } else {
                                                            if insn & 0x010000 == 0 {
                                                                if insn & 0x7ffffc00 == 0x5ac02000 {
                                                                    return Some(
                                                                        ABS_Rd_Rn::make_opcode(
                                                                            insn,
                                                                        ),
                                                                    );
                                                                }
                                                            } else {
                                                                if insn & 0xffffffe0 == 0xdac123e0 {
                                                                    return Some(
                                                                        PACIZA_Rd::make_opcode(
                                                                            insn,
                                                                        ),
                                                                    );
                                                                }
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x7fe0fc00 == 0x1ac06000 {
                                                            return Some(
                                                                SMAX_Rd_Rn_Rm::make_opcode(insn),
                                                            );
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0x002000 == 0 {
                                                    if insn & 0x004000 == 0 {
                                                        if insn & 0x40000000 == 0 {
                                                            if insn & 0xffe0fc00 == 0x9ac01000 {
                                                                return Some(
                                                                    IRG_Rd_SP_Rn_SP_Rm::make_opcode(
                                                                        insn,
                                                                    ),
                                                                );
                                                            }
                                                        } else {
                                                            if insn & 0x010000 == 0 {
                                                                if insn & 0x7ffffc00 == 0x5ac01000 {
                                                                    return Some(
                                                                        CLZ_Rd_Rn::make_opcode(
                                                                            insn,
                                                                        ),
                                                                    );
                                                                }
                                                            } else {
                                                                if insn & 0xfffffc00 == 0xdac11000 {
                                                                    return Some(
                                                                        AUTIA_Rd_Rn_SP::make_opcode(
                                                                            insn,
                                                                        ),
                                                                    );
                                                                }
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0xffe0fc00 == 0x1ac05000 {
                                                            return Some(
                                                                CRC32CB_Rd_Rn_Rm::make_opcode(insn),
                                                            );
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x40000000 == 0 {
                                                        if insn & 0xffe0fc00 == 0x9ac03000 {
                                                            return Some(
                                                                PACGA_Rd_Rn_Rm_SP::make_opcode(
                                                                    insn,
                                                                ),
                                                            );
                                                        }
                                                    } else {
                                                        if insn & 0xffffffe0 == 0xdac133e0 {
                                                            return Some(AUTIZA_Rd::make_opcode(
                                                                insn,
                                                            ));
                                                        }
                                                    }
                                                }
                                            }
                                        }
                                    }
                                } else {
                                    if insn & 0x400000 == 0 {
                                        if insn & 0x004000 == 0 {
                                            if insn & 0xfffffc1f == 0x3a00080d {
                                                return Some(SETF8_Rn::make_opcode(insn));
                                            }
                                        } else {
                                            if insn & 0xfffffc1f == 0x3a00480d {
                                                return Some(SETF16_Rn::make_opcode(insn));
                                            }
                                        }
                                    } else {
                                        if insn & 0x800000 == 0 {
                                            if insn & 0x40000000 == 0 {
                                                if insn & 0x7fe00c10 == 0x3a400800 {
                                                    return Some(
                                                        CCMN_Rn_CCMP_IMM_NZCV_COND::make_opcode(
                                                            insn,
                                                        ),
                                                    );
                                                }
                                            } else {
                                                if insn & 0x7fe00c10 == 0x7a400800 {
                                                    return Some(
                                                        CCMP_Rn_CCMP_IMM_NZCV_COND::make_opcode(
                                                            insn,
                                                        ),
                                                    );
                                                }
                                            }
                                        } else {
                                            if insn & 0x001000 == 0 {
                                                if insn & 0x002000 == 0 {
                                                    if insn & 0x004000 == 0 {
                                                        if insn & 0x40000000 == 0 {
                                                            if insn & 0x7fe0fc00 == 0x1ac00800 {
                                                                return Some(
                                                                    UDIV_Rd_Rn_Rm::make_opcode(
                                                                        insn,
                                                                    ),
                                                                );
                                                            }
                                                        } else {
                                                            if insn & 0x010000 == 0 {
                                                                if insn & 0x80000000 == 0 {
                                                                    if insn & 0xfffffc00
                                                                        == 0x5ac00800
                                                                    {
                                                                        return Some(
                                                                            REV_Rd_Rn::make_opcode(
                                                                                insn,
                                                                            ),
                                                                        );
                                                                    }
                                                                } else {
                                                                    if insn & 0xfffffc00
                                                                        == 0xdac00800
                                                                    {
                                                                        return Some (REV32_Rd_Rn :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0xfffffc00 == 0xdac10800 {
                                                                    return Some(
                                                                        PACDA_Rd_Rn_SP::make_opcode(
                                                                            insn,
                                                                        ),
                                                                    );
                                                                }
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0xffe0fc00 == 0x1ac04800 {
                                                            return Some(
                                                                CRC32W_Rd_Rn_Rm::make_opcode(insn),
                                                            );
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x004000 == 0 {
                                                        if insn & 0x40000000 == 0 {
                                                            if insn & 0x7fe0fc00 == 0x1ac02800 {
                                                                return Some(
                                                                    ASRV_Rd_Rn_Rm::make_opcode(
                                                                        insn,
                                                                    ),
                                                                );
                                                            }
                                                        } else {
                                                            if insn & 0xffffffe0 == 0xdac12be0 {
                                                                return Some(
                                                                    PACDZA_Rd::make_opcode(insn),
                                                                );
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x7fe0fc00 == 0x1ac06800 {
                                                            return Some(
                                                                SMIN_Rd_Rn_Rm::make_opcode(insn),
                                                            );
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0x002000 == 0 {
                                                    if insn & 0x004000 == 0 {
                                                        if insn & 0x010000 == 0 {
                                                            if insn & 0x7ffffc00 == 0x5ac01800 {
                                                                return Some(
                                                                    CTZ_Rd_Rn::make_opcode(insn),
                                                                );
                                                            }
                                                        } else {
                                                            if insn & 0xfffffc00 == 0xdac11800 {
                                                                return Some(
                                                                    AUTDA_Rd_Rn_SP::make_opcode(
                                                                        insn,
                                                                    ),
                                                                );
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0xffe0fc00 == 0x1ac05800 {
                                                            return Some(
                                                                CRC32CW_Rd_Rn_Rm::make_opcode(insn),
                                                            );
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0xffffffe0 == 0xdac13be0 {
                                                        return Some(AUTDZA_Rd::make_opcode(insn));
                                                    }
                                                }
                                            }
                                        }
                                    }
                                }
                            } else {
                                if insn & 0x000800 == 0 {
                                    if insn & 0x400000 == 0 {
                                        if insn & 0x800000 == 0 {
                                            if insn & 0xffe07c10 == 0xba000400 {
                                                return Some(RMIF_Rn_IMM_2_MASK::make_opcode(insn));
                                            }
                                        } else {
                                            if insn & 0x40000000 == 0 {
                                                if insn & 0x7fe00c00 == 0x1a800400 {
                                                    return Some(CSINC_Rd_Rn_Rm_COND::make_opcode(
                                                        insn,
                                                    ));
                                                }
                                            } else {
                                                if insn & 0x7fe00c00 == 0x5a800400 {
                                                    return Some(CSNEG_Rd_Rn_Rm_COND::make_opcode(
                                                        insn,
                                                    ));
                                                }
                                            }
                                        }
                                    } else {
                                        if insn & 0x001000 == 0 {
                                            if insn & 0x002000 == 0 {
                                                if insn & 0x004000 == 0 {
                                                    if insn & 0x010000 == 0 {
                                                        if insn & 0x7ffffc00 == 0x5ac00400 {
                                                            return Some(REV16_Rd_Rn::make_opcode(
                                                                insn,
                                                            ));
                                                        }
                                                    } else {
                                                        if insn & 0xfffffc00 == 0xdac10400 {
                                                            return Some(
                                                                PACIB_Rd_Rn_SP::make_opcode(insn),
                                                            );
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x40000000 == 0 {
                                                        if insn & 0xffe0fc00 == 0x1ac04400 {
                                                            return Some(
                                                                CRC32H_Rd_Rn_Rm::make_opcode(insn),
                                                            );
                                                        }
                                                    } else {
                                                        if insn & 0xffffffe0 == 0xdac147e0 {
                                                            return Some(XPACD_Rd::make_opcode(
                                                                insn,
                                                            ));
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0x004000 == 0 {
                                                    if insn & 0x40000000 == 0 {
                                                        if insn & 0x7fe0fc00 == 0x1ac02400 {
                                                            return Some(
                                                                LSRV_Rd_Rn_Rm::make_opcode(insn),
                                                            );
                                                        }
                                                    } else {
                                                        if insn & 0xffffffe0 == 0xdac127e0 {
                                                            return Some(PACIZB_Rd::make_opcode(
                                                                insn,
                                                            ));
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x7fe0fc00 == 0x1ac06400 {
                                                        return Some(UMAX_Rd_Rn_Rm::make_opcode(
                                                            insn,
                                                        ));
                                                    }
                                                }
                                            }
                                        } else {
                                            if insn & 0x002000 == 0 {
                                                if insn & 0x004000 == 0 {
                                                    if insn & 0x40000000 == 0 {
                                                        if insn & 0xffe0fc00 == 0x9ac01400 {
                                                            return Some(
                                                                GMI_Rd_Rn_SP_Rm::make_opcode(insn),
                                                            );
                                                        }
                                                    } else {
                                                        if insn & 0x010000 == 0 {
                                                            if insn & 0x7ffffc00 == 0x5ac01400 {
                                                                return Some(
                                                                    CLS_Rd_Rn::make_opcode(insn),
                                                                );
                                                            }
                                                        } else {
                                                            if insn & 0xfffffc00 == 0xdac11400 {
                                                                return Some(
                                                                    AUTIB_Rd_Rn_SP::make_opcode(
                                                                        insn,
                                                                    ),
                                                                );
                                                            }
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0xffe0fc00 == 0x1ac05400 {
                                                        return Some(
                                                            CRC32CH_Rd_Rn_Rm::make_opcode(insn),
                                                        );
                                                    }
                                                }
                                            } else {
                                                if insn & 0xffffffe0 == 0xdac137e0 {
                                                    return Some(AUTIZB_Rd::make_opcode(insn));
                                                }
                                            }
                                        }
                                    }
                                } else {
                                    if insn & 0x001000 == 0 {
                                        if insn & 0x002000 == 0 {
                                            if insn & 0x004000 == 0 {
                                                if insn & 0x40000000 == 0 {
                                                    if insn & 0x7fe0fc00 == 0x1ac00c00 {
                                                        return Some(SDIV_Rd_Rn_Rm::make_opcode(
                                                            insn,
                                                        ));
                                                    }
                                                } else {
                                                    if insn & 0x010000 == 0 {
                                                        if insn & 0xfffffc00 == 0xdac00c00 {
                                                            return Some(
                                                                REV_Rd_X_Rn_X::make_opcode(insn),
                                                            );
                                                        }
                                                    } else {
                                                        if insn & 0xfffffc00 == 0xdac10c00 {
                                                            return Some(
                                                                PACDB_Rd_Rn_SP::make_opcode(insn),
                                                            );
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0xffe0fc00 == 0x9ac04c00 {
                                                    return Some(CRC32X_Rd_Rn_Rm::make_opcode(
                                                        insn,
                                                    ));
                                                }
                                            }
                                        } else {
                                            if insn & 0x004000 == 0 {
                                                if insn & 0x40000000 == 0 {
                                                    if insn & 0x7fe0fc00 == 0x1ac02c00 {
                                                        return Some(RORV_Rd_Rn_Rm::make_opcode(
                                                            insn,
                                                        ));
                                                    }
                                                } else {
                                                    if insn & 0xffffffe0 == 0xdac12fe0 {
                                                        return Some(PACDZB_Rd::make_opcode(insn));
                                                    }
                                                }
                                            } else {
                                                if insn & 0x7fe0fc00 == 0x1ac06c00 {
                                                    return Some(UMIN_Rd_Rn_Rm::make_opcode(insn));
                                                }
                                            }
                                        }
                                    } else {
                                        if insn & 0x002000 == 0 {
                                            if insn & 0x004000 == 0 {
                                                if insn & 0x010000 == 0 {
                                                    if insn & 0x7ffffc00 == 0x5ac01c00 {
                                                        return Some(CNT_Rd_Rn::make_opcode(insn));
                                                    }
                                                } else {
                                                    if insn & 0xfffffc00 == 0xdac11c00 {
                                                        return Some(AUTDB_Rd_Rn_SP::make_opcode(
                                                            insn,
                                                        ));
                                                    }
                                                }
                                            } else {
                                                if insn & 0xffe0fc00 == 0x9ac05c00 {
                                                    return Some(CRC32CX_Rd_Rn_Rm::make_opcode(
                                                        insn,
                                                    ));
                                                }
                                            }
                                        } else {
                                            if insn & 0xffffffe0 == 0xdac13fe0 {
                                                return Some(AUTDZB_Rd::make_opcode(insn));
                                            }
                                        }
                                    }
                                }
                            }
                        }
                    } else {
                        if insn & 0x20000000 == 0 {
                            if insn & 0x40000000 == 0 {
                                if insn & 0x7f200000 == 0xa200000 {
                                    return Some(BIC_Rd_Rn_Rm_SFT::make_opcode(insn));
                                }
                            } else {
                                if insn & 0x7f200000 == 0x4a200000 {
                                    return Some(EON_Rd_Rn_Rm_SFT::make_opcode(insn));
                                }
                            }
                        } else {
                            if insn & 0x40000000 == 0 {
                                if insn & 0x7f200000 == 0x2a200000 {
                                    return Some(ORN_Rd_Rn_Rm_SFT::make_opcode(insn));
                                }
                            } else {
                                if insn & 0x7f200000 == 0x6a200000 {
                                    return Some(BICS_Rd_Rn_Rm_SFT::make_opcode(insn));
                                }
                            }
                        }
                    }
                }
            } else {
                if insn & 0x8000000 == 0 {
                    if insn & 0x800000 == 0 {
                        if insn & 0x20000000 == 0 {
                            if insn & 0x40000000 == 0 {
                                if insn & 0x7f800000 == 0x13000000 {
                                    return Some(SBFM_Rd_Rn_IMMR_IMMS::make_opcode(insn));
                                }
                            } else {
                                if insn & 0x7f800000 == 0x53000000 {
                                    return Some(UBFM_Rd_Rn_IMMR_IMMS::make_opcode(insn));
                                }
                            }
                        } else {
                            if insn & 0x7f800000 == 0x33000000 {
                                return Some(BFM_Rd_Rn_IMMR_IMMS::make_opcode(insn));
                            }
                        }
                    } else {
                        if insn & 0x7fa00000 == 0x13800000 {
                            return Some(EXTR_Rd_Rn_Rm_IMMS::make_opcode(insn));
                        }
                    }
                } else {
                    if insn & 0x200000 == 0 {
                        if insn & 0x10000000 == 0 {
                            if insn & 0x20000000 == 0 {
                                if insn & 0x40000000 == 0 {
                                    if insn & 0x7f200000 == 0xb000000 {
                                        return Some(ADD_Rd_Rn_Rm_SFT::make_opcode(insn));
                                    }
                                } else {
                                    if insn & 0x7f200000 == 0x4b000000 {
                                        return Some(SUB_Rd_Rn_Rm_SFT::make_opcode(insn));
                                    }
                                }
                            } else {
                                if insn & 0x40000000 == 0 {
                                    if insn & 0x7f200000 == 0x2b000000 {
                                        return Some(ADDS_Rd_Rn_Rm_SFT::make_opcode(insn));
                                    }
                                } else {
                                    if insn & 0x7f200000 == 0x6b000000 {
                                        return Some(SUBS_Rd_Rn_Rm_SFT::make_opcode(insn));
                                    }
                                }
                            }
                        } else {
                            if insn & 0x008000 == 0 {
                                if insn & 0x400000 == 0 {
                                    if insn & 0x7fe08000 == 0x1b000000 {
                                        return Some(MADD_Rd_Rn_Rm_Ra::make_opcode(insn));
                                    }
                                } else {
                                    if insn & 0x800000 == 0 {
                                        if insn & 0xffe0fc00 == 0x9b407c00 {
                                            return Some(SMULH_Rd_Rn_Rm::make_opcode(insn));
                                        }
                                    } else {
                                        if insn & 0xffe0fc00 == 0x9bc07c00 {
                                            return Some(UMULH_Rd_Rn_Rm::make_opcode(insn));
                                        }
                                    }
                                }
                            } else {
                                if insn & 0x7fe08000 == 0x1b008000 {
                                    return Some(MSUB_Rd_Rn_Rm_Ra::make_opcode(insn));
                                }
                            }
                        }
                    } else {
                        if insn & 0x800000 == 0 {
                            if insn & 0x10000000 == 0 {
                                if insn & 0x20000000 == 0 {
                                    if insn & 0x40000000 == 0 {
                                        if insn & 0x7fe00000 == 0xb200000 {
                                            return Some(ADD_Rd_SP_Rn_SP_Rm_EXT::make_opcode(insn));
                                        }
                                    } else {
                                        if insn & 0x7fe00000 == 0x4b200000 {
                                            return Some(SUB_Rd_SP_Rn_SP_Rm_EXT::make_opcode(insn));
                                        }
                                    }
                                } else {
                                    if insn & 0x40000000 == 0 {
                                        if insn & 0x7fe00000 == 0x2b200000 {
                                            return Some(ADDS_Rd_Rn_SP_Rm_EXT::make_opcode(insn));
                                        }
                                    } else {
                                        if insn & 0x7fe00000 == 0x6b200000 {
                                            return Some(SUBS_Rd_Rn_SP_Rm_EXT::make_opcode(insn));
                                        }
                                    }
                                }
                            } else {
                                if insn & 0x008000 == 0 {
                                    if insn & 0xffe08000 == 0x9b200000 {
                                        return Some(SMADDL_Rd_Rn_Rm_Ra::make_opcode(insn));
                                    }
                                } else {
                                    if insn & 0xffe08000 == 0x9b208000 {
                                        return Some(SMSUBL_Rd_Rn_Rm_Ra::make_opcode(insn));
                                    }
                                }
                            }
                        } else {
                            if insn & 0x008000 == 0 {
                                if insn & 0xffe08000 == 0x9ba00000 {
                                    return Some(UMADDL_Rd_Rn_Rm_Ra::make_opcode(insn));
                                }
                            } else {
                                if insn & 0xffe08000 == 0x9ba08000 {
                                    return Some(UMSUBL_Rd_Rn_Rm_Ra::make_opcode(insn));
                                }
                            }
                        }
                    }
                }
            }
        }
    } else {
        if insn & 0x8000000 == 0 {
            if insn & 0x10000000 == 0 {
                if insn & 0x1000000 == 0 {
                    if insn & 0x20000000 == 0 {
                        if insn & 0x002000 == 0 {
                            if insn & 0x004000 == 0 {
                                if insn & 0x008000 == 0 {
                                    if insn & 0x200000 == 0 {
                                        if insn & 0x40000000 == 0 {
                                            if insn & 0x80000000 == 0 {
                                                if insn & 0x010000 == 0 {
                                                    if insn & 0x020000 == 0 {
                                                        if insn & 0x040000 == 0 {
                                                            if insn & 0x080000 == 0 {
                                                                if insn & 0x100000 == 0 {
                                                                    if insn & 0xff3fe000
                                                                        == 0x4000000
                                                                    {
                                                                        return Some (ADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xff3fe000
                                                                        == 0x4100000
                                                                    {
                                                                        return Some (MUL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0x100000 == 0 {
                                                                    if insn & 0xff3fe000
                                                                        == 0x4080000
                                                                    {
                                                                        return Some (SMAX_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xff3fe000
                                                                        == 0x4180000
                                                                    {
                                                                        return Some (ORR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x080000 == 0 {
                                                                if insn & 0xffbfe000 == 0x4940000 {
                                                                    return Some (SDIV_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xff3fe000 == 0x40c0000 {
                                                                    return Some (SABD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x040000 == 0 {
                                                            if insn & 0x080000 == 0 {
                                                                if insn & 0xff3fe000 == 0x4120000 {
                                                                    return Some (SMULH_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0x100000 == 0 {
                                                                    if insn & 0xff3fe000
                                                                        == 0x40a0000
                                                                    {
                                                                        return Some (SMIN_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xff3fe000
                                                                        == 0x41a0000
                                                                    {
                                                                        return Some (AND_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0xffbfe000 == 0x4960000 {
                                                                return Some (SDIVR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x020000 == 0 {
                                                        if insn & 0x040000 == 0 {
                                                            if insn & 0x080000 == 0 {
                                                                if insn & 0xff3fe000 == 0x4010000 {
                                                                    return Some (SUB_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0x100000 == 0 {
                                                                    if insn & 0xff3fe000
                                                                        == 0x4090000
                                                                    {
                                                                        return Some (UMAX_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xff3fe000
                                                                        == 0x4190000
                                                                    {
                                                                        return Some (EOR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x080000 == 0 {
                                                                if insn & 0xffbfe000 == 0x4950000 {
                                                                    return Some (UDIV_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xff3fe000 == 0x40d0000 {
                                                                    return Some (UABD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x040000 == 0 {
                                                            if insn & 0x080000 == 0 {
                                                                if insn & 0x100000 == 0 {
                                                                    if insn & 0xff3fe000
                                                                        == 0x4030000
                                                                    {
                                                                        return Some (SUBR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xff3fe000
                                                                        == 0x4130000
                                                                    {
                                                                        return Some (UMULH_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0x100000 == 0 {
                                                                    if insn & 0xff3fe000
                                                                        == 0x40b0000
                                                                    {
                                                                        return Some (UMIN_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xff3fe000
                                                                        == 0x41b0000
                                                                    {
                                                                        return Some (BIC_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0xffbfe000 == 0x4970000 {
                                                                return Some (UDIVR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0x800000 == 0 {
                                                    if insn & 0xffa0e000 == 0x84000000 {
                                                        return Some (LD1SB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22 :: make_opcode (insn)) ;
                                                    }
                                                } else {
                                                    if insn & 0xffa0e000 == 0x84800000 {
                                                        return Some (LD1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22 :: make_opcode (insn)) ;
                                                    }
                                                }
                                            }
                                        } else {
                                            if insn & 0x80000000 == 0 {
                                                if insn & 0x001000 == 0 {
                                                    if insn & 0x000400 == 0 {
                                                        if insn & 0x000800 == 0 {
                                                            if insn & 0xffa0fc00 == 0x44800000 {
                                                                return Some (SDOT_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xff20fc00 == 0x44000800 {
                                                                return Some (SQDMLALBT_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x000800 == 0 {
                                                            if insn & 0xffa0fc00 == 0x44800400 {
                                                                return Some (UDOT_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xff20fc00 == 0x44000c00 {
                                                                return Some (SQDMLSLBT_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0xffa0f000 == 0x44801000 {
                                                        return Some (CDOT_SVE_Zd_SVE_Zn_SVE_Zm_16_SVE_IMM_ROT2 :: make_opcode (insn)) ;
                                                    }
                                                }
                                            } else {
                                                if insn & 0x800000 == 0 {
                                                    if insn & 0xffa0e000 == 0xc4000000 {
                                                        return Some (LD1SB_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW_22_S_D :: make_opcode (insn)) ;
                                                    }
                                                } else {
                                                    if insn & 0xffa0e000 == 0xc4800000 {
                                                        return Some (LD1SH_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW_22_S_D :: make_opcode (insn)) ;
                                                    }
                                                }
                                            }
                                        }
                                    } else {
                                        if insn & 0x40000000 == 0 {
                                            if insn & 0x80000000 == 0 {
                                                if insn & 0x000400 == 0 {
                                                    if insn & 0x000800 == 0 {
                                                        if insn & 0x001000 == 0 {
                                                            if insn & 0xff20fc00 == 0x4200000 {
                                                                return Some (ADD_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xff20fc00 == 0x4201000 {
                                                                return Some (SQADD_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0xff20fc00 == 0x4201800 {
                                                            return Some (SQSUB_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x000800 == 0 {
                                                        if insn & 0x001000 == 0 {
                                                            if insn & 0xff20fc00 == 0x4200400 {
                                                                return Some (SUB_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xff20fc00 == 0x4201400 {
                                                                return Some (UQADD_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0xff20fc00 == 0x4201c00 {
                                                            return Some (UQSUB_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0x800000 == 0 {
                                                    if insn & 0xffa0e010 == 0x84200000 {
                                                        return Some (PRFB_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RZ_XTW_22 :: make_opcode (insn)) ;
                                                    }
                                                } else {
                                                    if insn & 0xffa0e000 == 0x84a00000 {
                                                        return Some (LD1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW1_22 :: make_opcode (insn)) ;
                                                    }
                                                }
                                            }
                                        } else {
                                            if insn & 0x800000 == 0 {
                                                if insn & 0x80000000 == 0 {
                                                    if insn & 0x000400 == 0 {
                                                        if insn & 0x000800 == 0 {
                                                            if insn & 0xffa0fc00 == 0x44201000 {
                                                                return Some (SQRDMLAH_SVE_Zd_SVE_Zn_SVE_Zm3_22_INDEX :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xffa0fc00 == 0x44200800 {
                                                                return Some (MLA_SVE_Zd_SVE_Zn_SVE_Zm3_22_INDEX :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x000800 == 0 {
                                                            if insn & 0xffa0fc00 == 0x44201400 {
                                                                return Some (SQRDMLSH_SVE_Zd_SVE_Zn_SVE_Zm3_22_INDEX :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xffa0fc00 == 0x44200c00 {
                                                                return Some (MLS_SVE_Zd_SVE_Zn_SVE_Zm3_22_INDEX :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0xffa0e010 == 0xc4200000 {
                                                        return Some (PRFB_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RZ_XTW_22_c4200000 :: make_opcode (insn)) ;
                                                    }
                                                }
                                            } else {
                                                if insn & 0x80000000 == 0 {
                                                    if insn & 0x000400 == 0 {
                                                        if insn & 0x000800 == 0 {
                                                            if insn & 0x001000 == 0 {
                                                                if insn & 0x400000 == 0 {
                                                                    if insn & 0xffe0fc00
                                                                        == 0x44a00000
                                                                    {
                                                                        return Some (SDOT_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xffe0fc00
                                                                        == 0x44e00000
                                                                    {
                                                                        return Some (SDOT_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0x400000 == 0 {
                                                                    if insn & 0xffe0fc00
                                                                        == 0x44a01000
                                                                    {
                                                                        return Some (SQRDMLAH_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xffe0fc00
                                                                        == 0x44e01000
                                                                    {
                                                                        return Some (SQRDMLAH_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x001000 == 0 {
                                                                if insn & 0x400000 == 0 {
                                                                    if insn & 0xffe0fc00
                                                                        == 0x44a00800
                                                                    {
                                                                        return Some (MLA_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xffe0fc00
                                                                        == 0x44e00800
                                                                    {
                                                                        return Some (MLA_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0xffe0fc00 == 0x44a01800 {
                                                                    return Some (USDOT_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x000800 == 0 {
                                                            if insn & 0x001000 == 0 {
                                                                if insn & 0x400000 == 0 {
                                                                    if insn & 0xffe0fc00
                                                                        == 0x44a00400
                                                                    {
                                                                        return Some (UDOT_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xffe0fc00
                                                                        == 0x44e00400
                                                                    {
                                                                        return Some (UDOT_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0x400000 == 0 {
                                                                    if insn & 0xffe0fc00
                                                                        == 0x44a01400
                                                                    {
                                                                        return Some (SQRDMLSH_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xffe0fc00
                                                                        == 0x44e01400
                                                                    {
                                                                        return Some (SQRDMLSH_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x001000 == 0 {
                                                                if insn & 0x400000 == 0 {
                                                                    if insn & 0xffe0fc00
                                                                        == 0x44a00c00
                                                                    {
                                                                        return Some (MLS_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xffe0fc00
                                                                        == 0x44e00c00
                                                                    {
                                                                        return Some (MLS_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0xffe0fc00 == 0x44a01c00 {
                                                                    return Some (SUDOT_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0xffa0e000 == 0xc4a00000 {
                                                        return Some (LD1SH_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW1_22_S_D :: make_opcode (insn)) ;
                                                    }
                                                }
                                            }
                                        }
                                    }
                                } else {
                                    if insn & 0x80000000 == 0 {
                                        if insn & 0x200000 == 0 {
                                            if insn & 0x010000 == 0 {
                                                if insn & 0x020000 == 0 {
                                                    if insn & 0x040000 == 0 {
                                                        if insn & 0x080000 == 0 {
                                                            if insn & 0x100000 == 0 {
                                                                if insn & 0xff3fe000 == 0x4008000 {
                                                                    return Some (ASR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_SHRIMM_PRED :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0x40000000 == 0 {
                                                                    if insn & 0xff3fe000
                                                                        == 0x4108000
                                                                    {
                                                                        return Some (ASR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xff3fe000
                                                                        == 0x44108000
                                                                    {
                                                                        return Some (SHADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x100000 == 0 {
                                                                if insn & 0xff3fe000 == 0x44088000 {
                                                                    return Some (SQSHL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0x40000000 == 0 {
                                                                    if insn & 0xff3fe000
                                                                        == 0x4188000
                                                                    {
                                                                        return Some (ASR_SVE_Zd_S_B_SVE_Pg3_P_M_SVE_Zd_S_B_SVE_Zm_5_S_D :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xff3fe000
                                                                        == 0x44188000
                                                                    {
                                                                        return Some (SQADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x080000 == 0 {
                                                            if insn & 0x100000 == 0 {
                                                                if insn & 0xff3fe000 == 0x4048000 {
                                                                    return Some (ASRD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_SHRIMM_PRED :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0x40000000 == 0 {
                                                                    if insn & 0xff3fe000
                                                                        == 0x4148000
                                                                    {
                                                                        return Some (ASRR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xff3fe000
                                                                        == 0x44148000
                                                                    {
                                                                        return Some (SRHADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x100000 == 0 {
                                                                if insn & 0x40000000 == 0 {
                                                                    if insn & 0xff3fe000
                                                                        == 0x40c8000
                                                                    {
                                                                        return Some (SRSHR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_SHRIMM_PRED :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xff3fe000
                                                                        == 0x440c8000
                                                                    {
                                                                        return Some (SQSHLR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0xff3fe000 == 0x441c8000 {
                                                                    return Some (SUQADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x040000 == 0 {
                                                        if insn & 0x080000 == 0 {
                                                            if insn & 0x100000 == 0 {
                                                                if insn & 0xff3fe000 == 0x44028000 {
                                                                    return Some (SRSHL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xff3fe000 == 0x44128000 {
                                                                    return Some (SHSUB_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x100000 == 0 {
                                                                if insn & 0xff3fe000 == 0x440a8000 {
                                                                    return Some (SQRSHL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xff3fe000 == 0x441a8000 {
                                                                    return Some (SQSUB_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x080000 == 0 {
                                                            if insn & 0x100000 == 0 {
                                                                if insn & 0x40000000 == 0 {
                                                                    if insn & 0xff3fe000
                                                                        == 0x4068000
                                                                    {
                                                                        return Some (SQSHL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_SHLIMM_PRED :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xff3fe000
                                                                        == 0x44068000
                                                                    {
                                                                        return Some (SRSHLR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0xff3fe000 == 0x44168000 {
                                                                    return Some (SHSUBR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x100000 == 0 {
                                                                if insn & 0xff3fe000 == 0x440e8000 {
                                                                    return Some (SQRSHLR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xff3fe000 == 0x441e8000 {
                                                                    return Some (SQSUBR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0x020000 == 0 {
                                                    if insn & 0x040000 == 0 {
                                                        if insn & 0x080000 == 0 {
                                                            if insn & 0x100000 == 0 {
                                                                if insn & 0xff3fe000 == 0x4018000 {
                                                                    return Some (LSR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_SHRIMM_PRED :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0x40000000 == 0 {
                                                                    if insn & 0xff3fe000
                                                                        == 0x4118000
                                                                    {
                                                                        return Some (LSR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xff3fe000
                                                                        == 0x44118000
                                                                    {
                                                                        return Some (UHADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x100000 == 0 {
                                                                if insn & 0xff3fe000 == 0x44098000 {
                                                                    return Some (UQSHL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0x40000000 == 0 {
                                                                    if insn & 0xff3fe000
                                                                        == 0x4198000
                                                                    {
                                                                        return Some (LSR_SVE_Zd_S_B_SVE_Pg3_P_M_SVE_Zd_S_B_SVE_Zm_5_S_D :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xff3fe000
                                                                        == 0x44198000
                                                                    {
                                                                        return Some (UQADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x080000 == 0 {
                                                            if insn & 0x40000000 == 0 {
                                                                if insn & 0xff3fe000 == 0x4158000 {
                                                                    return Some (LSRR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xff3fe000 == 0x44158000 {
                                                                    return Some (URHADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x100000 == 0 {
                                                                if insn & 0x40000000 == 0 {
                                                                    if insn & 0xff3fe000
                                                                        == 0x40d8000
                                                                    {
                                                                        return Some (URSHR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_SHRIMM_PRED :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xff3fe000
                                                                        == 0x440d8000
                                                                    {
                                                                        return Some (UQSHLR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0xff3fe000 == 0x441d8000 {
                                                                    return Some (USQADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x040000 == 0 {
                                                        if insn & 0x080000 == 0 {
                                                            if insn & 0x100000 == 0 {
                                                                if insn & 0x40000000 == 0 {
                                                                    if insn & 0xff3fe000
                                                                        == 0x4038000
                                                                    {
                                                                        return Some (LSL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_SHLIMM_PRED :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xff3fe000
                                                                        == 0x44038000
                                                                    {
                                                                        return Some (URSHL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0x40000000 == 0 {
                                                                    if insn & 0xff3fe000
                                                                        == 0x4138000
                                                                    {
                                                                        return Some (LSL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xff3fe000
                                                                        == 0x44138000
                                                                    {
                                                                        return Some (UHSUB_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x100000 == 0 {
                                                                if insn & 0xff3fe000 == 0x440b8000 {
                                                                    return Some (UQRSHL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0x40000000 == 0 {
                                                                    if insn & 0xff3fe000
                                                                        == 0x41b8000
                                                                    {
                                                                        return Some (LSL_SVE_Zd_S_B_SVE_Pg3_P_M_SVE_Zd_S_B_SVE_Zm_5_S_D :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xff3fe000
                                                                        == 0x441b8000
                                                                    {
                                                                        return Some (UQSUB_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x080000 == 0 {
                                                            if insn & 0x100000 == 0 {
                                                                if insn & 0x40000000 == 0 {
                                                                    if insn & 0xff3fe000
                                                                        == 0x4078000
                                                                    {
                                                                        return Some (UQSHL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_SHLIMM_PRED :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xff3fe000
                                                                        == 0x44078000
                                                                    {
                                                                        return Some (URSHLR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0x40000000 == 0 {
                                                                    if insn & 0xff3fe000
                                                                        == 0x4178000
                                                                    {
                                                                        return Some (LSLR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xff3fe000
                                                                        == 0x44178000
                                                                    {
                                                                        return Some (UHSUBR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x100000 == 0 {
                                                                if insn & 0x40000000 == 0 {
                                                                    if insn & 0xff3fe000
                                                                        == 0x40f8000
                                                                    {
                                                                        return Some (SQSHLU_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_SHLIMM_PRED :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xff3fe000
                                                                        == 0x440f8000
                                                                    {
                                                                        return Some (UQRSHLR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0xff3fe000 == 0x441f8000 {
                                                                    return Some (UQSUBR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        }
                                                    }
                                                }
                                            }
                                        } else {
                                            if insn & 0x000400 == 0 {
                                                if insn & 0x001000 == 0 {
                                                    if insn & 0x40000000 == 0 {
                                                        if insn & 0xff20fc00 == 0x4208000 {
                                                            return Some (ASR_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0x400000 == 0 {
                                                            if insn & 0xffe0f400 == 0x44a08000 {
                                                                return Some (SMLALB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xffe0f400 == 0x44e08000 {
                                                                return Some (SMLALB_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x40000000 == 0 {
                                                        if insn & 0xff20fc00 == 0x4209000 {
                                                            return Some (ASR_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0x400000 == 0 {
                                                            if insn & 0xffe0f400 == 0x44a09000 {
                                                                return Some (UMLALB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xffe0f400 == 0x44e09000 {
                                                                return Some (UMLALB_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0x001000 == 0 {
                                                    if insn & 0x40000000 == 0 {
                                                        if insn & 0x000800 == 0 {
                                                            if insn & 0xff20fc00 == 0x4208400 {
                                                                return Some (LSR_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xff20fc00 == 0x4208c00 {
                                                                return Some (LSL_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x400000 == 0 {
                                                            if insn & 0xffe0f400 == 0x44a08400 {
                                                                return Some (SMLALT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xffe0f400 == 0x44e08400 {
                                                                return Some (SMLALT_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x40000000 == 0 {
                                                        if insn & 0x000800 == 0 {
                                                            if insn & 0xff20fc00 == 0x4209400 {
                                                                return Some (LSR_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xff20fc00 == 0x4209c00 {
                                                                return Some (LSL_SVE_Zd_SVE_Zn_SVE_SHLIMM_UNPRED :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x400000 == 0 {
                                                            if insn & 0xffe0f400 == 0x44a09400 {
                                                                return Some (UMLALT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xffe0f400 == 0x44e09400 {
                                                                return Some (UMLALT_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    }
                                                }
                                            }
                                        }
                                    } else {
                                        if insn & 0x400000 == 0 {
                                            if insn & 0x200000 == 0 {
                                                if insn & 0x800000 == 0 {
                                                    if insn & 0xbfe0e000 == 0x84008000 {
                                                        return Some (LDNT1SB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZX :: make_opcode (insn)) ;
                                                    }
                                                } else {
                                                    if insn & 0xbfe0e000 == 0x84808000 {
                                                        return Some (LDNT1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZX :: make_opcode (insn)) ;
                                                    }
                                                }
                                            } else {
                                                if insn & 0x800000 == 0 {
                                                    if insn & 0x40000000 == 0 {
                                                        if insn & 0xffe0e000 == 0x84208000 {
                                                            return Some (LD1SB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5 :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xffe0e000 == 0xc4208000 {
                                                            return Some (LD1SB_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_ZI_U5_S_D :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x40000000 == 0 {
                                                        if insn & 0xffe0e000 == 0x84a08000 {
                                                            return Some (LD1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x2 :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xffe0e000 == 0xc4a08000 {
                                                            return Some (LD1SH_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_ZI_U5x2_S_D :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                }
                                            }
                                        } else {
                                            if insn & 0x800000 == 0 {
                                                if insn & 0x40000000 == 0 {
                                                    if insn & 0xffc0e000 == 0x84408000 {
                                                        return Some (LD1RB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_U6 :: make_opcode (insn)) ;
                                                    }
                                                } else {
                                                    if insn & 0x200000 == 0 {
                                                        if insn & 0xffe0e000 == 0xc4408000 {
                                                            return Some (LD1SB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xffe0e010 == 0xc4608000 {
                                                            return Some (PRFB_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RZ :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0x40000000 == 0 {
                                                    if insn & 0xffc0e000 == 0x84c08000 {
                                                        return Some (LD1RSW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_U6x4 :: make_opcode (insn)) ;
                                                    }
                                                } else {
                                                    if insn & 0x200000 == 0 {
                                                        if insn & 0xffe0e000 == 0xc4c08000 {
                                                            return Some (LD1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xffe0e000 == 0xc4e08000 {
                                                            return Some (LD1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL1 :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                }
                                            }
                                        }
                                    }
                                }
                            } else {
                                if insn & 0x008000 == 0 {
                                    if insn & 0x200000 == 0 {
                                        if insn & 0x40000000 == 0 {
                                            if insn & 0x80000000 == 0 {
                                                if insn & 0xff20e000 == 0x4004000 {
                                                    return Some (MLA_SVE_Zd_SVE_Pg3_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                }
                                            } else {
                                                if insn & 0x800000 == 0 {
                                                    if insn & 0xffa0e000 == 0x84004000 {
                                                        return Some (LD1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22 :: make_opcode (insn)) ;
                                                    }
                                                } else {
                                                    if insn & 0xffa0e000 == 0x84804000 {
                                                        return Some (LD1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22 :: make_opcode (insn)) ;
                                                    }
                                                }
                                            }
                                        } else {
                                            if insn & 0x80000000 == 0 {
                                                if insn & 0x000400 == 0 {
                                                    if insn & 0x000800 == 0 {
                                                        if insn & 0x001000 == 0 {
                                                            if insn & 0xff20fc00 == 0x44004000 {
                                                                return Some (SMLALB_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xff20fc00 == 0x44005000 {
                                                                return Some (SMLSLB_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x001000 == 0 {
                                                            if insn & 0xff20fc00 == 0x44004800 {
                                                                return Some (UMLALB_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xff20fc00 == 0x44005800 {
                                                                return Some (UMLSLB_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x000800 == 0 {
                                                        if insn & 0x001000 == 0 {
                                                            if insn & 0xff20fc00 == 0x44004400 {
                                                                return Some (SMLALT_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xff20fc00 == 0x44005400 {
                                                                return Some (SMLSLT_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x001000 == 0 {
                                                            if insn & 0xff20fc00 == 0x44004c00 {
                                                                return Some (UMLALT_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xff20fc00 == 0x44005c00 {
                                                                return Some (UMLSLT_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0x800000 == 0 {
                                                    if insn & 0xffa0e000 == 0xc4004000 {
                                                        return Some (LD1B_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW_22_S_D :: make_opcode (insn)) ;
                                                    }
                                                } else {
                                                    if insn & 0xffa0e000 == 0xc4804000 {
                                                        return Some (LD1H_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW_22_S_D :: make_opcode (insn)) ;
                                                    }
                                                }
                                            }
                                        }
                                    } else {
                                        if insn & 0x40000000 == 0 {
                                            if insn & 0x80000000 == 0 {
                                                if insn & 0x000800 == 0 {
                                                    if insn & 0x001000 == 0 {
                                                        if insn & 0x000400 == 0 {
                                                            if insn & 0xff20fc00 == 0x4204000 {
                                                                return Some (INDEX_SVE_Zd_SVE_SIMM5_SVE_SIMM5B :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xff20fc00 == 0x4204400 {
                                                                return Some (INDEX_SVE_Zd_Rn_SIMM5 :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x400000 == 0 {
                                                            if insn & 0x800000 == 0 {
                                                                if insn & 0xffe0f800 == 0x4205000 {
                                                                    return Some (ADDVL_Rd_SP_SVE_Rn_SP_SVE_SIMM6 :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xfffff800 == 0x4bf5000 {
                                                                    return Some (RDVL_Rd_SVE_SIMM6 :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0xffe0f800 == 0x4605000 {
                                                                return Some (ADDPL_Rd_SP_SVE_Rn_SP_SVE_SIMM6 :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x001000 == 0 {
                                                        if insn & 0x000400 == 0 {
                                                            if insn & 0xff20fc00 == 0x4204800 {
                                                                return Some (INDEX_SVE_Zd_SVE_SIMM5_Rm :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xff20fc00 == 0x4204c00 {
                                                                return Some(
                                                                    INDEX_SVE_Zd_Rn_Rm::make_opcode(
                                                                        insn,
                                                                    ),
                                                                );
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x400000 == 0 {
                                                            if insn & 0x800000 == 0 {
                                                                if insn & 0xffe0f800 == 0x4205800 {
                                                                    return Some (ADDSVL_Rd_SP_SVE_Rn_SP_SVE_SIMM6 :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xfffff800 == 0x4bf5800 {
                                                                    return Some (RDSVL_Rd_SVE_SIMM6 :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0xffe0f800 == 0x4605800 {
                                                                return Some (ADDSPL_Rd_SP_SVE_Rn_SP_SVE_SIMM6 :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0x800000 == 0 {
                                                    if insn & 0xffa0e010 == 0x84204000 {
                                                        return Some (PRFW_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RZ_XTW2_22 :: make_opcode (insn)) ;
                                                    }
                                                } else {
                                                    if insn & 0xffa0e000 == 0x84a04000 {
                                                        return Some (LD1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW1_22 :: make_opcode (insn)) ;
                                                    }
                                                }
                                            }
                                        } else {
                                            if insn & 0x800000 == 0 {
                                                if insn & 0xffa0e010 == 0xc4204000 {
                                                    return Some (PRFW_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RZ_XTW2_22_c4204000 :: make_opcode (insn)) ;
                                                }
                                            } else {
                                                if insn & 0x80000000 == 0 {
                                                    if insn & 0x400000 == 0 {
                                                        if insn & 0xffe0f000 == 0x44a04000 {
                                                            return Some (CDOT_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX_SVE_IMM_ROT2 :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xffe0f000 == 0x44e04000 {
                                                            return Some (CDOT_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX_SVE_IMM_ROT2 :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0xffa0e000 == 0xc4a04000 {
                                                        return Some (LD1H_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW1_22_S_D :: make_opcode (insn)) ;
                                                    }
                                                }
                                            }
                                        }
                                    }
                                } else {
                                    if insn & 0x40000000 == 0 {
                                        if insn & 0x80000000 == 0 {
                                            if insn & 0x200000 == 0 {
                                                if insn & 0xff20e000 == 0x400c000 {
                                                    return Some (MAD_SVE_Zd_SVE_Pg3_SVE_Zm_16_SVE_Za_5 :: make_opcode (insn)) ;
                                                }
                                            } else {
                                                if insn & 0x000400 == 0 {
                                                    if insn & 0x000800 == 0 {
                                                        if insn & 0x100000 == 0 {
                                                            if insn & 0x400000 == 0 {
                                                                if insn & 0xfff0fc00 == 0x4a0c000 {
                                                                    return Some (SQINCW_SVE_Zd_SVE_PATTERN_SCALED :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0x800000 == 0 {
                                                                    if insn & 0xfff0fc00
                                                                        == 0x460c000
                                                                    {
                                                                        return Some (SQINCH_SVE_Zd_SVE_PATTERN_SCALED :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xfff0fc00
                                                                        == 0x4e0c000
                                                                    {
                                                                        return Some (SQINCD_SVE_Zd_SVE_PATTERN_SCALED :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x400000 == 0 {
                                                                if insn & 0xfff0fc00 == 0x4b0c000 {
                                                                    return Some (INCW_SVE_Zd_SVE_PATTERN_SCALED :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0x800000 == 0 {
                                                                    if insn & 0xfff0fc00
                                                                        == 0x470c000
                                                                    {
                                                                        return Some (INCH_SVE_Zd_SVE_PATTERN_SCALED :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xfff0fc00
                                                                        == 0x4f0c000
                                                                    {
                                                                        return Some (INCD_SVE_Zd_SVE_PATTERN_SCALED :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x400000 == 0 {
                                                            if insn & 0xfff0fc00 == 0x4a0c800 {
                                                                return Some (SQDECW_SVE_Zd_SVE_PATTERN_SCALED :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0x800000 == 0 {
                                                                if insn & 0xfff0fc00 == 0x460c800 {
                                                                    return Some (SQDECH_SVE_Zd_SVE_PATTERN_SCALED :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xfff0fc00 == 0x4e0c800 {
                                                                    return Some (SQDECD_SVE_Zd_SVE_PATTERN_SCALED :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x000800 == 0 {
                                                        if insn & 0x100000 == 0 {
                                                            if insn & 0x400000 == 0 {
                                                                if insn & 0xfff0fc00 == 0x4a0c400 {
                                                                    return Some (UQINCW_SVE_Zd_SVE_PATTERN_SCALED :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0x800000 == 0 {
                                                                    if insn & 0xfff0fc00
                                                                        == 0x460c400
                                                                    {
                                                                        return Some (UQINCH_SVE_Zd_SVE_PATTERN_SCALED :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xfff0fc00
                                                                        == 0x4e0c400
                                                                    {
                                                                        return Some (UQINCD_SVE_Zd_SVE_PATTERN_SCALED :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x400000 == 0 {
                                                                if insn & 0xfff0fc00 == 0x4b0c400 {
                                                                    return Some (DECW_SVE_Zd_SVE_PATTERN_SCALED :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0x800000 == 0 {
                                                                    if insn & 0xfff0fc00
                                                                        == 0x470c400
                                                                    {
                                                                        return Some (DECH_SVE_Zd_SVE_PATTERN_SCALED :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xfff0fc00
                                                                        == 0x4f0c400
                                                                    {
                                                                        return Some (DECD_SVE_Zd_SVE_PATTERN_SCALED :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x400000 == 0 {
                                                            if insn & 0xfff0fc00 == 0x4a0cc00 {
                                                                return Some (UQDECW_SVE_Zd_SVE_PATTERN_SCALED :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0x800000 == 0 {
                                                                if insn & 0xfff0fc00 == 0x460cc00 {
                                                                    return Some (UQDECH_SVE_Zd_SVE_PATTERN_SCALED :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xfff0fc00 == 0x4e0cc00 {
                                                                    return Some (UQDECD_SVE_Zd_SVE_PATTERN_SCALED :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        }
                                                    }
                                                }
                                            }
                                        } else {
                                            if insn & 0x400000 == 0 {
                                                if insn & 0x200000 == 0 {
                                                    if insn & 0x800000 == 0 {
                                                        if insn & 0xffe0e010 == 0x8400c000 {
                                                            return Some (PRFB_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RX :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xffe0e010 == 0x8480c000 {
                                                            return Some (PRFH_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RX_LSL1 :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x800000 == 0 {
                                                        if insn & 0xffe0e000 == 0x8420c000 {
                                                            return Some (LD1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5 :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xffe0e000 == 0x84a0c000 {
                                                            return Some (LD1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x2 :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0x800000 == 0 {
                                                    if insn & 0xffc0e000 == 0x8440c000 {
                                                        return Some (LD1RB_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RI_U6 :: make_opcode (insn)) ;
                                                    }
                                                } else {
                                                    if insn & 0xffc0e000 == 0x84c0c000 {
                                                        return Some (LD1RH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_U6x2 :: make_opcode (insn)) ;
                                                    }
                                                }
                                            }
                                        }
                                    } else {
                                        if insn & 0x200000 == 0 {
                                            if insn & 0x80000000 == 0 {
                                                if insn & 0x000400 == 0 {
                                                    if insn & 0x000800 == 0 {
                                                        if insn & 0xff20fc00 == 0x4400c000 {
                                                            return Some (SCLAMP_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0x800000 == 0 {
                                                            if insn & 0xffe0fc00 == 0x4400c800 {
                                                                return Some (SDOT_SVE_Zd_S_S_SVE_Zn_S_H_SVE_Zm_16_S_H :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xffe0fc00 == 0x4480c800 {
                                                                return Some (SDOT_SVE_Zd_SVE_Zn_SVE_Zm3_19_INDEX :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x000800 == 0 {
                                                        if insn & 0xff20fc00 == 0x4400c400 {
                                                            return Some (UCLAMP_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0x800000 == 0 {
                                                            if insn & 0xffe0fc00 == 0x4400cc00 {
                                                                return Some (UDOT_SVE_Zd_S_S_SVE_Zn_S_H_SVE_Zm_16_S_H :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xffe0fc00 == 0x4480cc00 {
                                                                return Some (UDOT_SVE_Zd_SVE_Zn_SVE_Zm3_19_INDEX :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0x400000 == 0 {
                                                    if insn & 0x800000 == 0 {
                                                        if insn & 0xffe0e000 == 0xc400c000 {
                                                            return Some (LDNT1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZX :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xffe0e000 == 0xc480c000 {
                                                            return Some (LDNT1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZX :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x800000 == 0 {
                                                        if insn & 0xffe0e000 == 0xc440c000 {
                                                            return Some (LD1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xffe0e000 == 0xc4c0c000 {
                                                            return Some (LD1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                }
                                            }
                                        } else {
                                            if insn & 0x400000 == 0 {
                                                if insn & 0x800000 == 0 {
                                                    if insn & 0xffe0e000 == 0xc420c000 {
                                                        return Some (LD1B_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_ZI_U5_S_D :: make_opcode (insn)) ;
                                                    }
                                                } else {
                                                    if insn & 0x80000000 == 0 {
                                                        if insn & 0x000400 == 0 {
                                                            if insn & 0x001000 == 0 {
                                                                if insn & 0xffe0f400 == 0x44a0c000 {
                                                                    return Some (SMULLB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xffe0f400 == 0x44a0d000 {
                                                                    return Some (UMULLB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x001000 == 0 {
                                                                if insn & 0xffe0f400 == 0x44a0c400 {
                                                                    return Some (SMULLT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xffe0f400 == 0x44a0d400 {
                                                                    return Some (UMULLT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0xffe0e000 == 0xc4a0c000 {
                                                            return Some (LD1H_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_ZI_U5x2_S_D :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0x800000 == 0 {
                                                    if insn & 0xffe0e010 == 0xc460c000 {
                                                        return Some (PRFW_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RZ_LSL2 :: make_opcode (insn)) ;
                                                    }
                                                } else {
                                                    if insn & 0x80000000 == 0 {
                                                        if insn & 0x000400 == 0 {
                                                            if insn & 0x001000 == 0 {
                                                                if insn & 0xffe0f400 == 0x44e0c000 {
                                                                    return Some (SMULLB_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xffe0f400 == 0x44e0d000 {
                                                                    return Some (UMULLB_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x001000 == 0 {
                                                                if insn & 0xffe0f400 == 0x44e0c400 {
                                                                    return Some (SMULLT_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xffe0f400 == 0x44e0d400 {
                                                                    return Some (UMULLT_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0xffe0e000 == 0xc4e0c000 {
                                                            return Some (LD1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL1 :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                }
                                            }
                                        }
                                    }
                                }
                            }
                        } else {
                            if insn & 0x004000 == 0 {
                                if insn & 0x008000 == 0 {
                                    if insn & 0x200000 == 0 {
                                        if insn & 0x40000000 == 0 {
                                            if insn & 0x80000000 == 0 {
                                                if insn & 0x020000 == 0 {
                                                    if insn & 0x040000 == 0 {
                                                        if insn & 0x080000 == 0 {
                                                            if insn & 0x100000 == 0 {
                                                                if insn & 0x010000 == 0 {
                                                                    if insn & 0xff3fe000
                                                                        == 0x4002000
                                                                    {
                                                                        return Some (SADDV_SVE_Vd_SVE_Pg3_SVE_Zn :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xff3fe000
                                                                        == 0x4012000
                                                                    {
                                                                        return Some (UADDV_SVE_Vd_SVE_Pg3_SVE_Zn :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0xff3ee000 == 0x4102000 {
                                                                    return Some (MOVPRFX_SVE_Zd_SVE_Pg3_SVE_Zn :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x010000 == 0 {
                                                                if insn & 0x100000 == 0 {
                                                                    if insn & 0xff3fe000
                                                                        == 0x4082000
                                                                    {
                                                                        return Some (SMAXV_SVE_Vd_SVE_Pg3_SVE_Zn :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xff3fe000
                                                                        == 0x4182000
                                                                    {
                                                                        return Some (ORV_SVE_Vd_SVE_Pg3_SVE_Zn :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0x100000 == 0 {
                                                                    if insn & 0xff3fe000
                                                                        == 0x4092000
                                                                    {
                                                                        return Some (UMAXV_SVE_Vd_SVE_Pg3_SVE_Zn :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xff3fe000
                                                                        == 0x4192000
                                                                    {
                                                                        return Some (EORV_SVE_Vd_SVE_Pg3_SVE_Zn :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x010000 == 0 {
                                                            if insn & 0xff3fe000 == 0x40c2000 {
                                                                return Some (SMAXQV_Vd_SVE_Pg3_SVE_Zn :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0x080000 == 0 {
                                                                if insn & 0xff3fe000 == 0x4052000 {
                                                                    return Some (ADDQV_Vd_SVE_Pg3_SVE_Zn :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0x100000 == 0 {
                                                                    if insn & 0xff3fe000
                                                                        == 0x40d2000
                                                                    {
                                                                        return Some (UMAXQV_Vd_SVE_Pg3_SVE_Zn :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xff3fe000
                                                                        == 0x41d2000
                                                                    {
                                                                        return Some (EORQV_Vd_SVE_Pg3_SVE_Zn :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            }
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x010000 == 0 {
                                                        if insn & 0x040000 == 0 {
                                                            if insn & 0x100000 == 0 {
                                                                if insn & 0xff3fe000 == 0x40a2000 {
                                                                    return Some (SMINV_SVE_Vd_SVE_Pg3_SVE_Zn :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xff3fe000 == 0x41a2000 {
                                                                    return Some (ANDV_SVE_Vd_SVE_Pg3_SVE_Zn :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x100000 == 0 {
                                                                if insn & 0xff3fe000 == 0x40e2000 {
                                                                    return Some (SMINQV_Vd_SVE_Pg3_SVE_Zn :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xff3fe000 == 0x41e2000 {
                                                                    return Some (ANDQV_Vd_SVE_Pg3_SVE_Zn :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x040000 == 0 {
                                                            if insn & 0xff3fe000 == 0x40b2000 {
                                                                return Some (UMINV_SVE_Vd_SVE_Pg3_SVE_Zn :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xff3fe000 == 0x40f2000 {
                                                                return Some (UMINQV_Vd_SVE_Pg3_SVE_Zn :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0x800000 == 0 {
                                                    if insn & 0xffa0e000 == 0x84002000 {
                                                        return Some (LDFF1SB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22 :: make_opcode (insn)) ;
                                                    }
                                                } else {
                                                    if insn & 0xffa0e000 == 0x84802000 {
                                                        return Some (LDFF1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22 :: make_opcode (insn)) ;
                                                    }
                                                }
                                            }
                                        } else {
                                            if insn & 0x80000000 == 0 {
                                                if insn & 0x001000 == 0 {
                                                    if insn & 0xff20f000 == 0x44002000 {
                                                        return Some (CMLA_SVE_Zd_SVE_Zn_SVE_Zm_16_SVE_IMM_ROT2 :: make_opcode (insn)) ;
                                                    }
                                                } else {
                                                    if insn & 0xff20f000 == 0x44003000 {
                                                        return Some (SQRDCMLAH_SVE_Zd_SVE_Zn_SVE_Zm_16_SVE_IMM_ROT2 :: make_opcode (insn)) ;
                                                    }
                                                }
                                            } else {
                                                if insn & 0x800000 == 0 {
                                                    if insn & 0xffa0e000 == 0xc4002000 {
                                                        return Some (LDFF1SB_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW_22_S_D :: make_opcode (insn)) ;
                                                    }
                                                } else {
                                                    if insn & 0xffa0e000 == 0xc4802000 {
                                                        return Some (LDFF1SH_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW_22_S_D :: make_opcode (insn)) ;
                                                    }
                                                }
                                            }
                                        }
                                    } else {
                                        if insn & 0x40000000 == 0 {
                                            if insn & 0x80000000 == 0 {
                                                if insn & 0x000400 == 0 {
                                                    if insn & 0x000800 == 0 {
                                                        if insn & 0x400000 == 0 {
                                                            if insn & 0x800000 == 0 {
                                                                if insn & 0xffe0fc00 == 0x4203000 {
                                                                    return Some (AND_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xffe0fc00 == 0x4a03000 {
                                                                    return Some (EOR_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x800000 == 0 {
                                                                if insn & 0xffe0fc00 == 0x4603000 {
                                                                    return Some (ORR_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xffe0fc00 == 0x4e03000 {
                                                                    return Some (BIC_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x400000 == 0 {
                                                            if insn & 0xffe0fc00 == 0x4203800 {
                                                                return Some (EOR3_SVE_Zd_SVE_Zd_SVE_Zm_16_SVE_Zn :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xffe0fc00 == 0x4603800 {
                                                                return Some (BCAX_SVE_Zd_SVE_Zd_SVE_Zm_16_SVE_Zn :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x000800 == 0 {
                                                        if insn & 0xff20fc00 == 0x4203400 {
                                                            return Some (XAR_SVE_Zd_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0x400000 == 0 {
                                                            if insn & 0x800000 == 0 {
                                                                if insn & 0xffe0fc00 == 0x4203c00 {
                                                                    return Some (BSL_SVE_Zd_SVE_Zd_SVE_Zm_16_SVE_Zn :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xffe0fc00 == 0x4a03c00 {
                                                                    return Some (BSL2N_SVE_Zd_SVE_Zd_SVE_Zm_16_SVE_Zn :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x800000 == 0 {
                                                                if insn & 0xffe0fc00 == 0x4603c00 {
                                                                    return Some (BSL1N_SVE_Zd_SVE_Zd_SVE_Zm_16_SVE_Zn :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xffe0fc00 == 0x4e03c00 {
                                                                    return Some (NBSL_SVE_Zd_SVE_Zd_SVE_Zm_16_SVE_Zn :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0x800000 == 0 {
                                                    if insn & 0xffa0e010 == 0x84202000 {
                                                        return Some (PRFH_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RZ_XTW1_22 :: make_opcode (insn)) ;
                                                    }
                                                } else {
                                                    if insn & 0xffa0e000 == 0x84a02000 {
                                                        return Some (LDFF1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW1_22 :: make_opcode (insn)) ;
                                                    }
                                                }
                                            }
                                        } else {
                                            if insn & 0x800000 == 0 {
                                                if insn & 0xffa0e010 == 0xc4202000 {
                                                    return Some (PRFH_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RZ_XTW1_22_c4202000 :: make_opcode (insn)) ;
                                                }
                                            } else {
                                                if insn & 0x80000000 == 0 {
                                                    if insn & 0x000400 == 0 {
                                                        if insn & 0x001000 == 0 {
                                                            if insn & 0x400000 == 0 {
                                                                if insn & 0xffe0f400 == 0x44a02000 {
                                                                    return Some (SQDMLALB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xffe0f400 == 0x44e02000 {
                                                                    return Some (SQDMLALB_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x400000 == 0 {
                                                                if insn & 0xffe0f400 == 0x44a03000 {
                                                                    return Some (SQDMLSLB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xffe0f400 == 0x44e03000 {
                                                                    return Some (SQDMLSLB_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x001000 == 0 {
                                                            if insn & 0x400000 == 0 {
                                                                if insn & 0xffe0f400 == 0x44a02400 {
                                                                    return Some (SQDMLALT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xffe0f400 == 0x44e02400 {
                                                                    return Some (SQDMLALT_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x400000 == 0 {
                                                                if insn & 0xffe0f400 == 0x44a03400 {
                                                                    return Some (SQDMLSLT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xffe0f400 == 0x44e03400 {
                                                                    return Some (SQDMLSLT_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0xffa0e000 == 0xc4a02000 {
                                                        return Some (LDFF1SH_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW1_22_S_D :: make_opcode (insn)) ;
                                                    }
                                                }
                                            }
                                        }
                                    }
                                } else {
                                    if insn & 0x40000000 == 0 {
                                        if insn & 0x80000000 == 0 {
                                            if insn & 0x200000 == 0 {
                                                if insn & 0x010000 == 0 {
                                                    if insn & 0x020000 == 0 {
                                                        if insn & 0x040000 == 0 {
                                                            if insn & 0x080000 == 0 {
                                                                if insn & 0xff3fe000 == 0x410a000 {
                                                                    return Some (SXTB_SVE_Zd_SVE_Pg3_SVE_Zn :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xff3fe000 == 0x418a000 {
                                                                    return Some (CLS_SVE_Zd_SVE_Pg3_SVE_Zn :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x080000 == 0 {
                                                                if insn & 0xffffe000 == 0x4d4a000 {
                                                                    return Some (SXTW_SVE_Zd_SVE_Pg3_SVE_Zn :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xff3fe000 == 0x41ca000 {
                                                                    return Some (FABS_SVE_Zd_SVE_Pg3_SVE_Zn :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x040000 == 0 {
                                                            if insn & 0x080000 == 0 {
                                                                if insn & 0xffbfe000 == 0x492a000 {
                                                                    return Some (SXTH_SVE_Zd_SVE_Pg3_SVE_Zn :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xff3fe000 == 0x41aa000 {
                                                                    return Some (CNT_SVE_Zd_SVE_Pg3_SVE_Zn :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x080000 == 0 {
                                                                if insn & 0xff3fe000 == 0x416a000 {
                                                                    return Some (ABS_SVE_Zd_SVE_Pg3_SVE_Zn :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xff3fe000 == 0x41ea000 {
                                                                    return Some (NOT_SVE_Zd_SVE_Pg3_SVE_Zn :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x020000 == 0 {
                                                        if insn & 0x040000 == 0 {
                                                            if insn & 0x080000 == 0 {
                                                                if insn & 0xff3fe000 == 0x411a000 {
                                                                    return Some (UXTB_SVE_Zd_SVE_Pg3_SVE_Zn :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xff3fe000 == 0x419a000 {
                                                                    return Some (CLZ_SVE_Zd_SVE_Pg3_SVE_Zn :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x080000 == 0 {
                                                                if insn & 0xffffe000 == 0x4d5a000 {
                                                                    return Some (UXTW_SVE_Zd_SVE_Pg3_SVE_Zn :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xff3fe000 == 0x41da000 {
                                                                    return Some (FNEG_SVE_Zd_SVE_Pg3_SVE_Zn :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x040000 == 0 {
                                                            if insn & 0x080000 == 0 {
                                                                if insn & 0xffbfe000 == 0x493a000 {
                                                                    return Some (UXTH_SVE_Zd_SVE_Pg3_SVE_Zn :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xff3fe000 == 0x41ba000 {
                                                                    return Some (CNOT_SVE_Zd_SVE_Pg3_SVE_Zn :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0xff3fe000 == 0x417a000 {
                                                                return Some (NEG_SVE_Zd_SVE_Pg3_SVE_Zn :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0x001000 == 0 {
                                                    if insn & 0x800000 == 0 {
                                                        if insn & 0x400000 == 0 {
                                                            if insn & 0xffe0f000 == 0x420a000 {
                                                                return Some (ADR_SVE_Zd_SVE_ADDR_ZZ_SXTW :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xffe0f000 == 0x460a000 {
                                                                return Some (ADR_SVE_Zd_SVE_ADDR_ZZ_UXTW :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0xffa0f000 == 0x4a0a000 {
                                                            return Some (ADR_SVE_Zd_SVE_ADDR_ZZ_LSL :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x000400 == 0 {
                                                        if insn & 0x000800 == 0 {
                                                            if insn & 0xff20fc00 == 0x420b000 {
                                                                return Some (FTSSEL_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xff3ffc00 == 0x420b800 {
                                                                return Some (FEXPA_SVE_Zd_SVE_Zn :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0xfffffc00 == 0x420bc00 {
                                                            return Some(
                                                                MOVPRFX_SVE_Zd_SVE_Zn::make_opcode(
                                                                    insn,
                                                                ),
                                                            );
                                                        }
                                                    }
                                                }
                                            }
                                        } else {
                                            if insn & 0x400000 == 0 {
                                                if insn & 0x200000 == 0 {
                                                    if insn & 0x800000 == 0 {
                                                        if insn & 0xffe0e000 == 0x8400a000 {
                                                            return Some (LDNT1B_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_ZX_S_S :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xffe0e000 == 0x8480a000 {
                                                            return Some (LDNT1H_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_ZX_S_S :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x800000 == 0 {
                                                        if insn & 0xffe0e000 == 0x8420a000 {
                                                            return Some (LDFF1SB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5 :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xffe0e000 == 0x84a0a000 {
                                                            return Some (LDFF1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x2 :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0x800000 == 0 {
                                                    if insn & 0xffc0e000 == 0x8440a000 {
                                                        return Some (LD1RB_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RI_U6 :: make_opcode (insn)) ;
                                                    }
                                                } else {
                                                    if insn & 0xffc0e000 == 0x84c0a000 {
                                                        return Some (LD1RH_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RI_U6x2 :: make_opcode (insn)) ;
                                                    }
                                                }
                                            }
                                        }
                                    } else {
                                        if insn & 0x200000 == 0 {
                                            if insn & 0x80000000 == 0 {
                                                if insn & 0x010000 == 0 {
                                                    if insn & 0x020000 == 0 {
                                                        if insn & 0x040000 == 0 {
                                                            if insn & 0x080000 == 0 {
                                                                if insn & 0xffffe000 == 0x4480a000 {
                                                                    return Some (URECPE_SVE_Zd_SVE_Pg3_SVE_Zn :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xff3fe000 == 0x4408a000 {
                                                                    return Some (SQABS_SVE_Zd_SVE_Pg3_SVE_Zn :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x100000 == 0 {
                                                                if insn & 0xff3fe000 == 0x4404a000 {
                                                                    return Some (SADALP_SVE_Zd_SVE_Pg3_SVE_Zn :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xff3fe000 == 0x4414a000 {
                                                                    return Some (SMAXP_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0xff3fe000 == 0x4416a000 {
                                                            return Some (SMINP_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x020000 == 0 {
                                                        if insn & 0x040000 == 0 {
                                                            if insn & 0x080000 == 0 {
                                                                if insn & 0x100000 == 0 {
                                                                    if insn & 0xffffe000
                                                                        == 0x4481a000
                                                                    {
                                                                        return Some (URSQRTE_SVE_Zd_SVE_Pg3_SVE_Zn :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xff3fe000
                                                                        == 0x4411a000
                                                                    {
                                                                        return Some (ADDP_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0xff3fe000 == 0x4409a000 {
                                                                    return Some (SQNEG_SVE_Zd_SVE_Pg3_SVE_Zn :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x100000 == 0 {
                                                                if insn & 0xff3fe000 == 0x4405a000 {
                                                                    return Some (UADALP_SVE_Zd_SVE_Pg3_SVE_Zn :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xff3fe000 == 0x4415a000 {
                                                                    return Some (UMAXP_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0xff3fe000 == 0x4417a000 {
                                                            return Some (UMINP_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0x400000 == 0 {
                                                    if insn & 0xffe0e000 == 0xc400a000 {
                                                        return Some (LD1Q_SVE_Zt_SVE_Pg3_SVE_ADDR_ZX :: make_opcode (insn)) ;
                                                    }
                                                } else {
                                                    if insn & 0x800000 == 0 {
                                                        if insn & 0xffe0e000 == 0xc440a000 {
                                                            return Some (LDFF1SB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xffe0e000 == 0xc4c0a000 {
                                                            return Some (LDFF1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                }
                                            }
                                        } else {
                                            if insn & 0x400000 == 0 {
                                                if insn & 0x800000 == 0 {
                                                    if insn & 0xffe0e000 == 0xc420a000 {
                                                        return Some (LDFF1SB_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_ZI_U5_S_D :: make_opcode (insn)) ;
                                                    }
                                                } else {
                                                    if insn & 0x80000000 == 0 {
                                                        if insn & 0x000400 == 0 {
                                                            if insn & 0x001000 == 0 {
                                                                if insn & 0xffe0f400 == 0x44a0a000 {
                                                                    return Some (SMLSLB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xffe0f400 == 0x44a0b000 {
                                                                    return Some (UMLSLB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x001000 == 0 {
                                                                if insn & 0xffe0f400 == 0x44a0a400 {
                                                                    return Some (SMLSLT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xffe0f400 == 0x44a0b400 {
                                                                    return Some (UMLSLT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0xffe0e000 == 0xc4a0a000 {
                                                            return Some (LDFF1SH_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_ZI_U5x2_S_D :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0x800000 == 0 {
                                                    if insn & 0xffe0e010 == 0xc460a000 {
                                                        return Some (PRFH_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RZ_LSL1 :: make_opcode (insn)) ;
                                                    }
                                                } else {
                                                    if insn & 0x80000000 == 0 {
                                                        if insn & 0x000400 == 0 {
                                                            if insn & 0x001000 == 0 {
                                                                if insn & 0xffe0f400 == 0x44e0a000 {
                                                                    return Some (SMLSLB_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xffe0f400 == 0x44e0b000 {
                                                                    return Some (UMLSLB_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x001000 == 0 {
                                                                if insn & 0xffe0f400 == 0x44e0a400 {
                                                                    return Some (SMLSLT_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xffe0f400 == 0x44e0b400 {
                                                                    return Some (UMLSLT_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0xffe0e000 == 0xc4e0a000 {
                                                            return Some (LDFF1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL1 :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                }
                                            }
                                        }
                                    }
                                }
                            } else {
                                if insn & 0x008000 == 0 {
                                    if insn & 0x200000 == 0 {
                                        if insn & 0x40000000 == 0 {
                                            if insn & 0x80000000 == 0 {
                                                if insn & 0xff20e000 == 0x4006000 {
                                                    return Some (MLS_SVE_Zd_SVE_Pg3_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                }
                                            } else {
                                                if insn & 0x800000 == 0 {
                                                    if insn & 0xffa0e000 == 0x84006000 {
                                                        return Some (LDFF1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22 :: make_opcode (insn)) ;
                                                    }
                                                } else {
                                                    if insn & 0xffa0e000 == 0x84806000 {
                                                        return Some (LDFF1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22 :: make_opcode (insn)) ;
                                                    }
                                                }
                                            }
                                        } else {
                                            if insn & 0x80000000 == 0 {
                                                if insn & 0x000400 == 0 {
                                                    if insn & 0x000800 == 0 {
                                                        if insn & 0x001000 == 0 {
                                                            if insn & 0xff20fc00 == 0x44006000 {
                                                                return Some (SQDMLALB_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xff20fc00 == 0x44007000 {
                                                                return Some (SQRDMLAH_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x001000 == 0 {
                                                            if insn & 0xff20fc00 == 0x44006800 {
                                                                return Some (SQDMLSLB_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xffe0fc00 == 0x44807800 {
                                                                return Some (USDOT_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x000800 == 0 {
                                                        if insn & 0x001000 == 0 {
                                                            if insn & 0xff20fc00 == 0x44006400 {
                                                                return Some (SQDMLALT_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xff20fc00 == 0x44007400 {
                                                                return Some (SQRDMLSH_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0xff20fc00 == 0x44006c00 {
                                                            return Some (SQDMLSLT_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0x800000 == 0 {
                                                    if insn & 0xffa0e000 == 0xc4006000 {
                                                        return Some (LDFF1B_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW_22_S_D :: make_opcode (insn)) ;
                                                    }
                                                } else {
                                                    if insn & 0xffa0e000 == 0xc4806000 {
                                                        return Some (LDFF1H_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW_22_S_D :: make_opcode (insn)) ;
                                                    }
                                                }
                                            }
                                        }
                                    } else {
                                        if insn & 0x40000000 == 0 {
                                            if insn & 0x80000000 == 0 {
                                                if insn & 0x000400 == 0 {
                                                    if insn & 0x000800 == 0 {
                                                        if insn & 0x001000 == 0 {
                                                            if insn & 0xff20fc00 == 0x4206000 {
                                                                return Some (MUL_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xff20fc00 == 0x4207000 {
                                                                return Some (SQDMULH_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0xff20fc00 == 0x4206800 {
                                                            return Some (SMULH_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x000800 == 0 {
                                                        if insn & 0x001000 == 0 {
                                                            if insn & 0xffe0fc00 == 0x4206400 {
                                                                return Some (PMUL_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xff20fc00 == 0x4207400 {
                                                                return Some (SQRDMULH_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0xff20fc00 == 0x4206c00 {
                                                            return Some (UMULH_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0x800000 == 0 {
                                                    if insn & 0xffa0e010 == 0x84206000 {
                                                        return Some (PRFD_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RZ_XTW3_22 :: make_opcode (insn)) ;
                                                    }
                                                } else {
                                                    if insn & 0xffa0e000 == 0x84a06000 {
                                                        return Some (LDFF1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW1_22 :: make_opcode (insn)) ;
                                                    }
                                                }
                                            }
                                        } else {
                                            if insn & 0x800000 == 0 {
                                                if insn & 0xffa0e010 == 0xc4206000 {
                                                    return Some (PRFD_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RZ_XTW3_22_c4206000 :: make_opcode (insn)) ;
                                                }
                                            } else {
                                                if insn & 0x80000000 == 0 {
                                                    if insn & 0x001000 == 0 {
                                                        if insn & 0x400000 == 0 {
                                                            if insn & 0xffe0f000 == 0x44a06000 {
                                                                return Some (CMLA_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX_SVE_IMM_ROT2 :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xffe0f000 == 0x44e06000 {
                                                                return Some (CMLA_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX_SVE_IMM_ROT2 :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x400000 == 0 {
                                                            if insn & 0xffe0f000 == 0x44a07000 {
                                                                return Some (SQRDCMLAH_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX_SVE_IMM_ROT2 :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xffe0f000 == 0x44e07000 {
                                                                return Some (SQRDCMLAH_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX_SVE_IMM_ROT2 :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0xffa0e000 == 0xc4a06000 {
                                                        return Some (LDFF1H_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW1_22_S_D :: make_opcode (insn)) ;
                                                    }
                                                }
                                            }
                                        }
                                    }
                                } else {
                                    if insn & 0x40000000 == 0 {
                                        if insn & 0x80000000 == 0 {
                                            if insn & 0x200000 == 0 {
                                                if insn & 0xff20e000 == 0x400e000 {
                                                    return Some (MSB_SVE_Zd_SVE_Pg3_SVE_Zm_16_SVE_Za_5 :: make_opcode (insn)) ;
                                                }
                                            } else {
                                                if insn & 0x000400 == 0 {
                                                    if insn & 0x000800 == 0 {
                                                        if insn & 0x001000 == 0 {
                                                            if insn & 0x100000 == 0 {
                                                                if insn & 0x400000 == 0 {
                                                                    if insn & 0x800000 == 0 {
                                                                        if insn & 0xfff0fc00
                                                                            == 0x420e000
                                                                        {
                                                                            return Some (CNTB_Rd_SVE_PATTERN_SCALED :: make_opcode (insn)) ;
                                                                        }
                                                                    } else {
                                                                        if insn & 0xfff0fc00
                                                                            == 0x4a0e000
                                                                        {
                                                                            return Some (CNTW_Rd_SVE_PATTERN_SCALED :: make_opcode (insn)) ;
                                                                        }
                                                                    }
                                                                } else {
                                                                    if insn & 0x800000 == 0 {
                                                                        if insn & 0xfff0fc00
                                                                            == 0x460e000
                                                                        {
                                                                            return Some (CNTH_Rd_SVE_PATTERN_SCALED :: make_opcode (insn)) ;
                                                                        }
                                                                    } else {
                                                                        if insn & 0xfff0fc00
                                                                            == 0x4e0e000
                                                                        {
                                                                            return Some (CNTD_Rd_SVE_PATTERN_SCALED :: make_opcode (insn)) ;
                                                                        }
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0x400000 == 0 {
                                                                    if insn & 0x800000 == 0 {
                                                                        if insn & 0xfff0fc00
                                                                            == 0x430e000
                                                                        {
                                                                            return Some (INCB_Rd_SVE_PATTERN_SCALED :: make_opcode (insn)) ;
                                                                        }
                                                                    } else {
                                                                        if insn & 0xfff0fc00
                                                                            == 0x4b0e000
                                                                        {
                                                                            return Some (INCW_Rd_SVE_PATTERN_SCALED :: make_opcode (insn)) ;
                                                                        }
                                                                    }
                                                                } else {
                                                                    if insn & 0x800000 == 0 {
                                                                        if insn & 0xfff0fc00
                                                                            == 0x470e000
                                                                        {
                                                                            return Some (INCH_Rd_SVE_PATTERN_SCALED :: make_opcode (insn)) ;
                                                                        }
                                                                    } else {
                                                                        if insn & 0xfff0fc00
                                                                            == 0x4f0e000
                                                                        {
                                                                            return Some (INCD_Rd_SVE_PATTERN_SCALED :: make_opcode (insn)) ;
                                                                        }
                                                                    }
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x100000 == 0 {
                                                                if insn & 0x400000 == 0 {
                                                                    if insn & 0x800000 == 0 {
                                                                        if insn & 0xfff0fc00
                                                                            == 0x420f000
                                                                        {
                                                                            return Some (SQINCB_Rd_Rd_SVE_PATTERN_SCALED :: make_opcode (insn)) ;
                                                                        }
                                                                    } else {
                                                                        if insn & 0xfff0fc00
                                                                            == 0x4a0f000
                                                                        {
                                                                            return Some (SQINCW_Rd_Rd_SVE_PATTERN_SCALED :: make_opcode (insn)) ;
                                                                        }
                                                                    }
                                                                } else {
                                                                    if insn & 0x800000 == 0 {
                                                                        if insn & 0xfff0fc00
                                                                            == 0x460f000
                                                                        {
                                                                            return Some (SQINCH_Rd_Rd_SVE_PATTERN_SCALED :: make_opcode (insn)) ;
                                                                        }
                                                                    } else {
                                                                        if insn & 0xfff0fc00
                                                                            == 0x4e0f000
                                                                        {
                                                                            return Some (SQINCD_Rd_Rd_SVE_PATTERN_SCALED :: make_opcode (insn)) ;
                                                                        }
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0x400000 == 0 {
                                                                    if insn & 0x800000 == 0 {
                                                                        if insn & 0xfff0fc00
                                                                            == 0x430f000
                                                                        {
                                                                            return Some (SQINCB_Rd_SVE_PATTERN_SCALED :: make_opcode (insn)) ;
                                                                        }
                                                                    } else {
                                                                        if insn & 0xfff0fc00
                                                                            == 0x4b0f000
                                                                        {
                                                                            return Some (SQINCW_Rd_SVE_PATTERN_SCALED :: make_opcode (insn)) ;
                                                                        }
                                                                    }
                                                                } else {
                                                                    if insn & 0x800000 == 0 {
                                                                        if insn & 0xfff0fc00
                                                                            == 0x470f000
                                                                        {
                                                                            return Some (SQINCH_Rd_SVE_PATTERN_SCALED :: make_opcode (insn)) ;
                                                                        }
                                                                    } else {
                                                                        if insn & 0xfff0fc00
                                                                            == 0x4f0f000
                                                                        {
                                                                            return Some (SQINCD_Rd_SVE_PATTERN_SCALED :: make_opcode (insn)) ;
                                                                        }
                                                                    }
                                                                }
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x100000 == 0 {
                                                            if insn & 0x400000 == 0 {
                                                                if insn & 0x800000 == 0 {
                                                                    if insn & 0xfff0fc00
                                                                        == 0x420f800
                                                                    {
                                                                        return Some (SQDECB_Rd_Rd_SVE_PATTERN_SCALED :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xfff0fc00
                                                                        == 0x4a0f800
                                                                    {
                                                                        return Some (SQDECW_Rd_Rd_SVE_PATTERN_SCALED :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0x800000 == 0 {
                                                                    if insn & 0xfff0fc00
                                                                        == 0x460f800
                                                                    {
                                                                        return Some (SQDECH_Rd_Rd_SVE_PATTERN_SCALED :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xfff0fc00
                                                                        == 0x4e0f800
                                                                    {
                                                                        return Some (SQDECD_Rd_Rd_SVE_PATTERN_SCALED :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x400000 == 0 {
                                                                if insn & 0x800000 == 0 {
                                                                    if insn & 0xfff0fc00
                                                                        == 0x430f800
                                                                    {
                                                                        return Some (SQDECB_Rd_SVE_PATTERN_SCALED :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xfff0fc00
                                                                        == 0x4b0f800
                                                                    {
                                                                        return Some (SQDECW_Rd_SVE_PATTERN_SCALED :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0x800000 == 0 {
                                                                    if insn & 0xfff0fc00
                                                                        == 0x470f800
                                                                    {
                                                                        return Some (SQDECH_Rd_SVE_PATTERN_SCALED :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xfff0fc00
                                                                        == 0x4f0f800
                                                                    {
                                                                        return Some (SQDECD_Rd_SVE_PATTERN_SCALED :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            }
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x000800 == 0 {
                                                        if insn & 0x001000 == 0 {
                                                            if insn & 0x400000 == 0 {
                                                                if insn & 0x800000 == 0 {
                                                                    if insn & 0xfff0fc00
                                                                        == 0x430e400
                                                                    {
                                                                        return Some (DECB_Rd_SVE_PATTERN_SCALED :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xfff0fc00
                                                                        == 0x4b0e400
                                                                    {
                                                                        return Some (DECW_Rd_SVE_PATTERN_SCALED :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0x800000 == 0 {
                                                                    if insn & 0xfff0fc00
                                                                        == 0x470e400
                                                                    {
                                                                        return Some (DECH_Rd_SVE_PATTERN_SCALED :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xfff0fc00
                                                                        == 0x4f0e400
                                                                    {
                                                                        return Some (DECD_Rd_SVE_PATTERN_SCALED :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x100000 == 0 {
                                                                if insn & 0x400000 == 0 {
                                                                    if insn & 0x800000 == 0 {
                                                                        if insn & 0xfff0fc00
                                                                            == 0x420f400
                                                                        {
                                                                            return Some (UQINCB_Rd_SVE_PATTERN_SCALED :: make_opcode (insn)) ;
                                                                        }
                                                                    } else {
                                                                        if insn & 0xfff0fc00
                                                                            == 0x4a0f400
                                                                        {
                                                                            return Some (UQINCW_Rd_SVE_PATTERN_SCALED :: make_opcode (insn)) ;
                                                                        }
                                                                    }
                                                                } else {
                                                                    if insn & 0x800000 == 0 {
                                                                        if insn & 0xfff0fc00
                                                                            == 0x460f400
                                                                        {
                                                                            return Some (UQINCH_Rd_SVE_PATTERN_SCALED :: make_opcode (insn)) ;
                                                                        }
                                                                    } else {
                                                                        if insn & 0xfff0fc00
                                                                            == 0x4e0f400
                                                                        {
                                                                            return Some (UQINCD_Rd_SVE_PATTERN_SCALED :: make_opcode (insn)) ;
                                                                        }
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0x400000 == 0 {
                                                                    if insn & 0x800000 == 0 {
                                                                        if insn & 0xfff0fc00
                                                                            == 0x430f400
                                                                        {
                                                                            return Some (UQINCB_Rd_X_SVE_PATTERN_SCALED :: make_opcode (insn)) ;
                                                                        }
                                                                    } else {
                                                                        if insn & 0xfff0fc00
                                                                            == 0x4b0f400
                                                                        {
                                                                            return Some (UQINCW_Rd_X_SVE_PATTERN_SCALED :: make_opcode (insn)) ;
                                                                        }
                                                                    }
                                                                } else {
                                                                    if insn & 0x800000 == 0 {
                                                                        if insn & 0xfff0fc00
                                                                            == 0x470f400
                                                                        {
                                                                            return Some (UQINCH_Rd_X_SVE_PATTERN_SCALED :: make_opcode (insn)) ;
                                                                        }
                                                                    } else {
                                                                        if insn & 0xfff0fc00
                                                                            == 0x4f0f400
                                                                        {
                                                                            return Some (UQINCD_Rd_X_SVE_PATTERN_SCALED :: make_opcode (insn)) ;
                                                                        }
                                                                    }
                                                                }
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x100000 == 0 {
                                                            if insn & 0x400000 == 0 {
                                                                if insn & 0x800000 == 0 {
                                                                    if insn & 0xfff0fc00
                                                                        == 0x420fc00
                                                                    {
                                                                        return Some (UQDECB_Rd_SVE_PATTERN_SCALED :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xfff0fc00
                                                                        == 0x4a0fc00
                                                                    {
                                                                        return Some (UQDECW_Rd_SVE_PATTERN_SCALED :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0x800000 == 0 {
                                                                    if insn & 0xfff0fc00
                                                                        == 0x460fc00
                                                                    {
                                                                        return Some (UQDECH_Rd_SVE_PATTERN_SCALED :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xfff0fc00
                                                                        == 0x4e0fc00
                                                                    {
                                                                        return Some (UQDECD_Rd_SVE_PATTERN_SCALED :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x400000 == 0 {
                                                                if insn & 0x800000 == 0 {
                                                                    if insn & 0xfff0fc00
                                                                        == 0x430fc00
                                                                    {
                                                                        return Some (UQDECB_Rd_X_SVE_PATTERN_SCALED :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xfff0fc00
                                                                        == 0x4b0fc00
                                                                    {
                                                                        return Some (UQDECW_Rd_X_SVE_PATTERN_SCALED :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0x800000 == 0 {
                                                                    if insn & 0xfff0fc00
                                                                        == 0x470fc00
                                                                    {
                                                                        return Some (UQDECH_Rd_X_SVE_PATTERN_SCALED :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xfff0fc00
                                                                        == 0x4f0fc00
                                                                    {
                                                                        return Some (UQDECD_Rd_X_SVE_PATTERN_SCALED :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            }
                                                        }
                                                    }
                                                }
                                            }
                                        } else {
                                            if insn & 0x400000 == 0 {
                                                if insn & 0x200000 == 0 {
                                                    if insn & 0x800000 == 0 {
                                                        if insn & 0xffe0e010 == 0x8400e000 {
                                                            return Some (PRFB_SVE_PRFOP_SVE_Pg3_SVE_ADDR_ZI_U5 :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xffe0e010 == 0x8480e000 {
                                                            return Some (PRFH_SVE_PRFOP_SVE_Pg3_SVE_ADDR_ZI_U5x2 :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x800000 == 0 {
                                                        if insn & 0xffe0e000 == 0x8420e000 {
                                                            return Some (LDFF1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5 :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xffe0e000 == 0x84a0e000 {
                                                            return Some (LDFF1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x2 :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0x800000 == 0 {
                                                    if insn & 0xffc0e000 == 0x8440e000 {
                                                        return Some (LD1RB_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RI_U6 :: make_opcode (insn)) ;
                                                    }
                                                } else {
                                                    if insn & 0xffc0e000 == 0x84c0e000 {
                                                        return Some (LD1RH_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RI_U6x2 :: make_opcode (insn)) ;
                                                    }
                                                }
                                            }
                                        }
                                    } else {
                                        if insn & 0x200000 == 0 {
                                            if insn & 0x400000 == 0 {
                                                if insn & 0x800000 == 0 {
                                                    if insn & 0xffe0e010 == 0xc400e000 {
                                                        return Some (PRFB_SVE_PRFOP_SVE_Pg3_SVE_ADDR_ZI_U5_c400e000 :: make_opcode (insn)) ;
                                                    }
                                                } else {
                                                    if insn & 0xffe0e010 == 0xc480e000 {
                                                        return Some (PRFH_SVE_PRFOP_SVE_Pg3_SVE_ADDR_ZI_U5x2_c480e000 :: make_opcode (insn)) ;
                                                    }
                                                }
                                            } else {
                                                if insn & 0x800000 == 0 {
                                                    if insn & 0xffe0e000 == 0xc440e000 {
                                                        return Some (LDFF1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ :: make_opcode (insn)) ;
                                                    }
                                                } else {
                                                    if insn & 0xffe0e000 == 0xc4c0e000 {
                                                        return Some (LDFF1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ :: make_opcode (insn)) ;
                                                    }
                                                }
                                            }
                                        } else {
                                            if insn & 0x800000 == 0 {
                                                if insn & 0x80000000 == 0 {
                                                    if insn & 0x000400 == 0 {
                                                        if insn & 0x000800 == 0 {
                                                            if insn & 0xffa0fc00 == 0x4420f000 {
                                                                return Some (SQDMULH_SVE_Zd_SVE_Zn_SVE_Zm3_22_INDEX :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xffa0fc00 == 0x4420f800 {
                                                                return Some (MUL_SVE_Zd_SVE_Zn_SVE_Zm3_22_INDEX :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0xffa0fc00 == 0x4420f400 {
                                                            return Some (SQRDMULH_SVE_Zd_SVE_Zn_SVE_Zm3_22_INDEX :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x400000 == 0 {
                                                        if insn & 0xffe0e000 == 0xc420e000 {
                                                            return Some (LDFF1B_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_ZI_U5_S_D :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xffe0e010 == 0xc460e000 {
                                                            return Some (PRFD_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RZ_LSL3 :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0x400000 == 0 {
                                                    if insn & 0x80000000 == 0 {
                                                        if insn & 0x000400 == 0 {
                                                            if insn & 0x001000 == 0 {
                                                                if insn & 0xffe0f400 == 0x44a0e000 {
                                                                    return Some (SQDMULLB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0x000800 == 0 {
                                                                    if insn & 0xffe0fc00
                                                                        == 0x44a0f000
                                                                    {
                                                                        return Some (SQDMULH_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xffe0fc00
                                                                        == 0x44a0f800
                                                                    {
                                                                        return Some (MUL_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x001000 == 0 {
                                                                if insn & 0xffe0f400 == 0x44a0e400 {
                                                                    return Some (SQDMULLT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xffe0fc00 == 0x44a0f400 {
                                                                    return Some (SQRDMULH_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0xffe0e000 == 0xc4a0e000 {
                                                            return Some (LDFF1H_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_ZI_U5x2_S_D :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x80000000 == 0 {
                                                        if insn & 0x000400 == 0 {
                                                            if insn & 0x001000 == 0 {
                                                                if insn & 0xffe0f400 == 0x44e0e000 {
                                                                    return Some (SQDMULLB_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0x000800 == 0 {
                                                                    if insn & 0xffe0fc00
                                                                        == 0x44e0f000
                                                                    {
                                                                        return Some (SQDMULH_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xffe0fc00
                                                                        == 0x44e0f800
                                                                    {
                                                                        return Some (MUL_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x001000 == 0 {
                                                                if insn & 0xffe0f400 == 0x44e0e400 {
                                                                    return Some (SQDMULLT_SVE_Zd_SVE_Zn_SVE_Zm4_11_INDEX :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xffe0fc00 == 0x44e0f400 {
                                                                    return Some (SQRDMULH_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0xffe0e000 == 0xc4e0e000 {
                                                            return Some (LDFF1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL1 :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                }
                                            }
                                        }
                                    }
                                }
                            }
                        }
                    } else {
                        if insn & 0x200000 == 0 {
                            if insn & 0x008000 == 0 {
                                if insn & 0x40000000 == 0 {
                                    if insn & 0x002000 == 0 {
                                        if insn & 0x004000 == 0 {
                                            if insn & 0x80000000 == 0 {
                                                if insn & 0x000010 == 0 {
                                                    if insn & 0xff20e010 == 0x24000000 {
                                                        return Some (CMPHS_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                    }
                                                } else {
                                                    if insn & 0xff20e010 == 0x24000010 {
                                                        return Some (CMPHI_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                    }
                                                }
                                            } else {
                                                if insn & 0x800000 == 0 {
                                                    if insn & 0xffe0e000 == 0xa4000000 {
                                                        return Some (LD1RQB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX :: make_opcode (insn)) ;
                                                    }
                                                } else {
                                                    if insn & 0xffe0e000 == 0xa4800000 {
                                                        return Some (LD1RQH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1 :: make_opcode (insn)) ;
                                                    }
                                                }
                                            }
                                        } else {
                                            if insn & 0x80000000 == 0 {
                                                if insn & 0x000010 == 0 {
                                                    if insn & 0xff20e010 == 0x24004000 {
                                                        return Some (CMPGE_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                    }
                                                } else {
                                                    if insn & 0xff20e010 == 0x24004010 {
                                                        return Some (CMPGT_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                    }
                                                }
                                            } else {
                                                if insn & 0x400000 == 0 {
                                                    if insn & 0x800000 == 0 {
                                                        if insn & 0xffe0e000 == 0xa4004000 {
                                                            return Some (LD1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xffe0e000 == 0xa4804000 {
                                                            return Some (LD1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2 :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x800000 == 0 {
                                                        if insn & 0xffe0e000 == 0xa4404000 {
                                                            return Some (LD1B_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RX :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xffe0e000 == 0xa4c04000 {
                                                            return Some (LD1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1 :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                }
                                            }
                                        }
                                    } else {
                                        if insn & 0x004000 == 0 {
                                            if insn & 0x80000000 == 0 {
                                                if insn & 0x000010 == 0 {
                                                    if insn & 0xff20e010 == 0x24002000 {
                                                        return Some (CMPEQ_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                    }
                                                } else {
                                                    if insn & 0xff20e010 == 0x24002010 {
                                                        return Some (CMPNE_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                    }
                                                }
                                            } else {
                                                if insn & 0x800000 == 0 {
                                                    if insn & 0xfff0e000 == 0xa4002000 {
                                                        return Some (LD1RQB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x16 :: make_opcode (insn)) ;
                                                    }
                                                } else {
                                                    if insn & 0xfff0e000 == 0xa4802000 {
                                                        return Some (LD1RQH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x16 :: make_opcode (insn)) ;
                                                    }
                                                }
                                            }
                                        } else {
                                            if insn & 0x80000000 == 0 {
                                                if insn & 0x000010 == 0 {
                                                    if insn & 0xff20e010 == 0x24006000 {
                                                        return Some (CMPLT_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                    }
                                                } else {
                                                    if insn & 0xff20e010 == 0x24006010 {
                                                        return Some (CMPLE_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                    }
                                                }
                                            } else {
                                                if insn & 0x400000 == 0 {
                                                    if insn & 0x800000 == 0 {
                                                        if insn & 0xffe0e000 == 0xa4006000 {
                                                            return Some (LDFF1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_R :: make_opcode (insn)) ;
                                                        }
                                                        if insn & 0xffe0e000 == 0xa4006000 {
                                                            return Some (LDFF1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_R :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xffe0e000 == 0xa4806000 {
                                                            return Some (LDFF1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_R :: make_opcode (insn)) ;
                                                        }
                                                        if insn & 0xffe0e000 == 0xa4806000 {
                                                            return Some (LDFF1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_R :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x800000 == 0 {
                                                        if insn & 0xffe0e000 == 0xa4406000 {
                                                            return Some (LDFF1B_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_R :: make_opcode (insn)) ;
                                                        }
                                                        if insn & 0xffe0e000 == 0xa4406000 {
                                                            return Some (LDFF1B_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_R :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xffe0e000 == 0xa4c06000 {
                                                            return Some (LDFF1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_R :: make_opcode (insn)) ;
                                                        }
                                                        if insn & 0xffe0e000 == 0xa4c06000 {
                                                            return Some (LDFF1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_R :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                }
                                            }
                                        }
                                    }
                                } else {
                                    if insn & 0x80000000 == 0 {
                                        if insn & 0xff208000 == 0x64000000 {
                                            return Some (FCMLA_SVE_Zd_SVE_Pg3_SVE_Zn_SVE_Zm_16_IMM_ROT2 :: make_opcode (insn)) ;
                                        }
                                    } else {
                                        if insn & 0x002000 == 0 {
                                            if insn & 0x004000 == 0 {
                                                if insn & 0x400000 == 0 {
                                                    if insn & 0xfff0e000 == 0xe4800000 {
                                                        return Some (ST3Q_SME_Zt3_SVE_Pg3_SVE_ADDR_RI_S4x2xVL :: make_opcode (insn)) ;
                                                    }
                                                } else {
                                                    if insn & 0x800000 == 0 {
                                                        if insn & 0xfff0e000 == 0xe4400000 {
                                                            return Some (ST2Q_SME_Zt2_SVE_Pg3_SVE_ADDR_RI_S4x2xVL :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xfff0e000 == 0xe4c00000 {
                                                            return Some (ST4Q_SME_Zt4_SVE_Pg3_SVE_ADDR_RI_S4x2xVL :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0x400000 == 0 {
                                                    if insn & 0xffe0e000 == 0xe4004000 {
                                                        return Some (ST1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX :: make_opcode (insn)) ;
                                                    }
                                                } else {
                                                    if insn & 0x800000 == 0 {
                                                        if insn & 0xffe0e000 == 0xe4404000 {
                                                            return Some (ST1B_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_RX :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xffe0e000 == 0xe4c04000 {
                                                            return Some (ST1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1 :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                }
                                            }
                                        } else {
                                            if insn & 0x004000 == 0 {
                                                if insn & 0x400000 == 0 {
                                                    if insn & 0x800000 == 0 {
                                                        if insn & 0xffe0e000 == 0xe4002000 {
                                                            return Some (STNT1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZX :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xffe0e000 == 0xe4802000 {
                                                            return Some (STNT1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZX :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x800000 == 0 {
                                                        if insn & 0xffe0e000 == 0xe4402000 {
                                                            return Some (STNT1B_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_ZX :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xffe0e000 == 0xe4c02000 {
                                                            return Some (STNT1H_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_ZX :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0x400000 == 0 {
                                                    if insn & 0x800000 == 0 {
                                                        if insn & 0xffe0e000 == 0xe4006000 {
                                                            return Some (STNT1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xffe0e000 == 0xe4806000 {
                                                            return Some (STNT1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1 :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x800000 == 0 {
                                                        if insn & 0xffe0e000 == 0xe4406000 {
                                                            return Some (ST3B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xffe0e000 == 0xe4c06000 {
                                                            return Some (ST3H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1 :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                }
                                            }
                                        }
                                    }
                                }
                            } else {
                                if insn & 0x002000 == 0 {
                                    if insn & 0x40000000 == 0 {
                                        if insn & 0x004000 == 0 {
                                            if insn & 0x000010 == 0 {
                                                if insn & 0xff20e010 == 0x24008000 {
                                                    return Some (CMPGE_SVE_Pd_S_B_SVE_Pg3_P_Z_SVE_Zn_S_B_SVE_Zm_16_S_B :: make_opcode (insn)) ;
                                                }
                                            } else {
                                                if insn & 0xff20e010 == 0x24008010 {
                                                    return Some (CMPGT_SVE_Pd_S_B_SVE_Pg3_P_Z_SVE_Zn_S_B_SVE_Zm_16_S_B :: make_opcode (insn)) ;
                                                }
                                            }
                                        } else {
                                            if insn & 0x80000000 == 0 {
                                                if insn & 0x000010 == 0 {
                                                    if insn & 0xff20e010 == 0x2400c000 {
                                                        return Some (CMPHS_SVE_Pd_S_B_SVE_Pg3_P_Z_SVE_Zn_S_B_SVE_Zm_16_S_D :: make_opcode (insn)) ;
                                                    }
                                                } else {
                                                    if insn & 0xff20e010 == 0x2400c010 {
                                                        return Some (CMPHI_SVE_Pd_S_B_SVE_Pg3_P_Z_SVE_Zn_S_B_SVE_Zm_16_S_D :: make_opcode (insn)) ;
                                                    }
                                                }
                                            } else {
                                                if insn & 0x400000 == 0 {
                                                    if insn & 0x800000 == 0 {
                                                        if insn & 0xffe0e000 == 0xa400c000 {
                                                            return Some (LDNT1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xffe0e000 == 0xa480c000 {
                                                            return Some (LDNT1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1 :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x800000 == 0 {
                                                        if insn & 0xffe0e000 == 0xa440c000 {
                                                            return Some (LD3B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xffe0e000 == 0xa4c0c000 {
                                                            return Some (LD3H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1 :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                }
                                            }
                                        }
                                    } else {
                                        if insn & 0x80000000 == 0 {
                                            if insn & 0x020000 == 0 {
                                                if insn & 0x040000 == 0 {
                                                    if insn & 0x100000 == 0 {
                                                        if insn & 0xff3ee000 == 0x64008000 {
                                                            return Some (FCADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5_SVE_IMM_ROT1 :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xff3fe000 == 0x64108000 {
                                                            return Some (FADDP_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x010000 == 0 {
                                                        if insn & 0xff3fe000 == 0x64148000 {
                                                            return Some (FMAXNMP_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xff3fe000 == 0x64158000 {
                                                            return Some (FMINNMP_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0x010000 == 0 {
                                                    if insn & 0xff3fe000 == 0x64168000 {
                                                        return Some (FMAXP_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn :: make_opcode (insn)) ;
                                                    }
                                                } else {
                                                    if insn & 0xff3fe000 == 0x64178000 {
                                                        return Some (FMINP_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zn :: make_opcode (insn)) ;
                                                    }
                                                }
                                            }
                                        } else {
                                            if insn & 0x400000 == 0 {
                                                if insn & 0x800000 == 0 {
                                                    if insn & 0xffe0a000 == 0xe4008000 {
                                                        return Some (ST1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_14 :: make_opcode (insn)) ;
                                                    }
                                                } else {
                                                    if insn & 0xffe0a000 == 0xe4808000 {
                                                        return Some (ST1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_14 :: make_opcode (insn)) ;
                                                    }
                                                }
                                            } else {
                                                if insn & 0x800000 == 0 {
                                                    if insn & 0xffe0a000 == 0xe4408000 {
                                                        return Some (ST1B_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_RZ_XTW_14 :: make_opcode (insn)) ;
                                                    }
                                                } else {
                                                    if insn & 0xffe0a000 == 0xe4c08000 {
                                                        return Some (ST1H_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_RZ_XTW_14 :: make_opcode (insn)) ;
                                                    }
                                                }
                                            }
                                        }
                                    }
                                } else {
                                    if insn & 0x004000 == 0 {
                                        if insn & 0x40000000 == 0 {
                                            if insn & 0x80000000 == 0 {
                                                if insn & 0x000010 == 0 {
                                                    if insn & 0xff20e010 == 0x2400a000 {
                                                        return Some (CMPEQ_SVE_Pd_S_B_SVE_Pg3_P_Z_SVE_Zn_S_B_SVE_Zm_16_S_B :: make_opcode (insn)) ;
                                                    }
                                                } else {
                                                    if insn & 0xff20e010 == 0x2400a010 {
                                                        return Some (CMPNE_SVE_Pd_S_B_SVE_Pg3_P_Z_SVE_Zn_S_B_SVE_Zm_16_S_B :: make_opcode (insn)) ;
                                                    }
                                                }
                                            } else {
                                                if insn & 0x100000 == 0 {
                                                    if insn & 0x400000 == 0 {
                                                        if insn & 0x800000 == 0 {
                                                            if insn & 0xfff0e000 == 0xa400a000 {
                                                                return Some (LD1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xfff0e000 == 0xa480a000 {
                                                                return Some (LD1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x800000 == 0 {
                                                            if insn & 0xfff0e000 == 0xa440a000 {
                                                                return Some (LD1B_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xfff0e000 == 0xa4c0a000 {
                                                                return Some (LD1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x400000 == 0 {
                                                        if insn & 0x800000 == 0 {
                                                            if insn & 0xfff0e000 == 0xa410a000 {
                                                                return Some (LDNF1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xfff0e000 == 0xa490a000 {
                                                                return Some (LDNF1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x800000 == 0 {
                                                            if insn & 0xfff0e000 == 0xa450a000 {
                                                                return Some (LDNF1B_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xfff0e000 == 0xa4d0a000 {
                                                                return Some (LDNF1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    }
                                                }
                                            }
                                        } else {
                                            if insn & 0x80000000 == 0 {
                                                if insn & 0x010000 == 0 {
                                                    if insn & 0x020000 == 0 {
                                                        if insn & 0x040000 == 0 {
                                                            if insn & 0x080000 == 0 {
                                                                if insn & 0xff3fe000 == 0x6410a000 {
                                                                    return Some (FADDQV_Vd_SVE_Pg3_SVE_Zn :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xffffe000 == 0x6488a000 {
                                                                    return Some (FCVTNT_SVE_Zd_SVE_Pg3_SVE_Zn :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0xff3fe000 == 0x6414a000 {
                                                                return Some (FMAXNMQV_Vd_SVE_Pg3_SVE_Zn :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x040000 == 0 {
                                                            if insn & 0x400000 == 0 {
                                                                if insn & 0x800000 == 0 {
                                                                    if insn & 0xffffe000
                                                                        == 0x640aa000
                                                                    {
                                                                        return Some (FCVTXNT_SVE_Zd_SVE_Pg3_SVE_Zn :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xffffe000
                                                                        == 0x648aa000
                                                                    {
                                                                        return Some (BFCVTNT_SVE_Zd_SVE_Pg3_SVE_Zn :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0xffffe000 == 0x64caa000 {
                                                                    return Some (FCVTNT_SVE_Zd_S_S_SVE_Pg3_P_M_SVE_Zn_S_D :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0xff3fe000 == 0x6416a000 {
                                                                return Some (FMAXQV_Vd_SVE_Pg3_SVE_Zn :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x020000 == 0 {
                                                        if insn & 0x040000 == 0 {
                                                            if insn & 0xffffe000 == 0x6489a000 {
                                                                return Some (FCVTLT_SVE_Zd_SVE_Pg3_SVE_Zn :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xff3fe000 == 0x6415a000 {
                                                                return Some (FMINNMQV_Vd_SVE_Pg3_SVE_Zn :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x040000 == 0 {
                                                            if insn & 0xffffe000 == 0x64cba000 {
                                                                return Some (FCVTLT_SVE_Zd_S_D_SVE_Pg3_P_M_SVE_Zn_S_S :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xff3fe000 == 0x6417a000 {
                                                                return Some (FMINQV_Vd_SVE_Pg3_SVE_Zn :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0x400000 == 0 {
                                                    if insn & 0x800000 == 0 {
                                                        if insn & 0xffe0e000 == 0xe400a000 {
                                                            return Some (ST1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xffe0e000 == 0xe480a000 {
                                                            return Some (ST1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x800000 == 0 {
                                                        if insn & 0xffe0e000 == 0xe440a000 {
                                                            return Some (ST1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5 :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xffe0e000 == 0xe4c0a000 {
                                                            return Some (ST1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x2 :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                }
                                            }
                                        }
                                    } else {
                                        if insn & 0x40000000 == 0 {
                                            if insn & 0x80000000 == 0 {
                                                if insn & 0x000010 == 0 {
                                                    if insn & 0xff20e010 == 0x2400e000 {
                                                        return Some (CMPLO_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                    }
                                                } else {
                                                    if insn & 0xff20e010 == 0x2400e010 {
                                                        return Some (CMPLS_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                    }
                                                }
                                            } else {
                                                if insn & 0x100000 == 0 {
                                                    if insn & 0x400000 == 0 {
                                                        if insn & 0x800000 == 0 {
                                                            if insn & 0xfff0e000 == 0xa400e000 {
                                                                return Some (LDNT1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xfff0e000 == 0xa480e000 {
                                                                return Some (LDNT1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x800000 == 0 {
                                                            if insn & 0xfff0e000 == 0xa440e000 {
                                                                return Some (LD3B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x3xVL :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xfff0e000 == 0xa4c0e000 {
                                                                return Some (LD3H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x3xVL :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0xfff0e000 == 0xa490e000 {
                                                        return Some (LD2Q_SME_Zt2_SVE_Pg3_SVE_ADDR_RI_S4x2xVL :: make_opcode (insn)) ;
                                                    }
                                                }
                                            }
                                        } else {
                                            if insn & 0x100000 == 0 {
                                                if insn & 0x400000 == 0 {
                                                    if insn & 0xfff0e000 == 0xe400e000 {
                                                        return Some (ST1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL :: make_opcode (insn)) ;
                                                    }
                                                } else {
                                                    if insn & 0x800000 == 0 {
                                                        if insn & 0xfff0e000 == 0xe440e000 {
                                                            return Some (ST1B_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_RI_S4xVL :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xfff0e000 == 0xe4c0e000 {
                                                            return Some (ST1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0x400000 == 0 {
                                                    if insn & 0x800000 == 0 {
                                                        if insn & 0xfff0e000 == 0xe410e000 {
                                                            return Some (STNT1B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xfff0e000 == 0xe490e000 {
                                                            return Some (STNT1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x800000 == 0 {
                                                        if insn & 0xfff0e000 == 0xe450e000 {
                                                            return Some (ST3B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x3xVL :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xfff0e000 == 0xe4d0e000 {
                                                            return Some (ST3H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x3xVL :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                }
                                            }
                                        }
                                    }
                                }
                            }
                        } else {
                            if insn & 0x002000 == 0 {
                                if insn & 0x40000000 == 0 {
                                    if insn & 0x80000000 == 0 {
                                        if insn & 0x000010 == 0 {
                                            if insn & 0xff202010 == 0x24200000 {
                                                return Some (CMPHS_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_UIMM7 :: make_opcode (insn)) ;
                                            }
                                        } else {
                                            if insn & 0xff202010 == 0x24200010 {
                                                return Some (CMPHI_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_UIMM7 :: make_opcode (insn)) ;
                                            }
                                        }
                                    } else {
                                        if insn & 0x004000 == 0 {
                                            if insn & 0x800000 == 0 {
                                                if insn & 0xffe0e000 == 0xa4200000 {
                                                    return Some (LD1ROB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX :: make_opcode (insn)) ;
                                                }
                                            } else {
                                                if insn & 0xffe0e000 == 0xa4a00000 {
                                                    return Some (LD1ROH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1 :: make_opcode (insn)) ;
                                                }
                                            }
                                        } else {
                                            if insn & 0x008000 == 0 {
                                                if insn & 0x400000 == 0 {
                                                    if insn & 0x800000 == 0 {
                                                        if insn & 0xffe0e000 == 0xa4204000 {
                                                            return Some (LD1B_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RX :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xffe0e000 == 0xa4a04000 {
                                                            return Some (LD1H_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RX_LSL1 :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x800000 == 0 {
                                                        if insn & 0xffe0e000 == 0xa4604000 {
                                                            return Some (LD1B_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RX :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xffe0e000 == 0xa4e04000 {
                                                            return Some (LD1H_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RX_LSL1 :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0x400000 == 0 {
                                                    if insn & 0x800000 == 0 {
                                                        if insn & 0xffe0e000 == 0xa420c000 {
                                                            return Some (LD2B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xffe0e000 == 0xa4a0c000 {
                                                            return Some (LD2H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1 :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x800000 == 0 {
                                                        if insn & 0xffe0e000 == 0xa460c000 {
                                                            return Some (LD4B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xffe0e000 == 0xa4e0c000 {
                                                            return Some (LD4H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1 :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                }
                                            }
                                        }
                                    }
                                } else {
                                    if insn & 0x008000 == 0 {
                                        if insn & 0x004000 == 0 {
                                            if insn & 0x800000 == 0 {
                                                if insn & 0x80000000 == 0 {
                                                    if insn & 0x000400 == 0 {
                                                        if insn & 0x000800 == 0 {
                                                            if insn & 0xffa0fc00 == 0x64200000 {
                                                                return Some (FMLA_SVE_Zd_SVE_Zn_SVE_Zm3_22_INDEX :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xffa0fc00 == 0x64200800 {
                                                                return Some (BFMLA_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x000800 == 0 {
                                                            if insn & 0xffa0fc00 == 0x64200400 {
                                                                return Some (FMLS_SVE_Zd_SVE_Zn_SVE_Zm3_22_INDEX :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xffa0fc00 == 0x64200c00 {
                                                                return Some (BFMLS_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0xffe0e000 == 0xe4600000 {
                                                        return Some (ST2Q_SME_Zt2_SVE_Pg3_SVE_ADDR_RR_LSL4 :: make_opcode (insn)) ;
                                                    }
                                                }
                                            } else {
                                                if insn & 0x400000 == 0 {
                                                    if insn & 0x80000000 == 0 {
                                                        if insn & 0x001000 == 0 {
                                                            if insn & 0x000400 == 0 {
                                                                if insn & 0xffe0fc00 == 0x64a00000 {
                                                                    return Some (FMLA_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xffe0fc00 == 0x64a00400 {
                                                                    return Some (FMLS_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0xffe0f000 == 0x64a01000 {
                                                                return Some (FCMLA_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX_SVE_IMM_ROT2 :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0xffe0e000 == 0xe4a00000 {
                                                            return Some (ST3Q_SME_Zt3_SVE_Pg3_SVE_ADDR_RR_LSL4 :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x80000000 == 0 {
                                                        if insn & 0x001000 == 0 {
                                                            if insn & 0x000400 == 0 {
                                                                if insn & 0xffe0fc00 == 0x64e00000 {
                                                                    return Some (FMLA_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xffe0fc00 == 0x64e00400 {
                                                                    return Some (FMLS_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0xffe0f000 == 0x64e01000 {
                                                                return Some (FCMLA_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX_SVE_IMM_ROT2 :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0xffe0e000 == 0xe4e00000 {
                                                            return Some (ST4Q_SME_Zt4_SVE_Pg3_SVE_ADDR_RR_LSL4 :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                }
                                            }
                                        } else {
                                            if insn & 0x400000 == 0 {
                                                if insn & 0x800000 == 0 {
                                                    if insn & 0x80000000 == 0 {
                                                        if insn & 0xffe0fc00 == 0x64204000 {
                                                            return Some (FDOT_SVE_Zd_SVE_Zn_SVE_Zm3_19_INDEX :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xffe0e000 == 0xe4204000 {
                                                            return Some (ST1B_SVE_ZtxN_S_H_SVE_Pg3_SVE_ADDR_RX :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x80000000 == 0 {
                                                        if insn & 0x000400 == 0 {
                                                            if insn & 0xffe0f400 == 0x64a04000 {
                                                                return Some (FMLALB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xffe0f400 == 0x64a04400 {
                                                                return Some (FMLALT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0xffe0e000 == 0xe4a04000 {
                                                            return Some (ST1H_SVE_ZtxN_S_H_SVE_Pg3_SVE_ADDR_RX_LSL1 :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0x800000 == 0 {
                                                    if insn & 0x80000000 == 0 {
                                                        if insn & 0xffe0fc00 == 0x64604000 {
                                                            return Some (BFDOT_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xffe0e000 == 0xe4604000 {
                                                            return Some (ST1B_SVE_ZtxN_S_D_SVE_Pg3_SVE_ADDR_RX :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x80000000 == 0 {
                                                        if insn & 0x000400 == 0 {
                                                            if insn & 0xffe0f400 == 0x64e04000 {
                                                                return Some (BFMLALB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xffe0f400 == 0x64e04400 {
                                                                return Some (BFMLALT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0xffe0e000 == 0xe4e04000 {
                                                            return Some (ST1H_SVE_ZtxN_S_D_SVE_Pg3_SVE_ADDR_RX_LSL1 :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                }
                                            }
                                        }
                                    } else {
                                        if insn & 0x400000 == 0 {
                                            if insn & 0x800000 == 0 {
                                                if insn & 0xffe0fc00 == 0x64208000 {
                                                    return Some(
                                                        FDOT_SVE_Zd_SVE_Zn_SVE_Zm_16::make_opcode(
                                                            insn,
                                                        ),
                                                    );
                                                }
                                            } else {
                                                if insn & 0x80000000 == 0 {
                                                    if insn & 0x000400 == 0 {
                                                        if insn & 0xffe0fc00 == 0x64a08000 {
                                                            return Some (FMLALB_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xffe0fc00 == 0x64a08400 {
                                                            return Some (FMLALT_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0xffe0a000 == 0xe4a08000 {
                                                        return Some (ST1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW1_14 :: make_opcode (insn)) ;
                                                    }
                                                }
                                            }
                                        } else {
                                            if insn & 0x800000 == 0 {
                                                if insn & 0xffe0fc00 == 0x64608000 {
                                                    return Some(
                                                        BFDOT_SVE_Zd_SVE_Zn_SVE_Zm_16::make_opcode(
                                                            insn,
                                                        ),
                                                    );
                                                }
                                            } else {
                                                if insn & 0x80000000 == 0 {
                                                    if insn & 0x000400 == 0 {
                                                        if insn & 0xffe0fc00 == 0x64e08000 {
                                                            return Some (BFMLALB_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xffe0fc00 == 0x64e08400 {
                                                            return Some (BFMLALT_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0xffe0a000 == 0xe4e08000 {
                                                        return Some (ST1H_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_RZ_XTW1_14 :: make_opcode (insn)) ;
                                                    }
                                                }
                                            }
                                        }
                                    }
                                }
                            } else {
                                if insn & 0x40000000 == 0 {
                                    if insn & 0x80000000 == 0 {
                                        if insn & 0x000010 == 0 {
                                            if insn & 0xff202010 == 0x24202000 {
                                                return Some (CMPLO_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_UIMM7 :: make_opcode (insn)) ;
                                            }
                                        } else {
                                            if insn & 0xff202010 == 0x24202010 {
                                                return Some (CMPLS_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_UIMM7 :: make_opcode (insn)) ;
                                            }
                                        }
                                    } else {
                                        if insn & 0x004000 == 0 {
                                            if insn & 0x008000 == 0 {
                                                if insn & 0x800000 == 0 {
                                                    if insn & 0xfff0e000 == 0xa4202000 {
                                                        return Some (LD1ROB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x32 :: make_opcode (insn)) ;
                                                    }
                                                } else {
                                                    if insn & 0xfff0e000 == 0xa4a02000 {
                                                        return Some (LD1ROH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x32 :: make_opcode (insn)) ;
                                                    }
                                                }
                                            } else {
                                                if insn & 0x100000 == 0 {
                                                    if insn & 0x400000 == 0 {
                                                        if insn & 0x800000 == 0 {
                                                            if insn & 0xfff0e000 == 0xa420a000 {
                                                                return Some (LD1B_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xfff0e000 == 0xa4a0a000 {
                                                                return Some (LD1H_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x800000 == 0 {
                                                            if insn & 0xfff0e000 == 0xa460a000 {
                                                                return Some (LD1B_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xfff0e000 == 0xa4e0a000 {
                                                                return Some (LD1H_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x400000 == 0 {
                                                        if insn & 0x800000 == 0 {
                                                            if insn & 0xfff0e000 == 0xa430a000 {
                                                                return Some (LDNF1B_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xfff0e000 == 0xa4b0a000 {
                                                                return Some (LDNF1H_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x800000 == 0 {
                                                            if insn & 0xfff0e000 == 0xa470a000 {
                                                                return Some (LDNF1B_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xfff0e000 == 0xa4f0a000 {
                                                                return Some (LDNF1H_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    }
                                                }
                                            }
                                        } else {
                                            if insn & 0x008000 == 0 {
                                                if insn & 0x400000 == 0 {
                                                    if insn & 0x800000 == 0 {
                                                        if insn & 0xffe0e000 == 0xa4206000 {
                                                            return Some (LDFF1B_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_R :: make_opcode (insn)) ;
                                                        }
                                                        if insn & 0xffe0e000 == 0xa4206000 {
                                                            return Some (LDFF1B_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_R :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xffe0e000 == 0xa4a06000 {
                                                            return Some (LDFF1H_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_R :: make_opcode (insn)) ;
                                                        }
                                                        if insn & 0xffe0e000 == 0xa4a06000 {
                                                            return Some (LDFF1H_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_R :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x800000 == 0 {
                                                        if insn & 0xffe0e000 == 0xa4606000 {
                                                            return Some (LDFF1B_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_R :: make_opcode (insn)) ;
                                                        }
                                                        if insn & 0xffe0e000 == 0xa4606000 {
                                                            return Some (LDFF1B_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_R :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xffe0e000 == 0xa4e06000 {
                                                            return Some (LDFF1H_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_R :: make_opcode (insn)) ;
                                                        }
                                                        if insn & 0xffe0e000 == 0xa4e06000 {
                                                            return Some (LDFF1H_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_R :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0x400000 == 0 {
                                                    if insn & 0x800000 == 0 {
                                                        if insn & 0xfff0e000 == 0xa420e000 {
                                                            return Some (LD2B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x2xVL :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xfff0e000 == 0xa4a0e000 {
                                                            return Some (LD2H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x2xVL :: make_opcode (insn)) ;
                                                        }
                                                        if insn & 0xffe0e000 == 0xa4a0e000 {
                                                            return Some (LD2Q_SME_Zt2_SVE_Pg3_SVE_ADDR_RR_LSL4 :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x800000 == 0 {
                                                        if insn & 0xfff0e000 == 0xa460e000 {
                                                            return Some (LD4B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x4xVL :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xfff0e000 == 0xa4e0e000 {
                                                            return Some (LD4H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x4xVL :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                }
                                            }
                                        }
                                    }
                                } else {
                                    if insn & 0x004000 == 0 {
                                        if insn & 0x008000 == 0 {
                                            if insn & 0x80000000 == 0 {
                                                if insn & 0x000400 == 0 {
                                                    if insn & 0x000800 == 0 {
                                                        if insn & 0x800000 == 0 {
                                                            if insn & 0xffa0fc00 == 0x64202000 {
                                                                return Some (FMUL_SVE_Zd_SVE_Zn_SVE_Zm3_22_INDEX :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0x400000 == 0 {
                                                                if insn & 0xffe0fc00 == 0x64a02000 {
                                                                    return Some (FMUL_SVE_Zd_SVE_Zn_SVE_Zm3_INDEX :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xffe0fc00 == 0x64e02000 {
                                                                    return Some (FMUL_SVE_Zd_SVE_Zn_SVE_Zm4_INDEX :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0xffa0fc00 == 0x64202800 {
                                                            return Some (BFMUL_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0xffe0fc00 == 0x64202400 {
                                                        return Some (BFCLAMP_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                    }
                                                    if insn & 0xff20fc00 == 0x64202400 {
                                                        return Some (FCLAMP_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                    }
                                                }
                                            } else {
                                                if insn & 0xffe0e000 == 0xe4202000 {
                                                    return Some (ST1Q_SVE_Zt_SVE_Pg3_SVE_ADDR_ZX :: make_opcode (insn)) ;
                                                }
                                            }
                                        } else {
                                            if insn & 0x400000 == 0 {
                                                if insn & 0x80000000 == 0 {
                                                    if insn & 0x000400 == 0 {
                                                        if insn & 0xffe0fc00 == 0x64a0a000 {
                                                            return Some (FMLSLB_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xffe0fc00 == 0x64a0a400 {
                                                            return Some (FMLSLT_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0xffe0e000 == 0xe4a0a000 {
                                                        return Some (ST1H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL1 :: make_opcode (insn)) ;
                                                    }
                                                }
                                            } else {
                                                if insn & 0x800000 == 0 {
                                                    if insn & 0xffe0e000 == 0xe460a000 {
                                                        return Some (ST1B_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_ZI_U5 :: make_opcode (insn)) ;
                                                    }
                                                } else {
                                                    if insn & 0x80000000 == 0 {
                                                        if insn & 0x000400 == 0 {
                                                            if insn & 0xffe0fc00 == 0x64e0a000 {
                                                                return Some (BFMLSLB_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xffe0fc00 == 0x64e0a400 {
                                                                return Some (BFMLSLT_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0xffe0e000 == 0xe4e0a000 {
                                                            return Some (ST1H_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_ZI_U5x2 :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                }
                                            }
                                        }
                                    } else {
                                        if insn & 0x008000 == 0 {
                                            if insn & 0x400000 == 0 {
                                                if insn & 0x800000 == 0 {
                                                    if insn & 0xffe0e000 == 0xe4206000 {
                                                        return Some (ST2B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX :: make_opcode (insn)) ;
                                                    }
                                                } else {
                                                    if insn & 0x80000000 == 0 {
                                                        if insn & 0x000400 == 0 {
                                                            if insn & 0xffe0f400 == 0x64a06000 {
                                                                return Some (FMLSLB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xffe0f400 == 0x64a06400 {
                                                                return Some (FMLSLT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0xffe0e000 == 0xe4a06000 {
                                                            return Some (ST2H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1 :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0x800000 == 0 {
                                                    if insn & 0xffe0e000 == 0xe4606000 {
                                                        return Some (ST4B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX :: make_opcode (insn)) ;
                                                    }
                                                } else {
                                                    if insn & 0x80000000 == 0 {
                                                        if insn & 0x000400 == 0 {
                                                            if insn & 0xffe0f400 == 0x64e06000 {
                                                                return Some (BFMLSLB_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xffe0f400 == 0x64e06400 {
                                                                return Some (BFMLSLT_SVE_Zd_SVE_Zn_SVE_Zm3_11_INDEX :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0xffe0e000 == 0xe4e06000 {
                                                            return Some (ST4H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1 :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                }
                                            }
                                        } else {
                                            if insn & 0x400000 == 0 {
                                                if insn & 0x800000 == 0 {
                                                    if insn & 0x100000 == 0 {
                                                        if insn & 0xfff0e000 == 0xe420e000 {
                                                            return Some (ST1B_SVE_ZtxN_S_H_SVE_Pg3_SVE_ADDR_RI_S4xVL :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xfff0e000 == 0xe430e000 {
                                                            return Some (ST2B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x2xVL :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x80000000 == 0 {
                                                        if insn & 0xffe0fc00 == 0x64a0e400 {
                                                            return Some (FMMLA_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0x100000 == 0 {
                                                            if insn & 0xfff0e000 == 0xe4a0e000 {
                                                                return Some (ST1H_SVE_ZtxN_S_H_SVE_Pg3_SVE_ADDR_RI_S4xVL :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xfff0e000 == 0xe4b0e000 {
                                                                return Some (ST2H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x2xVL :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0x800000 == 0 {
                                                    if insn & 0x80000000 == 0 {
                                                        if insn & 0xffe0fc00 == 0x6460e400 {
                                                            return Some (BFMMLA_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0x100000 == 0 {
                                                            if insn & 0xfff0e000 == 0xe460e000 {
                                                                return Some (ST1B_SVE_ZtxN_S_D_SVE_Pg3_SVE_ADDR_RI_S4xVL :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xfff0e000 == 0xe470e000 {
                                                                return Some (ST4B_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x4xVL :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x80000000 == 0 {
                                                        if insn & 0xffe0fc00 == 0x64e0e400 {
                                                            return Some (FMMLA_SVE_Zd_S_D_SVE_Zn_S_D_SVE_Zm_16_S_D :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0x100000 == 0 {
                                                            if insn & 0xfff0e000 == 0xe4e0e000 {
                                                                return Some (ST1H_SVE_ZtxN_S_D_SVE_Pg3_SVE_ADDR_RI_S4xVL :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xfff0e000 == 0xe4f0e000 {
                                                                return Some (ST4H_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x4xVL :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    }
                                                }
                                            }
                                        }
                                    }
                                }
                            }
                        }
                    }
                } else {
                    if insn & 0x20000000 == 0 {
                        if insn & 0x40000000 == 0 {
                            if insn & 0x80000000 == 0 {
                                if insn & 0x200000 == 0 {
                                    if insn & 0x100000 == 0 {
                                        if insn & 0x400000 == 0 {
                                            if insn & 0x800000 == 0 {
                                                if insn & 0xfffc0000 == 0x5000000 {
                                                    return Some(
                                                        ORR_SVE_Zd_SVE_Zd_SVE_LIMM::make_opcode(
                                                            insn,
                                                        ),
                                                    );
                                                }
                                            } else {
                                                if insn & 0xfffc0000 == 0x5800000 {
                                                    return Some(
                                                        AND_SVE_Zd_SVE_Zd_SVE_LIMM::make_opcode(
                                                            insn,
                                                        ),
                                                    );
                                                }
                                            }
                                        } else {
                                            if insn & 0x800000 == 0 {
                                                if insn & 0xfffc0000 == 0x5400000 {
                                                    return Some(
                                                        EOR_SVE_Zd_SVE_Zd_SVE_LIMM::make_opcode(
                                                            insn,
                                                        ),
                                                    );
                                                }
                                            } else {
                                                if insn & 0xfffc0000 == 0x5c00000 {
                                                    return Some(
                                                        DUPM_SVE_Zd_SVE_LIMM::make_opcode(insn),
                                                    );
                                                }
                                            }
                                        }
                                    } else {
                                        if insn & 0x008000 == 0 {
                                            if insn & 0xff308000 == 0x5100000 {
                                                return Some(
                                                    CPY_SVE_Zd_SVE_Pg4_16_SVE_ASIMM::make_opcode(
                                                        insn,
                                                    ),
                                                );
                                            }
                                        } else {
                                            if insn & 0xff30e000 == 0x510c000 {
                                                return Some(
                                                    FCPY_SVE_Zd_SVE_Pg4_16_SVE_FPIMM8::make_opcode(
                                                        insn,
                                                    ),
                                                );
                                            }
                                        }
                                    }
                                } else {
                                    if insn & 0x004000 == 0 {
                                        if insn & 0x002000 == 0 {
                                            if insn & 0x008000 == 0 {
                                                if insn & 0x400000 == 0 {
                                                    if insn & 0x800000 == 0 {
                                                        if insn & 0xffe0e000 == 0x5200000 {
                                                            return Some (EXT_SVE_Zd_SVE_Zd_SVE_Zm_5_SVE_UIMM8_53 :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0x000400 == 0 {
                                                            if insn & 0x000800 == 0 {
                                                                if insn & 0xffe0fc00 == 0x5a00000 {
                                                                    return Some (ZIP1_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0x001000 == 0 {
                                                                    if insn & 0xffe0fc00
                                                                        == 0x5a00800
                                                                    {
                                                                        return Some (UZP1_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xffe0fc00
                                                                        == 0x5a01800
                                                                    {
                                                                        return Some (TRN1_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x000800 == 0 {
                                                                if insn & 0xffe0fc00 == 0x5a00400 {
                                                                    return Some (ZIP2_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0x001000 == 0 {
                                                                    if insn & 0xffe0fc00
                                                                        == 0x5a00c00
                                                                    {
                                                                        return Some (UZP2_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xffe0fc00
                                                                        == 0x5a01c00
                                                                    {
                                                                        return Some (TRN2_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            }
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0xffe0e000 == 0x5600000 {
                                                        return Some (EXT_SVE_Zd_SVE_ZnxN_SVE_UIMM8_53 :: make_opcode (insn)) ;
                                                    }
                                                }
                                            } else {
                                                if insn & 0x010000 == 0 {
                                                    if insn & 0x020000 == 0 {
                                                        if insn & 0x040000 == 0 {
                                                            if insn & 0x080000 == 0 {
                                                                if insn & 0xff3fe000 == 0x5208000 {
                                                                    return Some (CPY_SVE_Zd_SVE_Pg3_SVE_Vn :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xff3fe000 == 0x5288000 {
                                                                    return Some (CLASTA_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x080000 == 0 {
                                                                if insn & 0xff3fe000 == 0x5248000 {
                                                                    return Some (REVB_SVE_Zd_SVE_Pg3_SVE_Zn :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xff3fe000 == 0x52c8000 {
                                                                    return Some (SPLICE_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x040000 == 0 {
                                                            if insn & 0x080000 == 0 {
                                                                if insn & 0xff3fe000 == 0x5228000 {
                                                                    return Some (LASTA_SVE_Vd_SVE_Pg3_SVE_Zn :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xff3fe000 == 0x52a8000 {
                                                                    return Some (CLASTA_SVE_Vd_SVE_Pg3_SVE_Vd_SVE_Zm_5 :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x080000 == 0 {
                                                                if insn & 0xffffe000 == 0x5e68000 {
                                                                    return Some (REVW_SVE_Zd_SVE_Pg3_SVE_Zn :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xffffe000 == 0x52e8000 {
                                                                    return Some (REVD_SVE_Zd_SVE_Pg3_SVE_Zn :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x020000 == 0 {
                                                        if insn & 0x040000 == 0 {
                                                            if insn & 0x080000 == 0 {
                                                                if insn & 0xffbfe000 == 0x5a18000 {
                                                                    return Some (COMPACT_SVE_Zd_SVE_Pg3_SVE_Zn :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xff3fe000 == 0x5298000 {
                                                                    return Some (CLASTB_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x080000 == 0 {
                                                                if insn & 0xffbfe000 == 0x5a58000 {
                                                                    return Some (REVH_SVE_Zd_SVE_Pg3_SVE_Zn :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xff3fe000 == 0x52d8000 {
                                                                    return Some (SPLICE_SVE_Zd_SVE_Pg3_SVE_ZnxN :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x040000 == 0 {
                                                            if insn & 0x080000 == 0 {
                                                                if insn & 0xff3fe000 == 0x5238000 {
                                                                    return Some (LASTB_SVE_Vd_SVE_Pg3_SVE_Zn :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xff3fe000 == 0x52b8000 {
                                                                    return Some (CLASTB_SVE_Vd_SVE_Pg3_SVE_Vd_SVE_Zm_5 :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0xff3fe000 == 0x5278000 {
                                                                return Some (RBIT_SVE_Zd_SVE_Pg3_SVE_Zn :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    }
                                                }
                                            }
                                        } else {
                                            if insn & 0x008000 == 0 {
                                                if insn & 0x000400 == 0 {
                                                    if insn & 0x000800 == 0 {
                                                        if insn & 0x001000 == 0 {
                                                            if insn & 0xff20fc00 == 0x5202000 {
                                                                return Some (DUP_SVE_Zd_SVE_Zn_INDEX :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xff20fc00 == 0x5203000 {
                                                                return Some (TBL_SVE_Zd_SVE_ZnxN_SVE_Zm_16 :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x001000 == 0 {
                                                            if insn & 0xff20fc00 == 0x5202800 {
                                                                return Some (TBL_SVE_Zd_S_B_SVE_ZnxN_S_B_SVE_Zm_16_S_B :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0x010000 == 0 {
                                                                if insn & 0x020000 == 0 {
                                                                    if insn & 0x040000 == 0 {
                                                                        if insn & 0x080000 == 0 {
                                                                            if insn & 0x100000 == 0
                                                                            {
                                                                                if insn & 0xff3ffc00
                                                                                    == 0x5203800
                                                                                {
                                                                                    return Some (DUP_SVE_Zd_Rn_SP :: make_opcode (insn)) ;
                                                                                }
                                                                            } else {
                                                                                if insn & 0xff3ffc00
                                                                                    == 0x5303800
                                                                                {
                                                                                    return Some (SUNPKLO_SVE_Zd_SVE_Zn :: make_opcode (insn)) ;
                                                                                }
                                                                            }
                                                                        } else {
                                                                            if insn & 0xff3ffc00
                                                                                == 0x5383800
                                                                            {
                                                                                return Some (REV_SVE_Zd_SVE_Zn :: make_opcode (insn)) ;
                                                                            }
                                                                        }
                                                                    } else {
                                                                        if insn & 0x100000 == 0 {
                                                                            if insn & 0xff3ffc00
                                                                                == 0x5243800
                                                                            {
                                                                                return Some (INSR_SVE_Zd_SVE_Rm :: make_opcode (insn)) ;
                                                                            }
                                                                        } else {
                                                                            if insn & 0xff3ffc00
                                                                                == 0x5343800
                                                                            {
                                                                                return Some (INSR_SVE_Zd_SVE_Vm :: make_opcode (insn)) ;
                                                                            }
                                                                        }
                                                                    }
                                                                } else {
                                                                    if insn & 0xff3ffc00
                                                                        == 0x5323800
                                                                    {
                                                                        return Some (UUNPKLO_SVE_Zd_SVE_Zn :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0x020000 == 0 {
                                                                    if insn & 0xff3ffc00
                                                                        == 0x5313800
                                                                    {
                                                                        return Some (SUNPKHI_SVE_Zd_SVE_Zn :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xff3ffc00
                                                                        == 0x5333800
                                                                    {
                                                                        return Some (UUNPKHI_SVE_Zd_SVE_Zn :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            }
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x000800 == 0 {
                                                        if insn & 0x400000 == 0 {
                                                            if insn & 0xffe0fc00 == 0x5202400 {
                                                                return Some (DUPQ_SVE_Zd_SVE_Zn_5_INDEX :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xfff0fc00 == 0x5602400 {
                                                                return Some (EXTQ_SVE_Zd_SVE_Zd_SVE_Zm_imm4 :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0xff20fc00 == 0x5202c00 {
                                                            return Some (TBX_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0x010000 == 0 {
                                                    if insn & 0x080000 == 0 {
                                                        if insn & 0x100000 == 0 {
                                                            if insn & 0xff3fe000 == 0x520a000 {
                                                                return Some (LASTA_Rd_SVE_Pg3_SVE_Zn :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xff3fe000 == 0x530a000 {
                                                                return Some (CLASTA_Rd_SVE_Pg3_Rd_SVE_Zm_5 :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0xff3fe000 == 0x528a000 {
                                                            return Some (CPY_SVE_Zd_SVE_Pg3_Rn_SP :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x100000 == 0 {
                                                        if insn & 0xff3fe000 == 0x521a000 {
                                                            return Some (LASTB_Rd_SVE_Pg3_SVE_Zn :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xff3fe000 == 0x531a000 {
                                                            return Some (CLASTB_Rd_SVE_Pg3_Rd_SVE_Zm_5 :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                }
                                            }
                                        }
                                    } else {
                                        if insn & 0x008000 == 0 {
                                            if insn & 0x000400 == 0 {
                                                if insn & 0x000800 == 0 {
                                                    if insn & 0x001000 == 0 {
                                                        if insn & 0x002000 == 0 {
                                                            if insn & 0x100000 == 0 {
                                                                if insn & 0xff30fe10 == 0x5204000 {
                                                                    return Some (ZIP1_SVE_Pd_SVE_Pn_SVE_Pm :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0x010000 == 0 {
                                                                    if insn & 0x040000 == 0 {
                                                                        if insn & 0xfffffe10
                                                                            == 0x5304000
                                                                        {
                                                                            return Some (PUNPKLO_SVE_Pd_SVE_Pn :: make_opcode (insn)) ;
                                                                        }
                                                                    } else {
                                                                        if insn & 0xff3ffe10
                                                                            == 0x5344000
                                                                        {
                                                                            return Some (REV_SVE_Pd_SVE_Pn :: make_opcode (insn)) ;
                                                                        }
                                                                    }
                                                                } else {
                                                                    if insn & 0xfffffe10
                                                                        == 0x5314000
                                                                    {
                                                                        return Some (PUNPKHI_SVE_Pd_SVE_Pn :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0xff20fc00 == 0x5206000 {
                                                                return Some (ZIP1_SVE_Zd_S_B_SVE_Zn_S_B_SVE_Zm_16_S_B :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x002000 == 0 {
                                                            if insn & 0xff30fe10 == 0x5205000 {
                                                                return Some (TRN1_SVE_Pd_SVE_Pn_SVE_Pm :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xff20fc00 == 0x5207000 {
                                                                return Some (TRN1_SVE_Zd_S_B_SVE_Zn_S_B_SVE_Zm_16_S_B :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x002000 == 0 {
                                                        if insn & 0xff30fe10 == 0x5204800 {
                                                            return Some (UZP1_SVE_Pd_SVE_Pn_SVE_Pm :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xff20fc00 == 0x5206800 {
                                                            return Some (UZP1_SVE_Zd_S_B_SVE_Zn_S_B_SVE_Zm_16_S_B :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0x000800 == 0 {
                                                    if insn & 0x001000 == 0 {
                                                        if insn & 0x002000 == 0 {
                                                            if insn & 0xff30fe10 == 0x5204400 {
                                                                return Some (ZIP2_SVE_Pd_SVE_Pn_SVE_Pm :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xff20fc00 == 0x5206400 {
                                                                return Some (ZIP2_SVE_Zd_S_B_SVE_Zn_S_B_SVE_Zm_16_S_B :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x002000 == 0 {
                                                            if insn & 0xff30fe10 == 0x5205400 {
                                                                return Some (TRN2_SVE_Pd_SVE_Pn_SVE_Pm :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xff20fc00 == 0x5207400 {
                                                                return Some (TRN2_SVE_Zd_S_B_SVE_Zn_S_B_SVE_Zm_16_S_B :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x002000 == 0 {
                                                        if insn & 0xff30fe10 == 0x5204c00 {
                                                            return Some (UZP2_SVE_Pd_SVE_Pn_SVE_Pm :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xff20fc00 == 0x5206c00 {
                                                            return Some (UZP2_SVE_Zd_S_B_SVE_Zn_S_B_SVE_Zm_16_S_B :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                }
                                            }
                                        } else {
                                            if insn & 0xff20c000 == 0x520c000 {
                                                return Some (SEL_SVE_Zd_SVE_Pg4_10_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                            }
                                        }
                                    }
                                }
                            } else {
                                if insn & 0x002000 == 0 {
                                    if insn & 0x004000 == 0 {
                                        if insn & 0x008000 == 0 {
                                            if insn & 0x400000 == 0 {
                                                if insn & 0xffc0e010 == 0x85800000 {
                                                    return Some(
                                                        LDR_SVE_PNt_SVE_ADDR_RI_S9xVL::make_opcode(
                                                            insn,
                                                        ),
                                                    );
                                                }
                                                if insn & 0xffc0e010 == 0x85800000 {
                                                    return Some(
                                                        LDR_SVE_PNt_SVE_ADDR_RI_S9xVL::make_opcode(
                                                            insn,
                                                        ),
                                                    );
                                                }
                                            } else {
                                                if insn & 0xffc0e010 == 0x85c00000 {
                                                    return Some (PRFB_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RI_S6xVL :: make_opcode (insn)) ;
                                                }
                                            }
                                        } else {
                                            if insn & 0x800000 == 0 {
                                                if insn & 0xffc0e000 == 0x85408000 {
                                                    return Some (LD1RSH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_U6x2 :: make_opcode (insn)) ;
                                                }
                                            } else {
                                                if insn & 0xffc0e000 == 0x85c08000 {
                                                    return Some (LD1RSB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_U6 :: make_opcode (insn)) ;
                                                }
                                            }
                                        }
                                    } else {
                                        if insn & 0x008000 == 0 {
                                            if insn & 0x800000 == 0 {
                                                if insn & 0x200000 == 0 {
                                                    if insn & 0xffa0e000 == 0x85004000 {
                                                        return Some (LD1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22 :: make_opcode (insn)) ;
                                                    }
                                                } else {
                                                    if insn & 0xffa0e000 == 0x85204000 {
                                                        return Some (LD1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW2_22 :: make_opcode (insn)) ;
                                                    }
                                                }
                                            } else {
                                                if insn & 0x400000 == 0 {
                                                    if insn & 0xffc0e000 == 0x85804000 {
                                                        return Some (LDR_SVE_Zt_SVE_ADDR_RI_S9xVL :: make_opcode (insn)) ;
                                                    }
                                                } else {
                                                    if insn & 0xffc0e010 == 0x85c04000 {
                                                        return Some (PRFW_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RI_S6xVL :: make_opcode (insn)) ;
                                                    }
                                                }
                                            }
                                        } else {
                                            if insn & 0x400000 == 0 {
                                                if insn & 0x200000 == 0 {
                                                    if insn & 0x800000 == 0 {
                                                        if insn & 0xffe0e010 == 0x8500c000 {
                                                            return Some (PRFW_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RX_LSL2 :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xffe0e010 == 0x8580c000 {
                                                            return Some (PRFD_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RX_LSL3 :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0xffe0e000 == 0x8520c000 {
                                                        return Some (LD1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x4 :: make_opcode (insn)) ;
                                                    }
                                                }
                                            } else {
                                                if insn & 0x800000 == 0 {
                                                    if insn & 0xffc0e000 == 0x8540c000 {
                                                        return Some (LD1RW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_U6x4 :: make_opcode (insn)) ;
                                                    }
                                                } else {
                                                    if insn & 0xffc0e000 == 0x85c0c000 {
                                                        return Some (LD1RSB_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RI_U6 :: make_opcode (insn)) ;
                                                    }
                                                }
                                            }
                                        }
                                    }
                                } else {
                                    if insn & 0x004000 == 0 {
                                        if insn & 0x008000 == 0 {
                                            if insn & 0xffc0e010 == 0x85c02000 {
                                                return Some (PRFH_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RI_S6xVL :: make_opcode (insn)) ;
                                            }
                                        } else {
                                            if insn & 0x400000 == 0 {
                                                if insn & 0xffe0e000 == 0x8500a000 {
                                                    return Some (LDNT1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZX :: make_opcode (insn)) ;
                                                }
                                            } else {
                                                if insn & 0x800000 == 0 {
                                                    if insn & 0xffc0e000 == 0x8540a000 {
                                                        return Some (LD1RSH_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RI_U6x2 :: make_opcode (insn)) ;
                                                    }
                                                } else {
                                                    if insn & 0xffc0e000 == 0x85c0a000 {
                                                        return Some (LD1RSB_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RI_U6 :: make_opcode (insn)) ;
                                                    }
                                                }
                                            }
                                        }
                                    } else {
                                        if insn & 0x008000 == 0 {
                                            if insn & 0x800000 == 0 {
                                                if insn & 0x200000 == 0 {
                                                    if insn & 0xffa0e000 == 0x85006000 {
                                                        return Some (LDFF1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22 :: make_opcode (insn)) ;
                                                    }
                                                } else {
                                                    if insn & 0xffa0e000 == 0x85206000 {
                                                        return Some (LDFF1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW2_22 :: make_opcode (insn)) ;
                                                    }
                                                }
                                            } else {
                                                if insn & 0xffc0e010 == 0x85c06000 {
                                                    return Some (PRFD_SVE_PRFOP_SVE_Pg3_SVE_ADDR_RI_S6xVL :: make_opcode (insn)) ;
                                                }
                                            }
                                        } else {
                                            if insn & 0x400000 == 0 {
                                                if insn & 0x200000 == 0 {
                                                    if insn & 0x800000 == 0 {
                                                        if insn & 0xffe0e010 == 0x8500e000 {
                                                            return Some (PRFW_SVE_PRFOP_SVE_Pg3_SVE_ADDR_ZI_U5x4 :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xffe0e010 == 0x8580e000 {
                                                            return Some (PRFD_SVE_PRFOP_SVE_Pg3_SVE_ADDR_ZI_U5x8 :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0xffe0e000 == 0x8520e000 {
                                                        return Some (LDFF1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x4 :: make_opcode (insn)) ;
                                                    }
                                                }
                                            } else {
                                                if insn & 0x800000 == 0 {
                                                    if insn & 0xffc0e000 == 0x8540e000 {
                                                        return Some (LD1RW_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RI_U6x4 :: make_opcode (insn)) ;
                                                    }
                                                } else {
                                                    if insn & 0xffc0e000 == 0x85c0e000 {
                                                        return Some (LD1RD_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_U6x8 :: make_opcode (insn)) ;
                                                    }
                                                }
                                            }
                                        }
                                    }
                                }
                            }
                        } else {
                            if insn & 0x002000 == 0 {
                                if insn & 0x004000 == 0 {
                                    if insn & 0x008000 == 0 {
                                        if insn & 0x200000 == 0 {
                                            if insn & 0x80000000 == 0 {
                                                if insn & 0x000400 == 0 {
                                                    if insn & 0x000800 == 0 {
                                                        if insn & 0x001000 == 0 {
                                                            if insn & 0xff20fc00 == 0x45000000 {
                                                                return Some (SADDLB_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xff20fc00 == 0x45001000 {
                                                                return Some (SSUBLB_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x001000 == 0 {
                                                            if insn & 0xff20fc00 == 0x45000800 {
                                                                return Some (UADDLB_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xff20fc00 == 0x45001800 {
                                                                return Some (USUBLB_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x000800 == 0 {
                                                        if insn & 0x001000 == 0 {
                                                            if insn & 0xff20fc00 == 0x45000400 {
                                                                return Some (SADDLT_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xff20fc00 == 0x45001400 {
                                                                return Some (SSUBLT_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x001000 == 0 {
                                                            if insn & 0xff20fc00 == 0x45000c00 {
                                                                return Some (UADDLT_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xff20fc00 == 0x45001c00 {
                                                                return Some (USUBLT_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0xffa0e000 == 0xc5000000 {
                                                    return Some (LD1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22 :: make_opcode (insn)) ;
                                                }
                                            }
                                        } else {
                                            if insn & 0x800000 == 0 {
                                                if insn & 0x80000000 == 0 {
                                                    if insn & 0x000400 == 0 {
                                                        if insn & 0x000800 == 0 {
                                                            if insn & 0x001000 == 0 {
                                                                if insn & 0xffa0fc00 == 0x45200000 {
                                                                    return Some (SQSHRUNB_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22 :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xffa0fc00 == 0x45201000 {
                                                                    return Some (SHRNB_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22 :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x001000 == 0 {
                                                                if insn & 0xffa0fc00 == 0x45200800 {
                                                                    return Some (SQRSHRUNB_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22 :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xffa0fc00 == 0x45201800 {
                                                                    return Some (RSHRNB_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22 :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x000800 == 0 {
                                                            if insn & 0x001000 == 0 {
                                                                if insn & 0xffa0fc00 == 0x45200400 {
                                                                    return Some (SQSHRUNT_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22 :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xffa0fc00 == 0x45201400 {
                                                                    return Some (SHRNT_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22 :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x001000 == 0 {
                                                                if insn & 0xffa0fc00 == 0x45200c00 {
                                                                    return Some (SQRSHRUNT_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22 :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xffa0fc00 == 0x45201c00 {
                                                                    return Some (RSHRNT_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22 :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0xffa0e000 == 0xc5200000 {
                                                        return Some (LD1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW2_22 :: make_opcode (insn)) ;
                                                    }
                                                }
                                            } else {
                                                if insn & 0xfff0fc20 == 0x45b00800 {
                                                    return Some (SQRSHRUN_SVE_Zd_SME_Znx2_SME_SHRIMM4 :: make_opcode (insn)) ;
                                                }
                                            }
                                        }
                                    } else {
                                        if insn & 0x200000 == 0 {
                                            if insn & 0x80000000 == 0 {
                                                if insn & 0x000400 == 0 {
                                                    if insn & 0x000800 == 0 {
                                                        if insn & 0x001000 == 0 {
                                                            if insn & 0xff20fc00 == 0x45008000 {
                                                                return Some (SADDLBT_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xff20fc00 == 0x45009000 {
                                                                return Some (EORBT_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x001000 == 0 {
                                                            if insn & 0xff20fc00 == 0x45008800 {
                                                                return Some (SSUBLBT_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0x400000 == 0 {
                                                                if insn & 0x800000 == 0 {
                                                                    if insn & 0xffe0fc00
                                                                        == 0x45009800
                                                                    {
                                                                        return Some (SMMLA_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xffe0fc00
                                                                        == 0x45809800
                                                                    {
                                                                        return Some (USMMLA_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0xffe0fc00 == 0x45c09800 {
                                                                    return Some (UMMLA_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x000800 == 0 {
                                                        if insn & 0xff20fc00 == 0x45009400 {
                                                            return Some (EORTB_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xff20fc00 == 0x45008c00 {
                                                            return Some (SSUBLTB_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0x400000 == 0 {
                                                    if insn & 0xffe0e000 == 0xc5008000 {
                                                        return Some (LDNT1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZX :: make_opcode (insn)) ;
                                                    }
                                                } else {
                                                    if insn & 0xffe0e000 == 0xc5408000 {
                                                        return Some (LD1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ :: make_opcode (insn)) ;
                                                    }
                                                }
                                            }
                                        } else {
                                            if insn & 0x80000000 == 0 {
                                                if insn & 0x000010 == 0 {
                                                    if insn & 0xffa0e010 == 0x45208000 {
                                                        return Some (MATCH_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                    }
                                                } else {
                                                    if insn & 0xffa0e010 == 0x45208010 {
                                                        return Some (NMATCH_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                    }
                                                }
                                            } else {
                                                if insn & 0x400000 == 0 {
                                                    if insn & 0xffe0e000 == 0xc5208000 {
                                                        return Some (LD1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x4 :: make_opcode (insn)) ;
                                                    }
                                                } else {
                                                    if insn & 0xffe0e000 == 0xc5608000 {
                                                        return Some (LD1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL2 :: make_opcode (insn)) ;
                                                    }
                                                }
                                            }
                                        }
                                    }
                                } else {
                                    if insn & 0x008000 == 0 {
                                        if insn & 0x200000 == 0 {
                                            if insn & 0x80000000 == 0 {
                                                if insn & 0x000400 == 0 {
                                                    if insn & 0x000800 == 0 {
                                                        if insn & 0x001000 == 0 {
                                                            if insn & 0xff20fc00 == 0x45004000 {
                                                                return Some (SADDWB_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xff20fc00 == 0x45005000 {
                                                                return Some (SSUBWB_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x001000 == 0 {
                                                            if insn & 0xff20fc00 == 0x45004800 {
                                                                return Some (UADDWB_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xff20fc00 == 0x45005800 {
                                                                return Some (USUBWB_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x000800 == 0 {
                                                        if insn & 0x001000 == 0 {
                                                            if insn & 0xff20fc00 == 0x45004400 {
                                                                return Some (SADDWT_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xff20fc00 == 0x45005400 {
                                                                return Some (SSUBWT_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x001000 == 0 {
                                                            if insn & 0xff20fc00 == 0x45004c00 {
                                                                return Some (UADDWT_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xff20fc00 == 0x45005c00 {
                                                                return Some (USUBWT_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0x800000 == 0 {
                                                    if insn & 0xffa0e000 == 0xc5004000 {
                                                        return Some (LD1W_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW_22_S_D :: make_opcode (insn)) ;
                                                    }
                                                } else {
                                                    if insn & 0xffa0e000 == 0xc5804000 {
                                                        return Some (LD1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22 :: make_opcode (insn)) ;
                                                    }
                                                }
                                            }
                                        } else {
                                            if insn & 0x800000 == 0 {
                                                if insn & 0x80000000 == 0 {
                                                    if insn & 0x000400 == 0 {
                                                        if insn & 0x000800 == 0 {
                                                            if insn & 0x001000 == 0 {
                                                                if insn & 0x010000 == 0 {
                                                                    if insn & 0xffa7fc00
                                                                        == 0x45204000
                                                                    {
                                                                        return Some (SQXTNB_SVE_Zd_SVE_Zn :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xfffffc20
                                                                        == 0x45314000
                                                                    {
                                                                        return Some (SQCVTN_SVE_Zd_SME_Znx2 :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0x010000 == 0 {
                                                                    if insn & 0xffa7fc00
                                                                        == 0x45205000
                                                                    {
                                                                        return Some (SQXTUNB_SVE_Zd_SVE_Zn :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xfffffc20
                                                                        == 0x45315000
                                                                    {
                                                                        return Some (SQCVTUN_SVE_Zd_SME_Znx2 :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x010000 == 0 {
                                                                if insn & 0xffa7fc00 == 0x45204800 {
                                                                    return Some (UQXTNB_SVE_Zd_SVE_Zn :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xfffffc20 == 0x45314800 {
                                                                    return Some (UQCVTN_SVE_Zd_SME_Znx2 :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x000800 == 0 {
                                                            if insn & 0x001000 == 0 {
                                                                if insn & 0xffa7fc00 == 0x45204400 {
                                                                    return Some (SQXTNT_SVE_Zd_SVE_Zn :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xffa7fc00 == 0x45205400 {
                                                                    return Some (SQXTUNT_SVE_Zd_SVE_Zn :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0xffa7fc00 == 0x45204c00 {
                                                                return Some (UQXTNT_SVE_Zd_SVE_Zn :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0xffa0e000 == 0xc5204000 {
                                                        return Some (LD1W_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW2_22_S_D :: make_opcode (insn)) ;
                                                    }
                                                }
                                            } else {
                                                if insn & 0xffa0e000 == 0xc5a04000 {
                                                    return Some (LD1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW3_22 :: make_opcode (insn)) ;
                                                }
                                            }
                                        }
                                    } else {
                                        if insn & 0x200000 == 0 {
                                            if insn & 0x80000000 == 0 {
                                                if insn & 0x000800 == 0 {
                                                    if insn & 0x000400 == 0 {
                                                        if insn & 0x001000 == 0 {
                                                            if insn & 0xff20fc00 == 0x4500c000 {
                                                                return Some (SABALB_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0x800000 == 0 {
                                                                if insn & 0xffa0fc00 == 0x4500d000 {
                                                                    return Some (ADCLB_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xffa0fc00 == 0x4580d000 {
                                                                    return Some (SBCLB_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x001000 == 0 {
                                                            if insn & 0xff20fc00 == 0x4500c400 {
                                                                return Some (SABALT_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0x800000 == 0 {
                                                                if insn & 0xffa0fc00 == 0x4500d400 {
                                                                    return Some (ADCLT_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xffa0fc00 == 0x4580d400 {
                                                                    return Some (SBCLT_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x001000 == 0 {
                                                        if insn & 0x000400 == 0 {
                                                            if insn & 0xff20fc00 == 0x4500c800 {
                                                                return Some (UABALB_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xff20fc00 == 0x4500cc00 {
                                                                return Some (UABALT_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x010000 == 0 {
                                                            if insn & 0xff3ff800 == 0x4500d800 {
                                                                return Some (CADD_SVE_Zd_SVE_Zd_SVE_Zn_SVE_IMM_ROT3 :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xff3ff800 == 0x4501d800 {
                                                                return Some (SQCADD_SVE_Zd_SVE_Zd_SVE_Zn_SVE_IMM_ROT3 :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0x400000 == 0 {
                                                    if insn & 0x800000 == 0 {
                                                        if insn & 0xffe0e000 == 0xc500c000 {
                                                            return Some (LDNT1W_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_ZX_S_D :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xffe0e000 == 0xc580c000 {
                                                            return Some (LDNT1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZX :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x800000 == 0 {
                                                        if insn & 0xffe0e000 == 0xc540c000 {
                                                            return Some (LD1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xffe0e000 == 0xc5c0c000 {
                                                            return Some (LD1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                }
                                            }
                                        } else {
                                            if insn & 0x800000 == 0 {
                                                if insn & 0x400000 == 0 {
                                                    if insn & 0xffe0e000 == 0xc520c000 {
                                                        return Some (LD1W_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_ZI_U5x4_S_D :: make_opcode (insn)) ;
                                                    }
                                                } else {
                                                    if insn & 0xffe0e000 == 0xc560c000 {
                                                        return Some (LD1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL2 :: make_opcode (insn)) ;
                                                    }
                                                }
                                            } else {
                                                if insn & 0x80000000 == 0 {
                                                    if insn & 0xffa0e000 == 0x45a0c000 {
                                                        return Some (HISTCNT_SVE_Zd_SVE_Pg3_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                    }
                                                } else {
                                                    if insn & 0x400000 == 0 {
                                                        if insn & 0xffe0e000 == 0xc5a0c000 {
                                                            return Some (LD1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x8 :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xffe0e000 == 0xc5e0c000 {
                                                            return Some (LD1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL3 :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                }
                                            }
                                        }
                                    }
                                }
                            } else {
                                if insn & 0x004000 == 0 {
                                    if insn & 0x008000 == 0 {
                                        if insn & 0x200000 == 0 {
                                            if insn & 0x80000000 == 0 {
                                                if insn & 0x000400 == 0 {
                                                    if insn & 0x000800 == 0 {
                                                        if insn & 0xff20fc00 == 0x45003000 {
                                                            return Some (SABDLB_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xff20fc00 == 0x45003800 {
                                                            return Some (UABDLB_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x000800 == 0 {
                                                        if insn & 0xff20fc00 == 0x45003400 {
                                                            return Some (SABDLT_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xff20fc00 == 0x45003c00 {
                                                            return Some (UABDLT_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0xffa0e000 == 0xc5002000 {
                                                    return Some (LDFF1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22 :: make_opcode (insn)) ;
                                                }
                                            }
                                        } else {
                                            if insn & 0x800000 == 0 {
                                                if insn & 0x80000000 == 0 {
                                                    if insn & 0x000400 == 0 {
                                                        if insn & 0x000800 == 0 {
                                                            if insn & 0x001000 == 0 {
                                                                if insn & 0xffa0fc00 == 0x45202000 {
                                                                    return Some (SQSHRNB_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22 :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xffa0fc00 == 0x45203000 {
                                                                    return Some (UQSHRNB_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22 :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x001000 == 0 {
                                                                if insn & 0xffa0fc00 == 0x45202800 {
                                                                    return Some (SQRSHRNB_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22 :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xffa0fc00 == 0x45203800 {
                                                                    return Some (UQRSHRNB_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22 :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x000800 == 0 {
                                                            if insn & 0x001000 == 0 {
                                                                if insn & 0xffa0fc00 == 0x45202400 {
                                                                    return Some (SQSHRNT_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22 :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xffa0fc00 == 0x45203400 {
                                                                    return Some (UQSHRNT_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22 :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x001000 == 0 {
                                                                if insn & 0xffa0fc00 == 0x45202c00 {
                                                                    return Some (SQRSHRNT_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22 :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xffa0fc00 == 0x45203c00 {
                                                                    return Some (UQRSHRNT_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED_22 :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0xffa0e000 == 0xc5202000 {
                                                        return Some (LDFF1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW2_22 :: make_opcode (insn)) ;
                                                    }
                                                }
                                            } else {
                                                if insn & 0x001000 == 0 {
                                                    if insn & 0xfff0fc20 == 0x45b02800 {
                                                        return Some (SQRSHRN_SVE_Zd_SME_Znx2_SME_SHRIMM4 :: make_opcode (insn)) ;
                                                    }
                                                } else {
                                                    if insn & 0xfff0fc20 == 0x45b03800 {
                                                        return Some (UQRSHRN_SVE_Zd_SME_Znx2_SME_SHRIMM4 :: make_opcode (insn)) ;
                                                    }
                                                }
                                            }
                                        }
                                    } else {
                                        if insn & 0x200000 == 0 {
                                            if insn & 0x80000000 == 0 {
                                                if insn & 0x000400 == 0 {
                                                    if insn & 0x000800 == 0 {
                                                        if insn & 0x001000 == 0 {
                                                            if insn & 0xffa0fc00 == 0x4500a000 {
                                                                return Some (SSHLLB_SVE_Zd_SVE_Zn_SVE_SHLIMM_UNPRED_22 :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xff20fc00 == 0x4500b000 {
                                                                return Some (BEXT_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x001000 == 0 {
                                                            if insn & 0xffa0fc00 == 0x4500a800 {
                                                                return Some (USHLLB_SVE_Zd_SVE_Zn_SVE_SHLIMM_UNPRED_22 :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xff20fc00 == 0x4500b800 {
                                                                return Some (BGRP_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x000800 == 0 {
                                                        if insn & 0x001000 == 0 {
                                                            if insn & 0xffa0fc00 == 0x4500a400 {
                                                                return Some (SSHLLT_SVE_Zd_SVE_Zn_SVE_SHLIMM_UNPRED_22 :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xff20fc00 == 0x4500b400 {
                                                                return Some (BDEP_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0xffa0fc00 == 0x4500ac00 {
                                                            return Some (USHLLT_SVE_Zd_SVE_Zn_SVE_SHLIMM_UNPRED_22 :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0xffe0e000 == 0xc540a000 {
                                                    return Some (LDFF1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ :: make_opcode (insn)) ;
                                                }
                                            }
                                        } else {
                                            if insn & 0x400000 == 0 {
                                                if insn & 0x80000000 == 0 {
                                                    if insn & 0xffe0fc00 == 0x4520a000 {
                                                        return Some (HISTSEG_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                    }
                                                } else {
                                                    if insn & 0xffe0e000 == 0xc520a000 {
                                                        return Some (LDFF1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x4 :: make_opcode (insn)) ;
                                                    }
                                                }
                                            } else {
                                                if insn & 0xffe0e000 == 0xc560a000 {
                                                    return Some (LDFF1SW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL2 :: make_opcode (insn)) ;
                                                }
                                            }
                                        }
                                    }
                                } else {
                                    if insn & 0x008000 == 0 {
                                        if insn & 0x200000 == 0 {
                                            if insn & 0x80000000 == 0 {
                                                if insn & 0x000400 == 0 {
                                                    if insn & 0x000800 == 0 {
                                                        if insn & 0x001000 == 0 {
                                                            if insn & 0xff20fc00 == 0x45006000 {
                                                                return Some (SQDMULLB_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xff20fc00 == 0x45007000 {
                                                                return Some (SMULLB_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x001000 == 0 {
                                                            if insn & 0x400000 == 0 {
                                                                if insn & 0xffe0fc00 == 0x45006800 {
                                                                    return Some (PMULLB_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xff60fc00 == 0x45406800 {
                                                                    return Some (PMULLB_SVE_Zd_S_H_SVE_Zn_S_B_SVE_Zm_16_S_B :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0xff20fc00 == 0x45007800 {
                                                                return Some (UMULLB_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x000800 == 0 {
                                                        if insn & 0x001000 == 0 {
                                                            if insn & 0xff20fc00 == 0x45006400 {
                                                                return Some (SQDMULLT_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xff20fc00 == 0x45007400 {
                                                                return Some (SMULLT_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x001000 == 0 {
                                                            if insn & 0x400000 == 0 {
                                                                if insn & 0xffe0fc00 == 0x45006c00 {
                                                                    return Some (PMULLT_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xff60fc00 == 0x45406c00 {
                                                                    return Some (PMULLT_SVE_Zd_S_H_SVE_Zn_S_B_SVE_Zm_16_S_B :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0xff20fc00 == 0x45007c00 {
                                                                return Some (UMULLT_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0x800000 == 0 {
                                                    if insn & 0xffa0e000 == 0xc5006000 {
                                                        return Some (LDFF1W_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW_22_S_D :: make_opcode (insn)) ;
                                                    }
                                                } else {
                                                    if insn & 0xffa0e000 == 0xc5806000 {
                                                        return Some (LDFF1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_22 :: make_opcode (insn)) ;
                                                    }
                                                }
                                            }
                                        } else {
                                            if insn & 0x80000000 == 0 {
                                                if insn & 0x000400 == 0 {
                                                    if insn & 0x000800 == 0 {
                                                        if insn & 0x001000 == 0 {
                                                            if insn & 0xff20fc00 == 0x45206000 {
                                                                return Some (ADDHNB_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xff20fc00 == 0x45207000 {
                                                                return Some (SUBHNB_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x001000 == 0 {
                                                            if insn & 0xff20fc00 == 0x45206800 {
                                                                return Some (RADDHNB_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xff20fc00 == 0x45207800 {
                                                                return Some (RSUBHNB_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x000800 == 0 {
                                                        if insn & 0x001000 == 0 {
                                                            if insn & 0xff20fc00 == 0x45206400 {
                                                                return Some (ADDHNT_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xff20fc00 == 0x45207400 {
                                                                return Some (SUBHNT_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x001000 == 0 {
                                                            if insn & 0xff20fc00 == 0x45206c00 {
                                                                return Some (RADDHNT_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xff20fc00 == 0x45207c00 {
                                                                return Some (RSUBHNT_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0x800000 == 0 {
                                                    if insn & 0xffa0e000 == 0xc5206000 {
                                                        return Some (LDFF1W_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RZ_XTW2_22_S_D :: make_opcode (insn)) ;
                                                    }
                                                } else {
                                                    if insn & 0xffa0e000 == 0xc5a06000 {
                                                        return Some (LDFF1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW3_22 :: make_opcode (insn)) ;
                                                    }
                                                }
                                            }
                                        }
                                    } else {
                                        if insn & 0x200000 == 0 {
                                            if insn & 0x80000000 == 0 {
                                                if insn & 0x000400 == 0 {
                                                    if insn & 0x000800 == 0 {
                                                        if insn & 0x001000 == 0 {
                                                            if insn & 0xff20fc00 == 0x4500e000 {
                                                                return Some (SSRA_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xff20fc00 == 0x4500f000 {
                                                                return Some (SRI_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x001000 == 0 {
                                                            if insn & 0xff20fc00 == 0x4500e800 {
                                                                return Some (SRSRA_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xff20fc00 == 0x4500f800 {
                                                                return Some (SABA_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x000800 == 0 {
                                                        if insn & 0x001000 == 0 {
                                                            if insn & 0xff20fc00 == 0x4500e400 {
                                                                return Some (USRA_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xff20fc00 == 0x4500f400 {
                                                                return Some (SLI_SVE_Zd_SVE_Zn_SVE_SHLIMM_UNPRED :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x001000 == 0 {
                                                            if insn & 0xff20fc00 == 0x4500ec00 {
                                                                return Some (URSRA_SVE_Zd_SVE_Zn_SVE_SHRIMM_UNPRED :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xff20fc00 == 0x4500fc00 {
                                                                return Some (UABA_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0x400000 == 0 {
                                                    if insn & 0x800000 == 0 {
                                                        if insn & 0xffe0e010 == 0xc500e000 {
                                                            return Some (PRFW_SVE_PRFOP_SVE_Pg3_SVE_ADDR_ZI_U5x4_c500e000 :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xffe0e010 == 0xc580e000 {
                                                            return Some (PRFD_SVE_PRFOP_SVE_Pg3_SVE_ADDR_ZI_U5x8_c580e000 :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x800000 == 0 {
                                                        if insn & 0xffe0e000 == 0xc540e000 {
                                                            return Some (LDFF1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xffe0e000 == 0xc5c0e000 {
                                                            return Some (LDFF1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                }
                                            }
                                        } else {
                                            if insn & 0x400000 == 0 {
                                                if insn & 0x800000 == 0 {
                                                    if insn & 0x80000000 == 0 {
                                                        if insn & 0x000400 == 0 {
                                                            if insn & 0x001000 == 0 {
                                                                if insn & 0x010000 == 0 {
                                                                    if insn & 0x020000 == 0 {
                                                                        if insn & 0xffffffe0
                                                                            == 0x4520e000
                                                                        {
                                                                            return Some (AESMC_SVE_Zd_SVE_Zd :: make_opcode (insn)) ;
                                                                        }
                                                                    } else {
                                                                        if insn & 0xfffffc00
                                                                            == 0x4522e000
                                                                        {
                                                                            return Some (AESE_SVE_Zd_SVE_Zd_SVE_Zn :: make_opcode (insn)) ;
                                                                        }
                                                                    }
                                                                } else {
                                                                    if insn & 0xfffffc00
                                                                        == 0x4523e000
                                                                    {
                                                                        return Some (SM4E_SVE_Zd_SVE_Zd_SVE_Zn :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0xffe0fc00 == 0x4520f000 {
                                                                    return Some (SM4EKEY_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x001000 == 0 {
                                                                if insn & 0x020000 == 0 {
                                                                    if insn & 0xffffffe0
                                                                        == 0x4520e400
                                                                    {
                                                                        return Some (AESIMC_SVE_Zd_SVE_Zd :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xfffffc00
                                                                        == 0x4522e400
                                                                    {
                                                                        return Some (AESD_SVE_Zd_SVE_Zd_SVE_Zn :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0xffe0fc00 == 0x4520f400 {
                                                                    return Some (RAX1_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0xffe0e000 == 0xc520e000 {
                                                            return Some (LDFF1W_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_ZI_U5x4_S_D :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0xffe0e000 == 0xc5a0e000 {
                                                        return Some (LDFF1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x8 :: make_opcode (insn)) ;
                                                    }
                                                }
                                            } else {
                                                if insn & 0x800000 == 0 {
                                                    if insn & 0xffe0e000 == 0xc560e000 {
                                                        return Some (LDFF1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL2 :: make_opcode (insn)) ;
                                                    }
                                                } else {
                                                    if insn & 0xffe0e000 == 0xc5e0e000 {
                                                        return Some (LDFF1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL3 :: make_opcode (insn)) ;
                                                    }
                                                }
                                            }
                                        }
                                    }
                                }
                            }
                        }
                    } else {
                        if insn & 0x008000 == 0 {
                            if insn & 0x004000 == 0 {
                                if insn & 0x002000 == 0 {
                                    if insn & 0x40000000 == 0 {
                                        if insn & 0x200000 == 0 {
                                            if insn & 0x80000000 == 0 {
                                                if insn & 0x000010 == 0 {
                                                    if insn & 0xff20e010 == 0x25000000 {
                                                        return Some (CMPGE_SVE_Pd_SVE_Pg3_SVE_Zn_SIMM5 :: make_opcode (insn)) ;
                                                    }
                                                } else {
                                                    if insn & 0xff20e010 == 0x25000010 {
                                                        return Some (CMPGT_SVE_Pd_SVE_Pg3_SVE_Zn_SIMM5 :: make_opcode (insn)) ;
                                                    }
                                                }
                                            } else {
                                                if insn & 0x800000 == 0 {
                                                    if insn & 0xffe0e000 == 0xa5000000 {
                                                        return Some (LD1RQW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2 :: make_opcode (insn)) ;
                                                    }
                                                } else {
                                                    if insn & 0xffe0e000 == 0xa5800000 {
                                                        return Some (LD1RQD_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL3 :: make_opcode (insn)) ;
                                                    }
                                                }
                                            }
                                        } else {
                                            if insn & 0x80000000 == 0 {
                                                if insn & 0x000010 == 0 {
                                                    if insn & 0x000400 == 0 {
                                                        if insn & 0x000800 == 0 {
                                                            if insn & 0x001000 == 0 {
                                                                if insn & 0xff20fc10 == 0x25200000 {
                                                                    return Some (WHILEGE_SVE_Pd_Rn_Rm :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xff20fc10 == 0x25201000 {
                                                                    return Some (WHILEGE_SVE_Pd_S_B_Rn_X_Rm_X :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x001000 == 0 {
                                                                if insn & 0xff20fc10 == 0x25200800 {
                                                                    return Some (WHILEHS_SVE_Pd_Rn_Rm :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xff20fc10 == 0x25201800 {
                                                                    return Some (WHILEHS_SVE_Pd_S_B_Rn_X_Rm_X :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x000800 == 0 {
                                                            if insn & 0x001000 == 0 {
                                                                if insn & 0xff20fc10 == 0x25200400 {
                                                                    return Some (WHILELT_SVE_Pd_Rn_Rm :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xff20fc10 == 0x25201400 {
                                                                    return Some (WHILELT_SVE_Pd_S_B_Rn_X_Rm_X :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x001000 == 0 {
                                                                if insn & 0xff20fc10 == 0x25200c00 {
                                                                    return Some (WHILELO_SVE_Pd_Rn_Rm :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xff20fc10 == 0x25201c00 {
                                                                    return Some (WHILELO_SVE_Pd_S_B_Rn_X_Rm_X :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x000400 == 0 {
                                                        if insn & 0x000800 == 0 {
                                                            if insn & 0x001000 == 0 {
                                                                if insn & 0xff20fc10 == 0x25200010 {
                                                                    return Some (WHILEGT_SVE_Pd_Rn_Rm :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xff20fc10 == 0x25201010 {
                                                                    return Some (WHILEGT_SVE_Pd_S_B_Rn_X_Rm_X :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x001000 == 0 {
                                                                if insn & 0xff20fc10 == 0x25200810 {
                                                                    return Some (WHILEHI_SVE_Pd_Rn_Rm :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xff20fc10 == 0x25201810 {
                                                                    return Some (WHILEHI_SVE_Pd_S_B_Rn_X_Rm_X :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x000800 == 0 {
                                                            if insn & 0x001000 == 0 {
                                                                if insn & 0xff20fc10 == 0x25200410 {
                                                                    return Some (WHILELE_SVE_Pd_Rn_Rm :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xff20fc10 == 0x25201410 {
                                                                    return Some (WHILELE_SVE_Pd_S_B_Rn_X_Rm_X :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x001000 == 0 {
                                                                if insn & 0xff20fc10 == 0x25200c10 {
                                                                    return Some (WHILELS_SVE_Pd_Rn_Rm :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xff20fc10 == 0x25201c10 {
                                                                    return Some (WHILELS_SVE_Pd_S_B_Rn_X_Rm_X :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0x800000 == 0 {
                                                    if insn & 0xffe0e000 == 0xa5200000 {
                                                        return Some (LD1ROW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2 :: make_opcode (insn)) ;
                                                    }
                                                } else {
                                                    if insn & 0xffe0e000 == 0xa5a00000 {
                                                        return Some (LD1ROD_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL3 :: make_opcode (insn)) ;
                                                    }
                                                }
                                            }
                                        }
                                    } else {
                                        if insn & 0x80000000 == 0 {
                                            if insn & 0x200000 == 0 {
                                                if insn & 0x000400 == 0 {
                                                    if insn & 0x000800 == 0 {
                                                        if insn & 0xffe0fc00 == 0x65000000 {
                                                            return Some (BFADD_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                        }
                                                        if insn & 0xff20fc00 == 0x65000000 {
                                                            return Some (FADD_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0x001000 == 0 {
                                                            if insn & 0xffe0fc00 == 0x65000800 {
                                                                return Some (BFMUL_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                            }
                                                            if insn & 0xff20fc00 == 0x65000800 {
                                                                return Some (FMUL_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xff20fc00 == 0x65001800 {
                                                                return Some (FRECPS_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x000800 == 0 {
                                                        if insn & 0xffe0fc00 == 0x65000400 {
                                                            return Some (BFSUB_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                        }
                                                        if insn & 0xff20fc00 == 0x65000400 {
                                                            return Some (FSUB_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0x001000 == 0 {
                                                            if insn & 0xff20fc00 == 0x65000c00 {
                                                                return Some (FTSMUL_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xff20fc00 == 0x65001c00 {
                                                                return Some (FRSQRTS_SVE_Zd_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0xffe0e000 == 0x65200000 {
                                                    return Some (BFMLA_SVE_Zd_SVE_Pg3_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                }
                                                if insn & 0xff20e000 == 0x65200000 {
                                                    return Some (FMLA_SVE_Zd_SVE_Pg3_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                }
                                            }
                                        } else {
                                            if insn & 0xffc0e010 == 0xe5800000 {
                                                return Some(
                                                    STR_SVE_PNt_SVE_ADDR_RI_S9xVL::make_opcode(
                                                        insn,
                                                    ),
                                                );
                                            }
                                            if insn & 0xffc0e010 == 0xe5800000 {
                                                return Some(
                                                    STR_SVE_PNt_SVE_ADDR_RI_S9xVL::make_opcode(
                                                        insn,
                                                    ),
                                                );
                                            }
                                        }
                                    }
                                } else {
                                    if insn & 0x200000 == 0 {
                                        if insn & 0x40000000 == 0 {
                                            if insn & 0x80000000 == 0 {
                                                if insn & 0x000010 == 0 {
                                                    if insn & 0xff20e010 == 0x25002000 {
                                                        return Some (CMPLT_SVE_Pd_SVE_Pg3_SVE_Zn_SIMM5 :: make_opcode (insn)) ;
                                                    }
                                                } else {
                                                    if insn & 0xff20e010 == 0x25002010 {
                                                        return Some (CMPLE_SVE_Pd_SVE_Pg3_SVE_Zn_SIMM5 :: make_opcode (insn)) ;
                                                    }
                                                }
                                            } else {
                                                if insn & 0x800000 == 0 {
                                                    if insn & 0xfff0e000 == 0xa5002000 {
                                                        return Some (LD1RQW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x16 :: make_opcode (insn)) ;
                                                    }
                                                } else {
                                                    if insn & 0xfff0e000 == 0xa5802000 {
                                                        return Some (LD1RQD_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x16 :: make_opcode (insn)) ;
                                                    }
                                                }
                                            }
                                        } else {
                                            if insn & 0x80000000 == 0 {
                                                if insn & 0x010000 == 0 {
                                                    if insn & 0x020000 == 0 {
                                                        if insn & 0x040000 == 0 {
                                                            if insn & 0x080000 == 0 {
                                                                if insn & 0x100000 == 0 {
                                                                    if insn & 0xff3fe000
                                                                        == 0x65002000
                                                                    {
                                                                        return Some (FADDV_SVE_Vd_SVE_Pg3_SVE_Zn :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0x000010 == 0 {
                                                                        if insn & 0xff3fe010
                                                                            == 0x65102000
                                                                        {
                                                                            return Some (FCMGE_SVE_Pd_SVE_Pg3_SVE_Zn_FPIMM0 :: make_opcode (insn)) ;
                                                                        }
                                                                    } else {
                                                                        if insn & 0xff3fe010
                                                                            == 0x65102010
                                                                        {
                                                                            return Some (FCMGT_SVE_Pd_SVE_Pg3_SVE_Zn_FPIMM0 :: make_opcode (insn)) ;
                                                                        }
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0xff3fe000 == 0x65182000 {
                                                                    return Some (FADDA_SVE_Vd_SVE_Pg3_SVE_Vd_SVE_Zm_5 :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0xff3fe000 == 0x65042000 {
                                                                return Some (FMAXNMV_SVE_Vd_SVE_Pg3_SVE_Zn :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x040000 == 0 {
                                                            if insn & 0xff3fe010 == 0x65122000 {
                                                                return Some (FCMEQ_SVE_Pd_SVE_Pg3_SVE_Zn_FPIMM0 :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0x080000 == 0 {
                                                                if insn & 0xff3fe000 == 0x65062000 {
                                                                    return Some (FMAXV_SVE_Vd_SVE_Pg3_SVE_Zn :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xff3ffc00 == 0x650e3000 {
                                                                    return Some (FRECPE_SVE_Zd_SVE_Zn :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x020000 == 0 {
                                                        if insn & 0x040000 == 0 {
                                                            if insn & 0x000010 == 0 {
                                                                if insn & 0xff3fe010 == 0x65112000 {
                                                                    return Some (FCMLT_SVE_Pd_SVE_Pg3_SVE_Zn_FPIMM0 :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xff3fe010 == 0x65112010 {
                                                                    return Some (FCMLE_SVE_Pd_SVE_Pg3_SVE_Zn_FPIMM0 :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0xff3fe000 == 0x65052000 {
                                                                return Some (FMINNMV_SVE_Vd_SVE_Pg3_SVE_Zn :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x040000 == 0 {
                                                            if insn & 0xff3fe010 == 0x65132000 {
                                                                return Some (FCMNE_SVE_Pd_SVE_Pg3_SVE_Zn_FPIMM0 :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0x080000 == 0 {
                                                                if insn & 0xff3fe000 == 0x65072000 {
                                                                    return Some (FMINV_SVE_Vd_SVE_Pg3_SVE_Zn :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xff3ffc00 == 0x650f3000 {
                                                                    return Some (FRSQRTE_SVE_Zd_SVE_Zn :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0x400000 == 0 {
                                                    if insn & 0x800000 == 0 {
                                                        if insn & 0xffe0e000 == 0xe5002000 {
                                                            return Some (STNT1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZX :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xffe0e000 == 0xe5802000 {
                                                            return Some (STNT1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZX :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0xffe0e000 == 0xe5402000 {
                                                        return Some (STNT1W_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_ZX :: make_opcode (insn)) ;
                                                    }
                                                }
                                            }
                                        }
                                    } else {
                                        if insn & 0x40000000 == 0 {
                                            if insn & 0x80000000 == 0 {
                                                if insn & 0x000010 == 0 {
                                                    if insn & 0x001000 == 0 {
                                                        if insn & 0xffa0fc1f == 0x25a02000 {
                                                            return Some(
                                                                CTERMEQ_Rn_Rm::make_opcode(insn),
                                                            );
                                                        }
                                                    } else {
                                                        if insn & 0xff20fc10 == 0x25203000 {
                                                            return Some(
                                                                WHILEWR_SVE_Pd_Rn_Rm::make_opcode(
                                                                    insn,
                                                                ),
                                                            );
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x001000 == 0 {
                                                        if insn & 0xffa0fc1f == 0x25a02010 {
                                                            return Some(
                                                                CTERMNE_Rn_Rm::make_opcode(insn),
                                                            );
                                                        }
                                                    } else {
                                                        if insn & 0xff20fc10 == 0x25203010 {
                                                            return Some(
                                                                WHILERW_SVE_Pd_Rn_Rm::make_opcode(
                                                                    insn,
                                                                ),
                                                            );
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0x800000 == 0 {
                                                    if insn & 0xfff0e000 == 0xa5202000 {
                                                        return Some (LD1ROW_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x32 :: make_opcode (insn)) ;
                                                    }
                                                } else {
                                                    if insn & 0xfff0e000 == 0xa5a02000 {
                                                        return Some (LD1ROD_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x32 :: make_opcode (insn)) ;
                                                    }
                                                }
                                            }
                                        } else {
                                            if insn & 0xffe0e000 == 0x65202000 {
                                                return Some (BFMLS_SVE_Zd_SVE_Pg3_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                            }
                                            if insn & 0xff20e000 == 0x65202000 {
                                                return Some (FMLS_SVE_Zd_SVE_Pg3_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                            }
                                        }
                                    }
                                }
                            } else {
                                if insn & 0x40000000 == 0 {
                                    if insn & 0x200000 == 0 {
                                        if insn & 0x400000 == 0 {
                                            if insn & 0x800000 == 0 {
                                                if insn & 0x80000000 == 0 {
                                                    if insn & 0x000200 == 0 {
                                                        if insn & 0x100000 == 0 {
                                                            if insn & 0x000010 == 0 {
                                                                if insn & 0xfff0c210 == 0x25004000 {
                                                                    return Some (AND_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xfff0c210 == 0x25004010 {
                                                                    return Some (BIC_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x080000 == 0 {
                                                                if insn & 0xffffc200 == 0x25104000 {
                                                                    return Some (BRKA_SVE_Pd_SVE_Pg4_10_SVE_Pn :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xffffc210 == 0x25184000 {
                                                                    return Some (BRKN_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pd :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x000010 == 0 {
                                                            if insn & 0xfff0c210 == 0x25004200 {
                                                                return Some (EOR_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xfff0c210 == 0x25004210 {
                                                                return Some (SEL_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x002000 == 0 {
                                                        if insn & 0xffe0e000 == 0xa5004000 {
                                                            return Some (LD1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL1 :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xffe0e000 == 0xa5006000 {
                                                            return Some (LDFF1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_R :: make_opcode (insn)) ;
                                                        }
                                                        if insn & 0xffe0e000 == 0xa5006000 {
                                                            return Some (LDFF1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_R :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0x80000000 == 0 {
                                                    if insn & 0x000200 == 0 {
                                                        if insn & 0x100000 == 0 {
                                                            if insn & 0x000010 == 0 {
                                                                if insn & 0xfff0c210 == 0x25804000 {
                                                                    return Some (ORR_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xfff0c210 == 0x25804010 {
                                                                    return Some (ORN_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0xffffc200 == 0x25904000 {
                                                                return Some (BRKB_SVE_Pd_SVE_Pg4_10_SVE_Pn :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x000010 == 0 {
                                                            if insn & 0xfff0c210 == 0x25804200 {
                                                                return Some (NOR_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xfff0c210 == 0x25804210 {
                                                                return Some (NAND_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x002000 == 0 {
                                                        if insn & 0xffe0e000 == 0xa5804000 {
                                                            return Some (LD1SB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xffe0e000 == 0xa5806000 {
                                                            return Some (LDFF1SB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_R :: make_opcode (insn)) ;
                                                        }
                                                        if insn & 0xffe0e000 == 0xa5806000 {
                                                            return Some (LDFF1SB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_R :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                }
                                            }
                                        } else {
                                            if insn & 0x800000 == 0 {
                                                if insn & 0x80000000 == 0 {
                                                    if insn & 0x000010 == 0 {
                                                        if insn & 0x000200 == 0 {
                                                            if insn & 0x100000 == 0 {
                                                                if insn & 0xfff0c210 == 0x25404000 {
                                                                    return Some (ANDS_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0x080000 == 0 {
                                                                    if insn & 0xffffc210
                                                                        == 0x25504000
                                                                    {
                                                                        return Some (BRKAS_SVE_Pd_SVE_Pg4_10_SVE_Pn :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xffffc210
                                                                        == 0x25584000
                                                                    {
                                                                        return Some (BRKNS_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pd :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0xfff0c210 == 0x25404200 {
                                                                return Some (EORS_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0xfff0c210 == 0x25404010 {
                                                            return Some (BICS_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x002000 == 0 {
                                                        if insn & 0xffe0e000 == 0xa5404000 {
                                                            return Some (LD1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2 :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xffe0e000 == 0xa5406000 {
                                                            return Some (LDFF1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_R :: make_opcode (insn)) ;
                                                        }
                                                        if insn & 0xffe0e000 == 0xa5406000 {
                                                            return Some (LDFF1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_R :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0x80000000 == 0 {
                                                    if insn & 0x000010 == 0 {
                                                        if insn & 0x000200 == 0 {
                                                            if insn & 0x100000 == 0 {
                                                                if insn & 0xfff0c210 == 0x25c04000 {
                                                                    return Some (ORRS_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xffffc210 == 0x25d04000 {
                                                                    return Some (BRKBS_SVE_Pd_SVE_Pg4_10_SVE_Pn :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0xfff0c210 == 0x25c04200 {
                                                                return Some (NORS_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x000200 == 0 {
                                                            if insn & 0xfff0c210 == 0x25c04010 {
                                                                return Some (ORNS_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xfff0c210 == 0x25c04210 {
                                                                return Some (NANDS_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x002000 == 0 {
                                                        if insn & 0xffe0e000 == 0xa5c04000 {
                                                            return Some (LD1SB_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RX :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xffe0e000 == 0xa5c06000 {
                                                            return Some (LDFF1SB_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_R :: make_opcode (insn)) ;
                                                        }
                                                        if insn & 0xffe0e000 == 0xa5c06000 {
                                                            return Some (LDFF1SB_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_R :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                }
                                            }
                                        }
                                    } else {
                                        if insn & 0x80000000 == 0 {
                                            if insn & 0x000010 == 0 {
                                                if insn & 0xff20c210 == 0x25204000 {
                                                    return Some (PSEL_SVE_PNd_SVE_PNg4_10_SME_PnT_Wm_imm :: make_opcode (insn)) ;
                                                }
                                                if insn & 0xff20c210 == 0x25204000 {
                                                    return Some (PSEL_SVE_PNd_SVE_PNg4_10_SME_PnT_Wm_imm :: make_opcode (insn)) ;
                                                }
                                            } else {
                                                if insn & 0x000400 == 0 {
                                                    if insn & 0x000800 == 0 {
                                                        if insn & 0x001000 == 0 {
                                                            if insn & 0x000008 == 0 {
                                                                if insn & 0xff20dc18 == 0x25204010 {
                                                                    return Some (WHILEGE_SME_PNd3_Rn_Rm_SME_VLxN_13 :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xff20dc18 == 0x25204018 {
                                                                    return Some (WHILEGT_SME_PNd3_Rn_Rm_SME_VLxN_13 :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x002000 == 0 {
                                                                if insn & 0x000001 == 0 {
                                                                    if insn & 0xff20fc11
                                                                        == 0x25205010
                                                                    {
                                                                        return Some (WHILEGE_SME_Pdx2_Rn_Rm :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xff20fc11
                                                                        == 0x25205011
                                                                    {
                                                                        return Some (WHILEGT_SME_Pdx2_Rn_Rm :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0xff3ffc10 == 0x25207010 {
                                                                    return Some (PEXT_SVE_Pd_SME_PNn3_INDEX2 :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x001000 == 0 {
                                                            if insn & 0x000008 == 0 {
                                                                if insn & 0xff20dc18 == 0x25204810 {
                                                                    return Some (WHILEHS_SME_PNd3_Rn_Rm_SME_VLxN_13 :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xff20dc18 == 0x25204818 {
                                                                    return Some (WHILEHI_SME_PNd3_Rn_Rm_SME_VLxN_13 :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x002000 == 0 {
                                                                if insn & 0x000001 == 0 {
                                                                    if insn & 0xff20fc11
                                                                        == 0x25205810
                                                                    {
                                                                        return Some (WHILEHS_SME_Pdx2_Rn_Rm :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xff20fc11
                                                                        == 0x25205811
                                                                    {
                                                                        return Some (WHILEHI_SME_Pdx2_Rn_Rm :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0xff3ffff8 == 0x25207810 {
                                                                    return Some(
                                                                        PTRUE_SME_PNd3::make_opcode(
                                                                            insn,
                                                                        ),
                                                                    );
                                                                }
                                                            }
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x000800 == 0 {
                                                        if insn & 0x001000 == 0 {
                                                            if insn & 0x000008 == 0 {
                                                                if insn & 0xff20dc18 == 0x25204410 {
                                                                    return Some (WHILELT_SME_PNd3_Rn_Rm_SME_VLxN_13 :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xff20dc18 == 0x25204418 {
                                                                    return Some (WHILELE_SME_PNd3_Rn_Rm_SME_VLxN_13 :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x002000 == 0 {
                                                                if insn & 0x000001 == 0 {
                                                                    if insn & 0xff20fc11
                                                                        == 0x25205410
                                                                    {
                                                                        return Some (WHILELT_SME_Pdx2_Rn_Rm :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xff20fc11
                                                                        == 0x25205411
                                                                    {
                                                                        return Some (WHILELE_SME_Pdx2_Rn_Rm :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0xff3ffe10 == 0x25207410 {
                                                                    return Some (PEXT_SME_PdxN_SME_PNn3_INDEX1 :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x001000 == 0 {
                                                            if insn & 0x000008 == 0 {
                                                                if insn & 0xff20dc18 == 0x25204c10 {
                                                                    return Some (WHILELO_SME_PNd3_Rn_Rm_SME_VLxN_13 :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xff20dc18 == 0x25204c18 {
                                                                    return Some (WHILELS_SME_PNd3_Rn_Rm_SME_VLxN_13 :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x000001 == 0 {
                                                                if insn & 0xff20fc11 == 0x25205c10 {
                                                                    return Some (WHILELO_SME_Pdx2_Rn_Rm :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xff20fc11 == 0x25205c11 {
                                                                    return Some (WHILELS_SME_Pdx2_Rn_Rm :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        }
                                                    }
                                                }
                                            }
                                        } else {
                                            if insn & 0x002000 == 0 {
                                                if insn & 0x400000 == 0 {
                                                    if insn & 0x800000 == 0 {
                                                        if insn & 0xffe0e000 == 0xa5204000 {
                                                            return Some (LD1SH_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RX_LSL1 :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xffe0e000 == 0xa5a04000 {
                                                            return Some (LD1SB_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RX :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x800000 == 0 {
                                                        if insn & 0xffe0e000 == 0xa5604000 {
                                                            return Some (LD1W_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RX_LSL2 :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xffe0e000 == 0xa5e04000 {
                                                            return Some (LD1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL3 :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0x400000 == 0 {
                                                    if insn & 0x800000 == 0 {
                                                        if insn & 0xffe0e000 == 0xa5206000 {
                                                            return Some (LDFF1SH_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_R :: make_opcode (insn)) ;
                                                        }
                                                        if insn & 0xffe0e000 == 0xa5206000 {
                                                            return Some (LDFF1SH_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_R :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xffe0e000 == 0xa5a06000 {
                                                            return Some (LDFF1SB_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_R :: make_opcode (insn)) ;
                                                        }
                                                        if insn & 0xffe0e000 == 0xa5a06000 {
                                                            return Some (LDFF1SB_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_R :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x800000 == 0 {
                                                        if insn & 0xffe0e000 == 0xa5606000 {
                                                            return Some (LDFF1W_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_R :: make_opcode (insn)) ;
                                                        }
                                                        if insn & 0xffe0e000 == 0xa5606000 {
                                                            return Some (LDFF1W_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_R :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xffe0e000 == 0xa5e06000 {
                                                            return Some (LDFF1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_R :: make_opcode (insn)) ;
                                                        }
                                                        if insn & 0xffe0e000 == 0xa5e06000 {
                                                            return Some (LDFF1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_R :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                }
                                            }
                                        }
                                    }
                                } else {
                                    if insn & 0x002000 == 0 {
                                        if insn & 0x80000000 == 0 {
                                            if insn & 0x200000 == 0 {
                                                if insn & 0x000010 == 0 {
                                                    if insn & 0xff20e010 == 0x65004000 {
                                                        return Some (FCMGE_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                    }
                                                } else {
                                                    if insn & 0xff20e010 == 0x65004010 {
                                                        return Some (FCMGT_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                    }
                                                }
                                            } else {
                                                if insn & 0xff20e000 == 0x65204000 {
                                                    return Some (FNMLA_SVE_Zd_SVE_Pg3_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                }
                                            }
                                        } else {
                                            if insn & 0x400000 == 0 {
                                                if insn & 0xffc0e000 == 0xe5804000 {
                                                    return Some(
                                                        STR_SVE_Zt_SVE_ADDR_RI_S9xVL::make_opcode(
                                                            insn,
                                                        ),
                                                    );
                                                }
                                            } else {
                                                if insn & 0x200000 == 0 {
                                                    if insn & 0xffe0e000 == 0xe5404000 {
                                                        return Some (ST1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2 :: make_opcode (insn)) ;
                                                    }
                                                } else {
                                                    if insn & 0x800000 == 0 {
                                                        if insn & 0xffe0e000 == 0xe5604000 {
                                                            return Some (ST1W_SVE_ZtxN_S_D_SVE_Pg3_SVE_ADDR_RX_LSL2 :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xffe0e000 == 0xe5e04000 {
                                                            return Some (ST1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL3 :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                }
                                            }
                                        }
                                    } else {
                                        if insn & 0x200000 == 0 {
                                            if insn & 0x80000000 == 0 {
                                                if insn & 0x000010 == 0 {
                                                    if insn & 0xff20e010 == 0x65006000 {
                                                        return Some (FCMEQ_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                    }
                                                } else {
                                                    if insn & 0xff20e010 == 0x65006010 {
                                                        return Some (FCMNE_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                    }
                                                }
                                            } else {
                                                if insn & 0x400000 == 0 {
                                                    if insn & 0x800000 == 0 {
                                                        if insn & 0xffe0e000 == 0xe5006000 {
                                                            return Some (STNT1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2 :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xffe0e000 == 0xe5806000 {
                                                            return Some (STNT1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL3 :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x800000 == 0 {
                                                        if insn & 0xffe0e000 == 0xe5406000 {
                                                            return Some (ST3W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2 :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xffe0e000 == 0xe5c06000 {
                                                            return Some (ST3D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL3 :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                }
                                            }
                                        } else {
                                            if insn & 0x80000000 == 0 {
                                                if insn & 0xff20e000 == 0x65206000 {
                                                    return Some (FNMLS_SVE_Zd_SVE_Pg3_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                }
                                            } else {
                                                if insn & 0x400000 == 0 {
                                                    if insn & 0x800000 == 0 {
                                                        if insn & 0xffe0e000 == 0xe5206000 {
                                                            return Some (ST2W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2 :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xffe0e000 == 0xe5a06000 {
                                                            return Some (ST2D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL3 :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x800000 == 0 {
                                                        if insn & 0xffe0e000 == 0xe5606000 {
                                                            return Some (ST4W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2 :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xffe0e000 == 0xe5e06000 {
                                                            return Some (ST4D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL3 :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                }
                                            }
                                        }
                                    }
                                }
                            }
                        } else {
                            if insn & 0x200000 == 0 {
                                if insn & 0x40000000 == 0 {
                                    if insn & 0x004000 == 0 {
                                        if insn & 0x002000 == 0 {
                                            if insn & 0x000010 == 0 {
                                                if insn & 0xff20e010 == 0x25008000 {
                                                    return Some (CMPEQ_SVE_Pd_SVE_Pg3_SVE_Zn_SIMM5 :: make_opcode (insn)) ;
                                                }
                                            } else {
                                                if insn & 0xff20e010 == 0x25008010 {
                                                    return Some (CMPNE_SVE_Pd_SVE_Pg3_SVE_Zn_SIMM5 :: make_opcode (insn)) ;
                                                }
                                            }
                                        } else {
                                            if insn & 0x100000 == 0 {
                                                if insn & 0x400000 == 0 {
                                                    if insn & 0x800000 == 0 {
                                                        if insn & 0xfff0e000 == 0xa500a000 {
                                                            return Some (LD1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xfff0e000 == 0xa580a000 {
                                                            return Some (LD1SB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x800000 == 0 {
                                                        if insn & 0xfff0e000 == 0xa540a000 {
                                                            return Some (LD1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xfff0e000 == 0xa5c0a000 {
                                                            return Some (LD1SB_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0x400000 == 0 {
                                                    if insn & 0x800000 == 0 {
                                                        if insn & 0xfff0e000 == 0xa510a000 {
                                                            return Some (LDNF1SH_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xfff0e000 == 0xa590a000 {
                                                            return Some (LDNF1SB_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x800000 == 0 {
                                                        if insn & 0xfff0e000 == 0xa550a000 {
                                                            return Some (LDNF1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xfff0e000 == 0xa5d0a000 {
                                                            return Some (LDNF1SB_SVE_ZtxN_S_H_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                }
                                            }
                                        }
                                    } else {
                                        if insn & 0x80000000 == 0 {
                                            if insn & 0x000010 == 0 {
                                                if insn & 0x100000 == 0 {
                                                    if insn & 0x400000 == 0 {
                                                        if insn & 0xfff0c210 == 0x2500c000 {
                                                            return Some (BRKPA_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xfff0c210 == 0x2540c000 {
                                                            return Some (BRKPAS_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x010000 == 0 {
                                                        if insn & 0x080000 == 0 {
                                                            if insn & 0xffffc21f == 0x2550c000 {
                                                                return Some (PTEST_SVE_Pg4_10_SVE_Pn :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0x000400 == 0 {
                                                                if insn & 0x001000 == 0 {
                                                                    if insn & 0x002000 == 0 {
                                                                        if insn & 0xfffffe10
                                                                            == 0x2558c000
                                                                        {
                                                                            return Some (PFIRST_SVE_Pd_SVE_Pg4_5_SVE_Pd :: make_opcode (insn)) ;
                                                                        }
                                                                    } else {
                                                                        if insn & 0xff3ffc10
                                                                            == 0x2518e000
                                                                        {
                                                                            return Some (PTRUE_SVE_Pd_SVE_PATTERN :: make_opcode (insn)) ;
                                                                        }
                                                                    }
                                                                } else {
                                                                    if insn & 0x400000 == 0 {
                                                                        if insn & 0xfffffe10
                                                                            == 0x2518f000
                                                                        {
                                                                            return Some (RDFFR_SVE_Pd_SVE_Pg4_5 :: make_opcode (insn)) ;
                                                                        }
                                                                    } else {
                                                                        if insn & 0xfffffe10
                                                                            == 0x2558f000
                                                                        {
                                                                            return Some (RDFFRS_SVE_Pd_SVE_Pg4_5 :: make_opcode (insn)) ;
                                                                        }
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0xfffffff0 == 0x2518e400 {
                                                                    return Some(
                                                                        PFALSE_SVE_PNd::make_opcode(
                                                                            insn,
                                                                        ),
                                                                    );
                                                                }
                                                                if insn & 0xfffffff0 == 0x2518e400 {
                                                                    return Some(
                                                                        PFALSE_SVE_PNd::make_opcode(
                                                                            insn,
                                                                        ),
                                                                    );
                                                                }
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x000400 == 0 {
                                                            if insn & 0x001000 == 0 {
                                                                if insn & 0xff3ffc10 == 0x2519e000 {
                                                                    return Some (PTRUES_SVE_Pd_SVE_PATTERN :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xfffffff0 == 0x2519f000 {
                                                                    return Some(
                                                                        RDFFR_SVE_Pd::make_opcode(
                                                                            insn,
                                                                        ),
                                                                    );
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0xff3ffe10 == 0x2519c400 {
                                                                return Some (PNEXT_SVE_Pd_SVE_Pg4_5_SVE_Pd :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0x400000 == 0 {
                                                    if insn & 0xfff0c210 == 0x2500c010 {
                                                        return Some (BRKPB_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm :: make_opcode (insn)) ;
                                                    }
                                                } else {
                                                    if insn & 0xfff0c210 == 0x2540c010 {
                                                        return Some (BRKPBS_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm :: make_opcode (insn)) ;
                                                    }
                                                }
                                            }
                                        } else {
                                            if insn & 0x002000 == 0 {
                                                if insn & 0x400000 == 0 {
                                                    if insn & 0x800000 == 0 {
                                                        if insn & 0xffe0e000 == 0xa500c000 {
                                                            return Some (LDNT1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2 :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xffe0e000 == 0xa580c000 {
                                                            return Some (LDNT1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL3 :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x800000 == 0 {
                                                        if insn & 0xffe0e000 == 0xa540c000 {
                                                            return Some (LD3W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2 :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xffe0e000 == 0xa5c0c000 {
                                                            return Some (LD3D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL3 :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0x100000 == 0 {
                                                    if insn & 0x400000 == 0 {
                                                        if insn & 0x800000 == 0 {
                                                            if insn & 0xfff0e000 == 0xa500e000 {
                                                                return Some (LDNT1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xfff0e000 == 0xa580e000 {
                                                                return Some (LDNT1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x800000 == 0 {
                                                            if insn & 0xfff0e000 == 0xa540e000 {
                                                                return Some (LD3W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x3xVL :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xfff0e000 == 0xa5c0e000 {
                                                                return Some (LD3D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x3xVL :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x800000 == 0 {
                                                        if insn & 0xfff0e000 == 0xa510e000 {
                                                            return Some (LD3Q_SME_Zt3_SVE_Pg3_SVE_ADDR_RI_S4x2xVL :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xfff0e000 == 0xa590e000 {
                                                            return Some (LD4Q_SME_Zt4_SVE_Pg3_SVE_ADDR_RI_S4x2xVL :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                }
                                            }
                                        }
                                    }
                                } else {
                                    if insn & 0x002000 == 0 {
                                        if insn & 0x80000000 == 0 {
                                            if insn & 0x004000 == 0 {
                                                if insn & 0x080000 == 0 {
                                                    if insn & 0x100000 == 0 {
                                                        if insn & 0x010000 == 0 {
                                                            if insn & 0x020000 == 0 {
                                                                if insn & 0x040000 == 0 {
                                                                    if insn & 0xffffe000
                                                                        == 0x65008000
                                                                    {
                                                                        return Some (BFADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 :: make_opcode (insn)) ;
                                                                    }
                                                                    if insn & 0xff3fe000
                                                                        == 0x65008000
                                                                    {
                                                                        return Some (FADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xffffe000
                                                                        == 0x65048000
                                                                    {
                                                                        return Some (BFMAXNM_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 :: make_opcode (insn)) ;
                                                                    }
                                                                    if insn & 0xff3fe000
                                                                        == 0x65048000
                                                                    {
                                                                        return Some (FMAXNM_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0x040000 == 0 {
                                                                    if insn & 0xffffe000
                                                                        == 0x65028000
                                                                    {
                                                                        return Some (BFMUL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 :: make_opcode (insn)) ;
                                                                    }
                                                                    if insn & 0xff3fe000
                                                                        == 0x65028000
                                                                    {
                                                                        return Some (FMUL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xffffe000
                                                                        == 0x65068000
                                                                    {
                                                                        return Some (BFMAX_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 :: make_opcode (insn)) ;
                                                                    }
                                                                    if insn & 0xff3fe000
                                                                        == 0x65068000
                                                                    {
                                                                        return Some (FMAX_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x020000 == 0 {
                                                                if insn & 0x040000 == 0 {
                                                                    if insn & 0xffffe000
                                                                        == 0x65018000
                                                                    {
                                                                        return Some (BFSUB_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 :: make_opcode (insn)) ;
                                                                    }
                                                                    if insn & 0xff3fe000
                                                                        == 0x65018000
                                                                    {
                                                                        return Some (FSUB_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xffffe000
                                                                        == 0x65058000
                                                                    {
                                                                        return Some (BFMINNM_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 :: make_opcode (insn)) ;
                                                                    }
                                                                    if insn & 0xff3fe000
                                                                        == 0x65058000
                                                                    {
                                                                        return Some (FMINNM_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0x040000 == 0 {
                                                                    if insn & 0xff3fe000
                                                                        == 0x65038000
                                                                    {
                                                                        return Some (FSUBR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xffffe000
                                                                        == 0x65078000
                                                                    {
                                                                        return Some (BFMIN_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 :: make_opcode (insn)) ;
                                                                    }
                                                                    if insn & 0xff3fe000
                                                                        == 0x65078000
                                                                    {
                                                                        return Some (FMIN_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0xff38fc00 == 0x65108000 {
                                                            return Some (FTMAD_SVE_Zd_SVE_Zd_SVE_Zm_5_SVE_UIMM3 :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x010000 == 0 {
                                                        if insn & 0x020000 == 0 {
                                                            if insn & 0x040000 == 0 {
                                                                if insn & 0x100000 == 0 {
                                                                    if insn & 0xff3fe000
                                                                        == 0x65088000
                                                                    {
                                                                        return Some (FABD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xff3fe3c0
                                                                        == 0x65188000
                                                                    {
                                                                        return Some (FADD_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_I1_HALF_ONE :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0x100000 == 0 {
                                                                    if insn & 0xff3fe000
                                                                        == 0x650c8000
                                                                    {
                                                                        return Some (FDIVR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xff3fe3c0
                                                                        == 0x651c8000
                                                                    {
                                                                        return Some (FMAXNM_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_I1_ZERO_ONE :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x040000 == 0 {
                                                                if insn & 0x100000 == 0 {
                                                                    if insn & 0xff3fe000
                                                                        == 0x650a8000
                                                                    {
                                                                        return Some (FMULX_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xff3fe3c0
                                                                        == 0x651a8000
                                                                    {
                                                                        return Some (FMUL_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_I1_HALF_TWO :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0xff3fe3c0 == 0x651e8000 {
                                                                    return Some (FMAX_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_I1_ZERO_ONE :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x020000 == 0 {
                                                            if insn & 0x040000 == 0 {
                                                                if insn & 0x100000 == 0 {
                                                                    if insn & 0xff3fe000
                                                                        == 0x65098000
                                                                    {
                                                                        return Some (FSCALE_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xff3fe3c0
                                                                        == 0x65198000
                                                                    {
                                                                        return Some (FSUB_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_I1_HALF_ONE :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0x100000 == 0 {
                                                                    if insn & 0xff3fe000
                                                                        == 0x650d8000
                                                                    {
                                                                        return Some (FDIV_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5 :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xff3fe3c0
                                                                        == 0x651d8000
                                                                    {
                                                                        return Some (FMINNM_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_I1_ZERO_ONE :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x040000 == 0 {
                                                                if insn & 0xff3fe3c0 == 0x651b8000 {
                                                                    return Some (FSUBR_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_I1_HALF_ONE :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xff3fe3c0 == 0x651f8000 {
                                                                    return Some (FMIN_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_I1_ZERO_ONE :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0x000010 == 0 {
                                                    if insn & 0xff20e010 == 0x6500c000 {
                                                        return Some (FCMUO_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                    }
                                                } else {
                                                    if insn & 0xff20e010 == 0x6500c010 {
                                                        return Some (FACGE_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                    }
                                                }
                                            }
                                        } else {
                                            if insn & 0x400000 == 0 {
                                                if insn & 0x800000 == 0 {
                                                    if insn & 0xffe0a000 == 0xe5008000 {
                                                        return Some (ST1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_14 :: make_opcode (insn)) ;
                                                    }
                                                } else {
                                                    if insn & 0xffe0a000 == 0xe5808000 {
                                                        return Some (ST1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW_14 :: make_opcode (insn)) ;
                                                    }
                                                }
                                            } else {
                                                if insn & 0xffe0a000 == 0xe5408000 {
                                                    return Some (ST1W_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_RZ_XTW_14 :: make_opcode (insn)) ;
                                                }
                                            }
                                        }
                                    } else {
                                        if insn & 0x004000 == 0 {
                                            if insn & 0x80000000 == 0 {
                                                if insn & 0x010000 == 0 {
                                                    if insn & 0x080000 == 0 {
                                                        if insn & 0x020000 == 0 {
                                                            if insn & 0x040000 == 0 {
                                                                if insn & 0x100000 == 0 {
                                                                    if insn & 0xff3fe000
                                                                        == 0x6500a000
                                                                    {
                                                                        return Some (FRINTN_SVE_Zd_SVE_Pg3_SVE_Zn :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xffffe000
                                                                        == 0x65d0a000
                                                                    {
                                                                        return Some (SCVTF_SVE_Zd_SVE_Pg3_SVE_Zn :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0x100000 == 0 {
                                                                    if insn & 0xff3fe000
                                                                        == 0x6504a000
                                                                    {
                                                                        return Some (FRINTA_SVE_Zd_SVE_Pg3_SVE_Zn :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0x400000 == 0 {
                                                                        if insn & 0xffffe000
                                                                            == 0x6594a000
                                                                        {
                                                                            return Some (SCVTF_SVE_Zd_S_S_SVE_Pg3_P_M_SVE_Zn_S_S :: make_opcode (insn)) ;
                                                                        }
                                                                    } else {
                                                                        if insn & 0x800000 == 0 {
                                                                            if insn & 0xffffe000
                                                                                == 0x6554a000
                                                                            {
                                                                                return Some (SCVTF_SVE_Zd_S_H_SVE_Pg3_P_M_SVE_Zn_S_S :: make_opcode (insn)) ;
                                                                            }
                                                                        } else {
                                                                            if insn & 0xffffe000
                                                                                == 0x65d4a000
                                                                            {
                                                                                return Some (SCVTF_SVE_Zd_S_S_SVE_Pg3_P_M_SVE_Zn_S_D :: make_opcode (insn)) ;
                                                                            }
                                                                        }
                                                                    }
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x040000 == 0 {
                                                                if insn & 0x100000 == 0 {
                                                                    if insn & 0xff3fe000
                                                                        == 0x6502a000
                                                                    {
                                                                        return Some (FRINTM_SVE_Zd_SVE_Pg3_SVE_Zn :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xffffe000
                                                                        == 0x6552a000
                                                                    {
                                                                        return Some (SCVTF_SVE_Zd_S_H_SVE_Pg3_P_M_SVE_Zn_S_H :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0x100000 == 0 {
                                                                    if insn & 0xff3fe000
                                                                        == 0x6506a000
                                                                    {
                                                                        return Some (FRINTX_SVE_Zd_SVE_Pg3_SVE_Zn :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0x800000 == 0 {
                                                                        if insn & 0xffffe000
                                                                            == 0x6556a000
                                                                        {
                                                                            return Some (SCVTF_SVE_Zd_S_H_SVE_Pg3_P_M_SVE_Zn_S_D :: make_opcode (insn)) ;
                                                                        }
                                                                    } else {
                                                                        if insn & 0xffffe000
                                                                            == 0x65d6a000
                                                                        {
                                                                            return Some (SCVTF_SVE_Zd_S_D_SVE_Pg3_P_M_SVE_Zn_S_D :: make_opcode (insn)) ;
                                                                        }
                                                                    }
                                                                }
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x100000 == 0 {
                                                            if insn & 0x020000 == 0 {
                                                                if insn & 0x040000 == 0 {
                                                                    if insn & 0x400000 == 0 {
                                                                        if insn & 0xffffe000
                                                                            == 0x6588a000
                                                                        {
                                                                            return Some (FCVT_SVE_Zd_SVE_Pg3_SVE_Zn :: make_opcode (insn)) ;
                                                                        }
                                                                    } else {
                                                                        if insn & 0xffffe000
                                                                            == 0x65c8a000
                                                                        {
                                                                            return Some (FCVT_SVE_Zd_S_H_SVE_Pg3_P_M_SVE_Zn_S_D :: make_opcode (insn)) ;
                                                                        }
                                                                    }
                                                                } else {
                                                                    if insn & 0xff3fe000
                                                                        == 0x650ca000
                                                                    {
                                                                        return Some (FRECPX_SVE_Zd_SVE_Pg3_SVE_Zn :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0x400000 == 0 {
                                                                    if insn & 0x800000 == 0 {
                                                                        if insn & 0xffffe000
                                                                            == 0x650aa000
                                                                        {
                                                                            return Some (FCVTX_SVE_Zd_SVE_Pg3_SVE_Zn :: make_opcode (insn)) ;
                                                                        }
                                                                    } else {
                                                                        if insn & 0xffffe000
                                                                            == 0x658aa000
                                                                        {
                                                                            return Some (BFCVT_SVE_Zd_SVE_Pg3_SVE_Zn :: make_opcode (insn)) ;
                                                                        }
                                                                    }
                                                                } else {
                                                                    if insn & 0xffffe000
                                                                        == 0x65caa000
                                                                    {
                                                                        return Some (FCVT_SVE_Zd_S_S_SVE_Pg3_P_M_SVE_Zn_S_D :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x400000 == 0 {
                                                                if insn & 0x800000 == 0 {
                                                                    if insn & 0xfff9e000
                                                                        == 0x6518a000
                                                                    {
                                                                        return Some (FLOGB_SVE_Zd_SVE_Pg3_SVE_Zn :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xffffe000
                                                                        == 0x659ca000
                                                                    {
                                                                        return Some (FCVTZS_SVE_Zd_SVE_Pg3_SVE_Zn :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0x020000 == 0 {
                                                                    if insn & 0x040000 == 0 {
                                                                        if insn & 0xffffe000
                                                                            == 0x65d8a000
                                                                        {
                                                                            return Some (FCVTZS_SVE_Zd_S_S_SVE_Pg3_P_M_SVE_Zn_S_D :: make_opcode (insn)) ;
                                                                        }
                                                                    } else {
                                                                        if insn & 0x800000 == 0 {
                                                                            if insn & 0xffffe000
                                                                                == 0x655ca000
                                                                            {
                                                                                return Some (FCVTZS_SVE_Zd_S_S_SVE_Pg3_P_M_SVE_Zn_S_H :: make_opcode (insn)) ;
                                                                            }
                                                                        } else {
                                                                            if insn & 0xffffe000
                                                                                == 0x65dca000
                                                                            {
                                                                                return Some (FCVTZS_SVE_Zd_S_D_SVE_Pg3_P_M_SVE_Zn_S_S :: make_opcode (insn)) ;
                                                                            }
                                                                        }
                                                                    }
                                                                } else {
                                                                    if insn & 0x040000 == 0 {
                                                                        if insn & 0xffffe000
                                                                            == 0x655aa000
                                                                        {
                                                                            return Some (FCVTZS_SVE_Zd_S_H_SVE_Pg3_P_M_SVE_Zn_S_H :: make_opcode (insn)) ;
                                                                        }
                                                                    } else {
                                                                        if insn & 0x800000 == 0 {
                                                                            if insn & 0xffffe000
                                                                                == 0x655ea000
                                                                            {
                                                                                return Some (FCVTZS_SVE_Zd_S_D_SVE_Pg3_P_M_SVE_Zn_S_H :: make_opcode (insn)) ;
                                                                            }
                                                                        } else {
                                                                            if insn & 0xffffe000
                                                                                == 0x65dea000
                                                                            {
                                                                                return Some (FCVTZS_SVE_Zd_S_D_SVE_Pg3_P_M_SVE_Zn_S_D :: make_opcode (insn)) ;
                                                                            }
                                                                        }
                                                                    }
                                                                }
                                                            }
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x020000 == 0 {
                                                        if insn & 0x040000 == 0 {
                                                            if insn & 0x080000 == 0 {
                                                                if insn & 0x100000 == 0 {
                                                                    if insn & 0xff3fe000
                                                                        == 0x6501a000
                                                                    {
                                                                        return Some (FRINTP_SVE_Zd_SVE_Pg3_SVE_Zn :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xffffe000
                                                                        == 0x65d1a000
                                                                    {
                                                                        return Some (UCVTF_SVE_Zd_SVE_Pg3_SVE_Zn :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0x100000 == 0 {
                                                                    if insn & 0x400000 == 0 {
                                                                        if insn & 0xffffe000
                                                                            == 0x6589a000
                                                                        {
                                                                            return Some (FCVT_SVE_Zd_S_S_SVE_Pg3_P_M_SVE_Zn_S_H :: make_opcode (insn)) ;
                                                                        }
                                                                    } else {
                                                                        if insn & 0xffffe000
                                                                            == 0x65c9a000
                                                                        {
                                                                            return Some (FCVT_SVE_Zd_S_D_SVE_Pg3_P_M_SVE_Zn_S_H :: make_opcode (insn)) ;
                                                                        }
                                                                    }
                                                                } else {
                                                                    if insn & 0xffffe000
                                                                        == 0x65d9a000
                                                                    {
                                                                        return Some (FCVTZU_SVE_Zd_SVE_Pg3_SVE_Zn :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x080000 == 0 {
                                                                if insn & 0x400000 == 0 {
                                                                    if insn & 0xffffe000
                                                                        == 0x6595a000
                                                                    {
                                                                        return Some (UCVTF_SVE_Zd_S_S_SVE_Pg3_P_M_SVE_Zn_S_S :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0x800000 == 0 {
                                                                        if insn & 0xffffe000
                                                                            == 0x6555a000
                                                                        {
                                                                            return Some (UCVTF_SVE_Zd_S_H_SVE_Pg3_P_M_SVE_Zn_S_S :: make_opcode (insn)) ;
                                                                        }
                                                                    } else {
                                                                        if insn & 0xffffe000
                                                                            == 0x65d5a000
                                                                        {
                                                                            return Some (UCVTF_SVE_Zd_S_S_SVE_Pg3_P_M_SVE_Zn_S_D :: make_opcode (insn)) ;
                                                                        }
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0x100000 == 0 {
                                                                    if insn & 0xff3fe000
                                                                        == 0x650da000
                                                                    {
                                                                        return Some (FSQRT_SVE_Zd_SVE_Pg3_SVE_Zn :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0x400000 == 0 {
                                                                        if insn & 0xffffe000
                                                                            == 0x659da000
                                                                        {
                                                                            return Some (FCVTZU_SVE_Zd_S_S_SVE_Pg3_P_M_SVE_Zn_S_S :: make_opcode (insn)) ;
                                                                        }
                                                                    } else {
                                                                        if insn & 0x800000 == 0 {
                                                                            if insn & 0xffffe000
                                                                                == 0x655da000
                                                                            {
                                                                                return Some (FCVTZU_SVE_Zd_S_S_SVE_Pg3_P_M_SVE_Zn_S_H :: make_opcode (insn)) ;
                                                                            }
                                                                        } else {
                                                                            if insn & 0xffffe000
                                                                                == 0x65dda000
                                                                            {
                                                                                return Some (FCVTZU_SVE_Zd_S_D_SVE_Pg3_P_M_SVE_Zn_S_S :: make_opcode (insn)) ;
                                                                            }
                                                                        }
                                                                    }
                                                                }
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x040000 == 0 {
                                                            if insn & 0x080000 == 0 {
                                                                if insn & 0x100000 == 0 {
                                                                    if insn & 0xff3fe000
                                                                        == 0x6503a000
                                                                    {
                                                                        return Some (FRINTZ_SVE_Zd_SVE_Pg3_SVE_Zn :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xffffe000
                                                                        == 0x6553a000
                                                                    {
                                                                        return Some (UCVTF_SVE_Zd_S_H_SVE_Pg3_P_M_SVE_Zn_S_H :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0x100000 == 0 {
                                                                    if insn & 0xffffe000
                                                                        == 0x65cba000
                                                                    {
                                                                        return Some (FCVT_SVE_Zd_S_D_SVE_Pg3_P_M_SVE_Zn_S_S :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xffffe000
                                                                        == 0x655ba000
                                                                    {
                                                                        return Some (FCVTZU_SVE_Zd_S_H_SVE_Pg3_P_M_SVE_Zn_S_H :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x080000 == 0 {
                                                                if insn & 0x100000 == 0 {
                                                                    if insn & 0xff3fe000
                                                                        == 0x6507a000
                                                                    {
                                                                        return Some (FRINTI_SVE_Zd_SVE_Pg3_SVE_Zn :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0x800000 == 0 {
                                                                        if insn & 0xffffe000
                                                                            == 0x6557a000
                                                                        {
                                                                            return Some (UCVTF_SVE_Zd_S_H_SVE_Pg3_P_M_SVE_Zn_S_D :: make_opcode (insn)) ;
                                                                        }
                                                                    } else {
                                                                        if insn & 0xffffe000
                                                                            == 0x65d7a000
                                                                        {
                                                                            return Some (UCVTF_SVE_Zd_S_D_SVE_Pg3_P_M_SVE_Zn_S_D :: make_opcode (insn)) ;
                                                                        }
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0x800000 == 0 {
                                                                    if insn & 0xffffe000
                                                                        == 0x655fa000
                                                                    {
                                                                        return Some (FCVTZU_SVE_Zd_S_D_SVE_Pg3_P_M_SVE_Zn_S_H :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xffffe000
                                                                        == 0x65dfa000
                                                                    {
                                                                        return Some (FCVTZU_SVE_Zd_S_D_SVE_Pg3_P_M_SVE_Zn_S_D :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            }
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0x400000 == 0 {
                                                    if insn & 0x800000 == 0 {
                                                        if insn & 0xffe0e000 == 0xe500a000 {
                                                            return Some (ST1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xffe0e000 == 0xe580a000 {
                                                            return Some (ST1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x800000 == 0 {
                                                        if insn & 0xffe0e000 == 0xe540a000 {
                                                            return Some (ST1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x4 :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xffe0e000 == 0xe5c0a000 {
                                                            return Some (ST1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_ZI_U5x8 :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                }
                                            }
                                        } else {
                                            if insn & 0x80000000 == 0 {
                                                if insn & 0xff20e010 == 0x6500e010 {
                                                    return Some (FACGT_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16 :: make_opcode (insn)) ;
                                                }
                                            } else {
                                                if insn & 0x100000 == 0 {
                                                    if insn & 0xfff0e000 == 0xe540e000 {
                                                        return Some (ST1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL :: make_opcode (insn)) ;
                                                    }
                                                } else {
                                                    if insn & 0x400000 == 0 {
                                                        if insn & 0x800000 == 0 {
                                                            if insn & 0xfff0e000 == 0xe510e000 {
                                                                return Some (STNT1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xfff0e000 == 0xe590e000 {
                                                                return Some (STNT1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x800000 == 0 {
                                                            if insn & 0xfff0e000 == 0xe550e000 {
                                                                return Some (ST3W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x3xVL :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xfff0e000 == 0xe5d0e000 {
                                                                return Some (ST3D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x3xVL :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    }
                                                }
                                            }
                                        }
                                    }
                                }
                            } else {
                                if insn & 0x40000000 == 0 {
                                    if insn & 0x004000 == 0 {
                                        if insn & 0x80000000 == 0 {
                                            if insn & 0x000200 == 0 {
                                                if insn & 0x010000 == 0 {
                                                    if insn & 0x020000 == 0 {
                                                        if insn & 0x040000 == 0 {
                                                            if insn & 0x080000 == 0 {
                                                                if insn & 0xff3fc200 == 0x25208000 {
                                                                    return Some (CNTP_Rd_SVE_Pg4_10_SVE_Pn :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0x000400 == 0 {
                                                                    if insn & 0x000800 == 0 {
                                                                        if insn & 0x001000 == 0 {
                                                                            if insn & 0xff3ffe00
                                                                                == 0x25288000
                                                                            {
                                                                                return Some (SQINCP_SVE_Zd_SVE_Pg4_5 :: make_opcode (insn)) ;
                                                                            }
                                                                        } else {
                                                                            if insn & 0xfffffe1f
                                                                                == 0x25289000
                                                                            {
                                                                                return Some (WRFFR_SVE_Pn :: make_opcode (insn)) ;
                                                                            }
                                                                        }
                                                                    } else {
                                                                        if insn & 0xff3ffe00
                                                                            == 0x25288800
                                                                        {
                                                                            return Some (SQINCP_Rd_SVE_Pg4_5_Rd :: make_opcode (insn)) ;
                                                                        }
                                                                    }
                                                                } else {
                                                                    if insn & 0xff3ffe00
                                                                        == 0x25288c00
                                                                    {
                                                                        return Some (SQINCP_Rd_SVE_Pg4_5 :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x000800 == 0 {
                                                                if insn & 0x001000 == 0 {
                                                                    if insn & 0xff3ffe00
                                                                        == 0x252c8000
                                                                    {
                                                                        return Some (INCP_SVE_Zd_SVE_Pg4_5 :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn == 0x252c9000 {
                                                                        return Some(
                                                                            SETFFR::make_opcode(
                                                                                insn,
                                                                            ),
                                                                        );
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0xff3ffe00 == 0x252c8800 {
                                                                    return Some (INCP_Rd_SVE_Pg4_5 :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x000400 == 0 {
                                                            if insn & 0x000800 == 0 {
                                                                if insn & 0xff3ffe00 == 0x252a8000 {
                                                                    return Some (SQDECP_SVE_Zd_SVE_Pg4_5 :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xff3ffe00 == 0x252a8800 {
                                                                    return Some (SQDECP_Rd_SVE_Pg4_5_Rd :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0xff3ffe00 == 0x252a8c00 {
                                                                return Some (SQDECP_Rd_SVE_Pg4_5 :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x000400 == 0 {
                                                        if insn & 0x000800 == 0 {
                                                            if insn & 0x020000 == 0 {
                                                                if insn & 0x040000 == 0 {
                                                                    if insn & 0xff3ffe00
                                                                        == 0x25298000
                                                                    {
                                                                        return Some (UQINCP_SVE_Zd_SVE_Pg4_5 :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xff3ffe00
                                                                        == 0x252d8000
                                                                    {
                                                                        return Some (DECP_SVE_Zd_SVE_Pg4_5 :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0xff3ffe00 == 0x252b8000 {
                                                                    return Some (UQDECP_SVE_Zd_SVE_Pg4_5 :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x020000 == 0 {
                                                                if insn & 0x040000 == 0 {
                                                                    if insn & 0xff3ffe00
                                                                        == 0x25298800
                                                                    {
                                                                        return Some (UQINCP_Rd_SVE_Pg4_5 :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xff3ffe00
                                                                        == 0x252d8800
                                                                    {
                                                                        return Some (DECP_Rd_SVE_Pg4_5 :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0xff3ffe00 == 0x252b8800 {
                                                                    return Some (UQDECP_Rd_SVE_Pg4_5 :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x020000 == 0 {
                                                            if insn & 0xff3ffe00 == 0x25298c00 {
                                                                return Some (UQINCP_Rd_X_SVE_Pg4_5_S_B :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xff3ffe00 == 0x252b8c00 {
                                                                return Some (UQDECP_Rd_X_SVE_Pg4_5_S_B :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0xff3ffa00 == 0x25208200 {
                                                    return Some(
                                                        CNTP_Rd_SME_PNn_SME_VLxN_10::make_opcode(
                                                            insn,
                                                        ),
                                                    );
                                                }
                                            }
                                        } else {
                                            if insn & 0x002000 == 0 {
                                                if insn & 0x800000 == 0 {
                                                    if insn & 0xffe0e000 == 0xa5208000 {
                                                        return Some (LD3Q_SME_Zt3_SVE_Pg3_SVE_ADDR_RR_LSL4 :: make_opcode (insn)) ;
                                                    }
                                                } else {
                                                    if insn & 0xffe0e000 == 0xa5a08000 {
                                                        return Some (LD4Q_SME_Zt4_SVE_Pg3_SVE_ADDR_RR_LSL4 :: make_opcode (insn)) ;
                                                    }
                                                }
                                            } else {
                                                if insn & 0x100000 == 0 {
                                                    if insn & 0x400000 == 0 {
                                                        if insn & 0x800000 == 0 {
                                                            if insn & 0xfff0e000 == 0xa520a000 {
                                                                return Some (LD1SH_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xfff0e000 == 0xa5a0a000 {
                                                                return Some (LD1SB_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x800000 == 0 {
                                                            if insn & 0xfff0e000 == 0xa560a000 {
                                                                return Some (LD1W_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xfff0e000 == 0xa5e0a000 {
                                                                return Some (LD1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x400000 == 0 {
                                                        if insn & 0x800000 == 0 {
                                                            if insn & 0xfff0e000 == 0xa530a000 {
                                                                return Some (LDNF1SH_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xfff0e000 == 0xa5b0a000 {
                                                                return Some (LDNF1SB_SVE_ZtxN_S_S_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x800000 == 0 {
                                                            if insn & 0xfff0e000 == 0xa570a000 {
                                                                return Some (LDNF1W_SVE_ZtxN_S_D_SVE_Pg3_P_Z_SVE_ADDR_RI_S4xVL :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xfff0e000 == 0xa5f0a000 {
                                                                return Some (LDNF1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    }
                                                }
                                            }
                                        }
                                    } else {
                                        if insn & 0x80000000 == 0 {
                                            if insn & 0x010000 == 0 {
                                                if insn & 0x020000 == 0 {
                                                    if insn & 0x040000 == 0 {
                                                        if insn & 0x080000 == 0 {
                                                            if insn & 0x100000 == 0 {
                                                                if insn & 0xff3fc000 == 0x2520c000 {
                                                                    return Some (ADD_SVE_Zd_SVE_Zd_SVE_AIMM :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xff3fe000 == 0x2530c000 {
                                                                    return Some (MUL_SVE_Zd_SVE_Zd_SVE_SIMM8 :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x100000 == 0 {
                                                                if insn & 0xff3fe000 == 0x2528c000 {
                                                                    return Some (SMAX_SVE_Zd_SVE_Zd_SVE_SIMM8 :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xff3fc000 == 0x2538c000 {
                                                                    return Some (DUP_SVE_Zd_SVE_ASIMM :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0xff3fc000 == 0x2524c000 {
                                                            return Some (SQADD_SVE_Zd_SVE_Zd_SVE_AIMM :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x040000 == 0 {
                                                        if insn & 0xff3fe000 == 0x252ac000 {
                                                            return Some (SMIN_SVE_Zd_SVE_Zd_SVE_SIMM8 :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xff3fc000 == 0x2526c000 {
                                                            return Some (SQSUB_SVE_Zd_SVE_Zd_SVE_AIMM :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0x020000 == 0 {
                                                    if insn & 0x040000 == 0 {
                                                        if insn & 0x080000 == 0 {
                                                            if insn & 0xff3fc000 == 0x2521c000 {
                                                                return Some (SUB_SVE_Zd_SVE_Zd_SVE_AIMM :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0x100000 == 0 {
                                                                if insn & 0xff3fe000 == 0x2529c000 {
                                                                    return Some (UMAX_SVE_Zd_SVE_Zd_SVE_UIMM8 :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xff3fe000 == 0x2539c000 {
                                                                    return Some (FDUP_SVE_Zd_SVE_FPIMM8 :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0xff3fc000 == 0x2525c000 {
                                                            return Some (UQADD_SVE_Zd_SVE_Zd_SVE_AIMM :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x040000 == 0 {
                                                        if insn & 0x080000 == 0 {
                                                            if insn & 0xff3fc000 == 0x2523c000 {
                                                                return Some (SUBR_SVE_Zd_SVE_Zd_SVE_AIMM :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xff3fe000 == 0x252bc000 {
                                                                return Some (UMIN_SVE_Zd_SVE_Zd_SVE_UIMM8 :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0xff3fc000 == 0x2527c000 {
                                                            return Some (UQSUB_SVE_Zd_SVE_Zd_SVE_AIMM :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                }
                                            }
                                        } else {
                                            if insn & 0x002000 == 0 {
                                                if insn & 0x400000 == 0 {
                                                    if insn & 0x800000 == 0 {
                                                        if insn & 0xffe0e000 == 0xa520c000 {
                                                            return Some (LD2W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2 :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xffe0e000 == 0xa5a0c000 {
                                                            return Some (LD2D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL3 :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x800000 == 0 {
                                                        if insn & 0xffe0e000 == 0xa560c000 {
                                                            return Some (LD4W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL2 :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xffe0e000 == 0xa5e0c000 {
                                                            return Some (LD4D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RX_LSL3 :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0x400000 == 0 {
                                                    if insn & 0x800000 == 0 {
                                                        if insn & 0xfff0e000 == 0xa520e000 {
                                                            return Some (LD2W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x2xVL :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xfff0e000 == 0xa5a0e000 {
                                                            return Some (LD2D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x2xVL :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x800000 == 0 {
                                                        if insn & 0xfff0e000 == 0xa560e000 {
                                                            return Some (LD4W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x4xVL :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xfff0e000 == 0xa5e0e000 {
                                                            return Some (LD4D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x4xVL :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                }
                                            }
                                        }
                                    }
                                } else {
                                    if insn & 0x002000 == 0 {
                                        if insn & 0x80000000 == 0 {
                                            if insn & 0x004000 == 0 {
                                                if insn & 0xff20e000 == 0x65208000 {
                                                    return Some (FMAD_SVE_Zd_SVE_Pg3_SVE_Zm_5_SVE_Za_16 :: make_opcode (insn)) ;
                                                }
                                            } else {
                                                if insn & 0xff20e000 == 0x6520c000 {
                                                    return Some (FNMAD_SVE_Zd_SVE_Pg3_SVE_Zm_5_SVE_Za_16 :: make_opcode (insn)) ;
                                                }
                                            }
                                        } else {
                                            if insn & 0x400000 == 0 {
                                                if insn & 0x800000 == 0 {
                                                    if insn & 0xffe0a000 == 0xe5208000 {
                                                        return Some (ST1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW2_14 :: make_opcode (insn)) ;
                                                    }
                                                } else {
                                                    if insn & 0xffe0a000 == 0xe5a08000 {
                                                        return Some (ST1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_XTW3_14 :: make_opcode (insn)) ;
                                                    }
                                                }
                                            } else {
                                                if insn & 0xffe0a000 == 0xe5608000 {
                                                    return Some (ST1W_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_RZ_XTW2_14 :: make_opcode (insn)) ;
                                                }
                                            }
                                        }
                                    } else {
                                        if insn & 0x004000 == 0 {
                                            if insn & 0x80000000 == 0 {
                                                if insn & 0xff20e000 == 0x6520a000 {
                                                    return Some (FMSB_SVE_Zd_SVE_Pg3_SVE_Zm_5_SVE_Za_16 :: make_opcode (insn)) ;
                                                }
                                            } else {
                                                if insn & 0x400000 == 0 {
                                                    if insn & 0x800000 == 0 {
                                                        if insn & 0xffe0e000 == 0xe520a000 {
                                                            return Some (ST1W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL2 :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xffe0e000 == 0xe5a0a000 {
                                                            return Some (ST1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RZ_LSL3 :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0xffe0e000 == 0xe560a000 {
                                                        return Some (ST1W_SVE_ZtxN_S_S_SVE_Pg3_SVE_ADDR_ZI_U5x4 :: make_opcode (insn)) ;
                                                    }
                                                }
                                            }
                                        } else {
                                            if insn & 0x80000000 == 0 {
                                                if insn & 0xff20e000 == 0x6520e000 {
                                                    return Some (FNMSB_SVE_Zd_SVE_Pg3_SVE_Zm_5_SVE_Za_16 :: make_opcode (insn)) ;
                                                }
                                            } else {
                                                if insn & 0x100000 == 0 {
                                                    if insn & 0x800000 == 0 {
                                                        if insn & 0xfff0e000 == 0xe560e000 {
                                                            return Some (ST1W_SVE_ZtxN_S_D_SVE_Pg3_SVE_ADDR_RI_S4xVL :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xfff0e000 == 0xe5e0e000 {
                                                            return Some (ST1D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4xVL :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x400000 == 0 {
                                                        if insn & 0x800000 == 0 {
                                                            if insn & 0xfff0e000 == 0xe530e000 {
                                                                return Some (ST2W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x2xVL :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xfff0e000 == 0xe5b0e000 {
                                                                return Some (ST2D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x2xVL :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x800000 == 0 {
                                                            if insn & 0xfff0e000 == 0xe570e000 {
                                                                return Some (ST4W_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x4xVL :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xfff0e000 == 0xe5f0e000 {
                                                                return Some (ST4D_SVE_ZtxN_SVE_Pg3_SVE_ADDR_RI_S4x4xVL :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    }
                                                }
                                            }
                                        }
                                    }
                                }
                            }
                        }
                    }
                }
            } else {
                if insn & 0x20000000 == 0 {
                    if insn & 0x40000000 == 0 {
                        if insn & 0x80000000 == 0 {
                            if insn & 0xfc000000 == 0x14000000 {
                                return Some(B_ADDR_PCREL26::make_opcode(insn));
                            }
                        } else {
                            if insn & 0xfc000000 == 0x94000000 {
                                return Some(BL_ADDR_PCREL26::make_opcode(insn));
                            }
                        }
                    } else {
                        if insn & 0x1000000 == 0 {
                            if insn & 0x000010 == 0 {
                                if insn & 0x2000000 == 0 {
                                    if insn & 0x80000000 == 0 {
                                        if insn & 0xff000010 == 0x54000000 {
                                            return Some(B__ADDR_PCREL19::make_opcode(insn));
                                        }
                                    } else {
                                        if insn & 0x000001 == 0 {
                                            if insn & 0x000002 == 0 {
                                                if insn & 0x200000 == 0 {
                                                    if insn & 0xffe0001f == 0xd4400000 {
                                                        return Some(HLT_EXCEPTION::make_opcode(
                                                            insn,
                                                        ));
                                                    }
                                                } else {
                                                    if insn & 0x400000 == 0 {
                                                        if insn & 0xffe0001f == 0xd4200000 {
                                                            return Some(
                                                                BRK_EXCEPTION::make_opcode(insn),
                                                            );
                                                        }
                                                    } else {
                                                        if insn & 0xffe0001f == 0xd4600000 {
                                                            return Some(
                                                                TCANCEL_TME_UIMM16::make_opcode(
                                                                    insn,
                                                                ),
                                                            );
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0x200000 == 0 {
                                                    if insn & 0xffe0001f == 0xd4000002 {
                                                        return Some(HVC_EXCEPTION::make_opcode(
                                                            insn,
                                                        ));
                                                    }
                                                } else {
                                                    if insn & 0xffe0001f == 0xd4a00002 {
                                                        return Some(DCPS2_EXCEPTION::make_opcode(
                                                            insn,
                                                        ));
                                                    }
                                                }
                                            }
                                        } else {
                                            if insn & 0x000002 == 0 {
                                                if insn & 0x200000 == 0 {
                                                    if insn & 0xffe0001f == 0xd4000001 {
                                                        return Some(SVC_EXCEPTION::make_opcode(
                                                            insn,
                                                        ));
                                                    }
                                                } else {
                                                    if insn & 0xffe0001f == 0xd4a00001 {
                                                        return Some(DCPS1_EXCEPTION::make_opcode(
                                                            insn,
                                                        ));
                                                    }
                                                }
                                            } else {
                                                if insn & 0x200000 == 0 {
                                                    if insn & 0xffe0001f == 0xd4000003 {
                                                        return Some(SMC_EXCEPTION::make_opcode(
                                                            insn,
                                                        ));
                                                    }
                                                } else {
                                                    if insn & 0xffe0001f == 0xd4a00003 {
                                                        return Some(DCPS3_EXCEPTION::make_opcode(
                                                            insn,
                                                        ));
                                                    }
                                                }
                                            }
                                        }
                                    }
                                } else {
                                    if insn & 0x200000 == 0 {
                                        if insn & 0x400000 == 0 {
                                            if insn & 0x800000 == 0 {
                                                if insn & 0xfffffc1f == 0xd61f0000 {
                                                    return Some(BR_Rn::make_opcode(insn));
                                                }
                                            } else {
                                                if insn == 0xd69f03e0 {
                                                    return Some(ERET::make_opcode(insn));
                                                }
                                            }
                                        } else {
                                            if insn & 0xfffffc1f == 0xd65f0000 {
                                                return Some(RET_Rn::make_opcode(insn));
                                            }
                                        }
                                    } else {
                                        if insn & 0x800000 == 0 {
                                            if insn & 0xfffffc1f == 0xd63f0000 {
                                                return Some(BLR_Rn::make_opcode(insn));
                                            }
                                        } else {
                                            if insn == 0xd6bf03e0 {
                                                return Some(DRPS::make_opcode(insn));
                                            }
                                        }
                                    }
                                }
                            } else {
                                if insn & 0x2000000 == 0 {
                                    if insn & 0xff000010 == 0x54000010 {
                                        return Some(BC__ADDR_PCREL19::make_opcode(insn));
                                    }
                                } else {
                                    if insn & 0x000400 == 0 {
                                        if insn & 0x200000 == 0 {
                                            if insn & 0x400000 == 0 {
                                                if insn & 0x800000 == 0 {
                                                    if insn & 0xfffffc1f == 0xd61f081f {
                                                        return Some(BRAAZ_Rn::make_opcode(insn));
                                                    }
                                                } else {
                                                    if insn == 0xd69f0bff {
                                                        return Some(ERETAA::make_opcode(insn));
                                                    }
                                                }
                                            } else {
                                                if insn == 0xd65f0bff {
                                                    return Some(RETAA::make_opcode(insn));
                                                }
                                            }
                                        } else {
                                            if insn & 0xfffffc1f == 0xd63f081f {
                                                return Some(BLRAAZ_Rn::make_opcode(insn));
                                            }
                                        }
                                    } else {
                                        if insn & 0x200000 == 0 {
                                            if insn & 0x400000 == 0 {
                                                if insn & 0x800000 == 0 {
                                                    if insn & 0xfffffc1f == 0xd61f0c1f {
                                                        return Some(BRABZ_Rn::make_opcode(insn));
                                                    }
                                                } else {
                                                    if insn == 0xd69f0fff {
                                                        return Some(ERETAB::make_opcode(insn));
                                                    }
                                                }
                                            } else {
                                                if insn == 0xd65f0fff {
                                                    return Some(RETAB::make_opcode(insn));
                                                }
                                            }
                                        } else {
                                            if insn & 0xfffffc1f == 0xd63f0c1f {
                                                return Some(BLRABZ_Rn::make_opcode(insn));
                                            }
                                        }
                                    }
                                }
                            }
                        } else {
                            if insn & 0x200000 == 0 {
                                if insn & 0x400000 == 0 {
                                    if insn & 0x2000000 == 0 {
                                        if insn == 0xd500403f {
                                            return Some(XAFLAG::make_opcode(insn));
                                        }
                                        if insn == 0xd500405f {
                                            return Some(AXFLAG::make_opcode(insn));
                                        }
                                        if insn == 0xd503307f {
                                            return Some(TCOMMIT::make_opcode(insn));
                                        }
                                        if insn == 0xd503477f {
                                            return Some(SMSTART::make_opcode(insn));
                                        }
                                        if insn == 0xd503467f {
                                            return Some(SMSTOP::make_opcode(insn));
                                        }
                                        if insn == 0xd503251f {
                                            return Some(CHKFEAT_X16::make_opcode(insn));
                                        }
                                        if insn == 0xd50320df {
                                            return Some(DGH::make_opcode(insn));
                                        }
                                        if insn == 0xd50330ff {
                                            return Some(SB::make_opcode(insn));
                                        }
                                        if insn == 0xd508779f {
                                            return Some(GCSPUSHX::make_opcode(insn));
                                        }
                                        if insn == 0xd50877df {
                                            return Some(GCSPOPX::make_opcode(insn));
                                        }
                                        if insn == 0xd50877bf {
                                            return Some(GCSPOPCX::make_opcode(insn));
                                        }
                                        if insn == 0xd500401f {
                                            return Some(CFINV::make_opcode(insn));
                                        }
                                        if insn & 0xfffff3ff == 0xd503323f {
                                            return Some(DSB_BARRIER_DSB_NXS::make_opcode(insn));
                                        }
                                        if insn & 0xfffff1ff == 0xd503417f {
                                            return Some(SMSTART_SME_SM_ZA::make_opcode(insn));
                                        }
                                        if insn & 0xfffff1ff == 0xd503407f {
                                            return Some(SMSTOP_SME_SM_ZA::make_opcode(insn));
                                        }
                                        if insn & 0xfffff0ff == 0xd503305f {
                                            return Some(CLREX_UIMM4::make_opcode(insn));
                                        }
                                        if insn & 0xfffff0ff == 0xd503309f {
                                            return Some(DSB_BARRIER::make_opcode(insn));
                                        }
                                        if insn & 0xfffff0ff == 0xd50330bf {
                                            return Some(DMB_BARRIER::make_opcode(insn));
                                        }
                                        if insn & 0xfffff0ff == 0xd50330df {
                                            return Some(ISB_BARRIER_ISB::make_opcode(insn));
                                        }
                                        if insn & 0xffffffe0 == 0xd50b7740 {
                                            return Some(GCSSS1_Rt::make_opcode(insn));
                                        }
                                        if insn & 0xffffffe0 == 0xd50b7700 {
                                            return Some(GCSPUSHM_Rt::make_opcode(insn));
                                        }
                                        if insn & 0xffffffe0 == 0xd5031000 {
                                            return Some(WFET_Rd::make_opcode(insn));
                                        }
                                        if insn & 0xffffffe0 == 0xd5031020 {
                                            return Some(WFIT_Rd::make_opcode(insn));
                                        }
                                        if insn & 0xfffff01f == 0xd503201f {
                                            return Some(HINT_UIMM7::make_opcode(insn));
                                        }
                                        if insn & 0xfff8f01f == 0xd500401f {
                                            return Some(MSR_PSTATEFIELD_UIMM4::make_opcode(insn));
                                        }
                                        if insn & 0xfff80000 == 0xd5080000 {
                                            return Some(
                                                SYS_UIMM3_OP1_CRn_CRm_UIMM3_OP2_Rt::make_opcode(
                                                    insn,
                                                ),
                                            );
                                        }
                                        if insn & 0xffe00000 == 0xd5000000 {
                                            return Some(MSR_SYSREG_Rt::make_opcode(insn));
                                        }
                                    } else {
                                        if insn & 0x000400 == 0 {
                                            if insn & 0xfffffc00 == 0xd71f0800 {
                                                return Some(BRAA_Rn_Rd_SP::make_opcode(insn));
                                            }
                                        } else {
                                            if insn & 0xfffffc00 == 0xd71f0c00 {
                                                return Some(BRAB_Rn_Rd_SP::make_opcode(insn));
                                            }
                                        }
                                    }
                                } else {
                                    if insn & 0x100000 == 0 {
                                        if insn & 0xfff80000 == 0xd5480000 {
                                            return Some (SYSP_UIMM3_OP1_CRn_CRm_UIMM3_OP2_Rt_PAIRREG_OR_XZR :: make_opcode (insn)) ;
                                        }
                                    } else {
                                        if insn & 0xfff00000 == 0xd5500000 {
                                            return Some(MSRR_SYSREG128_Rt_PAIRREG::make_opcode(
                                                insn,
                                            ));
                                        }
                                    }
                                }
                            } else {
                                if insn & 0x400000 == 0 {
                                    if insn & 0x2000000 == 0 {
                                        if insn == 0xd52b773f {
                                            return Some(GCSPOPM::make_opcode(insn));
                                        }
                                        if insn & 0xffffffe0 == 0xd5233060 {
                                            return Some(TSTART_Rd::make_opcode(insn));
                                        }
                                        if insn & 0xffffffe0 == 0xd5233160 {
                                            return Some(TTEST_Rd::make_opcode(insn));
                                        }
                                        if insn & 0xffffffe0 == 0xd52b7760 {
                                            return Some(GCSSS2_Rt::make_opcode(insn));
                                        }
                                        if insn & 0xffffffe0 == 0xd52b7720 {
                                            return Some(GCSPOPM_Rt::make_opcode(insn));
                                        }
                                        if insn & 0xfff80000 == 0xd5280000 {
                                            return Some(
                                                SYSL_Rt_UIMM3_OP1_CRn_CRm_UIMM3_OP2::make_opcode(
                                                    insn,
                                                ),
                                            );
                                        }
                                        if insn & 0xffe00000 == 0xd5200000 {
                                            return Some(MRS_Rt_SYSREG::make_opcode(insn));
                                        }
                                    } else {
                                        if insn & 0x000400 == 0 {
                                            if insn & 0xfffffc00 == 0xd73f0800 {
                                                return Some(BLRAA_Rn_Rd_SP::make_opcode(insn));
                                            }
                                        } else {
                                            if insn & 0xfffffc00 == 0xd73f0c00 {
                                                return Some(BLRAB_Rn_Rd_SP::make_opcode(insn));
                                            }
                                        }
                                    }
                                } else {
                                    if insn & 0xfff00000 == 0xd5700000 {
                                        return Some(MRRS_Rt_PAIRREG_SYSREG128::make_opcode(insn));
                                    }
                                }
                            }
                        }
                    }
                } else {
                    if insn & 0x1000000 == 0 {
                        if insn & 0x2000000 == 0 {
                            if insn & 0x7f000000 == 0x34000000 {
                                return Some(CBZ_Rt_ADDR_PCREL19::make_opcode(insn));
                            }
                        } else {
                            if insn & 0x7f000000 == 0x36000000 {
                                return Some(TBZ_Rt_BIT_NUM_ADDR_PCREL14::make_opcode(insn));
                            }
                        }
                    } else {
                        if insn & 0x2000000 == 0 {
                            if insn & 0x7f000000 == 0x35000000 {
                                return Some(CBNZ_Rt_ADDR_PCREL19::make_opcode(insn));
                            }
                        } else {
                            if insn & 0x7f000000 == 0x37000000 {
                                return Some(TBNZ_Rt_BIT_NUM_ADDR_PCREL14::make_opcode(insn));
                            }
                        }
                    }
                }
            }
        } else {
            if insn & 0x2000000 == 0 {
                if insn & 0x10000000 == 0 {
                    if insn & 0x400000 == 0 {
                        if insn & 0x800000 == 0 {
                            if insn & 0x1000000 == 0 {
                                if insn & 0x20000000 == 0 {
                                    if insn & 0xbfff0000 == 0xc000000 {
                                        return Some(ST4_LVt_SIMD_ADDR_SIMPLE::make_opcode(insn));
                                    }
                                    if insn & 0xbfff0000 == 0xc000000 {
                                        return Some(ST4_LVt_SIMD_ADDR_SIMPLE::make_opcode(insn));
                                    }
                                    if insn & 0xbfff0000 == 0xc000000 {
                                        return Some(ST4_LVt_SIMD_ADDR_SIMPLE::make_opcode(insn));
                                    }
                                    if insn & 0xbfff0000 == 0xc000000 {
                                        return Some(ST4_LVt_SIMD_ADDR_SIMPLE::make_opcode(insn));
                                    }
                                } else {
                                    if insn & 0x3fc00000 == 0x2c000000 {
                                        return Some(STNP_Ft_Ft2_ADDR_SIMM7::make_opcode(insn));
                                    }
                                }
                            } else {
                                if insn & 0x20000000 == 0 {
                                    if insn & 0x002000 == 0 {
                                        if insn & 0x010000 == 0 {
                                            if insn & 0x200000 == 0 {
                                                if insn & 0xbfff2000 == 0xd000000 {
                                                    return Some(
                                                        ST1_LEt_SIMD_ADDR_SIMPLE::make_opcode(insn),
                                                    );
                                                }
                                            } else {
                                                if insn & 0xbfff2000 == 0xd200000 {
                                                    return Some(
                                                        ST2_LEt_SIMD_ADDR_SIMPLE::make_opcode(insn),
                                                    );
                                                }
                                            }
                                        } else {
                                            if insn & 0xbffffc00 == 0xd018400 {
                                                return Some(
                                                    STL1_LEt_SIMD_ADDR_SIMPLE::make_opcode(insn),
                                                );
                                            }
                                        }
                                    } else {
                                        if insn & 0x200000 == 0 {
                                            if insn & 0xbfff2000 == 0xd002000 {
                                                return Some(
                                                    ST3_LEt_SIMD_ADDR_SIMPLE::make_opcode(insn),
                                                );
                                            }
                                        } else {
                                            if insn & 0xbfff2000 == 0xd202000 {
                                                return Some(
                                                    ST4_LEt_SIMD_ADDR_SIMPLE::make_opcode(insn),
                                                );
                                            }
                                        }
                                    }
                                } else {
                                    if insn & 0x3fc00000 == 0x2d000000 {
                                        return Some(STP_Ft_Ft2_ADDR_SIMM7::make_opcode(insn));
                                    }
                                }
                            }
                        } else {
                            if insn & 0x20000000 == 0 {
                                if insn & 0x200000 == 0 {
                                    if insn & 0x1000000 == 0 {
                                        if insn & 0xbfe00000 == 0xc800000 {
                                            return Some(ST4_LVt_SIMD_ADDR_POST::make_opcode(insn));
                                        }
                                        if insn & 0xbfe00000 == 0xc800000 {
                                            return Some(ST4_LVt_SIMD_ADDR_POST::make_opcode(insn));
                                        }
                                        if insn & 0xbfe00000 == 0xc800000 {
                                            return Some(ST4_LVt_SIMD_ADDR_POST::make_opcode(insn));
                                        }
                                        if insn & 0xbfe00000 == 0xc800000 {
                                            return Some(ST4_LVt_SIMD_ADDR_POST::make_opcode(insn));
                                        }
                                    } else {
                                        if insn & 0x002000 == 0 {
                                            if insn & 0xbfe02000 == 0xd800000 {
                                                return Some(ST1_LEt_SIMD_ADDR_POST::make_opcode(
                                                    insn,
                                                ));
                                            }
                                        } else {
                                            if insn & 0xbfe02000 == 0xd802000 {
                                                return Some(ST3_LEt_SIMD_ADDR_POST::make_opcode(
                                                    insn,
                                                ));
                                            }
                                        }
                                    }
                                } else {
                                    if insn & 0x002000 == 0 {
                                        if insn & 0xbfe02000 == 0xda00000 {
                                            return Some(ST2_LEt_SIMD_ADDR_POST::make_opcode(insn));
                                        }
                                    } else {
                                        if insn & 0xbfe02000 == 0xda02000 {
                                            return Some(ST4_LEt_SIMD_ADDR_POST::make_opcode(insn));
                                        }
                                    }
                                }
                            } else {
                                if insn & 0x3ec00000 == 0x2c800000 {
                                    return Some(STP_Ft_S_S_Ft2_S_S_ADDR_SIMM7_S_S::make_opcode(
                                        insn,
                                    ));
                                }
                            }
                        }
                    } else {
                        if insn & 0x800000 == 0 {
                            if insn & 0x1000000 == 0 {
                                if insn & 0x20000000 == 0 {
                                    if insn & 0xbfff0000 == 0xc400000 {
                                        return Some(LD4_LVt_SIMD_ADDR_SIMPLE::make_opcode(insn));
                                    }
                                    if insn & 0xbfff0000 == 0xc400000 {
                                        return Some(LD4_LVt_SIMD_ADDR_SIMPLE::make_opcode(insn));
                                    }
                                    if insn & 0xbfff0000 == 0xc400000 {
                                        return Some(LD4_LVt_SIMD_ADDR_SIMPLE::make_opcode(insn));
                                    }
                                    if insn & 0xbfff0000 == 0xc400000 {
                                        return Some(LD4_LVt_SIMD_ADDR_SIMPLE::make_opcode(insn));
                                    }
                                } else {
                                    if insn & 0x3fc00000 == 0x2c400000 {
                                        return Some(LDNP_Ft_Ft2_ADDR_SIMM7::make_opcode(insn));
                                    }
                                }
                            } else {
                                if insn & 0x20000000 == 0 {
                                    if insn & 0x002000 == 0 {
                                        if insn & 0x010000 == 0 {
                                            if insn & 0x200000 == 0 {
                                                if insn & 0xbffff000 == 0xd40c000 {
                                                    return Some(
                                                        LD1R_LVt_AL_SIMD_ADDR_SIMPLE::make_opcode(
                                                            insn,
                                                        ),
                                                    );
                                                }
                                                if insn & 0xbfff2000 == 0xd400000 {
                                                    return Some(
                                                        LD1_LEt_SIMD_ADDR_SIMPLE::make_opcode(insn),
                                                    );
                                                }
                                            } else {
                                                if insn & 0xbffff000 == 0xd60c000 {
                                                    return Some(
                                                        LD2R_LVt_AL_SIMD_ADDR_SIMPLE::make_opcode(
                                                            insn,
                                                        ),
                                                    );
                                                }
                                                if insn & 0xbfff2000 == 0xd600000 {
                                                    return Some(
                                                        LD2_LEt_SIMD_ADDR_SIMPLE::make_opcode(insn),
                                                    );
                                                }
                                            }
                                        } else {
                                            if insn & 0xbffffc00 == 0xd418400 {
                                                return Some(
                                                    LDAP1_LEt_SIMD_ADDR_SIMPLE::make_opcode(insn),
                                                );
                                            }
                                        }
                                    } else {
                                        if insn & 0x200000 == 0 {
                                            if insn & 0xbffff000 == 0xd40e000 {
                                                return Some(
                                                    LD3R_LVt_AL_SIMD_ADDR_SIMPLE::make_opcode(insn),
                                                );
                                            }
                                            if insn & 0xbfff2000 == 0xd402000 {
                                                return Some(
                                                    LD3_LEt_SIMD_ADDR_SIMPLE::make_opcode(insn),
                                                );
                                            }
                                        } else {
                                            if insn & 0xbffff000 == 0xd60e000 {
                                                return Some(
                                                    LD4R_LVt_AL_SIMD_ADDR_SIMPLE::make_opcode(insn),
                                                );
                                            }
                                            if insn & 0xbfff2000 == 0xd602000 {
                                                return Some(
                                                    LD4_LEt_SIMD_ADDR_SIMPLE::make_opcode(insn),
                                                );
                                            }
                                        }
                                    }
                                } else {
                                    if insn & 0x3fc00000 == 0x2d400000 {
                                        return Some(LDP_Ft_Ft2_ADDR_SIMM7::make_opcode(insn));
                                    }
                                }
                            }
                        } else {
                            if insn & 0x20000000 == 0 {
                                if insn & 0x200000 == 0 {
                                    if insn & 0x1000000 == 0 {
                                        if insn & 0xbfe00000 == 0xcc00000 {
                                            return Some(LD4_LVt_SIMD_ADDR_POST::make_opcode(insn));
                                        }
                                        if insn & 0xbfe00000 == 0xcc00000 {
                                            return Some(LD4_LVt_SIMD_ADDR_POST::make_opcode(insn));
                                        }
                                        if insn & 0xbfe00000 == 0xcc00000 {
                                            return Some(LD4_LVt_SIMD_ADDR_POST::make_opcode(insn));
                                        }
                                        if insn & 0xbfe00000 == 0xcc00000 {
                                            return Some(LD4_LVt_SIMD_ADDR_POST::make_opcode(insn));
                                        }
                                    } else {
                                        if insn & 0x002000 == 0 {
                                            if insn & 0xbfe0f000 == 0xdc0c000 {
                                                return Some(
                                                    LD1R_LVt_AL_SIMD_ADDR_POST::make_opcode(insn),
                                                );
                                            }
                                            if insn & 0xbfe02000 == 0xdc00000 {
                                                return Some(LD1_LEt_SIMD_ADDR_POST::make_opcode(
                                                    insn,
                                                ));
                                            }
                                        } else {
                                            if insn & 0xbfe0f000 == 0xdc0e000 {
                                                return Some(
                                                    LD3R_LVt_AL_SIMD_ADDR_POST::make_opcode(insn),
                                                );
                                            }
                                            if insn & 0xbfe02000 == 0xdc02000 {
                                                return Some(LD3_LEt_SIMD_ADDR_POST::make_opcode(
                                                    insn,
                                                ));
                                            }
                                        }
                                    }
                                } else {
                                    if insn & 0x002000 == 0 {
                                        if insn & 0xbfe0f000 == 0xde0c000 {
                                            return Some(LD2R_LVt_AL_SIMD_ADDR_POST::make_opcode(
                                                insn,
                                            ));
                                        }
                                        if insn & 0xbfe02000 == 0xde00000 {
                                            return Some(LD2_LEt_SIMD_ADDR_POST::make_opcode(insn));
                                        }
                                    } else {
                                        if insn & 0xbfe0f000 == 0xde0e000 {
                                            return Some(LD4R_LVt_AL_SIMD_ADDR_POST::make_opcode(
                                                insn,
                                            ));
                                        }
                                        if insn & 0xbfe02000 == 0xde02000 {
                                            return Some(LD4_LEt_SIMD_ADDR_POST::make_opcode(insn));
                                        }
                                    }
                                }
                            } else {
                                if insn & 0x3ec00000 == 0x2cc00000 {
                                    return Some(LDP_Ft_S_S_Ft2_S_S_ADDR_SIMM7_S_S::make_opcode(
                                        insn,
                                    ));
                                }
                            }
                        }
                    }
                } else {
                    if insn & 0x1000000 == 0 {
                        if insn & 0x20000000 == 0 {
                            if insn & 0x3f000000 == 0x1c000000 {
                                return Some(LDR_Ft_ADDR_PCREL19::make_opcode(insn));
                            }
                        } else {
                            if insn & 0x000400 == 0 {
                                if insn & 0x000800 == 0 {
                                    if insn & 0x400000 == 0 {
                                        if insn & 0x3f600c00 == 0x3c000000 {
                                            return Some(STUR_Ft_ADDR_SIMM9::make_opcode(insn));
                                        }
                                    } else {
                                        if insn & 0x3f600c00 == 0x3c400000 {
                                            return Some(LDUR_Ft_ADDR_SIMM9::make_opcode(insn));
                                        }
                                    }
                                } else {
                                    if insn & 0x400000 == 0 {
                                        if insn & 0x3f600c00 == 0x3c200800 {
                                            return Some(STR_Ft_ADDR_REGOFF::make_opcode(insn));
                                        }
                                    } else {
                                        if insn & 0x3f600c00 == 0x3c600800 {
                                            return Some(LDR_Ft_ADDR_REGOFF::make_opcode(insn));
                                        }
                                    }
                                }
                            } else {
                                if insn & 0x400000 == 0 {
                                    if insn & 0x3f600400 == 0x3c000400 {
                                        return Some(STR_Ft_ADDR_SIMM9::make_opcode(insn));
                                    }
                                } else {
                                    if insn & 0x3f600400 == 0x3c400400 {
                                        return Some(LDR_Ft_ADDR_SIMM9::make_opcode(insn));
                                    }
                                }
                            }
                        }
                    } else {
                        if insn & 0x400000 == 0 {
                            if insn & 0x20000000 == 0 {
                                if insn & 0x000400 == 0 {
                                    if insn & 0x3f600c00 == 0x1d000800 {
                                        return Some(STLUR_Ft_RCPC3_ADDR_OFFSET::make_opcode(insn));
                                    }
                                } else {
                                    if insn & 0x001000 == 0 {
                                        if insn & 0x002000 == 0 {
                                            if insn & 0x004000 == 0 {
                                                if insn & 0x008000 == 0 {
                                                    if insn & 0x800000 == 0 {
                                                        if insn & 0xffe0fc00 == 0x1d000400 {
                                                            return Some (CPYP_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xffe0fc00 == 0x1d800400 {
                                                            return Some (CPYE_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x800000 == 0 {
                                                        if insn & 0xffe0fc00 == 0x1d008400 {
                                                            return Some (CPYPRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xffe0fc00 == 0x1d808400 {
                                                            return Some (CPYERN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0x008000 == 0 {
                                                    if insn & 0x800000 == 0 {
                                                        if insn & 0xffe0fc00 == 0x1d004400 {
                                                            return Some (CPYPWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xffe0fc00 == 0x1d804400 {
                                                            return Some (CPYEWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x800000 == 0 {
                                                        if insn & 0xffe0fc00 == 0x1d00c400 {
                                                            return Some (CPYPN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xffe0fc00 == 0x1d80c400 {
                                                            return Some (CPYEN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                }
                                            }
                                        } else {
                                            if insn & 0x004000 == 0 {
                                                if insn & 0x008000 == 0 {
                                                    if insn & 0x800000 == 0 {
                                                        if insn & 0xffe0fc00 == 0x1d002400 {
                                                            return Some (CPYPRT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xffe0fc00 == 0x1d802400 {
                                                            return Some (CPYERT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x800000 == 0 {
                                                        if insn & 0xffe0fc00 == 0x1d00a400 {
                                                            return Some (CPYPRTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xffe0fc00 == 0x1d80a400 {
                                                            return Some (CPYERTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0x008000 == 0 {
                                                    if insn & 0x800000 == 0 {
                                                        if insn & 0xffe0fc00 == 0x1d006400 {
                                                            return Some (CPYPRTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xffe0fc00 == 0x1d806400 {
                                                            return Some (CPYERTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x800000 == 0 {
                                                        if insn & 0xffe0fc00 == 0x1d00e400 {
                                                            return Some (CPYPRTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xffe0fc00 == 0x1d80e400 {
                                                            return Some (CPYERTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                }
                                            }
                                        }
                                    } else {
                                        if insn & 0x002000 == 0 {
                                            if insn & 0x004000 == 0 {
                                                if insn & 0x008000 == 0 {
                                                    if insn & 0x800000 == 0 {
                                                        if insn & 0xffe0fc00 == 0x1d001400 {
                                                            return Some (CPYPWT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xffe0fc00 == 0x1d801400 {
                                                            return Some (CPYEWT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x800000 == 0 {
                                                        if insn & 0xffe0fc00 == 0x1d009400 {
                                                            return Some (CPYPWTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xffe0fc00 == 0x1d809400 {
                                                            return Some (CPYEWTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0x008000 == 0 {
                                                    if insn & 0x800000 == 0 {
                                                        if insn & 0xffe0fc00 == 0x1d005400 {
                                                            return Some (CPYPWTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xffe0fc00 == 0x1d805400 {
                                                            return Some (CPYEWTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x800000 == 0 {
                                                        if insn & 0xffe0fc00 == 0x1d00d400 {
                                                            return Some (CPYPWTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xffe0fc00 == 0x1d80d400 {
                                                            return Some (CPYEWTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                }
                                            }
                                        } else {
                                            if insn & 0x004000 == 0 {
                                                if insn & 0x008000 == 0 {
                                                    if insn & 0x800000 == 0 {
                                                        if insn & 0xffe0fc00 == 0x1d003400 {
                                                            return Some (CPYPT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xffe0fc00 == 0x1d803400 {
                                                            return Some (CPYET_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x800000 == 0 {
                                                        if insn & 0xffe0fc00 == 0x1d00b400 {
                                                            return Some (CPYPTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xffe0fc00 == 0x1d80b400 {
                                                            return Some (CPYETRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0x008000 == 0 {
                                                    if insn & 0x800000 == 0 {
                                                        if insn & 0xffe0fc00 == 0x1d007400 {
                                                            return Some (CPYPTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xffe0fc00 == 0x1d807400 {
                                                            return Some (CPYETWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x800000 == 0 {
                                                        if insn & 0xffe0fc00 == 0x1d00f400 {
                                                            return Some (CPYPTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xffe0fc00 == 0x1d80f400 {
                                                            return Some (CPYETN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                }
                                            }
                                        }
                                    }
                                }
                            } else {
                                if insn & 0x3f400000 == 0x3d000000 {
                                    return Some(STR_Ft_ADDR_UIMM12::make_opcode(insn));
                                }
                            }
                        } else {
                            if insn & 0x20000000 == 0 {
                                if insn & 0x000400 == 0 {
                                    if insn & 0x3f600c00 == 0x1d400800 {
                                        return Some(LDAPUR_Ft_RCPC3_ADDR_OFFSET::make_opcode(
                                            insn,
                                        ));
                                    }
                                } else {
                                    if insn & 0x001000 == 0 {
                                        if insn & 0x002000 == 0 {
                                            if insn & 0x004000 == 0 {
                                                if insn & 0x008000 == 0 {
                                                    if insn & 0x800000 == 0 {
                                                        if insn & 0xffe0fc00 == 0x1d400400 {
                                                            return Some (CPYM_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xffe0fc00 == 0x1dc00400 {
                                                            return Some (SETGP_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x800000 == 0 {
                                                        if insn & 0xffe0fc00 == 0x1d408400 {
                                                            return Some (CPYMRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xffe0fc00 == 0x1dc08400 {
                                                            return Some (SETGE_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0x008000 == 0 {
                                                    if insn & 0x800000 == 0 {
                                                        if insn & 0xffe0fc00 == 0x1d404400 {
                                                            return Some (CPYMWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xffe0fc00 == 0x1dc04400 {
                                                            return Some (SETGM_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0xffe0fc00 == 0x1d40c400 {
                                                        return Some (CPYMN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn :: make_opcode (insn)) ;
                                                    }
                                                }
                                            }
                                        } else {
                                            if insn & 0x004000 == 0 {
                                                if insn & 0x008000 == 0 {
                                                    if insn & 0x800000 == 0 {
                                                        if insn & 0xffe0fc00 == 0x1d402400 {
                                                            return Some (CPYMRT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xffe0fc00 == 0x1dc02400 {
                                                            return Some (SETGPN_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x800000 == 0 {
                                                        if insn & 0xffe0fc00 == 0x1d40a400 {
                                                            return Some (CPYMRTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xffe0fc00 == 0x1dc0a400 {
                                                            return Some (SETGEN_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0x008000 == 0 {
                                                    if insn & 0x800000 == 0 {
                                                        if insn & 0xffe0fc00 == 0x1d406400 {
                                                            return Some (CPYMRTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xffe0fc00 == 0x1dc06400 {
                                                            return Some (SETGMN_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0xffe0fc00 == 0x1d40e400 {
                                                        return Some (CPYMRTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn :: make_opcode (insn)) ;
                                                    }
                                                }
                                            }
                                        }
                                    } else {
                                        if insn & 0x002000 == 0 {
                                            if insn & 0x004000 == 0 {
                                                if insn & 0x008000 == 0 {
                                                    if insn & 0x800000 == 0 {
                                                        if insn & 0xffe0fc00 == 0x1d401400 {
                                                            return Some (CPYMWT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xffe0fc00 == 0x1dc01400 {
                                                            return Some (SETGPT_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x800000 == 0 {
                                                        if insn & 0xffe0fc00 == 0x1d409400 {
                                                            return Some (CPYMWTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xffe0fc00 == 0x1dc09400 {
                                                            return Some (SETGET_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0x008000 == 0 {
                                                    if insn & 0x800000 == 0 {
                                                        if insn & 0xffe0fc00 == 0x1d405400 {
                                                            return Some (CPYMWTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xffe0fc00 == 0x1dc05400 {
                                                            return Some (SETGMT_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0xffe0fc00 == 0x1d40d400 {
                                                        return Some (CPYMWTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn :: make_opcode (insn)) ;
                                                    }
                                                }
                                            }
                                        } else {
                                            if insn & 0x004000 == 0 {
                                                if insn & 0x008000 == 0 {
                                                    if insn & 0x800000 == 0 {
                                                        if insn & 0xffe0fc00 == 0x1d403400 {
                                                            return Some (CPYMT_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xffe0fc00 == 0x1dc03400 {
                                                            return Some (SETGPTN_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x800000 == 0 {
                                                        if insn & 0xffe0fc00 == 0x1d40b400 {
                                                            return Some (CPYMTRN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xffe0fc00 == 0x1dc0b400 {
                                                            return Some (SETGETN_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0x008000 == 0 {
                                                    if insn & 0x800000 == 0 {
                                                        if insn & 0xffe0fc00 == 0x1d407400 {
                                                            return Some (CPYMTWN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xffe0fc00 == 0x1dc07400 {
                                                            return Some (SETGMTN_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0xffe0fc00 == 0x1d40f400 {
                                                        return Some (CPYMTN_MOPS_ADDR_Rd_MOPS_ADDR_Rs_MOPS_WB_Rn :: make_opcode (insn)) ;
                                                    }
                                                }
                                            }
                                        }
                                    }
                                }
                            } else {
                                if insn & 0x3f400000 == 0x3d400000 {
                                    return Some(LDR_Ft_ADDR_UIMM12::make_opcode(insn));
                                }
                            }
                        }
                    }
                }
            } else {
                if insn & 0x1000000 == 0 {
                    if insn & 0x200000 == 0 {
                        if insn & 0x10000000 == 0 {
                            if insn & 0x20000000 == 0 {
                                if insn & 0x80000000 == 0 {
                                    if insn & 0x000400 == 0 {
                                        if insn & 0x000800 == 0 {
                                            if insn & 0x001000 == 0 {
                                                if insn & 0xbfe09c00 == 0xe000000 {
                                                    return Some(TBL_Vd_LVn_Vm::make_opcode(insn));
                                                }
                                            } else {
                                                if insn & 0xbfe09c00 == 0xe001000 {
                                                    return Some(TBX_Vd_LVn_Vm::make_opcode(insn));
                                                }
                                            }
                                        } else {
                                            if insn & 0x001000 == 0 {
                                                if insn & 0x004000 == 0 {
                                                    if insn & 0xbf20fc00 == 0xe002800 {
                                                        return Some(TRN1_Vd_Vn_Vm::make_opcode(
                                                            insn,
                                                        ));
                                                    }
                                                } else {
                                                    if insn & 0xbf20fc00 == 0xe006800 {
                                                        return Some(TRN2_Vd_Vn_Vm::make_opcode(
                                                            insn,
                                                        ));
                                                    }
                                                }
                                            } else {
                                                if insn & 0x002000 == 0 {
                                                    if insn & 0x004000 == 0 {
                                                        if insn & 0xbf20fc00 == 0xe001800 {
                                                            return Some(
                                                                UZP1_Vd_Vn_Vm::make_opcode(insn),
                                                            );
                                                        }
                                                    } else {
                                                        if insn & 0xbf20fc00 == 0xe005800 {
                                                            return Some(
                                                                UZP2_Vd_Vn_Vm::make_opcode(insn),
                                                            );
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x004000 == 0 {
                                                        if insn & 0xbf20fc00 == 0xe003800 {
                                                            return Some(
                                                                ZIP1_Vd_Vn_Vm::make_opcode(insn),
                                                            );
                                                        }
                                                    } else {
                                                        if insn & 0xbf20fc00 == 0xe007800 {
                                                            return Some(
                                                                ZIP2_Vd_Vn_Vm::make_opcode(insn),
                                                            );
                                                        }
                                                    }
                                                }
                                            }
                                        }
                                    } else {
                                        if insn & 0x000800 == 0 {
                                            if insn & 0x001000 == 0 {
                                                if insn & 0x002000 == 0 {
                                                    if insn & 0x400000 == 0 {
                                                        if insn & 0xbfe0fc00 == 0xe000400 {
                                                            return Some(DUP_Vd_En::make_opcode(
                                                                insn,
                                                            ));
                                                        }
                                                    } else {
                                                        if insn & 0x800000 == 0 {
                                                            if insn & 0xbfe0fc00 == 0xe400400 {
                                                                return Some(
                                                                    FMAXNM_Vd_Vn_Vm::make_opcode(
                                                                        insn,
                                                                    ),
                                                                );
                                                            }
                                                        } else {
                                                            if insn & 0xbfe0fc00 == 0xec00400 {
                                                                return Some(
                                                                    FMINNM_Vd_Vn_Vm::make_opcode(
                                                                        insn,
                                                                    ),
                                                                );
                                                            }
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x008000 == 0 {
                                                        if insn & 0xbfe0fc00 == 0xe402400 {
                                                            return Some(
                                                                FCMEQ_Vd_Vn_Vm::make_opcode(insn),
                                                            );
                                                        }
                                                    } else {
                                                        if insn & 0xffe0fc00 == 0x4e80a400 {
                                                            return Some(
                                                                SMMLA_Vd_Vn_Vm::make_opcode(insn),
                                                            );
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0x002000 == 0 {
                                                    if insn & 0x008000 == 0 {
                                                        if insn & 0x800000 == 0 {
                                                            if insn & 0xbfe0fc00 == 0xe401400 {
                                                                return Some(
                                                                    FADD_Vd_Vn_Vm::make_opcode(
                                                                        insn,
                                                                    ),
                                                                );
                                                            }
                                                        } else {
                                                            if insn & 0xbfe0fc00 == 0xec01400 {
                                                                return Some(
                                                                    FSUB_Vd_Vn_Vm::make_opcode(
                                                                        insn,
                                                                    ),
                                                                );
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0xbf20fc00 == 0xe009400 {
                                                            return Some(
                                                                SDOT_Vd_Vn_Vm::make_opcode(insn),
                                                            );
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x800000 == 0 {
                                                        if insn & 0xbfe0fc00 == 0xe403400 {
                                                            return Some(
                                                                FMAX_Vd_Vn_Vm::make_opcode(insn),
                                                            );
                                                        }
                                                    } else {
                                                        if insn & 0xbfe0fc00 == 0xec03400 {
                                                            return Some(
                                                                FMIN_Vd_Vn_Vm::make_opcode(insn),
                                                            );
                                                        }
                                                    }
                                                }
                                            }
                                        } else {
                                            if insn & 0x001000 == 0 {
                                                if insn & 0x002000 == 0 {
                                                    if insn & 0x400000 == 0 {
                                                        if insn & 0xbfe0fc00 == 0xe000c00 {
                                                            return Some(DUP_Vd_Rn::make_opcode(
                                                                insn,
                                                            ));
                                                        }
                                                    } else {
                                                        if insn & 0x800000 == 0 {
                                                            if insn & 0xbfe0fc00 == 0xe400c00 {
                                                                return Some(
                                                                    FMLA_Vd_Vn_Vm::make_opcode(
                                                                        insn,
                                                                    ),
                                                                );
                                                            }
                                                        } else {
                                                            if insn & 0xbfe0fc00 == 0xec00c00 {
                                                                return Some(
                                                                    FMLS_Vd_Vn_Vm::make_opcode(
                                                                        insn,
                                                                    ),
                                                                );
                                                            }
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x008000 == 0 {
                                                        if insn & 0xbfe0fc00 == 0xe002c00 {
                                                            return Some(SMOV_Rd_En::make_opcode(
                                                                insn,
                                                            ));
                                                        }
                                                    } else {
                                                        if insn & 0xffe0fc00 == 0x4e80ac00 {
                                                            return Some(
                                                                USMMLA_Vd_Vn_Vm::make_opcode(insn),
                                                            );
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0x002000 == 0 {
                                                    if insn & 0x008000 == 0 {
                                                        if insn & 0x400000 == 0 {
                                                            if insn & 0xffe0fc00 == 0x4e001c00 {
                                                                return Some(
                                                                    INS_Ed_Rn::make_opcode(insn),
                                                                );
                                                            }
                                                        } else {
                                                            if insn & 0xbfe0fc00 == 0xe401c00 {
                                                                return Some(
                                                                    FMULX_Vd_Vn_Vm::make_opcode(
                                                                        insn,
                                                                    ),
                                                                );
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0xbfe0fc00 == 0xe809c00 {
                                                            return Some(
                                                                USDOT_Vd_Vn_Vm::make_opcode(insn),
                                                            );
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x400000 == 0 {
                                                        if insn & 0xbfe0fc00 == 0xe003c00 {
                                                            return Some(UMOV_Rd_En::make_opcode(
                                                                insn,
                                                            ));
                                                        }
                                                    } else {
                                                        if insn & 0x800000 == 0 {
                                                            if insn & 0xbfe0fc00 == 0xe403c00 {
                                                                return Some(
                                                                    FRECPS_Vd_Vn_Vm::make_opcode(
                                                                        insn,
                                                                    ),
                                                                );
                                                            }
                                                        } else {
                                                            if insn & 0xbfe0fc00 == 0xec03c00 {
                                                                return Some(
                                                                    FRSQRTS_Vd_Vn_Vm::make_opcode(
                                                                        insn,
                                                                    ),
                                                                );
                                                            }
                                                        }
                                                    }
                                                }
                                            }
                                        }
                                    }
                                } else {
                                    if insn & 0x400000 == 0 {
                                        if insn & 0x800000 == 0 {
                                            if insn & 0xffe08000 == 0xce000000 {
                                                return Some(EOR3_Vd_Vn_Vm_Va::make_opcode(insn));
                                            }
                                        } else {
                                            if insn & 0xffe00000 == 0xce800000 {
                                                return Some(XAR_Vd_Vn_Vm_IMM::make_opcode(insn));
                                            }
                                        }
                                    } else {
                                        if insn & 0x008000 == 0 {
                                            if insn & 0xffe08000 == 0xce400000 {
                                                return Some(SM3SS1_Vd_Vn_Vm_Va::make_opcode(insn));
                                            }
                                        } else {
                                            if insn & 0x000400 == 0 {
                                                if insn & 0x000800 == 0 {
                                                    if insn & 0x800000 == 0 {
                                                        if insn & 0xffe0cc00 == 0xce408000 {
                                                            return Some(
                                                                SM3TT1A_Vd_Vn_Em::make_opcode(insn),
                                                            );
                                                        }
                                                    } else {
                                                        if insn & 0xfffffc00 == 0xcec08000 {
                                                            return Some(
                                                                SHA512SU0_Vd_Vn::make_opcode(insn),
                                                            );
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0xffe0cc00 == 0xce408800 {
                                                        return Some(
                                                            SM3TT2A_Vd_Vn_Em::make_opcode(insn),
                                                        );
                                                    }
                                                }
                                            } else {
                                                if insn & 0x000800 == 0 {
                                                    if insn & 0x800000 == 0 {
                                                        if insn & 0xffe0cc00 == 0xce408400 {
                                                            return Some(
                                                                SM3TT1B_Vd_Vn_Em::make_opcode(insn),
                                                            );
                                                        }
                                                    } else {
                                                        if insn & 0xfffffc00 == 0xcec08400 {
                                                            return Some(SM4E_Vd_Vn::make_opcode(
                                                                insn,
                                                            ));
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0xffe0cc00 == 0xce408c00 {
                                                        return Some(
                                                            SM3TT2B_Vd_Vn_Em::make_opcode(insn),
                                                        );
                                                    }
                                                }
                                            }
                                        }
                                    }
                                }
                            } else {
                                if insn & 0x000400 == 0 {
                                    if insn & 0xbfe08400 == 0x2e000000 {
                                        return Some(EXT_Vd_Vn_Vm_IDX::make_opcode(insn));
                                    }
                                } else {
                                    if insn & 0x008000 == 0 {
                                        if insn & 0x400000 == 0 {
                                            if insn & 0xffe08400 == 0x6e000400 {
                                                return Some(INS_Ed_En::make_opcode(insn));
                                            }
                                        } else {
                                            if insn & 0x000800 == 0 {
                                                if insn & 0x001000 == 0 {
                                                    if insn & 0x002000 == 0 {
                                                        if insn & 0x800000 == 0 {
                                                            if insn & 0xbfe0fc00 == 0x2e400400 {
                                                                return Some(
                                                                    FMAXNMP_Vd_Vn_Vm::make_opcode(
                                                                        insn,
                                                                    ),
                                                                );
                                                            }
                                                        } else {
                                                            if insn & 0xbfe0fc00 == 0x2ec00400 {
                                                                return Some(
                                                                    FMINNMP_Vd_Vn_Vm::make_opcode(
                                                                        insn,
                                                                    ),
                                                                );
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x800000 == 0 {
                                                            if insn & 0xbfe0fc00 == 0x2e402400 {
                                                                return Some(
                                                                    FCMGE_Vd_Vn_Vm::make_opcode(
                                                                        insn,
                                                                    ),
                                                                );
                                                            }
                                                        } else {
                                                            if insn & 0xbfe0fc00 == 0x2ec02400 {
                                                                return Some(
                                                                    FCMGT_Vd_Vn_Vm::make_opcode(
                                                                        insn,
                                                                    ),
                                                                );
                                                            }
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x002000 == 0 {
                                                        if insn & 0x800000 == 0 {
                                                            if insn & 0xbfe0fc00 == 0x2e401400 {
                                                                return Some(
                                                                    FADDP_Vd_Vn_Vm::make_opcode(
                                                                        insn,
                                                                    ),
                                                                );
                                                            }
                                                        } else {
                                                            if insn & 0xbfe0fc00 == 0x2ec01400 {
                                                                return Some(
                                                                    FABD_Vd_Vn_Vm::make_opcode(
                                                                        insn,
                                                                    ),
                                                                );
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x800000 == 0 {
                                                            if insn & 0xbfe0fc00 == 0x2e403400 {
                                                                return Some(
                                                                    FMAXP_Vd_Vn_Vm::make_opcode(
                                                                        insn,
                                                                    ),
                                                                );
                                                            }
                                                        } else {
                                                            if insn & 0xbfe0fc00 == 0x2ec03400 {
                                                                return Some(
                                                                    FMINP_Vd_Vn_Vm::make_opcode(
                                                                        insn,
                                                                    ),
                                                                );
                                                            }
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0x001000 == 0 {
                                                    if insn & 0x800000 == 0 {
                                                        if insn & 0xbfe0fc00 == 0x2e402c00 {
                                                            return Some(
                                                                FACGE_Vd_Vn_Vm::make_opcode(insn),
                                                            );
                                                        }
                                                    } else {
                                                        if insn & 0xbfe0fc00 == 0x2ec02c00 {
                                                            return Some(
                                                                FACGT_Vd_Vn_Vm::make_opcode(insn),
                                                            );
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x002000 == 0 {
                                                        if insn & 0xbfe0fc00 == 0x2e401c00 {
                                                            return Some(
                                                                FMUL_Vd_Vn_Vm::make_opcode(insn),
                                                            );
                                                        }
                                                    } else {
                                                        if insn & 0xbfe0fc00 == 0x2e403c00 {
                                                            return Some(
                                                                FDIV_Vd_Vn_Vm::make_opcode(insn),
                                                            );
                                                        }
                                                    }
                                                }
                                            }
                                        }
                                    } else {
                                        if insn & 0x002000 == 0 {
                                            if insn & 0x004000 == 0 {
                                                if insn & 0x000800 == 0 {
                                                    if insn & 0x001000 == 0 {
                                                        if insn & 0xbf20fc00 == 0x2e008400 {
                                                            return Some(
                                                                SQRDMLAH_Vd_Vn_Vm::make_opcode(
                                                                    insn,
                                                                ),
                                                            );
                                                        }
                                                    } else {
                                                        if insn & 0xbf20fc00 == 0x2e009400 {
                                                            return Some(
                                                                UDOT_Vd_Vn_Vm::make_opcode(insn),
                                                            );
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0xbf20fc00 == 0x2e008c00 {
                                                        return Some(
                                                            SQRDMLSH_Vd_Vn_Vm::make_opcode(insn),
                                                        );
                                                    }
                                                }
                                            } else {
                                                if insn & 0xbf20e400 == 0x2e00c400 {
                                                    return Some(
                                                        FCMLA_Vd_Vn_Vm_IMM_ROT1::make_opcode(insn),
                                                    );
                                                }
                                            }
                                        } else {
                                            if insn & 0x000800 == 0 {
                                                if insn & 0x004000 == 0 {
                                                    if insn & 0xffe0fc00 == 0x6e80a400 {
                                                        return Some(UMMLA_Vd_Vn_Vm::make_opcode(
                                                            insn,
                                                        ));
                                                    }
                                                } else {
                                                    if insn & 0xbf20ec00 == 0x2e00e400 {
                                                        return Some(
                                                            FCADD_Vd_Vn_Vm_IMM_ROT3::make_opcode(
                                                                insn,
                                                            ),
                                                        );
                                                    }
                                                }
                                            } else {
                                                if insn & 0x001000 == 0 {
                                                    if insn & 0xffe0fc00 == 0x6e40ec00 {
                                                        return Some(BFMMLA_Vd_Vn_Vm::make_opcode(
                                                            insn,
                                                        ));
                                                    }
                                                } else {
                                                    if insn & 0x800000 == 0 {
                                                        if insn & 0xbfe0fc00 == 0x2e40fc00 {
                                                            return Some(
                                                                BFDOT_Vd_Vn_Vm::make_opcode(insn),
                                                            );
                                                        }
                                                    } else {
                                                        if insn & 0x40000000 == 0 {
                                                            if insn & 0xffe0fc00 == 0x2ec0fc00 {
                                                                return Some(
                                                                    BFMLALB_Vd_Vn_Vm::make_opcode(
                                                                        insn,
                                                                    ),
                                                                );
                                                            }
                                                        } else {
                                                            if insn & 0xffe0fc00 == 0x6ec0fc00 {
                                                                return Some(
                                                                    BFMLALT_Vd_Vn_Vm::make_opcode(
                                                                        insn,
                                                                    ),
                                                                );
                                                            }
                                                        }
                                                    }
                                                }
                                            }
                                        }
                                    }
                                }
                            }
                        } else {
                            if insn & 0x20000000 == 0 {
                                if insn & 0x40000000 == 0 {
                                    if insn & 0x010000 == 0 {
                                        if insn & 0x020000 == 0 {
                                            if insn & 0x7fff0000 == 0x1ed80000 {
                                                return Some(FCVTZS_Rd_Fn_FBITS::make_opcode(insn));
                                            }
                                            if insn & 0x7f3f0000 == 0x1e180000 {
                                                return Some(
                                                    FCVTZS_Rd_W_Fn_S_D_FBITS_imm_1_32::make_opcode(
                                                        insn,
                                                    ),
                                                );
                                            }
                                        } else {
                                            if insn & 0x7fff0000 == 0x1ec20000 {
                                                return Some(SCVTF_Fd_Rn_FBITS::make_opcode(insn));
                                            }
                                            if insn & 0x7f3f0000 == 0x1e020000 {
                                                return Some(
                                                    SCVTF_Fd_S_D_Rn_W_FBITS_imm_1_32::make_opcode(
                                                        insn,
                                                    ),
                                                );
                                            }
                                        }
                                    } else {
                                        if insn & 0x020000 == 0 {
                                            if insn & 0x7fff0000 == 0x1ed90000 {
                                                return Some(FCVTZU_Rd_Fn_FBITS::make_opcode(insn));
                                            }
                                            if insn & 0x7f3f0000 == 0x1e190000 {
                                                return Some(
                                                    FCVTZU_Rd_W_Fn_S_D_FBITS_imm_1_32::make_opcode(
                                                        insn,
                                                    ),
                                                );
                                            }
                                        } else {
                                            if insn & 0x7fff0000 == 0x1ec30000 {
                                                return Some(UCVTF_Fd_Rn_FBITS::make_opcode(insn));
                                            }
                                            if insn & 0x7f3f0000 == 0x1e030000 {
                                                return Some(
                                                    UCVTF_Fd_S_D_Rn_W_FBITS_imm_1_32::make_opcode(
                                                        insn,
                                                    ),
                                                );
                                            }
                                        }
                                    }
                                } else {
                                    if insn & 0x000400 == 0 {
                                        if insn & 0x001000 == 0 {
                                            if insn & 0x002000 == 0 {
                                                if insn & 0x004000 == 0 {
                                                    if insn & 0xffe0fc00 == 0x5e000000 {
                                                        return Some(SHA1C_Fd_Fn_Vm::make_opcode(
                                                            insn,
                                                        ));
                                                    }
                                                } else {
                                                    if insn & 0xffe0fc00 == 0x5e004000 {
                                                        return Some(
                                                            SHA256H_Fd_Fn_Vm::make_opcode(insn),
                                                        );
                                                    }
                                                }
                                            } else {
                                                if insn & 0x004000 == 0 {
                                                    if insn & 0xffe0fc00 == 0x5e002000 {
                                                        return Some(SHA1M_Fd_Fn_Vm::make_opcode(
                                                            insn,
                                                        ));
                                                    }
                                                } else {
                                                    if insn & 0xffe0fc00 == 0x5e006000 {
                                                        return Some(
                                                            SHA256SU1_Vd_Vn_Vm::make_opcode(insn),
                                                        );
                                                    }
                                                }
                                            }
                                        } else {
                                            if insn & 0x002000 == 0 {
                                                if insn & 0x004000 == 0 {
                                                    if insn & 0xffe0fc00 == 0x5e001000 {
                                                        return Some(SHA1P_Fd_Fn_Vm::make_opcode(
                                                            insn,
                                                        ));
                                                    }
                                                } else {
                                                    if insn & 0xffe0fc00 == 0x5e005000 {
                                                        return Some(
                                                            SHA256H2_Fd_Fn_Vm::make_opcode(insn),
                                                        );
                                                    }
                                                }
                                            } else {
                                                if insn & 0xffe0fc00 == 0x5e003000 {
                                                    return Some(SHA1SU0_Vd_Vn_Vm::make_opcode(
                                                        insn,
                                                    ));
                                                }
                                            }
                                        }
                                    } else {
                                        if insn & 0x000800 == 0 {
                                            if insn & 0x002000 == 0 {
                                                if insn & 0xffe0fc00 == 0x5e000400 {
                                                    return Some(DUP_Sd_En::make_opcode(insn));
                                                }
                                            } else {
                                                if insn & 0xffe0fc00 == 0x5e402400 {
                                                    return Some(FCMEQ_Sd_Sn_Sm::make_opcode(insn));
                                                }
                                            }
                                        } else {
                                            if insn & 0x002000 == 0 {
                                                if insn & 0xffe0fc00 == 0x5e401c00 {
                                                    return Some(FMULX_Sd_Sn_Sm::make_opcode(insn));
                                                }
                                            } else {
                                                if insn & 0x800000 == 0 {
                                                    if insn & 0xffe0fc00 == 0x5e403c00 {
                                                        return Some(FRECPS_Sd_Sn_Sm::make_opcode(
                                                            insn,
                                                        ));
                                                    }
                                                } else {
                                                    if insn & 0xffe0fc00 == 0x5ec03c00 {
                                                        return Some(
                                                            FRSQRTS_Sd_Sn_Sm::make_opcode(insn),
                                                        );
                                                    }
                                                }
                                            }
                                        }
                                    }
                                }
                            } else {
                                if insn & 0x000800 == 0 {
                                    if insn & 0x001000 == 0 {
                                        if insn & 0x002000 == 0 {
                                            if insn & 0xff20fc00 == 0x7e008400 {
                                                return Some(SQRDMLAH_Sd_Sn_Sm::make_opcode(insn));
                                            }
                                        } else {
                                            if insn & 0x800000 == 0 {
                                                if insn & 0xffe0fc00 == 0x7e402400 {
                                                    return Some(FCMGE_Sd_Sn_Sm::make_opcode(insn));
                                                }
                                            } else {
                                                if insn & 0xffe0fc00 == 0x7ec02400 {
                                                    return Some(FCMGT_Sd_Sn_Sm::make_opcode(insn));
                                                }
                                            }
                                        }
                                    } else {
                                        if insn & 0xffe0fc00 == 0x7ec01400 {
                                            return Some(FABD_Sd_Sn_Sm::make_opcode(insn));
                                        }
                                    }
                                } else {
                                    if insn & 0x002000 == 0 {
                                        if insn & 0xff20fc00 == 0x7e008c00 {
                                            return Some(SQRDMLSH_Sd_Sn_Sm::make_opcode(insn));
                                        }
                                    } else {
                                        if insn & 0x800000 == 0 {
                                            if insn & 0xffe0fc00 == 0x7e402c00 {
                                                return Some(FACGE_Sd_Sn_Sm::make_opcode(insn));
                                            }
                                        } else {
                                            if insn & 0xffe0fc00 == 0x7ec02c00 {
                                                return Some(FACGT_Sd_Sn_Sm::make_opcode(insn));
                                            }
                                        }
                                    }
                                }
                            }
                        }
                    } else {
                        if insn & 0x10000000 == 0 {
                            if insn & 0x008000 == 0 {
                                if insn & 0x20000000 == 0 {
                                    if insn & 0x80000000 == 0 {
                                        if insn & 0x000400 == 0 {
                                            if insn & 0x000800 == 0 {
                                                if insn & 0x001000 == 0 {
                                                    if insn & 0x002000 == 0 {
                                                        if insn & 0x004000 == 0 {
                                                            if insn & 0x40000000 == 0 {
                                                                if insn & 0xff20fc00 == 0xe200000 {
                                                                    return Some(
                                                                        SADDL_Vd_Vn_Vm::make_opcode(
                                                                            insn,
                                                                        ),
                                                                    );
                                                                }
                                                            } else {
                                                                if insn & 0xff20fc00 == 0x4e200000 {
                                                                    return Some (SADDL2_Vd_Vn_Vm :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x40000000 == 0 {
                                                                if insn & 0xff20fc00 == 0xe204000 {
                                                                    return Some(
                                                                        ADDHN_Vd_Vn_Vm::make_opcode(
                                                                            insn,
                                                                        ),
                                                                    );
                                                                }
                                                            } else {
                                                                if insn & 0xff20fc00 == 0x4e204000 {
                                                                    return Some (ADDHN2_Vd_Vn_Vm :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x004000 == 0 {
                                                            if insn & 0x40000000 == 0 {
                                                                if insn & 0xff20fc00 == 0xe202000 {
                                                                    return Some(
                                                                        SSUBL_Vd_Vn_Vm::make_opcode(
                                                                            insn,
                                                                        ),
                                                                    );
                                                                }
                                                            } else {
                                                                if insn & 0xff20fc00 == 0x4e202000 {
                                                                    return Some (SSUBL2_Vd_Vn_Vm :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x40000000 == 0 {
                                                                if insn & 0xff20fc00 == 0xe206000 {
                                                                    return Some(
                                                                        SUBHN_Vd_Vn_Vm::make_opcode(
                                                                            insn,
                                                                        ),
                                                                    );
                                                                }
                                                            } else {
                                                                if insn & 0xff20fc00 == 0x4e206000 {
                                                                    return Some (SUBHN2_Vd_Vn_Vm :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x002000 == 0 {
                                                        if insn & 0x004000 == 0 {
                                                            if insn & 0x40000000 == 0 {
                                                                if insn & 0xff20fc00 == 0xe201000 {
                                                                    return Some(
                                                                        SADDW_Vd_Vn_Vm::make_opcode(
                                                                            insn,
                                                                        ),
                                                                    );
                                                                }
                                                            } else {
                                                                if insn & 0xff20fc00 == 0x4e201000 {
                                                                    return Some (SADDW2_Vd_Vn_Vm :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x40000000 == 0 {
                                                                if insn & 0xff20fc00 == 0xe205000 {
                                                                    return Some(
                                                                        SABAL_Vd_Vn_Vm::make_opcode(
                                                                            insn,
                                                                        ),
                                                                    );
                                                                }
                                                            } else {
                                                                if insn & 0xff20fc00 == 0x4e205000 {
                                                                    return Some (SABAL2_Vd_Vn_Vm :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x004000 == 0 {
                                                            if insn & 0x40000000 == 0 {
                                                                if insn & 0xff20fc00 == 0xe203000 {
                                                                    return Some(
                                                                        SSUBW_Vd_Vn_Vm::make_opcode(
                                                                            insn,
                                                                        ),
                                                                    );
                                                                }
                                                            } else {
                                                                if insn & 0xff20fc00 == 0x4e203000 {
                                                                    return Some (SSUBW2_Vd_Vn_Vm :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x40000000 == 0 {
                                                                if insn & 0xff20fc00 == 0xe207000 {
                                                                    return Some(
                                                                        SABDL_Vd_Vn_Vm::make_opcode(
                                                                            insn,
                                                                        ),
                                                                    );
                                                                }
                                                            } else {
                                                                if insn & 0xff20fc00 == 0x4e207000 {
                                                                    return Some (SABDL2_Vd_Vn_Vm :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0x001000 == 0 {
                                                    if insn & 0x002000 == 0 {
                                                        if insn & 0x004000 == 0 {
                                                            if insn & 0xbf3ffc00 == 0xe200800 {
                                                                return Some(
                                                                    REV64_Vd_Vn::make_opcode(insn),
                                                                );
                                                            }
                                                        } else {
                                                            if insn & 0x010000 == 0 {
                                                                if insn & 0x080000 == 0 {
                                                                    if insn & 0xbf3ffc00
                                                                        == 0xe204800
                                                                    {
                                                                        return Some(
                                                                            CLS_Vd_Vn::make_opcode(
                                                                                insn,
                                                                            ),
                                                                        );
                                                                    }
                                                                } else {
                                                                    if insn & 0xfffffc00
                                                                        == 0x4e284800
                                                                    {
                                                                        return Some(
                                                                            AESE_Vd_Vn::make_opcode(
                                                                                insn,
                                                                            ),
                                                                        );
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0x40000000 == 0 {
                                                                    if insn & 0xff3ffc00
                                                                        == 0xe214800
                                                                    {
                                                                        return Some (SQXTN_Vd_Vn :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xff3ffc00
                                                                        == 0x4e214800
                                                                    {
                                                                        return Some (SQXTN2_Vd_Vn :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x004000 == 0 {
                                                            if insn & 0x010000 == 0 {
                                                                if insn & 0xbf3ffc00 == 0xe202800 {
                                                                    return Some(
                                                                        SADDLP_Vd_Vn::make_opcode(
                                                                            insn,
                                                                        ),
                                                                    );
                                                                }
                                                            } else {
                                                                if insn & 0x40000000 == 0 {
                                                                    if insn & 0xff3ffc00
                                                                        == 0xe212800
                                                                    {
                                                                        return Some(
                                                                            XTN_Vd_Vn::make_opcode(
                                                                                insn,
                                                                            ),
                                                                        );
                                                                    }
                                                                } else {
                                                                    if insn & 0xff3ffc00
                                                                        == 0x4e212800
                                                                    {
                                                                        return Some(
                                                                            XTN2_Vd_Vn::make_opcode(
                                                                                insn,
                                                                            ),
                                                                        );
                                                                    }
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x010000 == 0 {
                                                                if insn & 0x080000 == 0 {
                                                                    if insn & 0xbf3ffc00
                                                                        == 0xe206800
                                                                    {
                                                                        return Some (SADALP_Vd_Vn :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xfffffc00
                                                                        == 0x4e286800
                                                                    {
                                                                        return Some (AESMC_Vd_Vn :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0x800000 == 0 {
                                                                    if insn & 0x40000000 == 0 {
                                                                        if insn & 0xffbffc00
                                                                            == 0xe216800
                                                                        {
                                                                            return Some (FCVTN_Vd_Vn :: make_opcode (insn)) ;
                                                                        }
                                                                    } else {
                                                                        if insn & 0xffbffc00
                                                                            == 0x4e216800
                                                                        {
                                                                            return Some (FCVTN2_Vd_Vn :: make_opcode (insn)) ;
                                                                        }
                                                                    }
                                                                } else {
                                                                    if insn & 0x40000000 == 0 {
                                                                        if insn & 0xfffffc00
                                                                            == 0xea16800
                                                                        {
                                                                            return Some (BFCVTN_Vd_Vn :: make_opcode (insn)) ;
                                                                        }
                                                                    } else {
                                                                        if insn & 0xfffffc00
                                                                            == 0x4ea16800
                                                                        {
                                                                            return Some (BFCVTN2_Vd_Vn :: make_opcode (insn)) ;
                                                                        }
                                                                    }
                                                                }
                                                            }
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x002000 == 0 {
                                                        if insn & 0x004000 == 0 {
                                                            if insn & 0xbf3ffc00 == 0xe201800 {
                                                                return Some(
                                                                    REV16_Vd_Vn::make_opcode(insn),
                                                                );
                                                            }
                                                        } else {
                                                            if insn & 0x080000 == 0 {
                                                                if insn & 0xbf3ffc00 == 0xe205800 {
                                                                    return Some(
                                                                        CNT_Vd_Vn::make_opcode(
                                                                            insn,
                                                                        ),
                                                                    );
                                                                }
                                                            } else {
                                                                if insn & 0xfffffc00 == 0x4e285800 {
                                                                    return Some(
                                                                        AESD_Vd_Vn::make_opcode(
                                                                            insn,
                                                                        ),
                                                                    );
                                                                }
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x004000 == 0 {
                                                            if insn & 0x100000 == 0 {
                                                                if insn & 0xbf3ffc00 == 0xe203800 {
                                                                    return Some(
                                                                        SUQADD_Vd_Vn::make_opcode(
                                                                            insn,
                                                                        ),
                                                                    );
                                                                }
                                                            } else {
                                                                if insn & 0xbf3ffc00 == 0xe303800 {
                                                                    return Some(
                                                                        SADDLV_Fd_Vn::make_opcode(
                                                                            insn,
                                                                        ),
                                                                    );
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x010000 == 0 {
                                                                if insn & 0x080000 == 0 {
                                                                    if insn & 0xbf3ffc00
                                                                        == 0xe207800
                                                                    {
                                                                        return Some (SQABS_Vd_Vn :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xfffffc00
                                                                        == 0x4e287800
                                                                    {
                                                                        return Some (AESIMC_Vd_Vn :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0x40000000 == 0 {
                                                                    if insn & 0xffbffc00
                                                                        == 0xe217800
                                                                    {
                                                                        return Some (FCVTL_Vd_Vn :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xffbffc00
                                                                        == 0x4e217800
                                                                    {
                                                                        return Some (FCVTL2_Vd_Vn :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            }
                                                        }
                                                    }
                                                }
                                            }
                                        } else {
                                            if insn & 0x000800 == 0 {
                                                if insn & 0x001000 == 0 {
                                                    if insn & 0x002000 == 0 {
                                                        if insn & 0x004000 == 0 {
                                                            if insn & 0xbf20fc00 == 0xe200400 {
                                                                return Some(
                                                                    SHADD_Vd_Vn_Vm::make_opcode(
                                                                        insn,
                                                                    ),
                                                                );
                                                            }
                                                        } else {
                                                            if insn & 0xbf20fc00 == 0xe204400 {
                                                                return Some(
                                                                    SSHL_Vd_Vn_Vm::make_opcode(
                                                                        insn,
                                                                    ),
                                                                );
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x004000 == 0 {
                                                            if insn & 0xbf20fc00 == 0xe202400 {
                                                                return Some(
                                                                    SHSUB_Vd_Vn_Vm::make_opcode(
                                                                        insn,
                                                                    ),
                                                                );
                                                            }
                                                        } else {
                                                            if insn & 0xbf20fc00 == 0xe206400 {
                                                                return Some(
                                                                    SMAX_Vd_Vn_Vm::make_opcode(
                                                                        insn,
                                                                    ),
                                                                );
                                                            }
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x002000 == 0 {
                                                        if insn & 0x004000 == 0 {
                                                            if insn & 0xbf20fc00 == 0xe201400 {
                                                                return Some(
                                                                    SRHADD_Vd_Vn_Vm::make_opcode(
                                                                        insn,
                                                                    ),
                                                                );
                                                            }
                                                        } else {
                                                            if insn & 0xbf20fc00 == 0xe205400 {
                                                                return Some(
                                                                    SRSHL_Vd_Vn_Vm::make_opcode(
                                                                        insn,
                                                                    ),
                                                                );
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x004000 == 0 {
                                                            if insn & 0xbf20fc00 == 0xe203400 {
                                                                return Some(
                                                                    CMGT_Vd_Vn_Vm::make_opcode(
                                                                        insn,
                                                                    ),
                                                                );
                                                            }
                                                        } else {
                                                            if insn & 0xbf20fc00 == 0xe207400 {
                                                                return Some(
                                                                    SABD_Vd_Vn_Vm::make_opcode(
                                                                        insn,
                                                                    ),
                                                                );
                                                            }
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0x001000 == 0 {
                                                    if insn & 0x002000 == 0 {
                                                        if insn & 0x004000 == 0 {
                                                            if insn & 0xbf20fc00 == 0xe200c00 {
                                                                return Some(
                                                                    SQADD_Vd_Vn_Vm::make_opcode(
                                                                        insn,
                                                                    ),
                                                                );
                                                            }
                                                        } else {
                                                            if insn & 0xbf20fc00 == 0xe204c00 {
                                                                return Some(
                                                                    SQSHL_Vd_Vn_Vm::make_opcode(
                                                                        insn,
                                                                    ),
                                                                );
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x004000 == 0 {
                                                            if insn & 0xbf20fc00 == 0xe202c00 {
                                                                return Some(
                                                                    SQSUB_Vd_Vn_Vm::make_opcode(
                                                                        insn,
                                                                    ),
                                                                );
                                                            }
                                                        } else {
                                                            if insn & 0xbf20fc00 == 0xe206c00 {
                                                                return Some(
                                                                    SMIN_Vd_Vn_Vm::make_opcode(
                                                                        insn,
                                                                    ),
                                                                );
                                                            }
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x002000 == 0 {
                                                        if insn & 0x004000 == 0 {
                                                            if insn & 0x400000 == 0 {
                                                                if insn & 0x800000 == 0 {
                                                                    if insn & 0xbfe0fc00
                                                                        == 0xe201c00
                                                                    {
                                                                        return Some (AND_Vd_Vn_Vm :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xbfe0fc00
                                                                        == 0xea01c00
                                                                    {
                                                                        return Some (ORR_Vd_Vn_Vm :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0x800000 == 0 {
                                                                    if insn & 0xbfe0fc00
                                                                        == 0xe601c00
                                                                    {
                                                                        return Some (BIC_Vd_Vn_Vm :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xbfe0fc00
                                                                        == 0xee01c00
                                                                    {
                                                                        return Some (ORN_Vd_Vn_Vm :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0xbf20fc00 == 0xe205c00 {
                                                                return Some(
                                                                    SQRSHL_Vd_Vn_Vm::make_opcode(
                                                                        insn,
                                                                    ),
                                                                );
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x004000 == 0 {
                                                            if insn & 0xbf20fc00 == 0xe203c00 {
                                                                return Some(
                                                                    CMGE_Vd_Vn_Vm::make_opcode(
                                                                        insn,
                                                                    ),
                                                                );
                                                            }
                                                        } else {
                                                            if insn & 0xbf20fc00 == 0xe207c00 {
                                                                return Some(
                                                                    SABA_Vd_Vn_Vm::make_opcode(
                                                                        insn,
                                                                    ),
                                                                );
                                                            }
                                                        }
                                                    }
                                                }
                                            }
                                        }
                                    } else {
                                        if insn & 0xffe08000 == 0xce200000 {
                                            return Some(BCAX_Vd_Vn_Vm_Va::make_opcode(insn));
                                        }
                                    }
                                } else {
                                    if insn & 0x000400 == 0 {
                                        if insn & 0x000800 == 0 {
                                            if insn & 0x001000 == 0 {
                                                if insn & 0x002000 == 0 {
                                                    if insn & 0x004000 == 0 {
                                                        if insn & 0x40000000 == 0 {
                                                            if insn & 0xff20fc00 == 0x2e200000 {
                                                                return Some(
                                                                    UADDL_Vd_Vn_Vm::make_opcode(
                                                                        insn,
                                                                    ),
                                                                );
                                                            }
                                                        } else {
                                                            if insn & 0xff20fc00 == 0x6e200000 {
                                                                return Some(
                                                                    UADDL2_Vd_Vn_Vm::make_opcode(
                                                                        insn,
                                                                    ),
                                                                );
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x40000000 == 0 {
                                                            if insn & 0xff20fc00 == 0x2e204000 {
                                                                return Some(
                                                                    RADDHN_Vd_Vn_Vm::make_opcode(
                                                                        insn,
                                                                    ),
                                                                );
                                                            }
                                                        } else {
                                                            if insn & 0xff20fc00 == 0x6e204000 {
                                                                return Some(
                                                                    RADDHN2_Vd_Vn_Vm::make_opcode(
                                                                        insn,
                                                                    ),
                                                                );
                                                            }
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x004000 == 0 {
                                                        if insn & 0x40000000 == 0 {
                                                            if insn & 0xff20fc00 == 0x2e202000 {
                                                                return Some(
                                                                    USUBL_Vd_Vn_Vm::make_opcode(
                                                                        insn,
                                                                    ),
                                                                );
                                                            }
                                                        } else {
                                                            if insn & 0xff20fc00 == 0x6e202000 {
                                                                return Some(
                                                                    USUBL2_Vd_Vn_Vm::make_opcode(
                                                                        insn,
                                                                    ),
                                                                );
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x40000000 == 0 {
                                                            if insn & 0xff20fc00 == 0x2e206000 {
                                                                return Some(
                                                                    RSUBHN_Vd_Vn_Vm::make_opcode(
                                                                        insn,
                                                                    ),
                                                                );
                                                            }
                                                        } else {
                                                            if insn & 0xff20fc00 == 0x6e206000 {
                                                                return Some(
                                                                    RSUBHN2_Vd_Vn_Vm::make_opcode(
                                                                        insn,
                                                                    ),
                                                                );
                                                            }
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0x002000 == 0 {
                                                    if insn & 0x004000 == 0 {
                                                        if insn & 0x40000000 == 0 {
                                                            if insn & 0xff20fc00 == 0x2e201000 {
                                                                return Some(
                                                                    UADDW_Vd_Vn_Vm::make_opcode(
                                                                        insn,
                                                                    ),
                                                                );
                                                            }
                                                        } else {
                                                            if insn & 0xff20fc00 == 0x6e201000 {
                                                                return Some(
                                                                    UADDW2_Vd_Vn_Vm::make_opcode(
                                                                        insn,
                                                                    ),
                                                                );
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x40000000 == 0 {
                                                            if insn & 0xff20fc00 == 0x2e205000 {
                                                                return Some(
                                                                    UABAL_Vd_Vn_Vm::make_opcode(
                                                                        insn,
                                                                    ),
                                                                );
                                                            }
                                                        } else {
                                                            if insn & 0xff20fc00 == 0x6e205000 {
                                                                return Some(
                                                                    UABAL2_Vd_Vn_Vm::make_opcode(
                                                                        insn,
                                                                    ),
                                                                );
                                                            }
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x004000 == 0 {
                                                        if insn & 0x40000000 == 0 {
                                                            if insn & 0xff20fc00 == 0x2e203000 {
                                                                return Some(
                                                                    USUBW_Vd_Vn_Vm::make_opcode(
                                                                        insn,
                                                                    ),
                                                                );
                                                            }
                                                        } else {
                                                            if insn & 0xff20fc00 == 0x6e203000 {
                                                                return Some(
                                                                    USUBW2_Vd_Vn_Vm::make_opcode(
                                                                        insn,
                                                                    ),
                                                                );
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x40000000 == 0 {
                                                            if insn & 0xff20fc00 == 0x2e207000 {
                                                                return Some(
                                                                    UABDL_Vd_Vn_Vm::make_opcode(
                                                                        insn,
                                                                    ),
                                                                );
                                                            }
                                                        } else {
                                                            if insn & 0xff20fc00 == 0x6e207000 {
                                                                return Some(
                                                                    UABDL2_Vd_Vn_Vm::make_opcode(
                                                                        insn,
                                                                    ),
                                                                );
                                                            }
                                                        }
                                                    }
                                                }
                                            }
                                        } else {
                                            if insn & 0x001000 == 0 {
                                                if insn & 0x002000 == 0 {
                                                    if insn & 0x004000 == 0 {
                                                        if insn & 0xbf3ffc00 == 0x2e200800 {
                                                            return Some(REV32_Vd_Vn::make_opcode(
                                                                insn,
                                                            ));
                                                        }
                                                    } else {
                                                        if insn & 0x010000 == 0 {
                                                            if insn & 0xbf3ffc00 == 0x2e204800 {
                                                                return Some(
                                                                    CLZ_Vd_Vn::make_opcode(insn),
                                                                );
                                                            }
                                                        } else {
                                                            if insn & 0x40000000 == 0 {
                                                                if insn & 0xff3ffc00 == 0x2e214800 {
                                                                    return Some(
                                                                        UQXTN_Vd_Vn::make_opcode(
                                                                            insn,
                                                                        ),
                                                                    );
                                                                }
                                                            } else {
                                                                if insn & 0xff3ffc00 == 0x6e214800 {
                                                                    return Some(
                                                                        UQXTN2_Vd_Vn::make_opcode(
                                                                            insn,
                                                                        ),
                                                                    );
                                                                }
                                                            }
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x004000 == 0 {
                                                        if insn & 0x010000 == 0 {
                                                            if insn & 0xbf3ffc00 == 0x2e202800 {
                                                                return Some(
                                                                    UADDLP_Vd_Vn::make_opcode(insn),
                                                                );
                                                            }
                                                        } else {
                                                            if insn & 0x40000000 == 0 {
                                                                if insn & 0xff3ffc00 == 0x2e212800 {
                                                                    return Some(
                                                                        SQXTUN_Vd_Vn::make_opcode(
                                                                            insn,
                                                                        ),
                                                                    );
                                                                }
                                                            } else {
                                                                if insn & 0xff3ffc00 == 0x6e212800 {
                                                                    return Some(
                                                                        SQXTUN2_Vd_Vn::make_opcode(
                                                                            insn,
                                                                        ),
                                                                    );
                                                                }
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x010000 == 0 {
                                                            if insn & 0xbf3ffc00 == 0x2e206800 {
                                                                return Some(
                                                                    UADALP_Vd_Vn::make_opcode(insn),
                                                                );
                                                            }
                                                        } else {
                                                            if insn & 0x40000000 == 0 {
                                                                if insn & 0xfffffc00 == 0x2e616800 {
                                                                    return Some(
                                                                        FCVTXN_Vd_Vn::make_opcode(
                                                                            insn,
                                                                        ),
                                                                    );
                                                                }
                                                            } else {
                                                                if insn & 0xfffffc00 == 0x6e616800 {
                                                                    return Some(
                                                                        FCVTXN2_Vd_Vn::make_opcode(
                                                                            insn,
                                                                        ),
                                                                    );
                                                                }
                                                            }
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0x002000 == 0 {
                                                    if insn & 0x400000 == 0 {
                                                        if insn & 0xbffffc00 == 0x2e205800 {
                                                            return Some(NOT_Vd_Vn::make_opcode(
                                                                insn,
                                                            ));
                                                        }
                                                    } else {
                                                        if insn & 0xbffffc00 == 0x2e605800 {
                                                            return Some(RBIT_Vd_Vn::make_opcode(
                                                                insn,
                                                            ));
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x004000 == 0 {
                                                        if insn & 0x010000 == 0 {
                                                            if insn & 0x100000 == 0 {
                                                                if insn & 0xbf3ffc00 == 0x2e203800 {
                                                                    return Some(
                                                                        USQADD_Vd_Vn::make_opcode(
                                                                            insn,
                                                                        ),
                                                                    );
                                                                }
                                                            } else {
                                                                if insn & 0xbf3ffc00 == 0x2e303800 {
                                                                    return Some(
                                                                        UADDLV_Fd_Vn::make_opcode(
                                                                            insn,
                                                                        ),
                                                                    );
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x40000000 == 0 {
                                                                if insn & 0xff3ffc00 == 0x2e213800 {
                                                                    return Some (SHLL_Vd_Vn_SHLL_IMM :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xff3ffc00 == 0x6e213800 {
                                                                    return Some (SHLL2_Vd_Vn_SHLL_IMM :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0xbf3ffc00 == 0x2e207800 {
                                                            return Some(SQNEG_Vd_Vn::make_opcode(
                                                                insn,
                                                            ));
                                                        }
                                                    }
                                                }
                                            }
                                        }
                                    } else {
                                        if insn & 0x000800 == 0 {
                                            if insn & 0x001000 == 0 {
                                                if insn & 0x002000 == 0 {
                                                    if insn & 0x004000 == 0 {
                                                        if insn & 0xbf20fc00 == 0x2e200400 {
                                                            return Some(
                                                                UHADD_Vd_Vn_Vm::make_opcode(insn),
                                                            );
                                                        }
                                                    } else {
                                                        if insn & 0xbf20fc00 == 0x2e204400 {
                                                            return Some(
                                                                USHL_Vd_Vn_Vm::make_opcode(insn),
                                                            );
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x004000 == 0 {
                                                        if insn & 0xbf20fc00 == 0x2e202400 {
                                                            return Some(
                                                                UHSUB_Vd_Vn_Vm::make_opcode(insn),
                                                            );
                                                        }
                                                    } else {
                                                        if insn & 0xbf20fc00 == 0x2e206400 {
                                                            return Some(
                                                                UMAX_Vd_Vn_Vm::make_opcode(insn),
                                                            );
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0x002000 == 0 {
                                                    if insn & 0x004000 == 0 {
                                                        if insn & 0xbf20fc00 == 0x2e201400 {
                                                            return Some(
                                                                URHADD_Vd_Vn_Vm::make_opcode(insn),
                                                            );
                                                        }
                                                    } else {
                                                        if insn & 0xbf20fc00 == 0x2e205400 {
                                                            return Some(
                                                                URSHL_Vd_Vn_Vm::make_opcode(insn),
                                                            );
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x004000 == 0 {
                                                        if insn & 0xbf20fc00 == 0x2e203400 {
                                                            return Some(
                                                                CMHI_Vd_Vn_Vm::make_opcode(insn),
                                                            );
                                                        }
                                                    } else {
                                                        if insn & 0xbf20fc00 == 0x2e207400 {
                                                            return Some(
                                                                UABD_Vd_Vn_Vm::make_opcode(insn),
                                                            );
                                                        }
                                                    }
                                                }
                                            }
                                        } else {
                                            if insn & 0x001000 == 0 {
                                                if insn & 0x002000 == 0 {
                                                    if insn & 0x004000 == 0 {
                                                        if insn & 0xbf20fc00 == 0x2e200c00 {
                                                            return Some(
                                                                UQADD_Vd_Vn_Vm::make_opcode(insn),
                                                            );
                                                        }
                                                    } else {
                                                        if insn & 0xbf20fc00 == 0x2e204c00 {
                                                            return Some(
                                                                UQSHL_Vd_Vn_Vm::make_opcode(insn),
                                                            );
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x004000 == 0 {
                                                        if insn & 0xbf20fc00 == 0x2e202c00 {
                                                            return Some(
                                                                UQSUB_Vd_Vn_Vm::make_opcode(insn),
                                                            );
                                                        }
                                                    } else {
                                                        if insn & 0xbf20fc00 == 0x2e206c00 {
                                                            return Some(
                                                                UMIN_Vd_Vn_Vm::make_opcode(insn),
                                                            );
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0x002000 == 0 {
                                                    if insn & 0x004000 == 0 {
                                                        if insn & 0x400000 == 0 {
                                                            if insn & 0x800000 == 0 {
                                                                if insn & 0xbfe0fc00 == 0x2e201c00 {
                                                                    return Some(
                                                                        EOR_Vd_Vn_Vm::make_opcode(
                                                                            insn,
                                                                        ),
                                                                    );
                                                                }
                                                            } else {
                                                                if insn & 0xbfe0fc00 == 0x2ea01c00 {
                                                                    return Some(
                                                                        BIT_Vd_Vn_Vm::make_opcode(
                                                                            insn,
                                                                        ),
                                                                    );
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x800000 == 0 {
                                                                if insn & 0xbfe0fc00 == 0x2e601c00 {
                                                                    return Some(
                                                                        BSL_Vd_Vn_Vm::make_opcode(
                                                                            insn,
                                                                        ),
                                                                    );
                                                                }
                                                            } else {
                                                                if insn & 0xbfe0fc00 == 0x2ee01c00 {
                                                                    return Some(
                                                                        BIF_Vd_Vn_Vm::make_opcode(
                                                                            insn,
                                                                        ),
                                                                    );
                                                                }
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0xbf20fc00 == 0x2e205c00 {
                                                            return Some(
                                                                UQRSHL_Vd_Vn_Vm::make_opcode(insn),
                                                            );
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x004000 == 0 {
                                                        if insn & 0xbf20fc00 == 0x2e203c00 {
                                                            return Some(
                                                                CMHS_Vd_Vn_Vm::make_opcode(insn),
                                                            );
                                                        }
                                                    } else {
                                                        if insn & 0xbf20fc00 == 0x2e207c00 {
                                                            return Some(
                                                                UABA_Vd_Vn_Vm::make_opcode(insn),
                                                            );
                                                        }
                                                    }
                                                }
                                            }
                                        }
                                    }
                                }
                            } else {
                                if insn & 0x000400 == 0 {
                                    if insn & 0x000800 == 0 {
                                        if insn & 0x001000 == 0 {
                                            if insn & 0x002000 == 0 {
                                                if insn & 0x004000 == 0 {
                                                    if insn & 0x20000000 == 0 {
                                                        if insn & 0x40000000 == 0 {
                                                            if insn & 0xff20fc00 == 0xe208000 {
                                                                return Some(
                                                                    SMLAL_Vd_Vn_Vm::make_opcode(
                                                                        insn,
                                                                    ),
                                                                );
                                                            }
                                                        } else {
                                                            if insn & 0x80000000 == 0 {
                                                                if insn & 0xff20fc00 == 0x4e208000 {
                                                                    return Some (SMLAL2_Vd_Vn_Vm :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xffe0fc00 == 0xce608000 {
                                                                    return Some (SHA512H_Fd_Fn_Vm :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x40000000 == 0 {
                                                            if insn & 0xff20fc00 == 0x2e208000 {
                                                                return Some(
                                                                    UMLAL_Vd_Vn_Vm::make_opcode(
                                                                        insn,
                                                                    ),
                                                                );
                                                            }
                                                        } else {
                                                            if insn & 0xff20fc00 == 0x6e208000 {
                                                                return Some(
                                                                    UMLAL2_Vd_Vn_Vm::make_opcode(
                                                                        insn,
                                                                    ),
                                                                );
                                                            }
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x20000000 == 0 {
                                                        if insn & 0x40000000 == 0 {
                                                            if insn & 0xff20fc00 == 0xe20c000 {
                                                                return Some(
                                                                    SMULL_Vd_Vn_Vm::make_opcode(
                                                                        insn,
                                                                    ),
                                                                );
                                                            }
                                                        } else {
                                                            if insn & 0x80000000 == 0 {
                                                                if insn & 0xff20fc00 == 0x4e20c000 {
                                                                    return Some (SMULL2_Vd_Vn_Vm :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xffe0fc00 == 0xce60c000 {
                                                                    return Some (SM3PARTW1_Vd_Vn_Vm :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x40000000 == 0 {
                                                            if insn & 0xff20fc00 == 0x2e20c000 {
                                                                return Some(
                                                                    UMULL_Vd_Vn_Vm::make_opcode(
                                                                        insn,
                                                                    ),
                                                                );
                                                            }
                                                        } else {
                                                            if insn & 0xff20fc00 == 0x6e20c000 {
                                                                return Some(
                                                                    UMULL2_Vd_Vn_Vm::make_opcode(
                                                                        insn,
                                                                    ),
                                                                );
                                                            }
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0x004000 == 0 {
                                                    if insn & 0x20000000 == 0 {
                                                        if insn & 0x40000000 == 0 {
                                                            if insn & 0xff20fc00 == 0xe20a000 {
                                                                return Some(
                                                                    SMLSL_Vd_Vn_Vm::make_opcode(
                                                                        insn,
                                                                    ),
                                                                );
                                                            }
                                                        } else {
                                                            if insn & 0xff20fc00 == 0x4e20a000 {
                                                                return Some(
                                                                    SMLSL2_Vd_Vn_Vm::make_opcode(
                                                                        insn,
                                                                    ),
                                                                );
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x40000000 == 0 {
                                                            if insn & 0xff20fc00 == 0x2e20a000 {
                                                                return Some(
                                                                    UMLSL_Vd_Vn_Vm::make_opcode(
                                                                        insn,
                                                                    ),
                                                                );
                                                            }
                                                        } else {
                                                            if insn & 0xff20fc00 == 0x6e20a000 {
                                                                return Some(
                                                                    UMLSL2_Vd_Vn_Vm::make_opcode(
                                                                        insn,
                                                                    ),
                                                                );
                                                            }
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x400000 == 0 {
                                                        if insn & 0x40000000 == 0 {
                                                            if insn & 0xffe0fc00 == 0xe20e000 {
                                                                return Some(
                                                                    PMULL_Vd_Vn_Vm::make_opcode(
                                                                        insn,
                                                                    ),
                                                                );
                                                            }
                                                        } else {
                                                            if insn & 0xffe0fc00 == 0x4e20e000 {
                                                                return Some(
                                                                    PMULL2_Vd_Vn_Vm::make_opcode(
                                                                        insn,
                                                                    ),
                                                                );
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x40000000 == 0 {
                                                            if insn & 0xffe0fc00 == 0xee0e000 {
                                                                return Some (PMULL_Vd_V_1Q_Vn_V_1D_Vm_V_1D :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xffe0fc00 == 0x4ee0e000 {
                                                                return Some (PMULL2_Vd_V_1Q_Vn_V_2D_Vm_V_2D :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    }
                                                }
                                            }
                                        } else {
                                            if insn & 0x002000 == 0 {
                                                if insn & 0x004000 == 0 {
                                                    if insn & 0x40000000 == 0 {
                                                        if insn & 0xff20fc00 == 0xe209000 {
                                                            return Some(
                                                                SQDMLAL_Vd_Vn_Vm::make_opcode(insn),
                                                            );
                                                        }
                                                    } else {
                                                        if insn & 0xff20fc00 == 0x4e209000 {
                                                            return Some(
                                                                SQDMLAL2_Vd_Vn_Vm::make_opcode(
                                                                    insn,
                                                                ),
                                                            );
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x40000000 == 0 {
                                                        if insn & 0xff20fc00 == 0xe20d000 {
                                                            return Some(
                                                                SQDMULL_Vd_Vn_Vm::make_opcode(insn),
                                                            );
                                                        }
                                                    } else {
                                                        if insn & 0xff20fc00 == 0x4e20d000 {
                                                            return Some(
                                                                SQDMULL2_Vd_Vn_Vm::make_opcode(
                                                                    insn,
                                                                ),
                                                            );
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0x40000000 == 0 {
                                                    if insn & 0xff20fc00 == 0xe20b000 {
                                                        return Some(
                                                            SQDMLSL_Vd_Vn_Vm::make_opcode(insn),
                                                        );
                                                    }
                                                } else {
                                                    if insn & 0xff20fc00 == 0x4e20b000 {
                                                        return Some(
                                                            SQDMLSL2_Vd_Vn_Vm::make_opcode(insn),
                                                        );
                                                    }
                                                }
                                            }
                                        }
                                    } else {
                                        if insn & 0x001000 == 0 {
                                            if insn & 0x002000 == 0 {
                                                if insn & 0x004000 == 0 {
                                                    if insn & 0x20000000 == 0 {
                                                        if insn & 0x80000000 == 0 {
                                                            if insn & 0x010000 == 0 {
                                                                if insn & 0xbf3ffc00 == 0xe208800 {
                                                                    return Some (CMGT_Vd_Vn_IMM0 :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0x080000 == 0 {
                                                                    if insn & 0x800000 == 0 {
                                                                        if insn & 0xbfbffc00
                                                                            == 0xe218800
                                                                        {
                                                                            return Some (FRINTN_Vd_Vn :: make_opcode (insn)) ;
                                                                        }
                                                                    } else {
                                                                        if insn & 0xbfbffc00
                                                                            == 0xea18800
                                                                        {
                                                                            return Some (FRINTP_Vd_Vn :: make_opcode (insn)) ;
                                                                        }
                                                                    }
                                                                } else {
                                                                    if insn & 0x800000 == 0 {
                                                                        if insn & 0xbffffc00
                                                                            == 0xe798800
                                                                        {
                                                                            return Some (FRINTN_Vd_V_4H_Vn_V_4H :: make_opcode (insn)) ;
                                                                        }
                                                                    } else {
                                                                        if insn & 0xbffffc00
                                                                            == 0xef98800
                                                                        {
                                                                            return Some (FRINTP_Vd_V_4H_Vn_V_4H :: make_opcode (insn)) ;
                                                                        }
                                                                    }
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0xffe0fc00 == 0xce608800 {
                                                                return Some(
                                                                    SHA512SU1_Vd_Vn_Vm::make_opcode(
                                                                        insn,
                                                                    ),
                                                                );
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x010000 == 0 {
                                                            if insn & 0xbf3ffc00 == 0x2e208800 {
                                                                return Some(
                                                                    CMGE_Vd_Vn_IMM0::make_opcode(
                                                                        insn,
                                                                    ),
                                                                );
                                                            }
                                                        } else {
                                                            if insn & 0x080000 == 0 {
                                                                if insn & 0xbfbffc00 == 0x2e218800 {
                                                                    return Some(
                                                                        FRINTA_Vd_Vn::make_opcode(
                                                                            insn,
                                                                        ),
                                                                    );
                                                                }
                                                            } else {
                                                                if insn & 0xbffffc00 == 0x2e798800 {
                                                                    return Some (FRINTA_Vd_V_4H_Vn_V_4H :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x800000 == 0 {
                                                        if insn & 0x20000000 == 0 {
                                                            if insn & 0x80000000 == 0 {
                                                                if insn & 0x010000 == 0 {
                                                                    if insn & 0xbffffc00
                                                                        == 0xe30c800
                                                                    {
                                                                        return Some (FMAXNMV_Fd_Vn :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0x080000 == 0 {
                                                                        if insn & 0xbfbffc00
                                                                            == 0xe21c800
                                                                        {
                                                                            return Some (FCVTAS_Vd_Vn :: make_opcode (insn)) ;
                                                                        }
                                                                    } else {
                                                                        if insn & 0xbffffc00
                                                                            == 0xe79c800
                                                                        {
                                                                            return Some (FCVTAS_Vd_V_4H_Vn_V_4H :: make_opcode (insn)) ;
                                                                        }
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0xffe0fc00 == 0xce60c800 {
                                                                    return Some (SM4EKEY_Vd_Vn_Vm :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x010000 == 0 {
                                                                if insn & 0xbfbffc00 == 0x2e30c800 {
                                                                    return Some (FMAXNMV_Fd_S_S_Vn_V_4S :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0x080000 == 0 {
                                                                    if insn & 0xbfbffc00
                                                                        == 0x2e21c800
                                                                    {
                                                                        return Some (FCVTAU_Vd_Vn :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xbffffc00
                                                                        == 0x2e79c800
                                                                    {
                                                                        return Some (FCVTAU_Vd_V_4H_Vn_V_4H :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x010000 == 0 {
                                                            if insn & 0x080000 == 0 {
                                                                if insn & 0x100000 == 0 {
                                                                    if insn & 0x20000000 == 0 {
                                                                        if insn & 0xbfbffc00
                                                                            == 0xea0c800
                                                                        {
                                                                            return Some (FCMGT_Vd_Vn_FPIMM0 :: make_opcode (insn)) ;
                                                                        }
                                                                    } else {
                                                                        if insn & 0xbfbffc00
                                                                            == 0x2ea0c800
                                                                        {
                                                                            return Some (FCMGE_Vd_Vn_FPIMM0 :: make_opcode (insn)) ;
                                                                        }
                                                                    }
                                                                } else {
                                                                    if insn & 0x20000000 == 0 {
                                                                        if insn & 0xbffffc00
                                                                            == 0xeb0c800
                                                                        {
                                                                            return Some (FMINNMV_Fd_Vn :: make_opcode (insn)) ;
                                                                        }
                                                                    } else {
                                                                        if insn & 0xbfbffc00
                                                                            == 0x2eb0c800
                                                                        {
                                                                            return Some (FMINNMV_Fd_S_S_Vn_V_4S :: make_opcode (insn)) ;
                                                                        }
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0x20000000 == 0 {
                                                                    if insn & 0xbffffc00
                                                                        == 0xef8c800
                                                                    {
                                                                        return Some (FCMGT_Vd_V_4H_Vn_V_4H_FPIMM0 :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xbffffc00
                                                                        == 0x2ef8c800
                                                                    {
                                                                        return Some (FCMGE_Vd_V_4H_Vn_V_4H_FPIMM0 :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x20000000 == 0 {
                                                                if insn & 0xbfbffc00 == 0xea1c800 {
                                                                    return Some(
                                                                        URECPE_Vd_Vn::make_opcode(
                                                                            insn,
                                                                        ),
                                                                    );
                                                                }
                                                            } else {
                                                                if insn & 0xbfbffc00 == 0x2ea1c800 {
                                                                    return Some(
                                                                        URSQRTE_Vd_Vn::make_opcode(
                                                                            insn,
                                                                        ),
                                                                    );
                                                                }
                                                            }
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0x004000 == 0 {
                                                    if insn & 0x010000 == 0 {
                                                        if insn & 0x100000 == 0 {
                                                            if insn & 0xbf3ffc00 == 0xe20a800 {
                                                                return Some(
                                                                    CMLT_Vd_Vn_IMM0::make_opcode(
                                                                        insn,
                                                                    ),
                                                                );
                                                            }
                                                        } else {
                                                            if insn & 0x20000000 == 0 {
                                                                if insn & 0xbf3ffc00 == 0xe30a800 {
                                                                    return Some(
                                                                        SMAXV_Fd_Vn::make_opcode(
                                                                            insn,
                                                                        ),
                                                                    );
                                                                }
                                                            } else {
                                                                if insn & 0xbf3ffc00 == 0x2e30a800 {
                                                                    return Some(
                                                                        UMAXV_Fd_Vn::make_opcode(
                                                                            insn,
                                                                        ),
                                                                    );
                                                                }
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x080000 == 0 {
                                                            if insn & 0x100000 == 0 {
                                                                if insn & 0x800000 == 0 {
                                                                    if insn & 0x20000000 == 0 {
                                                                        if insn & 0xbfbffc00
                                                                            == 0xe21a800
                                                                        {
                                                                            return Some (FCVTNS_Vd_Vn :: make_opcode (insn)) ;
                                                                        }
                                                                    } else {
                                                                        if insn & 0xbfbffc00
                                                                            == 0x2e21a800
                                                                        {
                                                                            return Some (FCVTNU_Vd_Vn :: make_opcode (insn)) ;
                                                                        }
                                                                    }
                                                                } else {
                                                                    if insn & 0x20000000 == 0 {
                                                                        if insn & 0xbfbffc00
                                                                            == 0xea1a800
                                                                        {
                                                                            return Some (FCVTPS_Vd_Vn :: make_opcode (insn)) ;
                                                                        }
                                                                    } else {
                                                                        if insn & 0xbfbffc00
                                                                            == 0x2ea1a800
                                                                        {
                                                                            return Some (FCVTPU_Vd_Vn :: make_opcode (insn)) ;
                                                                        }
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0x20000000 == 0 {
                                                                    if insn & 0xbf3ffc00
                                                                        == 0xe31a800
                                                                    {
                                                                        return Some (SMINV_Fd_Vn :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xbf3ffc00
                                                                        == 0x2e31a800
                                                                    {
                                                                        return Some (UMINV_Fd_Vn :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x800000 == 0 {
                                                                if insn & 0x20000000 == 0 {
                                                                    if insn & 0xbffffc00
                                                                        == 0xe79a800
                                                                    {
                                                                        return Some (FCVTNS_Vd_V_4H_Vn_V_4H :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xbffffc00
                                                                        == 0x2e79a800
                                                                    {
                                                                        return Some (FCVTNU_Vd_V_4H_Vn_V_4H :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0x20000000 == 0 {
                                                                    if insn & 0xbffffc00
                                                                        == 0xef9a800
                                                                    {
                                                                        return Some (FCVTPS_Vd_V_4H_Vn_V_4H :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xbffffc00
                                                                        == 0x2ef9a800
                                                                    {
                                                                        return Some (FCVTPU_Vd_V_4H_Vn_V_4H :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            }
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x010000 == 0 {
                                                        if insn & 0x080000 == 0 {
                                                            if insn & 0xbfbffc00 == 0xea0e800 {
                                                                return Some(
                                                                    FCMLT_Vd_Vn_FPIMM0::make_opcode(
                                                                        insn,
                                                                    ),
                                                                );
                                                            }
                                                        } else {
                                                            if insn & 0xbffffc00 == 0xef8e800 {
                                                                return Some (FCMLT_Vd_V_4H_Vn_V_4H_FPIMM0 :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x20000000 == 0 {
                                                            if insn & 0xbfbffc00 == 0xe21e800 {
                                                                return Some(
                                                                    FRINT32Z_Vd_Vn::make_opcode(
                                                                        insn,
                                                                    ),
                                                                );
                                                            }
                                                        } else {
                                                            if insn & 0xbfbffc00 == 0x2e21e800 {
                                                                return Some(
                                                                    FRINT32X_Vd_Vn::make_opcode(
                                                                        insn,
                                                                    ),
                                                                );
                                                            }
                                                        }
                                                    }
                                                }
                                            }
                                        } else {
                                            if insn & 0x002000 == 0 {
                                                if insn & 0x004000 == 0 {
                                                    if insn & 0x010000 == 0 {
                                                        if insn & 0x20000000 == 0 {
                                                            if insn & 0xbf3ffc00 == 0xe209800 {
                                                                return Some(
                                                                    CMEQ_Vd_Vn_IMM0::make_opcode(
                                                                        insn,
                                                                    ),
                                                                );
                                                            }
                                                        } else {
                                                            if insn & 0xbf3ffc00 == 0x2e209800 {
                                                                return Some(
                                                                    CMLE_Vd_Vn_IMM0::make_opcode(
                                                                        insn,
                                                                    ),
                                                                );
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x080000 == 0 {
                                                            if insn & 0x800000 == 0 {
                                                                if insn & 0x20000000 == 0 {
                                                                    if insn & 0xbfbffc00
                                                                        == 0xe219800
                                                                    {
                                                                        return Some (FRINTM_Vd_Vn :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xbfbffc00
                                                                        == 0x2e219800
                                                                    {
                                                                        return Some (FRINTX_Vd_Vn :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0x20000000 == 0 {
                                                                    if insn & 0xbfbffc00
                                                                        == 0xea19800
                                                                    {
                                                                        return Some (FRINTZ_Vd_Vn :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xbfbffc00
                                                                        == 0x2ea19800
                                                                    {
                                                                        return Some (FRINTI_Vd_Vn :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x800000 == 0 {
                                                                if insn & 0x20000000 == 0 {
                                                                    if insn & 0xbffffc00
                                                                        == 0xe799800
                                                                    {
                                                                        return Some (FRINTM_Vd_V_4H_Vn_V_4H :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xbffffc00
                                                                        == 0x2e799800
                                                                    {
                                                                        return Some (FRINTX_Vd_V_4H_Vn_V_4H :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0x20000000 == 0 {
                                                                    if insn & 0xbffffc00
                                                                        == 0xef99800
                                                                    {
                                                                        return Some (FRINTZ_Vd_V_4H_Vn_V_4H :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xbffffc00
                                                                        == 0x2ef99800
                                                                    {
                                                                        return Some (FRINTI_Vd_V_4H_Vn_V_4H :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            }
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x010000 == 0 {
                                                        if insn & 0x080000 == 0 {
                                                            if insn & 0x20000000 == 0 {
                                                                if insn & 0xbfbffc00 == 0xea0d800 {
                                                                    return Some (FCMEQ_Vd_Vn_FPIMM0 :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xbfbffc00 == 0x2ea0d800 {
                                                                    return Some (FCMLE_Vd_Vn_FPIMM0 :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x20000000 == 0 {
                                                                if insn & 0xbffffc00 == 0xef8d800 {
                                                                    return Some (FCMEQ_Vd_V_4H_Vn_V_4H_FPIMM0 :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xbffffc00 == 0x2ef8d800 {
                                                                    return Some (FCMLE_Vd_V_4H_Vn_V_4H_FPIMM0 :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x080000 == 0 {
                                                            if insn & 0x800000 == 0 {
                                                                if insn & 0x20000000 == 0 {
                                                                    if insn & 0xbfbffc00
                                                                        == 0xe21d800
                                                                    {
                                                                        return Some (SCVTF_Vd_Vn :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xbfbffc00
                                                                        == 0x2e21d800
                                                                    {
                                                                        return Some (UCVTF_Vd_Vn :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0x20000000 == 0 {
                                                                    if insn & 0xbfbffc00
                                                                        == 0xea1d800
                                                                    {
                                                                        return Some (FRECPE_Vd_Vn :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xbfbffc00
                                                                        == 0x2ea1d800
                                                                    {
                                                                        return Some (FRSQRTE_Vd_Vn :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x800000 == 0 {
                                                                if insn & 0x20000000 == 0 {
                                                                    if insn & 0xbffffc00
                                                                        == 0xe79d800
                                                                    {
                                                                        return Some (SCVTF_Vd_V_4H_Vn_V_4H :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xbffffc00
                                                                        == 0x2e79d800
                                                                    {
                                                                        return Some (UCVTF_Vd_V_4H_Vn_V_4H :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0x20000000 == 0 {
                                                                    if insn & 0xbffffc00
                                                                        == 0xef9d800
                                                                    {
                                                                        return Some (FRECPE_Vd_V_4H_Vn_V_4H :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xbffffc00
                                                                        == 0x2ef9d800
                                                                    {
                                                                        return Some (FRSQRTE_Vd_V_4H_Vn_V_4H :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            }
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0x004000 == 0 {
                                                    if insn & 0x010000 == 0 {
                                                        if insn & 0x20000000 == 0 {
                                                            if insn & 0xbf3ffc00 == 0xe20b800 {
                                                                return Some(
                                                                    ABS_Vd_Vn::make_opcode(insn),
                                                                );
                                                            }
                                                        } else {
                                                            if insn & 0xbf3ffc00 == 0x2e20b800 {
                                                                return Some(
                                                                    NEG_Vd_Vn::make_opcode(insn),
                                                                );
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x080000 == 0 {
                                                            if insn & 0x100000 == 0 {
                                                                if insn & 0x800000 == 0 {
                                                                    if insn & 0x20000000 == 0 {
                                                                        if insn & 0xbfbffc00
                                                                            == 0xe21b800
                                                                        {
                                                                            return Some (FCVTMS_Vd_Vn :: make_opcode (insn)) ;
                                                                        }
                                                                    } else {
                                                                        if insn & 0xbfbffc00
                                                                            == 0x2e21b800
                                                                        {
                                                                            return Some (FCVTMU_Vd_Vn :: make_opcode (insn)) ;
                                                                        }
                                                                    }
                                                                } else {
                                                                    if insn & 0x20000000 == 0 {
                                                                        if insn & 0xbfbffc00
                                                                            == 0xea1b800
                                                                        {
                                                                            return Some (FCVTZS_Vd_Vn :: make_opcode (insn)) ;
                                                                        }
                                                                    } else {
                                                                        if insn & 0xbfbffc00
                                                                            == 0x2ea1b800
                                                                        {
                                                                            return Some (FCVTZU_Vd_Vn :: make_opcode (insn)) ;
                                                                        }
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0xbf3ffc00 == 0xe31b800 {
                                                                    return Some(
                                                                        ADDV_Fd_Vn::make_opcode(
                                                                            insn,
                                                                        ),
                                                                    );
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x800000 == 0 {
                                                                if insn & 0x20000000 == 0 {
                                                                    if insn & 0xbffffc00
                                                                        == 0xe79b800
                                                                    {
                                                                        return Some (FCVTMS_Vd_V_4H_Vn_V_4H :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xbffffc00
                                                                        == 0x2e79b800
                                                                    {
                                                                        return Some (FCVTMU_Vd_V_4H_Vn_V_4H :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0x20000000 == 0 {
                                                                    if insn & 0xbffffc00
                                                                        == 0xef9b800
                                                                    {
                                                                        return Some (FCVTZS_Vd_V_4H_Vn_V_4H :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xbffffc00
                                                                        == 0x2ef9b800
                                                                    {
                                                                        return Some (FCVTZU_Vd_V_4H_Vn_V_4H :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            }
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x010000 == 0 {
                                                        if insn & 0x080000 == 0 {
                                                            if insn & 0x100000 == 0 {
                                                                if insn & 0x20000000 == 0 {
                                                                    if insn & 0xbfbffc00
                                                                        == 0xea0f800
                                                                    {
                                                                        return Some(
                                                                            FABS_Vd_Vn::make_opcode(
                                                                                insn,
                                                                            ),
                                                                        );
                                                                    }
                                                                } else {
                                                                    if insn & 0xbfbffc00
                                                                        == 0x2ea0f800
                                                                    {
                                                                        return Some(
                                                                            FNEG_Vd_Vn::make_opcode(
                                                                                insn,
                                                                            ),
                                                                        );
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0x800000 == 0 {
                                                                    if insn & 0x20000000 == 0 {
                                                                        if insn & 0xbffffc00
                                                                            == 0xe30f800
                                                                        {
                                                                            return Some (FMAXV_Fd_Vn :: make_opcode (insn)) ;
                                                                        }
                                                                    } else {
                                                                        if insn & 0xbfbffc00
                                                                            == 0x2e30f800
                                                                        {
                                                                            return Some (FMAXV_Fd_S_S_Vn_V_4S :: make_opcode (insn)) ;
                                                                        }
                                                                    }
                                                                } else {
                                                                    if insn & 0x20000000 == 0 {
                                                                        if insn & 0xbffffc00
                                                                            == 0xeb0f800
                                                                        {
                                                                            return Some (FMINV_Fd_Vn :: make_opcode (insn)) ;
                                                                        }
                                                                    } else {
                                                                        if insn & 0xbfbffc00
                                                                            == 0x2eb0f800
                                                                        {
                                                                            return Some (FMINV_Fd_S_S_Vn_V_4S :: make_opcode (insn)) ;
                                                                        }
                                                                    }
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x20000000 == 0 {
                                                                if insn & 0xbffffc00 == 0xef8f800 {
                                                                    return Some (FABS_Vd_V_4H_Vn_V_4H :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xbffffc00 == 0x2ef8f800 {
                                                                    return Some (FNEG_Vd_V_4H_Vn_V_4H :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x080000 == 0 {
                                                            if insn & 0x800000 == 0 {
                                                                if insn & 0x20000000 == 0 {
                                                                    if insn & 0xbfbffc00
                                                                        == 0xe21f800
                                                                    {
                                                                        return Some (FRINT64Z_Vd_Vn :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xbfbffc00
                                                                        == 0x2e21f800
                                                                    {
                                                                        return Some (FRINT64X_Vd_Vn :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0xbfbffc00 == 0x2ea1f800 {
                                                                    return Some(
                                                                        FSQRT_Vd_Vn::make_opcode(
                                                                            insn,
                                                                        ),
                                                                    );
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0xbffffc00 == 0x2ef9f800 {
                                                                return Some (FSQRT_Vd_V_4H_Vn_V_4H :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    }
                                                }
                                            }
                                        }
                                    }
                                } else {
                                    if insn & 0x000800 == 0 {
                                        if insn & 0x001000 == 0 {
                                            if insn & 0x002000 == 0 {
                                                if insn & 0x004000 == 0 {
                                                    if insn & 0x20000000 == 0 {
                                                        if insn & 0x80000000 == 0 {
                                                            if insn & 0xbf20fc00 == 0xe208400 {
                                                                return Some(
                                                                    ADD_Vd_Vn_Vm::make_opcode(insn),
                                                                );
                                                            }
                                                        } else {
                                                            if insn & 0xffe0fc00 == 0xce608400 {
                                                                return Some(
                                                                    SHA512H2_Fd_Fn_Vm::make_opcode(
                                                                        insn,
                                                                    ),
                                                                );
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0xbf20fc00 == 0x2e208400 {
                                                            return Some(
                                                                SUB_Vd_Vn_Vm::make_opcode(insn),
                                                            );
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x800000 == 0 {
                                                        if insn & 0x20000000 == 0 {
                                                            if insn & 0x80000000 == 0 {
                                                                if insn & 0xbfa0fc00 == 0xe20c400 {
                                                                    return Some (FMAXNM_Vd_V_2S_Vn_V_2S_Vm_V_2S :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xffe0fc00 == 0xce60c400 {
                                                                    return Some (SM3PARTW2_Vd_Vn_Vm :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0xbfa0fc00 == 0x2e20c400 {
                                                                return Some (FMAXNMP_Vd_V_2S_Vn_V_2S_Vm_V_2S :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x20000000 == 0 {
                                                            if insn & 0xbfa0fc00 == 0xea0c400 {
                                                                return Some (FMINNM_Vd_V_2S_Vn_V_2S_Vm_V_2S :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xbfa0fc00 == 0x2ea0c400 {
                                                                return Some (FMINNMP_Vd_V_2S_Vn_V_2S_Vm_V_2S :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0x004000 == 0 {
                                                    if insn & 0x20000000 == 0 {
                                                        if insn & 0xbf20fc00 == 0xe20a400 {
                                                            return Some(
                                                                SMAXP_Vd_Vn_Vm::make_opcode(insn),
                                                            );
                                                        }
                                                    } else {
                                                        if insn & 0xbf20fc00 == 0x2e20a400 {
                                                            return Some(
                                                                UMAXP_Vd_Vn_Vm::make_opcode(insn),
                                                            );
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x800000 == 0 {
                                                        if insn & 0x20000000 == 0 {
                                                            if insn & 0xbfa0fc00 == 0xe20e400 {
                                                                return Some (FCMEQ_Vd_V_2S_Vn_V_2S_Vm_V_2S :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xbfa0fc00 == 0x2e20e400 {
                                                                return Some (FCMGE_Vd_V_2S_Vn_V_2S_Vm_V_2S :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0xbfa0fc00 == 0x2ea0e400 {
                                                            return Some (FCMGT_Vd_V_2S_Vn_V_2S_Vm_V_2S :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                }
                                            }
                                        } else {
                                            if insn & 0x002000 == 0 {
                                                if insn & 0x004000 == 0 {
                                                    if insn & 0x20000000 == 0 {
                                                        if insn & 0xbf20fc00 == 0xe209400 {
                                                            return Some(
                                                                MLA_Vd_Vn_Vm::make_opcode(insn),
                                                            );
                                                        }
                                                    } else {
                                                        if insn & 0xbf20fc00 == 0x2e209400 {
                                                            return Some(
                                                                MLS_Vd_Vn_Vm::make_opcode(insn),
                                                            );
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x800000 == 0 {
                                                        if insn & 0x20000000 == 0 {
                                                            if insn & 0xbfa0fc00 == 0xe20d400 {
                                                                return Some (FADD_Vd_V_2S_Vn_V_2S_Vm_V_2S :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xbfa0fc00 == 0x2e20d400 {
                                                                return Some (FADDP_Vd_V_2S_Vn_V_2S_Vm_V_2S :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x20000000 == 0 {
                                                            if insn & 0xbfa0fc00 == 0xea0d400 {
                                                                return Some (FSUB_Vd_V_2S_Vn_V_2S_Vm_V_2S :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xbfa0fc00 == 0x2ea0d400 {
                                                                return Some (FABD_Vd_V_2S_Vn_V_2S_Vm_V_2S :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0x004000 == 0 {
                                                    if insn & 0x20000000 == 0 {
                                                        if insn & 0xbf20fc00 == 0xe20b400 {
                                                            return Some(
                                                                SQDMULH_Vd_Vn_Vm::make_opcode(insn),
                                                            );
                                                        }
                                                    } else {
                                                        if insn & 0xbf20fc00 == 0x2e20b400 {
                                                            return Some(
                                                                SQRDMULH_Vd_Vn_Vm::make_opcode(
                                                                    insn,
                                                                ),
                                                            );
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x800000 == 0 {
                                                        if insn & 0x20000000 == 0 {
                                                            if insn & 0xbfa0fc00 == 0xe20f400 {
                                                                return Some (FMAX_Vd_V_2S_Vn_V_2S_Vm_V_2S :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xbfa0fc00 == 0x2e20f400 {
                                                                return Some (FMAXP_Vd_V_2S_Vn_V_2S_Vm_V_2S :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x20000000 == 0 {
                                                            if insn & 0xbfa0fc00 == 0xea0f400 {
                                                                return Some (FMIN_Vd_V_2S_Vn_V_2S_Vm_V_2S :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xbfa0fc00 == 0x2ea0f400 {
                                                                return Some (FMINP_Vd_V_2S_Vn_V_2S_Vm_V_2S :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    }
                                                }
                                            }
                                        }
                                    } else {
                                        if insn & 0x001000 == 0 {
                                            if insn & 0x002000 == 0 {
                                                if insn & 0x004000 == 0 {
                                                    if insn & 0x20000000 == 0 {
                                                        if insn & 0x80000000 == 0 {
                                                            if insn & 0xbf20fc00 == 0xe208c00 {
                                                                return Some(
                                                                    CMTST_Vd_Vn_Vm::make_opcode(
                                                                        insn,
                                                                    ),
                                                                );
                                                            }
                                                        } else {
                                                            if insn & 0xffe0fc00 == 0xce608c00 {
                                                                return Some(
                                                                    RAX1_Vd_Vn_Vm::make_opcode(
                                                                        insn,
                                                                    ),
                                                                );
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0xbf20fc00 == 0x2e208c00 {
                                                            return Some(
                                                                CMEQ_Vd_Vn_Vm::make_opcode(insn),
                                                            );
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x800000 == 0 {
                                                        if insn & 0x20000000 == 0 {
                                                            if insn & 0xbfa0fc00 == 0xe20cc00 {
                                                                return Some (FMLA_Vd_V_2S_Vn_V_2S_Vm_V_2S :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0x40000000 == 0 {
                                                                if insn & 0xffa0fc00 == 0x2e20cc00 {
                                                                    return Some (FMLAL2_Vd_Vn_Vm :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xffa0fc00 == 0x6e20cc00 {
                                                                    return Some (FMLAL2_Vd_V_4S_Vn_V_4H_Vm_V_4H :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x20000000 == 0 {
                                                            if insn & 0xbfa0fc00 == 0xea0cc00 {
                                                                return Some (FMLS_Vd_V_2S_Vn_V_2S_Vm_V_2S :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0x40000000 == 0 {
                                                                if insn & 0xffa0fc00 == 0x2ea0cc00 {
                                                                    return Some (FMLSL2_Vd_Vn_Vm :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xffa0fc00 == 0x6ea0cc00 {
                                                                    return Some (FMLSL2_Vd_V_4S_Vn_V_4H_Vm_V_4H :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0x004000 == 0 {
                                                    if insn & 0x20000000 == 0 {
                                                        if insn & 0xbf20fc00 == 0xe20ac00 {
                                                            return Some(
                                                                SMINP_Vd_Vn_Vm::make_opcode(insn),
                                                            );
                                                        }
                                                    } else {
                                                        if insn & 0xbf20fc00 == 0x2e20ac00 {
                                                            return Some(
                                                                UMINP_Vd_Vn_Vm::make_opcode(insn),
                                                            );
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x800000 == 0 {
                                                        if insn & 0x20000000 == 0 {
                                                            if insn & 0x40000000 == 0 {
                                                                if insn & 0xffa0fc00 == 0xe20ec00 {
                                                                    return Some(
                                                                        FMLAL_Vd_Vn_Vm::make_opcode(
                                                                            insn,
                                                                        ),
                                                                    );
                                                                }
                                                            } else {
                                                                if insn & 0xffa0fc00 == 0x4e20ec00 {
                                                                    return Some (FMLAL_Vd_V_4S_Vn_V_4H_Vm_V_4H :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0xbfa0fc00 == 0x2e20ec00 {
                                                                return Some (FACGE_Vd_V_2S_Vn_V_2S_Vm_V_2S :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x20000000 == 0 {
                                                            if insn & 0x40000000 == 0 {
                                                                if insn & 0xffa0fc00 == 0xea0ec00 {
                                                                    return Some(
                                                                        FMLSL_Vd_Vn_Vm::make_opcode(
                                                                            insn,
                                                                        ),
                                                                    );
                                                                }
                                                            } else {
                                                                if insn & 0xffa0fc00 == 0x4ea0ec00 {
                                                                    return Some (FMLSL_Vd_V_4S_Vn_V_4H_Vm_V_4H :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0xbfa0fc00 == 0x2ea0ec00 {
                                                                return Some (FACGT_Vd_V_2S_Vn_V_2S_Vm_V_2S :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    }
                                                }
                                            }
                                        } else {
                                            if insn & 0x002000 == 0 {
                                                if insn & 0x004000 == 0 {
                                                    if insn & 0x20000000 == 0 {
                                                        if insn & 0xbf20fc00 == 0xe209c00 {
                                                            return Some(
                                                                MUL_Vd_Vn_Vm::make_opcode(insn),
                                                            );
                                                        }
                                                    } else {
                                                        if insn & 0xbf20fc00 == 0x2e209c00 {
                                                            return Some(
                                                                PMUL_Vd_Vn_Vm::make_opcode(insn),
                                                            );
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x20000000 == 0 {
                                                        if insn & 0xbfa0fc00 == 0xe20dc00 {
                                                            return Some (FMULX_Vd_V_2S_Vn_V_2S_Vm_V_2S :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xbfa0fc00 == 0x2e20dc00 {
                                                            return Some (FMUL_Vd_V_2S_Vn_V_2S_Vm_V_2S :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0x004000 == 0 {
                                                    if insn & 0xbf20fc00 == 0xe20bc00 {
                                                        return Some(ADDP_Vd_Vn_Vm::make_opcode(
                                                            insn,
                                                        ));
                                                    }
                                                } else {
                                                    if insn & 0x800000 == 0 {
                                                        if insn & 0x20000000 == 0 {
                                                            if insn & 0xbfa0fc00 == 0xe20fc00 {
                                                                return Some (FRECPS_Vd_V_2S_Vn_V_2S_Vm_V_2S :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xbfa0fc00 == 0x2e20fc00 {
                                                                return Some (FDIV_Vd_V_2S_Vn_V_2S_Vm_V_2S :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0xbfa0fc00 == 0xea0fc00 {
                                                            return Some (FRSQRTS_Vd_V_2S_Vn_V_2S_Vm_V_2S :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                }
                                            }
                                        }
                                    }
                                }
                            }
                        } else {
                            if insn & 0x000400 == 0 {
                                if insn & 0x000800 == 0 {
                                    if insn & 0x001000 == 0 {
                                        if insn & 0x002000 == 0 {
                                            if insn & 0x004000 == 0 {
                                                if insn & 0x010000 == 0 {
                                                    if insn & 0x020000 == 0 {
                                                        if insn & 0x040000 == 0 {
                                                            if insn & 0x080000 == 0 {
                                                                if insn & 0x100000 == 0 {
                                                                    if insn & 0x7ffffc00
                                                                        == 0x1ee00000
                                                                    {
                                                                        return Some (FCVTNS_Rd_Fn :: make_opcode (insn)) ;
                                                                    }
                                                                    if insn & 0x7f3ffc00
                                                                        == 0x1e200000
                                                                    {
                                                                        return Some (FCVTNS_Rd_W_Fn_S_D :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0x7ffffc00
                                                                        == 0x1ef00000
                                                                    {
                                                                        return Some (FCVTMS_Rd_Fn :: make_opcode (insn)) ;
                                                                    }
                                                                    if insn & 0x7f3ffc00
                                                                        == 0x1e300000
                                                                    {
                                                                        return Some (FCVTMS_Rd_W_Fn_S_D :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0x100000 == 0 {
                                                                    if insn & 0x7ffffc00
                                                                        == 0x1ee80000
                                                                    {
                                                                        return Some (FCVTPS_Rd_Fn :: make_opcode (insn)) ;
                                                                    }
                                                                    if insn & 0x7f3ffc00
                                                                        == 0x1e280000
                                                                    {
                                                                        return Some (FCVTPS_Rd_W_Fn_S_D :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0x7ffffc00
                                                                        == 0x1ef80000
                                                                    {
                                                                        return Some (FCVTZS_Rd_Fn :: make_opcode (insn)) ;
                                                                    }
                                                                    if insn & 0x7f3ffc00
                                                                        == 0x1e380000
                                                                    {
                                                                        return Some (FCVTZS_Rd_W_Fn_S_D :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x7ffffc00 == 0x1ee40000 {
                                                                return Some(
                                                                    FCVTAS_Rd_Fn::make_opcode(insn),
                                                                );
                                                            }
                                                            if insn & 0x7f3ffc00 == 0x1e240000 {
                                                                return Some(
                                                                    FCVTAS_Rd_W_Fn_S_D::make_opcode(
                                                                        insn,
                                                                    ),
                                                                );
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x040000 == 0 {
                                                            if insn & 0x7ffffc00 == 0x1ee20000 {
                                                                return Some(
                                                                    SCVTF_Fd_Rn::make_opcode(insn),
                                                                );
                                                            }
                                                            if insn & 0x7f3ffc00 == 0x1e220000 {
                                                                return Some(
                                                                    SCVTF_Fd_S_D_Rn_W::make_opcode(
                                                                        insn,
                                                                    ),
                                                                );
                                                            }
                                                        } else {
                                                            if insn & 0x080000 == 0 {
                                                                if insn & 0x7ffffc00 == 0x1ee60000 {
                                                                    return Some(
                                                                        FMOV_Rd_Fn::make_opcode(
                                                                            insn,
                                                                        ),
                                                                    );
                                                                }
                                                                if insn & 0x7f3ffc00 == 0x1e260000 {
                                                                    return Some (FMOV_Rd_W_Fn_S_S :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0x100000 == 0 {
                                                                    if insn & 0xfffffc00
                                                                        == 0x9eae0000
                                                                    {
                                                                        return Some (FMOV_Rd_VnD1 :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xfffffc00
                                                                        == 0x1e7e0000
                                                                    {
                                                                        return Some (FJCVTZS_Rd_Fn :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            }
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x020000 == 0 {
                                                        if insn & 0x040000 == 0 {
                                                            if insn & 0x080000 == 0 {
                                                                if insn & 0x100000 == 0 {
                                                                    if insn & 0x7ffffc00
                                                                        == 0x1ee10000
                                                                    {
                                                                        return Some (FCVTNU_Rd_Fn :: make_opcode (insn)) ;
                                                                    }
                                                                    if insn & 0x7f3ffc00
                                                                        == 0x1e210000
                                                                    {
                                                                        return Some (FCVTNU_Rd_W_Fn_S_D :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0x7ffffc00
                                                                        == 0x1ef10000
                                                                    {
                                                                        return Some (FCVTMU_Rd_Fn :: make_opcode (insn)) ;
                                                                    }
                                                                    if insn & 0x7f3ffc00
                                                                        == 0x1e310000
                                                                    {
                                                                        return Some (FCVTMU_Rd_W_Fn_S_D :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0x100000 == 0 {
                                                                    if insn & 0x7ffffc00
                                                                        == 0x1ee90000
                                                                    {
                                                                        return Some (FCVTPU_Rd_Fn :: make_opcode (insn)) ;
                                                                    }
                                                                    if insn & 0x7f3ffc00
                                                                        == 0x1e290000
                                                                    {
                                                                        return Some (FCVTPU_Rd_W_Fn_S_D :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0x7ffffc00
                                                                        == 0x1ef90000
                                                                    {
                                                                        return Some (FCVTZU_Rd_Fn :: make_opcode (insn)) ;
                                                                    }
                                                                    if insn & 0x7f3ffc00
                                                                        == 0x1e390000
                                                                    {
                                                                        return Some (FCVTZU_Rd_W_Fn_S_D :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x7ffffc00 == 0x1ee50000 {
                                                                return Some(
                                                                    FCVTAU_Rd_Fn::make_opcode(insn),
                                                                );
                                                            }
                                                            if insn & 0x7f3ffc00 == 0x1e250000 {
                                                                return Some(
                                                                    FCVTAU_Rd_W_Fn_S_D::make_opcode(
                                                                        insn,
                                                                    ),
                                                                );
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x040000 == 0 {
                                                            if insn & 0x7ffffc00 == 0x1ee30000 {
                                                                return Some(
                                                                    UCVTF_Fd_Rn::make_opcode(insn),
                                                                );
                                                            }
                                                            if insn & 0x7f3ffc00 == 0x1e230000 {
                                                                return Some(
                                                                    UCVTF_Fd_S_D_Rn_W::make_opcode(
                                                                        insn,
                                                                    ),
                                                                );
                                                            }
                                                        } else {
                                                            if insn & 0x080000 == 0 {
                                                                if insn & 0x7ffffc00 == 0x1ee70000 {
                                                                    return Some(
                                                                        FMOV_Fd_Rn::make_opcode(
                                                                            insn,
                                                                        ),
                                                                    );
                                                                }
                                                                if insn & 0x7f3ffc00 == 0x1e270000 {
                                                                    return Some (FMOV_Fd_S_S_Rn_W :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xfffffc00 == 0x9eaf0000 {
                                                                    return Some(
                                                                        FMOV_VdD1_Rn::make_opcode(
                                                                            insn,
                                                                        ),
                                                                    );
                                                                }
                                                            }
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0x020000 == 0 {
                                                    if insn & 0x008000 == 0 {
                                                        if insn & 0x010000 == 0 {
                                                            if insn & 0x040000 == 0 {
                                                                if insn & 0x080000 == 0 {
                                                                    if insn & 0xfffffc00
                                                                        == 0x1ee04000
                                                                    {
                                                                        return Some(
                                                                            FMOV_Fd_Fn::make_opcode(
                                                                                insn,
                                                                            ),
                                                                        );
                                                                    }
                                                                    if insn & 0xff3ffc00
                                                                        == 0x1e204000
                                                                    {
                                                                        return Some (FMOV_Fd_S_S_Fn_S_S :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xffbffc00
                                                                        == 0x1e284000
                                                                    {
                                                                        return Some (FRINT32Z_Fd_Fn :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0xfffffc00 == 0x1ee44000 {
                                                                    return Some(
                                                                        FRINTN_Fd_Fn::make_opcode(
                                                                            insn,
                                                                        ),
                                                                    );
                                                                }
                                                                if insn & 0xff3ffc00 == 0x1e244000 {
                                                                    return Some (FRINTN_Fd_S_S_Fn_S_S :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x040000 == 0 {
                                                                if insn & 0x080000 == 0 {
                                                                    if insn & 0xfffffc00
                                                                        == 0x1ee14000
                                                                    {
                                                                        return Some(
                                                                            FNEG_Fd_Fn::make_opcode(
                                                                                insn,
                                                                            ),
                                                                        );
                                                                    }
                                                                    if insn & 0xff3ffc00
                                                                        == 0x1e214000
                                                                    {
                                                                        return Some (FNEG_Fd_S_S_Fn_S_S :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xffbffc00
                                                                        == 0x1e294000
                                                                    {
                                                                        return Some (FRINT64Z_Fd_Fn :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0xfffffc00 == 0x1ee54000 {
                                                                    return Some(
                                                                        FRINTM_Fd_Fn::make_opcode(
                                                                            insn,
                                                                        ),
                                                                    );
                                                                }
                                                                if insn & 0xff3ffc00 == 0x1e254000 {
                                                                    return Some (FRINTM_Fd_S_S_Fn_S_S :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x010000 == 0 {
                                                            if insn & 0x040000 == 0 {
                                                                if insn & 0x080000 == 0 {
                                                                    if insn & 0xfffffc00
                                                                        == 0x1ee0c000
                                                                    {
                                                                        return Some(
                                                                            FABS_Fd_Fn::make_opcode(
                                                                                insn,
                                                                            ),
                                                                        );
                                                                    }
                                                                    if insn & 0xff3ffc00
                                                                        == 0x1e20c000
                                                                    {
                                                                        return Some (FABS_Fd_S_S_Fn_S_S :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xffbffc00
                                                                        == 0x1e28c000
                                                                    {
                                                                        return Some (FRINT32X_Fd_Fn :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0xfffffc00 == 0x1ee4c000 {
                                                                    return Some(
                                                                        FRINTP_Fd_Fn::make_opcode(
                                                                            insn,
                                                                        ),
                                                                    );
                                                                }
                                                                if insn & 0xff3ffc00 == 0x1e24c000 {
                                                                    return Some (FRINTP_Fd_S_S_Fn_S_S :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x040000 == 0 {
                                                                if insn & 0x080000 == 0 {
                                                                    if insn & 0xfffffc00
                                                                        == 0x1ee1c000
                                                                    {
                                                                        return Some (FSQRT_Fd_Fn :: make_opcode (insn)) ;
                                                                    }
                                                                    if insn & 0xff3ffc00
                                                                        == 0x1e21c000
                                                                    {
                                                                        return Some (FSQRT_Fd_S_S_Fn_S_S :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xffbffc00
                                                                        == 0x1e29c000
                                                                    {
                                                                        return Some (FRINT64X_Fd_Fn :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0xfffffc00 == 0x1ee5c000 {
                                                                    return Some(
                                                                        FRINTZ_Fd_Fn::make_opcode(
                                                                            insn,
                                                                        ),
                                                                    );
                                                                }
                                                                if insn & 0xff3ffc00 == 0x1e25c000 {
                                                                    return Some (FRINTZ_Fd_S_S_Fn_S_S :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x040000 == 0 {
                                                        if insn & 0xfffffc00 == 0x1e634000 {
                                                            return Some(BFCVT_Fd_Fn::make_opcode(
                                                                insn,
                                                            ));
                                                        }
                                                        if insn & 0xff3e7c00 == 0x1e224000 {
                                                            return Some(FCVT_Fd_Fn::make_opcode(
                                                                insn,
                                                            ));
                                                        }
                                                    } else {
                                                        if insn & 0x008000 == 0 {
                                                            if insn & 0x010000 == 0 {
                                                                if insn & 0xfffffc00 == 0x1ee64000 {
                                                                    return Some(
                                                                        FRINTA_Fd_Fn::make_opcode(
                                                                            insn,
                                                                        ),
                                                                    );
                                                                }
                                                                if insn & 0xff3ffc00 == 0x1e264000 {
                                                                    return Some (FRINTA_Fd_S_S_Fn_S_S :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xfffffc00 == 0x1ee74000 {
                                                                    return Some(
                                                                        FRINTX_Fd_Fn::make_opcode(
                                                                            insn,
                                                                        ),
                                                                    );
                                                                }
                                                                if insn & 0xff3ffc00 == 0x1e274000 {
                                                                    return Some (FRINTX_Fd_S_S_Fn_S_S :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0xfffffc00 == 0x1ee7c000 {
                                                                return Some(
                                                                    FRINTI_Fd_Fn::make_opcode(insn),
                                                                );
                                                            }
                                                            if insn & 0xff3ffc00 == 0x1e27c000 {
                                                                return Some (FRINTI_Fd_S_S_Fn_S_S :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    }
                                                }
                                            }
                                        } else {
                                            if insn & 0x000008 == 0 {
                                                if insn & 0x000010 == 0 {
                                                    if insn & 0xffe0fc1f == 0x1ee02000 {
                                                        return Some(FCMP_Fn_Fm::make_opcode(insn));
                                                    }
                                                    if insn & 0xff20fc1f == 0x1e202000 {
                                                        return Some(
                                                            FCMP_Fn_S_S_Fm_S_S::make_opcode(insn),
                                                        );
                                                    }
                                                } else {
                                                    if insn & 0xffe0fc1f == 0x1ee02010 {
                                                        return Some(FCMPE_Fn_Fm::make_opcode(
                                                            insn,
                                                        ));
                                                    }
                                                    if insn & 0xff20fc1f == 0x1e202010 {
                                                        return Some(
                                                            FCMPE_Fn_S_S_Fm_S_S::make_opcode(insn),
                                                        );
                                                    }
                                                }
                                            } else {
                                                if insn & 0x000010 == 0 {
                                                    if insn & 0xffe0fc1f == 0x1ee02008 {
                                                        return Some(FCMP_Fn_FPIMM0::make_opcode(
                                                            insn,
                                                        ));
                                                    }
                                                    if insn & 0xff20fc1f == 0x1e202008 {
                                                        return Some(
                                                            FCMP_Fn_S_S_FPIMM0::make_opcode(insn),
                                                        );
                                                    }
                                                } else {
                                                    if insn & 0xffe0fc1f == 0x1ee02018 {
                                                        return Some(FCMPE_Fn_FPIMM0::make_opcode(
                                                            insn,
                                                        ));
                                                    }
                                                    if insn & 0xff20fc1f == 0x1e202018 {
                                                        return Some(
                                                            FCMPE_Fn_S_S_FPIMM0::make_opcode(insn),
                                                        );
                                                    }
                                                }
                                            }
                                        }
                                    } else {
                                        if insn & 0x40000000 == 0 {
                                            if insn & 0xffe01fe0 == 0x1ee01000 {
                                                return Some(FMOV_Fd_FPIMM::make_opcode(insn));
                                            }
                                            if insn & 0xff201fe0 == 0x1e201000 {
                                                return Some(FMOV_Fd_S_S_FPIMM::make_opcode(insn));
                                            }
                                        } else {
                                            if insn & 0x002000 == 0 {
                                                if insn & 0x004000 == 0 {
                                                    if insn & 0xff20fc00 == 0x5e209000 {
                                                        return Some(
                                                            SQDMLAL_Sd_Sn_Sm::make_opcode(insn),
                                                        );
                                                    }
                                                } else {
                                                    if insn & 0xff20fc00 == 0x5e20d000 {
                                                        return Some(
                                                            SQDMULL_Sd_Sn_Sm::make_opcode(insn),
                                                        );
                                                    }
                                                }
                                            } else {
                                                if insn & 0xff20fc00 == 0x5e20b000 {
                                                    return Some(SQDMLSL_Sd_Sn_Sm::make_opcode(
                                                        insn,
                                                    ));
                                                }
                                            }
                                        }
                                    }
                                } else {
                                    if insn & 0x001000 == 0 {
                                        if insn & 0x002000 == 0 {
                                            if insn & 0x004000 == 0 {
                                                if insn & 0x008000 == 0 {
                                                    if insn & 0x40000000 == 0 {
                                                        if insn & 0xffe0fc00 == 0x1ee00800 {
                                                            return Some(
                                                                FMUL_Fd_Fn_Fm::make_opcode(insn),
                                                            );
                                                        }
                                                        if insn & 0xff20fc00 == 0x1e200800 {
                                                            return Some (FMUL_Fd_S_S_Fn_S_S_Fm_S_S :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xfffffc00 == 0x5e280800 {
                                                            return Some(SHA1H_Fd_Fn::make_opcode(
                                                                insn,
                                                            ));
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x20000000 == 0 {
                                                        if insn & 0x40000000 == 0 {
                                                            if insn & 0xffe0fc00 == 0x1ee08800 {
                                                                return Some(
                                                                    FNMUL_Fd_Fn_Fm::make_opcode(
                                                                        insn,
                                                                    ),
                                                                );
                                                            }
                                                            if insn & 0xff20fc00 == 0x1e208800 {
                                                                return Some (FNMUL_Fd_S_S_Fn_S_S_Fm_S_S :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xff3ffc00 == 0x5e208800 {
                                                                return Some(
                                                                    CMGT_Sd_Sn_IMM0::make_opcode(
                                                                        insn,
                                                                    ),
                                                                );
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0xff3ffc00 == 0x7e208800 {
                                                            return Some(
                                                                CMGE_Sd_Sn_IMM0::make_opcode(insn),
                                                            );
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0x008000 == 0 {
                                                    if insn & 0x20000000 == 0 {
                                                        if insn & 0x40000000 == 0 {
                                                            if insn & 0xffe0fc00 == 0x1ee04800 {
                                                                return Some(
                                                                    FMAX_Fd_Fn_Fm::make_opcode(
                                                                        insn,
                                                                    ),
                                                                );
                                                            }
                                                            if insn & 0xff20fc00 == 0x1e204800 {
                                                                return Some (FMAX_Fd_S_S_Fn_S_S_Fm_S_S :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xff3ffc00 == 0x5e214800 {
                                                                return Some(
                                                                    SQXTN_Sd_Sn::make_opcode(insn),
                                                                );
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0xff3ffc00 == 0x7e214800 {
                                                            return Some(UQXTN_Sd_Sn::make_opcode(
                                                                insn,
                                                            ));
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x010000 == 0 {
                                                        if insn & 0x080000 == 0 {
                                                            if insn & 0x100000 == 0 {
                                                                if insn & 0x20000000 == 0 {
                                                                    if insn & 0xffbffc00
                                                                        == 0x5ea0c800
                                                                    {
                                                                        return Some (FCMGT_Sd_Sn_FPIMM0 :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xffbffc00
                                                                        == 0x7ea0c800
                                                                    {
                                                                        return Some (FCMGE_Sd_Sn_FPIMM0 :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0x800000 == 0 {
                                                                    if insn & 0x20000000 == 0 {
                                                                        if insn & 0xfffffc00
                                                                            == 0x5e30c800
                                                                        {
                                                                            return Some (FMAXNMP_Sd_Vn :: make_opcode (insn)) ;
                                                                        }
                                                                    } else {
                                                                        if insn & 0xffbffc00
                                                                            == 0x7e30c800
                                                                        {
                                                                            return Some (FMAXNMP_Sd_S_S_Vn_V_2S :: make_opcode (insn)) ;
                                                                        }
                                                                    }
                                                                } else {
                                                                    if insn & 0x20000000 == 0 {
                                                                        if insn & 0xfffffc00
                                                                            == 0x5eb0c800
                                                                        {
                                                                            return Some (FMINNMP_Sd_Vn :: make_opcode (insn)) ;
                                                                        }
                                                                    } else {
                                                                        if insn & 0xffbffc00
                                                                            == 0x7eb0c800
                                                                        {
                                                                            return Some (FMINNMP_Sd_S_S_Vn_V_2S :: make_opcode (insn)) ;
                                                                        }
                                                                    }
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x20000000 == 0 {
                                                                if insn & 0xfffffc00 == 0x5ef8c800 {
                                                                    return Some (FCMGT_Sd_S_H_Sn_S_H_FPIMM0 :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xfffffc00 == 0x7ef8c800 {
                                                                    return Some (FCMGE_Sd_S_H_Sn_S_H_FPIMM0 :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x080000 == 0 {
                                                            if insn & 0x20000000 == 0 {
                                                                if insn & 0xffbffc00 == 0x5e21c800 {
                                                                    return Some(
                                                                        FCVTAS_Sd_Sn::make_opcode(
                                                                            insn,
                                                                        ),
                                                                    );
                                                                }
                                                            } else {
                                                                if insn & 0xffbffc00 == 0x7e21c800 {
                                                                    return Some(
                                                                        FCVTAU_Sd_Sn::make_opcode(
                                                                            insn,
                                                                        ),
                                                                    );
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x20000000 == 0 {
                                                                if insn & 0xfffffc00 == 0x5e79c800 {
                                                                    return Some (FCVTAS_Sd_S_H_Sn_S_H :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xfffffc00 == 0x7e79c800 {
                                                                    return Some (FCVTAU_Sd_S_H_Sn_S_H :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        }
                                                    }
                                                }
                                            }
                                        } else {
                                            if insn & 0x004000 == 0 {
                                                if insn & 0x008000 == 0 {
                                                    if insn & 0x20000000 == 0 {
                                                        if insn & 0x40000000 == 0 {
                                                            if insn & 0xffe0fc00 == 0x1ee02800 {
                                                                return Some(
                                                                    FADD_Fd_Fn_Fm::make_opcode(
                                                                        insn,
                                                                    ),
                                                                );
                                                            }
                                                            if insn & 0xff20fc00 == 0x1e202800 {
                                                                return Some (FADD_Fd_S_S_Fn_S_S_Fm_S_S :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xfffffc00 == 0x5e282800 {
                                                                return Some(
                                                                    SHA256SU0_Vd_Vn::make_opcode(
                                                                        insn,
                                                                    ),
                                                                );
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0xff3ffc00 == 0x7e212800 {
                                                            return Some(
                                                                SQXTUN_Sd_Sn::make_opcode(insn),
                                                            );
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x010000 == 0 {
                                                        if insn & 0xff3ffc00 == 0x5e20a800 {
                                                            return Some(
                                                                CMLT_Sd_Sn_IMM0::make_opcode(insn),
                                                            );
                                                        }
                                                    } else {
                                                        if insn & 0x080000 == 0 {
                                                            if insn & 0x800000 == 0 {
                                                                if insn & 0x20000000 == 0 {
                                                                    if insn & 0xffbffc00
                                                                        == 0x5e21a800
                                                                    {
                                                                        return Some (FCVTNS_Sd_Sn :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xffbffc00
                                                                        == 0x7e21a800
                                                                    {
                                                                        return Some (FCVTNU_Sd_Sn :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0x20000000 == 0 {
                                                                    if insn & 0xffbffc00
                                                                        == 0x5ea1a800
                                                                    {
                                                                        return Some (FCVTPS_Sd_Sn :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xffbffc00
                                                                        == 0x7ea1a800
                                                                    {
                                                                        return Some (FCVTPU_Sd_Sn :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x800000 == 0 {
                                                                if insn & 0x20000000 == 0 {
                                                                    if insn & 0xfffffc00
                                                                        == 0x5e79a800
                                                                    {
                                                                        return Some (FCVTNS_Sd_S_H_Sn_S_H :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xfffffc00
                                                                        == 0x7e79a800
                                                                    {
                                                                        return Some (FCVTNU_Sd_S_H_Sn_S_H :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0x20000000 == 0 {
                                                                    if insn & 0xfffffc00
                                                                        == 0x5ef9a800
                                                                    {
                                                                        return Some (FCVTPS_Sd_S_H_Sn_S_H :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xfffffc00
                                                                        == 0x7ef9a800
                                                                    {
                                                                        return Some (FCVTPU_Sd_S_H_Sn_S_H :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            }
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0x008000 == 0 {
                                                    if insn & 0x20000000 == 0 {
                                                        if insn & 0xffe0fc00 == 0x1ee06800 {
                                                            return Some(
                                                                FMAXNM_Fd_Fn_Fm::make_opcode(insn),
                                                            );
                                                        }
                                                        if insn & 0xff20fc00 == 0x1e206800 {
                                                            return Some (FMAXNM_Fd_S_S_Fn_S_S_Fm_S_S :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xffbffc00 == 0x7e216800 {
                                                            return Some(
                                                                FCVTXN_Sd_Sn::make_opcode(insn),
                                                            );
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x080000 == 0 {
                                                        if insn & 0xffbffc00 == 0x5ea0e800 {
                                                            return Some(
                                                                FCMLT_Sd_Sn_FPIMM0::make_opcode(
                                                                    insn,
                                                                ),
                                                            );
                                                        }
                                                    } else {
                                                        if insn & 0xfffffc00 == 0x5ef8e800 {
                                                            return Some (FCMLT_Sd_S_H_Sn_S_H_FPIMM0 :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                }
                                            }
                                        }
                                    } else {
                                        if insn & 0x002000 == 0 {
                                            if insn & 0x004000 == 0 {
                                                if insn & 0x008000 == 0 {
                                                    if insn & 0x40000000 == 0 {
                                                        if insn & 0xffe0fc00 == 0x1ee01800 {
                                                            return Some(
                                                                FDIV_Fd_Fn_Fm::make_opcode(insn),
                                                            );
                                                        }
                                                        if insn & 0xff20fc00 == 0x1e201800 {
                                                            return Some (FDIV_Fd_S_S_Fn_S_S_Fm_S_S :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xfffffc00 == 0x5e281800 {
                                                            return Some(
                                                                SHA1SU1_Vd_Vn::make_opcode(insn),
                                                            );
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x20000000 == 0 {
                                                        if insn & 0xff3ffc00 == 0x5e209800 {
                                                            return Some(
                                                                CMEQ_Sd_Sn_IMM0::make_opcode(insn),
                                                            );
                                                        }
                                                    } else {
                                                        if insn & 0xff3ffc00 == 0x7e209800 {
                                                            return Some(
                                                                CMLE_Sd_Sn_IMM0::make_opcode(insn),
                                                            );
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0x008000 == 0 {
                                                    if insn & 0xffe0fc00 == 0x1ee05800 {
                                                        return Some(FMIN_Fd_Fn_Fm::make_opcode(
                                                            insn,
                                                        ));
                                                    }
                                                    if insn & 0xff20fc00 == 0x1e205800 {
                                                        return Some(
                                                            FMIN_Fd_S_S_Fn_S_S_Fm_S_S::make_opcode(
                                                                insn,
                                                            ),
                                                        );
                                                    }
                                                } else {
                                                    if insn & 0x010000 == 0 {
                                                        if insn & 0x080000 == 0 {
                                                            if insn & 0x100000 == 0 {
                                                                if insn & 0x20000000 == 0 {
                                                                    if insn & 0xffbffc00
                                                                        == 0x5ea0d800
                                                                    {
                                                                        return Some (FCMEQ_Sd_Sn_FPIMM0 :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xffbffc00
                                                                        == 0x7ea0d800
                                                                    {
                                                                        return Some (FCMLE_Sd_Sn_FPIMM0 :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0x20000000 == 0 {
                                                                    if insn & 0xfffffc00
                                                                        == 0x5e30d800
                                                                    {
                                                                        return Some (FADDP_Sd_Vn :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xffbffc00
                                                                        == 0x7e30d800
                                                                    {
                                                                        return Some (FADDP_Sd_S_S_Vn_V_2S :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x20000000 == 0 {
                                                                if insn & 0xfffffc00 == 0x5ef8d800 {
                                                                    return Some (FCMEQ_Sd_S_H_Sn_S_H_FPIMM0 :: make_opcode (insn)) ;
                                                                }
                                                            } else {
                                                                if insn & 0xfffffc00 == 0x7ef8d800 {
                                                                    return Some (FCMLE_Sd_S_H_Sn_S_H_FPIMM0 :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x080000 == 0 {
                                                            if insn & 0x800000 == 0 {
                                                                if insn & 0x20000000 == 0 {
                                                                    if insn & 0xffbffc00
                                                                        == 0x5e21d800
                                                                    {
                                                                        return Some (SCVTF_Sd_Sn :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xffbffc00
                                                                        == 0x7e21d800
                                                                    {
                                                                        return Some (UCVTF_Sd_Sn :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0x20000000 == 0 {
                                                                    if insn & 0xffbffc00
                                                                        == 0x5ea1d800
                                                                    {
                                                                        return Some (FRECPE_Sd_Sn :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xffbffc00
                                                                        == 0x7ea1d800
                                                                    {
                                                                        return Some (FRSQRTE_Sd_Sn :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x800000 == 0 {
                                                                if insn & 0x20000000 == 0 {
                                                                    if insn & 0xfffffc00
                                                                        == 0x5e79d800
                                                                    {
                                                                        return Some (SCVTF_Sd_S_H_Sn_S_H :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xfffffc00
                                                                        == 0x7e79d800
                                                                    {
                                                                        return Some (UCVTF_Sd_S_H_Sn_S_H :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0x20000000 == 0 {
                                                                    if insn & 0xfffffc00
                                                                        == 0x5ef9d800
                                                                    {
                                                                        return Some (FRECPE_Sd_S_H_Sn_S_H :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xfffffc00
                                                                        == 0x7ef9d800
                                                                    {
                                                                        return Some (FRSQRTE_Sd_S_H_Sn_S_H :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            }
                                                        }
                                                    }
                                                }
                                            }
                                        } else {
                                            if insn & 0x004000 == 0 {
                                                if insn & 0x008000 == 0 {
                                                    if insn & 0x20000000 == 0 {
                                                        if insn & 0x40000000 == 0 {
                                                            if insn & 0xffe0fc00 == 0x1ee03800 {
                                                                return Some(
                                                                    FSUB_Fd_Fn_Fm::make_opcode(
                                                                        insn,
                                                                    ),
                                                                );
                                                            }
                                                            if insn & 0xff20fc00 == 0x1e203800 {
                                                                return Some (FSUB_Fd_S_S_Fn_S_S_Fm_S_S :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xff3ffc00 == 0x5e203800 {
                                                                return Some(
                                                                    SUQADD_Sd_Sn::make_opcode(insn),
                                                                );
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0xff3ffc00 == 0x7e203800 {
                                                            return Some(
                                                                USQADD_Sd_Sn::make_opcode(insn),
                                                            );
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x010000 == 0 {
                                                        if insn & 0x20000000 == 0 {
                                                            if insn & 0xff3ffc00 == 0x5e20b800 {
                                                                return Some(
                                                                    ABS_Sd_Sn::make_opcode(insn),
                                                                );
                                                            }
                                                        } else {
                                                            if insn & 0xff3ffc00 == 0x7e20b800 {
                                                                return Some(
                                                                    NEG_Sd_Sn::make_opcode(insn),
                                                                );
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x080000 == 0 {
                                                            if insn & 0x100000 == 0 {
                                                                if insn & 0x800000 == 0 {
                                                                    if insn & 0x20000000 == 0 {
                                                                        if insn & 0xffbffc00
                                                                            == 0x5e21b800
                                                                        {
                                                                            return Some (FCVTMS_Sd_Sn :: make_opcode (insn)) ;
                                                                        }
                                                                    } else {
                                                                        if insn & 0xffbffc00
                                                                            == 0x7e21b800
                                                                        {
                                                                            return Some (FCVTMU_Sd_Sn :: make_opcode (insn)) ;
                                                                        }
                                                                    }
                                                                } else {
                                                                    if insn & 0x20000000 == 0 {
                                                                        if insn & 0xffbffc00
                                                                            == 0x5ea1b800
                                                                        {
                                                                            return Some (FCVTZS_Sd_Sn :: make_opcode (insn)) ;
                                                                        }
                                                                    } else {
                                                                        if insn & 0xffbffc00
                                                                            == 0x7ea1b800
                                                                        {
                                                                            return Some (FCVTZU_Sd_Sn :: make_opcode (insn)) ;
                                                                        }
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0xff3ffc00 == 0x5e31b800 {
                                                                    return Some(
                                                                        ADDP_Sd_Vn::make_opcode(
                                                                            insn,
                                                                        ),
                                                                    );
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x800000 == 0 {
                                                                if insn & 0x20000000 == 0 {
                                                                    if insn & 0xfffffc00
                                                                        == 0x5e79b800
                                                                    {
                                                                        return Some (FCVTMS_Sd_S_H_Sn_S_H :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xfffffc00
                                                                        == 0x7e79b800
                                                                    {
                                                                        return Some (FCVTMU_Sd_S_H_Sn_S_H :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            } else {
                                                                if insn & 0x20000000 == 0 {
                                                                    if insn & 0xfffffc00
                                                                        == 0x5ef9b800
                                                                    {
                                                                        return Some (FCVTZS_Sd_S_H_Sn_S_H :: make_opcode (insn)) ;
                                                                    }
                                                                } else {
                                                                    if insn & 0xfffffc00
                                                                        == 0x7ef9b800
                                                                    {
                                                                        return Some (FCVTZU_Sd_S_H_Sn_S_H :: make_opcode (insn)) ;
                                                                    }
                                                                }
                                                            }
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0x008000 == 0 {
                                                    if insn & 0x20000000 == 0 {
                                                        if insn & 0x40000000 == 0 {
                                                            if insn & 0xffe0fc00 == 0x1ee07800 {
                                                                return Some(
                                                                    FMINNM_Fd_Fn_Fm::make_opcode(
                                                                        insn,
                                                                    ),
                                                                );
                                                            }
                                                            if insn & 0xff20fc00 == 0x1e207800 {
                                                                return Some (FMINNM_Fd_S_S_Fn_S_S_Fm_S_S :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xff3ffc00 == 0x5e207800 {
                                                                return Some(
                                                                    SQABS_Sd_Sn::make_opcode(insn),
                                                                );
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0xff3ffc00 == 0x7e207800 {
                                                            return Some(SQNEG_Sd_Sn::make_opcode(
                                                                insn,
                                                            ));
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x010000 == 0 {
                                                        if insn & 0x800000 == 0 {
                                                            if insn & 0x20000000 == 0 {
                                                                if insn & 0xfffffc00 == 0x5e30f800 {
                                                                    return Some(
                                                                        FMAXP_Sd_Vn::make_opcode(
                                                                            insn,
                                                                        ),
                                                                    );
                                                                }
                                                            } else {
                                                                if insn & 0xffbffc00 == 0x7e30f800 {
                                                                    return Some (FMAXP_Sd_S_S_Vn_V_2S :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        } else {
                                                            if insn & 0x20000000 == 0 {
                                                                if insn & 0xfffffc00 == 0x5eb0f800 {
                                                                    return Some(
                                                                        FMINP_Sd_Vn::make_opcode(
                                                                            insn,
                                                                        ),
                                                                    );
                                                                }
                                                            } else {
                                                                if insn & 0xffbffc00 == 0x7eb0f800 {
                                                                    return Some (FMINP_Sd_S_S_Vn_V_2S :: make_opcode (insn)) ;
                                                                }
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0x080000 == 0 {
                                                            if insn & 0xffbffc00 == 0x5ea1f800 {
                                                                return Some(
                                                                    FRECPX_Sd_Sn::make_opcode(insn),
                                                                );
                                                            }
                                                        } else {
                                                            if insn & 0xfffffc00 == 0x5ef9f800 {
                                                                return Some (FRECPX_Sd_S_H_Sn_S_H :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    }
                                                }
                                            }
                                        }
                                    }
                                }
                            } else {
                                if insn & 0x000800 == 0 {
                                    if insn & 0x20000000 == 0 {
                                        if insn & 0x40000000 == 0 {
                                            if insn & 0x000010 == 0 {
                                                if insn & 0xffe00c10 == 0x1ee00400 {
                                                    return Some(
                                                        FCCMP_Fn_Fm_NZCV_COND::make_opcode(insn),
                                                    );
                                                }
                                                if insn & 0xff200c10 == 0x1e200400 {
                                                    return Some(
                                                        FCCMP_Fn_S_S_Fm_S_S_NZCV_COND::make_opcode(
                                                            insn,
                                                        ),
                                                    );
                                                }
                                            } else {
                                                if insn & 0xffe00c10 == 0x1ee00410 {
                                                    return Some(
                                                        FCCMPE_Fn_Fm_NZCV_COND::make_opcode(insn),
                                                    );
                                                }
                                                if insn & 0xff200c10 == 0x1e200410 {
                                                    return Some(
                                                        FCCMPE_Fn_S_S_Fm_S_S_NZCV_COND::make_opcode(
                                                            insn,
                                                        ),
                                                    );
                                                }
                                            }
                                        } else {
                                            if insn & 0x001000 == 0 {
                                                if insn & 0x002000 == 0 {
                                                    if insn & 0x004000 == 0 {
                                                        if insn & 0xffe0fc00 == 0x5ee08400 {
                                                            return Some(
                                                                ADD_Sd_Sn_Sm::make_opcode(insn),
                                                            );
                                                        }
                                                    } else {
                                                        if insn & 0xffe0fc00 == 0x5ee04400 {
                                                            return Some(
                                                                SSHL_Sd_Sn_Sm::make_opcode(insn),
                                                            );
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0xffa0fc00 == 0x5e20e400 {
                                                        return Some(
                                                            FCMEQ_Sd_S_S_Sn_S_S_Sm_S_S::make_opcode(
                                                                insn,
                                                            ),
                                                        );
                                                    }
                                                }
                                            } else {
                                                if insn & 0x002000 == 0 {
                                                    if insn & 0xffe0fc00 == 0x5ee05400 {
                                                        return Some(SRSHL_Sd_Sn_Sm::make_opcode(
                                                            insn,
                                                        ));
                                                    }
                                                } else {
                                                    if insn & 0x008000 == 0 {
                                                        if insn & 0xffe0fc00 == 0x5ee03400 {
                                                            return Some(
                                                                CMGT_Sd_Sn_Sm::make_opcode(insn),
                                                            );
                                                        }
                                                    } else {
                                                        if insn & 0xff20fc00 == 0x5e20b400 {
                                                            return Some(
                                                                SQDMULH_Sd_Sn_Sm::make_opcode(insn),
                                                            );
                                                        }
                                                    }
                                                }
                                            }
                                        }
                                    } else {
                                        if insn & 0x001000 == 0 {
                                            if insn & 0x002000 == 0 {
                                                if insn & 0x004000 == 0 {
                                                    if insn & 0xffe0fc00 == 0x7ee08400 {
                                                        return Some(SUB_Sd_Sn_Sm::make_opcode(
                                                            insn,
                                                        ));
                                                    }
                                                } else {
                                                    if insn & 0xffe0fc00 == 0x7ee04400 {
                                                        return Some(USHL_Sd_Sn_Sm::make_opcode(
                                                            insn,
                                                        ));
                                                    }
                                                }
                                            } else {
                                                if insn & 0x800000 == 0 {
                                                    if insn & 0xffa0fc00 == 0x7e20e400 {
                                                        return Some(
                                                            FCMGE_Sd_S_S_Sn_S_S_Sm_S_S::make_opcode(
                                                                insn,
                                                            ),
                                                        );
                                                    }
                                                } else {
                                                    if insn & 0xffa0fc00 == 0x7ea0e400 {
                                                        return Some(
                                                            FCMGT_Sd_S_S_Sn_S_S_Sm_S_S::make_opcode(
                                                                insn,
                                                            ),
                                                        );
                                                    }
                                                }
                                            }
                                        } else {
                                            if insn & 0x002000 == 0 {
                                                if insn & 0x008000 == 0 {
                                                    if insn & 0xffe0fc00 == 0x7ee05400 {
                                                        return Some(URSHL_Sd_Sn_Sm::make_opcode(
                                                            insn,
                                                        ));
                                                    }
                                                } else {
                                                    if insn & 0xffa0fc00 == 0x7ea0d400 {
                                                        return Some(
                                                            FABD_Sd_S_S_Sn_S_S_Sm_S_S::make_opcode(
                                                                insn,
                                                            ),
                                                        );
                                                    }
                                                }
                                            } else {
                                                if insn & 0x008000 == 0 {
                                                    if insn & 0xffe0fc00 == 0x7ee03400 {
                                                        return Some(CMHI_Sd_Sn_Sm::make_opcode(
                                                            insn,
                                                        ));
                                                    }
                                                } else {
                                                    if insn & 0xff20fc00 == 0x7e20b400 {
                                                        return Some(
                                                            SQRDMULH_Sd_Sn_Sm::make_opcode(insn),
                                                        );
                                                    }
                                                }
                                            }
                                        }
                                    }
                                } else {
                                    if insn & 0x20000000 == 0 {
                                        if insn & 0x40000000 == 0 {
                                            if insn & 0xffe00c00 == 0x1ee00c00 {
                                                return Some(FCSEL_Fd_Fn_Fm_COND::make_opcode(
                                                    insn,
                                                ));
                                            }
                                            if insn & 0xff200c00 == 0x1e200c00 {
                                                return Some(
                                                    FCSEL_Fd_S_S_Fn_S_S_Fm_S_S_COND::make_opcode(
                                                        insn,
                                                    ),
                                                );
                                            }
                                        } else {
                                            if insn & 0x001000 == 0 {
                                                if insn & 0x002000 == 0 {
                                                    if insn & 0x004000 == 0 {
                                                        if insn & 0x008000 == 0 {
                                                            if insn & 0xff20fc00 == 0x5e200c00 {
                                                                return Some(
                                                                    SQADD_Sd_Sn_Sm::make_opcode(
                                                                        insn,
                                                                    ),
                                                                );
                                                            }
                                                        } else {
                                                            if insn & 0xffe0fc00 == 0x5ee08c00 {
                                                                return Some(
                                                                    CMTST_Sd_Sn_Sm::make_opcode(
                                                                        insn,
                                                                    ),
                                                                );
                                                            }
                                                        }
                                                    } else {
                                                        if insn & 0xff20fc00 == 0x5e204c00 {
                                                            return Some(
                                                                SQSHL_Sd_Sn_Sm::make_opcode(insn),
                                                            );
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0xff20fc00 == 0x5e202c00 {
                                                        return Some(SQSUB_Sd_Sn_Sm::make_opcode(
                                                            insn,
                                                        ));
                                                    }
                                                }
                                            } else {
                                                if insn & 0x002000 == 0 {
                                                    if insn & 0x008000 == 0 {
                                                        if insn & 0xff20fc00 == 0x5e205c00 {
                                                            return Some(
                                                                SQRSHL_Sd_Sn_Sm::make_opcode(insn),
                                                            );
                                                        }
                                                    } else {
                                                        if insn & 0xffa0fc00 == 0x5e20dc00 {
                                                            return Some (FMULX_Sd_S_S_Sn_S_S_Sm_S_S :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x004000 == 0 {
                                                        if insn & 0xffe0fc00 == 0x5ee03c00 {
                                                            return Some(
                                                                CMGE_Sd_Sn_Sm::make_opcode(insn),
                                                            );
                                                        }
                                                    } else {
                                                        if insn & 0x800000 == 0 {
                                                            if insn & 0xffa0fc00 == 0x5e20fc00 {
                                                                return Some (FRECPS_Sd_S_S_Sn_S_S_Sm_S_S :: make_opcode (insn)) ;
                                                            }
                                                        } else {
                                                            if insn & 0xffa0fc00 == 0x5ea0fc00 {
                                                                return Some (FRSQRTS_Sd_S_S_Sn_S_S_Sm_S_S :: make_opcode (insn)) ;
                                                            }
                                                        }
                                                    }
                                                }
                                            }
                                        }
                                    } else {
                                        if insn & 0x001000 == 0 {
                                            if insn & 0x002000 == 0 {
                                                if insn & 0x004000 == 0 {
                                                    if insn & 0x008000 == 0 {
                                                        if insn & 0xff20fc00 == 0x7e200c00 {
                                                            return Some(
                                                                UQADD_Sd_Sn_Sm::make_opcode(insn),
                                                            );
                                                        }
                                                    } else {
                                                        if insn & 0xffe0fc00 == 0x7ee08c00 {
                                                            return Some(
                                                                CMEQ_Sd_Sn_Sm::make_opcode(insn),
                                                            );
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0xff20fc00 == 0x7e204c00 {
                                                        return Some(UQSHL_Sd_Sn_Sm::make_opcode(
                                                            insn,
                                                        ));
                                                    }
                                                }
                                            } else {
                                                if insn & 0x004000 == 0 {
                                                    if insn & 0xff20fc00 == 0x7e202c00 {
                                                        return Some(UQSUB_Sd_Sn_Sm::make_opcode(
                                                            insn,
                                                        ));
                                                    }
                                                } else {
                                                    if insn & 0x800000 == 0 {
                                                        if insn & 0xffa0fc00 == 0x7e20ec00 {
                                                            return Some (FACGE_Sd_S_S_Sn_S_S_Sm_S_S :: make_opcode (insn)) ;
                                                        }
                                                    } else {
                                                        if insn & 0xffa0fc00 == 0x7ea0ec00 {
                                                            return Some (FACGT_Sd_S_S_Sn_S_S_Sm_S_S :: make_opcode (insn)) ;
                                                        }
                                                    }
                                                }
                                            }
                                        } else {
                                            if insn & 0x002000 == 0 {
                                                if insn & 0xff20fc00 == 0x7e205c00 {
                                                    return Some(UQRSHL_Sd_Sn_Sm::make_opcode(
                                                        insn,
                                                    ));
                                                }
                                            } else {
                                                if insn & 0xffe0fc00 == 0x7ee03c00 {
                                                    return Some(CMHS_Sd_Sn_Sm::make_opcode(insn));
                                                }
                                            }
                                        }
                                    }
                                }
                            }
                        }
                    }
                } else {
                    if insn & 0x008000 == 0 {
                        if insn & 0x10000000 == 0 {
                            if insn & 0x000400 == 0 {
                                if insn & 0x001000 == 0 {
                                    if insn & 0x002000 == 0 {
                                        if insn & 0x004000 == 0 {
                                            if insn & 0x20000000 == 0 {
                                                if insn & 0x40000000 == 0 {
                                                    if insn & 0xffc0f400 == 0xf800000 {
                                                        return Some(
                                                            FMLAL_Vd_Vn_Em16::make_opcode(insn),
                                                        );
                                                    }
                                                } else {
                                                    if insn & 0xffc0f400 == 0x4f800000 {
                                                        return Some (FMLAL_Vd_V_4S_Vn_V_4H_Em16_S_H :: make_opcode (insn)) ;
                                                    }
                                                }
                                            } else {
                                                if insn & 0xbf00f400 == 0x2f000000 {
                                                    return Some(MLA_Vd_Vn_Em16::make_opcode(insn));
                                                }
                                            }
                                        } else {
                                            if insn & 0x20000000 == 0 {
                                                if insn & 0x40000000 == 0 {
                                                    if insn & 0xffc0f400 == 0xf804000 {
                                                        return Some(
                                                            FMLSL_Vd_Vn_Em16::make_opcode(insn),
                                                        );
                                                    }
                                                } else {
                                                    if insn & 0xffc0f400 == 0x4f804000 {
                                                        return Some (FMLSL_Vd_V_4S_Vn_V_4H_Em16_S_H :: make_opcode (insn)) ;
                                                    }
                                                }
                                            } else {
                                                if insn & 0xbf00f400 == 0x2f004000 {
                                                    return Some(MLS_Vd_Vn_Em16::make_opcode(insn));
                                                }
                                            }
                                        }
                                    } else {
                                        if insn & 0x004000 == 0 {
                                            if insn & 0x20000000 == 0 {
                                                if insn & 0x40000000 == 0 {
                                                    if insn & 0xff00f400 == 0xf002000 {
                                                        return Some(
                                                            SMLAL_Vd_Vn_Em16::make_opcode(insn),
                                                        );
                                                    }
                                                } else {
                                                    if insn & 0xff00f400 == 0x4f002000 {
                                                        return Some(
                                                            SMLAL2_Vd_Vn_Em16::make_opcode(insn),
                                                        );
                                                    }
                                                }
                                            } else {
                                                if insn & 0x40000000 == 0 {
                                                    if insn & 0xff00f400 == 0x2f002000 {
                                                        return Some(
                                                            UMLAL_Vd_Vn_Em16::make_opcode(insn),
                                                        );
                                                    }
                                                } else {
                                                    if insn & 0xff00f400 == 0x6f002000 {
                                                        return Some(
                                                            UMLAL2_Vd_Vn_Em16::make_opcode(insn),
                                                        );
                                                    }
                                                }
                                            }
                                        } else {
                                            if insn & 0x20000000 == 0 {
                                                if insn & 0x40000000 == 0 {
                                                    if insn & 0xff00f400 == 0xf006000 {
                                                        return Some(
                                                            SMLSL_Vd_Vn_Em16::make_opcode(insn),
                                                        );
                                                    }
                                                } else {
                                                    if insn & 0xff00f400 == 0x4f006000 {
                                                        return Some(
                                                            SMLSL2_Vd_Vn_Em16::make_opcode(insn),
                                                        );
                                                    }
                                                }
                                            } else {
                                                if insn & 0x40000000 == 0 {
                                                    if insn & 0xff00f400 == 0x2f006000 {
                                                        return Some(
                                                            UMLSL_Vd_Vn_Em16::make_opcode(insn),
                                                        );
                                                    }
                                                } else {
                                                    if insn & 0xff00f400 == 0x6f006000 {
                                                        return Some(
                                                            UMLSL2_Vd_Vn_Em16::make_opcode(insn),
                                                        );
                                                    }
                                                }
                                            }
                                        }
                                    }
                                } else {
                                    if insn & 0x20000000 == 0 {
                                        if insn & 0x002000 == 0 {
                                            if insn & 0x004000 == 0 {
                                                if insn & 0x800000 == 0 {
                                                    if insn & 0xbfc0f400 == 0xf001000 {
                                                        return Some(FMLA_Vd_Vn_Em16::make_opcode(
                                                            insn,
                                                        ));
                                                    }
                                                } else {
                                                    if insn & 0xbf80f400 == 0xf801000 {
                                                        return Some(FMLA_Vd_Vn_Em::make_opcode(
                                                            insn,
                                                        ));
                                                    }
                                                }
                                            } else {
                                                if insn & 0x800000 == 0 {
                                                    if insn & 0xbfc0f400 == 0xf005000 {
                                                        return Some(FMLS_Vd_Vn_Em16::make_opcode(
                                                            insn,
                                                        ));
                                                    }
                                                } else {
                                                    if insn & 0xbf80f400 == 0xf805000 {
                                                        return Some(FMLS_Vd_Vn_Em::make_opcode(
                                                            insn,
                                                        ));
                                                    }
                                                }
                                            }
                                        } else {
                                            if insn & 0x004000 == 0 {
                                                if insn & 0x40000000 == 0 {
                                                    if insn & 0xff00f400 == 0xf003000 {
                                                        return Some(
                                                            SQDMLAL_Vd_Vn_Em16::make_opcode(insn),
                                                        );
                                                    }
                                                } else {
                                                    if insn & 0xff00f400 == 0x4f003000 {
                                                        return Some(
                                                            SQDMLAL2_Vd_Vn_Em16::make_opcode(insn),
                                                        );
                                                    }
                                                }
                                            } else {
                                                if insn & 0x40000000 == 0 {
                                                    if insn & 0xff00f400 == 0xf007000 {
                                                        return Some(
                                                            SQDMLSL_Vd_Vn_Em16::make_opcode(insn),
                                                        );
                                                    }
                                                } else {
                                                    if insn & 0xff00f400 == 0x4f007000 {
                                                        return Some(
                                                            SQDMLSL2_Vd_Vn_Em16::make_opcode(insn),
                                                        );
                                                    }
                                                }
                                            }
                                        }
                                    } else {
                                        if insn & 0xbf009400 == 0x2f001000 {
                                            return Some(FCMLA_Vd_Vn_Em_IMM_ROT2::make_opcode(
                                                insn,
                                            ));
                                        }
                                    }
                                }
                            } else {
                                if insn & 0x001000 == 0 {
                                    if insn & 0x20000000 == 0 {
                                        if insn & 0xbff89c00 == 0xf000400 {
                                            return Some(MOVI_Vd_SIMD_IMM_SFT::make_opcode(insn));
                                        }
                                        if insn & 0xbf80fc00 == 0xf000400 {
                                            return Some(SSHR_Vd_Vn_IMM_VLSR::make_opcode(insn));
                                        }
                                        if insn & 0xbf80fc00 == 0xf002400 {
                                            return Some(SRSHR_Vd_Vn_IMM_VLSR::make_opcode(insn));
                                        }
                                    } else {
                                        if insn & 0xbff89c00 == 0x2f000400 {
                                            return Some(MVNI_Vd_SIMD_IMM_SFT::make_opcode(insn));
                                        }
                                        if insn & 0xbf80fc00 == 0x2f000400 {
                                            return Some(USHR_Vd_Vn_IMM_VLSR::make_opcode(insn));
                                        }
                                        if insn & 0xbf80fc00 == 0x2f002400 {
                                            return Some(URSHR_Vd_Vn_IMM_VLSR::make_opcode(insn));
                                        }
                                        if insn & 0xbf80fc00 == 0x2f004400 {
                                            return Some(SRI_Vd_Vn_IMM_VLSR::make_opcode(insn));
                                        }
                                        if insn & 0xbf80fc00 == 0x2f006400 {
                                            return Some(SQSHLU_Vd_Vn_IMM_VLSL::make_opcode(insn));
                                        }
                                    }
                                } else {
                                    if insn & 0x20000000 == 0 {
                                        if insn & 0xbff89c00 == 0xf001400 {
                                            return Some(ORR_Vd_SIMD_IMM_SFT::make_opcode(insn));
                                        }
                                        if insn & 0xbf80fc00 == 0xf001400 {
                                            return Some(SSRA_Vd_Vn_IMM_VLSR::make_opcode(insn));
                                        }
                                        if insn & 0xbf80fc00 == 0xf003400 {
                                            return Some(SRSRA_Vd_Vn_IMM_VLSR::make_opcode(insn));
                                        }
                                        if insn & 0xbf80fc00 == 0xf005400 {
                                            return Some(SHL_Vd_Vn_IMM_VLSL::make_opcode(insn));
                                        }
                                        if insn & 0xbf80fc00 == 0xf007400 {
                                            return Some(SQSHL_Vd_Vn_IMM_VLSL::make_opcode(insn));
                                        }
                                    } else {
                                        if insn & 0xbff89c00 == 0x2f001400 {
                                            return Some(BIC_Vd_SIMD_IMM_SFT::make_opcode(insn));
                                        }
                                        if insn & 0xbf80fc00 == 0x2f001400 {
                                            return Some(USRA_Vd_Vn_IMM_VLSR::make_opcode(insn));
                                        }
                                        if insn & 0xbf80fc00 == 0x2f003400 {
                                            return Some(URSRA_Vd_Vn_IMM_VLSR::make_opcode(insn));
                                        }
                                        if insn & 0xbf80fc00 == 0x2f005400 {
                                            return Some(SLI_Vd_Vn_IMM_VLSL::make_opcode(insn));
                                        }
                                        if insn & 0xbf80fc00 == 0x2f007400 {
                                            return Some(UQSHL_Vd_Vn_IMM_VLSL::make_opcode(insn));
                                        }
                                    }
                                }
                            }
                        } else {
                            if insn & 0x20000000 == 0 {
                                if insn & 0x40000000 == 0 {
                                    if insn & 0x200000 == 0 {
                                        if insn & 0xffe08000 == 0x1fc00000 {
                                            return Some(FMADD_Fd_Fn_Fm_Fa::make_opcode(insn));
                                        }
                                        if insn & 0xff208000 == 0x1f000000 {
                                            return Some(
                                                FMADD_Fd_S_S_Fn_S_S_Fm_S_S_Fa_S_S::make_opcode(
                                                    insn,
                                                ),
                                            );
                                        }
                                    } else {
                                        if insn & 0xffe08000 == 0x1fe00000 {
                                            return Some(FNMADD_Fd_Fn_Fm_Fa::make_opcode(insn));
                                        }
                                        if insn & 0xff208000 == 0x1f200000 {
                                            return Some(
                                                FNMADD_Fd_S_S_Fn_S_S_Fm_S_S_Fa_S_S::make_opcode(
                                                    insn,
                                                ),
                                            );
                                        }
                                    }
                                } else {
                                    if insn & 0x000400 == 0 {
                                        if insn & 0x002000 == 0 {
                                            if insn & 0x004000 == 0 {
                                                if insn & 0x800000 == 0 {
                                                    if insn & 0xffc0f400 == 0x5f001000 {
                                                        return Some(FMLA_Sd_Sn_Em16::make_opcode(
                                                            insn,
                                                        ));
                                                    }
                                                } else {
                                                    if insn & 0xff80f400 == 0x5f801000 {
                                                        return Some(FMLA_Sd_Sn_Em::make_opcode(
                                                            insn,
                                                        ));
                                                    }
                                                }
                                            } else {
                                                if insn & 0x800000 == 0 {
                                                    if insn & 0xffc0f400 == 0x5f005000 {
                                                        return Some(FMLS_Sd_Sn_Em16::make_opcode(
                                                            insn,
                                                        ));
                                                    }
                                                } else {
                                                    if insn & 0xff80f400 == 0x5f805000 {
                                                        return Some(FMLS_Sd_Sn_Em::make_opcode(
                                                            insn,
                                                        ));
                                                    }
                                                }
                                            }
                                        } else {
                                            if insn & 0x004000 == 0 {
                                                if insn & 0xff00f400 == 0x5f003000 {
                                                    return Some(SQDMLAL_Sd_Sn_Em16::make_opcode(
                                                        insn,
                                                    ));
                                                }
                                            } else {
                                                if insn & 0xff00f400 == 0x5f007000 {
                                                    return Some(SQDMLSL_Sd_Sn_Em16::make_opcode(
                                                        insn,
                                                    ));
                                                }
                                            }
                                        }
                                    } else {
                                        if insn & 0x001000 == 0 {
                                            if insn & 0x002000 == 0 {
                                                if insn & 0xff80fc00 == 0x5f000400 {
                                                    return Some(SSHR_Sd_Sn_IMM_VLSR::make_opcode(
                                                        insn,
                                                    ));
                                                }
                                            } else {
                                                if insn & 0xff80fc00 == 0x5f002400 {
                                                    return Some(
                                                        SRSHR_Sd_Sn_IMM_VLSR::make_opcode(insn),
                                                    );
                                                }
                                            }
                                        } else {
                                            if insn & 0x002000 == 0 {
                                                if insn & 0x004000 == 0 {
                                                    if insn & 0xff80fc00 == 0x5f001400 {
                                                        return Some(
                                                            SSRA_Sd_Sn_IMM_VLSR::make_opcode(insn),
                                                        );
                                                    }
                                                } else {
                                                    if insn & 0xff80fc00 == 0x5f005400 {
                                                        return Some(
                                                            SHL_Sd_Sn_IMM_VLSL::make_opcode(insn),
                                                        );
                                                    }
                                                }
                                            } else {
                                                if insn & 0x004000 == 0 {
                                                    if insn & 0xff80fc00 == 0x5f003400 {
                                                        return Some(
                                                            SRSRA_Sd_Sn_IMM_VLSR::make_opcode(insn),
                                                        );
                                                    }
                                                } else {
                                                    if insn & 0xff80fc00 == 0x5f007400 {
                                                        return Some(
                                                            SQSHL_Sd_Sn_IMM_VLSL::make_opcode(insn),
                                                        );
                                                    }
                                                }
                                            }
                                        }
                                    }
                                }
                            } else {
                                if insn & 0x001000 == 0 {
                                    if insn & 0x002000 == 0 {
                                        if insn & 0x004000 == 0 {
                                            if insn & 0xff80fc00 == 0x7f000400 {
                                                return Some(USHR_Sd_Sn_IMM_VLSR::make_opcode(
                                                    insn,
                                                ));
                                            }
                                        } else {
                                            if insn & 0xff80fc00 == 0x7f004400 {
                                                return Some(SRI_Sd_Sn_IMM_VLSR::make_opcode(insn));
                                            }
                                        }
                                    } else {
                                        if insn & 0x004000 == 0 {
                                            if insn & 0xff80fc00 == 0x7f002400 {
                                                return Some(URSHR_Sd_Sn_IMM_VLSR::make_opcode(
                                                    insn,
                                                ));
                                            }
                                        } else {
                                            if insn & 0xff80fc00 == 0x7f006400 {
                                                return Some(SQSHLU_Sd_Sn_IMM_VLSL::make_opcode(
                                                    insn,
                                                ));
                                            }
                                        }
                                    }
                                } else {
                                    if insn & 0x002000 == 0 {
                                        if insn & 0x004000 == 0 {
                                            if insn & 0xff80fc00 == 0x7f001400 {
                                                return Some(USRA_Sd_Sn_IMM_VLSR::make_opcode(
                                                    insn,
                                                ));
                                            }
                                        } else {
                                            if insn & 0xff80fc00 == 0x7f005400 {
                                                return Some(SLI_Sd_Sn_IMM_VLSL::make_opcode(insn));
                                            }
                                        }
                                    } else {
                                        if insn & 0x004000 == 0 {
                                            if insn & 0xff80fc00 == 0x7f003400 {
                                                return Some(URSRA_Sd_Sn_IMM_VLSR::make_opcode(
                                                    insn,
                                                ));
                                            }
                                        } else {
                                            if insn & 0xff80fc00 == 0x7f007400 {
                                                return Some(UQSHL_Sd_Sn_IMM_VLSL::make_opcode(
                                                    insn,
                                                ));
                                            }
                                        }
                                    }
                                }
                            }
                        }
                    } else {
                        if insn & 0x10000000 == 0 {
                            if insn & 0x000400 == 0 {
                                if insn & 0x001000 == 0 {
                                    if insn & 0x002000 == 0 {
                                        if insn & 0x004000 == 0 {
                                            if insn & 0x20000000 == 0 {
                                                if insn & 0xbf00f400 == 0xf008000 {
                                                    return Some(MUL_Vd_Vn_Em16::make_opcode(insn));
                                                }
                                            } else {
                                                if insn & 0x40000000 == 0 {
                                                    if insn & 0xffc0f400 == 0x2f808000 {
                                                        return Some(
                                                            FMLAL2_Vd_Vn_Em16::make_opcode(insn),
                                                        );
                                                    }
                                                } else {
                                                    if insn & 0xffc0f400 == 0x6f808000 {
                                                        return Some (FMLAL2_Vd_V_4S_Vn_V_4H_Em16_S_H :: make_opcode (insn)) ;
                                                    }
                                                }
                                            }
                                        } else {
                                            if insn & 0x20000000 == 0 {
                                                if insn & 0xbf00f400 == 0xf00c000 {
                                                    return Some(SQDMULH_Vd_Vn_Em16::make_opcode(
                                                        insn,
                                                    ));
                                                }
                                            } else {
                                                if insn & 0x40000000 == 0 {
                                                    if insn & 0xffc0f400 == 0x2f80c000 {
                                                        return Some(
                                                            FMLSL2_Vd_Vn_Em16::make_opcode(insn),
                                                        );
                                                    }
                                                } else {
                                                    if insn & 0xffc0f400 == 0x6f80c000 {
                                                        return Some (FMLSL2_Vd_V_4S_Vn_V_4H_Em16_S_H :: make_opcode (insn)) ;
                                                    }
                                                }
                                            }
                                        }
                                    } else {
                                        if insn & 0x004000 == 0 {
                                            if insn & 0x20000000 == 0 {
                                                if insn & 0x40000000 == 0 {
                                                    if insn & 0xff00f400 == 0xf00a000 {
                                                        return Some(
                                                            SMULL_Vd_Vn_Em16::make_opcode(insn),
                                                        );
                                                    }
                                                } else {
                                                    if insn & 0xff00f400 == 0x4f00a000 {
                                                        return Some(
                                                            SMULL2_Vd_Vn_Em16::make_opcode(insn),
                                                        );
                                                    }
                                                }
                                            } else {
                                                if insn & 0x40000000 == 0 {
                                                    if insn & 0xff00f400 == 0x2f00a000 {
                                                        return Some(
                                                            UMULL_Vd_Vn_Em16::make_opcode(insn),
                                                        );
                                                    }
                                                } else {
                                                    if insn & 0xff00f400 == 0x6f00a000 {
                                                        return Some(
                                                            UMULL2_Vd_Vn_Em16::make_opcode(insn),
                                                        );
                                                    }
                                                }
                                            }
                                        } else {
                                            if insn & 0x20000000 == 0 {
                                                if insn & 0xbf00f400 == 0xf00e000 {
                                                    return Some(SDOT_Vd_Vn_Em::make_opcode(insn));
                                                }
                                            } else {
                                                if insn & 0xbf00f400 == 0x2f00e000 {
                                                    return Some(UDOT_Vd_Vn_Em::make_opcode(insn));
                                                }
                                            }
                                        }
                                    }
                                } else {
                                    if insn & 0x002000 == 0 {
                                        if insn & 0x004000 == 0 {
                                            if insn & 0x800000 == 0 {
                                                if insn & 0x20000000 == 0 {
                                                    if insn & 0xbfc0f400 == 0xf009000 {
                                                        return Some(FMUL_Vd_Vn_Em16::make_opcode(
                                                            insn,
                                                        ));
                                                    }
                                                } else {
                                                    if insn & 0xbfc0f400 == 0x2f009000 {
                                                        return Some(
                                                            FMULX_Vd_Vn_Em16::make_opcode(insn),
                                                        );
                                                    }
                                                }
                                            } else {
                                                if insn & 0x20000000 == 0 {
                                                    if insn & 0xbf80f400 == 0xf809000 {
                                                        return Some(FMUL_Vd_Vn_Em::make_opcode(
                                                            insn,
                                                        ));
                                                    }
                                                } else {
                                                    if insn & 0xbf80f400 == 0x2f809000 {
                                                        return Some(FMULX_Vd_Vn_Em::make_opcode(
                                                            insn,
                                                        ));
                                                    }
                                                }
                                            }
                                        } else {
                                            if insn & 0x20000000 == 0 {
                                                if insn & 0xbf00f400 == 0xf00d000 {
                                                    return Some(SQRDMULH_Vd_Vn_Em16::make_opcode(
                                                        insn,
                                                    ));
                                                }
                                            } else {
                                                if insn & 0xbf00f400 == 0x2f00d000 {
                                                    return Some(SQRDMLAH_Vd_Vn_Em16::make_opcode(
                                                        insn,
                                                    ));
                                                }
                                            }
                                        }
                                    } else {
                                        if insn & 0x004000 == 0 {
                                            if insn & 0x40000000 == 0 {
                                                if insn & 0xff00f400 == 0xf00b000 {
                                                    return Some(SQDMULL_Vd_Vn_Em16::make_opcode(
                                                        insn,
                                                    ));
                                                }
                                            } else {
                                                if insn & 0xff00f400 == 0x4f00b000 {
                                                    return Some(SQDMULL2_Vd_Vn_Em16::make_opcode(
                                                        insn,
                                                    ));
                                                }
                                            }
                                        } else {
                                            if insn & 0x20000000 == 0 {
                                                if insn & 0x400000 == 0 {
                                                    if insn & 0x800000 == 0 {
                                                        if insn & 0xbfc0f400 == 0xf00f000 {
                                                            return Some(
                                                                SUDOT_Vd_Vn_Em::make_opcode(insn),
                                                            );
                                                        }
                                                    } else {
                                                        if insn & 0xbfc0f400 == 0xf80f000 {
                                                            return Some(
                                                                USDOT_Vd_Vn_Em::make_opcode(insn),
                                                            );
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0x800000 == 0 {
                                                        if insn & 0xbfc0f400 == 0xf40f000 {
                                                            return Some(
                                                                BFDOT_Vd_Vn_Em::make_opcode(insn),
                                                            );
                                                        }
                                                    } else {
                                                        if insn & 0x40000000 == 0 {
                                                            if insn & 0xffc0f400 == 0xfc0f000 {
                                                                return Some(
                                                                    BFMLALB_Vd_Vn_Em16::make_opcode(
                                                                        insn,
                                                                    ),
                                                                );
                                                            }
                                                        } else {
                                                            if insn & 0xffc0f400 == 0x4fc0f000 {
                                                                return Some(
                                                                    BFMLALT_Vd_Vn_Em16::make_opcode(
                                                                        insn,
                                                                    ),
                                                                );
                                                            }
                                                        }
                                                    }
                                                }
                                            } else {
                                                if insn & 0xbf00f400 == 0x2f00f000 {
                                                    return Some(SQRDMLSH_Vd_Vn_Em16::make_opcode(
                                                        insn,
                                                    ));
                                                }
                                            }
                                        }
                                    }
                                }
                            } else {
                                if insn & 0x000800 == 0 {
                                    if insn & 0x004000 == 0 {
                                        if insn & 0x001000 == 0 {
                                            if insn & 0x20000000 == 0 {
                                                if insn & 0xbff8dc00 == 0xf008400 {
                                                    return Some(
                                                        MOVI_Vd_V_4H_SIMD_IMM_SFT_LSL::make_opcode(
                                                            insn,
                                                        ),
                                                    );
                                                }
                                                if insn & 0xff80fc00 == 0xf008400 {
                                                    return Some(SHRN_Vd_Vn_IMM_VLSR::make_opcode(
                                                        insn,
                                                    ));
                                                }
                                                if insn & 0xff80fc00 == 0x4f008400 {
                                                    return Some(
                                                        SHRN2_Vd_Vn_IMM_VLSR::make_opcode(insn),
                                                    );
                                                }
                                                if insn & 0xff80fc00 == 0xf00a400 {
                                                    return Some(
                                                        SSHLL_Vd_Vn_IMM_VLSL::make_opcode(insn),
                                                    );
                                                }
                                                if insn & 0xff80fc00 == 0x4f00a400 {
                                                    return Some(
                                                        SSHLL2_Vd_Vn_IMM_VLSL::make_opcode(insn),
                                                    );
                                                }
                                            } else {
                                                if insn & 0xbff8dc00 == 0x2f008400 {
                                                    return Some(
                                                        MVNI_Vd_V_4H_SIMD_IMM_SFT_LSL::make_opcode(
                                                            insn,
                                                        ),
                                                    );
                                                }
                                                if insn & 0xff80fc00 == 0x2f008400 {
                                                    return Some(
                                                        SQSHRUN_Vd_Vn_IMM_VLSR::make_opcode(insn),
                                                    );
                                                }
                                                if insn & 0xff80fc00 == 0x6f008400 {
                                                    return Some(
                                                        SQSHRUN2_Vd_Vn_IMM_VLSR::make_opcode(insn),
                                                    );
                                                }
                                                if insn & 0xff80fc00 == 0x2f00a400 {
                                                    return Some(
                                                        USHLL_Vd_Vn_IMM_VLSL::make_opcode(insn),
                                                    );
                                                }
                                                if insn & 0xff80fc00 == 0x6f00a400 {
                                                    return Some(
                                                        USHLL2_Vd_Vn_IMM_VLSL::make_opcode(insn),
                                                    );
                                                }
                                            }
                                        } else {
                                            if insn & 0x20000000 == 0 {
                                                if insn & 0xbff8dc00 == 0xf009400 {
                                                    return Some(
                                                        ORR_Vd_V_4H_SIMD_IMM_SFT_LSL::make_opcode(
                                                            insn,
                                                        ),
                                                    );
                                                }
                                                if insn & 0xff80fc00 == 0xf009400 {
                                                    return Some(
                                                        SQSHRN_Vd_Vn_IMM_VLSR::make_opcode(insn),
                                                    );
                                                }
                                                if insn & 0xff80fc00 == 0x4f009400 {
                                                    return Some(
                                                        SQSHRN2_Vd_Vn_IMM_VLSR::make_opcode(insn),
                                                    );
                                                }
                                            } else {
                                                if insn & 0xbff8dc00 == 0x2f009400 {
                                                    return Some(
                                                        BIC_Vd_V_4H_SIMD_IMM_SFT_LSL::make_opcode(
                                                            insn,
                                                        ),
                                                    );
                                                }
                                                if insn & 0xff80fc00 == 0x2f009400 {
                                                    return Some(
                                                        UQSHRN_Vd_Vn_IMM_VLSR::make_opcode(insn),
                                                    );
                                                }
                                                if insn & 0xff80fc00 == 0x6f009400 {
                                                    return Some(
                                                        UQSHRN2_Vd_Vn_IMM_VLSR::make_opcode(insn),
                                                    );
                                                }
                                            }
                                        }
                                    } else {
                                        if insn & 0x002000 == 0 {
                                            if insn & 0x20000000 == 0 {
                                                if insn & 0xbff8ec00 == 0xf00c400 {
                                                    return Some(
                                                        MOVI_Vd_V_2S_SIMD_IMM_SFT_MSL::make_opcode(
                                                            insn,
                                                        ),
                                                    );
                                                }
                                            } else {
                                                if insn & 0xbff8ec00 == 0x2f00c400 {
                                                    return Some(
                                                        MVNI_Vd_V_2S_SIMD_IMM_SFT_MSL::make_opcode(
                                                            insn,
                                                        ),
                                                    );
                                                }
                                            }
                                        } else {
                                            if insn & 0x001000 == 0 {
                                                if insn & 0x20000000 == 0 {
                                                    if insn & 0xbff8fc00 == 0xf00e400 {
                                                        return Some (MOVI_Vd_V_8B_SIMD_IMM_SFT_LSL :: make_opcode (insn)) ;
                                                    }
                                                    if insn & 0xbf90fc00 == 0xf10e400 {
                                                        return Some(
                                                            SCVTF_Vd_Vn_IMM_VLSR::make_opcode(insn),
                                                        );
                                                    }
                                                    if insn & 0xbf80fc00 == 0xf00e400 {
                                                        return Some (SCVTF_Vd_V_2S_Vn_V_2S_IMM_VLSR_V_2S :: make_opcode (insn)) ;
                                                    }
                                                } else {
                                                    if insn & 0xfff8fc00 == 0x2f00e400 {
                                                        return Some(
                                                            MOVI_Sd_SIMD_IMM::make_opcode(insn),
                                                        );
                                                    }
                                                    if insn & 0xfff8fc00 == 0x6f00e400 {
                                                        return Some(
                                                            MOVI_Vd_SIMD_IMM::make_opcode(insn),
                                                        );
                                                    }
                                                    if insn & 0xbf90fc00 == 0x2f10e400 {
                                                        return Some(
                                                            UCVTF_Vd_Vn_IMM_VLSR::make_opcode(insn),
                                                        );
                                                    }
                                                    if insn & 0xbf80fc00 == 0x2f00e400 {
                                                        return Some (UCVTF_Vd_V_2S_Vn_V_2S_IMM_VLSR_V_2S :: make_opcode (insn)) ;
                                                    }
                                                }
                                            } else {
                                                if insn & 0x20000000 == 0 {
                                                    if insn & 0xbff8fc00 == 0xf00f400 {
                                                        return Some(
                                                            FMOV_Vd_SIMD_FPIMM::make_opcode(insn),
                                                        );
                                                    }
                                                } else {
                                                    if insn & 0xfff8fc00 == 0x6f00f400 {
                                                        return Some(
                                                            FMOV_Vd_V_2D_SIMD_FPIMM::make_opcode(
                                                                insn,
                                                            ),
                                                        );
                                                    }
                                                }
                                            }
                                        }
                                    }
                                } else {
                                    if insn & 0x001000 == 0 {
                                        if insn & 0x20000000 == 0 {
                                            if insn & 0x40000000 == 0 {
                                                if insn & 0xff80fc00 == 0xf008c00 {
                                                    return Some(
                                                        RSHRN_Vd_Vn_IMM_VLSR::make_opcode(insn),
                                                    );
                                                }
                                            } else {
                                                if insn & 0xff80fc00 == 0x4f008c00 {
                                                    return Some(
                                                        RSHRN2_Vd_Vn_IMM_VLSR::make_opcode(insn),
                                                    );
                                                }
                                            }
                                        } else {
                                            if insn & 0x40000000 == 0 {
                                                if insn & 0xff80fc00 == 0x2f008c00 {
                                                    return Some(
                                                        SQRSHRUN_Vd_Vn_IMM_VLSR::make_opcode(insn),
                                                    );
                                                }
                                            } else {
                                                if insn & 0xff80fc00 == 0x6f008c00 {
                                                    return Some(
                                                        SQRSHRUN2_Vd_Vn_IMM_VLSR::make_opcode(insn),
                                                    );
                                                }
                                            }
                                        }
                                    } else {
                                        if insn & 0x002000 == 0 {
                                            if insn & 0x20000000 == 0 {
                                                if insn & 0x40000000 == 0 {
                                                    if insn & 0xff80fc00 == 0xf009c00 {
                                                        return Some(
                                                            SQRSHRN_Vd_Vn_IMM_VLSR::make_opcode(
                                                                insn,
                                                            ),
                                                        );
                                                    }
                                                } else {
                                                    if insn & 0xff80fc00 == 0x4f009c00 {
                                                        return Some(
                                                            SQRSHRN2_Vd_Vn_IMM_VLSR::make_opcode(
                                                                insn,
                                                            ),
                                                        );
                                                    }
                                                }
                                            } else {
                                                if insn & 0x40000000 == 0 {
                                                    if insn & 0xff80fc00 == 0x2f009c00 {
                                                        return Some(
                                                            UQRSHRN_Vd_Vn_IMM_VLSR::make_opcode(
                                                                insn,
                                                            ),
                                                        );
                                                    }
                                                } else {
                                                    if insn & 0xff80fc00 == 0x6f009c00 {
                                                        return Some(
                                                            UQRSHRN2_Vd_Vn_IMM_VLSR::make_opcode(
                                                                insn,
                                                            ),
                                                        );
                                                    }
                                                }
                                            }
                                        } else {
                                            if insn & 0x20000000 == 0 {
                                                if insn & 0xbff8fc00 == 0xf00fc00 {
                                                    return Some(
                                                        FMOV_Vd_V_4H_SIMD_FPIMM::make_opcode(insn),
                                                    );
                                                }
                                                if insn & 0xbf90fc00 == 0xf10fc00 {
                                                    return Some(
                                                        FCVTZS_Vd_Vn_IMM_VLSR::make_opcode(insn),
                                                    );
                                                }
                                                if insn & 0xbf80fc00 == 0xf00fc00 {
                                                    return Some (FCVTZS_Vd_V_2S_Vn_V_2S_IMM_VLSR_V_2S :: make_opcode (insn)) ;
                                                }
                                            } else {
                                                if insn & 0xbf90fc00 == 0x2f10fc00 {
                                                    return Some(
                                                        FCVTZU_Vd_Vn_IMM_VLSR::make_opcode(insn),
                                                    );
                                                }
                                                if insn & 0xbf80fc00 == 0x2f00fc00 {
                                                    return Some (FCVTZU_Vd_V_2S_Vn_V_2S_IMM_VLSR_V_2S :: make_opcode (insn)) ;
                                                }
                                            }
                                        }
                                    }
                                }
                            }
                        } else {
                            if insn & 0x20000000 == 0 {
                                if insn & 0x40000000 == 0 {
                                    if insn & 0x200000 == 0 {
                                        if insn & 0xffe08000 == 0x1fc08000 {
                                            return Some(FMSUB_Fd_Fn_Fm_Fa::make_opcode(insn));
                                        }
                                        if insn & 0xff208000 == 0x1f008000 {
                                            return Some(
                                                FMSUB_Fd_S_S_Fn_S_S_Fm_S_S_Fa_S_S::make_opcode(
                                                    insn,
                                                ),
                                            );
                                        }
                                    } else {
                                        if insn & 0xffe08000 == 0x1fe08000 {
                                            return Some(FNMSUB_Fd_Fn_Fm_Fa::make_opcode(insn));
                                        }
                                        if insn & 0xff208000 == 0x1f208000 {
                                            return Some(
                                                FNMSUB_Fd_S_S_Fn_S_S_Fm_S_S_Fa_S_S::make_opcode(
                                                    insn,
                                                ),
                                            );
                                        }
                                    }
                                } else {
                                    if insn & 0x000400 == 0 {
                                        if insn & 0x001000 == 0 {
                                            if insn & 0xff00f400 == 0x5f00c000 {
                                                return Some(SQDMULH_Sd_Sn_Em16::make_opcode(insn));
                                            }
                                        } else {
                                            if insn & 0x002000 == 0 {
                                                if insn & 0x004000 == 0 {
                                                    if insn & 0x800000 == 0 {
                                                        if insn & 0xffc0f400 == 0x5f009000 {
                                                            return Some(
                                                                FMUL_Sd_Sn_Em16::make_opcode(insn),
                                                            );
                                                        }
                                                    } else {
                                                        if insn & 0xff80f400 == 0x5f809000 {
                                                            return Some(
                                                                FMUL_Sd_Sn_Em::make_opcode(insn),
                                                            );
                                                        }
                                                    }
                                                } else {
                                                    if insn & 0xff00f400 == 0x5f00d000 {
                                                        return Some(
                                                            SQRDMULH_Sd_Sn_Em16::make_opcode(insn),
                                                        );
                                                    }
                                                }
                                            } else {
                                                if insn & 0xff00f400 == 0x5f00b000 {
                                                    return Some(SQDMULL_Sd_Sn_Em16::make_opcode(
                                                        insn,
                                                    ));
                                                }
                                            }
                                        }
                                    } else {
                                        if insn & 0x000800 == 0 {
                                            if insn & 0x001000 == 0 {
                                                if insn & 0xff90fc00 == 0x5f10e400 {
                                                    return Some(
                                                        SCVTF_Sd_Sn_IMM_VLSR::make_opcode(insn),
                                                    );
                                                }
                                                if insn & 0xff80fc00 == 0x5f00e400 {
                                                    return Some (SCVTF_Sd_S_S_Sn_S_S_IMM_VLSR_S_S :: make_opcode (insn)) ;
                                                }
                                            } else {
                                                if insn & 0xff80fc00 == 0x5f009400 {
                                                    return Some(
                                                        SQSHRN_Sd_Sn_IMM_VLSR::make_opcode(insn),
                                                    );
                                                }
                                            }
                                        } else {
                                            if insn & 0x002000 == 0 {
                                                if insn & 0xff80fc00 == 0x5f009c00 {
                                                    return Some(
                                                        SQRSHRN_Sd_Sn_IMM_VLSR::make_opcode(insn),
                                                    );
                                                }
                                            } else {
                                                if insn & 0xff90fc00 == 0x5f10fc00 {
                                                    return Some(
                                                        FCVTZS_Sd_Sn_IMM_VLSR::make_opcode(insn),
                                                    );
                                                }
                                                if insn & 0xff80fc00 == 0x5f00fc00 {
                                                    return Some (FCVTZS_Sd_S_S_Sn_S_S_IMM_VLSR_S_S :: make_opcode (insn)) ;
                                                }
                                            }
                                        }
                                    }
                                }
                            } else {
                                if insn & 0x000400 == 0 {
                                    if insn & 0x002000 == 0 {
                                        if insn & 0x004000 == 0 {
                                            if insn & 0x800000 == 0 {
                                                if insn & 0xffc0f400 == 0x7f009000 {
                                                    return Some(FMULX_Sd_Sn_Em16::make_opcode(
                                                        insn,
                                                    ));
                                                }
                                            } else {
                                                if insn & 0xff80f400 == 0x7f809000 {
                                                    return Some(FMULX_Sd_Sn_Em::make_opcode(insn));
                                                }
                                            }
                                        } else {
                                            if insn & 0xff00f400 == 0x7f00d000 {
                                                return Some(SQRDMLAH_Sd_Sn_Em16::make_opcode(
                                                    insn,
                                                ));
                                            }
                                        }
                                    } else {
                                        if insn & 0xff00f400 == 0x7f00f000 {
                                            return Some(SQRDMLSH_Sd_Sn_Em16::make_opcode(insn));
                                        }
                                    }
                                } else {
                                    if insn & 0x000800 == 0 {
                                        if insn & 0x001000 == 0 {
                                            if insn & 0x002000 == 0 {
                                                if insn & 0xff80fc00 == 0x7f008400 {
                                                    return Some(
                                                        SQSHRUN_Sd_Sn_IMM_VLSR::make_opcode(insn),
                                                    );
                                                }
                                            } else {
                                                if insn & 0xff90fc00 == 0x7f10e400 {
                                                    return Some(
                                                        UCVTF_Sd_Sn_IMM_VLSR::make_opcode(insn),
                                                    );
                                                }
                                                if insn & 0xff80fc00 == 0x7f00e400 {
                                                    return Some (UCVTF_Sd_S_S_Sn_S_S_IMM_VLSR_S_S :: make_opcode (insn)) ;
                                                }
                                            }
                                        } else {
                                            if insn & 0xff80fc00 == 0x7f009400 {
                                                return Some(UQSHRN_Sd_Sn_IMM_VLSR::make_opcode(
                                                    insn,
                                                ));
                                            }
                                        }
                                    } else {
                                        if insn & 0x001000 == 0 {
                                            if insn & 0xff80fc00 == 0x7f008c00 {
                                                return Some(SQRSHRUN_Sd_Sn_IMM_VLSR::make_opcode(
                                                    insn,
                                                ));
                                            }
                                        } else {
                                            if insn & 0x002000 == 0 {
                                                if insn & 0xff80fc00 == 0x7f009c00 {
                                                    return Some(
                                                        UQRSHRN_Sd_Sn_IMM_VLSR::make_opcode(insn),
                                                    );
                                                }
                                            } else {
                                                if insn & 0xff90fc00 == 0x7f10fc00 {
                                                    return Some(
                                                        FCVTZU_Sd_Sn_IMM_VLSR::make_opcode(insn),
                                                    );
                                                }
                                                if insn & 0xff80fc00 == 0x7f00fc00 {
                                                    return Some (FCVTZU_Sd_S_S_Sn_S_S_IMM_VLSR_S_S :: make_opcode (insn)) ;
                                                }
                                            }
                                        }
                                    }
                                }
                            }
                        }
                    }
                }
            }
        }
    }
    None
}
