################################################################################
# Autogenerated by build_tools/bazel_to_cmake/bazel_to_cmake.py from           #
# runtime/src/iree/builtins/ukernel/arch/x86_64/BUILD.bazel                    #
#                                                                              #
# Use iree_cmake_extra_content from iree/build_defs.oss.bzl to add arbitrary   #
# CMake-only content.                                                          #
#                                                                              #
# To disable autogeneration for this file entirely, delete this header.        #
################################################################################

iree_add_all_subdirs()

iree_compiler_targeting_iree_arch(_IREE_UKERNEL_BITCODE_BUILD_X86_64 "x86_64")
if(_IREE_UKERNEL_BITCODE_BUILD_X86_64)

iree_bitcode_library(
  NAME
    ukernel_bitcode_x86_64_entry_points
  ARCH
    wasm_64
  SRCS
    "mmt4d_x86_64_entry_point.c"
    "pack_x86_64_entry_point.c"
    "query_tile_sizes_x86_64_entry_point.c"
    "unpack_x86_64_entry_point.c"
)

iree_bitcode_library(
  NAME
    ukernel_bitcode_x86_64_avx2_fma
  ARCH
    x86_64
  SRCS
    "mmt4d_x86_64_avx2_fma.c"
    "pack_x86_64_avx2_fma.c"
    "unpack_x86_64_avx2_fma.c"
  COPTS
    "-mavx"
    "-mavx2"
    "-mfma"
    "-mf16c"
)

iree_bitcode_library(
  NAME
    ukernel_bitcode_x86_64_avx512_base
  ARCH
    x86_64
  SRCS
    "mmt4d_x86_64_avx512_base.c"
    "pack_x86_64_avx512_base.c"
    "unpack_x86_64_avx512_base.c"
  COPTS
    "-mavx"
    "-mavx2"
    "-mfma"
    "-mf16c"
    "-mavx512f"
    "-mavx512vl"
    "-mavx512cd"
    "-mavx512bw"
    "-mavx512dq"
)

iree_bitcode_library(
  NAME
    ukernel_bitcode_x86_64_avx512_vnni
  ARCH
    x86_64
  SRCS
    "mmt4d_x86_64_avx512_vnni.c"
  COPTS
    "-mavx"
    "-mavx2"
    "-mfma"
    "-mf16c"
    "-mavx512f"
    "-mavx512vl"
    "-mavx512cd"
    "-mavx512bw"
    "-mavx512dq"
    "-mavx512vnni"
)

iree_bitcode_library(
  NAME
    ukernel_bitcode_x86_64_avx512_bf16
  ARCH
    x86_64
  SRCS
    "mmt4d_x86_64_avx512_bf16.c"
  COPTS
    "-mavx"
    "-mavx2"
    "-mfma"
    "-mf16c"
    "-mavx512f"
    "-mavx512vl"
    "-mavx512cd"
    "-mavx512bw"
    "-mavx512dq"
    "-mavx512bf16"
)

iree_link_bitcode(
  NAME
    ukernel_bitcode_x86_64
  SRCS
    "ukernel_bitcode_x86_64_avx2_fma.bc"
    "ukernel_bitcode_x86_64_avx512_base.bc"
    "ukernel_bitcode_x86_64_avx512_bf16.bc"
    "ukernel_bitcode_x86_64_avx512_vnni.bc"

)

elseif(IREE_BUILD_COMPILER AND IREE_TARGET_BACKEND_LLVM_CPU)
iree_make_empty_file("${CMAKE_CURRENT_BINARY_DIR}/ukernel_bitcode_x86_64.bc")
iree_make_empty_file("${CMAKE_CURRENT_BINARY_DIR}/ukernel_bitcode_x86_64_entry_points.bc")
endif()  # _IREE_UKERNEL_BITCODE_BUILD_X86_64

### BAZEL_TO_CMAKE_PRESERVES_ALL_CONTENT_BELOW_THIS_LINE ###

if (NOT (IREE_ARCH STREQUAL "x86_64"))
  return()
endif()

# Target CPUs supporting AVX2+FMA3. That includes Intel Haswell (2013) and newer
# and AMD Excavator (2015) and newer. There is no current plan to look after
# SIMD performance on x86 microarchitectures not supporting this.
iree_select_compiler_opts(IREE_UK_COPTS_X86_64_AVX2_FMA
  CLANG_OR_GCC
    "-mavx2"
    "-mfma"
    "-mf16c"
  MSVC
    "/arch:AVX2"
)

# TODO: Support AVX-VNNI and/or AVX-VNNI-INT8?
# 1. AVX-VNNI is the 256-bit backport of AVX-512-VNNI. It is supported in Alder
#    Lake (2022).
# 2  AVX-VNNI-INT8 is a future ISA extension not yet mentioned in the Intel SDM,
#    but we can glean the following information from these links: it will be
#    supported in Sierra Forest (2024) it will introduce VPDPBSSD, the missing
#    signed*signed counterpart to VNNI's VPDPBUSD, meaning we will finally be
#    able to use the 8bit path, so that VNNI-IN8 will be a >= 2x win for us over
#    VNNI.
#    https://en.wikipedia.org/wiki/Sierra_Forest
#    https://gcc.gnu.org/pipermail/gcc-patches/2022-October/603546.html
#    https://gcc.gnu.org/git/?p=gcc.git;a=commitdiff;h=406675947d26ccbc2108e9689a2918bb36f61a63


# Target CPUs supporting the typical baseline AVX-512 features (F+VL+CD+BW+DQ).
# That includes Intel Skylake/server (2017) and AMD Zen4 (2022) while recent
# non-server x86 microarchitectures not supporting this continue to exist.
iree_select_compiler_opts(IREE_UK_COPTS_X86_64_AVX512_BASE
  CLANG_OR_GCC
    "-mavx512f"
    "-mavx512vl"
    "-mavx512cd"
    "-mavx512bw"
    "-mavx512dq"
  MSVC
    "/arch:AVX512"
)

# Target CPUs supporting AVX-512-VNNI. That includes Intel Cascade
# Lake (2019) and newer, and AMD Zen4 (2022).
iree_select_compiler_opts(IREE_UK_COPTS_X86_64_AVX512_VNNI_RELATIVE
  CLANG_OR_GCC
    "-mavx512vnni"
  MSVC
)
set(IREE_UK_COPTS_X86_64_AVX512_VNNI
  "${IREE_UK_COPTS_X86_64_AVX512_BASE}"
  "${IREE_UK_COPTS_X86_64_AVX512_VNNI_RELATIVE}"
)

# Target CPUs supporting AVX-512-BF16 feature. That includes Intel Cooper
# Lake (2020) and newer, and AMD Zen4 (2022).
iree_select_compiler_opts(IREE_UK_COPTS_X86_64_AVX512_BF16_RELATIVE
  CLANG_OR_GCC
    "-mavx512bf16"
  MSVC
)
set(IREE_UK_COPTS_X86_64_AVX512_BF16
  "${IREE_UK_COPTS_X86_64_AVX512_BASE}"
  "${IREE_UK_COPTS_X86_64_AVX512_BF16_RELATIVE}"
)

if ((CMAKE_C_COMPILER_ID STREQUAL GNU) AND
    (CMAKE_C_COMPILER_VERSION VERSION_LESS 12))
# Old GCC versions have incompatible x86 intrinsics. Supporting them
# is not considered worth it. By not defining these tokens, we leave these
# code paths out. At least GCC 9 is known to be problematic, while GCC 12 is
# known working, so the current test is based on that.
else()
check_cxx_compiler_flag("${IREE_UK_COPTS_X86_64_AVX2_FMA}" IREE_UK_BUILD_X86_64_AVX2_FMA)
check_cxx_compiler_flag("${IREE_UK_COPTS_X86_64_AVX512_BASE}" IREE_UK_BUILD_X86_64_AVX512_BASE)
check_cxx_compiler_flag("${IREE_UK_COPTS_X86_64_AVX512_VNNI}" IREE_UK_BUILD_X86_64_AVX512_VNNI)
check_cxx_compiler_flag("${IREE_UK_COPTS_X86_64_AVX512_BF16}" IREE_UK_BUILD_X86_64_AVX512_BF16)
endif()

configure_file("config_x86_64.h.in" "config_x86_64.h")

iree_cc_library(
  NAME
    common_x86_64
  HDRS
    "common_x86_64.h"
  DEPS
    iree::builtins::ukernel::internal_headers
    iree::schemas::cpu_data
)

set(IREE_UK_X86_64_DEPS "")

if(IREE_UK_BUILD_X86_64_AVX2_FMA)
iree_cc_library(
  NAME
    x86_64_avx2_fma
  SRCS
    "mmt4d_x86_64_avx2_fma.c"
    "pack_x86_64_avx2_fma.c"
    "unpack_x86_64_avx2_fma.c"
  COPTS
    "${IREE_UK_COPTS_X86_64_AVX2_FMA}"
  DEPS
    iree::builtins::ukernel::internal_headers
)
list(APPEND IREE_UK_X86_64_DEPS "::x86_64_avx2_fma")
endif()  # IREE_UK_BUILD_X86_64_AVX2_FMA

if(IREE_UK_BUILD_X86_64_AVX512_BASE)
iree_cc_library(
  NAME
    x86_64_avx512_base
  SRCS
    "mmt4d_x86_64_avx512_base.c"
    "pack_x86_64_avx512_base.c"
    "unpack_x86_64_avx512_base.c"
  COPTS
    "${IREE_UK_COPTS_X86_64_AVX512_BASE}"
  DEPS
    iree::builtins::ukernel::internal_headers
)
list(APPEND IREE_UK_X86_64_DEPS "::x86_64_avx512_base")
endif()  # IREE_UK_BUILD_X86_64_AVX512_BASE

if(IREE_UK_BUILD_X86_64_AVX512_VNNI)
iree_cc_library(
  NAME
    x86_64_avx512_vnni
  SRCS
    "mmt4d_x86_64_avx512_vnni.c"
  COPTS
    "${IREE_UK_COPTS_X86_64_AVX512_VNNI}"
  DEPS
    iree::builtins::ukernel::internal_headers
)
list(APPEND IREE_UK_X86_64_DEPS "::x86_64_avx512_vnni")
endif()  # IREE_UK_BUILD_X86_64_AVX512_VNNI

if(IREE_UK_BUILD_X86_64_AVX512_BF16)
iree_cc_library(
  NAME
    x86_64_avx512_bf16
  SRCS
    "mmt4d_x86_64_avx512_bf16.c"
  COPTS
    "${IREE_UK_COPTS_X86_64_AVX512_BF16}"
  DEPS
    iree::builtins::ukernel::internal_headers
)
list(APPEND IREE_UK_X86_64_DEPS "::x86_64_avx512_bf16")
endif()  # IREE_UK_BUILD_X86_64_AVX512_BF16

iree_cc_library(
  NAME
    x86_64
  SRCS
    "mmt4d_x86_64_entry_point.c"
    "pack_x86_64_entry_point.c"
    "query_tile_sizes_x86_64_entry_point.c"
    "unpack_x86_64_entry_point.c"
  DEPS
    ::common_x86_64
    iree::base::core_headers
    iree::builtins::ukernel::internal_headers
    ${IREE_UK_X86_64_DEPS}
  PUBLIC
)

set(IREE_UK_ARCH_DEPS "iree::builtins::ukernel::arch::x86_64" PARENT_SCOPE)
