#[doc = "Register `EVT_ST2_CLR` writer"]
pub type W = crate::W<EVT_ST2_CLR_SPEC>;
#[doc = "Field `MCPWM0_EVT_OP2_TEA_ST_CLR` writer - Configures whether or not to clear MCPWM0_evt_op2_tea trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
pub type MCPWM0_EVT_OP2_TEA_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MCPWM0_EVT_OP0_TEB_ST_CLR` writer - Configures whether or not to clear MCPWM0_evt_op0_teb trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
pub type MCPWM0_EVT_OP0_TEB_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MCPWM0_EVT_OP1_TEB_ST_CLR` writer - Configures whether or not to clear MCPWM0_evt_op1_teb trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
pub type MCPWM0_EVT_OP1_TEB_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MCPWM0_EVT_OP2_TEB_ST_CLR` writer - Configures whether or not to clear MCPWM0_evt_op2_teb trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
pub type MCPWM0_EVT_OP2_TEB_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MCPWM0_EVT_F0_ST_CLR` writer - Configures whether or not to clear MCPWM0_evt_f0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
pub type MCPWM0_EVT_F0_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MCPWM0_EVT_F1_ST_CLR` writer - Configures whether or not to clear MCPWM0_evt_f1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
pub type MCPWM0_EVT_F1_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MCPWM0_EVT_F2_ST_CLR` writer - Configures whether or not to clear MCPWM0_evt_f2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
pub type MCPWM0_EVT_F2_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MCPWM0_EVT_F0_CLR_ST_CLR` writer - Configures whether or not to clear MCPWM0_evt_f0_clr trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
pub type MCPWM0_EVT_F0_CLR_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MCPWM0_EVT_F1_CLR_ST_CLR` writer - Configures whether or not to clear MCPWM0_evt_f1_clr trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
pub type MCPWM0_EVT_F1_CLR_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MCPWM0_EVT_F2_CLR_ST_CLR` writer - Configures whether or not to clear MCPWM0_evt_f2_clr trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
pub type MCPWM0_EVT_F2_CLR_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MCPWM0_EVT_TZ0_CBC_ST_CLR` writer - Configures whether or not to clear MCPWM0_evt_tz0_cbc trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
pub type MCPWM0_EVT_TZ0_CBC_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MCPWM0_EVT_TZ1_CBC_ST_CLR` writer - Configures whether or not to clear MCPWM0_evt_tz1_cbc trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
pub type MCPWM0_EVT_TZ1_CBC_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MCPWM0_EVT_TZ2_CBC_ST_CLR` writer - Configures whether or not to clear MCPWM0_evt_tz2_cbc trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
pub type MCPWM0_EVT_TZ2_CBC_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MCPWM0_EVT_TZ0_OST_ST_CLR` writer - Configures whether or not to clear MCPWM0_evt_tz0_ost trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
pub type MCPWM0_EVT_TZ0_OST_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MCPWM0_EVT_TZ1_OST_ST_CLR` writer - Configures whether or not to clear MCPWM0_evt_tz1_ost trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
pub type MCPWM0_EVT_TZ1_OST_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MCPWM0_EVT_TZ2_OST_ST_CLR` writer - Configures whether or not to clear MCPWM0_evt_tz2_ost trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
pub type MCPWM0_EVT_TZ2_OST_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MCPWM0_EVT_CAP0_ST_CLR` writer - Configures whether or not to clear MCPWM0_evt_cap0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
pub type MCPWM0_EVT_CAP0_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MCPWM0_EVT_CAP1_ST_CLR` writer - Configures whether or not to clear MCPWM0_evt_cap1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
pub type MCPWM0_EVT_CAP1_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MCPWM0_EVT_CAP2_ST_CLR` writer - Configures whether or not to clear MCPWM0_evt_cap2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
pub type MCPWM0_EVT_CAP2_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MCPWM0_EVT_OP0_TEE1_ST_CLR` writer - Configures whether or not to clear MCPWM0_evt_op0_tee1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
pub type MCPWM0_EVT_OP0_TEE1_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MCPWM0_EVT_OP1_TEE1_ST_CLR` writer - Configures whether or not to clear MCPWM0_evt_op1_tee1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
pub type MCPWM0_EVT_OP1_TEE1_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MCPWM0_EVT_OP2_TEE1_ST_CLR` writer - Configures whether or not to clear MCPWM0_evt_op2_tee1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
pub type MCPWM0_EVT_OP2_TEE1_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MCPWM0_EVT_OP0_TEE2_ST_CLR` writer - Configures whether or not to clear MCPWM0_evt_op0_tee2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
pub type MCPWM0_EVT_OP0_TEE2_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MCPWM0_EVT_OP1_TEE2_ST_CLR` writer - Configures whether or not to clear MCPWM0_evt_op1_tee2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
pub type MCPWM0_EVT_OP1_TEE2_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MCPWM0_EVT_OP2_TEE2_ST_CLR` writer - Configures whether or not to clear MCPWM0_evt_op2_tee2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
pub type MCPWM0_EVT_OP2_TEE2_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC_EVT_CONV_CMPLT0_ST_CLR` writer - Configures whether or not to clear ADC_evt_conv_cmplt0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
pub type ADC_EVT_CONV_CMPLT0_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC_EVT_EQ_ABOVE_THRESH0_ST_CLR` writer - Configures whether or not to clear ADC_evt_eq_above_thresh0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
pub type ADC_EVT_EQ_ABOVE_THRESH0_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC_EVT_EQ_ABOVE_THRESH1_ST_CLR` writer - Configures whether or not to clear ADC_evt_eq_above_thresh1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
pub type ADC_EVT_EQ_ABOVE_THRESH1_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC_EVT_EQ_BELOW_THRESH0_ST_CLR` writer - Configures whether or not to clear ADC_evt_eq_below_thresh0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
pub type ADC_EVT_EQ_BELOW_THRESH0_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC_EVT_EQ_BELOW_THRESH1_ST_CLR` writer - Configures whether or not to clear ADC_evt_eq_below_thresh1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
pub type ADC_EVT_EQ_BELOW_THRESH1_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC_EVT_RESULT_DONE0_ST_CLR` writer - Configures whether or not to clear ADC_evt_result_done0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
pub type ADC_EVT_RESULT_DONE0_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC_EVT_STOPPED0_ST_CLR` writer - Configures whether or not to clear ADC_evt_stopped0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
pub type ADC_EVT_STOPPED0_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for crate::generic::Reg<EVT_ST2_CLR_SPEC> {
    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
        write!(f, "(not readable)")
    }
}
impl W {
    #[doc = "Bit 0 - Configures whether or not to clear MCPWM0_evt_op2_tea trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
    #[inline(always)]
    pub fn mcpwm0_evt_op2_tea_st_clr(
        &mut self,
    ) -> MCPWM0_EVT_OP2_TEA_ST_CLR_W<'_, EVT_ST2_CLR_SPEC> {
        MCPWM0_EVT_OP2_TEA_ST_CLR_W::new(self, 0)
    }
    #[doc = "Bit 1 - Configures whether or not to clear MCPWM0_evt_op0_teb trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
    #[inline(always)]
    pub fn mcpwm0_evt_op0_teb_st_clr(
        &mut self,
    ) -> MCPWM0_EVT_OP0_TEB_ST_CLR_W<'_, EVT_ST2_CLR_SPEC> {
        MCPWM0_EVT_OP0_TEB_ST_CLR_W::new(self, 1)
    }
    #[doc = "Bit 2 - Configures whether or not to clear MCPWM0_evt_op1_teb trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
    #[inline(always)]
    pub fn mcpwm0_evt_op1_teb_st_clr(
        &mut self,
    ) -> MCPWM0_EVT_OP1_TEB_ST_CLR_W<'_, EVT_ST2_CLR_SPEC> {
        MCPWM0_EVT_OP1_TEB_ST_CLR_W::new(self, 2)
    }
    #[doc = "Bit 3 - Configures whether or not to clear MCPWM0_evt_op2_teb trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
    #[inline(always)]
    pub fn mcpwm0_evt_op2_teb_st_clr(
        &mut self,
    ) -> MCPWM0_EVT_OP2_TEB_ST_CLR_W<'_, EVT_ST2_CLR_SPEC> {
        MCPWM0_EVT_OP2_TEB_ST_CLR_W::new(self, 3)
    }
    #[doc = "Bit 4 - Configures whether or not to clear MCPWM0_evt_f0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
    #[inline(always)]
    pub fn mcpwm0_evt_f0_st_clr(&mut self) -> MCPWM0_EVT_F0_ST_CLR_W<'_, EVT_ST2_CLR_SPEC> {
        MCPWM0_EVT_F0_ST_CLR_W::new(self, 4)
    }
    #[doc = "Bit 5 - Configures whether or not to clear MCPWM0_evt_f1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
    #[inline(always)]
    pub fn mcpwm0_evt_f1_st_clr(&mut self) -> MCPWM0_EVT_F1_ST_CLR_W<'_, EVT_ST2_CLR_SPEC> {
        MCPWM0_EVT_F1_ST_CLR_W::new(self, 5)
    }
    #[doc = "Bit 6 - Configures whether or not to clear MCPWM0_evt_f2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
    #[inline(always)]
    pub fn mcpwm0_evt_f2_st_clr(&mut self) -> MCPWM0_EVT_F2_ST_CLR_W<'_, EVT_ST2_CLR_SPEC> {
        MCPWM0_EVT_F2_ST_CLR_W::new(self, 6)
    }
    #[doc = "Bit 7 - Configures whether or not to clear MCPWM0_evt_f0_clr trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
    #[inline(always)]
    pub fn mcpwm0_evt_f0_clr_st_clr(&mut self) -> MCPWM0_EVT_F0_CLR_ST_CLR_W<'_, EVT_ST2_CLR_SPEC> {
        MCPWM0_EVT_F0_CLR_ST_CLR_W::new(self, 7)
    }
    #[doc = "Bit 8 - Configures whether or not to clear MCPWM0_evt_f1_clr trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
    #[inline(always)]
    pub fn mcpwm0_evt_f1_clr_st_clr(&mut self) -> MCPWM0_EVT_F1_CLR_ST_CLR_W<'_, EVT_ST2_CLR_SPEC> {
        MCPWM0_EVT_F1_CLR_ST_CLR_W::new(self, 8)
    }
    #[doc = "Bit 9 - Configures whether or not to clear MCPWM0_evt_f2_clr trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
    #[inline(always)]
    pub fn mcpwm0_evt_f2_clr_st_clr(&mut self) -> MCPWM0_EVT_F2_CLR_ST_CLR_W<'_, EVT_ST2_CLR_SPEC> {
        MCPWM0_EVT_F2_CLR_ST_CLR_W::new(self, 9)
    }
    #[doc = "Bit 10 - Configures whether or not to clear MCPWM0_evt_tz0_cbc trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
    #[inline(always)]
    pub fn mcpwm0_evt_tz0_cbc_st_clr(
        &mut self,
    ) -> MCPWM0_EVT_TZ0_CBC_ST_CLR_W<'_, EVT_ST2_CLR_SPEC> {
        MCPWM0_EVT_TZ0_CBC_ST_CLR_W::new(self, 10)
    }
    #[doc = "Bit 11 - Configures whether or not to clear MCPWM0_evt_tz1_cbc trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
    #[inline(always)]
    pub fn mcpwm0_evt_tz1_cbc_st_clr(
        &mut self,
    ) -> MCPWM0_EVT_TZ1_CBC_ST_CLR_W<'_, EVT_ST2_CLR_SPEC> {
        MCPWM0_EVT_TZ1_CBC_ST_CLR_W::new(self, 11)
    }
    #[doc = "Bit 12 - Configures whether or not to clear MCPWM0_evt_tz2_cbc trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
    #[inline(always)]
    pub fn mcpwm0_evt_tz2_cbc_st_clr(
        &mut self,
    ) -> MCPWM0_EVT_TZ2_CBC_ST_CLR_W<'_, EVT_ST2_CLR_SPEC> {
        MCPWM0_EVT_TZ2_CBC_ST_CLR_W::new(self, 12)
    }
    #[doc = "Bit 13 - Configures whether or not to clear MCPWM0_evt_tz0_ost trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
    #[inline(always)]
    pub fn mcpwm0_evt_tz0_ost_st_clr(
        &mut self,
    ) -> MCPWM0_EVT_TZ0_OST_ST_CLR_W<'_, EVT_ST2_CLR_SPEC> {
        MCPWM0_EVT_TZ0_OST_ST_CLR_W::new(self, 13)
    }
    #[doc = "Bit 14 - Configures whether or not to clear MCPWM0_evt_tz1_ost trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
    #[inline(always)]
    pub fn mcpwm0_evt_tz1_ost_st_clr(
        &mut self,
    ) -> MCPWM0_EVT_TZ1_OST_ST_CLR_W<'_, EVT_ST2_CLR_SPEC> {
        MCPWM0_EVT_TZ1_OST_ST_CLR_W::new(self, 14)
    }
    #[doc = "Bit 15 - Configures whether or not to clear MCPWM0_evt_tz2_ost trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
    #[inline(always)]
    pub fn mcpwm0_evt_tz2_ost_st_clr(
        &mut self,
    ) -> MCPWM0_EVT_TZ2_OST_ST_CLR_W<'_, EVT_ST2_CLR_SPEC> {
        MCPWM0_EVT_TZ2_OST_ST_CLR_W::new(self, 15)
    }
    #[doc = "Bit 16 - Configures whether or not to clear MCPWM0_evt_cap0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
    #[inline(always)]
    pub fn mcpwm0_evt_cap0_st_clr(&mut self) -> MCPWM0_EVT_CAP0_ST_CLR_W<'_, EVT_ST2_CLR_SPEC> {
        MCPWM0_EVT_CAP0_ST_CLR_W::new(self, 16)
    }
    #[doc = "Bit 17 - Configures whether or not to clear MCPWM0_evt_cap1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
    #[inline(always)]
    pub fn mcpwm0_evt_cap1_st_clr(&mut self) -> MCPWM0_EVT_CAP1_ST_CLR_W<'_, EVT_ST2_CLR_SPEC> {
        MCPWM0_EVT_CAP1_ST_CLR_W::new(self, 17)
    }
    #[doc = "Bit 18 - Configures whether or not to clear MCPWM0_evt_cap2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
    #[inline(always)]
    pub fn mcpwm0_evt_cap2_st_clr(&mut self) -> MCPWM0_EVT_CAP2_ST_CLR_W<'_, EVT_ST2_CLR_SPEC> {
        MCPWM0_EVT_CAP2_ST_CLR_W::new(self, 18)
    }
    #[doc = "Bit 19 - Configures whether or not to clear MCPWM0_evt_op0_tee1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
    #[inline(always)]
    pub fn mcpwm0_evt_op0_tee1_st_clr(
        &mut self,
    ) -> MCPWM0_EVT_OP0_TEE1_ST_CLR_W<'_, EVT_ST2_CLR_SPEC> {
        MCPWM0_EVT_OP0_TEE1_ST_CLR_W::new(self, 19)
    }
    #[doc = "Bit 20 - Configures whether or not to clear MCPWM0_evt_op1_tee1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
    #[inline(always)]
    pub fn mcpwm0_evt_op1_tee1_st_clr(
        &mut self,
    ) -> MCPWM0_EVT_OP1_TEE1_ST_CLR_W<'_, EVT_ST2_CLR_SPEC> {
        MCPWM0_EVT_OP1_TEE1_ST_CLR_W::new(self, 20)
    }
    #[doc = "Bit 21 - Configures whether or not to clear MCPWM0_evt_op2_tee1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
    #[inline(always)]
    pub fn mcpwm0_evt_op2_tee1_st_clr(
        &mut self,
    ) -> MCPWM0_EVT_OP2_TEE1_ST_CLR_W<'_, EVT_ST2_CLR_SPEC> {
        MCPWM0_EVT_OP2_TEE1_ST_CLR_W::new(self, 21)
    }
    #[doc = "Bit 22 - Configures whether or not to clear MCPWM0_evt_op0_tee2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
    #[inline(always)]
    pub fn mcpwm0_evt_op0_tee2_st_clr(
        &mut self,
    ) -> MCPWM0_EVT_OP0_TEE2_ST_CLR_W<'_, EVT_ST2_CLR_SPEC> {
        MCPWM0_EVT_OP0_TEE2_ST_CLR_W::new(self, 22)
    }
    #[doc = "Bit 23 - Configures whether or not to clear MCPWM0_evt_op1_tee2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
    #[inline(always)]
    pub fn mcpwm0_evt_op1_tee2_st_clr(
        &mut self,
    ) -> MCPWM0_EVT_OP1_TEE2_ST_CLR_W<'_, EVT_ST2_CLR_SPEC> {
        MCPWM0_EVT_OP1_TEE2_ST_CLR_W::new(self, 23)
    }
    #[doc = "Bit 24 - Configures whether or not to clear MCPWM0_evt_op2_tee2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
    #[inline(always)]
    pub fn mcpwm0_evt_op2_tee2_st_clr(
        &mut self,
    ) -> MCPWM0_EVT_OP2_TEE2_ST_CLR_W<'_, EVT_ST2_CLR_SPEC> {
        MCPWM0_EVT_OP2_TEE2_ST_CLR_W::new(self, 24)
    }
    #[doc = "Bit 25 - Configures whether or not to clear ADC_evt_conv_cmplt0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
    #[inline(always)]
    pub fn adc_evt_conv_cmplt0_st_clr(
        &mut self,
    ) -> ADC_EVT_CONV_CMPLT0_ST_CLR_W<'_, EVT_ST2_CLR_SPEC> {
        ADC_EVT_CONV_CMPLT0_ST_CLR_W::new(self, 25)
    }
    #[doc = "Bit 26 - Configures whether or not to clear ADC_evt_eq_above_thresh0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
    #[inline(always)]
    pub fn adc_evt_eq_above_thresh0_st_clr(
        &mut self,
    ) -> ADC_EVT_EQ_ABOVE_THRESH0_ST_CLR_W<'_, EVT_ST2_CLR_SPEC> {
        ADC_EVT_EQ_ABOVE_THRESH0_ST_CLR_W::new(self, 26)
    }
    #[doc = "Bit 27 - Configures whether or not to clear ADC_evt_eq_above_thresh1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
    #[inline(always)]
    pub fn adc_evt_eq_above_thresh1_st_clr(
        &mut self,
    ) -> ADC_EVT_EQ_ABOVE_THRESH1_ST_CLR_W<'_, EVT_ST2_CLR_SPEC> {
        ADC_EVT_EQ_ABOVE_THRESH1_ST_CLR_W::new(self, 27)
    }
    #[doc = "Bit 28 - Configures whether or not to clear ADC_evt_eq_below_thresh0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
    #[inline(always)]
    pub fn adc_evt_eq_below_thresh0_st_clr(
        &mut self,
    ) -> ADC_EVT_EQ_BELOW_THRESH0_ST_CLR_W<'_, EVT_ST2_CLR_SPEC> {
        ADC_EVT_EQ_BELOW_THRESH0_ST_CLR_W::new(self, 28)
    }
    #[doc = "Bit 29 - Configures whether or not to clear ADC_evt_eq_below_thresh1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
    #[inline(always)]
    pub fn adc_evt_eq_below_thresh1_st_clr(
        &mut self,
    ) -> ADC_EVT_EQ_BELOW_THRESH1_ST_CLR_W<'_, EVT_ST2_CLR_SPEC> {
        ADC_EVT_EQ_BELOW_THRESH1_ST_CLR_W::new(self, 29)
    }
    #[doc = "Bit 30 - Configures whether or not to clear ADC_evt_result_done0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
    #[inline(always)]
    pub fn adc_evt_result_done0_st_clr(
        &mut self,
    ) -> ADC_EVT_RESULT_DONE0_ST_CLR_W<'_, EVT_ST2_CLR_SPEC> {
        ADC_EVT_RESULT_DONE0_ST_CLR_W::new(self, 30)
    }
    #[doc = "Bit 31 - Configures whether or not to clear ADC_evt_stopped0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
    #[inline(always)]
    pub fn adc_evt_stopped0_st_clr(&mut self) -> ADC_EVT_STOPPED0_ST_CLR_W<'_, EVT_ST2_CLR_SPEC> {
        ADC_EVT_STOPPED0_ST_CLR_W::new(self, 31)
    }
}
#[doc = "Events trigger status clear register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`evt_st2_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EVT_ST2_CLR_SPEC;
impl crate::RegisterSpec for EVT_ST2_CLR_SPEC {
    type Ux = u32;
}
#[doc = "`write(|w| ..)` method takes [`evt_st2_clr::W`](W) writer structure"]
impl crate::Writable for EVT_ST2_CLR_SPEC {
    type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets EVT_ST2_CLR to value 0"]
impl crate::Resettable for EVT_ST2_CLR_SPEC {}
