#[repr(C)]
#[cfg_attr(feature = "impl-register-debug", derive(Debug))]
#[doc = "Register block"]
pub struct RegisterBlock {
    bod_mode0_cntl: BOD_MODE0_CNTL,
    bod_mode1_cntl: BOD_MODE1_CNTL,
    ck_glitch_cntl: CK_GLITCH_CNTL,
    fib_enable: FIB_ENABLE,
    int_raw: INT_RAW,
    int_st: INT_ST,
    int_ena: INT_ENA,
    int_clr: INT_CLR,
    lp_int_raw: LP_INT_RAW,
    lp_int_st: LP_INT_ST,
    lp_int_ena: LP_INT_ENA,
    lp_int_clr: LP_INT_CLR,
    _reserved12: [u8; 0x03cc],
    date: DATE,
}
impl RegisterBlock {
    #[doc = "0x00 - Configure brownout mode0"]
    #[inline(always)]
    pub const fn bod_mode0_cntl(&self) -> &BOD_MODE0_CNTL {
        &self.bod_mode0_cntl
    }
    #[doc = "0x04 - Configure brownout mode1"]
    #[inline(always)]
    pub const fn bod_mode1_cntl(&self) -> &BOD_MODE1_CNTL {
        &self.bod_mode1_cntl
    }
    #[doc = "0x08 - Configure power glitch"]
    #[inline(always)]
    pub const fn ck_glitch_cntl(&self) -> &CK_GLITCH_CNTL {
        &self.ck_glitch_cntl
    }
    #[doc = "0x0c - configure FIB REG"]
    #[inline(always)]
    pub const fn fib_enable(&self) -> &FIB_ENABLE {
        &self.fib_enable
    }
    #[doc = "0x10 - interrpt raw register"]
    #[inline(always)]
    pub const fn int_raw(&self) -> &INT_RAW {
        &self.int_raw
    }
    #[doc = "0x14 - interrpt status register"]
    #[inline(always)]
    pub const fn int_st(&self) -> &INT_ST {
        &self.int_st
    }
    #[doc = "0x18 - interrpt enable register"]
    #[inline(always)]
    pub const fn int_ena(&self) -> &INT_ENA {
        &self.int_ena
    }
    #[doc = "0x1c - interrpt clear register"]
    #[inline(always)]
    pub const fn int_clr(&self) -> &INT_CLR {
        &self.int_clr
    }
    #[doc = "0x20 - lp interrupt raw register"]
    #[inline(always)]
    pub const fn lp_int_raw(&self) -> &LP_INT_RAW {
        &self.lp_int_raw
    }
    #[doc = "0x24 - lp interrupt status register"]
    #[inline(always)]
    pub const fn lp_int_st(&self) -> &LP_INT_ST {
        &self.lp_int_st
    }
    #[doc = "0x28 - lp interrupt enable register"]
    #[inline(always)]
    pub const fn lp_int_ena(&self) -> &LP_INT_ENA {
        &self.lp_int_ena
    }
    #[doc = "0x2c - lp interrupt clear register"]
    #[inline(always)]
    pub const fn lp_int_clr(&self) -> &LP_INT_CLR {
        &self.lp_int_clr
    }
    #[doc = "0x3fc - version register"]
    #[inline(always)]
    pub const fn date(&self) -> &DATE {
        &self.date
    }
}
#[doc = "BOD_MODE0_CNTL (rw) register accessor: Configure brownout mode0\n\nYou can [`read`](crate::Reg::read) this register and get [`bod_mode0_cntl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bod_mode0_cntl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bod_mode0_cntl`] module"]
pub type BOD_MODE0_CNTL = crate::Reg<bod_mode0_cntl::BOD_MODE0_CNTL_SPEC>;
#[doc = "Configure brownout mode0"]
pub mod bod_mode0_cntl;
#[doc = "BOD_MODE1_CNTL (rw) register accessor: Configure brownout mode1\n\nYou can [`read`](crate::Reg::read) this register and get [`bod_mode1_cntl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bod_mode1_cntl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bod_mode1_cntl`] module"]
pub type BOD_MODE1_CNTL = crate::Reg<bod_mode1_cntl::BOD_MODE1_CNTL_SPEC>;
#[doc = "Configure brownout mode1"]
pub mod bod_mode1_cntl;
#[doc = "CK_GLITCH_CNTL (rw) register accessor: Configure power glitch\n\nYou can [`read`](crate::Reg::read) this register and get [`ck_glitch_cntl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ck_glitch_cntl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ck_glitch_cntl`] module"]
pub type CK_GLITCH_CNTL = crate::Reg<ck_glitch_cntl::CK_GLITCH_CNTL_SPEC>;
#[doc = "Configure power glitch"]
pub mod ck_glitch_cntl;
#[doc = "FIB_ENABLE (rw) register accessor: configure FIB REG\n\nYou can [`read`](crate::Reg::read) this register and get [`fib_enable::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fib_enable::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fib_enable`] module"]
pub type FIB_ENABLE = crate::Reg<fib_enable::FIB_ENABLE_SPEC>;
#[doc = "configure FIB REG"]
pub mod fib_enable;
#[doc = "INT_RAW (rw) register accessor: interrpt raw register\n\nYou can [`read`](crate::Reg::read) this register and get [`int_raw::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_raw::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_raw`] module"]
pub type INT_RAW = crate::Reg<int_raw::INT_RAW_SPEC>;
#[doc = "interrpt raw register"]
pub mod int_raw;
#[doc = "INT_ST (r) register accessor: interrpt status register\n\nYou can [`read`](crate::Reg::read) this register and get [`int_st::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_st`] module"]
pub type INT_ST = crate::Reg<int_st::INT_ST_SPEC>;
#[doc = "interrpt status register"]
pub mod int_st;
#[doc = "INT_ENA (rw) register accessor: interrpt enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`int_ena::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_ena::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_ena`] module"]
pub type INT_ENA = crate::Reg<int_ena::INT_ENA_SPEC>;
#[doc = "interrpt enable register"]
pub mod int_ena;
#[doc = "INT_CLR (w) register accessor: interrpt clear register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_clr`] module"]
pub type INT_CLR = crate::Reg<int_clr::INT_CLR_SPEC>;
#[doc = "interrpt clear register"]
pub mod int_clr;
#[doc = "LP_INT_RAW (rw) register accessor: lp interrupt raw register\n\nYou can [`read`](crate::Reg::read) this register and get [`lp_int_raw::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lp_int_raw::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_int_raw`] module"]
pub type LP_INT_RAW = crate::Reg<lp_int_raw::LP_INT_RAW_SPEC>;
#[doc = "lp interrupt raw register"]
pub mod lp_int_raw;
#[doc = "LP_INT_ST (r) register accessor: lp interrupt status register\n\nYou can [`read`](crate::Reg::read) this register and get [`lp_int_st::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_int_st`] module"]
pub type LP_INT_ST = crate::Reg<lp_int_st::LP_INT_ST_SPEC>;
#[doc = "lp interrupt status register"]
pub mod lp_int_st;
#[doc = "LP_INT_ENA (rw) register accessor: lp interrupt enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`lp_int_ena::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lp_int_ena::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_int_ena`] module"]
pub type LP_INT_ENA = crate::Reg<lp_int_ena::LP_INT_ENA_SPEC>;
#[doc = "lp interrupt enable register"]
pub mod lp_int_ena;
#[doc = "LP_INT_CLR (w) register accessor: lp interrupt clear register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lp_int_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_int_clr`] module"]
pub type LP_INT_CLR = crate::Reg<lp_int_clr::LP_INT_CLR_SPEC>;
#[doc = "lp interrupt clear register"]
pub mod lp_int_clr;
pub use crate::aes::{date, DATE};
