#[doc = "Register `TASK_ST3` reader"]
pub type R = crate::R<TASK_ST3_SPEC>;
#[doc = "Register `TASK_ST3` writer"]
pub type W = crate::W<TASK_ST3_SPEC>;
#[doc = "Field `TG1_TASK_ALARM_START_TIMER1_ST` reader - Represents TG1_task_alarm_start_timer1 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type TG1_TASK_ALARM_START_TIMER1_ST_R = crate::BitReader;
#[doc = "Field `TG1_TASK_ALARM_START_TIMER1_ST` writer - Represents TG1_task_alarm_start_timer1 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type TG1_TASK_ALARM_START_TIMER1_ST_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TG1_TASK_CNT_STOP_TIMER1_ST` reader - Represents TG1_task_cnt_stop_timer1 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type TG1_TASK_CNT_STOP_TIMER1_ST_R = crate::BitReader;
#[doc = "Field `TG1_TASK_CNT_STOP_TIMER1_ST` writer - Represents TG1_task_cnt_stop_timer1 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type TG1_TASK_CNT_STOP_TIMER1_ST_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TG1_TASK_CNT_RELOAD_TIMER1_ST` reader - Represents TG1_task_cnt_reload_timer1 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type TG1_TASK_CNT_RELOAD_TIMER1_ST_R = crate::BitReader;
#[doc = "Field `TG1_TASK_CNT_RELOAD_TIMER1_ST` writer - Represents TG1_task_cnt_reload_timer1 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type TG1_TASK_CNT_RELOAD_TIMER1_ST_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TG1_TASK_CNT_CAP_TIMER1_ST` reader - Represents TG1_task_cnt_cap_timer1 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type TG1_TASK_CNT_CAP_TIMER1_ST_R = crate::BitReader;
#[doc = "Field `TG1_TASK_CNT_CAP_TIMER1_ST` writer - Represents TG1_task_cnt_cap_timer1 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type TG1_TASK_CNT_CAP_TIMER1_ST_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MCPWM0_TASK_CMPR0_A_UP_ST` reader - Represents MCPWM0_task_cmpr0_a_up trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type MCPWM0_TASK_CMPR0_A_UP_ST_R = crate::BitReader;
#[doc = "Field `MCPWM0_TASK_CMPR0_A_UP_ST` writer - Represents MCPWM0_task_cmpr0_a_up trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type MCPWM0_TASK_CMPR0_A_UP_ST_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MCPWM0_TASK_CMPR1_A_UP_ST` reader - Represents MCPWM0_task_cmpr1_a_up trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type MCPWM0_TASK_CMPR1_A_UP_ST_R = crate::BitReader;
#[doc = "Field `MCPWM0_TASK_CMPR1_A_UP_ST` writer - Represents MCPWM0_task_cmpr1_a_up trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type MCPWM0_TASK_CMPR1_A_UP_ST_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MCPWM0_TASK_CMPR2_A_UP_ST` reader - Represents MCPWM0_task_cmpr2_a_up trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type MCPWM0_TASK_CMPR2_A_UP_ST_R = crate::BitReader;
#[doc = "Field `MCPWM0_TASK_CMPR2_A_UP_ST` writer - Represents MCPWM0_task_cmpr2_a_up trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type MCPWM0_TASK_CMPR2_A_UP_ST_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MCPWM0_TASK_CMPR0_B_UP_ST` reader - Represents MCPWM0_task_cmpr0_b_up trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type MCPWM0_TASK_CMPR0_B_UP_ST_R = crate::BitReader;
#[doc = "Field `MCPWM0_TASK_CMPR0_B_UP_ST` writer - Represents MCPWM0_task_cmpr0_b_up trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type MCPWM0_TASK_CMPR0_B_UP_ST_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MCPWM0_TASK_CMPR1_B_UP_ST` reader - Represents MCPWM0_task_cmpr1_b_up trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type MCPWM0_TASK_CMPR1_B_UP_ST_R = crate::BitReader;
#[doc = "Field `MCPWM0_TASK_CMPR1_B_UP_ST` writer - Represents MCPWM0_task_cmpr1_b_up trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type MCPWM0_TASK_CMPR1_B_UP_ST_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MCPWM0_TASK_CMPR2_B_UP_ST` reader - Represents MCPWM0_task_cmpr2_b_up trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type MCPWM0_TASK_CMPR2_B_UP_ST_R = crate::BitReader;
#[doc = "Field `MCPWM0_TASK_CMPR2_B_UP_ST` writer - Represents MCPWM0_task_cmpr2_b_up trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type MCPWM0_TASK_CMPR2_B_UP_ST_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MCPWM0_TASK_GEN_STOP_ST` reader - Represents MCPWM0_task_gen_stop trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type MCPWM0_TASK_GEN_STOP_ST_R = crate::BitReader;
#[doc = "Field `MCPWM0_TASK_GEN_STOP_ST` writer - Represents MCPWM0_task_gen_stop trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type MCPWM0_TASK_GEN_STOP_ST_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MCPWM0_TASK_TIMER0_SYN_ST` reader - Represents MCPWM0_task_timer0_syn trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type MCPWM0_TASK_TIMER0_SYN_ST_R = crate::BitReader;
#[doc = "Field `MCPWM0_TASK_TIMER0_SYN_ST` writer - Represents MCPWM0_task_timer0_syn trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type MCPWM0_TASK_TIMER0_SYN_ST_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MCPWM0_TASK_TIMER1_SYN_ST` reader - Represents MCPWM0_task_timer1_syn trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type MCPWM0_TASK_TIMER1_SYN_ST_R = crate::BitReader;
#[doc = "Field `MCPWM0_TASK_TIMER1_SYN_ST` writer - Represents MCPWM0_task_timer1_syn trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type MCPWM0_TASK_TIMER1_SYN_ST_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MCPWM0_TASK_TIMER2_SYN_ST` reader - Represents MCPWM0_task_timer2_syn trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type MCPWM0_TASK_TIMER2_SYN_ST_R = crate::BitReader;
#[doc = "Field `MCPWM0_TASK_TIMER2_SYN_ST` writer - Represents MCPWM0_task_timer2_syn trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type MCPWM0_TASK_TIMER2_SYN_ST_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MCPWM0_TASK_TIMER0_PERIOD_UP_ST` reader - Represents MCPWM0_task_timer0_period_up trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type MCPWM0_TASK_TIMER0_PERIOD_UP_ST_R = crate::BitReader;
#[doc = "Field `MCPWM0_TASK_TIMER0_PERIOD_UP_ST` writer - Represents MCPWM0_task_timer0_period_up trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type MCPWM0_TASK_TIMER0_PERIOD_UP_ST_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MCPWM0_TASK_TIMER1_PERIOD_UP_ST` reader - Represents MCPWM0_task_timer1_period_up trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type MCPWM0_TASK_TIMER1_PERIOD_UP_ST_R = crate::BitReader;
#[doc = "Field `MCPWM0_TASK_TIMER1_PERIOD_UP_ST` writer - Represents MCPWM0_task_timer1_period_up trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type MCPWM0_TASK_TIMER1_PERIOD_UP_ST_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MCPWM0_TASK_TIMER2_PERIOD_UP_ST` reader - Represents MCPWM0_task_timer2_period_up trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type MCPWM0_TASK_TIMER2_PERIOD_UP_ST_R = crate::BitReader;
#[doc = "Field `MCPWM0_TASK_TIMER2_PERIOD_UP_ST` writer - Represents MCPWM0_task_timer2_period_up trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type MCPWM0_TASK_TIMER2_PERIOD_UP_ST_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MCPWM0_TASK_TZ0_OST_ST` reader - Represents MCPWM0_task_tz0_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type MCPWM0_TASK_TZ0_OST_ST_R = crate::BitReader;
#[doc = "Field `MCPWM0_TASK_TZ0_OST_ST` writer - Represents MCPWM0_task_tz0_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type MCPWM0_TASK_TZ0_OST_ST_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MCPWM0_TASK_TZ1_OST_ST` reader - Represents MCPWM0_task_tz1_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type MCPWM0_TASK_TZ1_OST_ST_R = crate::BitReader;
#[doc = "Field `MCPWM0_TASK_TZ1_OST_ST` writer - Represents MCPWM0_task_tz1_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type MCPWM0_TASK_TZ1_OST_ST_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MCPWM0_TASK_TZ2_OST_ST` reader - Represents MCPWM0_task_tz2_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type MCPWM0_TASK_TZ2_OST_ST_R = crate::BitReader;
#[doc = "Field `MCPWM0_TASK_TZ2_OST_ST` writer - Represents MCPWM0_task_tz2_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type MCPWM0_TASK_TZ2_OST_ST_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MCPWM0_TASK_CLR0_OST_ST` reader - Represents MCPWM0_task_clr0_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type MCPWM0_TASK_CLR0_OST_ST_R = crate::BitReader;
#[doc = "Field `MCPWM0_TASK_CLR0_OST_ST` writer - Represents MCPWM0_task_clr0_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type MCPWM0_TASK_CLR0_OST_ST_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MCPWM0_TASK_CLR1_OST_ST` reader - Represents MCPWM0_task_clr1_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type MCPWM0_TASK_CLR1_OST_ST_R = crate::BitReader;
#[doc = "Field `MCPWM0_TASK_CLR1_OST_ST` writer - Represents MCPWM0_task_clr1_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type MCPWM0_TASK_CLR1_OST_ST_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MCPWM0_TASK_CLR2_OST_ST` reader - Represents MCPWM0_task_clr2_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type MCPWM0_TASK_CLR2_OST_ST_R = crate::BitReader;
#[doc = "Field `MCPWM0_TASK_CLR2_OST_ST` writer - Represents MCPWM0_task_clr2_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type MCPWM0_TASK_CLR2_OST_ST_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MCPWM0_TASK_CAP0_ST` reader - Represents MCPWM0_task_cap0 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type MCPWM0_TASK_CAP0_ST_R = crate::BitReader;
#[doc = "Field `MCPWM0_TASK_CAP0_ST` writer - Represents MCPWM0_task_cap0 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type MCPWM0_TASK_CAP0_ST_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MCPWM0_TASK_CAP1_ST` reader - Represents MCPWM0_task_cap1 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type MCPWM0_TASK_CAP1_ST_R = crate::BitReader;
#[doc = "Field `MCPWM0_TASK_CAP1_ST` writer - Represents MCPWM0_task_cap1 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type MCPWM0_TASK_CAP1_ST_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MCPWM0_TASK_CAP2_ST` reader - Represents MCPWM0_task_cap2 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type MCPWM0_TASK_CAP2_ST_R = crate::BitReader;
#[doc = "Field `MCPWM0_TASK_CAP2_ST` writer - Represents MCPWM0_task_cap2 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type MCPWM0_TASK_CAP2_ST_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC_TASK_SAMPLE0_ST` reader - Represents ADC_task_sample0 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type ADC_TASK_SAMPLE0_ST_R = crate::BitReader;
#[doc = "Field `ADC_TASK_SAMPLE0_ST` writer - Represents ADC_task_sample0 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type ADC_TASK_SAMPLE0_ST_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC_TASK_SAMPLE1_ST` reader - Represents ADC_task_sample1 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type ADC_TASK_SAMPLE1_ST_R = crate::BitReader;
#[doc = "Field `ADC_TASK_SAMPLE1_ST` writer - Represents ADC_task_sample1 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type ADC_TASK_SAMPLE1_ST_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC_TASK_START0_ST` reader - Represents ADC_task_start0 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type ADC_TASK_START0_ST_R = crate::BitReader;
#[doc = "Field `ADC_TASK_START0_ST` writer - Represents ADC_task_start0 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type ADC_TASK_START0_ST_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC_TASK_STOP0_ST` reader - Represents ADC_task_stop0 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type ADC_TASK_STOP0_ST_R = crate::BitReader;
#[doc = "Field `ADC_TASK_STOP0_ST` writer - Represents ADC_task_stop0 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type ADC_TASK_STOP0_ST_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `REGDMA_TASK_START0_ST` reader - Represents REGDMA_task_start0 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type REGDMA_TASK_START0_ST_R = crate::BitReader;
#[doc = "Field `REGDMA_TASK_START0_ST` writer - Represents REGDMA_task_start0 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type REGDMA_TASK_START0_ST_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `REGDMA_TASK_START1_ST` reader - Represents REGDMA_task_start1 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type REGDMA_TASK_START1_ST_R = crate::BitReader;
#[doc = "Field `REGDMA_TASK_START1_ST` writer - Represents REGDMA_task_start1 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type REGDMA_TASK_START1_ST_W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
    #[doc = "Bit 0 - Represents TG1_task_alarm_start_timer1 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn tg1_task_alarm_start_timer1_st(&self) -> TG1_TASK_ALARM_START_TIMER1_ST_R {
        TG1_TASK_ALARM_START_TIMER1_ST_R::new((self.bits & 1) != 0)
    }
    #[doc = "Bit 1 - Represents TG1_task_cnt_stop_timer1 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn tg1_task_cnt_stop_timer1_st(&self) -> TG1_TASK_CNT_STOP_TIMER1_ST_R {
        TG1_TASK_CNT_STOP_TIMER1_ST_R::new(((self.bits >> 1) & 1) != 0)
    }
    #[doc = "Bit 2 - Represents TG1_task_cnt_reload_timer1 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn tg1_task_cnt_reload_timer1_st(&self) -> TG1_TASK_CNT_RELOAD_TIMER1_ST_R {
        TG1_TASK_CNT_RELOAD_TIMER1_ST_R::new(((self.bits >> 2) & 1) != 0)
    }
    #[doc = "Bit 3 - Represents TG1_task_cnt_cap_timer1 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn tg1_task_cnt_cap_timer1_st(&self) -> TG1_TASK_CNT_CAP_TIMER1_ST_R {
        TG1_TASK_CNT_CAP_TIMER1_ST_R::new(((self.bits >> 3) & 1) != 0)
    }
    #[doc = "Bit 4 - Represents MCPWM0_task_cmpr0_a_up trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn mcpwm0_task_cmpr0_a_up_st(&self) -> MCPWM0_TASK_CMPR0_A_UP_ST_R {
        MCPWM0_TASK_CMPR0_A_UP_ST_R::new(((self.bits >> 4) & 1) != 0)
    }
    #[doc = "Bit 5 - Represents MCPWM0_task_cmpr1_a_up trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn mcpwm0_task_cmpr1_a_up_st(&self) -> MCPWM0_TASK_CMPR1_A_UP_ST_R {
        MCPWM0_TASK_CMPR1_A_UP_ST_R::new(((self.bits >> 5) & 1) != 0)
    }
    #[doc = "Bit 6 - Represents MCPWM0_task_cmpr2_a_up trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn mcpwm0_task_cmpr2_a_up_st(&self) -> MCPWM0_TASK_CMPR2_A_UP_ST_R {
        MCPWM0_TASK_CMPR2_A_UP_ST_R::new(((self.bits >> 6) & 1) != 0)
    }
    #[doc = "Bit 7 - Represents MCPWM0_task_cmpr0_b_up trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn mcpwm0_task_cmpr0_b_up_st(&self) -> MCPWM0_TASK_CMPR0_B_UP_ST_R {
        MCPWM0_TASK_CMPR0_B_UP_ST_R::new(((self.bits >> 7) & 1) != 0)
    }
    #[doc = "Bit 8 - Represents MCPWM0_task_cmpr1_b_up trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn mcpwm0_task_cmpr1_b_up_st(&self) -> MCPWM0_TASK_CMPR1_B_UP_ST_R {
        MCPWM0_TASK_CMPR1_B_UP_ST_R::new(((self.bits >> 8) & 1) != 0)
    }
    #[doc = "Bit 9 - Represents MCPWM0_task_cmpr2_b_up trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn mcpwm0_task_cmpr2_b_up_st(&self) -> MCPWM0_TASK_CMPR2_B_UP_ST_R {
        MCPWM0_TASK_CMPR2_B_UP_ST_R::new(((self.bits >> 9) & 1) != 0)
    }
    #[doc = "Bit 10 - Represents MCPWM0_task_gen_stop trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn mcpwm0_task_gen_stop_st(&self) -> MCPWM0_TASK_GEN_STOP_ST_R {
        MCPWM0_TASK_GEN_STOP_ST_R::new(((self.bits >> 10) & 1) != 0)
    }
    #[doc = "Bit 11 - Represents MCPWM0_task_timer0_syn trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn mcpwm0_task_timer0_syn_st(&self) -> MCPWM0_TASK_TIMER0_SYN_ST_R {
        MCPWM0_TASK_TIMER0_SYN_ST_R::new(((self.bits >> 11) & 1) != 0)
    }
    #[doc = "Bit 12 - Represents MCPWM0_task_timer1_syn trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn mcpwm0_task_timer1_syn_st(&self) -> MCPWM0_TASK_TIMER1_SYN_ST_R {
        MCPWM0_TASK_TIMER1_SYN_ST_R::new(((self.bits >> 12) & 1) != 0)
    }
    #[doc = "Bit 13 - Represents MCPWM0_task_timer2_syn trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn mcpwm0_task_timer2_syn_st(&self) -> MCPWM0_TASK_TIMER2_SYN_ST_R {
        MCPWM0_TASK_TIMER2_SYN_ST_R::new(((self.bits >> 13) & 1) != 0)
    }
    #[doc = "Bit 14 - Represents MCPWM0_task_timer0_period_up trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn mcpwm0_task_timer0_period_up_st(&self) -> MCPWM0_TASK_TIMER0_PERIOD_UP_ST_R {
        MCPWM0_TASK_TIMER0_PERIOD_UP_ST_R::new(((self.bits >> 14) & 1) != 0)
    }
    #[doc = "Bit 15 - Represents MCPWM0_task_timer1_period_up trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn mcpwm0_task_timer1_period_up_st(&self) -> MCPWM0_TASK_TIMER1_PERIOD_UP_ST_R {
        MCPWM0_TASK_TIMER1_PERIOD_UP_ST_R::new(((self.bits >> 15) & 1) != 0)
    }
    #[doc = "Bit 16 - Represents MCPWM0_task_timer2_period_up trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn mcpwm0_task_timer2_period_up_st(&self) -> MCPWM0_TASK_TIMER2_PERIOD_UP_ST_R {
        MCPWM0_TASK_TIMER2_PERIOD_UP_ST_R::new(((self.bits >> 16) & 1) != 0)
    }
    #[doc = "Bit 17 - Represents MCPWM0_task_tz0_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn mcpwm0_task_tz0_ost_st(&self) -> MCPWM0_TASK_TZ0_OST_ST_R {
        MCPWM0_TASK_TZ0_OST_ST_R::new(((self.bits >> 17) & 1) != 0)
    }
    #[doc = "Bit 18 - Represents MCPWM0_task_tz1_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn mcpwm0_task_tz1_ost_st(&self) -> MCPWM0_TASK_TZ1_OST_ST_R {
        MCPWM0_TASK_TZ1_OST_ST_R::new(((self.bits >> 18) & 1) != 0)
    }
    #[doc = "Bit 19 - Represents MCPWM0_task_tz2_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn mcpwm0_task_tz2_ost_st(&self) -> MCPWM0_TASK_TZ2_OST_ST_R {
        MCPWM0_TASK_TZ2_OST_ST_R::new(((self.bits >> 19) & 1) != 0)
    }
    #[doc = "Bit 20 - Represents MCPWM0_task_clr0_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn mcpwm0_task_clr0_ost_st(&self) -> MCPWM0_TASK_CLR0_OST_ST_R {
        MCPWM0_TASK_CLR0_OST_ST_R::new(((self.bits >> 20) & 1) != 0)
    }
    #[doc = "Bit 21 - Represents MCPWM0_task_clr1_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn mcpwm0_task_clr1_ost_st(&self) -> MCPWM0_TASK_CLR1_OST_ST_R {
        MCPWM0_TASK_CLR1_OST_ST_R::new(((self.bits >> 21) & 1) != 0)
    }
    #[doc = "Bit 22 - Represents MCPWM0_task_clr2_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn mcpwm0_task_clr2_ost_st(&self) -> MCPWM0_TASK_CLR2_OST_ST_R {
        MCPWM0_TASK_CLR2_OST_ST_R::new(((self.bits >> 22) & 1) != 0)
    }
    #[doc = "Bit 23 - Represents MCPWM0_task_cap0 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn mcpwm0_task_cap0_st(&self) -> MCPWM0_TASK_CAP0_ST_R {
        MCPWM0_TASK_CAP0_ST_R::new(((self.bits >> 23) & 1) != 0)
    }
    #[doc = "Bit 24 - Represents MCPWM0_task_cap1 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn mcpwm0_task_cap1_st(&self) -> MCPWM0_TASK_CAP1_ST_R {
        MCPWM0_TASK_CAP1_ST_R::new(((self.bits >> 24) & 1) != 0)
    }
    #[doc = "Bit 25 - Represents MCPWM0_task_cap2 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn mcpwm0_task_cap2_st(&self) -> MCPWM0_TASK_CAP2_ST_R {
        MCPWM0_TASK_CAP2_ST_R::new(((self.bits >> 25) & 1) != 0)
    }
    #[doc = "Bit 26 - Represents ADC_task_sample0 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn adc_task_sample0_st(&self) -> ADC_TASK_SAMPLE0_ST_R {
        ADC_TASK_SAMPLE0_ST_R::new(((self.bits >> 26) & 1) != 0)
    }
    #[doc = "Bit 27 - Represents ADC_task_sample1 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn adc_task_sample1_st(&self) -> ADC_TASK_SAMPLE1_ST_R {
        ADC_TASK_SAMPLE1_ST_R::new(((self.bits >> 27) & 1) != 0)
    }
    #[doc = "Bit 28 - Represents ADC_task_start0 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn adc_task_start0_st(&self) -> ADC_TASK_START0_ST_R {
        ADC_TASK_START0_ST_R::new(((self.bits >> 28) & 1) != 0)
    }
    #[doc = "Bit 29 - Represents ADC_task_stop0 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn adc_task_stop0_st(&self) -> ADC_TASK_STOP0_ST_R {
        ADC_TASK_STOP0_ST_R::new(((self.bits >> 29) & 1) != 0)
    }
    #[doc = "Bit 30 - Represents REGDMA_task_start0 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn regdma_task_start0_st(&self) -> REGDMA_TASK_START0_ST_R {
        REGDMA_TASK_START0_ST_R::new(((self.bits >> 30) & 1) != 0)
    }
    #[doc = "Bit 31 - Represents REGDMA_task_start1 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn regdma_task_start1_st(&self) -> REGDMA_TASK_START1_ST_R {
        REGDMA_TASK_START1_ST_R::new(((self.bits >> 31) & 1) != 0)
    }
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for R {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("TASK_ST3")
            .field(
                "tg1_task_alarm_start_timer1_st",
                &self.tg1_task_alarm_start_timer1_st(),
            )
            .field(
                "tg1_task_cnt_stop_timer1_st",
                &self.tg1_task_cnt_stop_timer1_st(),
            )
            .field(
                "tg1_task_cnt_reload_timer1_st",
                &self.tg1_task_cnt_reload_timer1_st(),
            )
            .field(
                "tg1_task_cnt_cap_timer1_st",
                &self.tg1_task_cnt_cap_timer1_st(),
            )
            .field(
                "mcpwm0_task_cmpr0_a_up_st",
                &self.mcpwm0_task_cmpr0_a_up_st(),
            )
            .field(
                "mcpwm0_task_cmpr1_a_up_st",
                &self.mcpwm0_task_cmpr1_a_up_st(),
            )
            .field(
                "mcpwm0_task_cmpr2_a_up_st",
                &self.mcpwm0_task_cmpr2_a_up_st(),
            )
            .field(
                "mcpwm0_task_cmpr0_b_up_st",
                &self.mcpwm0_task_cmpr0_b_up_st(),
            )
            .field(
                "mcpwm0_task_cmpr1_b_up_st",
                &self.mcpwm0_task_cmpr1_b_up_st(),
            )
            .field(
                "mcpwm0_task_cmpr2_b_up_st",
                &self.mcpwm0_task_cmpr2_b_up_st(),
            )
            .field("mcpwm0_task_gen_stop_st", &self.mcpwm0_task_gen_stop_st())
            .field(
                "mcpwm0_task_timer0_syn_st",
                &self.mcpwm0_task_timer0_syn_st(),
            )
            .field(
                "mcpwm0_task_timer1_syn_st",
                &self.mcpwm0_task_timer1_syn_st(),
            )
            .field(
                "mcpwm0_task_timer2_syn_st",
                &self.mcpwm0_task_timer2_syn_st(),
            )
            .field(
                "mcpwm0_task_timer0_period_up_st",
                &self.mcpwm0_task_timer0_period_up_st(),
            )
            .field(
                "mcpwm0_task_timer1_period_up_st",
                &self.mcpwm0_task_timer1_period_up_st(),
            )
            .field(
                "mcpwm0_task_timer2_period_up_st",
                &self.mcpwm0_task_timer2_period_up_st(),
            )
            .field("mcpwm0_task_tz0_ost_st", &self.mcpwm0_task_tz0_ost_st())
            .field("mcpwm0_task_tz1_ost_st", &self.mcpwm0_task_tz1_ost_st())
            .field("mcpwm0_task_tz2_ost_st", &self.mcpwm0_task_tz2_ost_st())
            .field("mcpwm0_task_clr0_ost_st", &self.mcpwm0_task_clr0_ost_st())
            .field("mcpwm0_task_clr1_ost_st", &self.mcpwm0_task_clr1_ost_st())
            .field("mcpwm0_task_clr2_ost_st", &self.mcpwm0_task_clr2_ost_st())
            .field("mcpwm0_task_cap0_st", &self.mcpwm0_task_cap0_st())
            .field("mcpwm0_task_cap1_st", &self.mcpwm0_task_cap1_st())
            .field("mcpwm0_task_cap2_st", &self.mcpwm0_task_cap2_st())
            .field("adc_task_sample0_st", &self.adc_task_sample0_st())
            .field("adc_task_sample1_st", &self.adc_task_sample1_st())
            .field("adc_task_start0_st", &self.adc_task_start0_st())
            .field("adc_task_stop0_st", &self.adc_task_stop0_st())
            .field("regdma_task_start0_st", &self.regdma_task_start0_st())
            .field("regdma_task_start1_st", &self.regdma_task_start1_st())
            .finish()
    }
}
impl W {
    #[doc = "Bit 0 - Represents TG1_task_alarm_start_timer1 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn tg1_task_alarm_start_timer1_st(
        &mut self,
    ) -> TG1_TASK_ALARM_START_TIMER1_ST_W<'_, TASK_ST3_SPEC> {
        TG1_TASK_ALARM_START_TIMER1_ST_W::new(self, 0)
    }
    #[doc = "Bit 1 - Represents TG1_task_cnt_stop_timer1 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn tg1_task_cnt_stop_timer1_st(
        &mut self,
    ) -> TG1_TASK_CNT_STOP_TIMER1_ST_W<'_, TASK_ST3_SPEC> {
        TG1_TASK_CNT_STOP_TIMER1_ST_W::new(self, 1)
    }
    #[doc = "Bit 2 - Represents TG1_task_cnt_reload_timer1 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn tg1_task_cnt_reload_timer1_st(
        &mut self,
    ) -> TG1_TASK_CNT_RELOAD_TIMER1_ST_W<'_, TASK_ST3_SPEC> {
        TG1_TASK_CNT_RELOAD_TIMER1_ST_W::new(self, 2)
    }
    #[doc = "Bit 3 - Represents TG1_task_cnt_cap_timer1 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn tg1_task_cnt_cap_timer1_st(
        &mut self,
    ) -> TG1_TASK_CNT_CAP_TIMER1_ST_W<'_, TASK_ST3_SPEC> {
        TG1_TASK_CNT_CAP_TIMER1_ST_W::new(self, 3)
    }
    #[doc = "Bit 4 - Represents MCPWM0_task_cmpr0_a_up trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn mcpwm0_task_cmpr0_a_up_st(&mut self) -> MCPWM0_TASK_CMPR0_A_UP_ST_W<'_, TASK_ST3_SPEC> {
        MCPWM0_TASK_CMPR0_A_UP_ST_W::new(self, 4)
    }
    #[doc = "Bit 5 - Represents MCPWM0_task_cmpr1_a_up trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn mcpwm0_task_cmpr1_a_up_st(&mut self) -> MCPWM0_TASK_CMPR1_A_UP_ST_W<'_, TASK_ST3_SPEC> {
        MCPWM0_TASK_CMPR1_A_UP_ST_W::new(self, 5)
    }
    #[doc = "Bit 6 - Represents MCPWM0_task_cmpr2_a_up trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn mcpwm0_task_cmpr2_a_up_st(&mut self) -> MCPWM0_TASK_CMPR2_A_UP_ST_W<'_, TASK_ST3_SPEC> {
        MCPWM0_TASK_CMPR2_A_UP_ST_W::new(self, 6)
    }
    #[doc = "Bit 7 - Represents MCPWM0_task_cmpr0_b_up trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn mcpwm0_task_cmpr0_b_up_st(&mut self) -> MCPWM0_TASK_CMPR0_B_UP_ST_W<'_, TASK_ST3_SPEC> {
        MCPWM0_TASK_CMPR0_B_UP_ST_W::new(self, 7)
    }
    #[doc = "Bit 8 - Represents MCPWM0_task_cmpr1_b_up trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn mcpwm0_task_cmpr1_b_up_st(&mut self) -> MCPWM0_TASK_CMPR1_B_UP_ST_W<'_, TASK_ST3_SPEC> {
        MCPWM0_TASK_CMPR1_B_UP_ST_W::new(self, 8)
    }
    #[doc = "Bit 9 - Represents MCPWM0_task_cmpr2_b_up trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn mcpwm0_task_cmpr2_b_up_st(&mut self) -> MCPWM0_TASK_CMPR2_B_UP_ST_W<'_, TASK_ST3_SPEC> {
        MCPWM0_TASK_CMPR2_B_UP_ST_W::new(self, 9)
    }
    #[doc = "Bit 10 - Represents MCPWM0_task_gen_stop trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn mcpwm0_task_gen_stop_st(&mut self) -> MCPWM0_TASK_GEN_STOP_ST_W<'_, TASK_ST3_SPEC> {
        MCPWM0_TASK_GEN_STOP_ST_W::new(self, 10)
    }
    #[doc = "Bit 11 - Represents MCPWM0_task_timer0_syn trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn mcpwm0_task_timer0_syn_st(&mut self) -> MCPWM0_TASK_TIMER0_SYN_ST_W<'_, TASK_ST3_SPEC> {
        MCPWM0_TASK_TIMER0_SYN_ST_W::new(self, 11)
    }
    #[doc = "Bit 12 - Represents MCPWM0_task_timer1_syn trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn mcpwm0_task_timer1_syn_st(&mut self) -> MCPWM0_TASK_TIMER1_SYN_ST_W<'_, TASK_ST3_SPEC> {
        MCPWM0_TASK_TIMER1_SYN_ST_W::new(self, 12)
    }
    #[doc = "Bit 13 - Represents MCPWM0_task_timer2_syn trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn mcpwm0_task_timer2_syn_st(&mut self) -> MCPWM0_TASK_TIMER2_SYN_ST_W<'_, TASK_ST3_SPEC> {
        MCPWM0_TASK_TIMER2_SYN_ST_W::new(self, 13)
    }
    #[doc = "Bit 14 - Represents MCPWM0_task_timer0_period_up trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn mcpwm0_task_timer0_period_up_st(
        &mut self,
    ) -> MCPWM0_TASK_TIMER0_PERIOD_UP_ST_W<'_, TASK_ST3_SPEC> {
        MCPWM0_TASK_TIMER0_PERIOD_UP_ST_W::new(self, 14)
    }
    #[doc = "Bit 15 - Represents MCPWM0_task_timer1_period_up trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn mcpwm0_task_timer1_period_up_st(
        &mut self,
    ) -> MCPWM0_TASK_TIMER1_PERIOD_UP_ST_W<'_, TASK_ST3_SPEC> {
        MCPWM0_TASK_TIMER1_PERIOD_UP_ST_W::new(self, 15)
    }
    #[doc = "Bit 16 - Represents MCPWM0_task_timer2_period_up trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn mcpwm0_task_timer2_period_up_st(
        &mut self,
    ) -> MCPWM0_TASK_TIMER2_PERIOD_UP_ST_W<'_, TASK_ST3_SPEC> {
        MCPWM0_TASK_TIMER2_PERIOD_UP_ST_W::new(self, 16)
    }
    #[doc = "Bit 17 - Represents MCPWM0_task_tz0_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn mcpwm0_task_tz0_ost_st(&mut self) -> MCPWM0_TASK_TZ0_OST_ST_W<'_, TASK_ST3_SPEC> {
        MCPWM0_TASK_TZ0_OST_ST_W::new(self, 17)
    }
    #[doc = "Bit 18 - Represents MCPWM0_task_tz1_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn mcpwm0_task_tz1_ost_st(&mut self) -> MCPWM0_TASK_TZ1_OST_ST_W<'_, TASK_ST3_SPEC> {
        MCPWM0_TASK_TZ1_OST_ST_W::new(self, 18)
    }
    #[doc = "Bit 19 - Represents MCPWM0_task_tz2_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn mcpwm0_task_tz2_ost_st(&mut self) -> MCPWM0_TASK_TZ2_OST_ST_W<'_, TASK_ST3_SPEC> {
        MCPWM0_TASK_TZ2_OST_ST_W::new(self, 19)
    }
    #[doc = "Bit 20 - Represents MCPWM0_task_clr0_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn mcpwm0_task_clr0_ost_st(&mut self) -> MCPWM0_TASK_CLR0_OST_ST_W<'_, TASK_ST3_SPEC> {
        MCPWM0_TASK_CLR0_OST_ST_W::new(self, 20)
    }
    #[doc = "Bit 21 - Represents MCPWM0_task_clr1_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn mcpwm0_task_clr1_ost_st(&mut self) -> MCPWM0_TASK_CLR1_OST_ST_W<'_, TASK_ST3_SPEC> {
        MCPWM0_TASK_CLR1_OST_ST_W::new(self, 21)
    }
    #[doc = "Bit 22 - Represents MCPWM0_task_clr2_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn mcpwm0_task_clr2_ost_st(&mut self) -> MCPWM0_TASK_CLR2_OST_ST_W<'_, TASK_ST3_SPEC> {
        MCPWM0_TASK_CLR2_OST_ST_W::new(self, 22)
    }
    #[doc = "Bit 23 - Represents MCPWM0_task_cap0 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn mcpwm0_task_cap0_st(&mut self) -> MCPWM0_TASK_CAP0_ST_W<'_, TASK_ST3_SPEC> {
        MCPWM0_TASK_CAP0_ST_W::new(self, 23)
    }
    #[doc = "Bit 24 - Represents MCPWM0_task_cap1 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn mcpwm0_task_cap1_st(&mut self) -> MCPWM0_TASK_CAP1_ST_W<'_, TASK_ST3_SPEC> {
        MCPWM0_TASK_CAP1_ST_W::new(self, 24)
    }
    #[doc = "Bit 25 - Represents MCPWM0_task_cap2 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn mcpwm0_task_cap2_st(&mut self) -> MCPWM0_TASK_CAP2_ST_W<'_, TASK_ST3_SPEC> {
        MCPWM0_TASK_CAP2_ST_W::new(self, 25)
    }
    #[doc = "Bit 26 - Represents ADC_task_sample0 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn adc_task_sample0_st(&mut self) -> ADC_TASK_SAMPLE0_ST_W<'_, TASK_ST3_SPEC> {
        ADC_TASK_SAMPLE0_ST_W::new(self, 26)
    }
    #[doc = "Bit 27 - Represents ADC_task_sample1 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn adc_task_sample1_st(&mut self) -> ADC_TASK_SAMPLE1_ST_W<'_, TASK_ST3_SPEC> {
        ADC_TASK_SAMPLE1_ST_W::new(self, 27)
    }
    #[doc = "Bit 28 - Represents ADC_task_start0 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn adc_task_start0_st(&mut self) -> ADC_TASK_START0_ST_W<'_, TASK_ST3_SPEC> {
        ADC_TASK_START0_ST_W::new(self, 28)
    }
    #[doc = "Bit 29 - Represents ADC_task_stop0 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn adc_task_stop0_st(&mut self) -> ADC_TASK_STOP0_ST_W<'_, TASK_ST3_SPEC> {
        ADC_TASK_STOP0_ST_W::new(self, 29)
    }
    #[doc = "Bit 30 - Represents REGDMA_task_start0 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn regdma_task_start0_st(&mut self) -> REGDMA_TASK_START0_ST_W<'_, TASK_ST3_SPEC> {
        REGDMA_TASK_START0_ST_W::new(self, 30)
    }
    #[doc = "Bit 31 - Represents REGDMA_task_start1 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn regdma_task_start1_st(&mut self) -> REGDMA_TASK_START1_ST_W<'_, TASK_ST3_SPEC> {
        REGDMA_TASK_START1_ST_W::new(self, 31)
    }
}
#[doc = "Tasks trigger status register\n\nYou can [`read`](crate::Reg::read) this register and get [`task_st3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`task_st3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TASK_ST3_SPEC;
impl crate::RegisterSpec for TASK_ST3_SPEC {
    type Ux = u32;
}
#[doc = "`read()` method returns [`task_st3::R`](R) reader structure"]
impl crate::Readable for TASK_ST3_SPEC {}
#[doc = "`write(|w| ..)` method takes [`task_st3::W`](W) writer structure"]
impl crate::Writable for TASK_ST3_SPEC {
    type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets TASK_ST3 to value 0"]
impl crate::Resettable for TASK_ST3_SPEC {}
