#[doc = "Register `EVT_ST2` reader"]
pub type R = crate::R<EVT_ST2_SPEC>;
#[doc = "Register `EVT_ST2` writer"]
pub type W = crate::W<EVT_ST2_SPEC>;
#[doc = "Field `MCPWM0_EVT_OP2_TEA_ST` reader - Represents MCPWM0_evt_op2_tea trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type MCPWM0_EVT_OP2_TEA_ST_R = crate::BitReader;
#[doc = "Field `MCPWM0_EVT_OP2_TEA_ST` writer - Represents MCPWM0_evt_op2_tea trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type MCPWM0_EVT_OP2_TEA_ST_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MCPWM0_EVT_OP0_TEB_ST` reader - Represents MCPWM0_evt_op0_teb trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type MCPWM0_EVT_OP0_TEB_ST_R = crate::BitReader;
#[doc = "Field `MCPWM0_EVT_OP0_TEB_ST` writer - Represents MCPWM0_evt_op0_teb trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type MCPWM0_EVT_OP0_TEB_ST_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MCPWM0_EVT_OP1_TEB_ST` reader - Represents MCPWM0_evt_op1_teb trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type MCPWM0_EVT_OP1_TEB_ST_R = crate::BitReader;
#[doc = "Field `MCPWM0_EVT_OP1_TEB_ST` writer - Represents MCPWM0_evt_op1_teb trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type MCPWM0_EVT_OP1_TEB_ST_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MCPWM0_EVT_OP2_TEB_ST` reader - Represents MCPWM0_evt_op2_teb trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type MCPWM0_EVT_OP2_TEB_ST_R = crate::BitReader;
#[doc = "Field `MCPWM0_EVT_OP2_TEB_ST` writer - Represents MCPWM0_evt_op2_teb trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type MCPWM0_EVT_OP2_TEB_ST_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MCPWM0_EVT_F0_ST` reader - Represents MCPWM0_evt_f0 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type MCPWM0_EVT_F0_ST_R = crate::BitReader;
#[doc = "Field `MCPWM0_EVT_F0_ST` writer - Represents MCPWM0_evt_f0 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type MCPWM0_EVT_F0_ST_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MCPWM0_EVT_F1_ST` reader - Represents MCPWM0_evt_f1 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type MCPWM0_EVT_F1_ST_R = crate::BitReader;
#[doc = "Field `MCPWM0_EVT_F1_ST` writer - Represents MCPWM0_evt_f1 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type MCPWM0_EVT_F1_ST_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MCPWM0_EVT_F2_ST` reader - Represents MCPWM0_evt_f2 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type MCPWM0_EVT_F2_ST_R = crate::BitReader;
#[doc = "Field `MCPWM0_EVT_F2_ST` writer - Represents MCPWM0_evt_f2 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type MCPWM0_EVT_F2_ST_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MCPWM0_EVT_F0_CLR_ST` reader - Represents MCPWM0_evt_f0_clr trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type MCPWM0_EVT_F0_CLR_ST_R = crate::BitReader;
#[doc = "Field `MCPWM0_EVT_F0_CLR_ST` writer - Represents MCPWM0_evt_f0_clr trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type MCPWM0_EVT_F0_CLR_ST_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MCPWM0_EVT_F1_CLR_ST` reader - Represents MCPWM0_evt_f1_clr trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type MCPWM0_EVT_F1_CLR_ST_R = crate::BitReader;
#[doc = "Field `MCPWM0_EVT_F1_CLR_ST` writer - Represents MCPWM0_evt_f1_clr trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type MCPWM0_EVT_F1_CLR_ST_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MCPWM0_EVT_F2_CLR_ST` reader - Represents MCPWM0_evt_f2_clr trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type MCPWM0_EVT_F2_CLR_ST_R = crate::BitReader;
#[doc = "Field `MCPWM0_EVT_F2_CLR_ST` writer - Represents MCPWM0_evt_f2_clr trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type MCPWM0_EVT_F2_CLR_ST_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MCPWM0_EVT_TZ0_CBC_ST` reader - Represents MCPWM0_evt_tz0_cbc trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type MCPWM0_EVT_TZ0_CBC_ST_R = crate::BitReader;
#[doc = "Field `MCPWM0_EVT_TZ0_CBC_ST` writer - Represents MCPWM0_evt_tz0_cbc trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type MCPWM0_EVT_TZ0_CBC_ST_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MCPWM0_EVT_TZ1_CBC_ST` reader - Represents MCPWM0_evt_tz1_cbc trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type MCPWM0_EVT_TZ1_CBC_ST_R = crate::BitReader;
#[doc = "Field `MCPWM0_EVT_TZ1_CBC_ST` writer - Represents MCPWM0_evt_tz1_cbc trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type MCPWM0_EVT_TZ1_CBC_ST_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MCPWM0_EVT_TZ2_CBC_ST` reader - Represents MCPWM0_evt_tz2_cbc trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type MCPWM0_EVT_TZ2_CBC_ST_R = crate::BitReader;
#[doc = "Field `MCPWM0_EVT_TZ2_CBC_ST` writer - Represents MCPWM0_evt_tz2_cbc trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type MCPWM0_EVT_TZ2_CBC_ST_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MCPWM0_EVT_TZ0_OST_ST` reader - Represents MCPWM0_evt_tz0_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type MCPWM0_EVT_TZ0_OST_ST_R = crate::BitReader;
#[doc = "Field `MCPWM0_EVT_TZ0_OST_ST` writer - Represents MCPWM0_evt_tz0_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type MCPWM0_EVT_TZ0_OST_ST_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MCPWM0_EVT_TZ1_OST_ST` reader - Represents MCPWM0_evt_tz1_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type MCPWM0_EVT_TZ1_OST_ST_R = crate::BitReader;
#[doc = "Field `MCPWM0_EVT_TZ1_OST_ST` writer - Represents MCPWM0_evt_tz1_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type MCPWM0_EVT_TZ1_OST_ST_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MCPWM0_EVT_TZ2_OST_ST` reader - Represents MCPWM0_evt_tz2_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type MCPWM0_EVT_TZ2_OST_ST_R = crate::BitReader;
#[doc = "Field `MCPWM0_EVT_TZ2_OST_ST` writer - Represents MCPWM0_evt_tz2_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type MCPWM0_EVT_TZ2_OST_ST_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MCPWM0_EVT_CAP0_ST` reader - Represents MCPWM0_evt_cap0 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type MCPWM0_EVT_CAP0_ST_R = crate::BitReader;
#[doc = "Field `MCPWM0_EVT_CAP0_ST` writer - Represents MCPWM0_evt_cap0 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type MCPWM0_EVT_CAP0_ST_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MCPWM0_EVT_CAP1_ST` reader - Represents MCPWM0_evt_cap1 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type MCPWM0_EVT_CAP1_ST_R = crate::BitReader;
#[doc = "Field `MCPWM0_EVT_CAP1_ST` writer - Represents MCPWM0_evt_cap1 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type MCPWM0_EVT_CAP1_ST_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MCPWM0_EVT_CAP2_ST` reader - Represents MCPWM0_evt_cap2 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type MCPWM0_EVT_CAP2_ST_R = crate::BitReader;
#[doc = "Field `MCPWM0_EVT_CAP2_ST` writer - Represents MCPWM0_evt_cap2 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type MCPWM0_EVT_CAP2_ST_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MCPWM0_EVT_OP0_TEE1_ST` reader - Represents MCPWM0_evt_op0_tee1 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type MCPWM0_EVT_OP0_TEE1_ST_R = crate::BitReader;
#[doc = "Field `MCPWM0_EVT_OP0_TEE1_ST` writer - Represents MCPWM0_evt_op0_tee1 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type MCPWM0_EVT_OP0_TEE1_ST_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MCPWM0_EVT_OP1_TEE1_ST` reader - Represents MCPWM0_evt_op1_tee1 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type MCPWM0_EVT_OP1_TEE1_ST_R = crate::BitReader;
#[doc = "Field `MCPWM0_EVT_OP1_TEE1_ST` writer - Represents MCPWM0_evt_op1_tee1 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type MCPWM0_EVT_OP1_TEE1_ST_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MCPWM0_EVT_OP2_TEE1_ST` reader - Represents MCPWM0_evt_op2_tee1 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type MCPWM0_EVT_OP2_TEE1_ST_R = crate::BitReader;
#[doc = "Field `MCPWM0_EVT_OP2_TEE1_ST` writer - Represents MCPWM0_evt_op2_tee1 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type MCPWM0_EVT_OP2_TEE1_ST_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MCPWM0_EVT_OP0_TEE2_ST` reader - Represents MCPWM0_evt_op0_tee2 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type MCPWM0_EVT_OP0_TEE2_ST_R = crate::BitReader;
#[doc = "Field `MCPWM0_EVT_OP0_TEE2_ST` writer - Represents MCPWM0_evt_op0_tee2 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type MCPWM0_EVT_OP0_TEE2_ST_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MCPWM0_EVT_OP1_TEE2_ST` reader - Represents MCPWM0_evt_op1_tee2 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type MCPWM0_EVT_OP1_TEE2_ST_R = crate::BitReader;
#[doc = "Field `MCPWM0_EVT_OP1_TEE2_ST` writer - Represents MCPWM0_evt_op1_tee2 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type MCPWM0_EVT_OP1_TEE2_ST_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MCPWM0_EVT_OP2_TEE2_ST` reader - Represents MCPWM0_evt_op2_tee2 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type MCPWM0_EVT_OP2_TEE2_ST_R = crate::BitReader;
#[doc = "Field `MCPWM0_EVT_OP2_TEE2_ST` writer - Represents MCPWM0_evt_op2_tee2 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type MCPWM0_EVT_OP2_TEE2_ST_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC_EVT_CONV_CMPLT0_ST` reader - Represents ADC_evt_conv_cmplt0 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type ADC_EVT_CONV_CMPLT0_ST_R = crate::BitReader;
#[doc = "Field `ADC_EVT_CONV_CMPLT0_ST` writer - Represents ADC_evt_conv_cmplt0 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type ADC_EVT_CONV_CMPLT0_ST_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC_EVT_EQ_ABOVE_THRESH0_ST` reader - Represents ADC_evt_eq_above_thresh0 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type ADC_EVT_EQ_ABOVE_THRESH0_ST_R = crate::BitReader;
#[doc = "Field `ADC_EVT_EQ_ABOVE_THRESH0_ST` writer - Represents ADC_evt_eq_above_thresh0 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type ADC_EVT_EQ_ABOVE_THRESH0_ST_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC_EVT_EQ_ABOVE_THRESH1_ST` reader - Represents ADC_evt_eq_above_thresh1 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type ADC_EVT_EQ_ABOVE_THRESH1_ST_R = crate::BitReader;
#[doc = "Field `ADC_EVT_EQ_ABOVE_THRESH1_ST` writer - Represents ADC_evt_eq_above_thresh1 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type ADC_EVT_EQ_ABOVE_THRESH1_ST_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC_EVT_EQ_BELOW_THRESH0_ST` reader - Represents ADC_evt_eq_below_thresh0 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type ADC_EVT_EQ_BELOW_THRESH0_ST_R = crate::BitReader;
#[doc = "Field `ADC_EVT_EQ_BELOW_THRESH0_ST` writer - Represents ADC_evt_eq_below_thresh0 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type ADC_EVT_EQ_BELOW_THRESH0_ST_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC_EVT_EQ_BELOW_THRESH1_ST` reader - Represents ADC_evt_eq_below_thresh1 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type ADC_EVT_EQ_BELOW_THRESH1_ST_R = crate::BitReader;
#[doc = "Field `ADC_EVT_EQ_BELOW_THRESH1_ST` writer - Represents ADC_evt_eq_below_thresh1 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type ADC_EVT_EQ_BELOW_THRESH1_ST_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC_EVT_RESULT_DONE0_ST` reader - Represents ADC_evt_result_done0 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type ADC_EVT_RESULT_DONE0_ST_R = crate::BitReader;
#[doc = "Field `ADC_EVT_RESULT_DONE0_ST` writer - Represents ADC_evt_result_done0 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type ADC_EVT_RESULT_DONE0_ST_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC_EVT_STOPPED0_ST` reader - Represents ADC_evt_stopped0 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type ADC_EVT_STOPPED0_ST_R = crate::BitReader;
#[doc = "Field `ADC_EVT_STOPPED0_ST` writer - Represents ADC_evt_stopped0 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
pub type ADC_EVT_STOPPED0_ST_W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
    #[doc = "Bit 0 - Represents MCPWM0_evt_op2_tea trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn mcpwm0_evt_op2_tea_st(&self) -> MCPWM0_EVT_OP2_TEA_ST_R {
        MCPWM0_EVT_OP2_TEA_ST_R::new((self.bits & 1) != 0)
    }
    #[doc = "Bit 1 - Represents MCPWM0_evt_op0_teb trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn mcpwm0_evt_op0_teb_st(&self) -> MCPWM0_EVT_OP0_TEB_ST_R {
        MCPWM0_EVT_OP0_TEB_ST_R::new(((self.bits >> 1) & 1) != 0)
    }
    #[doc = "Bit 2 - Represents MCPWM0_evt_op1_teb trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn mcpwm0_evt_op1_teb_st(&self) -> MCPWM0_EVT_OP1_TEB_ST_R {
        MCPWM0_EVT_OP1_TEB_ST_R::new(((self.bits >> 2) & 1) != 0)
    }
    #[doc = "Bit 3 - Represents MCPWM0_evt_op2_teb trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn mcpwm0_evt_op2_teb_st(&self) -> MCPWM0_EVT_OP2_TEB_ST_R {
        MCPWM0_EVT_OP2_TEB_ST_R::new(((self.bits >> 3) & 1) != 0)
    }
    #[doc = "Bit 4 - Represents MCPWM0_evt_f0 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn mcpwm0_evt_f0_st(&self) -> MCPWM0_EVT_F0_ST_R {
        MCPWM0_EVT_F0_ST_R::new(((self.bits >> 4) & 1) != 0)
    }
    #[doc = "Bit 5 - Represents MCPWM0_evt_f1 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn mcpwm0_evt_f1_st(&self) -> MCPWM0_EVT_F1_ST_R {
        MCPWM0_EVT_F1_ST_R::new(((self.bits >> 5) & 1) != 0)
    }
    #[doc = "Bit 6 - Represents MCPWM0_evt_f2 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn mcpwm0_evt_f2_st(&self) -> MCPWM0_EVT_F2_ST_R {
        MCPWM0_EVT_F2_ST_R::new(((self.bits >> 6) & 1) != 0)
    }
    #[doc = "Bit 7 - Represents MCPWM0_evt_f0_clr trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn mcpwm0_evt_f0_clr_st(&self) -> MCPWM0_EVT_F0_CLR_ST_R {
        MCPWM0_EVT_F0_CLR_ST_R::new(((self.bits >> 7) & 1) != 0)
    }
    #[doc = "Bit 8 - Represents MCPWM0_evt_f1_clr trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn mcpwm0_evt_f1_clr_st(&self) -> MCPWM0_EVT_F1_CLR_ST_R {
        MCPWM0_EVT_F1_CLR_ST_R::new(((self.bits >> 8) & 1) != 0)
    }
    #[doc = "Bit 9 - Represents MCPWM0_evt_f2_clr trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn mcpwm0_evt_f2_clr_st(&self) -> MCPWM0_EVT_F2_CLR_ST_R {
        MCPWM0_EVT_F2_CLR_ST_R::new(((self.bits >> 9) & 1) != 0)
    }
    #[doc = "Bit 10 - Represents MCPWM0_evt_tz0_cbc trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn mcpwm0_evt_tz0_cbc_st(&self) -> MCPWM0_EVT_TZ0_CBC_ST_R {
        MCPWM0_EVT_TZ0_CBC_ST_R::new(((self.bits >> 10) & 1) != 0)
    }
    #[doc = "Bit 11 - Represents MCPWM0_evt_tz1_cbc trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn mcpwm0_evt_tz1_cbc_st(&self) -> MCPWM0_EVT_TZ1_CBC_ST_R {
        MCPWM0_EVT_TZ1_CBC_ST_R::new(((self.bits >> 11) & 1) != 0)
    }
    #[doc = "Bit 12 - Represents MCPWM0_evt_tz2_cbc trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn mcpwm0_evt_tz2_cbc_st(&self) -> MCPWM0_EVT_TZ2_CBC_ST_R {
        MCPWM0_EVT_TZ2_CBC_ST_R::new(((self.bits >> 12) & 1) != 0)
    }
    #[doc = "Bit 13 - Represents MCPWM0_evt_tz0_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn mcpwm0_evt_tz0_ost_st(&self) -> MCPWM0_EVT_TZ0_OST_ST_R {
        MCPWM0_EVT_TZ0_OST_ST_R::new(((self.bits >> 13) & 1) != 0)
    }
    #[doc = "Bit 14 - Represents MCPWM0_evt_tz1_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn mcpwm0_evt_tz1_ost_st(&self) -> MCPWM0_EVT_TZ1_OST_ST_R {
        MCPWM0_EVT_TZ1_OST_ST_R::new(((self.bits >> 14) & 1) != 0)
    }
    #[doc = "Bit 15 - Represents MCPWM0_evt_tz2_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn mcpwm0_evt_tz2_ost_st(&self) -> MCPWM0_EVT_TZ2_OST_ST_R {
        MCPWM0_EVT_TZ2_OST_ST_R::new(((self.bits >> 15) & 1) != 0)
    }
    #[doc = "Bit 16 - Represents MCPWM0_evt_cap0 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn mcpwm0_evt_cap0_st(&self) -> MCPWM0_EVT_CAP0_ST_R {
        MCPWM0_EVT_CAP0_ST_R::new(((self.bits >> 16) & 1) != 0)
    }
    #[doc = "Bit 17 - Represents MCPWM0_evt_cap1 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn mcpwm0_evt_cap1_st(&self) -> MCPWM0_EVT_CAP1_ST_R {
        MCPWM0_EVT_CAP1_ST_R::new(((self.bits >> 17) & 1) != 0)
    }
    #[doc = "Bit 18 - Represents MCPWM0_evt_cap2 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn mcpwm0_evt_cap2_st(&self) -> MCPWM0_EVT_CAP2_ST_R {
        MCPWM0_EVT_CAP2_ST_R::new(((self.bits >> 18) & 1) != 0)
    }
    #[doc = "Bit 19 - Represents MCPWM0_evt_op0_tee1 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn mcpwm0_evt_op0_tee1_st(&self) -> MCPWM0_EVT_OP0_TEE1_ST_R {
        MCPWM0_EVT_OP0_TEE1_ST_R::new(((self.bits >> 19) & 1) != 0)
    }
    #[doc = "Bit 20 - Represents MCPWM0_evt_op1_tee1 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn mcpwm0_evt_op1_tee1_st(&self) -> MCPWM0_EVT_OP1_TEE1_ST_R {
        MCPWM0_EVT_OP1_TEE1_ST_R::new(((self.bits >> 20) & 1) != 0)
    }
    #[doc = "Bit 21 - Represents MCPWM0_evt_op2_tee1 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn mcpwm0_evt_op2_tee1_st(&self) -> MCPWM0_EVT_OP2_TEE1_ST_R {
        MCPWM0_EVT_OP2_TEE1_ST_R::new(((self.bits >> 21) & 1) != 0)
    }
    #[doc = "Bit 22 - Represents MCPWM0_evt_op0_tee2 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn mcpwm0_evt_op0_tee2_st(&self) -> MCPWM0_EVT_OP0_TEE2_ST_R {
        MCPWM0_EVT_OP0_TEE2_ST_R::new(((self.bits >> 22) & 1) != 0)
    }
    #[doc = "Bit 23 - Represents MCPWM0_evt_op1_tee2 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn mcpwm0_evt_op1_tee2_st(&self) -> MCPWM0_EVT_OP1_TEE2_ST_R {
        MCPWM0_EVT_OP1_TEE2_ST_R::new(((self.bits >> 23) & 1) != 0)
    }
    #[doc = "Bit 24 - Represents MCPWM0_evt_op2_tee2 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn mcpwm0_evt_op2_tee2_st(&self) -> MCPWM0_EVT_OP2_TEE2_ST_R {
        MCPWM0_EVT_OP2_TEE2_ST_R::new(((self.bits >> 24) & 1) != 0)
    }
    #[doc = "Bit 25 - Represents ADC_evt_conv_cmplt0 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn adc_evt_conv_cmplt0_st(&self) -> ADC_EVT_CONV_CMPLT0_ST_R {
        ADC_EVT_CONV_CMPLT0_ST_R::new(((self.bits >> 25) & 1) != 0)
    }
    #[doc = "Bit 26 - Represents ADC_evt_eq_above_thresh0 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn adc_evt_eq_above_thresh0_st(&self) -> ADC_EVT_EQ_ABOVE_THRESH0_ST_R {
        ADC_EVT_EQ_ABOVE_THRESH0_ST_R::new(((self.bits >> 26) & 1) != 0)
    }
    #[doc = "Bit 27 - Represents ADC_evt_eq_above_thresh1 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn adc_evt_eq_above_thresh1_st(&self) -> ADC_EVT_EQ_ABOVE_THRESH1_ST_R {
        ADC_EVT_EQ_ABOVE_THRESH1_ST_R::new(((self.bits >> 27) & 1) != 0)
    }
    #[doc = "Bit 28 - Represents ADC_evt_eq_below_thresh0 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn adc_evt_eq_below_thresh0_st(&self) -> ADC_EVT_EQ_BELOW_THRESH0_ST_R {
        ADC_EVT_EQ_BELOW_THRESH0_ST_R::new(((self.bits >> 28) & 1) != 0)
    }
    #[doc = "Bit 29 - Represents ADC_evt_eq_below_thresh1 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn adc_evt_eq_below_thresh1_st(&self) -> ADC_EVT_EQ_BELOW_THRESH1_ST_R {
        ADC_EVT_EQ_BELOW_THRESH1_ST_R::new(((self.bits >> 29) & 1) != 0)
    }
    #[doc = "Bit 30 - Represents ADC_evt_result_done0 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn adc_evt_result_done0_st(&self) -> ADC_EVT_RESULT_DONE0_ST_R {
        ADC_EVT_RESULT_DONE0_ST_R::new(((self.bits >> 30) & 1) != 0)
    }
    #[doc = "Bit 31 - Represents ADC_evt_stopped0 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn adc_evt_stopped0_st(&self) -> ADC_EVT_STOPPED0_ST_R {
        ADC_EVT_STOPPED0_ST_R::new(((self.bits >> 31) & 1) != 0)
    }
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for R {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("EVT_ST2")
            .field("mcpwm0_evt_op2_tea_st", &self.mcpwm0_evt_op2_tea_st())
            .field("mcpwm0_evt_op0_teb_st", &self.mcpwm0_evt_op0_teb_st())
            .field("mcpwm0_evt_op1_teb_st", &self.mcpwm0_evt_op1_teb_st())
            .field("mcpwm0_evt_op2_teb_st", &self.mcpwm0_evt_op2_teb_st())
            .field("mcpwm0_evt_f0_st", &self.mcpwm0_evt_f0_st())
            .field("mcpwm0_evt_f1_st", &self.mcpwm0_evt_f1_st())
            .field("mcpwm0_evt_f2_st", &self.mcpwm0_evt_f2_st())
            .field("mcpwm0_evt_f0_clr_st", &self.mcpwm0_evt_f0_clr_st())
            .field("mcpwm0_evt_f1_clr_st", &self.mcpwm0_evt_f1_clr_st())
            .field("mcpwm0_evt_f2_clr_st", &self.mcpwm0_evt_f2_clr_st())
            .field("mcpwm0_evt_tz0_cbc_st", &self.mcpwm0_evt_tz0_cbc_st())
            .field("mcpwm0_evt_tz1_cbc_st", &self.mcpwm0_evt_tz1_cbc_st())
            .field("mcpwm0_evt_tz2_cbc_st", &self.mcpwm0_evt_tz2_cbc_st())
            .field("mcpwm0_evt_tz0_ost_st", &self.mcpwm0_evt_tz0_ost_st())
            .field("mcpwm0_evt_tz1_ost_st", &self.mcpwm0_evt_tz1_ost_st())
            .field("mcpwm0_evt_tz2_ost_st", &self.mcpwm0_evt_tz2_ost_st())
            .field("mcpwm0_evt_cap0_st", &self.mcpwm0_evt_cap0_st())
            .field("mcpwm0_evt_cap1_st", &self.mcpwm0_evt_cap1_st())
            .field("mcpwm0_evt_cap2_st", &self.mcpwm0_evt_cap2_st())
            .field("mcpwm0_evt_op0_tee1_st", &self.mcpwm0_evt_op0_tee1_st())
            .field("mcpwm0_evt_op1_tee1_st", &self.mcpwm0_evt_op1_tee1_st())
            .field("mcpwm0_evt_op2_tee1_st", &self.mcpwm0_evt_op2_tee1_st())
            .field("mcpwm0_evt_op0_tee2_st", &self.mcpwm0_evt_op0_tee2_st())
            .field("mcpwm0_evt_op1_tee2_st", &self.mcpwm0_evt_op1_tee2_st())
            .field("mcpwm0_evt_op2_tee2_st", &self.mcpwm0_evt_op2_tee2_st())
            .field("adc_evt_conv_cmplt0_st", &self.adc_evt_conv_cmplt0_st())
            .field(
                "adc_evt_eq_above_thresh0_st",
                &self.adc_evt_eq_above_thresh0_st(),
            )
            .field(
                "adc_evt_eq_above_thresh1_st",
                &self.adc_evt_eq_above_thresh1_st(),
            )
            .field(
                "adc_evt_eq_below_thresh0_st",
                &self.adc_evt_eq_below_thresh0_st(),
            )
            .field(
                "adc_evt_eq_below_thresh1_st",
                &self.adc_evt_eq_below_thresh1_st(),
            )
            .field("adc_evt_result_done0_st", &self.adc_evt_result_done0_st())
            .field("adc_evt_stopped0_st", &self.adc_evt_stopped0_st())
            .finish()
    }
}
impl W {
    #[doc = "Bit 0 - Represents MCPWM0_evt_op2_tea trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn mcpwm0_evt_op2_tea_st(&mut self) -> MCPWM0_EVT_OP2_TEA_ST_W<'_, EVT_ST2_SPEC> {
        MCPWM0_EVT_OP2_TEA_ST_W::new(self, 0)
    }
    #[doc = "Bit 1 - Represents MCPWM0_evt_op0_teb trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn mcpwm0_evt_op0_teb_st(&mut self) -> MCPWM0_EVT_OP0_TEB_ST_W<'_, EVT_ST2_SPEC> {
        MCPWM0_EVT_OP0_TEB_ST_W::new(self, 1)
    }
    #[doc = "Bit 2 - Represents MCPWM0_evt_op1_teb trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn mcpwm0_evt_op1_teb_st(&mut self) -> MCPWM0_EVT_OP1_TEB_ST_W<'_, EVT_ST2_SPEC> {
        MCPWM0_EVT_OP1_TEB_ST_W::new(self, 2)
    }
    #[doc = "Bit 3 - Represents MCPWM0_evt_op2_teb trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn mcpwm0_evt_op2_teb_st(&mut self) -> MCPWM0_EVT_OP2_TEB_ST_W<'_, EVT_ST2_SPEC> {
        MCPWM0_EVT_OP2_TEB_ST_W::new(self, 3)
    }
    #[doc = "Bit 4 - Represents MCPWM0_evt_f0 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn mcpwm0_evt_f0_st(&mut self) -> MCPWM0_EVT_F0_ST_W<'_, EVT_ST2_SPEC> {
        MCPWM0_EVT_F0_ST_W::new(self, 4)
    }
    #[doc = "Bit 5 - Represents MCPWM0_evt_f1 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn mcpwm0_evt_f1_st(&mut self) -> MCPWM0_EVT_F1_ST_W<'_, EVT_ST2_SPEC> {
        MCPWM0_EVT_F1_ST_W::new(self, 5)
    }
    #[doc = "Bit 6 - Represents MCPWM0_evt_f2 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn mcpwm0_evt_f2_st(&mut self) -> MCPWM0_EVT_F2_ST_W<'_, EVT_ST2_SPEC> {
        MCPWM0_EVT_F2_ST_W::new(self, 6)
    }
    #[doc = "Bit 7 - Represents MCPWM0_evt_f0_clr trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn mcpwm0_evt_f0_clr_st(&mut self) -> MCPWM0_EVT_F0_CLR_ST_W<'_, EVT_ST2_SPEC> {
        MCPWM0_EVT_F0_CLR_ST_W::new(self, 7)
    }
    #[doc = "Bit 8 - Represents MCPWM0_evt_f1_clr trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn mcpwm0_evt_f1_clr_st(&mut self) -> MCPWM0_EVT_F1_CLR_ST_W<'_, EVT_ST2_SPEC> {
        MCPWM0_EVT_F1_CLR_ST_W::new(self, 8)
    }
    #[doc = "Bit 9 - Represents MCPWM0_evt_f2_clr trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn mcpwm0_evt_f2_clr_st(&mut self) -> MCPWM0_EVT_F2_CLR_ST_W<'_, EVT_ST2_SPEC> {
        MCPWM0_EVT_F2_CLR_ST_W::new(self, 9)
    }
    #[doc = "Bit 10 - Represents MCPWM0_evt_tz0_cbc trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn mcpwm0_evt_tz0_cbc_st(&mut self) -> MCPWM0_EVT_TZ0_CBC_ST_W<'_, EVT_ST2_SPEC> {
        MCPWM0_EVT_TZ0_CBC_ST_W::new(self, 10)
    }
    #[doc = "Bit 11 - Represents MCPWM0_evt_tz1_cbc trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn mcpwm0_evt_tz1_cbc_st(&mut self) -> MCPWM0_EVT_TZ1_CBC_ST_W<'_, EVT_ST2_SPEC> {
        MCPWM0_EVT_TZ1_CBC_ST_W::new(self, 11)
    }
    #[doc = "Bit 12 - Represents MCPWM0_evt_tz2_cbc trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn mcpwm0_evt_tz2_cbc_st(&mut self) -> MCPWM0_EVT_TZ2_CBC_ST_W<'_, EVT_ST2_SPEC> {
        MCPWM0_EVT_TZ2_CBC_ST_W::new(self, 12)
    }
    #[doc = "Bit 13 - Represents MCPWM0_evt_tz0_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn mcpwm0_evt_tz0_ost_st(&mut self) -> MCPWM0_EVT_TZ0_OST_ST_W<'_, EVT_ST2_SPEC> {
        MCPWM0_EVT_TZ0_OST_ST_W::new(self, 13)
    }
    #[doc = "Bit 14 - Represents MCPWM0_evt_tz1_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn mcpwm0_evt_tz1_ost_st(&mut self) -> MCPWM0_EVT_TZ1_OST_ST_W<'_, EVT_ST2_SPEC> {
        MCPWM0_EVT_TZ1_OST_ST_W::new(self, 14)
    }
    #[doc = "Bit 15 - Represents MCPWM0_evt_tz2_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn mcpwm0_evt_tz2_ost_st(&mut self) -> MCPWM0_EVT_TZ2_OST_ST_W<'_, EVT_ST2_SPEC> {
        MCPWM0_EVT_TZ2_OST_ST_W::new(self, 15)
    }
    #[doc = "Bit 16 - Represents MCPWM0_evt_cap0 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn mcpwm0_evt_cap0_st(&mut self) -> MCPWM0_EVT_CAP0_ST_W<'_, EVT_ST2_SPEC> {
        MCPWM0_EVT_CAP0_ST_W::new(self, 16)
    }
    #[doc = "Bit 17 - Represents MCPWM0_evt_cap1 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn mcpwm0_evt_cap1_st(&mut self) -> MCPWM0_EVT_CAP1_ST_W<'_, EVT_ST2_SPEC> {
        MCPWM0_EVT_CAP1_ST_W::new(self, 17)
    }
    #[doc = "Bit 18 - Represents MCPWM0_evt_cap2 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn mcpwm0_evt_cap2_st(&mut self) -> MCPWM0_EVT_CAP2_ST_W<'_, EVT_ST2_SPEC> {
        MCPWM0_EVT_CAP2_ST_W::new(self, 18)
    }
    #[doc = "Bit 19 - Represents MCPWM0_evt_op0_tee1 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn mcpwm0_evt_op0_tee1_st(&mut self) -> MCPWM0_EVT_OP0_TEE1_ST_W<'_, EVT_ST2_SPEC> {
        MCPWM0_EVT_OP0_TEE1_ST_W::new(self, 19)
    }
    #[doc = "Bit 20 - Represents MCPWM0_evt_op1_tee1 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn mcpwm0_evt_op1_tee1_st(&mut self) -> MCPWM0_EVT_OP1_TEE1_ST_W<'_, EVT_ST2_SPEC> {
        MCPWM0_EVT_OP1_TEE1_ST_W::new(self, 20)
    }
    #[doc = "Bit 21 - Represents MCPWM0_evt_op2_tee1 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn mcpwm0_evt_op2_tee1_st(&mut self) -> MCPWM0_EVT_OP2_TEE1_ST_W<'_, EVT_ST2_SPEC> {
        MCPWM0_EVT_OP2_TEE1_ST_W::new(self, 21)
    }
    #[doc = "Bit 22 - Represents MCPWM0_evt_op0_tee2 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn mcpwm0_evt_op0_tee2_st(&mut self) -> MCPWM0_EVT_OP0_TEE2_ST_W<'_, EVT_ST2_SPEC> {
        MCPWM0_EVT_OP0_TEE2_ST_W::new(self, 22)
    }
    #[doc = "Bit 23 - Represents MCPWM0_evt_op1_tee2 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn mcpwm0_evt_op1_tee2_st(&mut self) -> MCPWM0_EVT_OP1_TEE2_ST_W<'_, EVT_ST2_SPEC> {
        MCPWM0_EVT_OP1_TEE2_ST_W::new(self, 23)
    }
    #[doc = "Bit 24 - Represents MCPWM0_evt_op2_tee2 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn mcpwm0_evt_op2_tee2_st(&mut self) -> MCPWM0_EVT_OP2_TEE2_ST_W<'_, EVT_ST2_SPEC> {
        MCPWM0_EVT_OP2_TEE2_ST_W::new(self, 24)
    }
    #[doc = "Bit 25 - Represents ADC_evt_conv_cmplt0 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn adc_evt_conv_cmplt0_st(&mut self) -> ADC_EVT_CONV_CMPLT0_ST_W<'_, EVT_ST2_SPEC> {
        ADC_EVT_CONV_CMPLT0_ST_W::new(self, 25)
    }
    #[doc = "Bit 26 - Represents ADC_evt_eq_above_thresh0 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn adc_evt_eq_above_thresh0_st(
        &mut self,
    ) -> ADC_EVT_EQ_ABOVE_THRESH0_ST_W<'_, EVT_ST2_SPEC> {
        ADC_EVT_EQ_ABOVE_THRESH0_ST_W::new(self, 26)
    }
    #[doc = "Bit 27 - Represents ADC_evt_eq_above_thresh1 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn adc_evt_eq_above_thresh1_st(
        &mut self,
    ) -> ADC_EVT_EQ_ABOVE_THRESH1_ST_W<'_, EVT_ST2_SPEC> {
        ADC_EVT_EQ_ABOVE_THRESH1_ST_W::new(self, 27)
    }
    #[doc = "Bit 28 - Represents ADC_evt_eq_below_thresh0 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn adc_evt_eq_below_thresh0_st(
        &mut self,
    ) -> ADC_EVT_EQ_BELOW_THRESH0_ST_W<'_, EVT_ST2_SPEC> {
        ADC_EVT_EQ_BELOW_THRESH0_ST_W::new(self, 28)
    }
    #[doc = "Bit 29 - Represents ADC_evt_eq_below_thresh1 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn adc_evt_eq_below_thresh1_st(
        &mut self,
    ) -> ADC_EVT_EQ_BELOW_THRESH1_ST_W<'_, EVT_ST2_SPEC> {
        ADC_EVT_EQ_BELOW_THRESH1_ST_W::new(self, 29)
    }
    #[doc = "Bit 30 - Represents ADC_evt_result_done0 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn adc_evt_result_done0_st(&mut self) -> ADC_EVT_RESULT_DONE0_ST_W<'_, EVT_ST2_SPEC> {
        ADC_EVT_RESULT_DONE0_ST_W::new(self, 30)
    }
    #[doc = "Bit 31 - Represents ADC_evt_stopped0 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
    #[inline(always)]
    pub fn adc_evt_stopped0_st(&mut self) -> ADC_EVT_STOPPED0_ST_W<'_, EVT_ST2_SPEC> {
        ADC_EVT_STOPPED0_ST_W::new(self, 31)
    }
}
#[doc = "Events trigger status register\n\nYou can [`read`](crate::Reg::read) this register and get [`evt_st2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`evt_st2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EVT_ST2_SPEC;
impl crate::RegisterSpec for EVT_ST2_SPEC {
    type Ux = u32;
}
#[doc = "`read()` method returns [`evt_st2::R`](R) reader structure"]
impl crate::Readable for EVT_ST2_SPEC {}
#[doc = "`write(|w| ..)` method takes [`evt_st2::W`](W) writer structure"]
impl crate::Writable for EVT_ST2_SPEC {
    type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets EVT_ST2 to value 0"]
impl crate::Resettable for EVT_ST2_SPEC {}
