#[doc = "Register `CLK_CONF1_FORCE_ON` reader"]
pub type R = crate::R<CLK_CONF1_FORCE_ON_SPEC>;
#[doc = "Register `CLK_CONF1_FORCE_ON` writer"]
pub type W = crate::W<CLK_CONF1_FORCE_ON_SPEC>;
#[doc = "Field `CLK_WIFIBB_22M_FO` reader - "]
pub type CLK_WIFIBB_22M_FO_R = crate::BitReader;
#[doc = "Field `CLK_WIFIBB_22M_FO` writer - "]
pub type CLK_WIFIBB_22M_FO_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLK_WIFIBB_40M_FO` reader - "]
pub type CLK_WIFIBB_40M_FO_R = crate::BitReader;
#[doc = "Field `CLK_WIFIBB_40M_FO` writer - "]
pub type CLK_WIFIBB_40M_FO_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLK_WIFIBB_44M_FO` reader - "]
pub type CLK_WIFIBB_44M_FO_R = crate::BitReader;
#[doc = "Field `CLK_WIFIBB_44M_FO` writer - "]
pub type CLK_WIFIBB_44M_FO_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLK_WIFIBB_80M_FO` reader - "]
pub type CLK_WIFIBB_80M_FO_R = crate::BitReader;
#[doc = "Field `CLK_WIFIBB_80M_FO` writer - "]
pub type CLK_WIFIBB_80M_FO_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLK_WIFIBB_40X_FO` reader - "]
pub type CLK_WIFIBB_40X_FO_R = crate::BitReader;
#[doc = "Field `CLK_WIFIBB_40X_FO` writer - "]
pub type CLK_WIFIBB_40X_FO_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLK_WIFIBB_80X_FO` reader - "]
pub type CLK_WIFIBB_80X_FO_R = crate::BitReader;
#[doc = "Field `CLK_WIFIBB_80X_FO` writer - "]
pub type CLK_WIFIBB_80X_FO_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLK_WIFIBB_40X1_FO` reader - "]
pub type CLK_WIFIBB_40X1_FO_R = crate::BitReader;
#[doc = "Field `CLK_WIFIBB_40X1_FO` writer - "]
pub type CLK_WIFIBB_40X1_FO_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLK_WIFIBB_80X1_FO` reader - "]
pub type CLK_WIFIBB_80X1_FO_R = crate::BitReader;
#[doc = "Field `CLK_WIFIBB_80X1_FO` writer - "]
pub type CLK_WIFIBB_80X1_FO_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLK_WIFIBB_160X1_FO` reader - "]
pub type CLK_WIFIBB_160X1_FO_R = crate::BitReader;
#[doc = "Field `CLK_WIFIBB_160X1_FO` writer - "]
pub type CLK_WIFIBB_160X1_FO_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLK_WIFIMAC_FO` reader - "]
pub type CLK_WIFIMAC_FO_R = crate::BitReader;
#[doc = "Field `CLK_WIFIMAC_FO` writer - "]
pub type CLK_WIFIMAC_FO_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLK_WIFI_APB_FO` reader - "]
pub type CLK_WIFI_APB_FO_R = crate::BitReader;
#[doc = "Field `CLK_WIFI_APB_FO` writer - "]
pub type CLK_WIFI_APB_FO_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLK_FE_20M_FO` reader - "]
pub type CLK_FE_20M_FO_R = crate::BitReader;
#[doc = "Field `CLK_FE_20M_FO` writer - "]
pub type CLK_FE_20M_FO_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLK_FE_40M_FO` reader - "]
pub type CLK_FE_40M_FO_R = crate::BitReader;
#[doc = "Field `CLK_FE_40M_FO` writer - "]
pub type CLK_FE_40M_FO_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLK_FE_80M_FO` reader - "]
pub type CLK_FE_80M_FO_R = crate::BitReader;
#[doc = "Field `CLK_FE_80M_FO` writer - "]
pub type CLK_FE_80M_FO_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLK_FE_160M_FO` reader - "]
pub type CLK_FE_160M_FO_R = crate::BitReader;
#[doc = "Field `CLK_FE_160M_FO` writer - "]
pub type CLK_FE_160M_FO_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLK_FE_CAL_160M_FO` reader - "]
pub type CLK_FE_CAL_160M_FO_R = crate::BitReader;
#[doc = "Field `CLK_FE_CAL_160M_FO` writer - "]
pub type CLK_FE_CAL_160M_FO_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLK_FE_APB_FO` reader - "]
pub type CLK_FE_APB_FO_R = crate::BitReader;
#[doc = "Field `CLK_FE_APB_FO` writer - "]
pub type CLK_FE_APB_FO_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLK_BT_APB_FO` reader - "]
pub type CLK_BT_APB_FO_R = crate::BitReader;
#[doc = "Field `CLK_BT_APB_FO` writer - "]
pub type CLK_BT_APB_FO_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLK_BT_FO` reader - "]
pub type CLK_BT_FO_R = crate::BitReader;
#[doc = "Field `CLK_BT_FO` writer - "]
pub type CLK_BT_FO_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLK_WIFIBB_480M_FO` reader - "]
pub type CLK_WIFIBB_480M_FO_R = crate::BitReader;
#[doc = "Field `CLK_WIFIBB_480M_FO` writer - "]
pub type CLK_WIFIBB_480M_FO_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLK_FE_480M_FO` reader - "]
pub type CLK_FE_480M_FO_R = crate::BitReader;
#[doc = "Field `CLK_FE_480M_FO` writer - "]
pub type CLK_FE_480M_FO_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLK_FE_ANAMODE_40M_FO` reader - "]
pub type CLK_FE_ANAMODE_40M_FO_R = crate::BitReader;
#[doc = "Field `CLK_FE_ANAMODE_40M_FO` writer - "]
pub type CLK_FE_ANAMODE_40M_FO_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLK_FE_ANAMODE_80M_FO` reader - "]
pub type CLK_FE_ANAMODE_80M_FO_R = crate::BitReader;
#[doc = "Field `CLK_FE_ANAMODE_80M_FO` writer - "]
pub type CLK_FE_ANAMODE_80M_FO_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLK_FE_ANAMODE_160M_FO` reader - "]
pub type CLK_FE_ANAMODE_160M_FO_R = crate::BitReader;
#[doc = "Field `CLK_FE_ANAMODE_160M_FO` writer - "]
pub type CLK_FE_ANAMODE_160M_FO_W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
    #[doc = "Bit 0"]
    #[inline(always)]
    pub fn clk_wifibb_22m_fo(&self) -> CLK_WIFIBB_22M_FO_R {
        CLK_WIFIBB_22M_FO_R::new((self.bits & 1) != 0)
    }
    #[doc = "Bit 1"]
    #[inline(always)]
    pub fn clk_wifibb_40m_fo(&self) -> CLK_WIFIBB_40M_FO_R {
        CLK_WIFIBB_40M_FO_R::new(((self.bits >> 1) & 1) != 0)
    }
    #[doc = "Bit 2"]
    #[inline(always)]
    pub fn clk_wifibb_44m_fo(&self) -> CLK_WIFIBB_44M_FO_R {
        CLK_WIFIBB_44M_FO_R::new(((self.bits >> 2) & 1) != 0)
    }
    #[doc = "Bit 3"]
    #[inline(always)]
    pub fn clk_wifibb_80m_fo(&self) -> CLK_WIFIBB_80M_FO_R {
        CLK_WIFIBB_80M_FO_R::new(((self.bits >> 3) & 1) != 0)
    }
    #[doc = "Bit 4"]
    #[inline(always)]
    pub fn clk_wifibb_40x_fo(&self) -> CLK_WIFIBB_40X_FO_R {
        CLK_WIFIBB_40X_FO_R::new(((self.bits >> 4) & 1) != 0)
    }
    #[doc = "Bit 5"]
    #[inline(always)]
    pub fn clk_wifibb_80x_fo(&self) -> CLK_WIFIBB_80X_FO_R {
        CLK_WIFIBB_80X_FO_R::new(((self.bits >> 5) & 1) != 0)
    }
    #[doc = "Bit 6"]
    #[inline(always)]
    pub fn clk_wifibb_40x1_fo(&self) -> CLK_WIFIBB_40X1_FO_R {
        CLK_WIFIBB_40X1_FO_R::new(((self.bits >> 6) & 1) != 0)
    }
    #[doc = "Bit 7"]
    #[inline(always)]
    pub fn clk_wifibb_80x1_fo(&self) -> CLK_WIFIBB_80X1_FO_R {
        CLK_WIFIBB_80X1_FO_R::new(((self.bits >> 7) & 1) != 0)
    }
    #[doc = "Bit 8"]
    #[inline(always)]
    pub fn clk_wifibb_160x1_fo(&self) -> CLK_WIFIBB_160X1_FO_R {
        CLK_WIFIBB_160X1_FO_R::new(((self.bits >> 8) & 1) != 0)
    }
    #[doc = "Bit 9"]
    #[inline(always)]
    pub fn clk_wifimac_fo(&self) -> CLK_WIFIMAC_FO_R {
        CLK_WIFIMAC_FO_R::new(((self.bits >> 9) & 1) != 0)
    }
    #[doc = "Bit 10"]
    #[inline(always)]
    pub fn clk_wifi_apb_fo(&self) -> CLK_WIFI_APB_FO_R {
        CLK_WIFI_APB_FO_R::new(((self.bits >> 10) & 1) != 0)
    }
    #[doc = "Bit 11"]
    #[inline(always)]
    pub fn clk_fe_20m_fo(&self) -> CLK_FE_20M_FO_R {
        CLK_FE_20M_FO_R::new(((self.bits >> 11) & 1) != 0)
    }
    #[doc = "Bit 12"]
    #[inline(always)]
    pub fn clk_fe_40m_fo(&self) -> CLK_FE_40M_FO_R {
        CLK_FE_40M_FO_R::new(((self.bits >> 12) & 1) != 0)
    }
    #[doc = "Bit 13"]
    #[inline(always)]
    pub fn clk_fe_80m_fo(&self) -> CLK_FE_80M_FO_R {
        CLK_FE_80M_FO_R::new(((self.bits >> 13) & 1) != 0)
    }
    #[doc = "Bit 14"]
    #[inline(always)]
    pub fn clk_fe_160m_fo(&self) -> CLK_FE_160M_FO_R {
        CLK_FE_160M_FO_R::new(((self.bits >> 14) & 1) != 0)
    }
    #[doc = "Bit 15"]
    #[inline(always)]
    pub fn clk_fe_cal_160m_fo(&self) -> CLK_FE_CAL_160M_FO_R {
        CLK_FE_CAL_160M_FO_R::new(((self.bits >> 15) & 1) != 0)
    }
    #[doc = "Bit 16"]
    #[inline(always)]
    pub fn clk_fe_apb_fo(&self) -> CLK_FE_APB_FO_R {
        CLK_FE_APB_FO_R::new(((self.bits >> 16) & 1) != 0)
    }
    #[doc = "Bit 17"]
    #[inline(always)]
    pub fn clk_bt_apb_fo(&self) -> CLK_BT_APB_FO_R {
        CLK_BT_APB_FO_R::new(((self.bits >> 17) & 1) != 0)
    }
    #[doc = "Bit 18"]
    #[inline(always)]
    pub fn clk_bt_fo(&self) -> CLK_BT_FO_R {
        CLK_BT_FO_R::new(((self.bits >> 18) & 1) != 0)
    }
    #[doc = "Bit 19"]
    #[inline(always)]
    pub fn clk_wifibb_480m_fo(&self) -> CLK_WIFIBB_480M_FO_R {
        CLK_WIFIBB_480M_FO_R::new(((self.bits >> 19) & 1) != 0)
    }
    #[doc = "Bit 20"]
    #[inline(always)]
    pub fn clk_fe_480m_fo(&self) -> CLK_FE_480M_FO_R {
        CLK_FE_480M_FO_R::new(((self.bits >> 20) & 1) != 0)
    }
    #[doc = "Bit 21"]
    #[inline(always)]
    pub fn clk_fe_anamode_40m_fo(&self) -> CLK_FE_ANAMODE_40M_FO_R {
        CLK_FE_ANAMODE_40M_FO_R::new(((self.bits >> 21) & 1) != 0)
    }
    #[doc = "Bit 22"]
    #[inline(always)]
    pub fn clk_fe_anamode_80m_fo(&self) -> CLK_FE_ANAMODE_80M_FO_R {
        CLK_FE_ANAMODE_80M_FO_R::new(((self.bits >> 22) & 1) != 0)
    }
    #[doc = "Bit 23"]
    #[inline(always)]
    pub fn clk_fe_anamode_160m_fo(&self) -> CLK_FE_ANAMODE_160M_FO_R {
        CLK_FE_ANAMODE_160M_FO_R::new(((self.bits >> 23) & 1) != 0)
    }
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for R {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("CLK_CONF1_FORCE_ON")
            .field("clk_wifibb_22m_fo", &self.clk_wifibb_22m_fo())
            .field("clk_wifibb_40m_fo", &self.clk_wifibb_40m_fo())
            .field("clk_wifibb_44m_fo", &self.clk_wifibb_44m_fo())
            .field("clk_wifibb_80m_fo", &self.clk_wifibb_80m_fo())
            .field("clk_wifibb_40x_fo", &self.clk_wifibb_40x_fo())
            .field("clk_wifibb_80x_fo", &self.clk_wifibb_80x_fo())
            .field("clk_wifibb_40x1_fo", &self.clk_wifibb_40x1_fo())
            .field("clk_wifibb_80x1_fo", &self.clk_wifibb_80x1_fo())
            .field("clk_wifibb_160x1_fo", &self.clk_wifibb_160x1_fo())
            .field("clk_wifimac_fo", &self.clk_wifimac_fo())
            .field("clk_wifi_apb_fo", &self.clk_wifi_apb_fo())
            .field("clk_fe_20m_fo", &self.clk_fe_20m_fo())
            .field("clk_fe_40m_fo", &self.clk_fe_40m_fo())
            .field("clk_fe_80m_fo", &self.clk_fe_80m_fo())
            .field("clk_fe_160m_fo", &self.clk_fe_160m_fo())
            .field("clk_fe_cal_160m_fo", &self.clk_fe_cal_160m_fo())
            .field("clk_fe_apb_fo", &self.clk_fe_apb_fo())
            .field("clk_bt_apb_fo", &self.clk_bt_apb_fo())
            .field("clk_bt_fo", &self.clk_bt_fo())
            .field("clk_wifibb_480m_fo", &self.clk_wifibb_480m_fo())
            .field("clk_fe_480m_fo", &self.clk_fe_480m_fo())
            .field("clk_fe_anamode_40m_fo", &self.clk_fe_anamode_40m_fo())
            .field("clk_fe_anamode_80m_fo", &self.clk_fe_anamode_80m_fo())
            .field("clk_fe_anamode_160m_fo", &self.clk_fe_anamode_160m_fo())
            .finish()
    }
}
impl W {
    #[doc = "Bit 0"]
    #[inline(always)]
    pub fn clk_wifibb_22m_fo(&mut self) -> CLK_WIFIBB_22M_FO_W<'_, CLK_CONF1_FORCE_ON_SPEC> {
        CLK_WIFIBB_22M_FO_W::new(self, 0)
    }
    #[doc = "Bit 1"]
    #[inline(always)]
    pub fn clk_wifibb_40m_fo(&mut self) -> CLK_WIFIBB_40M_FO_W<'_, CLK_CONF1_FORCE_ON_SPEC> {
        CLK_WIFIBB_40M_FO_W::new(self, 1)
    }
    #[doc = "Bit 2"]
    #[inline(always)]
    pub fn clk_wifibb_44m_fo(&mut self) -> CLK_WIFIBB_44M_FO_W<'_, CLK_CONF1_FORCE_ON_SPEC> {
        CLK_WIFIBB_44M_FO_W::new(self, 2)
    }
    #[doc = "Bit 3"]
    #[inline(always)]
    pub fn clk_wifibb_80m_fo(&mut self) -> CLK_WIFIBB_80M_FO_W<'_, CLK_CONF1_FORCE_ON_SPEC> {
        CLK_WIFIBB_80M_FO_W::new(self, 3)
    }
    #[doc = "Bit 4"]
    #[inline(always)]
    pub fn clk_wifibb_40x_fo(&mut self) -> CLK_WIFIBB_40X_FO_W<'_, CLK_CONF1_FORCE_ON_SPEC> {
        CLK_WIFIBB_40X_FO_W::new(self, 4)
    }
    #[doc = "Bit 5"]
    #[inline(always)]
    pub fn clk_wifibb_80x_fo(&mut self) -> CLK_WIFIBB_80X_FO_W<'_, CLK_CONF1_FORCE_ON_SPEC> {
        CLK_WIFIBB_80X_FO_W::new(self, 5)
    }
    #[doc = "Bit 6"]
    #[inline(always)]
    pub fn clk_wifibb_40x1_fo(&mut self) -> CLK_WIFIBB_40X1_FO_W<'_, CLK_CONF1_FORCE_ON_SPEC> {
        CLK_WIFIBB_40X1_FO_W::new(self, 6)
    }
    #[doc = "Bit 7"]
    #[inline(always)]
    pub fn clk_wifibb_80x1_fo(&mut self) -> CLK_WIFIBB_80X1_FO_W<'_, CLK_CONF1_FORCE_ON_SPEC> {
        CLK_WIFIBB_80X1_FO_W::new(self, 7)
    }
    #[doc = "Bit 8"]
    #[inline(always)]
    pub fn clk_wifibb_160x1_fo(&mut self) -> CLK_WIFIBB_160X1_FO_W<'_, CLK_CONF1_FORCE_ON_SPEC> {
        CLK_WIFIBB_160X1_FO_W::new(self, 8)
    }
    #[doc = "Bit 9"]
    #[inline(always)]
    pub fn clk_wifimac_fo(&mut self) -> CLK_WIFIMAC_FO_W<'_, CLK_CONF1_FORCE_ON_SPEC> {
        CLK_WIFIMAC_FO_W::new(self, 9)
    }
    #[doc = "Bit 10"]
    #[inline(always)]
    pub fn clk_wifi_apb_fo(&mut self) -> CLK_WIFI_APB_FO_W<'_, CLK_CONF1_FORCE_ON_SPEC> {
        CLK_WIFI_APB_FO_W::new(self, 10)
    }
    #[doc = "Bit 11"]
    #[inline(always)]
    pub fn clk_fe_20m_fo(&mut self) -> CLK_FE_20M_FO_W<'_, CLK_CONF1_FORCE_ON_SPEC> {
        CLK_FE_20M_FO_W::new(self, 11)
    }
    #[doc = "Bit 12"]
    #[inline(always)]
    pub fn clk_fe_40m_fo(&mut self) -> CLK_FE_40M_FO_W<'_, CLK_CONF1_FORCE_ON_SPEC> {
        CLK_FE_40M_FO_W::new(self, 12)
    }
    #[doc = "Bit 13"]
    #[inline(always)]
    pub fn clk_fe_80m_fo(&mut self) -> CLK_FE_80M_FO_W<'_, CLK_CONF1_FORCE_ON_SPEC> {
        CLK_FE_80M_FO_W::new(self, 13)
    }
    #[doc = "Bit 14"]
    #[inline(always)]
    pub fn clk_fe_160m_fo(&mut self) -> CLK_FE_160M_FO_W<'_, CLK_CONF1_FORCE_ON_SPEC> {
        CLK_FE_160M_FO_W::new(self, 14)
    }
    #[doc = "Bit 15"]
    #[inline(always)]
    pub fn clk_fe_cal_160m_fo(&mut self) -> CLK_FE_CAL_160M_FO_W<'_, CLK_CONF1_FORCE_ON_SPEC> {
        CLK_FE_CAL_160M_FO_W::new(self, 15)
    }
    #[doc = "Bit 16"]
    #[inline(always)]
    pub fn clk_fe_apb_fo(&mut self) -> CLK_FE_APB_FO_W<'_, CLK_CONF1_FORCE_ON_SPEC> {
        CLK_FE_APB_FO_W::new(self, 16)
    }
    #[doc = "Bit 17"]
    #[inline(always)]
    pub fn clk_bt_apb_fo(&mut self) -> CLK_BT_APB_FO_W<'_, CLK_CONF1_FORCE_ON_SPEC> {
        CLK_BT_APB_FO_W::new(self, 17)
    }
    #[doc = "Bit 18"]
    #[inline(always)]
    pub fn clk_bt_fo(&mut self) -> CLK_BT_FO_W<'_, CLK_CONF1_FORCE_ON_SPEC> {
        CLK_BT_FO_W::new(self, 18)
    }
    #[doc = "Bit 19"]
    #[inline(always)]
    pub fn clk_wifibb_480m_fo(&mut self) -> CLK_WIFIBB_480M_FO_W<'_, CLK_CONF1_FORCE_ON_SPEC> {
        CLK_WIFIBB_480M_FO_W::new(self, 19)
    }
    #[doc = "Bit 20"]
    #[inline(always)]
    pub fn clk_fe_480m_fo(&mut self) -> CLK_FE_480M_FO_W<'_, CLK_CONF1_FORCE_ON_SPEC> {
        CLK_FE_480M_FO_W::new(self, 20)
    }
    #[doc = "Bit 21"]
    #[inline(always)]
    pub fn clk_fe_anamode_40m_fo(
        &mut self,
    ) -> CLK_FE_ANAMODE_40M_FO_W<'_, CLK_CONF1_FORCE_ON_SPEC> {
        CLK_FE_ANAMODE_40M_FO_W::new(self, 21)
    }
    #[doc = "Bit 22"]
    #[inline(always)]
    pub fn clk_fe_anamode_80m_fo(
        &mut self,
    ) -> CLK_FE_ANAMODE_80M_FO_W<'_, CLK_CONF1_FORCE_ON_SPEC> {
        CLK_FE_ANAMODE_80M_FO_W::new(self, 22)
    }
    #[doc = "Bit 23"]
    #[inline(always)]
    pub fn clk_fe_anamode_160m_fo(
        &mut self,
    ) -> CLK_FE_ANAMODE_160M_FO_W<'_, CLK_CONF1_FORCE_ON_SPEC> {
        CLK_FE_ANAMODE_160M_FO_W::new(self, 23)
    }
}
#[doc = "\n\nYou can [`read`](crate::Reg::read) this register and get [`clk_conf1_force_on::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_conf1_force_on::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CLK_CONF1_FORCE_ON_SPEC;
impl crate::RegisterSpec for CLK_CONF1_FORCE_ON_SPEC {
    type Ux = u32;
}
#[doc = "`read()` method returns [`clk_conf1_force_on::R`](R) reader structure"]
impl crate::Readable for CLK_CONF1_FORCE_ON_SPEC {}
#[doc = "`write(|w| ..)` method takes [`clk_conf1_force_on::W`](W) writer structure"]
impl crate::Writable for CLK_CONF1_FORCE_ON_SPEC {
    type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets CLK_CONF1_FORCE_ON to value 0"]
impl crate::Resettable for CLK_CONF1_FORCE_ON_SPEC {}
