#![doc = "Peripheral access API for ESP32-S2 microcontrollers (generated using svd2rust v0.37.1 (f74f0b3 2026-04-17))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next] svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.37.1/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"]
#![allow(non_camel_case_types)]
#![allow(non_snake_case)]
#![doc(html_logo_url = "https://avatars.githubusercontent.com/u/46717278")]
#![no_std]
#![cfg_attr(docsrs, feature(doc_cfg))]
#[doc = r"Number available in the NVIC for configuring priority"]
pub const NVIC_PRIO_BITS: u8 = 0;
#[allow(unused_imports)]
use generic::*;
#[doc = r"Common register and bit access and modify traits"]
pub mod generic;
#[cfg(feature = "rt")]
extern "C" {
    fn WIFI_MAC();
    fn WIFI_NMI();
    fn WIFI_PWR();
    fn WIFI_BB();
    fn BT_MAC();
    fn BT_BB();
    fn BT_BB_NMI();
    fn RWBT();
    fn RWBLE();
    fn RWBT_NMI();
    fn RWBLE_NMI();
    fn SLC0();
    fn SLC1();
    fn UHCI0();
    fn UHCI1();
    fn TG0_T0_LEVEL();
    fn TG0_T1_LEVEL();
    fn TG0_WDT_LEVEL();
    fn TG0_LACT_LEVEL();
    fn TG1_T0_LEVEL();
    fn TG1_T1_LEVEL();
    fn TG1_WDT_LEVEL();
    fn TG1_LACT_LEVEL();
    fn GPIO();
    fn GPIO_NMI();
    fn GPIO_INTR_2();
    fn GPIO_NMI_2();
    fn DEDICATED_GPIO();
    fn FROM_CPU_INTR0();
    fn FROM_CPU_INTR1();
    fn FROM_CPU_INTR2();
    fn FROM_CPU_INTR3();
    fn SPI1();
    fn SPI2();
    fn SPI3();
    fn I2S0();
    fn I2S1();
    fn UART0();
    fn UART1();
    fn UART2();
    fn SDIO_HOST();
    fn LEDC();
    fn EFUSE();
    fn TWAI0();
    fn USB();
    fn RTC_CORE();
    fn RMT();
    fn PCNT();
    fn I2C_EXT0();
    fn I2C_EXT1();
    fn RSA();
    fn SHA();
    fn AES();
    fn SPI2_DMA();
    fn SPI3_DMA();
    fn WDT();
    fn TIMER1();
    fn TIMER2();
    fn TG0_T0_EDGE();
    fn TG0_T1_EDGE();
    fn TG0_WDT_EDGE();
    fn TG0_LACT_EDGE();
    fn TG1_T0_EDGE();
    fn TG1_T1_EDGE();
    fn TG1_WDT_EDGE();
    fn TG1_LACT_EDGE();
    fn CACHE_IA();
    fn SYSTIMER_TARGET0();
    fn SYSTIMER_TARGET1();
    fn SYSTIMER_TARGET2();
    fn PMS_PRO_IRAM0_ILG();
    fn PMS_PRO_DRAM0_ILG();
    fn PMS_PRO_DPORT_ILG();
    fn PMS_PRO_AHB_ILG();
    fn PMS_PRO_CACHE_ILG();
    fn PMS_DMA_APB_I_ILG();
    fn PMS_DMA_RX_I_ILG();
    fn PMS_DMA_TX_I_ILG();
    fn SPI0_REJECT_CACHE();
    fn DMA_COPY();
    fn SPI4_DMA();
    fn SPI4();
    fn ICACHE_PRELOAD();
    fn DCACHE_PRELOAD();
    fn APB_ADC();
    fn CRYPTO_DMA();
    fn CPU_PERI_ERR();
    fn APB_PERI_ERR();
    fn DCACHE_SYNC();
    fn ICACHE_SYNC();
}
#[doc(hidden)]
#[repr(C)]
pub union Vector {
    pub _handler: unsafe extern "C" fn(),
    _reserved: u32,
}
#[cfg(feature = "rt")]
#[doc(hidden)]
#[link_section = ".rwtext"]
#[no_mangle]
pub static __INTERRUPTS: [Vector; 95] = [
    Vector { _handler: WIFI_MAC },
    Vector { _handler: WIFI_NMI },
    Vector { _handler: WIFI_PWR },
    Vector { _handler: WIFI_BB },
    Vector { _handler: BT_MAC },
    Vector { _handler: BT_BB },
    Vector {
        _handler: BT_BB_NMI,
    },
    Vector { _handler: RWBT },
    Vector { _handler: RWBLE },
    Vector { _handler: RWBT_NMI },
    Vector {
        _handler: RWBLE_NMI,
    },
    Vector { _handler: SLC0 },
    Vector { _handler: SLC1 },
    Vector { _handler: UHCI0 },
    Vector { _handler: UHCI1 },
    Vector {
        _handler: TG0_T0_LEVEL,
    },
    Vector {
        _handler: TG0_T1_LEVEL,
    },
    Vector {
        _handler: TG0_WDT_LEVEL,
    },
    Vector {
        _handler: TG0_LACT_LEVEL,
    },
    Vector {
        _handler: TG1_T0_LEVEL,
    },
    Vector {
        _handler: TG1_T1_LEVEL,
    },
    Vector {
        _handler: TG1_WDT_LEVEL,
    },
    Vector {
        _handler: TG1_LACT_LEVEL,
    },
    Vector { _handler: GPIO },
    Vector { _handler: GPIO_NMI },
    Vector {
        _handler: GPIO_INTR_2,
    },
    Vector {
        _handler: GPIO_NMI_2,
    },
    Vector {
        _handler: DEDICATED_GPIO,
    },
    Vector {
        _handler: FROM_CPU_INTR0,
    },
    Vector {
        _handler: FROM_CPU_INTR1,
    },
    Vector {
        _handler: FROM_CPU_INTR2,
    },
    Vector {
        _handler: FROM_CPU_INTR3,
    },
    Vector { _handler: SPI1 },
    Vector { _handler: SPI2 },
    Vector { _handler: SPI3 },
    Vector { _handler: I2S0 },
    Vector { _handler: I2S1 },
    Vector { _handler: UART0 },
    Vector { _handler: UART1 },
    Vector { _handler: UART2 },
    Vector {
        _handler: SDIO_HOST,
    },
    Vector { _reserved: 0 },
    Vector { _reserved: 0 },
    Vector { _reserved: 0 },
    Vector { _reserved: 0 },
    Vector { _handler: LEDC },
    Vector { _handler: EFUSE },
    Vector { _handler: TWAI0 },
    Vector { _handler: USB },
    Vector { _handler: RTC_CORE },
    Vector { _handler: RMT },
    Vector { _handler: PCNT },
    Vector { _handler: I2C_EXT0 },
    Vector { _handler: I2C_EXT1 },
    Vector { _handler: RSA },
    Vector { _handler: SHA },
    Vector { _handler: AES },
    Vector { _handler: SPI2_DMA },
    Vector { _handler: SPI3_DMA },
    Vector { _handler: WDT },
    Vector { _handler: TIMER1 },
    Vector { _handler: TIMER2 },
    Vector {
        _handler: TG0_T0_EDGE,
    },
    Vector {
        _handler: TG0_T1_EDGE,
    },
    Vector {
        _handler: TG0_WDT_EDGE,
    },
    Vector {
        _handler: TG0_LACT_EDGE,
    },
    Vector {
        _handler: TG1_T0_EDGE,
    },
    Vector {
        _handler: TG1_T1_EDGE,
    },
    Vector {
        _handler: TG1_WDT_EDGE,
    },
    Vector {
        _handler: TG1_LACT_EDGE,
    },
    Vector { _handler: CACHE_IA },
    Vector {
        _handler: SYSTIMER_TARGET0,
    },
    Vector {
        _handler: SYSTIMER_TARGET1,
    },
    Vector {
        _handler: SYSTIMER_TARGET2,
    },
    Vector { _reserved: 0 },
    Vector {
        _handler: PMS_PRO_IRAM0_ILG,
    },
    Vector {
        _handler: PMS_PRO_DRAM0_ILG,
    },
    Vector {
        _handler: PMS_PRO_DPORT_ILG,
    },
    Vector {
        _handler: PMS_PRO_AHB_ILG,
    },
    Vector {
        _handler: PMS_PRO_CACHE_ILG,
    },
    Vector {
        _handler: PMS_DMA_APB_I_ILG,
    },
    Vector {
        _handler: PMS_DMA_RX_I_ILG,
    },
    Vector {
        _handler: PMS_DMA_TX_I_ILG,
    },
    Vector {
        _handler: SPI0_REJECT_CACHE,
    },
    Vector { _handler: DMA_COPY },
    Vector { _handler: SPI4_DMA },
    Vector { _handler: SPI4 },
    Vector {
        _handler: ICACHE_PRELOAD,
    },
    Vector {
        _handler: DCACHE_PRELOAD,
    },
    Vector { _handler: APB_ADC },
    Vector {
        _handler: CRYPTO_DMA,
    },
    Vector {
        _handler: CPU_PERI_ERR,
    },
    Vector {
        _handler: APB_PERI_ERR,
    },
    Vector {
        _handler: DCACHE_SYNC,
    },
    Vector {
        _handler: ICACHE_SYNC,
    },
];
#[doc = r"Enumeration of all the interrupts."]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
#[repr(u16)]
pub enum Interrupt {
    #[doc = "0 - WIFI_MAC"]
    WIFI_MAC          = 0,
    #[doc = "1 - WIFI_NMI"]
    WIFI_NMI          = 1,
    #[doc = "2 - WIFI_PWR"]
    WIFI_PWR          = 2,
    #[doc = "3 - WIFI_BB"]
    WIFI_BB           = 3,
    #[doc = "4 - BT_MAC"]
    BT_MAC            = 4,
    #[doc = "5 - BT_BB"]
    BT_BB             = 5,
    #[doc = "6 - BT_BB_NMI"]
    BT_BB_NMI         = 6,
    #[doc = "7 - RWBT"]
    RWBT              = 7,
    #[doc = "8 - RWBLE"]
    RWBLE             = 8,
    #[doc = "9 - RWBT_NMI"]
    RWBT_NMI          = 9,
    #[doc = "10 - RWBLE_NMI"]
    RWBLE_NMI         = 10,
    #[doc = "11 - SLC0"]
    SLC0              = 11,
    #[doc = "12 - SLC1"]
    SLC1              = 12,
    #[doc = "13 - UHCI0"]
    UHCI0             = 13,
    #[doc = "14 - UHCI1"]
    UHCI1             = 14,
    #[doc = "15 - TG0_T0_LEVEL"]
    TG0_T0_LEVEL      = 15,
    #[doc = "16 - TG0_T1_LEVEL"]
    TG0_T1_LEVEL      = 16,
    #[doc = "17 - TG0_WDT_LEVEL"]
    TG0_WDT_LEVEL     = 17,
    #[doc = "18 - TG0_LACT_LEVEL"]
    TG0_LACT_LEVEL    = 18,
    #[doc = "19 - TG1_T0_LEVEL"]
    TG1_T0_LEVEL      = 19,
    #[doc = "20 - TG1_T1_LEVEL"]
    TG1_T1_LEVEL      = 20,
    #[doc = "21 - TG1_WDT_LEVEL"]
    TG1_WDT_LEVEL     = 21,
    #[doc = "22 - TG1_LACT_LEVEL"]
    TG1_LACT_LEVEL    = 22,
    #[doc = "23 - GPIO"]
    GPIO              = 23,
    #[doc = "24 - GPIO_NMI"]
    GPIO_NMI          = 24,
    #[doc = "25 - GPIO_INTR_2"]
    GPIO_INTR_2       = 25,
    #[doc = "26 - GPIO_NMI_2"]
    GPIO_NMI_2        = 26,
    #[doc = "27 - DEDICATED_GPIO"]
    DEDICATED_GPIO    = 27,
    #[doc = "28 - FROM_CPU_INTR0"]
    FROM_CPU_INTR0    = 28,
    #[doc = "29 - FROM_CPU_INTR1"]
    FROM_CPU_INTR1    = 29,
    #[doc = "30 - FROM_CPU_INTR2"]
    FROM_CPU_INTR2    = 30,
    #[doc = "31 - FROM_CPU_INTR3"]
    FROM_CPU_INTR3    = 31,
    #[doc = "32 - SPI1"]
    SPI1              = 32,
    #[doc = "33 - SPI2"]
    SPI2              = 33,
    #[doc = "34 - SPI3"]
    SPI3              = 34,
    #[doc = "35 - I2S0"]
    I2S0              = 35,
    #[doc = "36 - I2S1"]
    I2S1              = 36,
    #[doc = "37 - UART0"]
    UART0             = 37,
    #[doc = "38 - UART1"]
    UART1             = 38,
    #[doc = "39 - UART2"]
    UART2             = 39,
    #[doc = "40 - SDIO_HOST"]
    SDIO_HOST         = 40,
    #[doc = "45 - LEDC"]
    LEDC              = 45,
    #[doc = "46 - EFUSE"]
    EFUSE             = 46,
    #[doc = "47 - TWAI0"]
    TWAI0             = 47,
    #[doc = "48 - USB"]
    USB               = 48,
    #[doc = "49 - RTC_CORE"]
    RTC_CORE          = 49,
    #[doc = "50 - RMT"]
    RMT               = 50,
    #[doc = "51 - PCNT"]
    PCNT              = 51,
    #[doc = "52 - I2C_EXT0"]
    I2C_EXT0          = 52,
    #[doc = "53 - I2C_EXT1"]
    I2C_EXT1          = 53,
    #[doc = "54 - RSA"]
    RSA               = 54,
    #[doc = "55 - SHA"]
    SHA               = 55,
    #[doc = "56 - AES"]
    AES               = 56,
    #[doc = "57 - SPI2_DMA"]
    SPI2_DMA          = 57,
    #[doc = "58 - SPI3_DMA"]
    SPI3_DMA          = 58,
    #[doc = "59 - WDT"]
    WDT               = 59,
    #[doc = "60 - TIMER1"]
    TIMER1            = 60,
    #[doc = "61 - TIMER2"]
    TIMER2            = 61,
    #[doc = "62 - TG0_T0_EDGE"]
    TG0_T0_EDGE       = 62,
    #[doc = "63 - TG0_T1_EDGE"]
    TG0_T1_EDGE       = 63,
    #[doc = "64 - TG0_WDT_EDGE"]
    TG0_WDT_EDGE      = 64,
    #[doc = "65 - TG0_LACT_EDGE"]
    TG0_LACT_EDGE     = 65,
    #[doc = "66 - TG1_T0_EDGE"]
    TG1_T0_EDGE       = 66,
    #[doc = "67 - TG1_T1_EDGE"]
    TG1_T1_EDGE       = 67,
    #[doc = "68 - TG1_WDT_EDGE"]
    TG1_WDT_EDGE      = 68,
    #[doc = "69 - TG1_LACT_EDGE"]
    TG1_LACT_EDGE     = 69,
    #[doc = "70 - CACHE_IA"]
    CACHE_IA          = 70,
    #[doc = "71 - SYSTIMER_TARGET0"]
    SYSTIMER_TARGET0  = 71,
    #[doc = "72 - SYSTIMER_TARGET1"]
    SYSTIMER_TARGET1  = 72,
    #[doc = "73 - SYSTIMER_TARGET2"]
    SYSTIMER_TARGET2  = 73,
    #[doc = "75 - PMS_PRO_IRAM0_ILG"]
    PMS_PRO_IRAM0_ILG = 75,
    #[doc = "76 - PMS_PRO_DRAM0_ILG"]
    PMS_PRO_DRAM0_ILG = 76,
    #[doc = "77 - PMS_PRO_DPORT_ILG"]
    PMS_PRO_DPORT_ILG = 77,
    #[doc = "78 - PMS_PRO_AHB_ILG"]
    PMS_PRO_AHB_ILG   = 78,
    #[doc = "79 - PMS_PRO_CACHE_ILG"]
    PMS_PRO_CACHE_ILG = 79,
    #[doc = "80 - PMS_DMA_APB_I_ILG"]
    PMS_DMA_APB_I_ILG = 80,
    #[doc = "81 - PMS_DMA_RX_I_ILG"]
    PMS_DMA_RX_I_ILG  = 81,
    #[doc = "82 - PMS_DMA_TX_I_ILG"]
    PMS_DMA_TX_I_ILG  = 82,
    #[doc = "83 - SPI0_REJECT_CACHE"]
    SPI0_REJECT_CACHE = 83,
    #[doc = "84 - DMA_COPY"]
    DMA_COPY          = 84,
    #[doc = "85 - SPI4_DMA"]
    SPI4_DMA          = 85,
    #[doc = "86 - SPI4"]
    SPI4              = 86,
    #[doc = "87 - ICACHE_PRELOAD"]
    ICACHE_PRELOAD    = 87,
    #[doc = "88 - DCACHE_PRELOAD"]
    DCACHE_PRELOAD    = 88,
    #[doc = "89 - APB_ADC"]
    APB_ADC           = 89,
    #[doc = "90 - CRYPTO_DMA"]
    CRYPTO_DMA        = 90,
    #[doc = "91 - CPU_PERI_ERR"]
    CPU_PERI_ERR      = 91,
    #[doc = "92 - APB_PERI_ERR"]
    APB_PERI_ERR      = 92,
    #[doc = "93 - DCACHE_SYNC"]
    DCACHE_SYNC       = 93,
    #[doc = "94 - ICACHE_SYNC"]
    ICACHE_SYNC       = 94,
}
#[doc = r" TryFromInterruptError"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Debug, Copy, Clone)]
pub struct TryFromInterruptError(());
impl Interrupt {
    #[doc = r" Attempt to convert a given value into an `Interrupt`"]
    #[inline]
    pub fn try_from(value: u16) -> Result<Self, TryFromInterruptError> {
        match value {
            0 => Ok(Interrupt::WIFI_MAC),
            1 => Ok(Interrupt::WIFI_NMI),
            2 => Ok(Interrupt::WIFI_PWR),
            3 => Ok(Interrupt::WIFI_BB),
            4 => Ok(Interrupt::BT_MAC),
            5 => Ok(Interrupt::BT_BB),
            6 => Ok(Interrupt::BT_BB_NMI),
            7 => Ok(Interrupt::RWBT),
            8 => Ok(Interrupt::RWBLE),
            9 => Ok(Interrupt::RWBT_NMI),
            10 => Ok(Interrupt::RWBLE_NMI),
            11 => Ok(Interrupt::SLC0),
            12 => Ok(Interrupt::SLC1),
            13 => Ok(Interrupt::UHCI0),
            14 => Ok(Interrupt::UHCI1),
            15 => Ok(Interrupt::TG0_T0_LEVEL),
            16 => Ok(Interrupt::TG0_T1_LEVEL),
            17 => Ok(Interrupt::TG0_WDT_LEVEL),
            18 => Ok(Interrupt::TG0_LACT_LEVEL),
            19 => Ok(Interrupt::TG1_T0_LEVEL),
            20 => Ok(Interrupt::TG1_T1_LEVEL),
            21 => Ok(Interrupt::TG1_WDT_LEVEL),
            22 => Ok(Interrupt::TG1_LACT_LEVEL),
            23 => Ok(Interrupt::GPIO),
            24 => Ok(Interrupt::GPIO_NMI),
            25 => Ok(Interrupt::GPIO_INTR_2),
            26 => Ok(Interrupt::GPIO_NMI_2),
            27 => Ok(Interrupt::DEDICATED_GPIO),
            28 => Ok(Interrupt::FROM_CPU_INTR0),
            29 => Ok(Interrupt::FROM_CPU_INTR1),
            30 => Ok(Interrupt::FROM_CPU_INTR2),
            31 => Ok(Interrupt::FROM_CPU_INTR3),
            32 => Ok(Interrupt::SPI1),
            33 => Ok(Interrupt::SPI2),
            34 => Ok(Interrupt::SPI3),
            35 => Ok(Interrupt::I2S0),
            36 => Ok(Interrupt::I2S1),
            37 => Ok(Interrupt::UART0),
            38 => Ok(Interrupt::UART1),
            39 => Ok(Interrupt::UART2),
            40 => Ok(Interrupt::SDIO_HOST),
            45 => Ok(Interrupt::LEDC),
            46 => Ok(Interrupt::EFUSE),
            47 => Ok(Interrupt::TWAI0),
            48 => Ok(Interrupt::USB),
            49 => Ok(Interrupt::RTC_CORE),
            50 => Ok(Interrupt::RMT),
            51 => Ok(Interrupt::PCNT),
            52 => Ok(Interrupt::I2C_EXT0),
            53 => Ok(Interrupt::I2C_EXT1),
            54 => Ok(Interrupt::RSA),
            55 => Ok(Interrupt::SHA),
            56 => Ok(Interrupt::AES),
            57 => Ok(Interrupt::SPI2_DMA),
            58 => Ok(Interrupt::SPI3_DMA),
            59 => Ok(Interrupt::WDT),
            60 => Ok(Interrupt::TIMER1),
            61 => Ok(Interrupt::TIMER2),
            62 => Ok(Interrupt::TG0_T0_EDGE),
            63 => Ok(Interrupt::TG0_T1_EDGE),
            64 => Ok(Interrupt::TG0_WDT_EDGE),
            65 => Ok(Interrupt::TG0_LACT_EDGE),
            66 => Ok(Interrupt::TG1_T0_EDGE),
            67 => Ok(Interrupt::TG1_T1_EDGE),
            68 => Ok(Interrupt::TG1_WDT_EDGE),
            69 => Ok(Interrupt::TG1_LACT_EDGE),
            70 => Ok(Interrupt::CACHE_IA),
            71 => Ok(Interrupt::SYSTIMER_TARGET0),
            72 => Ok(Interrupt::SYSTIMER_TARGET1),
            73 => Ok(Interrupt::SYSTIMER_TARGET2),
            75 => Ok(Interrupt::PMS_PRO_IRAM0_ILG),
            76 => Ok(Interrupt::PMS_PRO_DRAM0_ILG),
            77 => Ok(Interrupt::PMS_PRO_DPORT_ILG),
            78 => Ok(Interrupt::PMS_PRO_AHB_ILG),
            79 => Ok(Interrupt::PMS_PRO_CACHE_ILG),
            80 => Ok(Interrupt::PMS_DMA_APB_I_ILG),
            81 => Ok(Interrupt::PMS_DMA_RX_I_ILG),
            82 => Ok(Interrupt::PMS_DMA_TX_I_ILG),
            83 => Ok(Interrupt::SPI0_REJECT_CACHE),
            84 => Ok(Interrupt::DMA_COPY),
            85 => Ok(Interrupt::SPI4_DMA),
            86 => Ok(Interrupt::SPI4),
            87 => Ok(Interrupt::ICACHE_PRELOAD),
            88 => Ok(Interrupt::DCACHE_PRELOAD),
            89 => Ok(Interrupt::APB_ADC),
            90 => Ok(Interrupt::CRYPTO_DMA),
            91 => Ok(Interrupt::CPU_PERI_ERR),
            92 => Ok(Interrupt::APB_PERI_ERR),
            93 => Ok(Interrupt::DCACHE_SYNC),
            94 => Ok(Interrupt::ICACHE_SYNC),
            _ => Err(TryFromInterruptError(())),
        }
    }
}
#[doc = "AES (Advanced Encryption Standard) Accelerator"]
pub type AES = crate::Periph<aes::RegisterBlock, 0x6003_a000>;
impl core::fmt::Debug for AES {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("AES").finish()
    }
}
#[doc = "AES (Advanced Encryption Standard) Accelerator"]
pub mod aes;
#[doc = "SAR (Successive Approximation Register) Analog-to-Digital Converter"]
pub type APB_SARADC = crate::Periph<apb_saradc::RegisterBlock, 0x3f44_0000>;
impl core::fmt::Debug for APB_SARADC {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("APB_SARADC").finish()
    }
}
#[doc = "SAR (Successive Approximation Register) Analog-to-Digital Converter"]
pub mod apb_saradc;
#[doc = "BB Peripheral"]
pub type BB = crate::Periph<bb::RegisterBlock, 0x3f41_d000>;
impl core::fmt::Debug for BB {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("BB").finish()
    }
}
#[doc = "BB Peripheral"]
pub mod bb;
#[doc = "DEDICATED_GPIO Peripheral"]
pub type DEDICATED_GPIO = crate::Periph<dedicated_gpio::RegisterBlock, 0x3f4c_f000>;
impl core::fmt::Debug for DEDICATED_GPIO {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("DEDICATED_GPIO").finish()
    }
}
#[doc = "DEDICATED_GPIO Peripheral"]
pub mod dedicated_gpio;
#[doc = "I2C Analog Master"]
pub type I2C_ANA_MST = crate::Periph<i2c_ana_mst::RegisterBlock, 0x6000_e000>;
impl core::fmt::Debug for I2C_ANA_MST {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("I2C_ANA_MST").finish()
    }
}
#[doc = "I2C Analog Master"]
pub mod i2c_ana_mst;
#[doc = "MAC controller for Wi-Fi peripheral"]
pub type WIFI = crate::Periph<wifi::RegisterBlock, 0x6003_3000>;
impl core::fmt::Debug for WIFI {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("WIFI").finish()
    }
}
#[doc = "MAC controller for Wi-Fi peripheral"]
pub mod wifi;
#[doc = "Digital Signature"]
pub type DS = crate::Periph<ds::RegisterBlock, 0x6003_d000>;
impl core::fmt::Debug for DS {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("DS").finish()
    }
}
#[doc = "Digital Signature"]
pub mod ds;
#[doc = "eFuse Controller"]
pub type EFUSE = crate::Periph<efuse::RegisterBlock, 0x3f41_a000>;
impl core::fmt::Debug for EFUSE {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("EFUSE").finish()
    }
}
#[doc = "eFuse Controller"]
pub mod efuse;
#[doc = "NRX Peripheral"]
pub type NRX = crate::Periph<nrx::RegisterBlock, 0x3f41_cc00>;
impl core::fmt::Debug for NRX {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("NRX").finish()
    }
}
#[doc = "NRX Peripheral"]
pub mod nrx;
#[doc = "External Memory"]
pub type EXTMEM = crate::Periph<extmem::RegisterBlock, 0x6180_0000>;
impl core::fmt::Debug for EXTMEM {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("EXTMEM").finish()
    }
}
#[doc = "External Memory"]
pub mod extmem;
#[doc = "General Purpose Input/Output"]
pub type GPIO = crate::Periph<gpio::RegisterBlock, 0x3f40_4000>;
impl core::fmt::Debug for GPIO {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("GPIO").finish()
    }
}
#[doc = "General Purpose Input/Output"]
pub mod gpio;
#[doc = "Sigma-Delta Modulation"]
pub type GPIO_SD = crate::Periph<gpio_sd::RegisterBlock, 0x3f40_4f00>;
impl core::fmt::Debug for GPIO_SD {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("GPIO_SD").finish()
    }
}
#[doc = "Sigma-Delta Modulation"]
pub mod gpio_sd;
#[doc = "FE2 Peripheral"]
pub type FE2 = crate::Periph<fe2::RegisterBlock, 0x3f40_5000>;
impl core::fmt::Debug for FE2 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("FE2").finish()
    }
}
#[doc = "FE2 Peripheral"]
pub mod fe2;
#[doc = "FE Peripheral"]
pub type FE = crate::Periph<fe::RegisterBlock, 0x3f40_6000>;
impl core::fmt::Debug for FE {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("FE").finish()
    }
}
#[doc = "FE Peripheral"]
pub mod fe;
#[doc = "HMAC (Hash-based Message Authentication Code) Accelerator"]
pub type HMAC = crate::Periph<hmac::RegisterBlock, 0x6003_e000>;
impl core::fmt::Debug for HMAC {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("HMAC").finish()
    }
}
#[doc = "HMAC (Hash-based Message Authentication Code) Accelerator"]
pub mod hmac;
#[doc = "Crypto DMA Controller"]
pub type CRYPTO_DMA = crate::Periph<crypto_dma::RegisterBlock, 0x6003_f000>;
impl core::fmt::Debug for CRYPTO_DMA {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("CRYPTO_DMA").finish()
    }
}
#[doc = "Crypto DMA Controller"]
pub mod crypto_dma;
#[doc = "I2C (Inter-Integrated Circuit) Controller 0"]
pub type I2C0 = crate::Periph<i2c0::RegisterBlock, 0x3f41_3000>;
impl core::fmt::Debug for I2C0 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("I2C0").finish()
    }
}
#[doc = "I2C (Inter-Integrated Circuit) Controller 0"]
pub mod i2c0;
#[doc = "I2C (Inter-Integrated Circuit) Controller 1"]
pub type I2C1 = crate::Periph<i2c0::RegisterBlock, 0x3f42_7000>;
impl core::fmt::Debug for I2C1 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("I2C1").finish()
    }
}
#[doc = "I2C (Inter-Integrated Circuit) Controller 1"]
pub use self::i2c0 as i2c1;
#[doc = "I2S (Inter-IC Sound) Controller 0"]
pub type I2S0 = crate::Periph<i2s0::RegisterBlock, 0x3f40_f000>;
impl core::fmt::Debug for I2S0 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("I2S0").finish()
    }
}
#[doc = "I2S (Inter-IC Sound) Controller 0"]
pub mod i2s0;
#[doc = "Interrupt Controller (Core 0)"]
pub type INTERRUPT_CORE0 = crate::Periph<interrupt_core0::RegisterBlock, 0x3f4c_2000>;
impl core::fmt::Debug for INTERRUPT_CORE0 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("INTERRUPT_CORE0").finish()
    }
}
#[doc = "Interrupt Controller (Core 0)"]
pub mod interrupt_core0;
#[doc = "Copy DMA Controller"]
pub type COPY_DMA = crate::Periph<copy_dma::RegisterBlock, 0x3f4c_3000>;
impl core::fmt::Debug for COPY_DMA {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("COPY_DMA").finish()
    }
}
#[doc = "Copy DMA Controller"]
pub mod copy_dma;
#[doc = "Input/Output Multiplexer"]
pub type IO_MUX = crate::Periph<io_mux::RegisterBlock, 0x3f40_9000>;
impl core::fmt::Debug for IO_MUX {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("IO_MUX").finish()
    }
}
#[doc = "Input/Output Multiplexer"]
pub mod io_mux;
#[doc = "LED Control PWM (Pulse Width Modulation)"]
pub type LEDC = crate::Periph<ledc::RegisterBlock, 0x3f41_9000>;
impl core::fmt::Debug for LEDC {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("LEDC").finish()
    }
}
#[doc = "LED Control PWM (Pulse Width Modulation)"]
pub mod ledc;
#[doc = "Pulse Count Controller"]
pub type PCNT = crate::Periph<pcnt::RegisterBlock, 0x3f41_7000>;
impl core::fmt::Debug for PCNT {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("PCNT").finish()
    }
}
#[doc = "Pulse Count Controller"]
pub mod pcnt;
#[doc = "Permissions Controller"]
pub type PMS = crate::Periph<pms::RegisterBlock, 0x3f4c_1000>;
impl core::fmt::Debug for PMS {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("PMS").finish()
    }
}
#[doc = "Permissions Controller"]
pub mod pms;
#[doc = "Remote Control"]
pub type RMT = crate::Periph<rmt::RegisterBlock, 0x3f41_6000>;
impl core::fmt::Debug for RMT {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("RMT").finish()
    }
}
#[doc = "Remote Control"]
pub mod rmt;
#[doc = "Hardware Random Number Generator"]
pub type RNG = crate::Periph<rng::RegisterBlock, 0x6003_5000>;
impl core::fmt::Debug for RNG {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("RNG").finish()
    }
}
#[doc = "Hardware Random Number Generator"]
pub mod rng;
#[doc = "RSA (Rivest Shamir Adleman) Accelerator"]
pub type RSA = crate::Periph<rsa::RegisterBlock, 0x6003_c000>;
impl core::fmt::Debug for RSA {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("RSA").finish()
    }
}
#[doc = "RSA (Rivest Shamir Adleman) Accelerator"]
pub mod rsa;
#[doc = "Low-power Input/Output"]
pub type RTC_IO = crate::Periph<rtc_io::RegisterBlock, 0x3f40_8400>;
impl core::fmt::Debug for RTC_IO {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("RTC_IO").finish()
    }
}
#[doc = "Low-power Input/Output"]
pub mod rtc_io;
#[doc = "Real-Time Clock Control"]
pub type RTC_CNTL = crate::Periph<rtc_cntl::RegisterBlock, 0x3f40_8000>;
impl core::fmt::Debug for RTC_CNTL {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("RTC_CNTL").finish()
    }
}
#[doc = "Real-Time Clock Control"]
pub mod rtc_cntl;
#[doc = "Low-power I2C (Inter-Integrated Circuit) Controller"]
pub type RTC_I2C = crate::Periph<rtc_i2c::RegisterBlock, 0x3f40_8c00>;
impl core::fmt::Debug for RTC_I2C {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("RTC_I2C").finish()
    }
}
#[doc = "Low-power I2C (Inter-Integrated Circuit) Controller"]
pub mod rtc_i2c;
#[doc = "SENS Peripheral"]
pub type SENS = crate::Periph<sens::RegisterBlock, 0x3f40_8800>;
impl core::fmt::Debug for SENS {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SENS").finish()
    }
}
#[doc = "SENS Peripheral"]
pub mod sens;
#[doc = "SHA (Secure Hash Algorithm) Accelerator"]
pub type SHA = crate::Periph<sha::RegisterBlock, 0x6003_b000>;
impl core::fmt::Debug for SHA {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SHA").finish()
    }
}
#[doc = "SHA (Secure Hash Algorithm) Accelerator"]
pub mod sha;
#[doc = "SPI (Serial Peripheral Interface) Controller 2 (GPSPI)"]
pub type SPI2 = crate::Periph<spi2::RegisterBlock, 0x3f42_4000>;
impl core::fmt::Debug for SPI2 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SPI2").finish()
    }
}
#[doc = "SPI (Serial Peripheral Interface) Controller 2 (GPSPI)"]
pub mod spi2;
#[doc = "SPI (Serial Peripheral Interface) Controller 1"]
pub type SPI1 = crate::Periph<spi0::RegisterBlock, 0x3f40_2000>;
impl core::fmt::Debug for SPI1 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SPI1").finish()
    }
}
#[doc = "SPI (Serial Peripheral Interface) Controller 1"]
pub use self::spi0 as spi1;
#[doc = "SPI (Serial Peripheral Interface) Controller 0 (MEMSPI)"]
pub type SPI0 = crate::Periph<spi0::RegisterBlock, 0x3f40_3000>;
impl core::fmt::Debug for SPI0 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SPI0").finish()
    }
}
#[doc = "SPI (Serial Peripheral Interface) Controller 0 (MEMSPI)"]
pub mod spi0;
#[doc = "SPI (Serial Peripheral Interface) Controller 3"]
pub type SPI3 = crate::Periph<spi2::RegisterBlock, 0x3f42_5000>;
impl core::fmt::Debug for SPI3 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SPI3").finish()
    }
}
#[doc = "SPI (Serial Peripheral Interface) Controller 3"]
pub use self::spi2 as spi3;
#[doc = "SPI (Serial Peripheral Interface) Controller 4"]
pub type SPI4 = crate::Periph<spi2::RegisterBlock, 0x3f43_7000>;
impl core::fmt::Debug for SPI4 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SPI4").finish()
    }
}
#[doc = "SPI (Serial Peripheral Interface) Controller 4"]
pub use self::spi2 as spi4;
#[doc = "SYSCON Peripheral"]
pub type SYSCON = crate::Periph<syscon::RegisterBlock, 0x3f42_6000>;
impl core::fmt::Debug for SYSCON {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SYSCON").finish()
    }
}
#[doc = "SYSCON Peripheral"]
pub mod syscon;
#[doc = "System Configuration Registers"]
pub type SYSTEM = crate::Periph<system::RegisterBlock, 0x3f4c_0000>;
impl core::fmt::Debug for SYSTEM {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SYSTEM").finish()
    }
}
#[doc = "System Configuration Registers"]
pub mod system;
#[doc = "System Timer"]
pub type SYSTIMER = crate::Periph<systimer::RegisterBlock, 0x3f42_3000>;
impl core::fmt::Debug for SYSTIMER {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SYSTIMER").finish()
    }
}
#[doc = "System Timer"]
pub mod systimer;
#[doc = "Timer Group 0"]
pub type TIMG0 = crate::Periph<timg0::RegisterBlock, 0x3f41_f000>;
impl core::fmt::Debug for TIMG0 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("TIMG0").finish()
    }
}
#[doc = "Timer Group 0"]
pub mod timg0;
#[doc = "Timer Group 1"]
pub type TIMG1 = crate::Periph<timg0::RegisterBlock, 0x3f42_0000>;
impl core::fmt::Debug for TIMG1 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("TIMG1").finish()
    }
}
#[doc = "Timer Group 1"]
pub use self::timg0 as timg1;
#[doc = "Two-Wire Automotive Interface"]
pub type TWAI0 = crate::Periph<twai0::RegisterBlock, 0x3f42_b000>;
impl core::fmt::Debug for TWAI0 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("TWAI0").finish()
    }
}
#[doc = "Two-Wire Automotive Interface"]
pub mod twai0;
#[doc = "UART (Universal Asynchronous Receiver-Transmitter) Controller 0"]
pub type UART0 = crate::Periph<uart0::RegisterBlock, 0x3f40_0000>;
impl core::fmt::Debug for UART0 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("UART0").finish()
    }
}
#[doc = "UART (Universal Asynchronous Receiver-Transmitter) Controller 0"]
pub mod uart0;
#[doc = "UART (Universal Asynchronous Receiver-Transmitter) Controller 1"]
pub type UART1 = crate::Periph<uart0::RegisterBlock, 0x3f41_0000>;
impl core::fmt::Debug for UART1 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("UART1").finish()
    }
}
#[doc = "UART (Universal Asynchronous Receiver-Transmitter) Controller 1"]
pub use self::uart0 as uart1;
#[doc = "Universal Host Controller Interface 0"]
pub type UHCI0 = crate::Periph<uhci0::RegisterBlock, 0x3f41_4000>;
impl core::fmt::Debug for UHCI0 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("UHCI0").finish()
    }
}
#[doc = "Universal Host Controller Interface 0"]
pub mod uhci0;
#[doc = "USB OTG (On-The-Go)"]
pub type USB0 = crate::Periph<usb0::RegisterBlock, 0x6008_0000>;
impl core::fmt::Debug for USB0 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("USB0").finish()
    }
}
#[doc = "USB OTG (On-The-Go)"]
pub mod usb0;
#[doc = "USB_WRAP Peripheral"]
pub type USB_WRAP = crate::Periph<usb_wrap::RegisterBlock, 0x3f43_9000>;
impl core::fmt::Debug for USB_WRAP {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("USB_WRAP").finish()
    }
}
#[doc = "USB_WRAP Peripheral"]
pub mod usb_wrap;
#[doc = "XTS-AES-128 Flash Encryption"]
pub type XTS_AES = crate::Periph<xts_aes::RegisterBlock, 0x6003_a100>;
impl core::fmt::Debug for XTS_AES {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("XTS_AES").finish()
    }
}
#[doc = "XTS-AES-128 Flash Encryption"]
pub mod xts_aes;
