/* automatically generated by rust-bindgen 0.72.1 */

pub const QSPI_ROM_BASE: u32 = 2550136832;
pub const QSPI_ROM_END: u32 = 2617245695;
pub const QSPI_CLK_DIV2: u32 = 65536;
pub const QSPI_CLK_DIV3: u32 = 131072;
pub const QSPI_CLK_DIV4: u32 = 196608;
pub const QSPI_CLK_DIV5: u32 = 262144;
pub const QSPI_CLK_DIV6: u32 = 327680;
pub const QSPI_CLK_DIV7: u32 = 393216;
pub const QSPI_CLK_DIV8: u32 = 458752;
pub const QSPI_CLK_DIV9: u32 = 524288;
pub const QSPI_CLK_DIV10: u32 = 589824;
pub const QSPI_CLK_DIV11: u32 = 655360;
pub const QSPI_CLK_DIV12: u32 = 720896;
pub const QSPI_CLK_DIV13: u32 = 786432;
pub const QSPI_CLK_DIV14: u32 = 851968;
pub const QSPI_CLK_DIV15: u32 = 917504;
pub const QSPI_CLK_DIV16: u32 = 983040;
pub const QSPI_CLK_DIV17: u32 = 1048576;
pub const QSPI_CLK_DIV18: u32 = 1114112;
pub const QSPI_CLK_DIV19: u32 = 1179648;
pub const QSPI_CLK_DIV20: u32 = 1245184;
pub const QSPI_CLK_DIV21: u32 = 1310720;
pub const QSPI_CLK_DIV22: u32 = 1376256;
pub const QSPI_CLK_DIV23: u32 = 1441792;
pub const QSPI_CLK_DIV24: u32 = 1507328;
pub const QSPI_CLK_DIV25: u32 = 1572864;
pub const QSPI_CLK_DIV26: u32 = 1638400;
pub const QSPI_CLK_DIV27: u32 = 1703936;
pub const QSPI_CLK_DIV28: u32 = 1769472;
pub const QSPI_CLK_DIV29: u32 = 1835008;
pub const QSPI_CLK_DIV30: u32 = 1900544;
pub const QSPI_CLK_DIV31: u32 = 1966080;
pub const QSPI_CLK_DIV32: u32 = 2031616;
pub const QSPI_CLK_DIV33: u32 = 2097152;
pub const QSPI_CLK_DIV34: u32 = 2162688;
pub const QSPI_CLK_DIV35: u32 = 2228224;
pub const QSPI_CLK_DIV36: u32 = 2293760;
pub const QSPI_CLK_DIV37: u32 = 2359296;
pub const QSPI_CLK_DIV38: u32 = 2424832;
pub const QSPI_CLK_DIV39: u32 = 2490368;
pub const QSPI_CLK_DIV40: u32 = 2555904;
pub const QSPI_CLK_DIV41: u32 = 2621440;
pub const QSPI_CLK_DIV42: u32 = 2686976;
pub const QSPI_CLK_DIV43: u32 = 2752512;
pub const QSPI_CLK_DIV44: u32 = 2818048;
pub const QSPI_CLK_DIV45: u32 = 2883584;
pub const QSPI_CLK_DIV46: u32 = 2949120;
pub const QSPI_CLK_DIV47: u32 = 3014656;
pub const QSPI_CLK_DIV48: u32 = 3080192;
pub const QSPI_CLK_DIV49: u32 = 3145728;
pub const QSPI_CLK_DIV50: u32 = 3211264;
pub const QSPI_CLK_DIV51: u32 = 3276800;
pub const QSPI_CLK_DIV52: u32 = 3342336;
pub const QSPI_CLK_DIV53: u32 = 3407872;
pub const QSPI_CLK_DIV54: u32 = 3473408;
pub const QSPI_CLK_DIV55: u32 = 3538944;
pub const QSPI_CLK_DIV56: u32 = 3604480;
pub const QSPI_CLK_DIV57: u32 = 3670016;
pub const QSPI_CLK_DIV58: u32 = 3735552;
pub const QSPI_CLK_DIV59: u32 = 3801088;
pub const QSPI_CLK_DIV60: u32 = 3866624;
pub const QSPI_CLK_DIV61: u32 = 3932160;
pub const QSPI_CLK_DIV62: u32 = 3997696;
pub const QSPI_CLK_DIV63: u32 = 4063232;
pub const QSPI_CLK_DIV64: u32 = 4128768;
pub const QSPI_SPI_MD0: u32 = 0;
pub const QSPI_SPI_MD3: u32 = 128;
pub const QSPI_PREFETCH_MD_INVD: u32 = 0;
pub const QSPI_PREFETCH_MD_EDGE_STOP: u32 = 8;
pub const QSPI_PREFETCH_MD_IMMED_STOP: u32 = 24;
pub const QSPI_RD_MD_STD_RD: u32 = 0;
pub const QSPI_RD_MD_FAST_RD: u32 = 1;
pub const QSPI_RD_MD_DUAL_OUTPUT_FAST_RD: u32 = 2;
pub const QSPI_RD_MD_DUAL_IO_FAST_RD: u32 = 3;
pub const QSPI_RD_MD_QUAD_OUTPUT_FAST_RD: u32 = 4;
pub const QSPI_RD_MD_QUAD_IO_FAST_RD: u32 = 5;
pub const QSPI_RD_MD_CUSTOM_STANDARD_RD: u32 = 6;
pub const QSPI_RD_MD_CUSTOM_FAST_RD: u32 = 7;
pub const QSPI_DUMMY_CYCLE3: u32 = 0;
pub const QSPI_DUMMY_CYCLE4: u32 = 256;
pub const QSPI_DUMMY_CYCLE5: u32 = 512;
pub const QSPI_DUMMY_CYCLE6: u32 = 768;
pub const QSPI_DUMMY_CYCLE7: u32 = 1024;
pub const QSPI_DUMMY_CYCLE8: u32 = 1280;
pub const QSPI_DUMMY_CYCLE9: u32 = 1536;
pub const QSPI_DUMMY_CYCLE10: u32 = 1792;
pub const QSPI_DUMMY_CYCLE11: u32 = 2048;
pub const QSPI_DUMMY_CYCLE12: u32 = 2304;
pub const QSPI_DUMMY_CYCLE13: u32 = 2560;
pub const QSPI_DUMMY_CYCLE14: u32 = 2816;
pub const QSPI_DUMMY_CYCLE15: u32 = 3072;
pub const QSPI_DUMMY_CYCLE16: u32 = 3328;
pub const QSPI_DUMMY_CYCLE17: u32 = 3584;
pub const QSPI_DUMMY_CYCLE18: u32 = 3840;
pub const QSPI_ADDR_WIDTH_8BIT: u32 = 0;
pub const QSPI_ADDR_WIDTH_16BIT: u32 = 1;
pub const QSPI_ADDR_WIDTH_24BIT: u32 = 2;
pub const QSPI_ADDR_WIDTH_32BIT_INSTR_24BIT: u32 = 3;
pub const QSPI_ADDR_WIDTH_32BIT_INSTR_32BIT: u32 = 7;
pub const QSPI_QSSN_SETUP_ADVANCE_QSCK0P5: u32 = 0;
pub const QSPI_QSSN_SETUP_ADVANCE_QSCK1P5: u32 = 32;
pub const QSPI_QSSN_RELEASE_DELAY_QSCK0P5: u32 = 0;
pub const QSPI_QSSN_RELEASE_DELAY_QSCK1P5: u32 = 16;
pub const QSPI_QSSN_RELEASE_DELAY_QSCK32: u32 = 4096;
pub const QSPI_QSSN_RELEASE_DELAY_QSCK128: u32 = 8192;
pub const QSPI_QSSN_RELEASE_DELAY_INFINITE: u32 = 12288;
pub const QSPI_QSSN_INTERVAL_QSCK1: u32 = 0;
pub const QSPI_QSSN_INTERVAL_QSCK2: u32 = 1;
pub const QSPI_QSSN_INTERVAL_QSCK3: u32 = 2;
pub const QSPI_QSSN_INTERVAL_QSCK4: u32 = 3;
pub const QSPI_QSSN_INTERVAL_QSCK5: u32 = 4;
pub const QSPI_QSSN_INTERVAL_QSCK6: u32 = 5;
pub const QSPI_QSSN_INTERVAL_QSCK7: u32 = 6;
pub const QSPI_QSSN_INTERVAL_QSCK8: u32 = 7;
pub const QSPI_QSSN_INTERVAL_QSCK9: u32 = 8;
pub const QSPI_QSSN_INTERVAL_QSCK10: u32 = 9;
pub const QSPI_QSSN_INTERVAL_QSCK11: u32 = 10;
pub const QSPI_QSSN_INTERVAL_QSCK12: u32 = 11;
pub const QSPI_QSSN_INTERVAL_QSCK13: u32 = 12;
pub const QSPI_QSSN_INTERVAL_QSCK14: u32 = 13;
pub const QSPI_QSSN_INTERVAL_QSCK15: u32 = 14;
pub const QSPI_QSSN_INTERVAL_QSCK16: u32 = 15;
pub const QSPI_INSTR_PROTOCOL_1LINE: u32 = 0;
pub const QSPI_INSTR_PROTOCOL_2LINE: u32 = 256;
pub const QSPI_INSTR_PROTOCOL_4LINE: u32 = 512;
pub const QSPI_ADDR_PROTOCOL_1LINE: u32 = 0;
pub const QSPI_ADDR_PROTOCOL_2LINE: u32 = 1024;
pub const QSPI_ADDR_PROTOCOL_4LINE: u32 = 2048;
pub const QSPI_DATA_PROTOCOL_1LINE: u32 = 0;
pub const QSPI_DATA_PROTOCOL_2LINE: u32 = 4096;
pub const QSPI_DATA_PROTOCOL_4LINE: u32 = 8192;
pub const QSPI_WP_PIN_LOW: u32 = 0;
pub const QSPI_WP_PIN_HIGH: u32 = 64;
pub const QSPI_DIRECT_COMM_PROTOCOL_1LINE: u32 = 0;
pub const QSPI_DIRECT_COMM_PROTOCOL_2LINE: u32 = 256;
pub const QSPI_DIRECT_COMM_PROTOCOL_4LINE: u32 = 512;
pub const QSPI_FLAG_DIRECT_COMM_BUSY: u32 = 1;
pub const QSPI_FLAG_XIP_MD: u32 = 64;
pub const QSPI_FLAG_ROM_ACCESS_ERR: u32 = 128;
pub const QSPI_FLAG_PREFETCH_BUF_FULL: u32 = 16384;
pub const QSPI_FLAG_PREFETCH_STOP: u32 = 32768;
pub const QSPI_FLAG_ALL: u32 = 49345;
pub const QSPI_FLAG_CLR_ALL: u32 = 128;
pub const en_functional_state_t_DISABLE: en_functional_state_t = 0;
pub const en_functional_state_t_ENABLE: en_functional_state_t = 1;
#[doc = " @brief Functional state"]
pub type en_functional_state_t = ::core::ffi::c_uint;
pub const en_flag_status_t_RESET: en_flag_status_t = 0;
pub const en_flag_status_t_SET: en_flag_status_t = 1;
#[doc = " @brief Flag status"]
pub type en_flag_status_t = ::core::ffi::c_uint;
#[doc = " @brief QSPI initialization structure definition"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_qspi_init_t {
    #[doc = "< Specifies the clock division.\nThis parameter can be a value of @ref QSPI_Clock_Division"]
    pub u32ClockDiv: u32,
    #[doc = "< Specifies the SPI mode.\nThis parameter can be a value of @ref QSPI_SPI_Mode"]
    pub u32SpiMode: u32,
    #[doc = "< Specifies the prefetch mode.\nThis parameter can be a value of @ref QSPI_Prefetch_Mode"]
    pub u32PrefetchMode: u32,
    #[doc = "< Specifies the read mode.\nThis parameter can be a value of @ref QSPI_Read_Mode"]
    pub u32ReadMode: u32,
    #[doc = "< Specifies the number of dummy cycles.\nThis parameter can be a value of @ref QSPI_Dummy_Cycle"]
    pub u32DummyCycle: u32,
    #[doc = "< Specifies the address width.\nThis parameter can be a value of @ref QSPI_Addr_Width"]
    pub u32AddrWidth: u32,
    #[doc = "< Specifies the advance time of QSSN setup.\nThis parameter can be a value of @ref QSPI_QSSN_Setup_Time"]
    pub u32SetupTime: u32,
    #[doc = "< Specifies the delay time of QSSN release.\nThis parameter can be a value of @ref QSPI_QSSN_Release_Time"]
    pub u32ReleaseTime: u32,
    #[doc = "< Specifies the minimum interval time of QSSN.\nThis parameter can be a value of @ref QSPI_QSSN_Interval_Time"]
    pub u32IntervalTime: u32,
}
#[doc = " @brief QSPI Custom read mode structure definition"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_qspi_custom_mode_t {
    #[doc = "< Specifies the instruction stage protocol.\nThis parameter can be a value of @ref QSPI_Instruction_Protocol"]
    pub u32InstrProtocol: u32,
    #[doc = "< Specifies the address stage protocol.\nThis parameter can be a value of @ref QSPI_Addr_Protocol"]
    pub u32AddrProtocol: u32,
    #[doc = "< Specifies the data stage protocol.\nThis parameter can be a value of @ref QSPI_Data_Protocol"]
    pub u32DataProtocol: u32,
    #[doc = "< Specifies the instruction code in custom read mode.\nThis parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFF"]
    pub u8InstrCode: u8,
}
unsafe extern "C" {
    pub fn QSPI_DeInit() -> i32;
    pub fn QSPI_Init(pstcQspiInit: *const stc_qspi_init_t) -> i32;
    pub fn QSPI_StructInit(pstcQspiInit: *mut stc_qspi_init_t) -> i32;
    pub fn QSPI_SetWpPinLevel(u32Level: u32);
    pub fn QSPI_SetPrefetchMode(u32Mode: u32);
    pub fn QSPI_SelectMemoryBlock(u8Block: u8);
    pub fn QSPI_SetReadMode(u32Mode: u32);
    pub fn QSPI_CustomReadConfig(pstcCustomMode: *const stc_qspi_custom_mode_t) -> i32;
    pub fn QSPI_XipModeCmd(u8ModeCode: u8, enNewState: en_functional_state_t);
    pub fn QSPI_EnterDirectCommMode();
    pub fn QSPI_ExitDirectCommMode();
    pub fn QSPI_WriteDirectCommValue(u32Protocol: u32, u8Value: u8);
    pub fn QSPI_GetPrefetchBufSize() -> u8;
    pub fn QSPI_GetStatus(u32Flag: u32) -> en_flag_status_t;
    pub fn QSPI_ClearStatus(u32Flag: u32);
}
