/* automatically generated by rust-bindgen 0.72.1 */

pub const EXMC_SMC_CHIP0: u32 = 0;
pub const EXMC_SMC_READ_ASYNC: u32 = 0;
pub const EXMC_SMC_READ_SYNC: u32 = 1;
pub const EXMC_SMC_WRITE_ASYNC: u32 = 0;
pub const EXMC_SMC_WRITE_SYNC: u32 = 16;
pub const EXMC_SMC_MEMORY_WIDTH_8BIT: u32 = 0;
pub const EXMC_SMC_MEMORY_WIDTH_16BIT: u32 = 256;
pub const EXMC_SMC_BAA_PORT_DISABLE: u32 = 0;
pub const EXMC_SMC_BAA_PORT_ENABLE: u32 = 1024;
pub const EXMC_SMC_ADV_PORT_DISABLE: u32 = 0;
pub const EXMC_SMC_ADV_PORT_ENABLE: u32 = 2048;
pub const EXMC_SMC_BLS_SYNC_CS: u32 = 0;
pub const EXMC_SMC_BLS_SYNC_WE: u32 = 4096;
pub const EXMC_SMC_CMD_MDREGCONFIG: u32 = 2097152;
pub const EXMC_SMC_CMD_UPDATEREGS: u32 = 4194304;
pub const EXMC_SMC_CMD_MDREGCONFIG_AND_UPDATEREGS: u32 = 6291456;
pub const EXMC_SMC_CRE_POLARITY_LOW: u32 = 0;
pub const EXMC_SMC_CRE_POLARITY_HIGH: u32 = 1048576;
pub const EXMC_SMC_READY: u32 = 0;
pub const EXMC_SMC_LOWPOWER: u32 = 1;
pub const EXMC_SMC_SAMPLE_CLK_INTERNCLK: u32 = 0;
pub const EXMC_SMC_SAMPLE_CLK_INTERNCLK_INVT: u32 = 16384;
pub const EXMC_SMC_SAMPLE_CLK_EXTCLK: u32 = 32768;
pub const EXMC_SMC_ADDR_MASK_16MB: u32 = 255;
pub const EXMC_SMC_ADDR_MASK_32MB: u32 = 254;
pub const EXMC_SMC_ADDR_MASK_64MB: u32 = 252;
pub const EXMC_SMC_ADDR_MASK_128MB: u32 = 248;
pub const EXMC_SMC_ADDR_MASK_256MB: u32 = 240;
pub const EXMC_SMC_ADDR_MASK_512MB: u32 = 224;
pub const EXMC_SMC_ADDR_MIN: u32 = 1610612736;
pub const EXMC_SMC_ADDR_MAX: u32 = 2147483647;
pub const en_functional_state_t_DISABLE: en_functional_state_t = 0;
pub const en_functional_state_t_ENABLE: en_functional_state_t = 1;
#[doc = " @brief Functional state"]
pub type en_functional_state_t = ::core::ffi::c_uint;
#[doc = " @brief  EXMC_SMC Chip Configuration Structure definition"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_exmc_smc_chip_config_t {
    #[doc = "< Defines the read sync enable.\nThis parameter can be a value of @ref EXMC_SMC_Memory_Read_Mode"]
    pub u32ReadMode: u32,
    #[doc = "< Defines the write sync enable.\nThis parameter can be a value of @ref EXMC_SMC_Memory_Write_Mode"]
    pub u32WriteMode: u32,
    #[doc = "< Defines the SMC memory width.\nThis parameter can be a value of @ref EXMC_SMC_Memory_Width."]
    pub u32MemoryWidth: u32,
    #[doc = "< Defines the SMC BAA signal enable.\nThis parameter can be a value of @ref EXMC_SMC_BAA_Port_Selection."]
    pub u32BAA: u32,
    #[doc = "< Defines the SMC ADVS signal enable.\nThis parameter can be a value of @ref EXMC_SMC_ADV_Port_Selection."]
    pub u32ADV: u32,
    #[doc = "< Defines the SMC BLS signal selection.\nThis parameter can be a value of @ref EXMC_SMC_BLS_Synchronization_Selection."]
    pub u32BLS: u32,
    #[doc = "< Defines the address match.\nThis parameter can be a value between Min_Data = 0x60 and Max_Data = 0x7F"]
    pub u32AddrMatch: u32,
    #[doc = "< Defines the address mask.\nThis parameter can be a value of @ref EXMC_SMC_Mask_Address."]
    pub u32AddrMask: u32,
}
#[doc = " @brief  EXMC_SMC Timing Configuration Structure definition"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_exmc_smc_timing_config_t {
    #[doc = "< Defines the RC in memory clock cycles.\nThis parameter can be a value between Min_Data = 0 and Max_Data = 0x0F"]
    pub u8RC: u8,
    #[doc = "< Defines the WC in memory clock cycles.\nThis parameter can be a value between Min_Data = 0 and Max_Data = 0x0F"]
    pub u8WC: u8,
    #[doc = "< Defines the CEOE in memory clock cycles.\nThis parameter can be a value between Min_Data = 0 and Max_Data = 7"]
    pub u8CEOE: u8,
    #[doc = "< Defines the WP in memory clock cycles.\nThis parameter can be a value between Min_Data = 0 and Max_Data = 7"]
    pub u8WP: u8,
    #[doc = "< Defines the TR in memory clock cycles.\nThis parameter can be a value between Min_Data = 0 and Max_Data = 7"]
    pub u8TR: u8,
    #[doc = "< Defines the ADV in memory clock cycles.\nThis parameter can be a value between Min_Data = 0 and Max_Data = 7"]
    pub u8ADV: u8,
}
#[doc = " @brief  EXMC_SMC Initialization Structure definition"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_exmc_smc_init_t {
    #[doc = "< SMC memory chip configure.\nThis structure details refer @ref stc_exmc_smc_chip_config_t."]
    pub stcChipConfig: stc_exmc_smc_chip_config_t,
    #[doc = "< SMC memory timing configure.\nThis structure details refer @ref stc_exmc_smc_timing_config_t."]
    pub stcTimingConfig: stc_exmc_smc_timing_config_t,
}
unsafe extern "C" {
    pub fn EXMC_SMC_StructInit(pstcSmcInit: *mut stc_exmc_smc_init_t) -> i32;
    pub fn EXMC_SMC_Init(u32Chip: u32, pstcSmcInit: *const stc_exmc_smc_init_t) -> i32;
    pub fn EXMC_SMC_DeInit() -> i32;
    pub fn EXMC_SMC_Cmd(enNewState: en_functional_state_t);
    pub fn EXMC_SMC_PinMuxCmd(enNewState: en_functional_state_t);
    pub fn EXMC_SMC_SetSampleClock(u32SampleClock: u32);
    pub fn EXMC_SMC_SetRefreshPeriod(u8PeriodVal: u8);
    pub fn EXMC_SMC_SetCommand(u32Chip: u32, u32Cmd: u32, u32CrePolarity: u32, u32Addr: u32);
    pub fn EXMC_SMC_GetChipStartAddr(u32Chip: u32) -> u32;
    pub fn EXMC_SMC_GetChipEndAddr(u32Chip: u32) -> u32;
    pub fn EXMC_SMC_GetChipConfig(
        u32Chip: u32,
        pstcChipConfig: *mut stc_exmc_smc_chip_config_t,
    ) -> i32;
    pub fn EXMC_SMC_GetTimingConfig(
        u32Chip: u32,
        pstcTimingConfig: *mut stc_exmc_smc_timing_config_t,
    ) -> i32;
}
