/* automatically generated by rust-bindgen 0.72.1 */

pub const TMR6_CNT_SRC_SW: u32 = 0;
pub const TMR6_CNT_SRC_HW: u32 = 1;
pub const TMR6_FLAG_MATCH_A: u32 = 1;
pub const TMR6_FLAG_MATCH_B: u32 = 2;
pub const TMR6_FLAG_MATCH_C: u32 = 4;
pub const TMR6_FLAG_MATCH_D: u32 = 8;
pub const TMR6_FLAG_MATCH_E: u32 = 16;
pub const TMR6_FLAG_MATCH_F: u32 = 32;
pub const TMR6_FLAG_OVF: u32 = 64;
pub const TMR6_FLAG_UDF: u32 = 128;
pub const TMR6_FLAG_DEAD_TIME_ERR: u32 = 256;
pub const TMR6_FLAG_UP_CNT_SPECIAL_MATCH_A: u32 = 512;
pub const TMR6_FLAG_DOWN_CNT_SPECIAL_MATCH_A: u32 = 1024;
pub const TMR6_FLAG_UP_CNT_SPECIAL_MATCH_B: u32 = 2048;
pub const TMR6_FLAG_DOWN_CNT_SPECIAL_MATCH_B: u32 = 4096;
pub const TMR6_FLAG_CNT_DIR: u32 = 2147483648;
pub const TMR6_FLAG_CAPT_AGAIN_A: u32 = 67108864;
pub const TMR6_FLAG_CAPT_AGAIN_B: u32 = 134217728;
pub const TMR6_FLAG_CLR_ALL: u32 = 201334527;
pub const TMR6_FLAG_ALL: u32 = 2348818431;
pub const TMR6_INT_MATCH_A: u32 = 1;
pub const TMR6_INT_MATCH_B: u32 = 2;
pub const TMR6_INT_MATCH_C: u32 = 4;
pub const TMR6_INT_MATCH_D: u32 = 8;
pub const TMR6_INT_MATCH_E: u32 = 16;
pub const TMR6_INT_MATCH_F: u32 = 32;
pub const TMR6_INT_OVF: u32 = 64;
pub const TMR6_INT_UDF: u32 = 128;
pub const TMR6_INT_DEAD_TIME_ERR: u32 = 256;
pub const TMR6_INT_UP_CNT_SPECIAL_MATCH_A: u32 = 65536;
pub const TMR6_INT_DOWN_CNT_SPECIAL_MATCH_A: u32 = 131072;
pub const TMR6_INT_UP_CNT_SPECIAL_MATCH_B: u32 = 262144;
pub const TMR6_INT_DOWN_CNT_SPECIAL_MATCH_B: u32 = 524288;
pub const TMR6_INT_ALL: u32 = 983551;
pub const TMR6_PERIOD_REG_A: u32 = 0;
pub const TMR6_PERIOD_REG_B: u32 = 1;
pub const TMR6_PERIOD_REG_C: u32 = 2;
pub const TMR6_CMP_REG_A: u32 = 0;
pub const TMR6_CMP_REG_B: u32 = 1;
pub const TMR6_CMP_REG_C: u32 = 2;
pub const TMR6_CMP_REG_D: u32 = 3;
pub const TMR6_CMP_REG_E: u32 = 4;
pub const TMR6_CMP_REG_F: u32 = 5;
pub const TMR6_CH_A: u32 = 0;
pub const TMR6_CH_B: u32 = 1;
pub const TMR6_BUF_SINGLE: u32 = 0;
pub const TMR6_BUF_DUAL: u32 = 2;
pub const TMR6_BUF_TRANS_INVD: u32 = 0;
pub const TMR6_BUF_TRANS_OVF: u32 = 4;
pub const TMR6_BUF_TRANS_UDF: u32 = 8;
pub const TMR6_BUF_TRANS_OVF_UDF: u32 = 12;
pub const TMR6_VALID_PERIOD_INVD: u32 = 0;
pub const TMR6_VALID_PERIOD_CNT_COND_VALLEY: u32 = 65536;
pub const TMR6_VALID_PERIOD_CNT_COND_PEAK: u32 = 131072;
pub const TMR6_VALID_PERIOD_CNT_COND_VALLEY_PEAK: u32 = 196608;
pub const TMR6_VALID_PERIOD_CNT_INVD: u32 = 0;
pub const TMR6_VALID_PERIOD_CNT1: u32 = 262144;
pub const TMR6_VALID_PERIOD_CNT2: u32 = 524288;
pub const TMR6_VALID_PERIOD_CNT3: u32 = 786432;
pub const TMR6_VALID_PERIOD_CNT4: u32 = 1048576;
pub const TMR6_VALID_PERIOD_CNT5: u32 = 1310720;
pub const TMR6_VALID_PERIOD_CNT6: u32 = 1572864;
pub const TMR6_VALID_PERIOD_CNT7: u32 = 1835008;
pub const TMR6_DEADTIME_REG_UP_A: u32 = 0;
pub const TMR6_DEADTIME_REG_DOWN_A: u32 = 1;
pub const TMR6_DEADTIME_REG_UP_B: u32 = 2;
pub const TMR6_DEADTIME_REG_DOWN_B: u32 = 3;
pub const TMR6_IO_PWMA: u32 = 0;
pub const TMR6_IO_PWMB: u32 = 1;
pub const TMR6_INPUT_TRIGA: u32 = 2;
pub const TMR6_INPUT_TRIGB: u32 = 3;
pub const TMR6_FILTER_CLK_DIV1: u32 = 0;
pub const TMR6_FILTER_CLK_DIV4: u32 = 1;
pub const TMR6_FILTER_CLK_DIV16: u32 = 2;
pub const TMR6_FILTER_CLK_DIV64: u32 = 3;
pub const TMR6_PIN_CMP_OUTPUT: u32 = 0;
pub const TMR6_PIN_CAPT_INPUT: u32 = 2147483648;
pub const TMR6_STAT_START: u32 = 0;
pub const TMR6_STAT_STOP: u32 = 1;
pub const TMR6_STAT_OVF: u32 = 2;
pub const TMR6_STAT_UDF: u32 = 3;
pub const TMR6_STAT_UP_CNT_MATCH_A: u32 = 4;
pub const TMR6_STAT_DOWN_CNT_MATCH_A: u32 = 5;
pub const TMR6_STAT_UP_CNT_MATCH_B: u32 = 6;
pub const TMR6_STAT_DOWN_CNT_MATCH_B: u32 = 7;
pub const TMR6_PWM_LOW: u32 = 0;
pub const TMR6_PWM_HIGH: u32 = 1;
pub const TMR6_PWM_HOLD: u32 = 2;
pub const TMR6_PWM_INVT: u32 = 3;
pub const TMR6_PWM_FORCE_INVD: u32 = 0;
pub const TMR6_PWM_FORCE_LOW: u32 = 2;
pub const TMR6_PWM_FORCE_HIGH: u32 = 3;
pub const TMR6_EMB_EVT_CH0: u32 = 0;
pub const TMR6_EMB_RELEASE_IMMED: u32 = 0;
pub const TMR6_EMB_RELEASE_OVF: u32 = 4194304;
pub const TMR6_EMB_RELEASE_UDF: u32 = 8388608;
pub const TMR6_EMB_RELEASE_OVF_UDF: u32 = 12582912;
pub const TMR6_EMB_PIN_NORMAL: u32 = 0;
pub const TMR6_EMB_PIN_HIZ: u32 = 1048576;
pub const TMR6_EMB_PIN_LOW: u32 = 2097152;
pub const TMR6_EMB_PIN_HIGH: u32 = 3145728;
pub const TMR6_DEADTIME_CNT_UP_BUF_OFF: u32 = 0;
pub const TMR6_DEADTIME_CNT_UP_BUF_ON: u32 = 16;
pub const TMR6_DEADTIME_CNT_DOWN_BUF_OFF: u32 = 0;
pub const TMR6_DEADTIME_CNT_DOWN_BUF_ON: u32 = 32;
pub const TMR6_DEADTIME_BUF_COND_INVD: u32 = 0;
pub const TMR6_DEADTIME_BUF_COND_OVF: u32 = 64;
pub const TMR6_DEADTIME_BUF_COND_UDF: u32 = 128;
pub const TMR6_DEADTIME_BUF_COND_OVF_UDF: u32 = 192;
pub const TMR6_DEADTIME_EQUAL_OFF: u32 = 0;
pub const TMR6_DEADTIME_EQUAL_ON: u32 = 2;
pub const TMR6_SW_SYNC_U1: u32 = 1;
pub const TMR6_SW_SYNC_U2: u32 = 2;
pub const TMR6_SW_SYNC_ALL: u32 = 3;
pub const TMR6_START_COND_PWMA_RISING: u32 = 1;
pub const TMR6_START_COND_PWMA_FALLING: u32 = 2;
pub const TMR6_START_COND_PWMB_RISING: u32 = 4;
pub const TMR6_START_COND_PWMB_FALLING: u32 = 8;
pub const TMR6_START_COND_EVT0: u32 = 256;
pub const TMR6_START_COND_EVT1: u32 = 512;
pub const TMR6_START_COND_TRIGA_RISING: u32 = 65536;
pub const TMR6_START_COND_TRIGA_FALLING: u32 = 131072;
pub const TMR6_START_COND_TRIGB_RISING: u32 = 262144;
pub const TMR6_START_COND_TRIGB_FALLING: u32 = 524288;
pub const TMR6_START_COND_ALL: u32 = 983823;
pub const TMR6_STOP_COND_PWMA_RISING: u32 = 1;
pub const TMR6_STOP_COND_PWMA_FALLING: u32 = 2;
pub const TMR6_STOP_COND_PWMB_RISING: u32 = 4;
pub const TMR6_STOP_COND_PWMB_FALLING: u32 = 8;
pub const TMR6_STOP_COND_EVT0: u32 = 256;
pub const TMR6_STOP_COND_EVT1: u32 = 512;
pub const TMR6_STOP_COND_TRIGA_RISING: u32 = 65536;
pub const TMR6_STOP_COND_TRIGA_FALLING: u32 = 131072;
pub const TMR6_STOP_COND_TRIGB_RISING: u32 = 262144;
pub const TMR6_STOP_COND_TRIGB_FALLING: u32 = 524288;
pub const TMR6_STOP_COND_ALL: u32 = 983823;
pub const TMR6_CLR_COND_PWMA_RISING: u32 = 1;
pub const TMR6_CLR_COND_PWMA_FALLING: u32 = 2;
pub const TMR6_CLR_COND_PWMB_RISING: u32 = 4;
pub const TMR6_CLR_COND_PWMB_FALLING: u32 = 8;
pub const TMR6_CLR_COND_EVT0: u32 = 256;
pub const TMR6_CLR_COND_EVT1: u32 = 512;
pub const TMR6_CLR_COND_TRIGA_RISING: u32 = 65536;
pub const TMR6_CLR_COND_TRIGA_FALLING: u32 = 131072;
pub const TMR6_CLR_COND_TRIGB_RISING: u32 = 262144;
pub const TMR6_CLR_COND_TRIGB_FALLING: u32 = 524288;
pub const TMR6_CLR_COND_ALL: u32 = 983823;
pub const TMR6_UPD_COND_PWMA_RISING: u32 = 1;
pub const TMR6_UPD_COND_PWMA_FALLING: u32 = 2;
pub const TMR6_UPD_COND_PWMB_RISING: u32 = 4;
pub const TMR6_UPD_COND_PWMB_FALLING: u32 = 8;
pub const TMR6_UPD_COND_EVT0: u32 = 256;
pub const TMR6_UPD_COND_EVT1: u32 = 512;
pub const TMR6_UPD_COND_TRIGA_RISING: u32 = 65536;
pub const TMR6_UPD_COND_TRIGA_FALLING: u32 = 131072;
pub const TMR6_UPD_COND_TRIGB_RISING: u32 = 262144;
pub const TMR6_UPD_COND_TRIGB_FALLING: u32 = 524288;
pub const TMR6_UPD_COND_ALL: u32 = 983823;
pub const TMR6_CAPT_COND_PWMA_RISING: u32 = 1;
pub const TMR6_CAPT_COND_PWMA_FALLING: u32 = 2;
pub const TMR6_CAPT_COND_PWMB_RISING: u32 = 4;
pub const TMR6_CAPT_COND_PWMB_FALLING: u32 = 8;
pub const TMR6_CAPT_COND_EVT0: u32 = 256;
pub const TMR6_CAPT_COND_EVT1: u32 = 512;
pub const TMR6_CAPT_COND_TRIGA_RISING: u32 = 65536;
pub const TMR6_CAPT_COND_TRIGA_FALLING: u32 = 131072;
pub const TMR6_CAPT_COND_TRIGB_RISING: u32 = 262144;
pub const TMR6_CAPT_COND_TRIGB_FALLING: u32 = 524288;
pub const TMR6_CAPT_COND_XOR_RISING: u32 = 16777216;
pub const TMR6_CAPT_COND_XOR_FALLING: u32 = 33554432;
pub const TMR6_CAPT_COND_ALL: u32 = 51315471;
pub const TMR6_CNT_UP_COND_INVD: u32 = 0;
pub const TMR6_CNT_UP_COND_PWMA_LOW_PWMB_RISING: u32 = 1;
pub const TMR6_CNT_UP_COND_PWMA_LOW_PWMB_FALLING: u32 = 2;
pub const TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING: u32 = 4;
pub const TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_FALLING: u32 = 8;
pub const TMR6_CNT_UP_COND_PWMB_LOW_PWMA_RISING: u32 = 16;
pub const TMR6_CNT_UP_COND_PWMB_LOW_PWMA_FALLING: u32 = 32;
pub const TMR6_CNT_UP_COND_PWMB_HIGH_PWMA_RISING: u32 = 64;
pub const TMR6_CNT_UP_COND_PWMB_HIGH_PWMA_FALLING: u32 = 128;
pub const TMR6_CNT_UP_COND_EVT0: u32 = 256;
pub const TMR6_CNT_UP_COND_EVT1: u32 = 512;
pub const TMR6_CNT_UP_COND_TRIGA_RISING: u32 = 65536;
pub const TMR6_CNT_UP_COND_TRIGA_FALLING: u32 = 131072;
pub const TMR6_CNT_UP_COND_TRIGB_RISING: u32 = 262144;
pub const TMR6_CNT_UP_COND_TRIGB_FALLING: u32 = 524288;
pub const TMR6_CNT_UP_COND_ALL: u32 = 984063;
pub const TMR6_CNT_DOWN_COND_INVD: u32 = 0;
pub const TMR6_CNT_DOWN_COND_PWMA_LOW_PWMB_RISING: u32 = 1;
pub const TMR6_CNT_DOWN_COND_PWMA_LOW_PWMB_FALLING: u32 = 2;
pub const TMR6_CNT_DOWN_COND_PWMA_HIGH_PWMB_RISING: u32 = 4;
pub const TMR6_CNT_DOWN_COND_PWMA_HIGH_PWMB_FALLING: u32 = 8;
pub const TMR6_CNT_DOWN_COND_PWMB_LOW_PWMA_RISING: u32 = 16;
pub const TMR6_CNT_DOWN_COND_PWMB_LOW_PWMA_FALLING: u32 = 32;
pub const TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING: u32 = 64;
pub const TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_FALLING: u32 = 128;
pub const TMR6_CNT_DOWN_COND_EVT0: u32 = 256;
pub const TMR6_CNT_DOWN_COND_EVT1: u32 = 512;
pub const TMR6_CNT_DOWN_COND_TRIGA_RISING: u32 = 65536;
pub const TMR6_CNT_DOWN_COND_TRIGA_FALLING: u32 = 131072;
pub const TMR6_CNT_DOWN_COND_TRIGB_RISING: u32 = 262144;
pub const TMR6_CNT_DOWN_COND_TRIGB_FALLING: u32 = 524288;
pub const TMR6_CNT_DOWN_COND_ALL: u32 = 984063;
pub const TMR6_CNT_UP: u32 = 2;
pub const TMR6_CNT_DOWN: u32 = 0;
pub const TMR6_STAT_CNT_UP: u32 = 2147483648;
pub const TMR6_STAT_CNT_DOWN: u32 = 0;
pub const TMR6_MD_SAWTOOTH: u32 = 0;
pub const TMR6_MD_TRIANGLE: u32 = 4;
pub const TMR6_CLK_DIV1: u32 = 0;
pub const TMR6_CLK_DIV2: u32 = 16;
pub const TMR6_CLK_DIV4: u32 = 32;
pub const TMR6_CLK_DIV8: u32 = 48;
pub const TMR6_CLK_DIV16: u32 = 64;
pub const TMR6_CLK_DIV32: u32 = 80;
pub const TMR6_CLK_DIV64: u32 = 96;
pub const TMR6_CLK_DIV128: u32 = 112;
pub const TMR6_CLK_DIV256: u32 = 128;
pub const TMR6_CLK_DIV512: u32 = 144;
pub const TMR6_CLK_DIV1024: u32 = 160;
pub const TMR6_CNT_RELOAD_ON: u32 = 0;
pub const TMR6_CNT_RELOAD_OFF: u32 = 256;
pub const TMR6_ZMASK_FUNC_INVD: u32 = 0;
pub const TMR6_ZMASK_CYCLE_4: u32 = 262144;
pub const TMR6_ZMASK_CYCLE_8: u32 = 524288;
pub const TMR6_ZMASK_CYCLE_16: u32 = 786432;
pub const TMR6_POS_CLR_ZMASK_FUNC_OFF: u32 = 0;
pub const TMR6_POS_CLR_ZMASK_FUNC_ON: u32 = 131072;
pub const TMR6_REVO_CNT_ZMASK_FUNC_OFF: u32 = 0;
pub const TMR6_REVO_CNT_ZMASK_FUNC_ON: u32 = 65536;
pub const en_functional_state_t_DISABLE: en_functional_state_t = 0;
pub const en_functional_state_t_ENABLE: en_functional_state_t = 1;
#[doc = " @brief Functional state"]
pub type en_functional_state_t = ::core::ffi::c_uint;
pub const en_flag_status_t_RESET: en_flag_status_t = 0;
pub const en_flag_status_t_SET: en_flag_status_t = 1;
#[doc = " @brief Flag status"]
pub type en_flag_status_t = ::core::ffi::c_uint;
#[doc = " @brief TMR6"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct CM_TMR6_TypeDef {
    pub CNTER: u32,
    pub UPDAR: u32,
    pub RESERVED0: [u8; 56usize],
    pub PERAR: u32,
    pub PERBR: u32,
    pub PERCR: u32,
    pub RESERVED1: [u8; 52usize],
    pub GCMAR: u32,
    pub GCMBR: u32,
    pub GCMCR: u32,
    pub GCMDR: u32,
    pub GCMER: u32,
    pub GCMFR: u32,
    pub RESERVED2: [u8; 40usize],
    pub SCMAR: u32,
    pub SCMBR: u32,
    pub SCMCR: u32,
    pub SCMDR: u32,
    pub SCMER: u32,
    pub SCMFR: u32,
    pub RESERVED3: [u8; 40usize],
    pub DTUAR: u32,
    pub DTDAR: u32,
    pub DTUBR: u32,
    pub DTDBR: u32,
    pub RESERVED4: [u8; 48usize],
    pub GCONR: u32,
    pub ICONR: u32,
    pub BCONR: u32,
    pub DCONR: u32,
    pub RESERVED5: [u8; 4usize],
    pub PCNAR: u32,
    pub PCNBR: u32,
    pub FCNGR: u32,
    pub VPERR: u32,
    pub STFLR: u32,
    pub RESERVED6: [u8; 24usize],
    pub HSTAR: u32,
    pub HSTPR: u32,
    pub HCLRR: u32,
    pub HUPDR: u32,
    pub HCPAR: u32,
    pub HCPBR: u32,
    pub HCUPR: u32,
    pub HCDOR: u32,
}
#[doc = " @brief Timer6 count function structure definition"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_tmr6_init_t {
    #[doc = "< Specifies the count source @ref TMR6_Count_Src_Define"]
    pub u8CountSrc: u8,
    pub sw_count: stc_tmr6_init_t__bindgen_ty_1,
    pub hw_count: stc_tmr6_init_t__bindgen_ty_2,
    #[doc = "< The period reference value. (0x00 ~ 0xFFFF) or (0x00 ~ 0xFFFFFFFF)"]
    pub u32PeriodValue: u32,
    #[doc = "< Count reload after overflow @ref TMR6_Count_Reload_Define"]
    pub u32CountReload: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_tmr6_init_t__bindgen_ty_1 {
    #[doc = "< Count clock division select, @ref TMR6_Count_Clock_Define"]
    pub u32ClockDiv: u32,
    #[doc = "< Count mode, @ref TMR6_Count_Mode_Define"]
    pub u32CountMode: u32,
    #[doc = "< Count direction, @ref TMR6_Count_Dir_Define"]
    pub u32CountDir: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_tmr6_init_t__bindgen_ty_2 {
    #[doc = "< Hardware count up condition. @ref TMR6_HW_Count_Up_Cond_Define"]
    pub u32CountUpCond: u32,
    #[doc = "< Hardware count down condition. @ref TMR6_HW_Count_Down_Cond_Define"]
    pub u32CountDownCond: u32,
}
#[doc = " @brief Timer6 pwm output function structure definition"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_tmr6_pwm_init_t {
    #[doc = "< Range (0 ~ 0xFFFF) or (0 ~ 0xFFFFFFFF)"]
    pub u32CompareValue: u32,
    #[doc = "< Pin polarity when count start @ref TMR6_Pin_Polarity_Define"]
    pub u32StartPolarity: u32,
    #[doc = "< Pin polarity when count stop @ref TMR6_Pin_Polarity_Define"]
    pub u32StopPolarity: u32,
    #[doc = "< Port state when match compare register A(GCMAR) at count-up mode \\\n@ref TMR6_Pin_Polarity_Define"]
    pub u32CountUpMatchAPolarity: u32,
    #[doc = "< Port state when match compare register A(GCMAR) at count-down mode \\\n@ref TMR6_Pin_Polarity_Define"]
    pub u32CountDownMatchAPolarity: u32,
    #[doc = "< Port state when match compare register B(GCMBR) at count-up mode \\\n@ref TMR6_Pin_Polarity_Define"]
    pub u32CountUpMatchBPolarity: u32,
    #[doc = "< Port state when match compare register B(GCMBR) at count-down mode\\\n@ref TMR6_Pin_Polarity_Define"]
    pub u32CountDownMatchBPolarity: u32,
    #[doc = "< Pin polarity when underflow @ref TMR6_Pin_Polarity_Define"]
    pub u32UdfPolarity: u32,
    #[doc = "< Pin polarity when overflow @ref TMR6_Pin_Polarity_Define"]
    pub u32OvfPolarity: u32,
}
#[doc = " @brief Timer6 buffer function configuration structure definition"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_tmr6_buf_config_t {
    #[doc = "< The buffer number, and this parameter can be a value of \\\n@ref TMR6_Buf_Num_Define"]
    pub u32BufNum: u32,
    #[doc = "< The buffer send time, and this parameter can be a value of \\\n@ref TMR6_Buf_Trans_Cond_Define"]
    pub u32BufTransCond: u32,
}
#[doc = " @brief Timer6 Valid period function configuration structure definition"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_tmr6_valid_period_config_t {
    #[doc = "< The count condition, and this parameter can be a value of \\\n@ref TMR6_Valid_Period_Count_Cond_Define"]
    pub u32CountCond: u32,
    #[doc = "< The interval of the valid period @ref TMR6_Valid_Period_Count_Define"]
    pub u32PeriodInterval: u32,
}
#[doc = " @brief Timer6 EMB configuration structure definition"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_tmr6_emb_config_t {
    #[doc = "< Valid EMB event channel @ref TMR6_Emb_Ch_Define"]
    pub u32ValidCh: u32,
    #[doc = "< Pin release mode when EMB event invalid @ref TMR6_Emb_Release_Mode_Define"]
    pub u32ReleaseMode: u32,
    #[doc = "< Pin output status when EMB event valid @ref TMR6_Emb_Pin_Status_Define"]
    pub u32PinStatus: u32,
}
#[doc = " @brief Timer6 Dead time function configuration structure definition"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_tmr6_deadtime_config_t {
    #[doc = "< Enable down count dead time register equal to up count DT register \\\n@ref TMR6_DeadTime_Reg_Equal_Func_Define"]
    pub u32EqualUpDown: u32,
    #[doc = "< Enable buffer transfer for up count dead time register (DTUBR-->DTUAR) \\\n@ref TMR6_DeadTime_CountUp_Buf_Func_Define"]
    pub u32BufUp: u32,
    #[doc = "< Enable buffer transfer for down count dead time register (DTDBR-->DTDAR) \\\n@ref TMR6_DeadTime_CountDown_Buf_Func_Define"]
    pub u32BufDown: u32,
    #[doc = "< Buffer transfer condition for triangular wave mode \\\n@ref TMR6_DeadTime_Buf_Trans_Cond_Define"]
    pub u32BufTransCond: u32,
}
#[doc = " @brief Timer6 Dead time function configuration structure definition"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_tmr6_zmask_config_t {
    #[doc = "< Z phase input mask periods selection @ref TMR6_Zmask_Cycle_Define"]
    pub u32ZMaskCycle: u32,
    #[doc = "< As position count timer, clear function enable(TRUE) or disable(FALSE) during \\\nthe time of Z phase input mask @ref TMR6_Zmask_Pos_Unit_Clear_Func_Define"]
    pub u32PosCountMaskFunc: u32,
    #[doc = "< As revolution count timer, the counter function enable(TRUE) or disable(FALSE) \\\nduring the time of Z phase input mask \\\n@ref TMR6_Zmask_Revo_Unit_Count_Func_Define"]
    pub u32RevoCountMaskFunc: u32,
}
unsafe extern "C" {
    pub fn TMR6_StructInit(pstcTmr6Init: *mut stc_tmr6_init_t) -> i32;
    pub fn TMR6_Init(TMR6x: *mut CM_TMR6_TypeDef, pstcTmr6Init: *const stc_tmr6_init_t) -> i32;
    pub fn TMR6_SetCountMode(TMR6x: *mut CM_TMR6_TypeDef, u32Mode: u32);
    pub fn TMR6_SetCountDir(TMR6x: *mut CM_TMR6_TypeDef, u32Dir: u32);
    pub fn TMR6_GetCountDir(TMR6x: *mut CM_TMR6_TypeDef) -> u32;
    pub fn TMR6_SetClockDiv(TMR6x: *mut CM_TMR6_TypeDef, u32Div: u32);
    pub fn TMR6_CountReloadCmd(TMR6x: *mut CM_TMR6_TypeDef, enNewState: en_functional_state_t);
    pub fn TMR6_HWCountUpCondCmd(
        TMR6x: *mut CM_TMR6_TypeDef,
        u32Cond: u32,
        enNewState: en_functional_state_t,
    );
    pub fn TMR6_HWCountDownCondCmd(
        TMR6x: *mut CM_TMR6_TypeDef,
        u32Cond: u32,
        enNewState: en_functional_state_t,
    );
    pub fn TMR6_PWM_StructInit(pstcPwmInit: *mut stc_tmr6_pwm_init_t) -> i32;
    pub fn TMR6_PWM_Init(
        TMR6x: *mut CM_TMR6_TypeDef,
        u32Ch: u32,
        pstcPwmInit: *const stc_tmr6_pwm_init_t,
    ) -> i32;
    pub fn TMR6_PWM_OutputCmd(
        TMR6x: *mut CM_TMR6_TypeDef,
        u32Ch: u32,
        enNewState: en_functional_state_t,
    );
    pub fn TMR6_PWM_SetPolarity(
        TMR6x: *mut CM_TMR6_TypeDef,
        u32Ch: u32,
        u32CountState: u32,
        u32Polarity: u32,
    );
    pub fn TMR6_PWM_SetForcePolarity(TMR6x: *mut CM_TMR6_TypeDef, u32Ch: u32, u32Polarity: u32);
    pub fn TMR6_HWCaptureCondCmd(
        TMR6x: *mut CM_TMR6_TypeDef,
        u32Ch: u32,
        u32Cond: u32,
        enNewState: en_functional_state_t,
    );
    pub fn TMR6_SetFilterClockDiv(TMR6x: *mut CM_TMR6_TypeDef, u32Pin: u32, u32Div: u32);
    pub fn TMR6_FilterCmd(
        TMR6x: *mut CM_TMR6_TypeDef,
        u32Pin: u32,
        enNewState: en_functional_state_t,
    );
    pub fn TMR6_SetFunc(TMR6x: *mut CM_TMR6_TypeDef, u32Ch: u32, u32Func: u32);
    pub fn TMR6_IntCmd(
        TMR6x: *mut CM_TMR6_TypeDef,
        u32IntType: u32,
        enNewState: en_functional_state_t,
    );
    pub fn TMR6_GetStatus(TMR6x: *const CM_TMR6_TypeDef, u32Flag: u32) -> en_flag_status_t;
    pub fn TMR6_ClearStatus(TMR6x: *mut CM_TMR6_TypeDef, u32Flag: u32);
    pub fn TMR6_GetPeriodNum(TMR6x: *const CM_TMR6_TypeDef) -> u32;
    pub fn TMR6_DeInit(TMR6x: *mut CM_TMR6_TypeDef);
    pub fn TMR6_Start(TMR6x: *mut CM_TMR6_TypeDef);
    pub fn TMR6_Stop(TMR6x: *mut CM_TMR6_TypeDef);
    pub fn TMR6_SetCountValue(TMR6x: *mut CM_TMR6_TypeDef, u32Value: u32);
    pub fn TMR6_SetUpdateValue(TMR6x: *mut CM_TMR6_TypeDef, u32Value: u32);
    pub fn TMR6_SetPeriodValue(TMR6x: *mut CM_TMR6_TypeDef, u32Index: u32, u32Value: u32);
    pub fn TMR6_SetCompareValue(TMR6x: *mut CM_TMR6_TypeDef, u32Index: u32, u32Value: u32);
    pub fn TMR6_SetSpecialCompareValue(TMR6x: *mut CM_TMR6_TypeDef, u32Index: u32, u32Value: u32);
    pub fn TMR6_SetDeadTimeValue(TMR6x: *mut CM_TMR6_TypeDef, u32Index: u32, u32Value: u32);
    pub fn TMR6_GetCountValue(TMR6x: *const CM_TMR6_TypeDef) -> u32;
    pub fn TMR6_GetUpdateValue(TMR6x: *const CM_TMR6_TypeDef) -> u32;
    pub fn TMR6_GetPeriodValue(TMR6x: *const CM_TMR6_TypeDef, u32Index: u32) -> u32;
    pub fn TMR6_GetCompareValue(TMR6x: *const CM_TMR6_TypeDef, u32Index: u32) -> u32;
    pub fn TMR6_GetSpecialCompareValue(TMR6x: *const CM_TMR6_TypeDef, u32Index: u32) -> u32;
    pub fn TMR6_GetDeadTimeValue(TMR6x: *const CM_TMR6_TypeDef, u32Index: u32) -> u32;
    pub fn TMR6_GeneralBufConfig(
        TMR6x: *mut CM_TMR6_TypeDef,
        u32Ch: u32,
        pstcBufConfig: *const stc_tmr6_buf_config_t,
    ) -> i32;
    pub fn TMR6_PeriodBufConfig(
        TMR6x: *mut CM_TMR6_TypeDef,
        pstcBufConfig: *const stc_tmr6_buf_config_t,
    ) -> i32;
    pub fn TMR6_SpecialBufConfig(
        TMR6x: *mut CM_TMR6_TypeDef,
        u32Ch: u32,
        pstcBufConfig: *const stc_tmr6_buf_config_t,
    ) -> i32;
    pub fn TMR6_GeneralBufCmd(
        TMR6x: *mut CM_TMR6_TypeDef,
        u32Ch: u32,
        enNewState: en_functional_state_t,
    );
    pub fn TMR6_SpecialBufCmd(
        TMR6x: *mut CM_TMR6_TypeDef,
        u32Ch: u32,
        enNewState: en_functional_state_t,
    );
    pub fn TMR6_PeriodBufCmd(TMR6x: *mut CM_TMR6_TypeDef, enNewState: en_functional_state_t);
    pub fn TMR6_ValidPeriodConfig(
        TMR6x: *mut CM_TMR6_TypeDef,
        pstcValidperiodConfig: *const stc_tmr6_valid_period_config_t,
    ) -> i32;
    pub fn TMR6_ValidPeriodCmd(
        TMR6x: *mut CM_TMR6_TypeDef,
        u32Ch: u32,
        enNewState: en_functional_state_t,
    );
    pub fn TMR6_DeadTimeFuncCmd(TMR6x: *mut CM_TMR6_TypeDef, enNewState: en_functional_state_t);
    pub fn TMR6_DeadTimeConfig(
        TMR6x: *mut CM_TMR6_TypeDef,
        pstcDeadTimeConfig: *const stc_tmr6_deadtime_config_t,
    ) -> i32;
    pub fn TMR6_ZMaskConfig(
        TMR6x: *mut CM_TMR6_TypeDef,
        pstcZMaskConfig: *const stc_tmr6_zmask_config_t,
    ) -> i32;
    pub fn TMR6_EMBConfig(
        TMR6x: *mut CM_TMR6_TypeDef,
        u32Ch: u32,
        pstcEmbConfig: *const stc_tmr6_emb_config_t,
    ) -> i32;
    pub fn TMR6_BufFuncStructInit(pstcBufConfig: *mut stc_tmr6_buf_config_t) -> i32;
    pub fn TMR6_ValidPeriodStructInit(
        pstcValidperiodConfig: *mut stc_tmr6_valid_period_config_t,
    ) -> i32;
    pub fn TMR6_EMBConfigStructInit(pstcEmbConfig: *mut stc_tmr6_emb_config_t) -> i32;
    pub fn TMR6_DeadTimeStructInit(pstcDeadTimeConfig: *mut stc_tmr6_deadtime_config_t) -> i32;
    pub fn TMR6_ZMaskConfigStructInit(pstcZMaskConfig: *mut stc_tmr6_zmask_config_t) -> i32;
    pub fn TMR6_SWSyncStart(u32Unit: u32);
    pub fn TMR6_SWSyncStop(u32Unit: u32);
    pub fn TMR6_SWSyncClear(u32Unit: u32);
    pub fn TMR6_SWSyncUpdate(u32Unit: u32);
    pub fn TMR6_HWStartCondCmd(
        TMR6x: *mut CM_TMR6_TypeDef,
        u32Cond: u32,
        enNewState: en_functional_state_t,
    );
    pub fn TMR6_HWStartCmd(TMR6x: *mut CM_TMR6_TypeDef, enNewState: en_functional_state_t);
    pub fn TMR6_HWStopCondCmd(
        TMR6x: *mut CM_TMR6_TypeDef,
        u32Cond: u32,
        enNewState: en_functional_state_t,
    );
    pub fn TMR6_HWStopCmd(TMR6x: *mut CM_TMR6_TypeDef, enNewState: en_functional_state_t);
    pub fn TMR6_HWClearCondCmd(
        TMR6x: *mut CM_TMR6_TypeDef,
        u32Cond: u32,
        enNewState: en_functional_state_t,
    );
    pub fn TMR6_HWClearCmd(TMR6x: *mut CM_TMR6_TypeDef, enNewState: en_functional_state_t);
    pub fn TMR6_HWUpdateCondCmd(
        TMR6x: *mut CM_TMR6_TypeDef,
        u32Cond: u32,
        enNewState: en_functional_state_t,
    );
    pub fn TMR6_HWUpdateCmd(TMR6x: *mut CM_TMR6_TypeDef, enNewState: en_functional_state_t);
}
