/* automatically generated by rust-bindgen 0.72.1 */

pub const DDL_IRQ_PRIO_00: u32 = 0;
pub const DDL_IRQ_PRIO_01: u32 = 1;
pub const DDL_IRQ_PRIO_02: u32 = 2;
pub const DDL_IRQ_PRIO_03: u32 = 3;
pub const DDL_IRQ_PRIO_04: u32 = 4;
pub const DDL_IRQ_PRIO_05: u32 = 5;
pub const DDL_IRQ_PRIO_06: u32 = 6;
pub const DDL_IRQ_PRIO_07: u32 = 7;
pub const DDL_IRQ_PRIO_08: u32 = 8;
pub const DDL_IRQ_PRIO_09: u32 = 9;
pub const DDL_IRQ_PRIO_10: u32 = 10;
pub const DDL_IRQ_PRIO_11: u32 = 11;
pub const DDL_IRQ_PRIO_12: u32 = 12;
pub const DDL_IRQ_PRIO_13: u32 = 13;
pub const DDL_IRQ_PRIO_14: u32 = 14;
pub const DDL_IRQ_PRIO_15: u32 = 15;
pub const DDL_IRQ_PRIO_DEFAULT: u32 = 15;
pub const NMI_SRC_SWDT: u32 = 2;
pub const NMI_SRC_LVD1: u32 = 4;
pub const NMI_SRC_LVD2: u32 = 8;
pub const NMI_SRC_XTAL: u32 = 32;
pub const NMI_SRC_SRAM_PARITY: u32 = 256;
pub const NMI_SRC_SRAM_ECC: u32 = 512;
pub const NMI_SRC_BUS_ERR: u32 = 1024;
pub const NMI_SRC_WDT: u32 = 2048;
pub const NMI_SRC_ALL: u32 = 3886;
pub const EXTINT_CH00: u32 = 1;
pub const EXTINT_CH01: u32 = 2;
pub const EXTINT_CH02: u32 = 4;
pub const EXTINT_CH03: u32 = 8;
pub const EXTINT_CH04: u32 = 16;
pub const EXTINT_CH05: u32 = 32;
pub const EXTINT_CH06: u32 = 64;
pub const EXTINT_CH07: u32 = 128;
pub const EXTINT_CH08: u32 = 256;
pub const EXTINT_CH09: u32 = 512;
pub const EXTINT_CH10: u32 = 1024;
pub const EXTINT_CH11: u32 = 2048;
pub const EXTINT_CH12: u32 = 4096;
pub const EXTINT_CH13: u32 = 8192;
pub const EXTINT_CH14: u32 = 16384;
pub const EXTINT_CH15: u32 = 32768;
pub const EXTINT_CH_ALL: u32 = 65535;
pub const INTC_INT0: u32 = 1;
pub const INTC_INT1: u32 = 2;
pub const INTC_INT2: u32 = 4;
pub const INTC_INT3: u32 = 8;
pub const INTC_INT4: u32 = 16;
pub const INTC_INT5: u32 = 32;
pub const INTC_INT6: u32 = 64;
pub const INTC_INT7: u32 = 128;
pub const INTC_INT8: u32 = 256;
pub const INTC_INT9: u32 = 512;
pub const INTC_INT10: u32 = 1024;
pub const INTC_INT11: u32 = 2048;
pub const INTC_INT12: u32 = 4096;
pub const INTC_INT13: u32 = 8192;
pub const INTC_INT14: u32 = 16384;
pub const INTC_INT15: u32 = 32768;
pub const INTC_INT16: u32 = 65536;
pub const INTC_INT17: u32 = 131072;
pub const INTC_INT18: u32 = 262144;
pub const INTC_INT19: u32 = 524288;
pub const INTC_INT20: u32 = 1048576;
pub const INTC_INT21: u32 = 2097152;
pub const INTC_INT22: u32 = 4194304;
pub const INTC_INT23: u32 = 8388608;
pub const INTC_INT24: u32 = 16777216;
pub const INTC_INT25: u32 = 33554432;
pub const INTC_INT26: u32 = 67108864;
pub const INTC_INT27: u32 = 134217728;
pub const INTC_INT28: u32 = 268435456;
pub const INTC_INT29: u32 = 536870912;
pub const INTC_INT30: u32 = 1073741824;
pub const INTC_INT31: u32 = 2147483648;
pub const INTC_INT_ALL: u32 = 4294967295;
pub const INTC_EVT0: u32 = 1;
pub const INTC_EVT1: u32 = 2;
pub const INTC_EVT2: u32 = 4;
pub const INTC_EVT3: u32 = 8;
pub const INTC_EVT4: u32 = 16;
pub const INTC_EVT5: u32 = 32;
pub const INTC_EVT6: u32 = 64;
pub const INTC_EVT7: u32 = 128;
pub const INTC_EVT8: u32 = 256;
pub const INTC_EVT9: u32 = 512;
pub const INTC_EVT10: u32 = 1024;
pub const INTC_EVT11: u32 = 2048;
pub const INTC_EVT12: u32 = 4096;
pub const INTC_EVT13: u32 = 8192;
pub const INTC_EVT14: u32 = 16384;
pub const INTC_EVT15: u32 = 32768;
pub const INTC_EVT16: u32 = 65536;
pub const INTC_EVT17: u32 = 131072;
pub const INTC_EVT18: u32 = 262144;
pub const INTC_EVT19: u32 = 524288;
pub const INTC_EVT20: u32 = 1048576;
pub const INTC_EVT21: u32 = 2097152;
pub const INTC_EVT22: u32 = 4194304;
pub const INTC_EVT23: u32 = 8388608;
pub const INTC_EVT24: u32 = 16777216;
pub const INTC_EVT25: u32 = 33554432;
pub const INTC_EVT26: u32 = 67108864;
pub const INTC_EVT27: u32 = 134217728;
pub const INTC_EVT28: u32 = 268435456;
pub const INTC_EVT29: u32 = 536870912;
pub const INTC_EVT30: u32 = 1073741824;
pub const INTC_EVT31: u32 = 2147483648;
pub const INTC_EVT_ALL: u32 = 4294967295;
pub const SWINT_CH00: u32 = 1;
pub const SWINT_CH01: u32 = 2;
pub const SWINT_CH02: u32 = 4;
pub const SWINT_CH03: u32 = 8;
pub const SWINT_CH04: u32 = 16;
pub const SWINT_CH05: u32 = 32;
pub const SWINT_CH06: u32 = 64;
pub const SWINT_CH07: u32 = 128;
pub const SWINT_CH08: u32 = 256;
pub const SWINT_CH09: u32 = 512;
pub const SWINT_CH10: u32 = 1024;
pub const SWINT_CH11: u32 = 2048;
pub const SWINT_CH12: u32 = 4096;
pub const SWINT_CH13: u32 = 8192;
pub const SWINT_CH14: u32 = 16384;
pub const SWINT_CH15: u32 = 32768;
pub const SWINT_CH16: u32 = 65536;
pub const SWINT_CH17: u32 = 131072;
pub const SWINT_CH18: u32 = 262144;
pub const SWINT_CH19: u32 = 524288;
pub const SWINT_CH20: u32 = 1048576;
pub const SWINT_CH21: u32 = 2097152;
pub const SWINT_CH22: u32 = 4194304;
pub const SWINT_CH23: u32 = 8388608;
pub const SWINT_CH24: u32 = 16777216;
pub const SWINT_CH25: u32 = 33554432;
pub const SWINT_CH26: u32 = 67108864;
pub const SWINT_CH27: u32 = 134217728;
pub const SWINT_CH28: u32 = 268435456;
pub const SWINT_CH29: u32 = 536870912;
pub const SWINT_CH30: u32 = 1073741824;
pub const SWINT_CH31: u32 = 2147483648;
pub const SWINT_ALL: u32 = 4294967295;
pub const EXTINT_FILTER_OFF: u32 = 0;
pub const EXTINT_FILTER_ON: u32 = 128;
pub const EXTINT_FILTER_B_OFF: u32 = 0;
pub const EXTINT_FILTER_B_ON: u32 = 32768;
pub const EXTINT_FCLK_DIV1: u32 = 0;
pub const EXTINT_FCLK_DIV8: u32 = 16;
pub const EXTINT_FCLK_DIV32: u32 = 32;
pub const EXTINT_FCLK_DIV64: u32 = 48;
pub const EXTINT_FILTER_B_LVL1: u32 = 0;
pub const EXTINT_FILTER_B_LVL2: u32 = 4096;
pub const EXTINT_FILTER_B_LVL3: u32 = 8192;
pub const EXTINT_FILTER_B_LVL4: u32 = 12288;
pub const EXTINT_TRIG_FALLING: u32 = 0;
pub const EXTINT_TRIG_RISING: u32 = 1;
pub const EXTINT_TRIG_BOTH: u32 = 2;
pub const EXTINT_TRIG_LOW: u32 = 3;
pub const INTC_STOP_WKUP_EXTINT_CH0: u32 = 1;
pub const INTC_STOP_WKUP_EXTINT_CH1: u32 = 2;
pub const INTC_STOP_WKUP_EXTINT_CH2: u32 = 4;
pub const INTC_STOP_WKUP_EXTINT_CH3: u32 = 8;
pub const INTC_STOP_WKUP_EXTINT_CH4: u32 = 16;
pub const INTC_STOP_WKUP_EXTINT_CH5: u32 = 32;
pub const INTC_STOP_WKUP_EXTINT_CH6: u32 = 64;
pub const INTC_STOP_WKUP_EXTINT_CH7: u32 = 128;
pub const INTC_STOP_WKUP_EXTINT_CH8: u32 = 256;
pub const INTC_STOP_WKUP_EXTINT_CH9: u32 = 512;
pub const INTC_STOP_WKUP_EXTINT_CH10: u32 = 1024;
pub const INTC_STOP_WKUP_EXTINT_CH11: u32 = 2048;
pub const INTC_STOP_WKUP_EXTINT_CH12: u32 = 4096;
pub const INTC_STOP_WKUP_EXTINT_CH13: u32 = 8192;
pub const INTC_STOP_WKUP_EXTINT_CH14: u32 = 16384;
pub const INTC_STOP_WKUP_EXTINT_CH15: u32 = 32768;
pub const INTC_STOP_WKUP_SWDT: u32 = 65536;
pub const INTC_STOP_WKUP_CMP1: u32 = 524288;
pub const INTC_STOP_WKUP_WKTM: u32 = 1048576;
pub const INTC_STOP_WKUP_RTC_ALM: u32 = 2097152;
pub const INTC_STOP_WKUP_RTC_PRD: u32 = 4194304;
pub const INTC_STOP_WKUP_TMR0_CMP: u32 = 8388608;
pub const INTC_STOP_WKUP_USART1_RX: u32 = 67108864;
pub const INTC_STOP_WKUP_CMP2: u32 = 536870912;
pub const INTC_STOP_WKUP_CMP3: u32 = 1073741824;
pub const INTC_STOP_WKUP_CMP4: u32 = 2147483648;
pub const INTC_WUPEN_ALL: u32 = 3841589247;
#[doc = " @brief Function pointer type to void/void function"]
pub type func_ptr_t = ::core::option::Option<unsafe extern "C" fn()>;
pub const en_functional_state_t_DISABLE: en_functional_state_t = 0;
pub const en_functional_state_t_ENABLE: en_functional_state_t = 1;
#[doc = " @brief Functional state"]
pub type en_functional_state_t = ::core::ffi::c_uint;
pub const en_flag_status_t_RESET: en_flag_status_t = 0;
pub const en_flag_status_t_SET: en_flag_status_t = 1;
#[doc = " @brief Flag status"]
pub type en_flag_status_t = ::core::ffi::c_uint;
pub const IRQn_Type_NMI_IRQn: IRQn_Type = -14;
pub const IRQn_Type_HardFault_IRQn: IRQn_Type = -13;
pub const IRQn_Type_MemManageFault_IRQn: IRQn_Type = -12;
pub const IRQn_Type_BusFault_IRQn: IRQn_Type = -11;
pub const IRQn_Type_UsageFault_IRQn: IRQn_Type = -10;
pub const IRQn_Type_SVC_IRQn: IRQn_Type = -5;
pub const IRQn_Type_DebugMonitor_IRQn: IRQn_Type = -4;
pub const IRQn_Type_PendSV_IRQn: IRQn_Type = -2;
pub const IRQn_Type_SysTick_IRQn: IRQn_Type = -1;
pub const IRQn_Type_INT000_IRQn: IRQn_Type = 0;
pub const IRQn_Type_INT001_IRQn: IRQn_Type = 1;
pub const IRQn_Type_INT002_IRQn: IRQn_Type = 2;
pub const IRQn_Type_INT003_IRQn: IRQn_Type = 3;
pub const IRQn_Type_INT004_IRQn: IRQn_Type = 4;
pub const IRQn_Type_INT005_IRQn: IRQn_Type = 5;
pub const IRQn_Type_INT006_IRQn: IRQn_Type = 6;
pub const IRQn_Type_INT007_IRQn: IRQn_Type = 7;
pub const IRQn_Type_INT008_IRQn: IRQn_Type = 8;
pub const IRQn_Type_INT009_IRQn: IRQn_Type = 9;
pub const IRQn_Type_INT010_IRQn: IRQn_Type = 10;
pub const IRQn_Type_INT011_IRQn: IRQn_Type = 11;
pub const IRQn_Type_INT012_IRQn: IRQn_Type = 12;
pub const IRQn_Type_INT013_IRQn: IRQn_Type = 13;
pub const IRQn_Type_INT014_IRQn: IRQn_Type = 14;
pub const IRQn_Type_INT015_IRQn: IRQn_Type = 15;
pub const IRQn_Type_EXTINT_PORT_EIRQ0_IRQn: IRQn_Type = 16;
pub const IRQn_Type_EXTINT_PORT_EIRQ1_IRQn: IRQn_Type = 17;
pub const IRQn_Type_EXTINT_PORT_EIRQ2_IRQn: IRQn_Type = 18;
pub const IRQn_Type_EXTINT_PORT_EIRQ3_IRQn: IRQn_Type = 19;
pub const IRQn_Type_EXTINT_PORT_EIRQ4_IRQn: IRQn_Type = 20;
pub const IRQn_Type_EXTINT_PORT_EIRQ5_IRQn: IRQn_Type = 21;
pub const IRQn_Type_EXTINT_PORT_EIRQ6_IRQn: IRQn_Type = 22;
pub const IRQn_Type_EXTINT_PORT_EIRQ7_IRQn: IRQn_Type = 23;
pub const IRQn_Type_EXTINT_PORT_EIRQ8_IRQn: IRQn_Type = 24;
pub const IRQn_Type_EXTINT_PORT_EIRQ9_IRQn: IRQn_Type = 25;
pub const IRQn_Type_EXTINT_PORT_EIRQ10_IRQn: IRQn_Type = 26;
pub const IRQn_Type_EXTINT_PORT_EIRQ11_IRQn: IRQn_Type = 27;
pub const IRQn_Type_EXTINT_PORT_EIRQ12_IRQn: IRQn_Type = 28;
pub const IRQn_Type_EXTINT_PORT_EIRQ13_IRQn: IRQn_Type = 29;
pub const IRQn_Type_EXTINT_PORT_EIRQ14_IRQn: IRQn_Type = 30;
pub const IRQn_Type_EXTINT_PORT_EIRQ15_IRQn: IRQn_Type = 31;
pub const IRQn_Type_SWINT0_IRQn: IRQn_Type = 0;
pub const IRQn_Type_SWINT1_IRQn: IRQn_Type = 1;
pub const IRQn_Type_SWINT2_IRQn: IRQn_Type = 2;
pub const IRQn_Type_SWINT3_IRQn: IRQn_Type = 3;
pub const IRQn_Type_SWINT4_IRQn: IRQn_Type = 4;
pub const IRQn_Type_SWINT5_IRQn: IRQn_Type = 5;
pub const IRQn_Type_SWINT6_IRQn: IRQn_Type = 6;
pub const IRQn_Type_SWINT7_IRQn: IRQn_Type = 7;
pub const IRQn_Type_SWINT8_IRQn: IRQn_Type = 8;
pub const IRQn_Type_SWINT9_IRQn: IRQn_Type = 9;
pub const IRQn_Type_SWINT10_IRQn: IRQn_Type = 10;
pub const IRQn_Type_SWINT11_IRQn: IRQn_Type = 11;
pub const IRQn_Type_SWINT12_IRQn: IRQn_Type = 12;
pub const IRQn_Type_SWINT13_IRQn: IRQn_Type = 13;
pub const IRQn_Type_SWINT14_IRQn: IRQn_Type = 14;
pub const IRQn_Type_SWINT15_IRQn: IRQn_Type = 15;
pub const IRQn_Type_SWINT16_IRQn: IRQn_Type = 16;
pub const IRQn_Type_SWINT17_IRQn: IRQn_Type = 17;
pub const IRQn_Type_SWINT18_IRQn: IRQn_Type = 18;
pub const IRQn_Type_SWINT19_IRQn: IRQn_Type = 19;
pub const IRQn_Type_SWINT20_IRQn: IRQn_Type = 20;
pub const IRQn_Type_SWINT21_IRQn: IRQn_Type = 21;
pub const IRQn_Type_SWINT22_IRQn: IRQn_Type = 22;
pub const IRQn_Type_SWINT23_IRQn: IRQn_Type = 23;
pub const IRQn_Type_SWINT24_IRQn: IRQn_Type = 24;
pub const IRQn_Type_SWINT25_IRQn: IRQn_Type = 25;
pub const IRQn_Type_SWINT26_IRQn: IRQn_Type = 26;
pub const IRQn_Type_SWINT27_IRQn: IRQn_Type = 27;
pub const IRQn_Type_SWINT28_IRQn: IRQn_Type = 28;
pub const IRQn_Type_SWINT29_IRQn: IRQn_Type = 29;
pub const IRQn_Type_SWINT30_IRQn: IRQn_Type = 30;
pub const IRQn_Type_SWINT31_IRQn: IRQn_Type = 31;
pub const IRQn_Type_DMA1_ERR_IRQn: IRQn_Type = 32;
pub const IRQn_Type_DMA1_TC0_BTC0_IRQn: IRQn_Type = 33;
pub const IRQn_Type_DMA1_TC1_BTC1_IRQn: IRQn_Type = 34;
pub const IRQn_Type_DMA1_TC2_BTC2_IRQn: IRQn_Type = 35;
pub const IRQn_Type_DMA1_TC3_BTC3_IRQn: IRQn_Type = 36;
pub const IRQn_Type_DMA1_TC4_BTC4_IRQn: IRQn_Type = 37;
pub const IRQn_Type_DMA1_TC5_BTC5_IRQn: IRQn_Type = 38;
pub const IRQn_Type_EFM_PEERR_RDCOL_IRQn: IRQn_Type = 39;
pub const IRQn_Type_EFM_OPTEND_IRQn: IRQn_Type = 40;
pub const IRQn_Type_QSPI_IRQn: IRQn_Type = 41;
pub const IRQn_Type_DCU1_IRQn: IRQn_Type = 42;
pub const IRQn_Type_DCU2_IRQn: IRQn_Type = 43;
pub const IRQn_Type_DCU3_IRQn: IRQn_Type = 44;
pub const IRQn_Type_DCU4_IRQn: IRQn_Type = 45;
pub const IRQn_Type_DMA2_ERR_IRQn: IRQn_Type = 46;
pub const IRQn_Type_DMA2_TC0_BTC0_IRQn: IRQn_Type = 47;
pub const IRQn_Type_DMA2_TC1_BTC1_IRQn: IRQn_Type = 48;
pub const IRQn_Type_DMA2_TC2_BTC2_IRQn: IRQn_Type = 49;
pub const IRQn_Type_DMA2_TC3_BTC3_IRQn: IRQn_Type = 50;
pub const IRQn_Type_DMA2_TC4_BTC4_IRQn: IRQn_Type = 51;
pub const IRQn_Type_DMA2_TC5_BTC5_IRQn: IRQn_Type = 52;
pub const IRQn_Type_TMR0_1_IRQn: IRQn_Type = 53;
pub const IRQn_Type_TMR0_2_IRQn: IRQn_Type = 54;
pub const IRQn_Type_RTC_IRQn: IRQn_Type = 55;
pub const IRQn_Type_XTAL_IRQn: IRQn_Type = 56;
pub const IRQn_Type_WKTM_IRQn: IRQn_Type = 57;
pub const IRQn_Type_SWDT_IRQn: IRQn_Type = 58;
pub const IRQn_Type_TMR6_1_GCMP_IRQn: IRQn_Type = 59;
pub const IRQn_Type_TMR6_1_OVF_UDF_IRQn: IRQn_Type = 60;
pub const IRQn_Type_TMR6_1_DTE_IRQn: IRQn_Type = 61;
pub const IRQn_Type_TMR6_1_SCMP_IRQn: IRQn_Type = 62;
pub const IRQn_Type_TMRA_1_OVF_UDF_IRQn: IRQn_Type = 63;
pub const IRQn_Type_TMRA_1_CMP_IRQn: IRQn_Type = 64;
pub const IRQn_Type_TMR6_2_GCMP_IRQn: IRQn_Type = 65;
pub const IRQn_Type_TMR6_2_OVF_UDF_IRQn: IRQn_Type = 66;
pub const IRQn_Type_TMR6_2_DTE_IRQn: IRQn_Type = 67;
pub const IRQn_Type_TMR6_2_SCMP_IRQn: IRQn_Type = 68;
pub const IRQn_Type_TMRA_2_OVF_UDF_IRQn: IRQn_Type = 69;
pub const IRQn_Type_TMRA_2_CMP_IRQn: IRQn_Type = 70;
pub const IRQn_Type_TMRA_3_OVF_UDF_IRQn: IRQn_Type = 71;
pub const IRQn_Type_TMRA_3_CMP_IRQn: IRQn_Type = 72;
pub const IRQn_Type_TMRA_4_OVF_UDF_IRQn: IRQn_Type = 73;
pub const IRQn_Type_TMRA_4_CMP_IRQn: IRQn_Type = 74;
pub const IRQn_Type_TMR4_1_GCMP_IRQn: IRQn_Type = 75;
pub const IRQn_Type_TMR4_1_OVF_UDF_IRQn: IRQn_Type = 76;
pub const IRQn_Type_TMR4_1_RELOAD_IRQn: IRQn_Type = 77;
pub const IRQn_Type_TMR4_1_SCMP_IRQn: IRQn_Type = 78;
pub const IRQn_Type_TMR4_2_GCMP_IRQn: IRQn_Type = 79;
pub const IRQn_Type_TMR4_2_OVF_UDF_IRQn: IRQn_Type = 80;
pub const IRQn_Type_TMR4_2_RELOAD_IRQn: IRQn_Type = 81;
pub const IRQn_Type_TMR4_2_SCMP_IRQn: IRQn_Type = 82;
pub const IRQn_Type_TMR4_3_GCMP_IRQn: IRQn_Type = 83;
pub const IRQn_Type_TMR4_3_OVF_UDF_IRQn: IRQn_Type = 84;
pub const IRQn_Type_TMR4_3_RELOAD_IRQn: IRQn_Type = 85;
pub const IRQn_Type_TMR4_3_SCMP_IRQn: IRQn_Type = 86;
pub const IRQn_Type_I2C1_IRQn: IRQn_Type = 87;
pub const IRQn_Type_I2C2_IRQn: IRQn_Type = 88;
pub const IRQn_Type_CMP1_IRQn: IRQn_Type = 89;
pub const IRQn_Type_CMP2_IRQn: IRQn_Type = 90;
pub const IRQn_Type_CMP3_IRQn: IRQn_Type = 91;
pub const IRQn_Type_CMP4_IRQn: IRQn_Type = 92;
pub const IRQn_Type_USART1_IRQn: IRQn_Type = 93;
pub const IRQn_Type_USART1_TCI_IRQn: IRQn_Type = 94;
pub const IRQn_Type_USART2_IRQn: IRQn_Type = 95;
pub const IRQn_Type_USART2_TCI_IRQn: IRQn_Type = 96;
pub const IRQn_Type_SPI1_IRQn: IRQn_Type = 97;
pub const IRQn_Type_TMRA_5_OVF_UDF_IRQn: IRQn_Type = 98;
pub const IRQn_Type_TMRA_5_CMP_IRQn: IRQn_Type = 99;
pub const IRQn_Type_EVENT_PORT1_IRQn: IRQn_Type = 100;
pub const IRQn_Type_EVENT_PORT2_IRQn: IRQn_Type = 101;
pub const IRQn_Type_EVENT_PORT3_IRQn: IRQn_Type = 102;
pub const IRQn_Type_EVENT_PORT4_IRQn: IRQn_Type = 103;
pub const IRQn_Type_USART3_IRQn: IRQn_Type = 104;
pub const IRQn_Type_USART3_TCI_IRQn: IRQn_Type = 105;
pub const IRQn_Type_USART4_IRQn: IRQn_Type = 106;
pub const IRQn_Type_USART4_TCI_IRQn: IRQn_Type = 107;
pub const IRQn_Type_SPI2_IRQn: IRQn_Type = 108;
pub const IRQn_Type_SPI3_IRQn: IRQn_Type = 109;
pub const IRQn_Type_EMB_GR0_IRQn: IRQn_Type = 110;
pub const IRQn_Type_EMB_GR1_IRQn: IRQn_Type = 111;
pub const IRQn_Type_EMB_GR2_IRQn: IRQn_Type = 112;
pub const IRQn_Type_EMB_GR3_IRQn: IRQn_Type = 113;
pub const IRQn_Type_USART5_IRQn: IRQn_Type = 114;
pub const IRQn_Type_USART5_TCI_IRQn: IRQn_Type = 115;
pub const IRQn_Type_USART6_IRQn: IRQn_Type = 116;
pub const IRQn_Type_USART6_TCI_IRQn: IRQn_Type = 117;
pub const IRQn_Type_MCAN1_INT0_IRQn: IRQn_Type = 118;
pub const IRQn_Type_MCAN1_INT1_IRQn: IRQn_Type = 119;
pub const IRQn_Type_MCAN2_INT0_IRQn: IRQn_Type = 120;
pub const IRQn_Type_MCAN2_INT1_IRQn: IRQn_Type = 121;
pub const IRQn_Type_USART1_WUPI_IRQn: IRQn_Type = 122;
pub const IRQn_Type_FCM_IRQn: IRQn_Type = 125;
pub const IRQn_Type_WDT_IRQn: IRQn_Type = 126;
pub const IRQn_Type_CTC_IRQn: IRQn_Type = 127;
pub const IRQn_Type_ADC1_IRQn: IRQn_Type = 128;
pub const IRQn_Type_ADC2_IRQn: IRQn_Type = 129;
pub const IRQn_Type_ADC3_IRQn: IRQn_Type = 130;
pub const IRQn_Type_TRNG_IRQn: IRQn_Type = 131;
#[doc = " Interrupt Number Definition"]
pub type IRQn_Type = ::core::ffi::c_int;
pub const en_int_src_t_INT_SRC_SWI_IRQ0: en_int_src_t = 0;
pub const en_int_src_t_INT_SRC_SWI_IRQ1: en_int_src_t = 1;
pub const en_int_src_t_INT_SRC_SWI_IRQ2: en_int_src_t = 2;
pub const en_int_src_t_INT_SRC_SWI_IRQ3: en_int_src_t = 3;
pub const en_int_src_t_INT_SRC_SWI_IRQ4: en_int_src_t = 4;
pub const en_int_src_t_INT_SRC_SWI_IRQ5: en_int_src_t = 5;
pub const en_int_src_t_INT_SRC_SWI_IRQ6: en_int_src_t = 6;
pub const en_int_src_t_INT_SRC_SWI_IRQ7: en_int_src_t = 7;
pub const en_int_src_t_INT_SRC_SWI_IRQ8: en_int_src_t = 8;
pub const en_int_src_t_INT_SRC_SWI_IRQ9: en_int_src_t = 9;
pub const en_int_src_t_INT_SRC_SWI_IRQ10: en_int_src_t = 10;
pub const en_int_src_t_INT_SRC_SWI_IRQ11: en_int_src_t = 11;
pub const en_int_src_t_INT_SRC_SWI_IRQ12: en_int_src_t = 12;
pub const en_int_src_t_INT_SRC_SWI_IRQ13: en_int_src_t = 13;
pub const en_int_src_t_INT_SRC_SWI_IRQ14: en_int_src_t = 14;
pub const en_int_src_t_INT_SRC_SWI_IRQ15: en_int_src_t = 15;
pub const en_int_src_t_INT_SRC_SWI_IRQ16: en_int_src_t = 16;
pub const en_int_src_t_INT_SRC_SWI_IRQ17: en_int_src_t = 17;
pub const en_int_src_t_INT_SRC_SWI_IRQ18: en_int_src_t = 18;
pub const en_int_src_t_INT_SRC_SWI_IRQ19: en_int_src_t = 19;
pub const en_int_src_t_INT_SRC_SWI_IRQ20: en_int_src_t = 20;
pub const en_int_src_t_INT_SRC_SWI_IRQ21: en_int_src_t = 21;
pub const en_int_src_t_INT_SRC_SWI_IRQ22: en_int_src_t = 22;
pub const en_int_src_t_INT_SRC_SWI_IRQ23: en_int_src_t = 23;
pub const en_int_src_t_INT_SRC_SWI_IRQ24: en_int_src_t = 24;
pub const en_int_src_t_INT_SRC_SWI_IRQ25: en_int_src_t = 25;
pub const en_int_src_t_INT_SRC_SWI_IRQ26: en_int_src_t = 26;
pub const en_int_src_t_INT_SRC_SWI_IRQ27: en_int_src_t = 27;
pub const en_int_src_t_INT_SRC_SWI_IRQ28: en_int_src_t = 28;
pub const en_int_src_t_INT_SRC_SWI_IRQ29: en_int_src_t = 29;
pub const en_int_src_t_INT_SRC_SWI_IRQ30: en_int_src_t = 30;
pub const en_int_src_t_INT_SRC_SWI_IRQ31: en_int_src_t = 31;
pub const en_int_src_t_INT_SRC_PORT_EIRQ0: en_int_src_t = 0;
pub const en_int_src_t_INT_SRC_PORT_EIRQ1: en_int_src_t = 1;
pub const en_int_src_t_INT_SRC_PORT_EIRQ2: en_int_src_t = 2;
pub const en_int_src_t_INT_SRC_PORT_EIRQ3: en_int_src_t = 3;
pub const en_int_src_t_INT_SRC_PORT_EIRQ4: en_int_src_t = 4;
pub const en_int_src_t_INT_SRC_PORT_EIRQ5: en_int_src_t = 5;
pub const en_int_src_t_INT_SRC_PORT_EIRQ6: en_int_src_t = 6;
pub const en_int_src_t_INT_SRC_PORT_EIRQ7: en_int_src_t = 7;
pub const en_int_src_t_INT_SRC_PORT_EIRQ8: en_int_src_t = 8;
pub const en_int_src_t_INT_SRC_PORT_EIRQ9: en_int_src_t = 9;
pub const en_int_src_t_INT_SRC_PORT_EIRQ10: en_int_src_t = 10;
pub const en_int_src_t_INT_SRC_PORT_EIRQ11: en_int_src_t = 11;
pub const en_int_src_t_INT_SRC_PORT_EIRQ12: en_int_src_t = 12;
pub const en_int_src_t_INT_SRC_PORT_EIRQ13: en_int_src_t = 13;
pub const en_int_src_t_INT_SRC_PORT_EIRQ14: en_int_src_t = 14;
pub const en_int_src_t_INT_SRC_PORT_EIRQ15: en_int_src_t = 15;
pub const en_int_src_t_INT_SRC_DMA1_ERR: en_int_src_t = 32;
pub const en_int_src_t_INT_SRC_DMA1_TC0: en_int_src_t = 33;
pub const en_int_src_t_INT_SRC_DMA1_BTC0: en_int_src_t = 34;
pub const en_int_src_t_INT_SRC_DMA1_TC1: en_int_src_t = 35;
pub const en_int_src_t_INT_SRC_DMA1_BTC1: en_int_src_t = 36;
pub const en_int_src_t_INT_SRC_DMA1_TC2: en_int_src_t = 37;
pub const en_int_src_t_INT_SRC_DMA1_BTC2: en_int_src_t = 38;
pub const en_int_src_t_INT_SRC_DMA1_TC3: en_int_src_t = 39;
pub const en_int_src_t_INT_SRC_DMA1_BTC3: en_int_src_t = 40;
pub const en_int_src_t_INT_SRC_DMA1_TC4: en_int_src_t = 41;
pub const en_int_src_t_INT_SRC_DMA1_BTC4: en_int_src_t = 42;
pub const en_int_src_t_INT_SRC_DMA1_TC5: en_int_src_t = 43;
pub const en_int_src_t_INT_SRC_DMA1_BTC5: en_int_src_t = 44;
pub const en_int_src_t_INT_SRC_EFM_PEERR: en_int_src_t = 49;
pub const en_int_src_t_INT_SRC_EFM_RDCOL: en_int_src_t = 50;
pub const en_int_src_t_INT_SRC_EFM_OPTEND: en_int_src_t = 51;
pub const en_int_src_t_INT_SRC_QSPI_INTR: en_int_src_t = 54;
pub const en_int_src_t_INT_SRC_DCU1: en_int_src_t = 55;
pub const en_int_src_t_INT_SRC_DCU2: en_int_src_t = 56;
pub const en_int_src_t_INT_SRC_DCU3: en_int_src_t = 57;
pub const en_int_src_t_INT_SRC_DCU4: en_int_src_t = 58;
pub const en_int_src_t_INT_SRC_DMA2_ERR: en_int_src_t = 64;
pub const en_int_src_t_INT_SRC_DMA2_TC0: en_int_src_t = 65;
pub const en_int_src_t_INT_SRC_DMA2_BTC0: en_int_src_t = 66;
pub const en_int_src_t_INT_SRC_DMA2_TC1: en_int_src_t = 67;
pub const en_int_src_t_INT_SRC_DMA2_BTC1: en_int_src_t = 68;
pub const en_int_src_t_INT_SRC_DMA2_TC2: en_int_src_t = 69;
pub const en_int_src_t_INT_SRC_DMA2_BTC2: en_int_src_t = 70;
pub const en_int_src_t_INT_SRC_DMA2_TC3: en_int_src_t = 71;
pub const en_int_src_t_INT_SRC_DMA2_BTC3: en_int_src_t = 72;
pub const en_int_src_t_INT_SRC_DMA2_TC4: en_int_src_t = 73;
pub const en_int_src_t_INT_SRC_DMA2_BTC4: en_int_src_t = 74;
pub const en_int_src_t_INT_SRC_DMA2_TC5: en_int_src_t = 75;
pub const en_int_src_t_INT_SRC_DMA2_BTC5: en_int_src_t = 76;
pub const en_int_src_t_INT_SRC_TMR0_1_CMP_A: en_int_src_t = 96;
pub const en_int_src_t_INT_SRC_TMR0_1_CMP_B: en_int_src_t = 97;
pub const en_int_src_t_INT_SRC_TMR0_1_OVF_A: en_int_src_t = 98;
pub const en_int_src_t_INT_SRC_TMR0_1_OVF_B: en_int_src_t = 99;
pub const en_int_src_t_INT_SRC_TMR0_2_CMP_A: en_int_src_t = 100;
pub const en_int_src_t_INT_SRC_TMR0_2_CMP_B: en_int_src_t = 101;
pub const en_int_src_t_INT_SRC_TMR0_2_OVF_A: en_int_src_t = 102;
pub const en_int_src_t_INT_SRC_TMR0_2_OVF_B: en_int_src_t = 103;
pub const en_int_src_t_INT_SRC_RTC_ALM: en_int_src_t = 121;
pub const en_int_src_t_INT_SRC_RTC_PRD: en_int_src_t = 122;
pub const en_int_src_t_INT_SRC_XTAL_STOP: en_int_src_t = 125;
pub const en_int_src_t_INT_SRC_WKTM_PRD: en_int_src_t = 126;
pub const en_int_src_t_INT_SRC_SWDT_REFUDF: en_int_src_t = 127;
pub const en_int_src_t_INT_SRC_TMR6_1_GCMP_A: en_int_src_t = 128;
pub const en_int_src_t_INT_SRC_TMR6_1_GCMP_B: en_int_src_t = 129;
pub const en_int_src_t_INT_SRC_TMR6_1_GCMP_C: en_int_src_t = 130;
pub const en_int_src_t_INT_SRC_TMR6_1_GCMP_D: en_int_src_t = 131;
pub const en_int_src_t_INT_SRC_TMR6_1_GCMP_E: en_int_src_t = 132;
pub const en_int_src_t_INT_SRC_TMR6_1_GCMP_F: en_int_src_t = 133;
pub const en_int_src_t_INT_SRC_TMR6_1_OVF: en_int_src_t = 134;
pub const en_int_src_t_INT_SRC_TMR6_1_UDF: en_int_src_t = 135;
pub const en_int_src_t_INT_SRC_TMR6_1_DTE: en_int_src_t = 136;
pub const en_int_src_t_INT_SRC_TMR6_1_SCMP_A: en_int_src_t = 137;
pub const en_int_src_t_INT_SRC_TMR6_1_SCMP_B: en_int_src_t = 138;
pub const en_int_src_t_INT_SRC_TMRA_1_OVF: en_int_src_t = 139;
pub const en_int_src_t_INT_SRC_TMRA_1_UDF: en_int_src_t = 140;
pub const en_int_src_t_INT_SRC_TMRA_1_CMP: en_int_src_t = 141;
pub const en_int_src_t_INT_SRC_TMR6_2_GCMP_A: en_int_src_t = 144;
pub const en_int_src_t_INT_SRC_TMR6_2_GCMP_B: en_int_src_t = 145;
pub const en_int_src_t_INT_SRC_TMR6_2_GCMP_C: en_int_src_t = 146;
pub const en_int_src_t_INT_SRC_TMR6_2_GCMP_D: en_int_src_t = 147;
pub const en_int_src_t_INT_SRC_TMR6_2_GCMP_E: en_int_src_t = 148;
pub const en_int_src_t_INT_SRC_TMR6_2_GCMP_F: en_int_src_t = 149;
pub const en_int_src_t_INT_SRC_TMR6_2_OVF: en_int_src_t = 150;
pub const en_int_src_t_INT_SRC_TMR6_2_UDF: en_int_src_t = 151;
pub const en_int_src_t_INT_SRC_TMR6_2_DTE: en_int_src_t = 152;
pub const en_int_src_t_INT_SRC_TMR6_2_SCMP_A: en_int_src_t = 153;
pub const en_int_src_t_INT_SRC_TMR6_2_SCMP_B: en_int_src_t = 154;
pub const en_int_src_t_INT_SRC_TMRA_2_OVF: en_int_src_t = 155;
pub const en_int_src_t_INT_SRC_TMRA_2_UDF: en_int_src_t = 156;
pub const en_int_src_t_INT_SRC_TMRA_2_CMP: en_int_src_t = 157;
pub const en_int_src_t_INT_SRC_TMRA_3_OVF: en_int_src_t = 171;
pub const en_int_src_t_INT_SRC_TMRA_3_UDF: en_int_src_t = 172;
pub const en_int_src_t_INT_SRC_TMRA_3_CMP: en_int_src_t = 173;
pub const en_int_src_t_INT_SRC_TMRA_4_OVF: en_int_src_t = 187;
pub const en_int_src_t_INT_SRC_TMRA_4_UDF: en_int_src_t = 188;
pub const en_int_src_t_INT_SRC_TMRA_4_CMP: en_int_src_t = 189;
pub const en_int_src_t_INT_SRC_TMR4_1_GCMP_UH: en_int_src_t = 192;
pub const en_int_src_t_INT_SRC_TMR4_1_GCMP_UL: en_int_src_t = 193;
pub const en_int_src_t_INT_SRC_TMR4_1_GCMP_VH: en_int_src_t = 194;
pub const en_int_src_t_INT_SRC_TMR4_1_GCMP_VL: en_int_src_t = 195;
pub const en_int_src_t_INT_SRC_TMR4_1_GCMP_WH: en_int_src_t = 196;
pub const en_int_src_t_INT_SRC_TMR4_1_GCMP_WL: en_int_src_t = 197;
pub const en_int_src_t_INT_SRC_TMR4_1_GCMP_XH: en_int_src_t = 198;
pub const en_int_src_t_INT_SRC_TMR4_1_GCMP_XL: en_int_src_t = 199;
pub const en_int_src_t_INT_SRC_TMR4_1_OVF: en_int_src_t = 200;
pub const en_int_src_t_INT_SRC_TMR4_1_UDF: en_int_src_t = 201;
pub const en_int_src_t_INT_SRC_TMR4_1_RELOAD_U: en_int_src_t = 202;
pub const en_int_src_t_INT_SRC_TMR4_1_RELOAD_V: en_int_src_t = 203;
pub const en_int_src_t_INT_SRC_TMR4_1_RELOAD_W: en_int_src_t = 204;
pub const en_int_src_t_INT_SRC_TMR4_1_RELOAD_X: en_int_src_t = 205;
pub const en_int_src_t_INT_SRC_TMR4_1_SCMP0: en_int_src_t = 206;
pub const en_int_src_t_INT_SRC_TMR4_1_SCMP1: en_int_src_t = 207;
pub const en_int_src_t_INT_SRC_TMR4_1_SCMP2: en_int_src_t = 208;
pub const en_int_src_t_INT_SRC_TMR4_1_SCMP3: en_int_src_t = 209;
pub const en_int_src_t_INT_SRC_TMR4_1_SCMP4: en_int_src_t = 210;
pub const en_int_src_t_INT_SRC_TMR4_1_SCMP5: en_int_src_t = 211;
pub const en_int_src_t_INT_SRC_TMR4_1_SCMP6: en_int_src_t = 212;
pub const en_int_src_t_INT_SRC_TMR4_1_SCMP7: en_int_src_t = 213;
pub const en_int_src_t_INT_SRC_TMR4_2_GCMP_UH: en_int_src_t = 224;
pub const en_int_src_t_INT_SRC_TMR4_2_GCMP_UL: en_int_src_t = 225;
pub const en_int_src_t_INT_SRC_TMR4_2_GCMP_VH: en_int_src_t = 226;
pub const en_int_src_t_INT_SRC_TMR4_2_GCMP_VL: en_int_src_t = 227;
pub const en_int_src_t_INT_SRC_TMR4_2_GCMP_WH: en_int_src_t = 228;
pub const en_int_src_t_INT_SRC_TMR4_2_GCMP_WL: en_int_src_t = 229;
pub const en_int_src_t_INT_SRC_TMR4_2_GCMP_XH: en_int_src_t = 230;
pub const en_int_src_t_INT_SRC_TMR4_2_GCMP_XL: en_int_src_t = 231;
pub const en_int_src_t_INT_SRC_TMR4_2_OVF: en_int_src_t = 232;
pub const en_int_src_t_INT_SRC_TMR4_2_UDF: en_int_src_t = 233;
pub const en_int_src_t_INT_SRC_TMR4_2_RELOAD_U: en_int_src_t = 234;
pub const en_int_src_t_INT_SRC_TMR4_2_RELOAD_V: en_int_src_t = 235;
pub const en_int_src_t_INT_SRC_TMR4_2_RELOAD_W: en_int_src_t = 236;
pub const en_int_src_t_INT_SRC_TMR4_2_RELOAD_X: en_int_src_t = 237;
pub const en_int_src_t_INT_SRC_TMR4_2_SCMP0: en_int_src_t = 238;
pub const en_int_src_t_INT_SRC_TMR4_2_SCMP1: en_int_src_t = 239;
pub const en_int_src_t_INT_SRC_TMR4_2_SCMP2: en_int_src_t = 240;
pub const en_int_src_t_INT_SRC_TMR4_2_SCMP3: en_int_src_t = 241;
pub const en_int_src_t_INT_SRC_TMR4_2_SCMP4: en_int_src_t = 242;
pub const en_int_src_t_INT_SRC_TMR4_2_SCMP5: en_int_src_t = 243;
pub const en_int_src_t_INT_SRC_TMR4_2_SCMP6: en_int_src_t = 244;
pub const en_int_src_t_INT_SRC_TMR4_2_SCMP7: en_int_src_t = 245;
pub const en_int_src_t_INT_SRC_TMR4_3_GCMP_UH: en_int_src_t = 256;
pub const en_int_src_t_INT_SRC_TMR4_3_GCMP_UL: en_int_src_t = 257;
pub const en_int_src_t_INT_SRC_TMR4_3_GCMP_VH: en_int_src_t = 258;
pub const en_int_src_t_INT_SRC_TMR4_3_GCMP_VL: en_int_src_t = 259;
pub const en_int_src_t_INT_SRC_TMR4_3_GCMP_WH: en_int_src_t = 260;
pub const en_int_src_t_INT_SRC_TMR4_3_GCMP_WL: en_int_src_t = 261;
pub const en_int_src_t_INT_SRC_TMR4_3_GCMP_XH: en_int_src_t = 262;
pub const en_int_src_t_INT_SRC_TMR4_3_GCMP_XL: en_int_src_t = 263;
pub const en_int_src_t_INT_SRC_TMR4_3_OVF: en_int_src_t = 264;
pub const en_int_src_t_INT_SRC_TMR4_3_UDF: en_int_src_t = 265;
pub const en_int_src_t_INT_SRC_TMR4_3_RELOAD_U: en_int_src_t = 266;
pub const en_int_src_t_INT_SRC_TMR4_3_RELOAD_V: en_int_src_t = 267;
pub const en_int_src_t_INT_SRC_TMR4_3_RELOAD_W: en_int_src_t = 268;
pub const en_int_src_t_INT_SRC_TMR4_3_RELOAD_X: en_int_src_t = 269;
pub const en_int_src_t_INT_SRC_TMR4_3_SCMP0: en_int_src_t = 270;
pub const en_int_src_t_INT_SRC_TMR4_3_SCMP1: en_int_src_t = 271;
pub const en_int_src_t_INT_SRC_TMR4_3_SCMP2: en_int_src_t = 272;
pub const en_int_src_t_INT_SRC_TMR4_3_SCMP3: en_int_src_t = 273;
pub const en_int_src_t_INT_SRC_TMR4_3_SCMP4: en_int_src_t = 274;
pub const en_int_src_t_INT_SRC_TMR4_3_SCMP5: en_int_src_t = 275;
pub const en_int_src_t_INT_SRC_TMR4_3_SCMP6: en_int_src_t = 276;
pub const en_int_src_t_INT_SRC_TMR4_3_SCMP7: en_int_src_t = 277;
pub const en_int_src_t_INT_SRC_I2C1_RXI: en_int_src_t = 288;
pub const en_int_src_t_INT_SRC_I2C1_TXI: en_int_src_t = 289;
pub const en_int_src_t_INT_SRC_I2C1_TEI: en_int_src_t = 290;
pub const en_int_src_t_INT_SRC_I2C1_EEI: en_int_src_t = 291;
pub const en_int_src_t_INT_SRC_I2C2_RXI: en_int_src_t = 292;
pub const en_int_src_t_INT_SRC_I2C2_TXI: en_int_src_t = 293;
pub const en_int_src_t_INT_SRC_I2C2_TEI: en_int_src_t = 294;
pub const en_int_src_t_INT_SRC_I2C2_EEI: en_int_src_t = 295;
pub const en_int_src_t_INT_SRC_CMP1: en_int_src_t = 312;
pub const en_int_src_t_INT_SRC_CMP2: en_int_src_t = 313;
pub const en_int_src_t_INT_SRC_CMP3: en_int_src_t = 314;
pub const en_int_src_t_INT_SRC_CMP4: en_int_src_t = 315;
pub const en_int_src_t_INT_SRC_USART1_EI: en_int_src_t = 321;
pub const en_int_src_t_INT_SRC_USART1_RI: en_int_src_t = 322;
pub const en_int_src_t_INT_SRC_USART1_TI: en_int_src_t = 323;
pub const en_int_src_t_INT_SRC_USART1_RTO: en_int_src_t = 324;
pub const en_int_src_t_INT_SRC_USART1_TENDI: en_int_src_t = 325;
pub const en_int_src_t_INT_SRC_USART1_TCI: en_int_src_t = 326;
pub const en_int_src_t_INT_SRC_USART2_EI: en_int_src_t = 328;
pub const en_int_src_t_INT_SRC_USART2_RI: en_int_src_t = 329;
pub const en_int_src_t_INT_SRC_USART2_TI: en_int_src_t = 330;
pub const en_int_src_t_INT_SRC_USART2_RTO: en_int_src_t = 331;
pub const en_int_src_t_INT_SRC_USART2_TENDI: en_int_src_t = 332;
pub const en_int_src_t_INT_SRC_USART2_TCI: en_int_src_t = 333;
pub const en_int_src_t_INT_SRC_SPI1_SPRI: en_int_src_t = 334;
pub const en_int_src_t_INT_SRC_SPI1_SPTI: en_int_src_t = 335;
pub const en_int_src_t_INT_SRC_SPI1_SPII: en_int_src_t = 336;
pub const en_int_src_t_INT_SRC_SPI1_SPEI: en_int_src_t = 337;
pub const en_int_src_t_INT_SRC_TMRA_5_OVF: en_int_src_t = 340;
pub const en_int_src_t_INT_SRC_TMRA_5_UDF: en_int_src_t = 341;
pub const en_int_src_t_INT_SRC_TMRA_5_CMP: en_int_src_t = 342;
pub const en_int_src_t_INT_SRC_EVENT_PORT1: en_int_src_t = 348;
pub const en_int_src_t_INT_SRC_EVENT_PORT2: en_int_src_t = 349;
pub const en_int_src_t_INT_SRC_EVENT_PORT3: en_int_src_t = 350;
pub const en_int_src_t_INT_SRC_EVENT_PORT4: en_int_src_t = 351;
pub const en_int_src_t_INT_SRC_USART3_BRKWKPI: en_int_src_t = 352;
pub const en_int_src_t_INT_SRC_USART3_EI: en_int_src_t = 353;
pub const en_int_src_t_INT_SRC_USART3_RI: en_int_src_t = 354;
pub const en_int_src_t_INT_SRC_USART3_TI: en_int_src_t = 355;
pub const en_int_src_t_INT_SRC_USART3_TENDI: en_int_src_t = 357;
pub const en_int_src_t_INT_SRC_USART3_TCI: en_int_src_t = 358;
pub const en_int_src_t_INT_SRC_USART4_EI: en_int_src_t = 360;
pub const en_int_src_t_INT_SRC_USART4_RI: en_int_src_t = 361;
pub const en_int_src_t_INT_SRC_USART4_TI: en_int_src_t = 362;
pub const en_int_src_t_INT_SRC_USART4_RTO: en_int_src_t = 363;
pub const en_int_src_t_INT_SRC_USART4_TENDI: en_int_src_t = 364;
pub const en_int_src_t_INT_SRC_USART4_TCI: en_int_src_t = 365;
pub const en_int_src_t_INT_SRC_SPI2_SPRI: en_int_src_t = 366;
pub const en_int_src_t_INT_SRC_SPI2_SPTI: en_int_src_t = 367;
pub const en_int_src_t_INT_SRC_SPI2_SPII: en_int_src_t = 368;
pub const en_int_src_t_INT_SRC_SPI2_SPEI: en_int_src_t = 369;
pub const en_int_src_t_INT_SRC_SPI3_SPRI: en_int_src_t = 371;
pub const en_int_src_t_INT_SRC_SPI3_SPTI: en_int_src_t = 372;
pub const en_int_src_t_INT_SRC_SPI3_SPII: en_int_src_t = 373;
pub const en_int_src_t_INT_SRC_SPI3_SPEI: en_int_src_t = 374;
pub const en_int_src_t_INT_SRC_EMB_GR0: en_int_src_t = 376;
pub const en_int_src_t_INT_SRC_EMB_GR1: en_int_src_t = 377;
pub const en_int_src_t_INT_SRC_EMB_GR2: en_int_src_t = 378;
pub const en_int_src_t_INT_SRC_EMB_GR3: en_int_src_t = 379;
pub const en_int_src_t_INT_SRC_USART5_EI: en_int_src_t = 385;
pub const en_int_src_t_INT_SRC_USART5_RI: en_int_src_t = 386;
pub const en_int_src_t_INT_SRC_USART5_TI: en_int_src_t = 387;
pub const en_int_src_t_INT_SRC_USART5_RTO: en_int_src_t = 388;
pub const en_int_src_t_INT_SRC_USART5_TENDI: en_int_src_t = 389;
pub const en_int_src_t_INT_SRC_USART5_TCI: en_int_src_t = 390;
pub const en_int_src_t_INT_SRC_USART6_BRKWKPI: en_int_src_t = 391;
pub const en_int_src_t_INT_SRC_USART6_EI: en_int_src_t = 392;
pub const en_int_src_t_INT_SRC_USART6_RI: en_int_src_t = 393;
pub const en_int_src_t_INT_SRC_USART6_TI: en_int_src_t = 394;
pub const en_int_src_t_INT_SRC_USART6_TENDI: en_int_src_t = 395;
pub const en_int_src_t_INT_SRC_USART6_TCI: en_int_src_t = 396;
pub const en_int_src_t_INT_SRC_MCAN1_INT0: en_int_src_t = 408;
pub const en_int_src_t_INT_SRC_MCAN1_INT1: en_int_src_t = 409;
pub const en_int_src_t_INT_SRC_MCAN2_INT0: en_int_src_t = 410;
pub const en_int_src_t_INT_SRC_MCAN2_INT1: en_int_src_t = 411;
pub const en_int_src_t_INT_SRC_USART1_WUPI: en_int_src_t = 464;
pub const en_int_src_t_INT_SRC_FCMFERRI: en_int_src_t = 468;
pub const en_int_src_t_INT_SRC_FCMMENDI: en_int_src_t = 469;
pub const en_int_src_t_INT_SRC_FCMCOVFI: en_int_src_t = 470;
pub const en_int_src_t_INT_SRC_WDT_REFUDF: en_int_src_t = 471;
pub const en_int_src_t_INT_SRC_CTC_ERR: en_int_src_t = 472;
pub const en_int_src_t_INT_SRC_ADC1_EOCA: en_int_src_t = 480;
pub const en_int_src_t_INT_SRC_ADC1_EOCB: en_int_src_t = 481;
pub const en_int_src_t_INT_SRC_ADC1_CMP0: en_int_src_t = 482;
pub const en_int_src_t_INT_SRC_ADC1_CMP1: en_int_src_t = 483;
pub const en_int_src_t_INT_SRC_ADC2_EOCA: en_int_src_t = 484;
pub const en_int_src_t_INT_SRC_ADC2_EOCB: en_int_src_t = 485;
pub const en_int_src_t_INT_SRC_ADC2_CMP0: en_int_src_t = 486;
pub const en_int_src_t_INT_SRC_ADC2_CMP1: en_int_src_t = 487;
pub const en_int_src_t_INT_SRC_ADC3_EOCA: en_int_src_t = 488;
pub const en_int_src_t_INT_SRC_ADC3_EOCB: en_int_src_t = 489;
pub const en_int_src_t_INT_SRC_ADC3_CMP0: en_int_src_t = 490;
pub const en_int_src_t_INT_SRC_ADC3_CMP1: en_int_src_t = 491;
pub const en_int_src_t_INT_SRC_TRNG_END: en_int_src_t = 492;
pub const en_int_src_t_INT_SRC_MAX: en_int_src_t = 511;
#[doc = " \\brief Interrupt number enumeration"]
pub type en_int_src_t = ::core::ffi::c_uint;
#[doc = " @brief  Interrupt registration structure definition"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_irq_signin_config_t {
    #[doc = "< Peripheral interrupt number, can be any value @ref en_int_src_t"]
    pub enIntSrc: en_int_src_t,
    #[doc = "< Peripheral IRQ type, can be INT000_IRQn~INT127_IRQn @ref IRQn_Type"]
    pub enIRQn: IRQn_Type,
    #[doc = "< Callback function for corresponding peripheral IRQ"]
    pub pfnCallback: func_ptr_t,
}
#[doc = " @brief  NMI initialize configuration structure definition"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_nmi_init_t {
    #[doc = "< NMI trigger source, @ref NMI_TriggerSrc_Sel for details"]
    pub u32Src: u32,
}
#[doc = " @brief  EXTINT initialize configuration structure definition"]
#[repr(C)]
#[derive(Debug, Copy, Clone, PartialEq)]
pub struct stc_extint_init_t {
    #[doc = "< ExtInt filter (A) function setting, @ref EXTINT_FilterClock_Sel for details"]
    pub u32Filter: u32,
    #[doc = "< ExtInt filter (A) clock division, @ref EXTINT_FilterClock_Div for details"]
    pub u32FilterClock: u32,
    #[doc = "< ExtInt trigger edge, @ref EXTINT_Trigger_Sel for details"]
    pub u32Edge: u32,
    #[doc = "< ExtInt filter B function setting, @ref EXTINT_FilterBClock_Sel for details"]
    pub u32FilterB: u32,
    #[doc = "< ExtInt filter B time, @ref EXTINT_FilterBTim_Sel for details"]
    pub u32FilterBClock: u32,
}
unsafe extern "C" {
    #[doc = "Global function prototypes (definition in C source)\n/\n/**\n @addtogroup INTC_Global_Functions\n @{"]
    pub fn INTC_IrqSignIn(pstcIrqSignConfig: *const stc_irq_signin_config_t) -> i32;
    pub fn INTC_IrqSignOut(enIRQn: IRQn_Type) -> i32;
    pub fn INTC_IrqInstallHandle(
        enIRQn: IRQn_Type,
        enIntSrc: en_int_src_t,
        u16Prio: u16,
        pfnCallback: func_ptr_t,
    ) -> i32;
    pub fn INTC_WakeupSrcCmd(u32WakeupSrc: u32, enNewState: en_functional_state_t);
    pub fn INTC_EventCmd(u32Event: u32, enNewState: en_functional_state_t);
    pub fn INTC_IntCmd(u32Int: u32, enNewState: en_functional_state_t);
    pub fn INTC_SWIntInit(u32Ch: u32, pfnCallback: func_ptr_t, u32Priority: u32);
    pub fn INTC_SWIntCmd(u32SWInt: u32, enNewState: en_functional_state_t);
    pub fn NMI_Init(pstcNmiInit: *const stc_nmi_init_t) -> i32;
    pub fn NMI_StructInit(pstcNmiInit: *mut stc_nmi_init_t) -> i32;
    pub fn NMI_GetNmiStatus(u32Src: u32) -> en_flag_status_t;
    pub fn NMI_NmiSrcCmd(u32Src: u32, enNewState: en_functional_state_t);
    pub fn NMI_ClearNmiStatus(u32Src: u32);
    pub fn EXTINT_Init(u32Ch: u32, pstcExtIntInit: *const stc_extint_init_t) -> i32;
    pub fn EXTINT_StructInit(pstcExtIntInit: *mut stc_extint_init_t) -> i32;
    pub fn EXTINT_GetExtIntStatus(u32ExtIntCh: u32) -> en_flag_status_t;
    pub fn EXTINT_ClearExtIntStatus(u32ExtIntCh: u32);
    pub fn INTC_IntSrcCmd(enIntSrc: en_int_src_t, enNewState: en_functional_state_t);
    pub fn INTC_GetIntSrcState(enIntSrc: en_int_src_t) -> en_functional_state_t;
    pub fn IRQ000_Handler();
    pub fn IRQ001_Handler();
    pub fn IRQ002_Handler();
    pub fn IRQ003_Handler();
    pub fn IRQ004_Handler();
    pub fn IRQ005_Handler();
    pub fn IRQ006_Handler();
    pub fn IRQ007_Handler();
    pub fn IRQ008_Handler();
    pub fn IRQ009_Handler();
    pub fn IRQ010_Handler();
    pub fn IRQ011_Handler();
    pub fn IRQ012_Handler();
    pub fn IRQ013_Handler();
    pub fn IRQ014_Handler();
    pub fn IRQ015_Handler();
}
