#[doc = "Register `EOTINTCLR` writer"]
pub type W = crate::W<EotintclrSpec>;
#[doc = "Field `EPTXINTCLR0` writer - Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
pub type Eptxintclr0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `EPTXINTCLR1` writer - Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
pub type Eptxintclr1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `EPTXINTCLR2` writer - Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
pub type Eptxintclr2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `EPTXINTCLR3` writer - Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
pub type Eptxintclr3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `EPTXINTCLR4` writer - Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
pub type Eptxintclr4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `EPTXINTCLR5` writer - Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
pub type Eptxintclr5W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `EPTXINTCLR6` writer - Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
pub type Eptxintclr6W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `EPTXINTCLR7` writer - Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
pub type Eptxintclr7W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `EPTXINTCLR8` writer - Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
pub type Eptxintclr8W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `EPTXINTCLR9` writer - Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
pub type Eptxintclr9W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `EPTXINTCLR10` writer - Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
pub type Eptxintclr10W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `EPTXINTCLR11` writer - Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
pub type Eptxintclr11W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `EPTXINTCLR12` writer - Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
pub type Eptxintclr12W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `EPTXINTCLR13` writer - Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
pub type Eptxintclr13W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `EPTXINTCLR14` writer - Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
pub type Eptxintclr14W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `EPTXINTCLR15` writer - Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
pub type Eptxintclr15W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `EPTXINTCLR16` writer - Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
pub type Eptxintclr16W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `EPTXINTCLR17` writer - Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
pub type Eptxintclr17W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `EPTXINTCLR18` writer - Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
pub type Eptxintclr18W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `EPTXINTCLR19` writer - Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
pub type Eptxintclr19W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `EPTXINTCLR20` writer - Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
pub type Eptxintclr20W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `EPTXINTCLR21` writer - Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
pub type Eptxintclr21W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `EPTXINTCLR22` writer - Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
pub type Eptxintclr22W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `EPTXINTCLR23` writer - Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
pub type Eptxintclr23W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `EPTXINTCLR24` writer - Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
pub type Eptxintclr24W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `EPTXINTCLR25` writer - Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
pub type Eptxintclr25W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `EPTXINTCLR26` writer - Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
pub type Eptxintclr26W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `EPTXINTCLR27` writer - Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
pub type Eptxintclr27W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `EPTXINTCLR28` writer - Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
pub type Eptxintclr28W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `EPTXINTCLR29` writer - Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
pub type Eptxintclr29W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `EPTXINTCLR30` writer - Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
pub type Eptxintclr30W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `EPTXINTCLR31` writer - Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
pub type Eptxintclr31W<'a, REG> = crate::BitWriter<'a, REG>;
impl W {
    #[doc = "Bit 0 - Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
    #[inline(always)]
    pub fn eptxintclr0(&mut self) -> Eptxintclr0W<'_, EotintclrSpec> {
        Eptxintclr0W::new(self, 0)
    }
    #[doc = "Bit 1 - Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
    #[inline(always)]
    pub fn eptxintclr1(&mut self) -> Eptxintclr1W<'_, EotintclrSpec> {
        Eptxintclr1W::new(self, 1)
    }
    #[doc = "Bit 2 - Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
    #[inline(always)]
    pub fn eptxintclr2(&mut self) -> Eptxintclr2W<'_, EotintclrSpec> {
        Eptxintclr2W::new(self, 2)
    }
    #[doc = "Bit 3 - Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
    #[inline(always)]
    pub fn eptxintclr3(&mut self) -> Eptxintclr3W<'_, EotintclrSpec> {
        Eptxintclr3W::new(self, 3)
    }
    #[doc = "Bit 4 - Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
    #[inline(always)]
    pub fn eptxintclr4(&mut self) -> Eptxintclr4W<'_, EotintclrSpec> {
        Eptxintclr4W::new(self, 4)
    }
    #[doc = "Bit 5 - Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
    #[inline(always)]
    pub fn eptxintclr5(&mut self) -> Eptxintclr5W<'_, EotintclrSpec> {
        Eptxintclr5W::new(self, 5)
    }
    #[doc = "Bit 6 - Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
    #[inline(always)]
    pub fn eptxintclr6(&mut self) -> Eptxintclr6W<'_, EotintclrSpec> {
        Eptxintclr6W::new(self, 6)
    }
    #[doc = "Bit 7 - Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
    #[inline(always)]
    pub fn eptxintclr7(&mut self) -> Eptxintclr7W<'_, EotintclrSpec> {
        Eptxintclr7W::new(self, 7)
    }
    #[doc = "Bit 8 - Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
    #[inline(always)]
    pub fn eptxintclr8(&mut self) -> Eptxintclr8W<'_, EotintclrSpec> {
        Eptxintclr8W::new(self, 8)
    }
    #[doc = "Bit 9 - Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
    #[inline(always)]
    pub fn eptxintclr9(&mut self) -> Eptxintclr9W<'_, EotintclrSpec> {
        Eptxintclr9W::new(self, 9)
    }
    #[doc = "Bit 10 - Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
    #[inline(always)]
    pub fn eptxintclr10(&mut self) -> Eptxintclr10W<'_, EotintclrSpec> {
        Eptxintclr10W::new(self, 10)
    }
    #[doc = "Bit 11 - Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
    #[inline(always)]
    pub fn eptxintclr11(&mut self) -> Eptxintclr11W<'_, EotintclrSpec> {
        Eptxintclr11W::new(self, 11)
    }
    #[doc = "Bit 12 - Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
    #[inline(always)]
    pub fn eptxintclr12(&mut self) -> Eptxintclr12W<'_, EotintclrSpec> {
        Eptxintclr12W::new(self, 12)
    }
    #[doc = "Bit 13 - Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
    #[inline(always)]
    pub fn eptxintclr13(&mut self) -> Eptxintclr13W<'_, EotintclrSpec> {
        Eptxintclr13W::new(self, 13)
    }
    #[doc = "Bit 14 - Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
    #[inline(always)]
    pub fn eptxintclr14(&mut self) -> Eptxintclr14W<'_, EotintclrSpec> {
        Eptxintclr14W::new(self, 14)
    }
    #[doc = "Bit 15 - Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
    #[inline(always)]
    pub fn eptxintclr15(&mut self) -> Eptxintclr15W<'_, EotintclrSpec> {
        Eptxintclr15W::new(self, 15)
    }
    #[doc = "Bit 16 - Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
    #[inline(always)]
    pub fn eptxintclr16(&mut self) -> Eptxintclr16W<'_, EotintclrSpec> {
        Eptxintclr16W::new(self, 16)
    }
    #[doc = "Bit 17 - Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
    #[inline(always)]
    pub fn eptxintclr17(&mut self) -> Eptxintclr17W<'_, EotintclrSpec> {
        Eptxintclr17W::new(self, 17)
    }
    #[doc = "Bit 18 - Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
    #[inline(always)]
    pub fn eptxintclr18(&mut self) -> Eptxintclr18W<'_, EotintclrSpec> {
        Eptxintclr18W::new(self, 18)
    }
    #[doc = "Bit 19 - Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
    #[inline(always)]
    pub fn eptxintclr19(&mut self) -> Eptxintclr19W<'_, EotintclrSpec> {
        Eptxintclr19W::new(self, 19)
    }
    #[doc = "Bit 20 - Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
    #[inline(always)]
    pub fn eptxintclr20(&mut self) -> Eptxintclr20W<'_, EotintclrSpec> {
        Eptxintclr20W::new(self, 20)
    }
    #[doc = "Bit 21 - Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
    #[inline(always)]
    pub fn eptxintclr21(&mut self) -> Eptxintclr21W<'_, EotintclrSpec> {
        Eptxintclr21W::new(self, 21)
    }
    #[doc = "Bit 22 - Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
    #[inline(always)]
    pub fn eptxintclr22(&mut self) -> Eptxintclr22W<'_, EotintclrSpec> {
        Eptxintclr22W::new(self, 22)
    }
    #[doc = "Bit 23 - Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
    #[inline(always)]
    pub fn eptxintclr23(&mut self) -> Eptxintclr23W<'_, EotintclrSpec> {
        Eptxintclr23W::new(self, 23)
    }
    #[doc = "Bit 24 - Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
    #[inline(always)]
    pub fn eptxintclr24(&mut self) -> Eptxintclr24W<'_, EotintclrSpec> {
        Eptxintclr24W::new(self, 24)
    }
    #[doc = "Bit 25 - Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
    #[inline(always)]
    pub fn eptxintclr25(&mut self) -> Eptxintclr25W<'_, EotintclrSpec> {
        Eptxintclr25W::new(self, 25)
    }
    #[doc = "Bit 26 - Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
    #[inline(always)]
    pub fn eptxintclr26(&mut self) -> Eptxintclr26W<'_, EotintclrSpec> {
        Eptxintclr26W::new(self, 26)
    }
    #[doc = "Bit 27 - Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
    #[inline(always)]
    pub fn eptxintclr27(&mut self) -> Eptxintclr27W<'_, EotintclrSpec> {
        Eptxintclr27W::new(self, 27)
    }
    #[doc = "Bit 28 - Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
    #[inline(always)]
    pub fn eptxintclr28(&mut self) -> Eptxintclr28W<'_, EotintclrSpec> {
        Eptxintclr28W::new(self, 28)
    }
    #[doc = "Bit 29 - Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
    #[inline(always)]
    pub fn eptxintclr29(&mut self) -> Eptxintclr29W<'_, EotintclrSpec> {
        Eptxintclr29W::new(self, 29)
    }
    #[doc = "Bit 30 - Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
    #[inline(always)]
    pub fn eptxintclr30(&mut self) -> Eptxintclr30W<'_, EotintclrSpec> {
        Eptxintclr30W::new(self, 30)
    }
    #[doc = "Bit 31 - Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register."]
    #[inline(always)]
    pub fn eptxintclr31(&mut self) -> Eptxintclr31W<'_, EotintclrSpec> {
        Eptxintclr31W::new(self, 31)
    }
}
#[doc = "USB End of Transfer Interrupt Clear\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`eotintclr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EotintclrSpec;
impl crate::RegisterSpec for EotintclrSpec {
    type Ux = u32;
}
#[doc = "`write(|w| ..)` method takes [`eotintclr::W`](W) writer structure"]
impl crate::Writable for EotintclrSpec {
    type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets EOTINTCLR to value 0"]
impl crate::Resettable for EotintclrSpec {}
