#[doc = "Register `SYNC` reader"]
pub type R = crate::R<SyncSpec>;
#[doc = "Register `SYNC` writer"]
pub type W = crate::W<SyncSpec>;
#[doc = "Field `DMACSYNC0` reader - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled."]
pub type Dmacsync0R = crate::BitReader;
#[doc = "Field `DMACSYNC0` writer - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled."]
pub type Dmacsync0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DMACSYNC1` reader - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled."]
pub type Dmacsync1R = crate::BitReader;
#[doc = "Field `DMACSYNC1` writer - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled."]
pub type Dmacsync1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DMACSYNC2` reader - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled."]
pub type Dmacsync2R = crate::BitReader;
#[doc = "Field `DMACSYNC2` writer - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled."]
pub type Dmacsync2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DMACSYNC3` reader - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled."]
pub type Dmacsync3R = crate::BitReader;
#[doc = "Field `DMACSYNC3` writer - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled."]
pub type Dmacsync3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DMACSYNC4` reader - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled."]
pub type Dmacsync4R = crate::BitReader;
#[doc = "Field `DMACSYNC4` writer - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled."]
pub type Dmacsync4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DMACSYNC5` reader - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled."]
pub type Dmacsync5R = crate::BitReader;
#[doc = "Field `DMACSYNC5` writer - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled."]
pub type Dmacsync5W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DMACSYNC6` reader - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled."]
pub type Dmacsync6R = crate::BitReader;
#[doc = "Field `DMACSYNC6` writer - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled."]
pub type Dmacsync6W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DMACSYNC7` reader - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled."]
pub type Dmacsync7R = crate::BitReader;
#[doc = "Field `DMACSYNC7` writer - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled."]
pub type Dmacsync7W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DMACSYNC8` reader - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled."]
pub type Dmacsync8R = crate::BitReader;
#[doc = "Field `DMACSYNC8` writer - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled."]
pub type Dmacsync8W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DMACSYNC9` reader - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled."]
pub type Dmacsync9R = crate::BitReader;
#[doc = "Field `DMACSYNC9` writer - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled."]
pub type Dmacsync9W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DMACSYNC10` reader - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled."]
pub type Dmacsync10R = crate::BitReader;
#[doc = "Field `DMACSYNC10` writer - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled."]
pub type Dmacsync10W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DMACSYNC11` reader - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled."]
pub type Dmacsync11R = crate::BitReader;
#[doc = "Field `DMACSYNC11` writer - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled."]
pub type Dmacsync11W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DMACSYNC12` reader - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled."]
pub type Dmacsync12R = crate::BitReader;
#[doc = "Field `DMACSYNC12` writer - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled."]
pub type Dmacsync12W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DMACSYNC13` reader - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled."]
pub type Dmacsync13R = crate::BitReader;
#[doc = "Field `DMACSYNC13` writer - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled."]
pub type Dmacsync13W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DMACSYNC14` reader - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled."]
pub type Dmacsync14R = crate::BitReader;
#[doc = "Field `DMACSYNC14` writer - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled."]
pub type Dmacsync14W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DMACSYNC15` reader - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled."]
pub type Dmacsync15R = crate::BitReader;
#[doc = "Field `DMACSYNC15` writer - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled."]
pub type Dmacsync15W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
    #[doc = "Bit 0 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled."]
    #[inline(always)]
    pub fn dmacsync0(&self) -> Dmacsync0R {
        Dmacsync0R::new((self.bits & 1) != 0)
    }
    #[doc = "Bit 1 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled."]
    #[inline(always)]
    pub fn dmacsync1(&self) -> Dmacsync1R {
        Dmacsync1R::new(((self.bits >> 1) & 1) != 0)
    }
    #[doc = "Bit 2 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled."]
    #[inline(always)]
    pub fn dmacsync2(&self) -> Dmacsync2R {
        Dmacsync2R::new(((self.bits >> 2) & 1) != 0)
    }
    #[doc = "Bit 3 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled."]
    #[inline(always)]
    pub fn dmacsync3(&self) -> Dmacsync3R {
        Dmacsync3R::new(((self.bits >> 3) & 1) != 0)
    }
    #[doc = "Bit 4 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled."]
    #[inline(always)]
    pub fn dmacsync4(&self) -> Dmacsync4R {
        Dmacsync4R::new(((self.bits >> 4) & 1) != 0)
    }
    #[doc = "Bit 5 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled."]
    #[inline(always)]
    pub fn dmacsync5(&self) -> Dmacsync5R {
        Dmacsync5R::new(((self.bits >> 5) & 1) != 0)
    }
    #[doc = "Bit 6 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled."]
    #[inline(always)]
    pub fn dmacsync6(&self) -> Dmacsync6R {
        Dmacsync6R::new(((self.bits >> 6) & 1) != 0)
    }
    #[doc = "Bit 7 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled."]
    #[inline(always)]
    pub fn dmacsync7(&self) -> Dmacsync7R {
        Dmacsync7R::new(((self.bits >> 7) & 1) != 0)
    }
    #[doc = "Bit 8 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled."]
    #[inline(always)]
    pub fn dmacsync8(&self) -> Dmacsync8R {
        Dmacsync8R::new(((self.bits >> 8) & 1) != 0)
    }
    #[doc = "Bit 9 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled."]
    #[inline(always)]
    pub fn dmacsync9(&self) -> Dmacsync9R {
        Dmacsync9R::new(((self.bits >> 9) & 1) != 0)
    }
    #[doc = "Bit 10 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled."]
    #[inline(always)]
    pub fn dmacsync10(&self) -> Dmacsync10R {
        Dmacsync10R::new(((self.bits >> 10) & 1) != 0)
    }
    #[doc = "Bit 11 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled."]
    #[inline(always)]
    pub fn dmacsync11(&self) -> Dmacsync11R {
        Dmacsync11R::new(((self.bits >> 11) & 1) != 0)
    }
    #[doc = "Bit 12 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled."]
    #[inline(always)]
    pub fn dmacsync12(&self) -> Dmacsync12R {
        Dmacsync12R::new(((self.bits >> 12) & 1) != 0)
    }
    #[doc = "Bit 13 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled."]
    #[inline(always)]
    pub fn dmacsync13(&self) -> Dmacsync13R {
        Dmacsync13R::new(((self.bits >> 13) & 1) != 0)
    }
    #[doc = "Bit 14 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled."]
    #[inline(always)]
    pub fn dmacsync14(&self) -> Dmacsync14R {
        Dmacsync14R::new(((self.bits >> 14) & 1) != 0)
    }
    #[doc = "Bit 15 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled."]
    #[inline(always)]
    pub fn dmacsync15(&self) -> Dmacsync15R {
        Dmacsync15R::new(((self.bits >> 15) & 1) != 0)
    }
}
impl W {
    #[doc = "Bit 0 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled."]
    #[inline(always)]
    pub fn dmacsync0(&mut self) -> Dmacsync0W<'_, SyncSpec> {
        Dmacsync0W::new(self, 0)
    }
    #[doc = "Bit 1 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled."]
    #[inline(always)]
    pub fn dmacsync1(&mut self) -> Dmacsync1W<'_, SyncSpec> {
        Dmacsync1W::new(self, 1)
    }
    #[doc = "Bit 2 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled."]
    #[inline(always)]
    pub fn dmacsync2(&mut self) -> Dmacsync2W<'_, SyncSpec> {
        Dmacsync2W::new(self, 2)
    }
    #[doc = "Bit 3 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled."]
    #[inline(always)]
    pub fn dmacsync3(&mut self) -> Dmacsync3W<'_, SyncSpec> {
        Dmacsync3W::new(self, 3)
    }
    #[doc = "Bit 4 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled."]
    #[inline(always)]
    pub fn dmacsync4(&mut self) -> Dmacsync4W<'_, SyncSpec> {
        Dmacsync4W::new(self, 4)
    }
    #[doc = "Bit 5 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled."]
    #[inline(always)]
    pub fn dmacsync5(&mut self) -> Dmacsync5W<'_, SyncSpec> {
        Dmacsync5W::new(self, 5)
    }
    #[doc = "Bit 6 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled."]
    #[inline(always)]
    pub fn dmacsync6(&mut self) -> Dmacsync6W<'_, SyncSpec> {
        Dmacsync6W::new(self, 6)
    }
    #[doc = "Bit 7 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled."]
    #[inline(always)]
    pub fn dmacsync7(&mut self) -> Dmacsync7W<'_, SyncSpec> {
        Dmacsync7W::new(self, 7)
    }
    #[doc = "Bit 8 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled."]
    #[inline(always)]
    pub fn dmacsync8(&mut self) -> Dmacsync8W<'_, SyncSpec> {
        Dmacsync8W::new(self, 8)
    }
    #[doc = "Bit 9 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled."]
    #[inline(always)]
    pub fn dmacsync9(&mut self) -> Dmacsync9W<'_, SyncSpec> {
        Dmacsync9W::new(self, 9)
    }
    #[doc = "Bit 10 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled."]
    #[inline(always)]
    pub fn dmacsync10(&mut self) -> Dmacsync10W<'_, SyncSpec> {
        Dmacsync10W::new(self, 10)
    }
    #[doc = "Bit 11 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled."]
    #[inline(always)]
    pub fn dmacsync11(&mut self) -> Dmacsync11W<'_, SyncSpec> {
        Dmacsync11W::new(self, 11)
    }
    #[doc = "Bit 12 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled."]
    #[inline(always)]
    pub fn dmacsync12(&mut self) -> Dmacsync12W<'_, SyncSpec> {
        Dmacsync12W::new(self, 12)
    }
    #[doc = "Bit 13 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled."]
    #[inline(always)]
    pub fn dmacsync13(&mut self) -> Dmacsync13W<'_, SyncSpec> {
        Dmacsync13W::new(self, 13)
    }
    #[doc = "Bit 14 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled."]
    #[inline(always)]
    pub fn dmacsync14(&mut self) -> Dmacsync14W<'_, SyncSpec> {
        Dmacsync14W::new(self, 14)
    }
    #[doc = "Bit 15 - Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled."]
    #[inline(always)]
    pub fn dmacsync15(&mut self) -> Dmacsync15W<'_, SyncSpec> {
        Dmacsync15W::new(self, 15)
    }
}
#[doc = "DMA Synchronization Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sync::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sync::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SyncSpec;
impl crate::RegisterSpec for SyncSpec {
    type Ux = u32;
}
#[doc = "`read()` method returns [`sync::R`](R) reader structure"]
impl crate::Readable for SyncSpec {}
#[doc = "`write(|w| ..)` method takes [`sync::W`](W) writer structure"]
impl crate::Writable for SyncSpec {
    type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets SYNC to value 0"]
impl crate::Resettable for SyncSpec {}
