#[repr(C)]
#[doc = "Register block"]
pub struct RegisterBlock {
    conset: Conset,
    stat: Stat,
    dat: Dat,
    adr0: Adr0,
    sclh: Sclh,
    scll: Scll,
    conclr: Conclr,
    mmctrl: Mmctrl,
    adr: [Adr; 3],
    data_buffer: DataBuffer,
    mask: [Mask; 4],
}
impl RegisterBlock {
    #[doc = "0x00 - I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register."]
    #[inline(always)]
    pub const fn conset(&self) -> &Conset {
        &self.conset
    }
    #[doc = "0x04 - I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed."]
    #[inline(always)]
    pub const fn stat(&self) -> &Stat {
        &self.stat
    }
    #[doc = "0x08 - I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register."]
    #[inline(always)]
    pub const fn dat(&self) -> &Dat {
        &self.dat
    }
    #[doc = "0x0c - I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address."]
    #[inline(always)]
    pub const fn adr0(&self) -> &Adr0 {
        &self.adr0
    }
    #[doc = "0x10 - SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock."]
    #[inline(always)]
    pub const fn sclh(&self) -> &Sclh {
        &self.sclh
    }
    #[doc = "0x14 - SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. SCLL and SCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode."]
    #[inline(always)]
    pub const fn scll(&self) -> &Scll {
        &self.scll
    }
    #[doc = "0x18 - I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register."]
    #[inline(always)]
    pub const fn conclr(&self) -> &Conclr {
        &self.conclr
    }
    #[doc = "0x1c - Monitor mode control register."]
    #[inline(always)]
    pub const fn mmctrl(&self) -> &Mmctrl {
        &self.mmctrl
    }
    #[doc = "0x20..0x2c - I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address."]
    #[doc = ""]
    #[doc = "<div class=\"warning\">`n` is the index of register in the array. `n == 0` corresponds to `ADR1` register.</div>"]
    #[inline(always)]
    pub const fn adr(&self, n: usize) -> &Adr {
        &self.adr[n]
    }
    #[doc = "Iterator for array of:"]
    #[doc = "0x20..0x2c - I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address."]
    #[inline(always)]
    pub fn adr_iter(&self) -> impl Iterator<Item = &Adr> {
        self.adr.iter()
    }
    #[doc = "0x20 - I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address."]
    #[inline(always)]
    pub const fn adr1(&self) -> &Adr {
        self.adr(0)
    }
    #[doc = "0x24 - I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address."]
    #[inline(always)]
    pub const fn adr2(&self) -> &Adr {
        self.adr(1)
    }
    #[doc = "0x28 - I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address."]
    #[inline(always)]
    pub const fn adr3(&self) -> &Adr {
        self.adr(2)
    }
    #[doc = "0x2c - Data buffer register. The contents of the 8 MSBs of the DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus."]
    #[inline(always)]
    pub const fn data_buffer(&self) -> &DataBuffer {
        &self.data_buffer
    }
    #[doc = "0x30..0x40 - I2C Slave address mask register"]
    #[inline(always)]
    pub const fn mask(&self, n: usize) -> &Mask {
        &self.mask[n]
    }
    #[doc = "Iterator for array of:"]
    #[doc = "0x30..0x40 - I2C Slave address mask register"]
    #[inline(always)]
    pub fn mask_iter(&self) -> impl Iterator<Item = &Mask> {
        self.mask.iter()
    }
}
#[doc = "CONSET (rw) register accessor: I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register.\n\nYou can [`read`](crate::Reg::read) this register and get [`conset::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`conset::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@conset`] module"]
#[doc(alias = "CONSET")]
pub type Conset = crate::Reg<conset::ConsetSpec>;
#[doc = "I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register."]
pub mod conset;
#[doc = "STAT (r) register accessor: I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed.\n\nYou can [`read`](crate::Reg::read) this register and get [`stat::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stat`] module"]
#[doc(alias = "STAT")]
pub type Stat = crate::Reg<stat::StatSpec>;
#[doc = "I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed."]
pub mod stat;
#[doc = "DAT (rw) register accessor: I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register.\n\nYou can [`read`](crate::Reg::read) this register and get [`dat::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dat::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dat`] module"]
#[doc(alias = "DAT")]
pub type Dat = crate::Reg<dat::DatSpec>;
#[doc = "I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register."]
pub mod dat;
pub use Adr as Adr0;
pub use adr as adr0;
#[doc = "SCLH (rw) register accessor: SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock.\n\nYou can [`read`](crate::Reg::read) this register and get [`sclh::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sclh::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sclh`] module"]
#[doc(alias = "SCLH")]
pub type Sclh = crate::Reg<sclh::SclhSpec>;
#[doc = "SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock."]
pub mod sclh;
#[doc = "SCLL (rw) register accessor: SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. SCLL and SCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode.\n\nYou can [`read`](crate::Reg::read) this register and get [`scll::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scll::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scll`] module"]
#[doc(alias = "SCLL")]
pub type Scll = crate::Reg<scll::ScllSpec>;
#[doc = "SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. SCLL and SCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode."]
pub mod scll;
#[doc = "CONCLR (w) register accessor: I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register.\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`conclr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@conclr`] module"]
#[doc(alias = "CONCLR")]
pub type Conclr = crate::Reg<conclr::ConclrSpec>;
#[doc = "I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register."]
pub mod conclr;
#[doc = "MMCTRL (rw) register accessor: Monitor mode control register.\n\nYou can [`read`](crate::Reg::read) this register and get [`mmctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mmctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mmctrl`] module"]
#[doc(alias = "MMCTRL")]
pub type Mmctrl = crate::Reg<mmctrl::MmctrlSpec>;
#[doc = "Monitor mode control register."]
pub mod mmctrl;
#[doc = "ADR (rw) register accessor: I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address.\n\nYou can [`read`](crate::Reg::read) this register and get [`adr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adr`] module"]
#[doc(alias = "ADR")]
pub type Adr = crate::Reg<adr::AdrSpec>;
#[doc = "I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address."]
pub mod adr;
#[doc = "DATA_BUFFER (r) register accessor: Data buffer register. The contents of the 8 MSBs of the DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus.\n\nYou can [`read`](crate::Reg::read) this register and get [`data_buffer::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data_buffer`] module"]
#[doc(alias = "DATA_BUFFER")]
pub type DataBuffer = crate::Reg<data_buffer::DataBufferSpec>;
#[doc = "Data buffer register. The contents of the 8 MSBs of the DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus."]
pub mod data_buffer;
#[doc = "MASK (rw) register accessor: I2C Slave address mask register\n\nYou can [`read`](crate::Reg::read) this register and get [`mask::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mask::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mask`] module"]
#[doc(alias = "MASK")]
pub type Mask = crate::Reg<mask::MaskSpec>;
#[doc = "I2C Slave address mask register"]
pub mod mask;
