#[doc = "Register `CLR0` writer"]
pub type W = crate::W<Clr0Spec>;
#[doc = "Field `P0_0CI` writer - Clear GPIO port Interrupts for P0\\[0\\]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF."]
pub type P0_0ciW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P0_1CI` writer - Clear GPIO port Interrupts for P0\\[1\\]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF."]
pub type P0_1ciW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P0_2CI` writer - Clear GPIO port Interrupts for P0\\[2\\]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF."]
pub type P0_2ciW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P0_3CI` writer - Clear GPIO port Interrupts for P0\\[3\\]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF."]
pub type P0_3ciW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P0_4CI` writer - Clear GPIO port Interrupts for P0\\[4\\]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF."]
pub type P0_4ciW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P0_5CI` writer - Clear GPIO port Interrupts for P0\\[5\\]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF."]
pub type P0_5ciW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P0_6CI` writer - Clear GPIO port Interrupts for P0\\[6\\]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF."]
pub type P0_6ciW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P0_7CI` writer - Clear GPIO port Interrupts for P0\\[7\\]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF."]
pub type P0_7ciW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P0_8CI` writer - Clear GPIO port Interrupts for P0\\[8\\]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF."]
pub type P0_8ciW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P0_9CI` writer - Clear GPIO port Interrupts for P0\\[9\\]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF."]
pub type P0_9ciW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P0_10CI` writer - Clear GPIO port Interrupts for P0\\[10\\]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF."]
pub type P0_10ciW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P0_11CI` writer - Clear GPIO port Interrupts for P0\\[11\\]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF."]
pub type P0_11ciW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P0_12CI` writer - Clear GPIO port Interrupts for P0\\[12\\]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF."]
pub type P0_12ciW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P0_13CI` writer - Clear GPIO port Interrupts for P0\\[13\\]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF."]
pub type P0_13ciW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P0_14CI` writer - Clear GPIO port Interrupts for P0\\[14\\]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF."]
pub type P0_14ciW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P0_15CI` writer - Clear GPIO port Interrupts for P0\\[15\\]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF."]
pub type P0_15ciW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P0_16CI` writer - Clear GPIO port Interrupts for P0\\[16\\]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF."]
pub type P0_16ciW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P0_17CI` writer - Clear GPIO port Interrupts for P0\\[17\\]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF."]
pub type P0_17ciW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P0_18CI` writer - Clear GPIO port Interrupts for P0\\[18\\]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF."]
pub type P0_18ciW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P0_19CI` writer - Clear GPIO port Interrupts for P0\\[19\\]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF."]
pub type P0_19ciW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P0_20CI` writer - Clear GPIO port Interrupts for P0\\[20\\]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF."]
pub type P0_20ciW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P0_21CI` writer - Clear GPIO port Interrupts for P0\\[21\\]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF."]
pub type P0_21ciW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P0_22CI` writer - Clear GPIO port Interrupts for P0\\[22\\]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF."]
pub type P0_22ciW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P0_23CI` writer - Clear GPIO port Interrupts for P0\\[23\\]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF."]
pub type P0_23ciW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P0_24CI` writer - Clear GPIO port Interrupts for P0\\[24\\]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF."]
pub type P0_24ciW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P0_25CI` writer - Clear GPIO port Interrupts for P0\\[25\\]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF."]
pub type P0_25ciW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P0_26CI` writer - Clear GPIO port Interrupts for P0\\[26\\]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF."]
pub type P0_26ciW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P0_27CI` writer - Clear GPIO port Interrupts for P0\\[27\\]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF."]
pub type P0_27ciW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P0_28CI` writer - Clear GPIO port Interrupts for P0\\[28\\]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF."]
pub type P0_28ciW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P0_29CI` writer - Clear GPIO port Interrupts for P0\\[29\\]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF."]
pub type P0_29ciW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P0_30CI` writer - Clear GPIO port Interrupts for P0\\[30\\]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF."]
pub type P0_30ciW<'a, REG> = crate::BitWriter<'a, REG>;
impl W {
    #[doc = "Bit 0 - Clear GPIO port Interrupts for P0\\[0\\]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF."]
    #[inline(always)]
    pub fn p0_0ci(&mut self) -> P0_0ciW<'_, Clr0Spec> {
        P0_0ciW::new(self, 0)
    }
    #[doc = "Bit 1 - Clear GPIO port Interrupts for P0\\[1\\]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF."]
    #[inline(always)]
    pub fn p0_1ci(&mut self) -> P0_1ciW<'_, Clr0Spec> {
        P0_1ciW::new(self, 1)
    }
    #[doc = "Bit 2 - Clear GPIO port Interrupts for P0\\[2\\]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF."]
    #[inline(always)]
    pub fn p0_2ci(&mut self) -> P0_2ciW<'_, Clr0Spec> {
        P0_2ciW::new(self, 2)
    }
    #[doc = "Bit 3 - Clear GPIO port Interrupts for P0\\[3\\]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF."]
    #[inline(always)]
    pub fn p0_3ci(&mut self) -> P0_3ciW<'_, Clr0Spec> {
        P0_3ciW::new(self, 3)
    }
    #[doc = "Bit 4 - Clear GPIO port Interrupts for P0\\[4\\]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF."]
    #[inline(always)]
    pub fn p0_4ci(&mut self) -> P0_4ciW<'_, Clr0Spec> {
        P0_4ciW::new(self, 4)
    }
    #[doc = "Bit 5 - Clear GPIO port Interrupts for P0\\[5\\]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF."]
    #[inline(always)]
    pub fn p0_5ci(&mut self) -> P0_5ciW<'_, Clr0Spec> {
        P0_5ciW::new(self, 5)
    }
    #[doc = "Bit 6 - Clear GPIO port Interrupts for P0\\[6\\]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF."]
    #[inline(always)]
    pub fn p0_6ci(&mut self) -> P0_6ciW<'_, Clr0Spec> {
        P0_6ciW::new(self, 6)
    }
    #[doc = "Bit 7 - Clear GPIO port Interrupts for P0\\[7\\]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF."]
    #[inline(always)]
    pub fn p0_7ci(&mut self) -> P0_7ciW<'_, Clr0Spec> {
        P0_7ciW::new(self, 7)
    }
    #[doc = "Bit 8 - Clear GPIO port Interrupts for P0\\[8\\]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF."]
    #[inline(always)]
    pub fn p0_8ci(&mut self) -> P0_8ciW<'_, Clr0Spec> {
        P0_8ciW::new(self, 8)
    }
    #[doc = "Bit 9 - Clear GPIO port Interrupts for P0\\[9\\]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF."]
    #[inline(always)]
    pub fn p0_9ci(&mut self) -> P0_9ciW<'_, Clr0Spec> {
        P0_9ciW::new(self, 9)
    }
    #[doc = "Bit 10 - Clear GPIO port Interrupts for P0\\[10\\]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF."]
    #[inline(always)]
    pub fn p0_10ci(&mut self) -> P0_10ciW<'_, Clr0Spec> {
        P0_10ciW::new(self, 10)
    }
    #[doc = "Bit 11 - Clear GPIO port Interrupts for P0\\[11\\]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF."]
    #[inline(always)]
    pub fn p0_11ci(&mut self) -> P0_11ciW<'_, Clr0Spec> {
        P0_11ciW::new(self, 11)
    }
    #[doc = "Bit 12 - Clear GPIO port Interrupts for P0\\[12\\]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF."]
    #[inline(always)]
    pub fn p0_12ci(&mut self) -> P0_12ciW<'_, Clr0Spec> {
        P0_12ciW::new(self, 12)
    }
    #[doc = "Bit 13 - Clear GPIO port Interrupts for P0\\[13\\]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF."]
    #[inline(always)]
    pub fn p0_13ci(&mut self) -> P0_13ciW<'_, Clr0Spec> {
        P0_13ciW::new(self, 13)
    }
    #[doc = "Bit 14 - Clear GPIO port Interrupts for P0\\[14\\]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF."]
    #[inline(always)]
    pub fn p0_14ci(&mut self) -> P0_14ciW<'_, Clr0Spec> {
        P0_14ciW::new(self, 14)
    }
    #[doc = "Bit 15 - Clear GPIO port Interrupts for P0\\[15\\]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF."]
    #[inline(always)]
    pub fn p0_15ci(&mut self) -> P0_15ciW<'_, Clr0Spec> {
        P0_15ciW::new(self, 15)
    }
    #[doc = "Bit 16 - Clear GPIO port Interrupts for P0\\[16\\]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF."]
    #[inline(always)]
    pub fn p0_16ci(&mut self) -> P0_16ciW<'_, Clr0Spec> {
        P0_16ciW::new(self, 16)
    }
    #[doc = "Bit 17 - Clear GPIO port Interrupts for P0\\[17\\]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF."]
    #[inline(always)]
    pub fn p0_17ci(&mut self) -> P0_17ciW<'_, Clr0Spec> {
        P0_17ciW::new(self, 17)
    }
    #[doc = "Bit 18 - Clear GPIO port Interrupts for P0\\[18\\]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF."]
    #[inline(always)]
    pub fn p0_18ci(&mut self) -> P0_18ciW<'_, Clr0Spec> {
        P0_18ciW::new(self, 18)
    }
    #[doc = "Bit 19 - Clear GPIO port Interrupts for P0\\[19\\]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF."]
    #[inline(always)]
    pub fn p0_19ci(&mut self) -> P0_19ciW<'_, Clr0Spec> {
        P0_19ciW::new(self, 19)
    }
    #[doc = "Bit 20 - Clear GPIO port Interrupts for P0\\[20\\]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF."]
    #[inline(always)]
    pub fn p0_20ci(&mut self) -> P0_20ciW<'_, Clr0Spec> {
        P0_20ciW::new(self, 20)
    }
    #[doc = "Bit 21 - Clear GPIO port Interrupts for P0\\[21\\]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF."]
    #[inline(always)]
    pub fn p0_21ci(&mut self) -> P0_21ciW<'_, Clr0Spec> {
        P0_21ciW::new(self, 21)
    }
    #[doc = "Bit 22 - Clear GPIO port Interrupts for P0\\[22\\]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF."]
    #[inline(always)]
    pub fn p0_22ci(&mut self) -> P0_22ciW<'_, Clr0Spec> {
        P0_22ciW::new(self, 22)
    }
    #[doc = "Bit 23 - Clear GPIO port Interrupts for P0\\[23\\]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF."]
    #[inline(always)]
    pub fn p0_23ci(&mut self) -> P0_23ciW<'_, Clr0Spec> {
        P0_23ciW::new(self, 23)
    }
    #[doc = "Bit 24 - Clear GPIO port Interrupts for P0\\[24\\]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF."]
    #[inline(always)]
    pub fn p0_24ci(&mut self) -> P0_24ciW<'_, Clr0Spec> {
        P0_24ciW::new(self, 24)
    }
    #[doc = "Bit 25 - Clear GPIO port Interrupts for P0\\[25\\]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF."]
    #[inline(always)]
    pub fn p0_25ci(&mut self) -> P0_25ciW<'_, Clr0Spec> {
        P0_25ciW::new(self, 25)
    }
    #[doc = "Bit 26 - Clear GPIO port Interrupts for P0\\[26\\]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF."]
    #[inline(always)]
    pub fn p0_26ci(&mut self) -> P0_26ciW<'_, Clr0Spec> {
        P0_26ciW::new(self, 26)
    }
    #[doc = "Bit 27 - Clear GPIO port Interrupts for P0\\[27\\]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF."]
    #[inline(always)]
    pub fn p0_27ci(&mut self) -> P0_27ciW<'_, Clr0Spec> {
        P0_27ciW::new(self, 27)
    }
    #[doc = "Bit 28 - Clear GPIO port Interrupts for P0\\[28\\]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF."]
    #[inline(always)]
    pub fn p0_28ci(&mut self) -> P0_28ciW<'_, Clr0Spec> {
        P0_28ciW::new(self, 28)
    }
    #[doc = "Bit 29 - Clear GPIO port Interrupts for P0\\[29\\]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF."]
    #[inline(always)]
    pub fn p0_29ci(&mut self) -> P0_29ciW<'_, Clr0Spec> {
        P0_29ciW::new(self, 29)
    }
    #[doc = "Bit 30 - Clear GPIO port Interrupts for P0\\[30\\]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF."]
    #[inline(always)]
    pub fn p0_30ci(&mut self) -> P0_30ciW<'_, Clr0Spec> {
        P0_30ciW::new(self, 30)
    }
}
#[doc = "GPIO Interrupt Clear.\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clr0::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Clr0Spec;
impl crate::RegisterSpec for Clr0Spec {
    type Ux = u32;
}
#[doc = "`write(|w| ..)` method takes [`clr0::W`](W) writer structure"]
impl crate::Writable for Clr0Spec {
    type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets CLR0 to value 0"]
impl crate::Resettable for Clr0Spec {}
