#[doc = "Register `SCLL` reader"]
pub type R = crate::R<ScllSpec>;
#[doc = "Register `SCLL` writer"]
pub type W = crate::W<ScllSpec>;
#[doc = "Field `SCLL` reader - Count for SCL low time period selection."]
pub type ScllR = crate::FieldReader<u16>;
#[doc = "Field `SCLL` writer - Count for SCL low time period selection."]
pub type ScllW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
impl R {
    #[doc = "Bits 0:15 - Count for SCL low time period selection."]
    #[inline(always)]
    pub fn scll(&self) -> ScllR {
        ScllR::new((self.bits & 0xffff) as u16)
    }
}
impl W {
    #[doc = "Bits 0:15 - Count for SCL low time period selection."]
    #[inline(always)]
    pub fn scll(&mut self) -> ScllW<'_, ScllSpec> {
        ScllW::new(self, 0)
    }
}
#[doc = "SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. SCLL and SCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode.\n\nYou can [`read`](crate::Reg::read) this register and get [`scll::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scll::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ScllSpec;
impl crate::RegisterSpec for ScllSpec {
    type Ux = u32;
}
#[doc = "`read()` method returns [`scll::R`](R) reader structure"]
impl crate::Readable for ScllSpec {}
#[doc = "`write(|w| ..)` method takes [`scll::W`](W) writer structure"]
impl crate::Writable for ScllSpec {
    type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets SCLL to value 0x04"]
impl crate::Resettable for ScllSpec {
    const RESET_VALUE: u32 = 0x04;
}
