import "noc_router.mirr" as router_mod;

module noc_test_wrapper {
    signals {
        clk: in bool;
        rst_n: in bool;

        // TX ports for test input
        port_tx_valid_0: in bool;  port_tx_data_0: in u64;
        port_tx_valid_1: in bool;  port_tx_data_1: in u64;
        port_tx_valid_2: in bool;  port_tx_data_2: in u64;
        port_tx_valid_3: in bool;  port_tx_data_3: in u64;
        port_tx_valid_4: in bool;  port_tx_data_4: in u64;
        port_tx_valid_5: in bool;  port_tx_data_5: in u64;
        port_tx_valid_6: in bool;  port_tx_data_6: in u64;
        port_tx_valid_7: in bool;  port_tx_data_7: in u64;
        port_tx_valid_8: in bool;  port_tx_data_8: in u64;
        port_tx_valid_9: in bool;  port_tx_data_9: in u64;
        port_tx_valid_10: in bool; port_tx_data_10: in u64;
        port_tx_valid_11: in bool; port_tx_data_11: in u64;
        port_tx_valid_12: in bool; port_tx_data_12: in u64;
        port_tx_valid_13: in bool; port_tx_data_13: in u64;
        port_tx_valid_14: in bool; port_tx_data_14: in u64;

        // RX ports for test output
        port_rx_valid_0: out bool; port_rx_data_0: out u64;
        port_rx_valid_1: out bool; port_rx_data_1: out u64;
        port_rx_valid_2: out bool; port_rx_data_2: out u64;
        port_rx_valid_3: out bool; port_rx_data_3: out u64;
        port_rx_valid_4: out bool; port_rx_data_4: out u64;
        port_rx_valid_5: out bool; port_rx_data_5: out u64;
        port_rx_valid_6: out bool; port_rx_data_6: out u64;
        port_rx_valid_7: out bool; port_rx_data_7: out u64;
        port_rx_valid_8: out bool; port_rx_data_8: out u64;
        port_rx_valid_9: out bool; port_rx_data_9: out u64;
        port_rx_valid_10: out bool; port_rx_data_10: out u64;
        port_rx_valid_11: out bool; port_rx_data_11: out u64;
        port_rx_valid_12: out bool; port_rx_data_12: out u64;
        port_rx_valid_13: out bool; port_rx_data_13: out u64;
        port_rx_valid_14: out bool; port_rx_data_14: out u64;
    }

    router_mod::noc_router(
        clk, rst_n,
        port_tx_valid_0, port_tx_data_0,
        port_tx_valid_1, port_tx_data_1,
        port_tx_valid_2, port_tx_data_2,
        port_tx_valid_3, port_tx_data_3,
        port_tx_valid_4, port_tx_data_4,
        port_tx_valid_5, port_tx_data_5,
        port_tx_valid_6, port_tx_data_6,
        port_tx_valid_7, port_tx_data_7,
        port_tx_valid_8, port_tx_data_8,
        port_tx_valid_9, port_tx_data_9,
        port_tx_valid_10, port_tx_data_10,
        port_tx_valid_11, port_tx_data_11,
        port_tx_valid_12, port_tx_data_12,
        port_tx_valid_13, port_tx_data_13,
        port_tx_valid_14, port_tx_data_14,
        port_rx_valid_0, port_rx_data_0,
        port_rx_valid_1, port_rx_data_1,
        port_rx_valid_2, port_rx_data_2,
        port_rx_valid_3, port_rx_data_3,
        port_rx_valid_4, port_rx_data_4,
        port_rx_valid_5, port_rx_data_5,
        port_rx_valid_6, port_rx_data_6,
        port_rx_valid_7, port_rx_data_7,
        port_rx_valid_8, port_rx_data_8,
        port_rx_valid_9, port_rx_data_9,
        port_rx_valid_10, port_rx_data_10,
        port_rx_valid_11, port_rx_data_11,
        port_rx_valid_12, port_rx_data_12,
        port_rx_valid_13, port_rx_data_13,
        port_rx_valid_14, port_rx_data_14
    );
}
