use super::*;

// Section 1: Module Header Tests
// ===========================================================================

#[test]
fn header_contains_auto_generated_comment() {
    let result = run_pipeline(MINIMAL_MODULE, &default_config()).unwrap();
    let sv = verilog::emit_sv(&result);

    assert!(
        sv.contains("Auto-generated by MIRR compiler"),
        "header must contain auto-generated comment"
    );
}

#[test]
fn header_contains_phase6_marker() {
    let result = run_pipeline(MINIMAL_MODULE, &default_config()).unwrap();
    let sv = verilog::emit_sv(&result);

    assert!(sv.contains("Phase 6"), "header must reference Phase 6");
}

#[test]
fn header_contains_do_not_edit_warning() {
    let result = run_pipeline(MINIMAL_MODULE, &default_config()).unwrap();
    let sv = verilog::emit_sv(&result);

    assert!(sv.contains("Do not edit"), "header must contain 'Do not edit' warning");
}

#[test]
fn header_contains_target_sv() {
    let result = run_pipeline(MINIMAL_MODULE, &default_config()).unwrap();
    let sv = verilog::emit_sv(&result);

    assert!(sv.contains("Target: SystemVerilog"), "header must specify SystemVerilog target");
}

#[test]
fn output_ends_with_endmodule() {
    let result = run_pipeline(MINIMAL_MODULE, &default_config()).unwrap();
    let sv = verilog::emit_sv(&result);

    assert!(sv.trim_end().ends_with("endmodule"), "output must end with endmodule");
}

// ===========================================================================
