//! Phase 8a: R-SPU Generic RAM
//!
//! Synchronous Block RAM (BRAM) interface for 64-bit words.
//!
//! Implementation: ram.sv

def ram(
    clk: signal in bool,
    addr: signal in u16,
    data_in: signal in u64,
    data_out: signal out u64
) {
    reflect {
        // Dummy signal to satisfy compiler (logic moved to ram.sv)
        signal _interface_active: internal bool;
    }
}

module ram {}
