//! Phase 3: ALU and Dispatcher Integration (16-Core Liquid Architecture)
//!
//! Top-level assembly for the RS-16 chip.
//! Integrates 16 R-SPU cores via a high-throughput NoC Interconnect.

import "interconnect/noc_router.mirr" as fabric;
import "core/core_top.mirr" as core;

module rspu_top {
    signal clk: in bool;
    signal rst_n: in bool;

    // --- Core Signals ---
    for i in 0..16 {
        signal instr[i]: internal u32;
        signal pc[i]: internal u32;
        signal core_data[i]: internal u64;
        signal rx_valid[i]: internal bool;
        signal rx_data[i]: internal u64;
        signal tx_valid[i]: internal bool;
        signal tx_data[i]: internal u64;

        // Physical Outputs to prevent Dead Code Elimination (DCE)
        signal out_pc[i]: out u32;
        signal out_data[i]: out u64;
    }

    signal global_trap: out bool;

    // --- 16-Core Integration ---
    for i in 0..16 {
        core::core_top(clk, rst_n, instr[i], pc[i], core_data[i], rx_valid[i], rx_data[i], tx_valid[i], tx_data[i]);
    }

    // --- NoC Interconnect ---
    fabric::noc_router(clk, rst_n, 
        tx_valid_0, tx_data_0, tx_valid_1, tx_data_1, tx_valid_2, tx_data_2, tx_valid_3, tx_data_3,
        tx_valid_4, tx_data_4, tx_valid_5, tx_data_5, tx_valid_6, tx_data_6, tx_valid_7, tx_data_7,
        tx_valid_8, tx_data_8, tx_valid_9, tx_data_9, tx_valid_10, tx_data_10, tx_valid_11, tx_data_11,
        tx_valid_12, tx_data_12, tx_valid_13, tx_data_13, tx_valid_14, tx_data_14, tx_valid_15, tx_data_15,
        rx_valid_0, rx_data_0, rx_valid_1, rx_data_1, rx_valid_2, rx_data_2, rx_valid_3, rx_data_3,
        rx_valid_4, rx_data_4, rx_valid_5, rx_data_5, rx_valid_6, rx_data_6, rx_valid_7, rx_data_7,
        rx_valid_8, rx_data_8, rx_valid_9, rx_data_9, rx_valid_10, rx_data_10, rx_valid_11, rx_data_11,
        rx_valid_12, rx_data_12, rx_valid_13, rx_data_13, rx_valid_14, rx_data_14, rx_valid_15, rx_data_15
    );

    // --- Monitoring & Diagnostics (DCE Protection) ---
    reflex collect_diagnostics {
        on always {
            for i in 0..16 {
                // DRIVE INSTR TO PREVENT DCE
                instr[i] = 16777216 + (i * 4096); 
                out_pc[i] = pc[i];
                // DRIVE OUTPUT WITH CORE DATA TO KEEP ALU ALIVE
                out_data[i] = core_data[i];
            }
            // Aggregated trap signal
            global_trap = tx_valid_0 || tx_valid_1 || tx_valid_2 || tx_valid_3 || tx_valid_4 || tx_valid_5 || tx_valid_6 || tx_valid_7 || tx_valid_8 || tx_valid_9 || tx_valid_10 || tx_valid_11 || tx_valid_12 || tx_valid_13 || tx_valid_14 || tx_valid_15;
        }
    }
}
