// Auto-generated by MIRR compiler (Phase 6)
// Do not edit — regenerate from .mirr source.
// Target: SystemVerilog (.sv)

module fir_filter (
  input  logic        clk,
  input  logic        rst_n,
  input  logic [15:0] coeff_0,
  input  logic [15:0] coeff_1,
  input  logic [15:0] coeff_2,
  input  logic [15:0] coeff_3,
  input  logic [15:0] sample_in,
  input  logic        sample_valid,
  output logic [31:0] filter_out
);

  // Internal signals
  logic [31:0] tap_0;

  // ── Temporal Guards ──

  // Guard: new_sample — when sample_valid (high) for 1 cycle (combinational)
  logic new_sample_cond;
  assign new_sample_cond = sample_valid;
  assign new_sample_out = new_sample_cond;

  // ── Reflex Assignments ──

  logic new_sample_out;

  // Reflex: compute_tap0
  always_comb begin
    tap_0 = '0;
    if (new_sample_out) tap_0 = (sample_in * coeff_0);
  end

  // Reflex: output_sum
  always_comb begin
    filter_out = '0;
    if (new_sample_out) filter_out = tap_0;
  end

  // ── Safety Properties (SVA) ──

  // property: output_bounded
  assert property (@(posedge clk)
    (filter_out < 4294967295));

endmodule
