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Description: MIRR: A hardware rule language for safety-critical systems. Compile temporal specs into synthesizable hardware logic.

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# MIRR

A hardware rule language for safety-critical systems.

Write a rule in plain code. Get nanosecond-speed hardware logic — no OS, no scheduler, no delays.

Compiler operational 10 emit targets v0.3.0

## The Three Primitives

MIRR programs are built from exactly three constructs. Every safety rule you write uses only these:

### `signal` — The Wire

A named data path carrying a typed value every clock cycle. Signals are the inputs and outputs of your safety logic.

### `guard` — The Watcher

A temporal condition that monitors signals over time. Guards count consecutive cycles a condition holds before triggering.

### `reflex` — The Responder

An action that fires when a guard triggers. Reflexes are the only way to drive output signals in hardware.

The compiler turns your rules into synthesizable Verilog RTL that enforces them in hardware, with nanosecond response times.

## Quick Example

    module neonatal_respirator {
        signals {
            airway_pressure: in u16
            clamp_valve:     out bool
        }

        guard sustained_pressure_drop {
            when airway_pressure < 50
            for  1000 cycles;
        }

        reflex emergency_clamp {
            on sustained_pressure_drop {
                clamp_valve = true;
            }
        }
    }

If `airway_pressure` stays below 50 for 1000 consecutive clock cycles, `clamp_valve` is set to `true` -- enforced directly in hardware.

## Documentation

Document | Description
--- | ---
Tutorial | 10-lesson beginner guide -- no hardware experience needed
Error Codes | Complete catalogue of compiler diagnostics
Type System | Signed/unsigned types, width inference, and error codes
R-SPU Reference | R-SPU instruction set architecture and register file
Migration Guide | Upgrade notes for 0.1.0 through 0.3.0
Roadmap | Phase 0-10 project roadmap
Glossary | Project terminology and acronyms
Contributing | Coding standards, workflow, error allocation
FPGA Targets Guide | FPGA toolchain, synthesis, and target configuration
MAPE-K Guide | Autonomic feedback loop simulator and LTL monitoring
S-Expression Guide | Homoiconic S-expression IR, round-trip invariant
Documentation Index | Canonical index for all project docs

## Getting Started

    # Clone and build
    git clone https://github.com/brandonfromph/mirr-project.git
    cd mirr-project
    cargo build

    # Compile an example
    cargo run --bin mirr-compile -- --emit verilog examples/neonatal_respirator.mirr

> Tip: MIRR requires no hardware experience. Start with the Tutorial for a step-by-step introduction to signals, guards, and reflexes.

## License

Distributed under the GPL-3.0 License. See LICENSE for details.