//! Phase 8a: R-SPU Register File
//!
//! High-performance synchronous register file interface.
//! Implements 256 tagged-word registers (64-bit each).
//! Supports two read ports and one write port.
//!
//! Implementation: regfile.sv (BRAM inferred)

def regfile(
    clk: signal in bool,
    rs1: signal in u8,
    rs2: signal in u8,
    rd:  signal in u8,
    we:  signal in bool,
    din: signal in u64,
    dout1: signal out u64,
    dout2: signal out u64
) {
    reflect {
        // Dummy signal to satisfy compiler (logic moved to regfile.sv)
        signal _interface_active: internal bool;
    }
}

module regfile {}
