// Auto-generated by MIRR compiler (Phase 6)
// Do not edit — regenerate from .mirr source.
// Target: SystemVerilog (.sv)

module crossbar (
  input  logic        rst_n,
  input  logic        clk,
  input  logic [15:0] addr_0,
  input  logic [15:0] data_in_0,
  output logic [15:0] data_out_0,
  input  logic [15:0] addr_1,
  input  logic [15:0] data_in_1,
  output logic [15:0] data_out_1,
  input  logic [15:0] addr_2,
  input  logic [15:0] data_in_2,
  output logic [15:0] data_out_2,
  input  logic [15:0] addr_3,
  input  logic [15:0] data_in_3,
  output logic [15:0] data_out_3,
  input  logic [15:0] addr_4,
  input  logic [15:0] data_in_4,
  output logic [15:0] data_out_4,
  input  logic [15:0] addr_5,
  input  logic [15:0] data_in_5,
  output logic [15:0] data_out_5,
  input  logic [15:0] addr_6,
  input  logic [15:0] data_in_6,
  output logic [15:0] data_out_6,
  input  logic [15:0] addr_7,
  input  logic [15:0] data_in_7,
  output logic [15:0] data_out_7,
  input  logic [15:0] addr_8,
  input  logic [15:0] data_in_8,
  output logic [15:0] data_out_8,
  input  logic [15:0] addr_9,
  input  logic [15:0] data_in_9,
  output logic [15:0] data_out_9,
  input  logic [15:0] addr_10,
  input  logic [15:0] data_in_10,
  output logic [15:0] data_out_10,
  input  logic [15:0] addr_11,
  input  logic [15:0] data_in_11,
  output logic [15:0] data_out_11,
  input  logic [15:0] addr_12,
  input  logic [15:0] data_in_12,
  output logic [15:0] data_out_12,
  input  logic [15:0] addr_13,
  input  logic [15:0] data_in_13,
  output logic [15:0] data_out_13,
  input  logic [15:0] addr_14,
  input  logic [15:0] data_in_14,
  output logic [15:0] data_out_14,
  input  logic [15:0] addr_15,
  input  logic [15:0] data_in_15,
  output logic [15:0] data_out_15
);

  // ── Temporal Guards ──

  // Guard: always_on — when clk (high) for 1 cycle (combinational)
  logic always_on_cond;
  assign always_on_cond = clk;
  assign always_on_out = always_on_cond;

  // ── Reflex Assignments ──

  logic always_on_out;

  // Reflex: route
  always_comb begin
    data_out_0 = '0;
    data_out_1 = '0;
    data_out_2 = '0;
    data_out_3 = '0;
    data_out_4 = '0;
    data_out_5 = '0;
    data_out_6 = '0;
    data_out_7 = '0;
    data_out_8 = '0;
    data_out_9 = '0;
    data_out_10 = '0;
    data_out_11 = '0;
    data_out_12 = '0;
    data_out_13 = '0;
    data_out_14 = '0;
    data_out_15 = '0;
    if (always_on_out) data_out_0 = data_in_0;
    if (always_on_out) data_out_1 = data_in_1;
    if (always_on_out) data_out_2 = data_in_2;
    if (always_on_out) data_out_3 = data_in_3;
    if (always_on_out) data_out_4 = data_in_4;
    if (always_on_out) data_out_5 = data_in_5;
    if (always_on_out) data_out_6 = data_in_6;
    if (always_on_out) data_out_7 = data_in_7;
    if (always_on_out) data_out_8 = data_in_8;
    if (always_on_out) data_out_9 = data_in_9;
    if (always_on_out) data_out_10 = data_in_10;
    if (always_on_out) data_out_11 = data_in_11;
    if (always_on_out) data_out_12 = data_in_12;
    if (always_on_out) data_out_13 = data_in_13;
    if (always_on_out) data_out_14 = data_in_14;
    if (always_on_out) data_out_15 = data_in_15;
  end

endmodule
