*Source: <https://everything.explained.today/DisplayID/>*

**DisplayID** is a [VESA](https://everything.explained.today/VESA/ "Video Electronics Standards Association is an American technical standards organization for computer display standard s.") standard for [metadata](https://everything.explained.today/metadata/ "Metadata is \" data that provides information about other data\", but not the content of the data itself, such as the text of ...") describing [display device](https://everything.explained.today/display_device/ "A display device is an output device for presentation of information in visual or tactile form.") capabilities to the video source. It is designed to replace [E-EDID](https://everything.explained.today/Extended_display_identification_data/ "Extended Display Identification Data is defined by a standard published by the Video Electronics Standards Association.") standard and EDID structure v1.4.

The DisplayID standard was initially released in December 2007.
Version 1.1 was released in March 2009 and was followed by version 1.2
released in August 2011. Version 1.3 was released in June 2013[[1]](#Ref-1) and current version 2.0 was released in September 2017.

DisplayID uses variable-length structures of up to 256 bytes each, which encompass all existing [EDID](https://everything.explained.today/EDID/ "Extended Display Identification Data is defined by a standard published by the Video Electronics Standards Association.") extensions as well as new extensions for [3D displays](https://everything.explained.today/3D_displays/ "A 3D display is a display device capable of conveying depth to the viewer."), embedded displays, Wide Color Gamut and [HDR](https://everything.explained.today/High_Dynamic_Range_(color_representation)/ "High-dynamic-range television is a technology that uses high dynamic range to improve the quality of display signals.") [EOTF](https://everything.explained.today/EOTF/). DisplayID format includes several blocks which describe logical parts of the display such as video [interfaces](https://everything.explained.today/Interface_(computing)/ "Interface is a shared boundary across which two or more separate components of a computer system exchange information."),
display device technology, timing details and manufacturer information.
Data blocks are identified with a unique tag. The length of each block
can be variable or fixed to a specific number of [bytes](https://everything.explained.today/bytes/ "The byte is a unit of digital information that most commonly consists of eight bit s.").
Only the base data block is mandatory, while all extension blocks are
optional. This variable structure is based on CEA EDID Extension Block
Version 3 first defined in CEA-861-B.

The DisplayID standard is [freely available](https://everything.explained.today/open_license/ "A free license is a license that allows copyrighted work to be reused, modified, and redistributed.") and is [royalty-free](https://everything.explained.today/royalty-free/) to implement.

## DisplayID 2.0 structures

Version 2.0 introduces new generalized information blocks primarily intended for UltraHD [High Dynamic Range](https://everything.explained.today/High_Dynamic_Range_(color_representation)/ "High-dynamic-range television is a technology that uses high dynamic range to improve the quality of display signals.") (HDR) displays, such as LCD computer monitors and LCD/OLED televisions with native support for [BT.2100](https://everything.explained.today/Rec._2100/ "Rec. 2100 is the same as Rec.") color space and [PQ](https://everything.explained.today/Perceptual_quantizer/ "The perceptual quantizer is a transfer function that allows for HDR display by replacing the gamma curve used in SDR.")/[HLG](https://everything.explained.today/Hybrid_log%e2%80%93gamma/ "The hybrid log–gamma is a transfer function jointly developed by the BBC and NHK for high dynamic range display.")
transfer functions. It also makes optional predefined CRT/LCD timings
from DMT and CEA-861 standards, switching to formula-based structures
which follow VESA CVT-RB and GTF.

The base DisplayID 2.0 variable-length structure is the same for all data blocks:

|  |  |  |
| --- | --- | --- |
| Value | Mandatory | Description |
| 0 | `0x20` |  | DisplayID Version 2, Revision 0 |
| 1 | 0–251 |  | Length of the variable data block |
| 2 | 0–15 |  | Display primary use case (reserved in the extension sections): `0` = Extension section – same use case as the Base section `1` = Test structure (generated by testing equipment) `2` = Generic `3` = Television  `4` = Productivity `5` = Gaming `6` = Presentation `7` = Virtual reality `8` = Augmented reality |
| 3 |  |  | Extension count (reserved in the extension sections) |
| 4 | Data blocks (N bytes) | | |
| (N+4) |  |  | Checksum |  |

Each
data block starts with mandatory block tag, revision number (0-7), and
payload length (0-248) bytes, and has a variable length of up to 251
bytes. The following blocks are currently defined:

|  |  |  |
| --- | --- | --- |
| Mandatory | Name | Notes |
| 0x00–0x1F |  | Reserved (legacy 1.0 data blocks) |  |
| 0x20 |  | Product Identification |  |
| 0x21 |  | Display Parameters | Per primary use case |
| 0x22 |  | Type VII – Detailed timing | Per primary use case |
| 0x23 |  | Type VIII – Enumerated Timing Code |  |
| 0x24 |  | Type IX – Formula-based Timing |  |
| 0x25 |  | Dynamic video timing range Limits |  |
| 0x26 |  | Display Interface Features | Per primary use case |
| 0x27 |  | Stereo Display Interface |  |
| 0x28 |  | Tiled Display Topology |  |
| 0x29 |  | ContainerID | For multi-function devices |
| 0x7E |  | Vendor specific |  |
| 0x81 |  | CTA DisplayID |  |  |

### 0x20 Product identification

`0x20` Product identification block contains standard vendor and product IDs, serial number, date of manufacture and product name.

Comparing to legacy block `0x00`, Microsoft ISA Plug&Play identifier is replaced with IEEE [OUI](https://everything.explained.today/Organizationally_unique_identifier/ "An organizationally unique identifier is a 24-bit number that uniquely identifies a vendor, manufacturer, or other organization."), first used in the network MAC address.

|  |  |
| --- | --- |
| Bit/value | Description/format |
| 0 | `0x20` | Product Identification block tag |
| 1 | `0` | Revision |
| 2 | 12–248 | Number of payload bytes |
| 3–5 |  | Manufacturer/Vendor ID  IEEE Organizationally Unique Identifier (OUI) |
| 6–7 |  | Product ID, LSB/MSB |
| 8–11 |  | Serial number, optional |
| 12 | 0–51, 255 | Week of Manufacture (`0`=unspecified); Model year tag (`255`) |
| 13 | 0, 15–255 | Year of Manufacture/Model Year (`0`=unspecified); Stored Value = (Year-2000) |
| 14 | 1–236 | Length of product name string |
| 15–251 |  | Product name string, optional |  |

### 0x21 Display parameters

`0x21` Display parameters block contains basic parameters
such as viewable area size and pixel count, supported color depth, and
factory calibrated RGB color space, white point, luminance, and gamma
transfer function.

Comparing to legacy block `0x01`, color calibration values have been moved here from block `0x02`
and max/min luminance values have been added. Display size can be
specified in 1 mm increments in addition to default 0.1 mm.

|  |  |
| --- | --- |
| Bit/value | Description/format |
| 0 | `0x21` | Display parameters block tag |
| 1 | Bits 2:0 = `0` | Revision |
| Bit 7 | Image size precision: `0` = 0.1 mm (default) `1` = 1 mm |
| 2 | `29` | Number of payload bytes |
| 3–4 |  | Horizontal image size |
| 5–6 |  | Vertical image size |
| 7–8 |  | Horizontal pixel count |
| 9–10 |  | Vertical pixel count |
| 11 | Feature-support flags | |
| Bits 2:0 | Scan orientation: `0` = Left–right, top–bottom (default) `1` = Right–left, top–bottom `2` = Top–bottom, right–left `3` = Bottom–top, right–left `4` = Right–left, bottom–top `5` = Left–right, bottom–top `6` = Bottom–top, left–right `7` = Top–bottom, left–right |
| Bits 4:3 | Max luminance information: `0` = non-zero values are a guaranteed minimum `1` = non-zero values are a guidance for the source device |
| Bit 6 | Color-space information: `0` = uses CIE 1931 (x,y) coordinates (default) `1` = uses CIE 1976 (u',v') coordinates |
| Bit 7 | Audio speakers information: `0` = integrated (default) `1` = external jack |
| 12–14 | Primary Color 1 Chromaticity | |
| Bits 7:0 | x/u' value, 8-bit LSB |
| Bits 11:8 | x/u' value, 4-bit MSB |
| Bits 15:12 | y/v' value, 4-bit LSB |
| Bits 23:16 | y/v' value, 8-bit MSB |
| 15–17 |  | Primary color 2 chromaticity |
| 18–20 |  | Primary color 3 chromaticity |
| 21–23 |  | White point chromaticity |
| 24–25 |  | Max luminance (full coverage), cd/m2 |
| 26–27 |  | Max luminance (10% coverage), cd/m2 |
| 28–29 |  | Min luminance, cd/m2 |
| 30 | Color-depth, display-technology flags | |
| Bits 2:0 | Color Depth: `0` = not defined `1` = 6 bpc `2` = 8 bpc `3` = 10 bpc `4` = 12 bpc `5` = 16 bpc |
| Bits 6:4 | Display technology: `0` = not specified `1` = AMLCD `2` = AMOLED |
| 31 |  | Gamma EOTF (1.00–3.54), stored value = (Gamma × 100) – 100 = (Gamma – 1) × 100 (`255`=unspecified) |
| Notes: Chromaticity values use 12-bit fractional integer numbers (bit12 × 2−1 + ... + bit0 × 2−12) Luminance values use 16-bit IEEE 754-2008 half-precision floating-point format (`−0` = not used) | | |  |

### 0x22 Type VII detailed timings

`0x22` Detailed timing block type VII defines CTA-861 compatible timings based on pixel rate. This block is based on type VI block `0x13`.

|  |  |
| --- | --- |
| Bit/value | Description/format |
| 0 | `0x22` | Detailed timing block tag |
| 1 | Bits 2:0 | Revision: `0`, `1` |
| Bit 2 | DSC support `0` = Standard descriptor `1` = Descriptors with DSC pass-through (block revision 1) |
| 2 | 20–240 | Number of payload bytes (N × 20, 1 ≤ N ≤ 12) |  |

|  |  |
| --- | --- |
| Bit/value | Description/format |
| 0–2 | Pixel Clock, kHz (0.001–16,777.216 MPix/s) | |
| Bits 7:0 | 8-bit LSB |
| Bits 15:8 | 8-bit middle bits |
| Bits 23:16 | 8-bit MSB |
| 3 | Timing options | |
| Bits 3:0 | Aspect ratio: `0` = 1:1 `1` = 5:4 `2` = 4:3 `3` = 15:9 `4` = 16:9 `5` = 16:10 `6` = 64:27 `7` = 256:135 `8` = Calculate using horizontal/vertical active image pixels/lines (bytes 4-5 and 12–13) |
| Bit 4 | Frame scanning type: `0` = progressive `1` = interlaced |
| Bits 6:5 | Stereoscopic 3D: `0` = mono timing `1` = 3D stereo timing `2` = mono or 3D stereo depending on user action |
| Bit 7 | Preferred timing: `1` = preferred detailed timing |
| 4–5 |  | Horizontal active image pixels |
| 6–7 |  | Horizontal blank pixels |
| 8–9 | Horizontal offset (front porch) | |
| Bits 7:0 | 8-bit LSB |
| Bits 14:8 | 7-bit MSB |
| Bit 15 | Horizontal sync polarity: `0` = negative `1` = positive |
| 10–11 |  | Horizontal sync width |
| 12–13 |  | Vertical active image lines |
| 14–15 |  | Vertical blank lines |
| 16–17 | Vertical sync offset (front porch) | |
| Bits 7:0 | 8-bit LSB |
| Bits 14:8 | 7-bit MSB |
| Bit 15 | Vertical sync polarity: `0` = negative `1` = positive |
| 18–19 |  | Vertical Sync Width |  |

### 0x23 Type VIII enumerated timing code

`0x23` Type VIII enumerated timing code block is based on type IV DMT ID block `0x06`.
It provides one-byte or two-byte video mode codes as defined in VESA
Display Monitor Timings standard or Video Information Codes defined by
CTA-861 and HDMI.

|  |  |
| --- | --- |
| Bit/value | Description/format |
| 0 | `0x23` | Enumerated timing code block tag |
| 1 | Bits 2:0 = `0` | Revision |
| Bit 3 | Timing code size: `0` = one-byte descriptor `1` = two-byte descriptor |
| Bits 7:6 | Timing code type: `0` = DMT `1` = CTA VIC code `2` = HDMI VIC code |
| 2 | 1–248 | Number of payload bytes |  |

### 0x24 Type IX formula-based timings

`0x24` Type IX formula-based timings block is based on type V short timings block `0x11`.

|  |  |
| --- | --- |
| Bit/value | Description/format |
| 0 | `0x24` | Formula-based timing block tag |
| 1 | Bits 2:0 = `0` | Revision |
| 2 | 6–248 | Number of payload bytes (N × 6) |  |

|  |  |
| --- | --- |
| Bit/value | Description/format |
| 0 | Timing options | |
| Bits 2:0 | Timing Formula/Algorithm `0` = CVT `1` = CVT-RB `2` = CVT-R2 |
| Bit 3 | NTSC Video optimized refresh rate × (1000/1001): `0` = not supported `1` = supported |
| Bits 6:5 | Stereoscopic 3D: `0` = Mono timing `1` = 3D stereo timing `2` = Mono or 3D stereo depending on user action |
| 1–2 |  | Horizontal active image pixels |
| 3–4 |  | Vertical active image lines |
| 5 |  | vertical refresh rate, Hz (1-256) |  |

### 0x25 Dynamic video timing range

`0x25` Dynamic video timing range block is based on block `0x9h`
Video Timing Range Limits; the new version allows more precise
definition of pixel rate in 1 kHz steps and adds indication for
variable refresh rates.

|  |  |
| --- | --- |
| Bit/value | Description/format |
| 0 | `0x25` | Dynamic video timing range block tag |
| 1 | Bits 2:0 | Revision: `0`, `1` |
| 2 | `9` | Number of payload bytes |
| 3–5 |  | Minimum pixel clock, kHz |
| 6–8 |  | Maximum pixel clock, kHz |
| 9 |  | Minimum vertical refresh rate, Hz |
| 10 |  | Maximum vertical refresh rate LSB, Hz |
| 11 | Dynamic video timing range Support Flags | |
| Bits 1:0 | Maximum vertical refresh rate MSB, Hz (block revision 1) |
| Bit 7 | Seamless dynamic video timing change: `0` = not supported `1` = supported with fixed horizontal pixel rate and dynamic vertical blanking |  |

### 0x26 Display interface features

`0x26` Display interface features block describes color
depth, dynamic range, and transfer function supported by the display
controller. It is based on blocks `0x0F` display interface features and `0x02` color characteristics.

|  |  |
| --- | --- |
| Bit/value | Description/format |
| 0 | `0x26` | Display interface features block tag |
| 1 | Bits 2:0 = `0` | Revision |
| 2 | `9` | Number of payload bytes |
| 3 | Color-depth support, RGB encoding | |
| Bit 0 | 6 bpc |
| Bit 1 | 8 bpc |
| Bit 2 | 10 bpc |
| Bit 3 | 12 bpc |
| Bit 4 | 14 bpc |
| Bit 5 | 16 bpc |
| `0` = no support `1` = supported | |
| 4 | Color-depth support, YCbCr 4:4:4 encoding | |
| 5 | Color-depth support, YCbCr 4:2:2 encoding | |
| Bit 0 | 8 bpc |
| Bit 1 | 10 bpc |
| Bit 2 | 12 bpc |
| Bit 3 | 14 bpc |
| Bit 4 | 16 bpc |
| `0` = no support `1` = supported | |
| 6 | Color-depth support, YCbCr 4:2:0 encoding | |
| 7 | Minimum pixel rate for YCbCr 4:2:0 encoding,  pixel rate = 74.25 MP/s × Stored Value (`0`=supported at all modes) | |
| 8 | Audio capability and feature support flags | |
| Bit 5 | 48 kHz sample rate |
| Bit 6 | 44.1 kHz sample rate |
| Bit 7 | 32 kHz sample rate |
| `0` = no support `1` = supported | |
| 9 | Color space and EOTF combination 1 | |
| Bit 0 | sRGB (IEC 61966-2-1) Color space and EOTF |
| Bit 1 | ITU-R BT.601 Color space and EOTF |
| Bit 2 | ITU-R BT.709 Color space and ITU-R BT.1886 EOTF |
| Bit 3 | Adobe RGB Color space and EOTF |
| Bit 4 | DCI-P3 (SMPTE RP 431–2) Color space and EOTF |
| Bit 5 | ITU-R BT.2020 Color space and EOTF |
| Bit 6 | ITU-R BT.2020 Color space and SMPTE ST 2084 EOTF |
| `0` = no support `1` = supported | |
| 10 | `0` | Color space and EOTF combination 2: reserved |
| 11 | 0–7 | Number of additional color space and EOTF bytes (N) |
| 11+#N | Additional color space and EOTF byte #N | |
| Bits 3:0 | EOTF: `0` = defined by display interface rules `1` = sRGB (IEC 61966-2-1) `2` = ITU-R BT.601 `3` = ITU-R BT.1886 for ITU-R BT.709 `4` = Adobe RGB  `5` = DCI-P3 (SMPTE RP 431–2)  `6` = ITU-R BT.2020 `7` = Gamma function (value stored in Display Parameters byte 31) `8` = SMPTE ST 2084 `9` = Hybrid log–gamma `10` = Custom (details defined in another block) |
| Bits 3:0 | Color space: `0` = Undefined – follow display interface rules `1` = sRGB (IEC 61966-2-1) `2` = ITU-R BT.601 `3` = ITU-R BT.709 `4` = Adobe RGB  `5` = DCI-P3 (SMPTE RP 431–2)  `6` = ITU-R BT.2020 `7` = Custom (details defined in another block) |  |

### 0x27 Stereo display interface

`0x27` Stereo display interface block is based on block `0x10`and describes stereoscopic 3D/VR modes (i.e. timings codes and stereo frame formats) supported by the display.

|  |  |
| --- | --- |
| Bit/value | Description/format |
| 0 | `0x27` | Stereo Display Interface block tag |
| 1 | Bits 2:0 | Revision: `0`, `1` |
| Bits 7:6 | Stereoscopic 3D Timing: `0` = `0b00` = block applies to all 3D timings `1` = `0b01` = block applies to 3D timings with specified Timing Code (block revision `1`) `2` = `0b10` = block applies to all timings in any timing block `3` = `0b11` = block applies to timings with specified Timing Code (block revision `1`) |
| 2 | (N+2) | Number of payload bytes |
| 3 | (N+1) | Number of bytes in Stereo Interface Method block |
| 4 |  | Stereo Interface Method code: `0` = Frame/Field Sequential (N=1) `1` = Side-by-Side (N=1) `2` = Pixel Interleaved (N=8) `3` = Dual Interface (N=1) `4` = Multi-view (N=2) `5` = Stacked Frame (N=1) `255` = Vendor defined (N=0) |
| 5 | Stereo Interface Method-specific Parameters (N bytes) | |
| 5+N | 3D Timings descriptor 1 | |
| Bits 4:0 | Timing Code number (M1, 1-31) |
| Bits 7:6 | Timing Code Type: `0` = DMT `1` = CTA VIC code `2` = HDMI VIC code |
| (6+N+#M1) | One-byte Timing Code #M1 | |
| (7+N+M1) | 3D Timings descriptor 2 | |
| (6+N+M1+#M2) | One-byte Timing Code #M2 | |
| Note: 3D Timings descriptors only exist when byte 1 bit 6 = `1` | | |  |

|  |  |
| --- | --- |
| Bit/value | Description/format |
| 1 | Method code: `0` = Frame/Field Sequential | |
| Bit 0 | Stereo Polarity: `0` = Stereo Sync on left eye image `1` = Stereo Sync on right eye image |
| 1 | `1` = Side-by-Side | |
| Bit 0 | View Identify: `0` = Left half represents left eye image `1` = Left half represents right eye image |
| 8 | `2` = Pixel Interleaved | |
| Bits 7:0 | Interleave pattern – 8x8 bit mask `0` = Pixel position for right eye image `1` = Pixel position for left eye image |
| 1 | `3` = Dual Interface | |
| Bit 0 | Interface Left and Right Polarity: `0` = Interface carries right eye image `1` = Interface carries left eye image |
| Bits 2:1 | Mirroring  `0` = No mirroring `1` = Left/Right are mirrored `1` = Top/Bottom are mirrored |
| 2 | `4` = Multi-view | |
|  | Number of Views |
|  | View Interleaving Method Code |
| 1 | `5` = Stacked Frame | |
| Bit 0 | View Identity: `0` = Top is left-eye image, bottom is right-eye image |  |

### 0x28 Tiled display topology

`0x28` Tiled display topology block describes displays
that consist of multiple physical display panels, each driven by a
separate video interface. It is based on block `0x12`.

|  |  |
| --- | --- |
| Bit/value | Description/format |
| 0 | `0x28` | Tiled Display Topology block tag |
| 1 | Bits 2:0 = `0` | Revision |
| 2 | `22` | Number of payload bytes |
| 3 | Tiled Display and Tile Capabilities | |
| Bits 2:0 | Tile Behavior when the only tile being transmitted: `0` = None of the following `1` = Display at Tile Location (byte 5) `2` = Scale to fit the display `3` = Clone to other tiles |
| Bits 4:3 | Tile Behavior when N tiles (1 < N < Max, N<>2) are being transmitted: `0` = None of the following `1` = Display at Tile Location (byte 5) |
| Bit 6 | Tile Bezel Descriptor: `0` = Not available `1` = Available at bytes 11-15 |
| Bit 7 | Physical Display Enclosure: `0` = Multiple physical enclosures `1` = Single physical enclosure |
| 4–6 | Tiled Display Topology and Tile Location | |
| 4 | Total Number of Tiles | |
| Bits 3:0 | Number of Vertical Tiles, 4-bit LSB |
| Bits 7:4 | Number of Horizontal Tiles, 4-bit LSB |
| 5 | Tile Location | |
| Bits 3:0 | Vertical Tile Location, 4-bit LSB |
| Bits 7:4 | Horizontal Tile Location, 4-bit LSB |
| 6 | Tile Location and Total Number of Tiles | |
| Bits 1:0 | Vertical Tile Location, 2-bit MSB |
| Bits 3:2 | Horizontal Tile Location, 2-bit MSB |
| Bits 5:4 | Number of Vertical Tiles, 2-bit MSB |
| Bits 7:6 | Number of Horizontal Tiles, 2-bit MSB |
| 7–10 | Tile Size | |
| Bits 7:0 | Horizontal Size, 8-bit LSB |
| Bits 15:8 | Horizontal Size, 8-bit MSB |
| Bits 23:16 | Vertical Size, 8-bit LSB |
| Bits 31:24 | Vertical Size, 8-bit MSB |
| 11–15 | Tile Pixel Multiplier and Tile Bezel-related Information | |
| 11 |  | Tile Pixel Multiplier |
| 12 |  | Tile Top Bezel Size |
| 13 |  | Tile Bottom Bezel Size |
| 14 |  | Tile Right Bezel Size |
| 15 |  | Tile Left Bezel Size |
| Note: Tile Bezel in pixels = (Tile Pixel Multiplier × Tile Bezel Size × 0.1) | | |
| 16–24 | Tiled Display Topology ID | |
| 16–18 |  | Tiled Display Manufacturer/Vendor ID  IEEE Organizationally Unique Identifier (OUI) |
| 19–20 |  | Tiled Display Product ID LSB/MSB |
| 21–24 |  | Serial number, optional |  |

### 0x29 Container ID

`0x29` Container ID block defines a unique identifier used
to associate additional devices that may be present in a
multifunctional display.

|  |  |
| --- | --- |
| Bit/value | Description/format |
| 0 | `0x29` | ContainerID block tag |
| 1 | Bits 2:0 = `0` | Revision |
| 2 | `16` | Number of payload bytes |
| 3–18 | Bits 128:0 | ContainerID  Universally Unique Identifier (UUID) |  |

### 0x7E Vendor-specific data

`0x7E` Vendor-specific data includes proprietary parameters which are not supported by DisplayID 2.0 structures.

|  |  |
| --- | --- |
| Bit/value | Description/format |
| 0 | `0x7E` | Vendor-specific block tag |
| 1 | Bits 2:0 | Revision |
| 2 | 3–248 | Number of payload bytes |
| 3–5 |  | Manufacturer/Vendor ID  IEEE Organizationally Unique Identifier (OUI) |
| 6–224 |  | Payload bytes |  |

|  |  |
| --- | --- |
| Bit/value | Description/format |
| 0 | `0x7E` | Vendor-specific block tag |
| 1 | Bits 2:0 = `1` | Revision |
| 2–4 | `0x3A0292` | VESA OUI |
| 5 | Bits 2:0 | Structure type: `0` = Embedded DisplayPort (eDP) `1` = External DisplayPort |
| Bit 7 | Default Color space and EOTF handling: `0` = interpret "RGB unspecified color space" as sRGB Color space and EOTF `1` = interpret as "native" color space, EOTF is specified in the Display Parameters block `0x21` |
| 6 | Bits 3:0 | Number of horizontal pixels overlapping an adjacent panel segment: `0-8` |
| Bits 6:5 | Multi-SST operation: `0` = `0b00` = not supported (Conventional Single-Stream Transport) `1` = `0b01` = two streams (two or four links) `2` = `0b10` = four streams (four links) |
| 7 | Bits 5:0 | Pass-through timing, integer target DSC bpp (bits per pixel) |
| 8 | Bits 3:0 | Pass-through timing, fractional target DSC bpp (bits per pixel) |  |

### 0x81 CTA DisplayID

`0x81` CTA DisplayID block provides information on CTA-861 EDID timings.

|  |  |
| --- | --- |
| Bit/value | Description/format |
| 0 | `0x81` | CTA DisplayID block tag |
| 1 | Bits 2:0 = `0` | Revision |
| 2 | 3–248 | Number of payload bytes |
| 3 | CTA Block 1 Tag Code and Block 1 Length | |
| Bits 4:0 | Block 1 Length (L1) |
| Bits 7:5 | Tag code (CTA-861-G) |
| 4-L1 | CTA Block 1 Descriptor #L1 | |
| (L1+2) |  | CTA Block 2 Tag Code and Block 2 Length |  |

## DisplayID 1.3 structures

Version 1.3 information blocks 0x10-0x1F borrow heavily from EDID 1.4
standard, which was designed for previous generation CRT/LCD/DLP/PDP
displays.

|  |  |  |
| --- | --- | --- |
| Value | Mandatory | Description |
| 0 | `0x12` |  | DisplayID Version 1, Revision 3 |
| 2 | 0–15 |  | Display Type Identifier: `0` = Extension section – same use case as the Base section `1` = Test structure (generated by testing equipment) `2` = Display panel `3` = Monitor `4` = Television `5` = Repeater `6` = Direct-drive monitor |  |

The following block types are defined:

|  |
| --- |
| Name |
| 0x00 | Product identification |
| 0x01 | Display parameters |
| 0x02 | Color characteristics |
| 0x03 | Type I timing – detailed |
| 0x04 | Type II timing – detailed |
| 0x05 | Type III timing – short |
| 0x06 | Type IV timing – DMT ID code |
| 0x07 | VESA timing standard |
| 0x08 | CEA Timing Standard |
| 0x09 | Video timing range |
| 0x0A | Product serial number |
| 0x0B | General-purpose ASCII string |
| 0x0C | Display device data |
| 0x0D | Interface power sequencing |
| 0x0E | Transfer characteristics |
| 0x0F | Display interface data |
| 0x10 | Stereo display interface |
| 0x11 | Type V timing – short |
| 0x13 | Type VI timing – detailed |
| 0x7F | Vendor specific |  |

Note: where indicated, only the difference from similar/superseding structures in Version 2.0 are shown in the sections below.

### 0x00 Product identification

`0x00` Product identification – superseded by `0x20`. The difference is:

|  |  |
| --- | --- |
| Bit/value | Description/format |
| 0 | `0x00` | Product identification block tag |
| 3–5 |  | Manufacturer/vendor ID  Microsoft ISA Plug&Play ID (PnPID) |  |

### 0x01 Display parameters

`0x01` Display parameters – superseded by `0x21`. The differences are:

|  |  |
| --- | --- |
| Bit/value | Description/format |
| 0 | `0x01` | Display parameters block tag |
| 11 | Feature-support flags | |
| Bit 0 | Deinterlacing |
| Bit 1 | Support\_AI in ACP/ISRC packets |
| Bit 2 | Single fixed pixel format only |
| Bit 3 | Single fixed timing only |
| Bit 4 | VESA display power management |
| Bit 5 | Audio input override |
| Bit 6 | Separate audio inputs |
| Bit 7 | Audio support |
| `0` = no support/no `1` = supported/yes | |
| 12 |  | Transfer characteristic gamma EOTF (1.00–3.54), stored value = (Gamma × 100) – 100 = (Gamma – 1) × 100 (`255`=unspecified) |
| 13 |  | Aspect ratio = long axis / short axis (1.00–3.55), stored value = (AR – 1) × 100 (78 for 16:9) |
| 14 | Color bit depth | |
| Bits 3:0 | Panel native dynamic range, stored value = bpc – 1 |
| Bits 7:4 | Display device overall dynamic range, stored value = bpc – 1 |  |

### 0x02 Color characteristics

`0x02` Color characteristics – superseded by `0x21` Display parameters.

|  |  |
| --- | --- |
| Bit/value | Description/format |
| 0 | `0x02` | Color characteristics block tag |
| 1 | Bits 2:0 = `1` | Revision |
| Bits 6:3 | Transfer characteristic block number  (block `0x0E`) |
| Bit 7 | Color space information: `0` = uses CIE 1931 (x,y) coordinates (default) `1` = uses CIE 1976 (u',v') coordinates |
| 2 | (Np + Nw) × 3 [+ 1 ] | Number of payload bytes; add 1 if Np=0 |
| 3 | Color characteristics information | |
| Bits 3:0 | Number of white points (Nw) |
| Bits 6:4 | Number of primaries (Np)  (`0`=Standard color space, additional Identifier byte is added to the block payload) |
| Bit 7 | Color mode: `0` = Spatial – separate subpixels for each primary color `1` = Temporal – field-sequential color (DLP) |
| 4–6 | Color primary or white point chromaticity | |
| Bits 7:0 | x/u' value, 8-bit LSB,  or  **Standard color space identifier** code if Np=0: `0` = sRGB (IEC 61966-2-1) `1` = ITU-R BT.601 `2` = ITU-R BT.709 `3` = Adobe RGB  `4` = DCI-P3 (SMPTE RP 431–2)  `5` = NTSC "SMPTE C" (SMPTE RP 145) `6` = PAL (ITU-R BT.470) `7` = Adobe Wide Gamut RGB `8` = DICOM (PS3.14 Grayscale standard display function) |
| Bits 11:8 | x/u' value, 4-bit MSB |
| Bits 15:12 | y/v' value, 4-bit LSB |
| Bits 23:16 | y/v' value, 8-bit MSB |
| Notes: Chromaticity values use 12-bit fractional integer numbers (bit12 × 2−1 + ... + bit0 × 2−12) | | |  |

### 0x03 Type I detailed timings

`0x03` Type I detailed timings – superseded by `0x22` type VII detailed timings. The differences are:

|  |  |
| --- | --- |
| Bit/value | Description/format |
| 0 | `0x03` | Detailed timing block tag |
| 1 | Bits 2:0 = `1` | Revision |  |

|  |  |
| --- | --- |
| Bit/value | Description/format |
| 0–2 | Pixel clock, 10 kHz steps (0.01–167,772.16 MPix/s) | |
| 3 | Timing options | |
| Bits 3:0 | Aspect ratio: `8` = Not defined |  |

### 0x04 Type II detailed timings

`0x04` Type II detailed timings block provides a
compressed structure with less precise pixel coordinates and reduced
blank intervals comparing to Type I:

|  |  |
| --- | --- |
| Bit/value | Description/format |
| 0 | `0x04` | Detailed timing block tag |
| 1 | Bits 2:0 = `0` | Revision |
| 2 | 11–242 | Number of payload bytes (N × 11, 1 ≤ N ≤ 22) |  |

|  |  |
| --- | --- |
| Bit/value | Description/format |
| 0–2 | Pixel clock, 10 kHz steps (0.01–167,772.16 MPix/s) | |
| 3 | Timing options | |
| Bit 2 | Vertical sync polarity: `0` = negative `1` = positive |
| Bit 3 | Horizontal sync polarity: `0` = negative `1` = positive |
| 4 |  | Horizontal active image pixels, 8-bit LSB |
| 5 | Bits 7:1 | Horizontal blank pixels |
| Bit 0 | Horizontal active image pixels, 1-bit MSB |
| 6 | Horizontal sync offset (front porch) and width | |
| Bits 3:0 | Sync offset (front porch) |
| Bits 7:4 | Sync width |
| 7 |  | Vertical active image lines, 8-bit LSB |
| 8 | Bits 4:0 | Vertical active image pixels, 4-bit MSB |
| 9 |  | Vertical blank lines |
| 10 | Vertical sync offset (front porch) and width | |
| Bits 3:0 | Sync offset (front porch) |
| Bits 7:4 | Sync width |
| Note: For all pixel dimensions, stored value = (Pixels / 8) – 1 | | |  |

### 0x05 Type III short timings

`0x05` Type III short timings block provides a very short compressed structure which uses formula-based CVT timings.

|  |  |
| --- | --- |
| Bit/value | Description/format |
| 0 | `0x05` | Short timing block tag |
| 1 | Bits 2:0 = `1` | Revision |
| 2 | 6–248 | Number of payload bytes (N × 3, 1 ≤ N ≤ 82) |  |

|  |  |
| --- | --- |
| Bit/value | Description/format |
| 0 | Timing options | |
| Bits 6:4 | Timing formula/algorithm `0` = CVT `1` = CVT-RB |
| Bits 3:0 | Aspect ratio |
| 1 |  | Horizontal active image pixels |
| 2 | Frame transfer type and rate | |
| Bit 7 | Frame transfer type: `0` = progressive `1` = field interlaced |
| Note: For all pixel dimensions, stored value = (Pixels / 8) – 1 | | |  |

### 0x06 Type IV short timings

`0x06` Type IV short timing (DMT ID code) block uses video
mode codes defined in VESA display monitor timings standard, as well as
video information codes defined by CTA-861 and HDMI. Superseded by `0x23` enumerated timing.

|  |  |
| --- | --- |
| Bit/value | Description/format |
| 0 | `0x06` | Type IV – Short timing (DMT ID code) block tag |
| 1 | Bits 2:0 = `1` | Revision |
| Bits 7:6 | Timing code type: `0` = DMT `1` = CTA VIC code `2` = HDMI VIC code |
| 2 | 1–248 | Number of payload bytes |  |

### 0x11 Type V short timings

`0x11` Type V short timings block is based on Type III
short timings block 0x05, but provides greater pixel precision and only
supports CVT-RB. Superseded by `0x24` Type IX formula-based timings.

|  |  |
| --- | --- |
| Bit/value | Description/format |
| 0 | `0x11` | Type V – Short timing block tag |
| 1 | Bits 2:0 = `0` | Revision |
| 2 | 6–248 | Number of payload bytes (N × 7, 1 ≤ N ≤ 35) |  |

|  |  |
| --- | --- |
| Bit/value | Description/format |
| 0 | Timing options | |
| Bits 1:0 | Timing formula/algorithm `0` = CVT-RB2 `1` = CVT-RB |
| Bit 4 | NTSC Video optimized refresh rate × (1000/1001): `0` = not supported `1` = supported |
| Bits 6:5 | Stereoscopic 3D: `0` = Mono timing `1` = 3D stereo timing `2` = Mono or 3D stereo depending on user action |
| Bit 7 | Preferred timing: `1` = preferred detailed timing |
| 1–2 |  | Horizontal active image pixels |
| 3–4 |  | Vertical active image lines |
| 5 |  | Vertical Refresh Rate, Hz (1–256) |  |

### 0x13 Type VI detailed timing

`0x13` Type VI Detailed timing block supports higher
precision pixel clock and high-resolution timings. This block is based
on Type I block 0x03, but allows greater timings precision using
1 kHz steps instead of 10 kHz. Superseded by `0x22` Type VII Detailed timings.

|  |  |
| --- | --- |
| Bit/value | Description/format |
| 0 | `0x13` | Type VI detailed timing block tag |
| 1 | Bits 2:0 = `0` | Revision |
| 2 |  | Number of payload bytes (N × 17 + M × 14) |  |

|  |  |
| --- | --- |
| Bit/value | Description/format |
| 0–2 | Pixel clock, kHz (0.001–4,194.303 MPix/s) | |
| Bits 7:0 | 8-bit LSB |
| Bits 15:8 | 8-bit middle bits |
| Bits 21:16 | 6-bit MSB |
| Bit 22 | Aspect and size information: `0` = not included `1` = included in bytes 14–16 |
| Bit 23 | Preferred timing: `0` = not a preferred detailed timing `1` = preferred detailed timing |
| 3–4 | Horizontal active image pixels & timing | |
| Bits 7:0 | Horizontal active image pixels, 8-bit LSB |
| Bits 14:8 | Horizontal active image pixels, 7-bit MSB |
| Bit 16 | Horizontal Sync Polarity: `0` = negative `1` = positive |
| 5–6 | Vertical active image lines & timing | |
| Bits 7:0 | Vertical active image lines, 8-bit LSB |
| Bits 14:8 | Vertical active image lines, 7-bit MSB |
| Bit 16 | Vertical Sync Polarity: `0` = negative `1` = positive |
| 7–9 | Horizontal blank pixels & front porch | |
| Bits 7:0 | Horizontal blank pixels, 8-bit LSB |
| Bits 15:8 | Horizontal offset (front porch), 8-bit LSB |
| Bits 19:16 | Horizontal blank pixels, 4-bit MSB |
| Bits 23:20 | Horizontal offset (front porch), 4-bit MSB |
| 10 |  | Horizontal Sync Width |
| 11 |  | Vertical Blank Lines |
| 12 |  | Vertical Sync offset (front porch) |
| 13 |  | Vertical Sync Width and Timing |
| Bits 3:0 | Vertical Sync Width |
| Bits 6:5 | Stereoscopic 3D: `0` = mono timing `1` = 3D stereo timing `2` = mono or 3D stereo depending on user action |
| Bit 7 | Frame scanning type: `0` = progressive `1` = interlaced |
| 14 |  | Aspect multiplier, aspect ratio = Aspect Multiplier × 3 / 256 |
| 15–16 | Vertical image base size and size multiplier | |
| Bits 7:0 | Vertical image base size, 8-bit LSB |
| Bits 11:8 | Vertical image base size, 4-bit MSB |
| Bits 15:12 | Size Multiplier |
| Vertical image size = Vertical image base size × Size Multiplier | | |  |

### 0x09 Video timing range limits

`0x09` Video timing range limits block describes displays capable of variable timings. Superseded by `0x25` Dynamic video timings range.

|  |  |
| --- | --- |
| Bit/value | Description/format |
| 0 | `0x09` | Video timing range limits block tag |
| 1 | Bits 2:0 = `0` | Revision |
| 2 | `9` | Number of payload bytes |
| 3–5 |  | Minimum pixel clock, 10 kHz steps |
| 6–8 |  | Maximum pixel clock, 10 kHz steps |
| 9 |  | Minimum Horizontal Frequency, kHz |
| 10 |  | Maximum Horizontal Frequency, kHz |
| 11–12 |  | Minimum Horizontal Blanking Pixels |
| 13 |  | Minimum Vertical Refresh Rate, Hz |
| 14 |  | Maximum Vertical Refresh Rate, Hz |
| 15–16 |  | Minimum Vertical Blanking Lines |
| 17 | Video timing support flags | |
| Bit 4 | Discrete frequency display |
| Bit 5 | VESA CVT |
| Bit 6 | VESA CVT-RB |
| Bit 7 | Interlaced |
| `0` = no support/no `1` = supported/yes | |  |

### 0x0C Display device data

`0x0C` Display device data block provides information
about display panel characteristics for embedded applications, such as
display technology, panel type, and pixel response times.

|  |  |
| --- | --- |
| Bit/value | Description/format |
| 0 | `0x0C` | Display device data block tag |
| 1 | Bits 2:0 = `0` | Revision |
| 2 | `13` | Number of payload bytes |
| 3 | Display device technology and sub-type codes | |
| Bits 7:0 | *CRT* `0`=`0x00` = Monochrome CRT `1`=`0x01` = Tricolor CRT `2`=`0x02` = Other CRT *LCD*  `16`=`0x10` = Passive matrix TN (HTN, STN) `17`=`0x11` = Passive matrix cholesteric LC `18`=`0x12` = Passive matrix ferroelectric LC `19`=`0x13` = Other passive matrix LC `20`=`0x14` = Active matrix TN `21`=`0x15` = Active matrix IPS `22`=`0x16` = Active matrix VA `22`=`0x16` = Active matrix OCB `22`=`0x16` = Active matrix ferroelectric `31`=`0x1F` = Other LC *Plasma display (PDP)*  `32`=`0x20` = DC plasma `33`=`0x21` = AC plasma *Other display technology* `48`=`0x30` = Electroluminescent (except OLED/OEL) `64`=`0x40` = Inorganic LED `80`=`0x50` = OLED/OEL `96`=`0x60` = FED/SED (cold-cathode, phosphor-based) `112`=`0x70` = Electrophoretic `128`=`0x80` = Electrochromic `144`=`0x90` = Electromechanic `160`=`0xA0` = Electrowetting `240`=`0xF0` = Other |
| Bits 7:4 | Display Technology, 4-bit MSB `0` = CRT `1` = LCD `2` = PDP `3` = ELD `4` = LED `5` = OLED/OEL `6` = FED/SED `7` = Ep `8` = Ec `9` = Em `10`=`0xA` = Ew `15`=`0xF` = Other |
| 4 | Display Device Operating Mode & Flags | |
| Bit 2 | Backlight can be switched off |
| Bit 3 | Backlight intensity can be controlled |
| `0` = no support/no `1` = supported/yes | |
| Bits 7:4 | Operating Mode code: `0` = Direct-view reflective, ambient lighting (no illumination) `1` = Direct-view reflective, illuminated, ambient lighting (no illumination) by default  `2` = Direct-view reflective, illuminated `3` = Direct-view transmissive, ambient lighting (no illumination) `4` = Direct-view transmissive, illuminated, ambient lighting (no illumination) by default `5` = Direct-view transmissive, illuminated `6` = Direct-view emissive `7` = Direct-view transflective, reflective (backlight off) by default `8` = Direct-view transflective, transmissive (backlight on) by default `9` = Transparent, viewable in ambient light `10` = Transparent emissive `11` = Projection, reflective light modulator (DLP/LCOS) `12` = Projection, transmissive light modulator (LCD projection) `13` = Projection, emissive image transducer (CRT projection) |
| 5–8 | Display Device Native Pixel Format | |
| 5–6 |  | Horizontal pixel count |
| 7–8 |  | Vertical pixel count |
| 9–10 | Aspect Ratio and Orientation | |
| 9 |  | Aspect Ratio = long axis / short axis (1.00–3.55), stored value = (AR – 1) × 100 (78 for 16:9) |
| 10 | Orientation | |
| Bits 1:0 | Scan direction: `0` = Not defined/no raster scan `1` = Line (fast scan) on long axis, frame/field (slow scan) on short axis `2` = Line (fast scan) on short axis, frame/field (slow scan) on long axis |
| Bits 3:2 | Zero pixel location: `0` = Upper left corner `1` = Upper right corner `2` = Lower left corner `3` = Lower right corner |
| Bits 5:4 | Rotation capability: `0` = No rotation `1` = Clockwise 90° `2` = Counter-clockwise 90° `2` = 90° in either direction |
| Bits 7:6 | Orientation: `0` = Landscape (horizontal long axis) `1` = Portrait (vertical long axis) `2` = Not fixed (can be rotated by user) |
| 11 |  | RGB Sub-pixel Information codes: `0` = Not defined `1` = RGB vertical stripes `2` = RGB horizontal stripes `3` = Vertical stripes, ordered as in Display Chromaticity block `4` = Horizontal stripes, ordered as in Display Chromaticity block `5` = RGGB 2x2 quad structure, red at top left, blue at bottom right `6` = RGGB 2x2 quad structure, red at bottom left, blue at top right `7` = Triad (delta) `8` = Mosaic (delta) `9` = RGBE/RGBW 2x2 quad structure, any order `10` = Five subpixels – RGB vertical and two colors above and below `11` = Six subpixels – RGB vertical and three colors in any order `11` = PenTile |
| 12 |  | Horizontal Pixel Pitch, in 0.01 mm steps (0.01% for projection) |
| 13 |  | Vertical Pixel pitch, in 0.01 mm steps (0.01% for projection) |
| 14 | Color Bit Depth | |
| Bits 3:0 | Panel native dynamic range, stored value = bpc – 1 |
| 15 | Response Time | |
| Bits 6:0 | Pixel response time, in ms (clamped to 0 and 126) |
| Bit 7 | Measurement method: `0` = Black to white (lower to higher) transition `1` = White to black (higher to lower) transition |  |

### 0x0F Display interface data

Display interface features block – superseded by `0x26` Display Interface Features.

|  |  |
| --- | --- |
| Bit/value | Description/format |
| 0 | `0x0F` | Display Interface Features block tag |
| 1 | Bits 2:0 = `0` | Revision |
| 2 | `10` | Number of payload bytes |
| 3 | Interface Type and Number of Links | |
| Bits 3:0 | Number of links (`1`, `2`, or `4`), or Analog sub-type (if bits 7:4 = `0`): `0` = 15HD/VGA (VESA EDDC Standard) `1` = VESA NAVI-V (15HD) `2` = VESA NAVI-D |
| Bits 7:4 | Display Interface Type: `0` = Analog `1` = LVDS (generic) `2` = TMDS (generic) `3` = RSDS (generic) `4` = DVI-D `5` = DVI-I, analog `6` = DVI-I, digital `7` = HDMI-A `8` = HDMI-B (dual link) `9` = MDDI `10` = DisplayPort `11` = Proprietary digital interface |
| 4 | Interface Standard Version and Revision | |
| Bits 3:0 | Interface revision |
| Bits 7:4 | Interface version |
| 5 | Color Depth Support, RGB encoding | |
| Bit 0 | 6 bpc |
| Bit 1 | 8 bpc |
| Bit 2 | 10 bpc |
| Bit 3 | 12 bpc |
| Bit 4 | 14 bpc |
| Bit 5 | 16 bpc |
| `0` = no support `1` = supported | |
| 6 | Color Depth Support, YCbCr 4:4:4 encoding | |
| 7 | Color Depth Support, YCbCr 4:2:2 encoding | |
| Bit 0 | 8 bpc |
| Bit 1 | 10 bpc |
| Bit 2 | 12 bpc |
| Bit 3 | 14 bpc |
| Bit 4 | 16 bpc |
| `0` = no support `1` = supported | |
| 8 | Content Protection support: `0` = No support `1` = HDCP `2` = DTCP `3` = DPCP | |
| 9 | Content Protection Standard Version and Revision | |
| Bits 3:0 | Standard revision |
| Bits 7:4 | Standard version |
| 10 | Spread Spectrum Information | |
| Bits 3:0 | Spread percentage, in 0.1% increments (range 0 to 1.5%) |
| Bits 7:6 | Spread type supported: `0` = No support `1` = Down spread `2` = Center spread |
| 11 | Interface type dependent attribute 1 | |
| Bit 0 | 3.3 V |
| Bit 1 | 5 V |
| Bit 2 | 12 V |
| Bit 3 | 2.8 V |
| `0` = no support `1` = supported | |
| Bit 4 | Color mapping: `0` = NS (Normal) mode `1` = 6-bit compatible mode |
| 12 | Interface type dependent attribute 2 | |
| Bit 0 | Shift clock data strobe: `0` = Falling edge `1` = Rising edge |
| Bit 1 | DE polarity: `0` = Active high (high signal level) `1` = Active low (low signal level) |
| Bit 2 | DE mode : `0` = DE (data enable) mode `1` = Fixed mode (VSync/HSync) |  |

### Additional blocks

Data blocks not described above are:

`0x0A` Serial number data block provides product serial number as an ASCII string.

`0x0B` General-purpose ASCII string block provides general purpose text strings that may be required by specific applications.

`0xD0` Interface power sequencing block defines display interface signal timings required for entering and exiting sleep mode.

`0x0E` Transfer characteristics block defines detailed
gamma curves according to VESA display transfer characteristic data
block (DTCDB) standard, as may be required by byte 1 in `0x02` color characteristics block.

`0x10` Stereo display interface block describes stereoscopic 3D/VR modes – superseded by `0x27` Ssereo display interface.

`0x12` Tiled display topology data block defines multi-panel displays – superseded by `0x28` tiled display topology.

`0x7F` Vendor specific block defines proprietary vendor data.

## 