/* SPDX-FileCopyrightText: © 2024-2025 Decompollaborate */
/* SPDX-License-Identifier: MIT */

mod common;

use common::{check_test_entries, TestEntry};

use rabbitizer::{
    display_flags::{DefaultLabelDisplay, InstructionDisplayFlags},
    instr::{Instruction, InstructionFlags},
    isa::IsaVersion,
    opcodes::Opcode,
    vram::Vram,
};

// TODO: test cases for MIPS_I and MIPS_II

#[test]
fn check_none_instructions_mips_1() {
    static ENTRIES: &[TestEntry] = &[
        TestEntry {
            instr: Instruction::new(
                0x08000419,
                Vram::new(0x80001100),
                InstructionFlags::new(IsaVersion::MIPS_I),
            ),
            imm_override: None,
            display_flags: InstructionDisplayFlags::default()
                .with_jump_default_label_display(DefaultLabelDisplay::FullExpression),
            valid: true,
            expected: "j           . + 4 + (0x419 << 2)",
            expected_opcode: Opcode::core_j,
            opcode_str: "j",
            operands_str: [Some(". + 4 + (0x419 << 2)"), None, None, None, None],
            test_encoder: true,
        },
        TestEntry {
            instr: Instruction::new(
                0x08000419,
                Vram::new(0x80001100),
                InstructionFlags::new(IsaVersion::MIPS_I),
            ),
            imm_override: None,
            display_flags: InstructionDisplayFlags::default()
                .with_jump_default_label_display(DefaultLabelDisplay::Computed),
            valid: true,
            expected: "j           . + 0x1068",
            expected_opcode: Opcode::core_j,
            opcode_str: "j",
            operands_str: [Some(". + 0x1068"), None, None, None, None],
            test_encoder: true,
        },
        TestEntry {
            instr: Instruction::new(
                0x08000419,
                Vram::new(0x80001100),
                InstructionFlags::new(IsaVersion::MIPS_I),
            ),
            imm_override: None,
            display_flags: InstructionDisplayFlags::default()
                .with_jump_default_label_display(DefaultLabelDisplay::Absolute),
            valid: true,
            expected: "j           func_80001064",
            expected_opcode: Opcode::core_j,
            opcode_str: "j",
            operands_str: [Some("func_80001064"), None, None, None, None],
            test_encoder: true,
        },
        TestEntry {
            instr: Instruction::new(
                0x1520FFFB,
                Vram::new(0x80000000),
                InstructionFlags::new(IsaVersion::MIPS_I),
            ),
            imm_override: None,
            display_flags: InstructionDisplayFlags::default()
                .with_branch_default_label_display(DefaultLabelDisplay::FullExpression),
            valid: true,
            expected: "bnez        $t1, . + 4 + (-0x5 << 2)",
            expected_opcode: Opcode::core_bnez,
            opcode_str: "bnez",
            operands_str: [Some("$t1"), Some(". + 4 + (-0x5 << 2)"), None, None, None],
            test_encoder: true,
        },
        TestEntry {
            instr: Instruction::new(
                0x1520FFFB,
                Vram::new(0x80000000),
                InstructionFlags::new(IsaVersion::MIPS_I),
            ),
            imm_override: None,
            display_flags: InstructionDisplayFlags::default()
                .with_branch_default_label_display(DefaultLabelDisplay::Computed),
            valid: true,
            expected: "bnez        $t1, . + -0x10",
            expected_opcode: Opcode::core_bnez,
            opcode_str: "bnez",
            operands_str: [Some("$t1"), Some(". + -0x10"), None, None, None],
            test_encoder: true,
        },
        TestEntry {
            instr: Instruction::new(
                0x1520FFFB,
                Vram::new(0x80000000),
                InstructionFlags::new(IsaVersion::MIPS_I),
            ),
            imm_override: None,
            display_flags: InstructionDisplayFlags::default()
                .with_branch_default_label_display(DefaultLabelDisplay::Absolute),
            valid: true,
            expected: "bnez        $t1, 0x7FFFFFF0",
            expected_opcode: Opcode::core_bnez,
            opcode_str: "bnez",
            operands_str: [Some("$t1"), Some("0x7FFFFFF0"), None, None, None],
            test_encoder: true,
        },
        TestEntry {
            instr: Instruction::new(
                0x46041000,
                Vram::new(0x80000000),
                InstructionFlags::new(IsaVersion::MIPS_I),
            ),
            imm_override: None,
            display_flags: InstructionDisplayFlags::default(),
            valid: true,
            expected: "add.s       $fv0, $fv1, $ft0",
            expected_opcode: Opcode::core_add_s,
            opcode_str: "add.s",
            operands_str: [Some("$fv0"), Some("$fv1"), Some("$ft0"), None, None],
            test_encoder: true,
        },
        TestEntry {
            instr: Instruction::new(
                0x46041001,
                Vram::new(0x80000000),
                InstructionFlags::new(IsaVersion::MIPS_I),
            ),
            imm_override: None,
            display_flags: InstructionDisplayFlags::default(),
            valid: true,
            expected: "sub.s       $fv0, $fv1, $ft0",
            expected_opcode: Opcode::core_sub_s,
            opcode_str: "sub.s",
            operands_str: [Some("$fv0"), Some("$fv1"), Some("$ft0"), None, None],
            test_encoder: true,
        },
        TestEntry {
            instr: Instruction::new(
                0x46041002,
                Vram::new(0x80000000),
                InstructionFlags::new(IsaVersion::MIPS_I),
            ),
            imm_override: None,
            display_flags: InstructionDisplayFlags::default(),
            valid: true,
            expected: "mul.s       $fv0, $fv1, $ft0",
            expected_opcode: Opcode::core_mul_s,
            opcode_str: "mul.s",
            operands_str: [Some("$fv0"), Some("$fv1"), Some("$ft0"), None, None],
            test_encoder: true,
        },
        TestEntry {
            instr: Instruction::new(
                0x46041003,
                Vram::new(0x80000000),
                InstructionFlags::new(IsaVersion::MIPS_I),
            ),
            imm_override: None,
            display_flags: InstructionDisplayFlags::default(),
            valid: true,
            expected: "div.s       $fv0, $fv1, $ft0",
            expected_opcode: Opcode::core_div_s,
            opcode_str: "div.s",
            operands_str: [Some("$fv0"), Some("$fv1"), Some("$ft0"), None, None],
            test_encoder: true,
        },
        TestEntry {
            instr: Instruction::new(
                0x46001005,
                Vram::new(0x80000000),
                InstructionFlags::new(IsaVersion::MIPS_I),
            ),
            imm_override: None,
            display_flags: InstructionDisplayFlags::default(),
            valid: true,
            expected: "abs.s       $fv0, $fv1",
            expected_opcode: Opcode::core_abs_s,
            opcode_str: "abs.s",
            operands_str: [Some("$fv0"), Some("$fv1"), None, None, None],
            test_encoder: true,
        },
        TestEntry {
            instr: Instruction::new(
                0x46001006,
                Vram::new(0x80000000),
                InstructionFlags::new(IsaVersion::MIPS_I),
            ),
            imm_override: None,
            display_flags: InstructionDisplayFlags::default(),
            valid: true,
            expected: "mov.s       $fv0, $fv1",
            expected_opcode: Opcode::core_mov_s,
            opcode_str: "mov.s",
            operands_str: [Some("$fv0"), Some("$fv1"), None, None, None],
            test_encoder: true,
        },
        TestEntry {
            instr: Instruction::new(
                0x46001007,
                Vram::new(0x80000000),
                InstructionFlags::new(IsaVersion::MIPS_I),
            ),
            imm_override: None,
            display_flags: InstructionDisplayFlags::default(),
            valid: true,
            expected: "neg.s       $fv0, $fv1",
            expected_opcode: Opcode::core_neg_s,
            opcode_str: "neg.s",
            operands_str: [Some("$fv0"), Some("$fv1"), None, None, None],
            test_encoder: true,
        },
        TestEntry {
            instr: Instruction::new(
                0x46001021,
                Vram::new(0x80000000),
                InstructionFlags::new(IsaVersion::MIPS_I),
            ),
            imm_override: None,
            display_flags: InstructionDisplayFlags::default(),
            valid: true,
            expected: "cvt.d.s     $fv0, $fv1",
            expected_opcode: Opcode::core_cvt_d_s,
            opcode_str: "cvt.d.s",
            operands_str: [Some("$fv0"), Some("$fv1"), None, None, None],
            test_encoder: true,
        },
        TestEntry {
            instr: Instruction::new(
                0x46001024,
                Vram::new(0x80000000),
                InstructionFlags::new(IsaVersion::MIPS_I),
            ),
            imm_override: None,
            display_flags: InstructionDisplayFlags::default(),
            valid: true,
            expected: "cvt.w.s     $fv0, $fv1",
            expected_opcode: Opcode::core_cvt_w_s,
            opcode_str: "cvt.w.s",
            operands_str: [Some("$fv0"), Some("$fv1"), None, None, None],
            test_encoder: true,
        },
        TestEntry {
            instr: Instruction::new(
                0x46020030,
                Vram::new(0x80000000),
                InstructionFlags::new(IsaVersion::MIPS_I),
            ),
            imm_override: None,
            display_flags: InstructionDisplayFlags::default(),
            valid: true,
            expected: "c.f.s       $fv0, $fv1",
            expected_opcode: Opcode::core_c_f_s,
            opcode_str: "c.f.s",
            operands_str: [Some("$fv0"), Some("$fv1"), None, None, None],
            test_encoder: true,
        },
        TestEntry {
            instr: Instruction::new(
                0x46020031,
                Vram::new(0x80000000),
                InstructionFlags::new(IsaVersion::MIPS_I),
            ),
            imm_override: None,
            display_flags: InstructionDisplayFlags::default(),
            valid: true,
            expected: "c.un.s      $fv0, $fv1",
            expected_opcode: Opcode::core_c_un_s,
            opcode_str: "c.un.s",
            operands_str: [Some("$fv0"), Some("$fv1"), None, None, None],
            test_encoder: true,
        },
        TestEntry {
            instr: Instruction::new(
                0x46020032,
                Vram::new(0x80000000),
                InstructionFlags::new(IsaVersion::MIPS_I),
            ),
            imm_override: None,
            display_flags: InstructionDisplayFlags::default(),
            valid: true,
            expected: "c.eq.s      $fv0, $fv1",
            expected_opcode: Opcode::core_c_eq_s,
            opcode_str: "c.eq.s",
            operands_str: [Some("$fv0"), Some("$fv1"), None, None, None],
            test_encoder: true,
        },
        TestEntry {
            instr: Instruction::new(
                0x46020033,
                Vram::new(0x80000000),
                InstructionFlags::new(IsaVersion::MIPS_I),
            ),
            imm_override: None,
            display_flags: InstructionDisplayFlags::default(),
            valid: true,
            expected: "c.ueq.s     $fv0, $fv1",
            expected_opcode: Opcode::core_c_ueq_s,
            opcode_str: "c.ueq.s",
            operands_str: [Some("$fv0"), Some("$fv1"), None, None, None],
            test_encoder: true,
        },
        TestEntry {
            instr: Instruction::new(
                0x46020034,
                Vram::new(0x80000000),
                InstructionFlags::new(IsaVersion::MIPS_I),
            ),
            imm_override: None,
            display_flags: InstructionDisplayFlags::default(),
            valid: true,
            expected: "c.olt.s     $fv0, $fv1",
            expected_opcode: Opcode::core_c_olt_s,
            opcode_str: "c.olt.s",
            operands_str: [Some("$fv0"), Some("$fv1"), None, None, None],
            test_encoder: true,
        },
        TestEntry {
            instr: Instruction::new(
                0x46020035,
                Vram::new(0x80000000),
                InstructionFlags::new(IsaVersion::MIPS_I),
            ),
            imm_override: None,
            display_flags: InstructionDisplayFlags::default(),
            valid: true,
            expected: "c.ult.s     $fv0, $fv1",
            expected_opcode: Opcode::core_c_ult_s,
            opcode_str: "c.ult.s",
            operands_str: [Some("$fv0"), Some("$fv1"), None, None, None],
            test_encoder: true,
        },
        TestEntry {
            instr: Instruction::new(
                0x46020036,
                Vram::new(0x80000000),
                InstructionFlags::new(IsaVersion::MIPS_I),
            ),
            imm_override: None,
            display_flags: InstructionDisplayFlags::default(),
            valid: true,
            expected: "c.ole.s     $fv0, $fv1",
            expected_opcode: Opcode::core_c_ole_s,
            opcode_str: "c.ole.s",
            operands_str: [Some("$fv0"), Some("$fv1"), None, None, None],
            test_encoder: true,
        },
        TestEntry {
            instr: Instruction::new(
                0x46020037,
                Vram::new(0x80000000),
                InstructionFlags::new(IsaVersion::MIPS_I),
            ),
            imm_override: None,
            display_flags: InstructionDisplayFlags::default(),
            valid: true,
            expected: "c.ule.s     $fv0, $fv1",
            expected_opcode: Opcode::core_c_ule_s,
            opcode_str: "c.ule.s",
            operands_str: [Some("$fv0"), Some("$fv1"), None, None, None],
            test_encoder: true,
        },
        TestEntry {
            instr: Instruction::new(
                0x46020038,
                Vram::new(0x80000000),
                InstructionFlags::new(IsaVersion::MIPS_I),
            ),
            imm_override: None,
            display_flags: InstructionDisplayFlags::default(),
            valid: true,
            expected: "c.sf.s      $fv0, $fv1",
            expected_opcode: Opcode::core_c_sf_s,
            opcode_str: "c.sf.s",
            operands_str: [Some("$fv0"), Some("$fv1"), None, None, None],
            test_encoder: true,
        },
        TestEntry {
            instr: Instruction::new(
                0x46020039,
                Vram::new(0x80000000),
                InstructionFlags::new(IsaVersion::MIPS_I),
            ),
            imm_override: None,
            display_flags: InstructionDisplayFlags::default(),
            valid: true,
            expected: "c.ngle.s    $fv0, $fv1",
            expected_opcode: Opcode::core_c_ngle_s,
            opcode_str: "c.ngle.s",
            operands_str: [Some("$fv0"), Some("$fv1"), None, None, None],
            test_encoder: true,
        },
        TestEntry {
            instr: Instruction::new(
                0x4602003A,
                Vram::new(0x80000000),
                InstructionFlags::new(IsaVersion::MIPS_I),
            ),
            imm_override: None,
            display_flags: InstructionDisplayFlags::default(),
            valid: true,
            expected: "c.seq.s     $fv0, $fv1",
            expected_opcode: Opcode::core_c_seq_s,
            opcode_str: "c.seq.s",
            operands_str: [Some("$fv0"), Some("$fv1"), None, None, None],
            test_encoder: true,
        },
        TestEntry {
            instr: Instruction::new(
                0x4602003B,
                Vram::new(0x80000000),
                InstructionFlags::new(IsaVersion::MIPS_I),
            ),
            imm_override: None,
            display_flags: InstructionDisplayFlags::default(),
            valid: true,
            expected: "c.ngl.s     $fv0, $fv1",
            expected_opcode: Opcode::core_c_ngl_s,
            opcode_str: "c.ngl.s",
            operands_str: [Some("$fv0"), Some("$fv1"), None, None, None],
            test_encoder: true,
        },
        TestEntry {
            instr: Instruction::new(
                0x4602003C,
                Vram::new(0x80000000),
                InstructionFlags::new(IsaVersion::MIPS_I),
            ),
            imm_override: None,
            display_flags: InstructionDisplayFlags::default(),
            valid: true,
            expected: "c.lt.s      $fv0, $fv1",
            expected_opcode: Opcode::core_c_lt_s,
            opcode_str: "c.lt.s",
            operands_str: [Some("$fv0"), Some("$fv1"), None, None, None],
            test_encoder: true,
        },
        TestEntry {
            instr: Instruction::new(
                0x4602003D,
                Vram::new(0x80000000),
                InstructionFlags::new(IsaVersion::MIPS_I),
            ),
            imm_override: None,
            display_flags: InstructionDisplayFlags::default(),
            valid: true,
            expected: "c.nge.s     $fv0, $fv1",
            expected_opcode: Opcode::core_c_nge_s,
            opcode_str: "c.nge.s",
            operands_str: [Some("$fv0"), Some("$fv1"), None, None, None],
            test_encoder: true,
        },
        TestEntry {
            instr: Instruction::new(
                0x4602003E,
                Vram::new(0x80000000),
                InstructionFlags::new(IsaVersion::MIPS_I),
            ),
            imm_override: None,
            display_flags: InstructionDisplayFlags::default(),
            valid: true,
            expected: "c.le.s      $fv0, $fv1",
            expected_opcode: Opcode::core_c_le_s,
            opcode_str: "c.le.s",
            operands_str: [Some("$fv0"), Some("$fv1"), None, None, None],
            test_encoder: true,
        },
        TestEntry {
            instr: Instruction::new(
                0x4602003F,
                Vram::new(0x80000000),
                InstructionFlags::new(IsaVersion::MIPS_I),
            ),
            imm_override: None,
            display_flags: InstructionDisplayFlags::default(),
            valid: true,
            expected: "c.ngt.s     $fv0, $fv1",
            expected_opcode: Opcode::core_c_ngt_s,
            opcode_str: "c.ngt.s",
            operands_str: [Some("$fv0"), Some("$fv1"), None, None, None],
            test_encoder: true,
        },
        TestEntry {
            instr: Instruction::new(
                0x46801020,
                Vram::new(0x80000000),
                InstructionFlags::new(IsaVersion::MIPS_I),
            ),
            imm_override: None,
            display_flags: InstructionDisplayFlags::default(),
            valid: true,
            expected: "cvt.s.w     $fv0, $fv1",
            expected_opcode: Opcode::core_cvt_s_w,
            opcode_str: "cvt.s.w",
            operands_str: [Some("$fv0"), Some("$fv1"), None, None, None],
            test_encoder: true,
        },
        TestEntry {
            instr: Instruction::new(
                0x46801021,
                Vram::new(0x80000000),
                InstructionFlags::new(IsaVersion::MIPS_I),
            ),
            imm_override: None,
            display_flags: InstructionDisplayFlags::default(),
            valid: true,
            expected: "cvt.d.w     $fv0, $fv1",
            expected_opcode: Opcode::core_cvt_d_w,
            opcode_str: "cvt.d.w",
            operands_str: [Some("$fv0"), Some("$fv1"), None, None, None],
            test_encoder: true,
        },
        TestEntry {
            instr: Instruction::new(
                0x46241000,
                Vram::new(0x80000000),
                InstructionFlags::new(IsaVersion::MIPS_I),
            ),
            imm_override: None,
            display_flags: InstructionDisplayFlags::default(),
            valid: true,
            expected: "add.d       $fv0, $fv1, $ft0",
            expected_opcode: Opcode::core_add_d,
            opcode_str: "add.d",
            operands_str: [Some("$fv0"), Some("$fv1"), Some("$ft0"), None, None],
            test_encoder: true,
        },
        TestEntry {
            instr: Instruction::new(
                0x46241001,
                Vram::new(0x80000000),
                InstructionFlags::new(IsaVersion::MIPS_I),
            ),
            imm_override: None,
            display_flags: InstructionDisplayFlags::default(),
            valid: true,
            expected: "sub.d       $fv0, $fv1, $ft0",
            expected_opcode: Opcode::core_sub_d,
            opcode_str: "sub.d",
            operands_str: [Some("$fv0"), Some("$fv1"), Some("$ft0"), None, None],
            test_encoder: true,
        },
        TestEntry {
            instr: Instruction::new(
                0x46241002,
                Vram::new(0x80000000),
                InstructionFlags::new(IsaVersion::MIPS_I),
            ),
            imm_override: None,
            display_flags: InstructionDisplayFlags::default(),
            valid: true,
            expected: "mul.d       $fv0, $fv1, $ft0",
            expected_opcode: Opcode::core_mul_d,
            opcode_str: "mul.d",
            operands_str: [Some("$fv0"), Some("$fv1"), Some("$ft0"), None, None],
            test_encoder: true,
        },
        TestEntry {
            instr: Instruction::new(
                0x46241003,
                Vram::new(0x80000000),
                InstructionFlags::new(IsaVersion::MIPS_I),
            ),
            imm_override: None,
            display_flags: InstructionDisplayFlags::default(),
            valid: true,
            expected: "div.d       $fv0, $fv1, $ft0",
            expected_opcode: Opcode::core_div_d,
            opcode_str: "div.d",
            operands_str: [Some("$fv0"), Some("$fv1"), Some("$ft0"), None, None],
            test_encoder: true,
        },
        TestEntry {
            instr: Instruction::new(
                0x46201005,
                Vram::new(0x80000000),
                InstructionFlags::new(IsaVersion::MIPS_I),
            ),
            imm_override: None,
            display_flags: InstructionDisplayFlags::default(),
            valid: true,
            expected: "abs.d       $fv0, $fv1",
            expected_opcode: Opcode::core_abs_d,
            opcode_str: "abs.d",
            operands_str: [Some("$fv0"), Some("$fv1"), None, None, None],
            test_encoder: true,
        },
        TestEntry {
            instr: Instruction::new(
                0x46201006,
                Vram::new(0x80000000),
                InstructionFlags::new(IsaVersion::MIPS_I),
            ),
            imm_override: None,
            display_flags: InstructionDisplayFlags::default(),
            valid: true,
            expected: "mov.d       $fv0, $fv1",
            expected_opcode: Opcode::core_mov_d,
            opcode_str: "mov.d",
            operands_str: [Some("$fv0"), Some("$fv1"), None, None, None],
            test_encoder: true,
        },
        TestEntry {
            instr: Instruction::new(
                0x46201007,
                Vram::new(0x80000000),
                InstructionFlags::new(IsaVersion::MIPS_I),
            ),
            imm_override: None,
            display_flags: InstructionDisplayFlags::default(),
            valid: true,
            expected: "neg.d       $fv0, $fv1",
            expected_opcode: Opcode::core_neg_d,
            opcode_str: "neg.d",
            operands_str: [Some("$fv0"), Some("$fv1"), None, None, None],
            test_encoder: true,
        },
        TestEntry {
            instr: Instruction::new(
                0x46201020,
                Vram::new(0x80000000),
                InstructionFlags::new(IsaVersion::MIPS_I),
            ),
            imm_override: None,
            display_flags: InstructionDisplayFlags::default(),
            valid: true,
            expected: "cvt.s.d     $fv0, $fv1",
            expected_opcode: Opcode::core_cvt_s_d,
            opcode_str: "cvt.s.d",
            operands_str: [Some("$fv0"), Some("$fv1"), None, None, None],
            test_encoder: true,
        },
        TestEntry {
            instr: Instruction::new(
                0x46201024,
                Vram::new(0x80000000),
                InstructionFlags::new(IsaVersion::MIPS_I),
            ),
            imm_override: None,
            display_flags: InstructionDisplayFlags::default(),
            valid: true,
            expected: "cvt.w.d     $fv0, $fv1",
            expected_opcode: Opcode::core_cvt_w_d,
            opcode_str: "cvt.w.d",
            operands_str: [Some("$fv0"), Some("$fv1"), None, None, None],
            test_encoder: true,
        },
        TestEntry {
            instr: Instruction::new(
                0x46220030,
                Vram::new(0x80000000),
                InstructionFlags::new(IsaVersion::MIPS_I),
            ),
            imm_override: None,
            display_flags: InstructionDisplayFlags::default(),
            valid: true,
            expected: "c.f.d       $fv0, $fv1",
            expected_opcode: Opcode::core_c_f_d,
            opcode_str: "c.f.d",
            operands_str: [Some("$fv0"), Some("$fv1"), None, None, None],
            test_encoder: true,
        },
        TestEntry {
            instr: Instruction::new(
                0x46220031,
                Vram::new(0x80000000),
                InstructionFlags::new(IsaVersion::MIPS_I),
            ),
            imm_override: None,
            display_flags: InstructionDisplayFlags::default(),
            valid: true,
            expected: "c.un.d      $fv0, $fv1",
            expected_opcode: Opcode::core_c_un_d,
            opcode_str: "c.un.d",
            operands_str: [Some("$fv0"), Some("$fv1"), None, None, None],
            test_encoder: true,
        },
        TestEntry {
            instr: Instruction::new(
                0x46220032,
                Vram::new(0x80000000),
                InstructionFlags::new(IsaVersion::MIPS_I),
            ),
            imm_override: None,
            display_flags: InstructionDisplayFlags::default(),
            valid: true,
            expected: "c.eq.d      $fv0, $fv1",
            expected_opcode: Opcode::core_c_eq_d,
            opcode_str: "c.eq.d",
            operands_str: [Some("$fv0"), Some("$fv1"), None, None, None],
            test_encoder: true,
        },
        TestEntry {
            instr: Instruction::new(
                0x46220033,
                Vram::new(0x80000000),
                InstructionFlags::new(IsaVersion::MIPS_I),
            ),
            imm_override: None,
            display_flags: InstructionDisplayFlags::default(),
            valid: true,
            expected: "c.ueq.d     $fv0, $fv1",
            expected_opcode: Opcode::core_c_ueq_d,
            opcode_str: "c.ueq.d",
            operands_str: [Some("$fv0"), Some("$fv1"), None, None, None],
            test_encoder: true,
        },
        TestEntry {
            instr: Instruction::new(
                0x46220034,
                Vram::new(0x80000000),
                InstructionFlags::new(IsaVersion::MIPS_I),
            ),
            imm_override: None,
            display_flags: InstructionDisplayFlags::default(),
            valid: true,
            expected: "c.olt.d     $fv0, $fv1",
            expected_opcode: Opcode::core_c_olt_d,
            opcode_str: "c.olt.d",
            operands_str: [Some("$fv0"), Some("$fv1"), None, None, None],
            test_encoder: true,
        },
        TestEntry {
            instr: Instruction::new(
                0x46220035,
                Vram::new(0x80000000),
                InstructionFlags::new(IsaVersion::MIPS_I),
            ),
            imm_override: None,
            display_flags: InstructionDisplayFlags::default(),
            valid: true,
            expected: "c.ult.d     $fv0, $fv1",
            expected_opcode: Opcode::core_c_ult_d,
            opcode_str: "c.ult.d",
            operands_str: [Some("$fv0"), Some("$fv1"), None, None, None],
            test_encoder: true,
        },
        TestEntry {
            instr: Instruction::new(
                0x46220036,
                Vram::new(0x80000000),
                InstructionFlags::new(IsaVersion::MIPS_I),
            ),
            imm_override: None,
            display_flags: InstructionDisplayFlags::default(),
            valid: true,
            expected: "c.ole.d     $fv0, $fv1",
            expected_opcode: Opcode::core_c_ole_d,
            opcode_str: "c.ole.d",
            operands_str: [Some("$fv0"), Some("$fv1"), None, None, None],
            test_encoder: true,
        },
        TestEntry {
            instr: Instruction::new(
                0x46220037,
                Vram::new(0x80000000),
                InstructionFlags::new(IsaVersion::MIPS_I),
            ),
            imm_override: None,
            display_flags: InstructionDisplayFlags::default(),
            valid: true,
            expected: "c.ule.d     $fv0, $fv1",
            expected_opcode: Opcode::core_c_ule_d,
            opcode_str: "c.ule.d",
            operands_str: [Some("$fv0"), Some("$fv1"), None, None, None],
            test_encoder: true,
        },
        TestEntry {
            instr: Instruction::new(
                0x46220038,
                Vram::new(0x80000000),
                InstructionFlags::new(IsaVersion::MIPS_I),
            ),
            imm_override: None,
            display_flags: InstructionDisplayFlags::default(),
            valid: true,
            expected: "c.df.d      $fv0, $fv1",
            expected_opcode: Opcode::core_c_df_d,
            opcode_str: "c.df.d",
            operands_str: [Some("$fv0"), Some("$fv1"), None, None, None],
            test_encoder: true,
        },
        TestEntry {
            instr: Instruction::new(
                0x46220039,
                Vram::new(0x80000000),
                InstructionFlags::new(IsaVersion::MIPS_I),
            ),
            imm_override: None,
            display_flags: InstructionDisplayFlags::default(),
            valid: true,
            expected: "c.ngle.d    $fv0, $fv1",
            expected_opcode: Opcode::core_c_ngle_d,
            opcode_str: "c.ngle.d",
            operands_str: [Some("$fv0"), Some("$fv1"), None, None, None],
            test_encoder: true,
        },
        TestEntry {
            instr: Instruction::new(
                0x4622003A,
                Vram::new(0x80000000),
                InstructionFlags::new(IsaVersion::MIPS_I),
            ),
            imm_override: None,
            display_flags: InstructionDisplayFlags::default(),
            valid: true,
            expected: "c.seq.d     $fv0, $fv1",
            expected_opcode: Opcode::core_c_seq_d,
            opcode_str: "c.seq.d",
            operands_str: [Some("$fv0"), Some("$fv1"), None, None, None],
            test_encoder: true,
        },
        TestEntry {
            instr: Instruction::new(
                0x4622003B,
                Vram::new(0x80000000),
                InstructionFlags::new(IsaVersion::MIPS_I),
            ),
            imm_override: None,
            display_flags: InstructionDisplayFlags::default(),
            valid: true,
            expected: "c.ngl.d     $fv0, $fv1",
            expected_opcode: Opcode::core_c_ngl_d,
            opcode_str: "c.ngl.d",
            operands_str: [Some("$fv0"), Some("$fv1"), None, None, None],
            test_encoder: true,
        },
        TestEntry {
            instr: Instruction::new(
                0x4622003C,
                Vram::new(0x80000000),
                InstructionFlags::new(IsaVersion::MIPS_I),
            ),
            imm_override: None,
            display_flags: InstructionDisplayFlags::default(),
            valid: true,
            expected: "c.lt.d      $fv0, $fv1",
            expected_opcode: Opcode::core_c_lt_d,
            opcode_str: "c.lt.d",
            operands_str: [Some("$fv0"), Some("$fv1"), None, None, None],
            test_encoder: true,
        },
        TestEntry {
            instr: Instruction::new(
                0x4622003D,
                Vram::new(0x80000000),
                InstructionFlags::new(IsaVersion::MIPS_I),
            ),
            imm_override: None,
            display_flags: InstructionDisplayFlags::default(),
            valid: true,
            expected: "c.nge.d     $fv0, $fv1",
            expected_opcode: Opcode::core_c_nge_d,
            opcode_str: "c.nge.d",
            operands_str: [Some("$fv0"), Some("$fv1"), None, None, None],
            test_encoder: true,
        },
        TestEntry {
            instr: Instruction::new(
                0x4622003E,
                Vram::new(0x80000000),
                InstructionFlags::new(IsaVersion::MIPS_I),
            ),
            imm_override: None,
            display_flags: InstructionDisplayFlags::default(),
            valid: true,
            expected: "c.le.d      $fv0, $fv1",
            expected_opcode: Opcode::core_c_le_d,
            opcode_str: "c.le.d",
            operands_str: [Some("$fv0"), Some("$fv1"), None, None, None],
            test_encoder: true,
        },
        TestEntry {
            instr: Instruction::new(
                0x4622003F,
                Vram::new(0x80000000),
                InstructionFlags::new(IsaVersion::MIPS_I),
            ),
            imm_override: None,
            display_flags: InstructionDisplayFlags::default(),
            valid: true,
            expected: "c.ngt.d     $fv0, $fv1",
            expected_opcode: Opcode::core_c_ngt_d,
            opcode_str: "c.ngt.d",
            operands_str: [Some("$fv0"), Some("$fv1"), None, None, None],
            test_encoder: true,
        },
    ];

    assert_eq!(check_test_entries(ENTRIES), (0, 0));
}

#[cfg(feature = "MIPS_II")]
#[test]
fn check_none_instructions_mips_2() {
    static ENTRIES: &[TestEntry] = &[
        TestEntry {
            instr: Instruction::new(
                0x46001004,
                Vram::new(0x80000000),
                InstructionFlags::new(IsaVersion::MIPS_II),
            ),
            imm_override: None,
            display_flags: InstructionDisplayFlags::default(),
            valid: true,
            expected: "sqrt.s      $fv0, $fv1",
            expected_opcode: Opcode::core_sqrt_s,
            opcode_str: "sqrt.s",
            operands_str: [Some("$fv0"), Some("$fv1"), None, None, None],
            test_encoder: true,
        },
        TestEntry {
            instr: Instruction::new(
                0x4600100C,
                Vram::new(0x80000000),
                InstructionFlags::new(IsaVersion::MIPS_II),
            ),
            imm_override: None,
            display_flags: InstructionDisplayFlags::default(),
            valid: true,
            expected: "round.w.s   $fv0, $fv1",
            expected_opcode: Opcode::core_round_w_s,
            opcode_str: "round.w.s",
            operands_str: [Some("$fv0"), Some("$fv1"), None, None, None],
            test_encoder: true,
        },
        TestEntry {
            instr: Instruction::new(
                0x4600100D,
                Vram::new(0x80000000),
                InstructionFlags::new(IsaVersion::MIPS_II),
            ),
            imm_override: None,
            display_flags: InstructionDisplayFlags::default(),
            valid: true,
            expected: "trunc.w.s   $fv0, $fv1",
            expected_opcode: Opcode::core_trunc_w_s,
            opcode_str: "trunc.w.s",
            operands_str: [Some("$fv0"), Some("$fv1"), None, None, None],
            test_encoder: true,
        },
        TestEntry {
            instr: Instruction::new(
                0x4600100E,
                Vram::new(0x80000000),
                InstructionFlags::new(IsaVersion::MIPS_II),
            ),
            imm_override: None,
            display_flags: InstructionDisplayFlags::default(),
            valid: true,
            expected: "ceil.w.s    $fv0, $fv1",
            expected_opcode: Opcode::core_ceil_w_s,
            opcode_str: "ceil.w.s",
            operands_str: [Some("$fv0"), Some("$fv1"), None, None, None],
            test_encoder: true,
        },
        TestEntry {
            instr: Instruction::new(
                0x4600100F,
                Vram::new(0x80000000),
                InstructionFlags::new(IsaVersion::MIPS_II),
            ),
            imm_override: None,
            display_flags: InstructionDisplayFlags::default(),
            valid: true,
            expected: "floor.w.s   $fv0, $fv1",
            expected_opcode: Opcode::core_floor_w_s,
            opcode_str: "floor.w.s",
            operands_str: [Some("$fv0"), Some("$fv1"), None, None, None],
            test_encoder: true,
        },
        TestEntry {
            instr: Instruction::new(
                0x46201004,
                Vram::new(0x80000000),
                InstructionFlags::new(IsaVersion::MIPS_II),
            ),
            imm_override: None,
            display_flags: InstructionDisplayFlags::default(),
            valid: true,
            expected: "sqrt.d      $fv0, $fv1",
            expected_opcode: Opcode::core_sqrt_d,
            opcode_str: "sqrt.d",
            operands_str: [Some("$fv0"), Some("$fv1"), None, None, None],
            test_encoder: true,
        },
        TestEntry {
            instr: Instruction::new(
                0x4620100C,
                Vram::new(0x80000000),
                InstructionFlags::new(IsaVersion::MIPS_II),
            ),
            imm_override: None,
            display_flags: InstructionDisplayFlags::default(),
            valid: true,
            expected: "round.w.d   $fv0, $fv1",
            expected_opcode: Opcode::core_round_w_d,
            opcode_str: "round.w.d",
            operands_str: [Some("$fv0"), Some("$fv1"), None, None, None],
            test_encoder: true,
        },
        TestEntry {
            instr: Instruction::new(
                0x4620100D,
                Vram::new(0x80000000),
                InstructionFlags::new(IsaVersion::MIPS_II),
            ),
            imm_override: None,
            display_flags: InstructionDisplayFlags::default(),
            valid: true,
            expected: "trunc.w.d   $fv0, $fv1",
            expected_opcode: Opcode::core_trunc_w_d,
            opcode_str: "trunc.w.d",
            operands_str: [Some("$fv0"), Some("$fv1"), None, None, None],
            test_encoder: true,
        },
        TestEntry {
            instr: Instruction::new(
                0x4620100E,
                Vram::new(0x80000000),
                InstructionFlags::new(IsaVersion::MIPS_II),
            ),
            imm_override: None,
            display_flags: InstructionDisplayFlags::default(),
            valid: true,
            expected: "ceil.w.d    $fv0, $fv1",
            expected_opcode: Opcode::core_ceil_w_d,
            opcode_str: "ceil.w.d",
            operands_str: [Some("$fv0"), Some("$fv1"), None, None, None],
            test_encoder: true,
        },
        TestEntry {
            instr: Instruction::new(
                0x4620100F,
                Vram::new(0x80000000),
                InstructionFlags::new(IsaVersion::MIPS_II),
            ),
            imm_override: None,
            display_flags: InstructionDisplayFlags::default(),
            valid: true,
            expected: "floor.w.d   $fv0, $fv1",
            expected_opcode: Opcode::core_floor_w_d,
            opcode_str: "floor.w.d",
            operands_str: [Some("$fv0"), Some("$fv1"), None, None, None],
            test_encoder: true,
        },
    ];

    assert_eq!(check_test_entries(ENTRIES), (0, 0));
}

#[cfg(feature = "MIPS_III")]
#[test]
fn check_none_instructions_mips_3() {
    static ENTRIES: &[TestEntry] = &[
        TestEntry {
            instr: Instruction::new(
                0x08000419,
                Vram::new(0x80001100),
                InstructionFlags::new(IsaVersion::MIPS_III),
            ),
            imm_override: None,
            display_flags: InstructionDisplayFlags::default(),
            valid: true,
            expected: "j           func_80001064",
            expected_opcode: Opcode::core_j,
            opcode_str: "j",
            operands_str: [Some("func_80001064"), None, None, None, None],
            test_encoder: true,
        },
        TestEntry::new(
            0x3C088001,
            InstructionFlags::new(IsaVersion::MIPS_III),
            "lui         $t0, 0x8001",
            Opcode::core_lui,
            "lui",
            [Some("$t0"), Some("0x8001"), None, None, None],
        ),
        TestEntry::new(
            0x25080E60,
            InstructionFlags::new(IsaVersion::MIPS_III),
            "addiu       $t0, $t0, 0xE60",
            Opcode::core_addiu,
            "addiu",
            [Some("$t0"), Some("$t0"), Some("0xE60"), None, None],
        ),
        TestEntry::new(
            0x3C090002,
            InstructionFlags::new(IsaVersion::MIPS_III),
            "lui         $t1, 0x2",
            Opcode::core_lui,
            "lui",
            [Some("$t1"), Some("0x2"), None, None, None],
        ),
        TestEntry::new(
            0x25298DE0,
            InstructionFlags::new(IsaVersion::MIPS_III),
            "addiu       $t1, $t1, -0x7220",
            Opcode::core_addiu,
            "addiu",
            [Some("$t1"), Some("$t1"), Some("-0x7220"), None, None],
        ),
        TestEntry {
            instr: Instruction::new(
                0x25298DE0,
                Vram::new(0x80000000),
                InstructionFlags::new(IsaVersion::MIPS_III),
            ),
            imm_override: None,
            display_flags: InstructionDisplayFlags::default().with_use_dollar(false),
            valid: true,
            expected: "addiu       t1, t1, -0x7220",
            expected_opcode: Opcode::core_addiu,
            opcode_str: "addiu",
            operands_str: [Some("t1"), Some("t1"), Some("-0x7220"), None, None],
            test_encoder: true,
        },
        TestEntry::new(
            0xAD000000,
            InstructionFlags::new(IsaVersion::MIPS_III),
            "sw          $zero, 0x0($t0)",
            Opcode::core_sw,
            "sw",
            [Some("$zero"), Some("0x0($t0)"), None, None, None],
        ),
        TestEntry::new(
            0xAD000004,
            InstructionFlags::new(IsaVersion::MIPS_III),
            "sw          $zero, 0x4($t0)",
            Opcode::core_sw,
            "sw",
            [Some("$zero"), Some("0x4($t0)"), None, None, None],
        ),
        TestEntry::new(
            0x21080008,
            InstructionFlags::new(IsaVersion::MIPS_III),
            "addi        $t0, $t0, 0x8",
            Opcode::core_addi,
            "addi",
            [Some("$t0"), Some("$t0"), Some("0x8"), None, None],
        ),
        TestEntry::new(
            0x2129FFF8,
            InstructionFlags::new(IsaVersion::MIPS_III),
            "addi        $t1, $t1, -0x8",
            Opcode::core_addi,
            "addi",
            [Some("$t1"), Some("$t1"), Some("-0x8"), None, None],
        ),
        TestEntry::new(
            0x00000000,
            InstructionFlags::new(IsaVersion::MIPS_III),
            "nop",
            Opcode::core_nop,
            "nop",
            [None, None, None, None, None],
        ),
        TestEntry::new(
            0x3C0A8000,
            InstructionFlags::new(IsaVersion::MIPS_III),
            "lui         $t2, 0x8000",
            Opcode::core_lui,
            "lui",
            [Some("$t2"), Some("0x8000"), None, None, None],
        ),
        TestEntry::new(
            0x254A0494,
            InstructionFlags::new(IsaVersion::MIPS_III),
            "addiu       $t2, $t2, 0x494",
            Opcode::core_addiu,
            "addiu",
            [Some("$t2"), Some("$t2"), Some("0x494"), None, None],
        ),
        TestEntry::new(
            0x3C1D8002,
            InstructionFlags::new(IsaVersion::MIPS_III),
            "lui         $sp, 0x8002",
            Opcode::core_lui,
            "lui",
            [Some("$sp"), Some("0x8002"), None, None, None],
        ),
        TestEntry::new(
            0x01400008,
            InstructionFlags::new(IsaVersion::MIPS_III),
            "jr          $t2",
            Opcode::core_jr,
            "jr",
            [Some("$t2"), None, None, None, None],
        ),
        TestEntry::new(
            0x27BDF8C0,
            InstructionFlags::new(IsaVersion::MIPS_III),
            "addiu       $sp, $sp, -0x740",
            Opcode::core_addiu,
            "addiu",
            [Some("$sp"), Some("$sp"), Some("-0x740"), None, None],
        ),
        TestEntry::new(
            0x3C018001,
            InstructionFlags::new(IsaVersion::MIPS_III),
            "lui         $at, 0x8001",
            Opcode::core_lui,
            "lui",
            [Some("$at"), Some("0x8001"), None, None, None],
        ),
        TestEntry::new(
            0x03E00008,
            InstructionFlags::new(IsaVersion::MIPS_III),
            "jr          $ra",
            Opcode::core_jr,
            "jr",
            [Some("$ra"), None, None, None, None],
        ),
        TestEntry::new(
            0xAC24E190,
            InstructionFlags::new(IsaVersion::MIPS_III),
            "sw          $a0, -0x1E70($at)",
            Opcode::core_sw,
            "sw",
            [Some("$a0"), Some("-0x1E70($at)"), None, None, None],
        ),
        TestEntry {
            instr: Instruction::new(
                0x3C018001,
                Vram::new(0x80000000),
                InstructionFlags::new(IsaVersion::MIPS_III),
            ),
            imm_override: Some("%hi(D_8000E190)"),
            display_flags: InstructionDisplayFlags::default(),
            valid: true,
            expected: "lui         $at, %hi(D_8000E190)",
            expected_opcode: Opcode::core_lui,
            opcode_str: "lui",
            operands_str: [Some("$at"), Some("%hi(D_8000E190)"), None, None, None],
            test_encoder: true,
        },
        TestEntry {
            instr: Instruction::new(
                0xAC24E190,
                Vram::new(0x80000000),
                InstructionFlags::new(IsaVersion::MIPS_III),
            ),
            imm_override: Some("%lo(D_8000E190)"),
            display_flags: InstructionDisplayFlags::default(),
            valid: true,
            expected: "sw          $a0, %lo(D_8000E190)($at)",
            expected_opcode: Opcode::core_sw,
            opcode_str: "sw",
            operands_str: [Some("$a0"), Some("%lo(D_8000E190)($at)"), None, None, None],
            test_encoder: true,
        },
        TestEntry::new(
            0x0C001F24,
            InstructionFlags::new(IsaVersion::MIPS_III),
            "jal         func_80007C90",
            Opcode::core_jal,
            "jal",
            [Some("func_80007C90"), None, None, None, None],
        ),
        TestEntry {
            instr: Instruction::new(
                0x0C001F24,
                Vram::new(0x80000000),
                InstructionFlags::new(IsaVersion::MIPS_III),
            ),
            imm_override: Some("some_func"),
            display_flags: InstructionDisplayFlags::default(),
            valid: true,
            expected: "jal         some_func",
            expected_opcode: Opcode::core_jal,
            opcode_str: "jal",
            operands_str: [Some("some_func"), None, None, None, None],
            test_encoder: true,
        },
        TestEntry::new(
            0x8F99805C,
            InstructionFlags::new(IsaVersion::MIPS_III),
            "lw          $t9, -0x7FA4($gp)",
            Opcode::core_lw,
            "lw",
            [Some("$t9"), Some("-0x7FA4($gp)"), None, None, None],
        ),
        TestEntry {
            instr: Instruction::new(
                0x8F99805C,
                Vram::new(0x80000000),
                InstructionFlags::new(IsaVersion::MIPS_III),
            ),
            imm_override: Some("%call16(strcmp)"),
            display_flags: InstructionDisplayFlags::default(),
            valid: true,
            expected: "lw          $t9, %call16(strcmp)($gp)",
            expected_opcode: Opcode::core_lw,
            opcode_str: "lw",
            operands_str: [Some("$t9"), Some("%call16(strcmp)($gp)"), None, None, None],
            test_encoder: true,
        },
        TestEntry::new(
            0x8F858028,
            InstructionFlags::new(IsaVersion::MIPS_III),
            "lw          $a1, -0x7FD8($gp)",
            Opcode::core_lw,
            "lw",
            [Some("$a1"), Some("-0x7FD8($gp)"), None, None, None],
        ),
        TestEntry {
            instr: Instruction::new(
                0x8F858028,
                Vram::new(0x80000000),
                InstructionFlags::new(IsaVersion::MIPS_III),
            ),
            imm_override: Some("%got(STR_10007C90)"),
            display_flags: InstructionDisplayFlags::default(),
            valid: true,
            expected: "lw          $a1, %got(STR_10007C90)($gp)",
            expected_opcode: Opcode::core_lw,
            opcode_str: "lw",
            operands_str: [
                Some("$a1"),
                Some("%got(STR_10007C90)($gp)"),
                None,
                None,
                None,
            ],
            test_encoder: true,
        },
        TestEntry::new(
            0x00435022,
            InstructionFlags::new(IsaVersion::MIPS_III),
            "sub         $t2, $v0, $v1",
            Opcode::core_sub,
            "sub",
            [Some("$t2"), Some("$v0"), Some("$v1"), None, None],
        ),
        TestEntry::new(
            0x00025022,
            InstructionFlags::new(IsaVersion::MIPS_III),
            "neg         $t2, $v0",
            Opcode::core_neg,
            "neg",
            [Some("$t2"), Some("$v0"), None, None, None],
        ),
        TestEntry::new(
            0x00E41823,
            InstructionFlags::new(IsaVersion::MIPS_III),
            "subu        $v1, $a3, $a0",
            Opcode::core_subu,
            "subu",
            [Some("$v1"), Some("$a3"), Some("$a0"), None, None],
        ),
        TestEntry::new(
            0x00041823,
            InstructionFlags::new(IsaVersion::MIPS_III),
            "negu        $v1, $a0",
            Opcode::core_negu,
            "negu",
            [Some("$v1"), Some("$a0"), None, None, None],
        ),
        TestEntry::new(
            0x42000010,
            InstructionFlags::new(IsaVersion::MIPS_III),
            "rfe",
            Opcode::core_rfe,
            "rfe",
            [None, None, None, None, None],
        ),
        TestEntry::new(
            0x0260F809,
            InstructionFlags::new(IsaVersion::MIPS_III),
            "jalr        $s3",
            Opcode::core_jalr,
            "jalr",
            [Some("$s3"), None, None, None, None],
        ),
        TestEntry {
            instr: Instruction::new(
                0x0260F809,
                Vram::new(0x80000000),
                InstructionFlags::new(IsaVersion::MIPS_III),
            ),
            imm_override: None,
            display_flags: InstructionDisplayFlags::default().with_expand_jalr(true),
            valid: true,
            expected: "jalr        $ra, $s3",
            expected_opcode: Opcode::core_jalr,
            opcode_str: "jalr",
            operands_str: [Some("$ra, $s3"), None, None, None, None],
            test_encoder: true,
        },
        TestEntry::new(
            0x02602009,
            InstructionFlags::new(IsaVersion::MIPS_III),
            "jalr        $a0, $s3",
            Opcode::core_jalr,
            "jalr",
            [Some("$a0, $s3"), None, None, None, None],
        ),
        TestEntry::new(
            0x00042100,
            InstructionFlags::new(IsaVersion::MIPS_III),
            "sll         $a0, $a0, 4",
            Opcode::core_sll,
            "sll",
            [Some("$a0"), Some("$a0"), Some("4"), None, None],
        ),
        TestEntry::new(
            0x00021882,
            InstructionFlags::new(IsaVersion::MIPS_III),
            "srl         $v1, $v0, 2",
            Opcode::core_srl,
            "srl",
            [Some("$v1"), Some("$v0"), Some("2"), None, None],
        ),
        TestEntry::new(
            0x00017443,
            InstructionFlags::new(IsaVersion::MIPS_III),
            "sra         $t6, $at, 17",
            Opcode::core_sra,
            "sra",
            [Some("$t6"), Some("$at"), Some("17"), None, None],
        ),
        TestEntry::new(
            0x00042FF8,
            InstructionFlags::new(IsaVersion::MIPS_III),
            "dsll        $a1, $a0, 31",
            Opcode::core_dsll,
            "dsll",
            [Some("$a1"), Some("$a0"), Some("31"), None, None],
        ),
        TestEntry::new(
            0x000637FA,
            InstructionFlags::new(IsaVersion::MIPS_III),
            "dsrl        $a2, $a2, 31",
            Opcode::core_dsrl,
            "dsrl",
            [Some("$a2"), Some("$a2"), Some("31"), None, None],
        ),
        TestEntry::new(
            0x0002137B,
            InstructionFlags::new(IsaVersion::MIPS_III),
            "dsra        $v0, $v0, 13",
            Opcode::core_dsra,
            "dsra",
            [Some("$v0"), Some("$v0"), Some("13"), None, None],
        ),
        TestEntry::new(
            0x000437FC,
            InstructionFlags::new(IsaVersion::MIPS_III),
            "dsll32      $a2, $a0, 31",
            Opcode::core_dsll32,
            "dsll32",
            [Some("$a2"), Some("$a0"), Some("31"), None, None],
        ),
        TestEntry::new(
            0x0005283E,
            InstructionFlags::new(IsaVersion::MIPS_III),
            "dsrl32      $a1, $a1, 0",
            Opcode::core_dsrl32,
            "dsrl32",
            [Some("$a1"), Some("$a1"), Some("0"), None, None],
        ),
        TestEntry::new(
            0x0002103F,
            InstructionFlags::new(IsaVersion::MIPS_III),
            "dsra32      $v0, $v0, 0",
            Opcode::core_dsra32,
            "dsra32",
            [Some("$v0"), Some("$v0"), Some("0"), None, None],
        ),
        TestEntry::new(
            0x40086800,
            InstructionFlags::new(IsaVersion::MIPS_III),
            "mfc0        $t0, $13",
            Opcode::core_mfc0,
            "mfc0",
            [Some("$t0"), Some("$13"), None, None, None],
        ),
        TestEntry::new(
            0x40286800,
            InstructionFlags::new(IsaVersion::MIPS_III),
            "dmfc0       $t0, $13",
            Opcode::core_dmfc0,
            "dmfc0",
            [Some("$t0"), Some("$13"), None, None, None],
        ),
        TestEntry::new(
            0x40486800,
            InstructionFlags::new(IsaVersion::MIPS_III),
            "cfc0        $t0, $13",
            Opcode::core_cfc0,
            "cfc0",
            [Some("$t0"), Some("$13"), None, None, None],
        ),
        TestEntry::new(
            0x40886800,
            InstructionFlags::new(IsaVersion::MIPS_III),
            "mtc0        $t0, $13",
            Opcode::core_mtc0,
            "mtc0",
            [Some("$t0"), Some("$13"), None, None, None],
        ),
        TestEntry::new(
            0x40A86800,
            InstructionFlags::new(IsaVersion::MIPS_III),
            "dmtc0       $t0, $13",
            Opcode::core_dmtc0,
            "dmtc0",
            [Some("$t0"), Some("$13"), None, None, None],
        ),
        TestEntry::new(
            0x40C86800,
            InstructionFlags::new(IsaVersion::MIPS_III),
            "ctc0        $t0, $13",
            Opcode::core_ctc0,
            "ctc0",
            [Some("$t0"), Some("$13"), None, None, None],
        ),
        TestEntry {
            instr: Instruction::new(
                0x46168200,
                Vram::new(0x80000000),
                InstructionFlags::new(IsaVersion::MIPS_III),
            ),
            imm_override: None,
            display_flags: InstructionDisplayFlags::default().with_named_fpr(false),
            valid: true,
            expected: "add.s       $f8, $f16, $f22",
            expected_opcode: Opcode::core_add_s,
            opcode_str: "add.s",
            operands_str: [Some("$f8"), Some("$f16"), Some("$f22"), None, None],
            test_encoder: true,
        },
        TestEntry {
            instr: Instruction::new(
                0x46168200,
                Vram::new(0x80000000),
                InstructionFlags::new(IsaVersion::MIPS_III),
            ),
            imm_override: None,
            display_flags: InstructionDisplayFlags::default().with_named_fpr(true),
            valid: true,
            expected: "add.s       $ft2, $ft4, $fs1",
            expected_opcode: Opcode::core_add_s,
            opcode_str: "add.s",
            operands_str: [Some("$ft2"), Some("$ft4"), Some("$fs1"), None, None],
            test_encoder: true,
        },
        TestEntry {
            instr: Instruction::new(
                0x46168200,
                Vram::new(0x80000000),
                InstructionFlags::new(IsaVersion::MIPS_III),
            ),
            imm_override: None,
            display_flags: InstructionDisplayFlags::default().with_use_dollar(false),
            valid: true,
            expected: "add.s       ft2, ft4, fs1",
            expected_opcode: Opcode::core_add_s,
            opcode_str: "add.s",
            operands_str: [Some("ft2"), Some("ft4"), Some("fs1"), None, None],
            test_encoder: true,
        },
        TestEntry::new(
            0x44C2F800,
            InstructionFlags::new(IsaVersion::MIPS_III),
            "ctc1        $v0, $31",
            Opcode::core_ctc1,
            "ctc1",
            [Some("$v0"), Some("$31"), None, None, None],
        ),
        TestEntry::new(
            0xBD150000,
            InstructionFlags::new(IsaVersion::MIPS_III),
            "cache       0x15, 0x0($t0)",
            Opcode::core_cache,
            "cache",
            [Some("0x15"), Some("0x0($t0)"), None, None, None],
        ),
        TestEntry::new_full_invalid(0xCD150018, InstructionFlags::new(IsaVersion::MIPS_III), ".word       0xCD150018                   /* INVALID / 01150018 <OpcodeCategory: CORE_NORMAL> */"),
        TestEntry::new(
            0x0001008D,
            InstructionFlags::new(IsaVersion::MIPS_III),
            "break       1, 2",
            Opcode::core_break,
            "break",
            [Some("1, 2"), None, None, None, None],
        ),
        TestEntry {
            instr: Instruction::new(
                0x0001008D,
                Vram::new(0x80000000),
                InstructionFlags::new(IsaVersion::MIPS_III),
            ),
            imm_override: None,
            display_flags: InstructionDisplayFlags::default().with_sn64_break_fix(true),
            valid: true,
            expected: ".word       0x0001008D                   /* break       1, 2 / 00000000 <OpcodeCategory: CORE_SPECIAL> */",
            expected_opcode: Opcode::core_break,
            opcode_str: "break",
            operands_str: [Some("1, 2"), None, None, None, None],
            test_encoder: true,
        },
        TestEntry::new(
            0x0007000D,
            InstructionFlags::new(IsaVersion::MIPS_III),
            "break       7",
            Opcode::core_break,
            "break",
            [Some("7"), None, None, None, None],
        ),
        TestEntry {
            instr: Instruction::new(
                0x0007000D,
                Vram::new(0x80000000),
                InstructionFlags::new(IsaVersion::MIPS_III),
            ),
            imm_override: None,
            display_flags: InstructionDisplayFlags::default().with_sn64_break_fix(true),
            valid: true,
            expected: ".word       0x0007000D                   /* break       7 / 00000000 <OpcodeCategory: CORE_SPECIAL> */",
            expected_opcode: Opcode::core_break,
            opcode_str: "break",
            operands_str: [Some("7"), None, None, None, None],
            test_encoder: true,
        },
        TestEntry::new(
            0x0000000C,
            InstructionFlags::new(IsaVersion::MIPS_III),
            "syscall     0",
            Opcode::core_syscall,
            "syscall",
            [Some("0"), None, None, None, None],
        ),
        TestEntry::new(
            0x00E200B0,
            InstructionFlags::new(IsaVersion::MIPS_III),
            "tge         $a3, $v0, 2",
            Opcode::core_tge,
            "tge",
            [Some("$a3"), Some("$v0"), Some("2"), None, None],
        ),
        TestEntry::new(
            0x00E200B1,
            InstructionFlags::new(IsaVersion::MIPS_III),
            "tgeu        $a3, $v0, 2",
            Opcode::core_tgeu,
            "tgeu",
            [Some("$a3"), Some("$v0"), Some("2"), None, None],
        ),
        TestEntry::new(
            0x00E200B2,
            InstructionFlags::new(IsaVersion::MIPS_III),
            "tlt         $a3, $v0, 2",
            Opcode::core_tlt,
            "tlt",
            [Some("$a3"), Some("$v0"), Some("2"), None, None],
        ),
        TestEntry::new(
            0x00E200B3,
            InstructionFlags::new(IsaVersion::MIPS_III),
            "tltu        $a3, $v0, 2",
            Opcode::core_tltu,
            "tltu",
            [Some("$a3"), Some("$v0"), Some("2"), None, None],
        ),
        TestEntry::new(
            0x00E200B4,
            InstructionFlags::new(IsaVersion::MIPS_III),
            "teq         $a3, $v0, 2",
            Opcode::core_teq,
            "teq",
            [Some("$a3"), Some("$v0"), Some("2"), None, None],
        ),
        TestEntry::new(
            0x00E200B6,
            InstructionFlags::new(IsaVersion::MIPS_III),
            "tne         $a3, $v0, 2",
            Opcode::core_tne,
            "tne",
            [Some("$a3"), Some("$v0"), Some("2"), None, None],
        ),
        TestEntry::new(
            0xC8621800,
            InstructionFlags::new(IsaVersion::MIPS_III),
            "lwc2        $2, 0x1800($v1)",
            Opcode::core_lwc2,
            "lwc2",
            [Some("$2"), Some("0x1800($v1)"), None, None, None],
        ),
        TestEntry::new(
            0xD8621800,
            InstructionFlags::new(IsaVersion::MIPS_III),
            "ldc2        $2, 0x1800($v1)",
            Opcode::core_ldc2,
            "ldc2",
            [Some("$2"), Some("0x1800($v1)"), None, None, None],
        ),
        TestEntry::new(
            0xE8810878,
            InstructionFlags::new(IsaVersion::MIPS_III),
            "swc2        $1, 0x878($a0)",
            Opcode::core_swc2,
            "swc2",
            [Some("$1"), Some("0x878($a0)"), None, None, None],
        ),
        TestEntry::new(
            0xF8810878,
            InstructionFlags::new(IsaVersion::MIPS_III),
            "sdc2        $1, 0x878($a0)",
            Opcode::core_sdc2,
            "sdc2",
            [Some("$1"), Some("0x878($a0)"), None, None, None],
        ),
        TestEntry::new(
            0x4802E000,
            InstructionFlags::new(IsaVersion::MIPS_III),
            "mfc2        $v0, $28",
            Opcode::core_mfc2,
            "mfc2",
            [Some("$v0"), Some("$28"), None, None, None],
        ),
        TestEntry::new(
            0x4882E000,
            InstructionFlags::new(IsaVersion::MIPS_III),
            "mtc2        $v0, $28",
            Opcode::core_mtc2,
            "mtc2",
            [Some("$v0"), Some("$28"), None, None, None],
        ),
        TestEntry::new(
            0x4842E000,
            InstructionFlags::new(IsaVersion::MIPS_III),
            "cfc2        $v0, $28",
            Opcode::core_cfc2,
            "cfc2",
            [Some("$v0"), Some("$28"), None, None, None],
        ),
        TestEntry::new(
            0x48C2E000,
            InstructionFlags::new(IsaVersion::MIPS_III),
            "ctc2        $v0, $28",
            Opcode::core_ctc2,
            "ctc2",
            [Some("$v0"), Some("$28"), None, None, None],
        ),
        TestEntry::new(
            0x50850007,
            InstructionFlags::new(IsaVersion::MIPS_III).with_pseudo_beqzl(true),
            "beql        $a0, $a1, . + 4 + (0x7 << 2)",
            Opcode::core_beql,
            "beql",
            [Some("$a0"), Some("$a1"), Some(". + 4 + (0x7 << 2)"), None, None],
        ),
        TestEntry::new(
            0x50800007,
            InstructionFlags::new(IsaVersion::MIPS_III).with_pseudo_beqzl(true),
            "beqzl       $a0, . + 4 + (0x7 << 2)",
            Opcode::core_beqzl,
            "beqzl",
            [Some("$a0"), Some(". + 4 + (0x7 << 2)"), None, None, None],
        ),
        TestEntry::new(
            0x50800007,
            InstructionFlags::new(IsaVersion::MIPS_III).with_pseudo_beqzl(false),
            "beql        $a0, $zero, . + 4 + (0x7 << 2)",
            Opcode::core_beql,
            "beql",
            [Some("$a0"), Some("$zero"), Some(". + 4 + (0x7 << 2)"), None, None],
        ),
        TestEntry::new(
            0x54850005,
            InstructionFlags::new(IsaVersion::MIPS_III).with_pseudo_bnezl(true),
            "bnel        $a0, $a1, . + 4 + (0x5 << 2)",
            Opcode::core_bnel,
            "bnel",
            [Some("$a0"), Some("$a1"), Some(". + 4 + (0x5 << 2)"), None, None],
        ),
        TestEntry::new(
            0x54800005,
            InstructionFlags::new(IsaVersion::MIPS_III).with_pseudo_bnezl(true),
            "bnezl       $a0, . + 4 + (0x5 << 2)",
            Opcode::core_bnezl,
            "bnezl",
            [Some("$a0"), Some(". + 4 + (0x5 << 2)"), None, None, None],
        ),
        TestEntry::new(
            0x54800005,
            InstructionFlags::new(IsaVersion::MIPS_III).with_pseudo_bnezl(false),
            "bnel        $a0, $zero, . + 4 + (0x5 << 2)",
            Opcode::core_bnel,
            "bnel",
            [Some("$a0"), Some("$zero"), Some(". + 4 + (0x5 << 2)"), None, None],
        ),

        // gnu_div

        TestEntry {
            instr: Instruction::new(
                0x0085001A,
                Vram::new(0x80000000),
                InstructionFlags::new(IsaVersion::MIPS_III),
            ),
            imm_override: None,
            display_flags: InstructionDisplayFlags::default().with_gnu_div(true),
            valid: true,
            expected: "div         $zero, $a0, $a1",
            expected_opcode: Opcode::core_div,
            opcode_str: "div",
            operands_str: [Some("$zero, $a0"), Some("$a1"), None, None, None],
            test_encoder: true,
        },
        TestEntry {
            instr: Instruction::new(
                0x0085001A,
                Vram::new(0x80000000),
                InstructionFlags::new(IsaVersion::MIPS_III),
            ),
            imm_override: None,
            display_flags: InstructionDisplayFlags::default().with_gnu_div(false),
            valid: true,
            expected: "div         $a0, $a1",
            expected_opcode: Opcode::core_div,
            opcode_str: "div",
            operands_str: [Some("$a0"), Some("$a1"), None, None, None],
            test_encoder: true,
        },
        TestEntry {
            instr: Instruction::new(
                0x0085001B,
                Vram::new(0x80000000),
                InstructionFlags::new(IsaVersion::MIPS_III),
            ),
            imm_override: None,
            display_flags: InstructionDisplayFlags::default().with_gnu_div(true),
            valid: true,
            expected: "divu        $zero, $a0, $a1",
            expected_opcode: Opcode::core_divu,
            opcode_str: "divu",
            operands_str: [Some("$zero, $a0"), Some("$a1"), None, None, None],
            test_encoder: true,
        },
        TestEntry {
            instr: Instruction::new(
                0x0085001B,
                Vram::new(0x80000000),
                InstructionFlags::new(IsaVersion::MIPS_III),
            ),
            imm_override: None,
            display_flags: InstructionDisplayFlags::default().with_gnu_div(false),
            valid: true,
            expected: "divu        $a0, $a1",
            expected_opcode: Opcode::core_divu,
            opcode_str: "divu",
            operands_str: [Some("$a0"), Some("$a1"), None, None, None],
            test_encoder: true,
        },
        TestEntry {
            instr: Instruction::new(
                0x0085001E,
                Vram::new(0x80000000),
                InstructionFlags::new(IsaVersion::MIPS_III),
            ),
            imm_override: None,
            display_flags: InstructionDisplayFlags::default().with_gnu_div(true),
            valid: true,
            expected: "ddiv        $zero, $a0, $a1",
            expected_opcode: Opcode::core_ddiv,
            opcode_str: "ddiv",
            operands_str: [Some("$zero, $a0"), Some("$a1"), None, None, None],
            test_encoder: true,
        },
        TestEntry {
            instr: Instruction::new(
                0x0085001E,
                Vram::new(0x80000000),
                InstructionFlags::new(IsaVersion::MIPS_III),
            ),
            imm_override: None,
            display_flags: InstructionDisplayFlags::default().with_gnu_div(false),
            valid: true,
            expected: "ddiv        $a0, $a1",
            expected_opcode: Opcode::core_ddiv,
            opcode_str: "ddiv",
            operands_str: [Some("$a0"), Some("$a1"), None, None, None],
            test_encoder: true,
        },
        TestEntry {
            instr: Instruction::new(
                0x0085001F,
                Vram::new(0x80000000),
                InstructionFlags::new(IsaVersion::MIPS_III),
            ),
            imm_override: None,
            display_flags: InstructionDisplayFlags::default().with_gnu_div(true),
            valid: true,
            expected: "ddivu       $zero, $a0, $a1",
            expected_opcode: Opcode::core_ddivu,
            opcode_str: "ddivu",
            operands_str: [Some("$zero, $a0"), Some("$a1"), None, None, None],
            test_encoder: true,
        },
        TestEntry {
            instr: Instruction::new(
                0x0085001F,
                Vram::new(0x80000000),
                InstructionFlags::new(IsaVersion::MIPS_III),
            ),
            imm_override: None,
            display_flags: InstructionDisplayFlags::default().with_gnu_div(false),
            valid: true,
            expected: "ddivu       $a0, $a1",
            expected_opcode: Opcode::core_ddivu,
            opcode_str: "ddivu",
            operands_str: [Some("$a0"), Some("$a1"), None, None, None],
            test_encoder: true,
        },
        TestEntry {
            instr: Instruction::new(
                0x46001008,
                Vram::new(0x80000000),
                InstructionFlags::new(IsaVersion::MIPS_III),
            ),
            imm_override: None,
            display_flags: InstructionDisplayFlags::default(),
            valid: true,
            expected: "round.l.s   $fv0, $fv1",
            expected_opcode: Opcode::core_round_l_s,
            opcode_str: "round.l.s",
            operands_str: [Some("$fv0"), Some("$fv1"), None, None, None],
            test_encoder: true,
        },
        TestEntry {
            instr: Instruction::new(
                0x46001009,
                Vram::new(0x80000000),
                InstructionFlags::new(IsaVersion::MIPS_III),
            ),
            imm_override: None,
            display_flags: InstructionDisplayFlags::default(),
            valid: true,
            expected: "trunc.l.s   $fv0, $fv1",
            expected_opcode: Opcode::core_trunc_l_s,
            opcode_str: "trunc.l.s",
            operands_str: [Some("$fv0"), Some("$fv1"), None, None, None],
            test_encoder: true,
        },
        TestEntry {
            instr: Instruction::new(
                0x4600100A,
                Vram::new(0x80000000),
                InstructionFlags::new(IsaVersion::MIPS_III),
            ),
            imm_override: None,
            display_flags: InstructionDisplayFlags::default(),
            valid: true,
            expected: "ceil.l.s    $fv0, $fv1",
            expected_opcode: Opcode::core_ceil_l_s,
            opcode_str: "ceil.l.s",
            operands_str: [Some("$fv0"), Some("$fv1"), None, None, None],
            test_encoder: true,
        },
        TestEntry {
            instr: Instruction::new(
                0x4600100B,
                Vram::new(0x80000000),
                InstructionFlags::new(IsaVersion::MIPS_III),
            ),
            imm_override: None,
            display_flags: InstructionDisplayFlags::default(),
            valid: true,
            expected: "floor.l.s   $fv0, $fv1",
            expected_opcode: Opcode::core_floor_l_s,
            opcode_str: "floor.l.s",
            operands_str: [Some("$fv0"), Some("$fv1"), None, None, None],
            test_encoder: true,
        },
        TestEntry {
            instr: Instruction::new(
                0x46001025,
                Vram::new(0x80000000),
                InstructionFlags::new(IsaVersion::MIPS_III),
            ),
            imm_override: None,
            display_flags: InstructionDisplayFlags::default(),
            valid: true,
            expected: "cvt.l.s     $fv0, $fv1",
            expected_opcode: Opcode::core_cvt_l_s,
            opcode_str: "cvt.l.s",
            operands_str: [Some("$fv0"), Some("$fv1"), None, None, None],
            test_encoder: true,
        },
        TestEntry {
            instr: Instruction::new(
                0x46201008,
                Vram::new(0x80000000),
                InstructionFlags::new(IsaVersion::MIPS_III),
            ),
            imm_override: None,
            display_flags: InstructionDisplayFlags::default(),
            valid: true,
            expected: "round.l.d   $fv0, $fv1",
            expected_opcode: Opcode::core_round_l_d,
            opcode_str: "round.l.d",
            operands_str: [Some("$fv0"), Some("$fv1"), None, None, None],
            test_encoder: true,
        },
        TestEntry {
            instr: Instruction::new(
                0x46201009,
                Vram::new(0x80000000),
                InstructionFlags::new(IsaVersion::MIPS_III),
            ),
            imm_override: None,
            display_flags: InstructionDisplayFlags::default(),
            valid: true,
            expected: "trunc.l.d   $fv0, $fv1",
            expected_opcode: Opcode::core_trunc_l_d,
            opcode_str: "trunc.l.d",
            operands_str: [Some("$fv0"), Some("$fv1"), None, None, None],
            test_encoder: true,
        },
        TestEntry {
            instr: Instruction::new(
                0x4620100A,
                Vram::new(0x80000000),
                InstructionFlags::new(IsaVersion::MIPS_III),
            ),
            imm_override: None,
            display_flags: InstructionDisplayFlags::default(),
            valid: true,
            expected: "ceil.l.d    $fv0, $fv1",
            expected_opcode: Opcode::core_ceil_l_d,
            opcode_str: "ceil.l.d",
            operands_str: [Some("$fv0"), Some("$fv1"), None, None, None],
            test_encoder: true,
        },
        TestEntry {
            instr: Instruction::new(
                0x4620100B,
                Vram::new(0x80000000),
                InstructionFlags::new(IsaVersion::MIPS_III),
            ),
            imm_override: None,
            display_flags: InstructionDisplayFlags::default(),
            valid: true,
            expected: "floor.l.d   $fv0, $fv1",
            expected_opcode: Opcode::core_floor_l_d,
            opcode_str: "floor.l.d",
            operands_str: [Some("$fv0"), Some("$fv1"), None, None, None],
            test_encoder: true,
        },
        TestEntry {
            instr: Instruction::new(
                0x46201025,
                Vram::new(0x80000000),
                InstructionFlags::new(IsaVersion::MIPS_III),
            ),
            imm_override: None,
            display_flags: InstructionDisplayFlags::default(),
            valid: true,
            expected: "cvt.l.d     $fv0, $fv1",
            expected_opcode: Opcode::core_cvt_l_d,
            opcode_str: "cvt.l.d",
            operands_str: [Some("$fv0"), Some("$fv1"), None, None, None],
            test_encoder: true,
        },
        TestEntry {
            instr: Instruction::new(
                0x46A01020,
                Vram::new(0x80000000),
                InstructionFlags::new(IsaVersion::MIPS_III),
            ),
            imm_override: None,
            display_flags: InstructionDisplayFlags::default(),
            valid: true,
            expected: "cvt.s.l     $fv0, $fv1",
            expected_opcode: Opcode::core_cvt_s_l,
            opcode_str: "cvt.s.l",
            operands_str: [Some("$fv0"), Some("$fv1"), None, None, None],
            test_encoder: true,
        },
        TestEntry {
            instr: Instruction::new(
                0x46A01021,
                Vram::new(0x80000000),
                InstructionFlags::new(IsaVersion::MIPS_III),
            ),
            imm_override: None,
            display_flags: InstructionDisplayFlags::default(),
            valid: true,
            expected: "cvt.d.l     $fv0, $fv1",
            expected_opcode: Opcode::core_cvt_d_l,
            opcode_str: "cvt.d.l",
            operands_str: [Some("$fv0"), Some("$fv1"), None, None, None],
            test_encoder: true,
        },
    ];

    assert_eq!(check_test_entries(ENTRIES), (0, 0));
}

#[cfg(feature = "MIPS_IV")]
#[test]
fn check_none_instructions_mips_4() {
    static ENTRIES: &[TestEntry] = &[TestEntry::new(
        0xCD150008,
        InstructionFlags::new(IsaVersion::MIPS_IV),
        "pref        0x15, 0x8($t0)",
        Opcode::core_pref,
        "pref",
        [Some("0x15"), Some("0x8($t0)"), None, None, None],
    )];

    assert_eq!(check_test_entries(ENTRIES), (0, 0));
}

#[cfg(feature = "MIPS_III")]
#[test]
fn check_none_instructions_invalid() {
    static ENTRIES: &[TestEntry] = &[
        TestEntry::new_semi_invalid(0x44444444, InstructionFlags::new(IsaVersion::MIPS_III), ".word       0x44444444                   /* cfc1        $a0, $8 / 00000444 <OpcodeCategory: CORE_COP1> */", Opcode::core_cfc1, "cfc1", [Some("$a0"), Some("$8"), None, None, None]),
        TestEntry::new_full_invalid(0x77777777, InstructionFlags::new(IsaVersion::MIPS_III), ".word       0x77777777                   /* INVALID / 03777777 <OpcodeCategory: CORE_NORMAL> */"),
        TestEntry::new_full_invalid(0xEEEEEEEE, InstructionFlags::new(IsaVersion::MIPS_III), ".word       0xEEEEEEEE                   /* INVALID / 02EEEEEE <OpcodeCategory: CORE_NORMAL> */"),
    ];

    assert_eq!(check_test_entries(ENTRIES), (0, 0));
}
