/* Generated by rlvgl-creator from chipdb/rlvgl-chips-esp/db/chips/{{ chip_stem }}.yaml.
 *
 * MEMORY block for {{ ir.chip.name }} ({{ ir.chip.arch }}). Each region
 * comes from the chip yaml's `memory:` array and is sized by the TRM
 * cited there. The REGION_ALIAS lines map the chip's regions onto the
 * generic names that riscv-rt's link.x consumes (REGION_TEXT, REGION_DATA,
 * etc.) — the alias targets come from the chip yaml's `linker:` section.
 */

MEMORY
{
{%- for r in ir.chip.memory %}
  {{ r.name|upper }} : ORIGIN = {{ r.base|hex32 }}, LENGTH = {{ r.size|hex32 }}    /* {{ r.access }} */
{%- endfor %}
}

/* Aliases consumed by riscv-rt's link.x. */
REGION_ALIAS("REGION_TEXT",   {{ ir.chip.linker.region_text|upper }});
REGION_ALIAS("REGION_RODATA", {{ ir.chip.linker.region_text|upper }});
REGION_ALIAS("REGION_DATA",   {{ ir.chip.linker.region_data|upper }});
REGION_ALIAS("REGION_BSS",    {{ ir.chip.linker.region_data|upper }});
REGION_ALIAS("REGION_HEAP",   {{ ir.chip.linker.region_data|upper }});
REGION_ALIAS("REGION_STACK",  {{ ir.chip.linker.region_data|upper }});
