/* Generated by rlvgl-creator from chipdb/rlvgl-chips-ti/db/chips/{{ chip_stem }}.yaml.
 *
 * MEMORY block for {{ ir.chip.name }} ({{ ir.chip.arch }}). Each region
 * comes from the chip yaml's `memory:` array; sizes are sourced from the
 * TI TRM cited in that yaml (SWCU185 §1.5 Memory Map for the CC13x2 /
 * CC26x2 family).
 *
 * The REGION_ALIAS lines map the chip's regions onto the names that
 * cortex-m-rt's `link.x` consumes (FLASH / RAM are the canonical names;
 * the REGION_TEXT / REGION_DATA / REGION_RODATA aliases are accepted by
 * recent cortex-m-rt link scripts and are harmless on older versions).
 * The alias targets come from the chip yaml's `linker:` section.
 */

MEMORY
{
{%- for r in ir.chip.memory %}
  {{ r.name|upper }} : ORIGIN = {{ r.base|hex32 }}, LENGTH = {{ r.size|hex32 }}    /* {{ r.access }} */
{%- endfor %}
}

/* Canonical cortex-m-rt names. */
REGION_ALIAS("FLASH", {{ ir.chip.linker.region_text|upper }});
REGION_ALIAS("RAM",   {{ ir.chip.linker.region_data|upper }});

/* Optional aliases consumed by newer link.x scripts; harmless if unused. */
REGION_ALIAS("REGION_TEXT",   {{ ir.chip.linker.region_text|upper }});
REGION_ALIAS("REGION_RODATA", {{ ir.chip.linker.region_text|upper }});
REGION_ALIAS("REGION_DATA",   {{ ir.chip.linker.region_data|upper }});
REGION_ALIAS("REGION_BSS",    {{ ir.chip.linker.region_data|upper }});
REGION_ALIAS("REGION_HEAP",   {{ ir.chip.linker.region_data|upper }});
REGION_ALIAS("REGION_STACK",  {{ ir.chip.linker.region_data|upper }});
