//! Clock initialization for {{ ir.chip.name }}.
//!
//! Generated by rlvgl-creator BSP generator.
//!
//! Target frequencies:
//!   clk_sys:  {{ ir.clocks.sys_hz }} Hz
//!   clk_ref:  {{ ir.clocks.ref_hz }} Hz
//!   clk_peri: {{ ir.clocks.peri_hz }} Hz
//!   clk_usb:  {{ ir.clocks.usb_hz }} Hz
//!   XOSC:     {{ ir.clocks.xosc_hz }} Hz

#![allow(unused)]

use super::pac;

/// Initialize the clock tree.
///
/// Configures XOSC, PLL_SYS, PLL_USB, and derived clock domains.
pub unsafe fn init_clocks() {
    // TODO: XOSC startup
    // TODO: PLL_SYS configuration
{%- for pll in ir.chip.clock_tree.plls %}
    // {{ pll.name }}: ref_div={{ pll.ref_div }}, vco={{ pll.vco_freq_hz }} Hz,
    //   post_div1={{ pll.post_div1 }}, post_div2={{ pll.post_div2 }}
{%- endfor %}
    // TODO: Switch clk_sys to PLL output
    // TODO: Configure clk_peri, clk_usb, clk_adc, clk_rtc
}
