/* Generated by rlvgl-creator from
 * chipdb/rlvgl-chips-microchip/db/chips/{{ ir.chip.name }}.yaml.
 *
 * Linker supplement for {{ ir.chip.name }} ({{ ir.chip.arch }}). Reserves a
 * slot for chip-specific section directives beyond the cortex-m-rt
 * default `link.x` and beyond the `atsamd51j19a` PAC crate's
 * auto-generated `device.x` (emitted by its `build.rs` into `OUT_DIR`,
 * INCLUDEd by cortex-m-rt's `link.x`; authoritative for NVIC vector
 * extensions).
 *
 * Per CHIPS-MICROCHIP-05 §5.3, ATSAMD51J19A v0 has no generator-emitted
 * chip-specific section directives — NVMCTRL fuse rows, SmartEEPROM
 * emulation regions, QSPI XIP layout, and `BOOTPROT` carve-outs are all
 * out of v0 scope (CHIPS-MICROCHIP-05 §9). The slot exists so that:
 *
 *   1. Future D5x / D21 / L21 chips whose section needs are non-trivial
 *      (boot-loader header `.app_header` blocks, multi-image
 *      `mcuboot`-style splits, alternate `.peripherals_init` placement)
 *      populate this template via a CHIPS-MICROCHIP-NN walkthrough
 *      rather than racing the emission shape through a Standards Action
 *      amendment.
 *   2. Consuming crates can write a stable `-T{{ chip_link_stem }}.x`
 *      line in their `build.rs` today, even though the file body is
 *      empty. When a future amendment populates the slot, the consumer
 *      build picks it up without a `build.rs` change.
 *
 * Consumed via the example crate's build.rs as
 * `-T{{ chip_link_stem }}.x`, sequenced after `-Tmemory.x` and before
 * `-Tlink.x` so FLASH / RAM are defined when this file is parsed (per
 * CHIPS-MICROCHIP-05 §5.5).
 *
 * Authority for the slot rationale: CHIPS-MICROCHIP-05 §5.3, §9, §10.2.
 */

/* No chip-specific section directives in v0 — see header comment.
 * Adding non-empty content here is Specification Required per
 * CHIPS-MICROCHIP-05 §5.3 (walkthrough updates this template and
 * re-blesses the `{{ chip_link_stem }}_x.snap` snapshot in the same PR).
 */
