//! CCM clock gating for {{ ir.board.name }}.
//!
//! Ungates the CCGR fields for each peripheral used by the board.
//! XTAL: {{ ir.clocks.xtal_hz }} Hz, CPU: {{ ir.clocks.cpu_hz }} Hz,
//! AHB: {{ ir.clocks.ahb_hz }} Hz, IPG: {{ ir.clocks.ipg_hz }} Hz.

/// XTAL frequency in Hz.
pub const XTAL_HZ: u32 = {{ ir.clocks.xtal_hz }};

/// CPU core clock in Hz.
pub const CPU_HZ: u32 = {{ ir.clocks.cpu_hz }};

/// AHB bus clock in Hz.
pub const AHB_HZ: u32 = {{ ir.clocks.ahb_hz }};

/// IPG bus clock in Hz.
pub const IPG_HZ: u32 = {{ ir.clocks.ipg_hz }};

/// Ungate all peripheral clocks used by this board.
pub fn init() {
    // IOMUXC clock gate (required before pad configuration).
    {% if ir.chip.clock_tree.ccgr_gates.iomuxc is defined %}
    // IOMUXC — CCGR{{ ir.chip.clock_tree.ccgr_gates.iomuxc.ccgr }}[CG{{ ir.chip.clock_tree.ccgr_gates.iomuxc.field }}]
    unsafe {
        let ccgr = (0x400FC068u32 + 4 * {{ ir.chip.clock_tree.ccgr_gates.iomuxc.ccgr }}) as *mut u32;
        let val = core::ptr::read_volatile(ccgr);
        core::ptr::write_volatile(ccgr, val | (0b11 << (2 * {{ ir.chip.clock_tree.ccgr_gates.iomuxc.field }})));
    }
    {% endif %}

    {% for name in peripherals_used %}
    {% if ir.chip.clock_tree.ccgr_gates[name] is defined %}
    // {{ name }} — CCGR{{ ir.chip.clock_tree.ccgr_gates[name].ccgr }}[CG{{ ir.chip.clock_tree.ccgr_gates[name].field }}]
    unsafe {
        let ccgr = (0x400FC068u32 + 4 * {{ ir.chip.clock_tree.ccgr_gates[name].ccgr }}) as *mut u32;
        let val = core::ptr::read_volatile(ccgr);
        core::ptr::write_volatile(ccgr, val | (0b11 << (2 * {{ ir.chip.clock_tree.ccgr_gates[name].field }})));
    }
    {% endif %}
    {% endfor %}
}
