/* Generated by rlvgl-creator from chipdb/rlvgl-chips-silabs/db/chips/{{ chip_stem }}.yaml.
 *
 * Linker supplement for {{ ir.chip.name }} ({{ ir.chip.arch }}). Reserved
 * for chip-specific section directives beyond the cortex-m-rt default.
 *
 * At CHIPS-SILABS-05 v0 this file carries no SECTIONS block: EFM32GG11
 * (Series 1) has no SiLabs equivalent of the SimpleLink-family CCFG
 * region — the boot ROM does not consume a fixed-address customer
 * configuration block. The file is emitted alongside `memory.x` to
 * keep the SILABS file-emission set symmetrical with the TI and
 * Microchip generators (§5.1 of CHIPS-SILABS-05), and to provide a
 * forward-compatible hook for future amendments (e.g. relocating the
 * user-data page into its own KEEP(*(.userdata)) section).
 *
 * Consumed via the example crate's build.rs as `-T{{ chip_stem }}.x`,
 * sequenced after `-Tmemory.x` and before `-Tlink.x` so FLASH is
 * defined when this file is parsed.
 *
 * NON-GOALS at v0 (per CHIPS-SILABS-05 §11):
 *   - AAP / DCI / UD region content (consumer-defined).
 *   - XIP from external flash via EBI.
 *   - DMA buffer placement sections.
 *   - .vector_table customisation (owned by cortex-m-rt).
 */
